1 /* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #ifndef TCG_H 26 #define TCG_H 27 28 #include "cpu.h" 29 #include "exec/memop.h" 30 #include "exec/memopidx.h" 31 #include "qemu/bitops.h" 32 #include "qemu/plugin.h" 33 #include "qemu/queue.h" 34 #include "tcg/tcg-mo.h" 35 #include "tcg-target.h" 36 #include "tcg/tcg-cond.h" 37 38 /* XXX: make safe guess about sizes */ 39 #define MAX_OP_PER_INSTR 266 40 41 #define MAX_CALL_IARGS 7 42 43 #define CPU_TEMP_BUF_NLONGS 128 44 #define TCG_STATIC_FRAME_SIZE (CPU_TEMP_BUF_NLONGS * sizeof(long)) 45 46 /* Default target word size to pointer size. */ 47 #ifndef TCG_TARGET_REG_BITS 48 # if UINTPTR_MAX == UINT32_MAX 49 # define TCG_TARGET_REG_BITS 32 50 # elif UINTPTR_MAX == UINT64_MAX 51 # define TCG_TARGET_REG_BITS 64 52 # else 53 # error Unknown pointer size for tcg target 54 # endif 55 #endif 56 57 #if TCG_TARGET_REG_BITS == 32 58 typedef int32_t tcg_target_long; 59 typedef uint32_t tcg_target_ulong; 60 #define TCG_PRIlx PRIx32 61 #define TCG_PRIld PRId32 62 #elif TCG_TARGET_REG_BITS == 64 63 typedef int64_t tcg_target_long; 64 typedef uint64_t tcg_target_ulong; 65 #define TCG_PRIlx PRIx64 66 #define TCG_PRIld PRId64 67 #else 68 #error unsupported 69 #endif 70 71 /* Oversized TCG guests make things like MTTCG hard 72 * as we can't use atomics for cputlb updates. 73 */ 74 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS 75 #define TCG_OVERSIZED_GUEST 1 76 #else 77 #define TCG_OVERSIZED_GUEST 0 78 #endif 79 80 #if TCG_TARGET_NB_REGS <= 32 81 typedef uint32_t TCGRegSet; 82 #elif TCG_TARGET_NB_REGS <= 64 83 typedef uint64_t TCGRegSet; 84 #else 85 #error unsupported 86 #endif 87 88 #if TCG_TARGET_REG_BITS == 32 89 /* Turn some undef macros into false macros. */ 90 #define TCG_TARGET_HAS_extrl_i64_i32 0 91 #define TCG_TARGET_HAS_extrh_i64_i32 0 92 #define TCG_TARGET_HAS_div_i64 0 93 #define TCG_TARGET_HAS_rem_i64 0 94 #define TCG_TARGET_HAS_div2_i64 0 95 #define TCG_TARGET_HAS_rot_i64 0 96 #define TCG_TARGET_HAS_ext8s_i64 0 97 #define TCG_TARGET_HAS_ext16s_i64 0 98 #define TCG_TARGET_HAS_ext32s_i64 0 99 #define TCG_TARGET_HAS_ext8u_i64 0 100 #define TCG_TARGET_HAS_ext16u_i64 0 101 #define TCG_TARGET_HAS_ext32u_i64 0 102 #define TCG_TARGET_HAS_bswap16_i64 0 103 #define TCG_TARGET_HAS_bswap32_i64 0 104 #define TCG_TARGET_HAS_bswap64_i64 0 105 #define TCG_TARGET_HAS_neg_i64 0 106 #define TCG_TARGET_HAS_not_i64 0 107 #define TCG_TARGET_HAS_andc_i64 0 108 #define TCG_TARGET_HAS_orc_i64 0 109 #define TCG_TARGET_HAS_eqv_i64 0 110 #define TCG_TARGET_HAS_nand_i64 0 111 #define TCG_TARGET_HAS_nor_i64 0 112 #define TCG_TARGET_HAS_clz_i64 0 113 #define TCG_TARGET_HAS_ctz_i64 0 114 #define TCG_TARGET_HAS_ctpop_i64 0 115 #define TCG_TARGET_HAS_deposit_i64 0 116 #define TCG_TARGET_HAS_extract_i64 0 117 #define TCG_TARGET_HAS_sextract_i64 0 118 #define TCG_TARGET_HAS_extract2_i64 0 119 #define TCG_TARGET_HAS_movcond_i64 0 120 #define TCG_TARGET_HAS_add2_i64 0 121 #define TCG_TARGET_HAS_sub2_i64 0 122 #define TCG_TARGET_HAS_mulu2_i64 0 123 #define TCG_TARGET_HAS_muls2_i64 0 124 #define TCG_TARGET_HAS_muluh_i64 0 125 #define TCG_TARGET_HAS_mulsh_i64 0 126 /* Turn some undef macros into true macros. */ 127 #define TCG_TARGET_HAS_add2_i32 1 128 #define TCG_TARGET_HAS_sub2_i32 1 129 #endif 130 131 #ifndef TCG_TARGET_deposit_i32_valid 132 #define TCG_TARGET_deposit_i32_valid(ofs, len) 1 133 #endif 134 #ifndef TCG_TARGET_deposit_i64_valid 135 #define TCG_TARGET_deposit_i64_valid(ofs, len) 1 136 #endif 137 #ifndef TCG_TARGET_extract_i32_valid 138 #define TCG_TARGET_extract_i32_valid(ofs, len) 1 139 #endif 140 #ifndef TCG_TARGET_extract_i64_valid 141 #define TCG_TARGET_extract_i64_valid(ofs, len) 1 142 #endif 143 144 /* Only one of DIV or DIV2 should be defined. */ 145 #if defined(TCG_TARGET_HAS_div_i32) 146 #define TCG_TARGET_HAS_div2_i32 0 147 #elif defined(TCG_TARGET_HAS_div2_i32) 148 #define TCG_TARGET_HAS_div_i32 0 149 #define TCG_TARGET_HAS_rem_i32 0 150 #endif 151 #if defined(TCG_TARGET_HAS_div_i64) 152 #define TCG_TARGET_HAS_div2_i64 0 153 #elif defined(TCG_TARGET_HAS_div2_i64) 154 #define TCG_TARGET_HAS_div_i64 0 155 #define TCG_TARGET_HAS_rem_i64 0 156 #endif 157 158 /* For 32-bit targets, some sort of unsigned widening multiply is required. */ 159 #if TCG_TARGET_REG_BITS == 32 \ 160 && !(defined(TCG_TARGET_HAS_mulu2_i32) \ 161 || defined(TCG_TARGET_HAS_muluh_i32)) 162 # error "Missing unsigned widening multiply" 163 #endif 164 165 #if !defined(TCG_TARGET_HAS_v64) \ 166 && !defined(TCG_TARGET_HAS_v128) \ 167 && !defined(TCG_TARGET_HAS_v256) 168 #define TCG_TARGET_MAYBE_vec 0 169 #define TCG_TARGET_HAS_abs_vec 0 170 #define TCG_TARGET_HAS_neg_vec 0 171 #define TCG_TARGET_HAS_not_vec 0 172 #define TCG_TARGET_HAS_andc_vec 0 173 #define TCG_TARGET_HAS_orc_vec 0 174 #define TCG_TARGET_HAS_nand_vec 0 175 #define TCG_TARGET_HAS_nor_vec 0 176 #define TCG_TARGET_HAS_eqv_vec 0 177 #define TCG_TARGET_HAS_roti_vec 0 178 #define TCG_TARGET_HAS_rots_vec 0 179 #define TCG_TARGET_HAS_rotv_vec 0 180 #define TCG_TARGET_HAS_shi_vec 0 181 #define TCG_TARGET_HAS_shs_vec 0 182 #define TCG_TARGET_HAS_shv_vec 0 183 #define TCG_TARGET_HAS_mul_vec 0 184 #define TCG_TARGET_HAS_sat_vec 0 185 #define TCG_TARGET_HAS_minmax_vec 0 186 #define TCG_TARGET_HAS_bitsel_vec 0 187 #define TCG_TARGET_HAS_cmpsel_vec 0 188 #else 189 #define TCG_TARGET_MAYBE_vec 1 190 #endif 191 #ifndef TCG_TARGET_HAS_v64 192 #define TCG_TARGET_HAS_v64 0 193 #endif 194 #ifndef TCG_TARGET_HAS_v128 195 #define TCG_TARGET_HAS_v128 0 196 #endif 197 #ifndef TCG_TARGET_HAS_v256 198 #define TCG_TARGET_HAS_v256 0 199 #endif 200 201 #ifndef TARGET_INSN_START_EXTRA_WORDS 202 # define TARGET_INSN_START_WORDS 1 203 #else 204 # define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS) 205 #endif 206 207 typedef enum TCGOpcode { 208 #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name, 209 #include "tcg/tcg-opc.h" 210 #undef DEF 211 NB_OPS, 212 } TCGOpcode; 213 214 #define tcg_regset_set_reg(d, r) ((d) |= (TCGRegSet)1 << (r)) 215 #define tcg_regset_reset_reg(d, r) ((d) &= ~((TCGRegSet)1 << (r))) 216 #define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1) 217 218 #ifndef TCG_TARGET_INSN_UNIT_SIZE 219 # error "Missing TCG_TARGET_INSN_UNIT_SIZE" 220 #elif TCG_TARGET_INSN_UNIT_SIZE == 1 221 typedef uint8_t tcg_insn_unit; 222 #elif TCG_TARGET_INSN_UNIT_SIZE == 2 223 typedef uint16_t tcg_insn_unit; 224 #elif TCG_TARGET_INSN_UNIT_SIZE == 4 225 typedef uint32_t tcg_insn_unit; 226 #elif TCG_TARGET_INSN_UNIT_SIZE == 8 227 typedef uint64_t tcg_insn_unit; 228 #else 229 /* The port better have done this. */ 230 #endif 231 232 233 #if defined CONFIG_DEBUG_TCG || defined QEMU_STATIC_ANALYSIS 234 # define tcg_debug_assert(X) do { assert(X); } while (0) 235 #else 236 # define tcg_debug_assert(X) \ 237 do { if (!(X)) { __builtin_unreachable(); } } while (0) 238 #endif 239 240 typedef struct TCGRelocation TCGRelocation; 241 struct TCGRelocation { 242 QSIMPLEQ_ENTRY(TCGRelocation) next; 243 tcg_insn_unit *ptr; 244 intptr_t addend; 245 int type; 246 }; 247 248 typedef struct TCGLabel TCGLabel; 249 struct TCGLabel { 250 unsigned present : 1; 251 unsigned has_value : 1; 252 unsigned id : 14; 253 unsigned refs : 16; 254 union { 255 uintptr_t value; 256 const tcg_insn_unit *value_ptr; 257 } u; 258 QSIMPLEQ_HEAD(, TCGRelocation) relocs; 259 QSIMPLEQ_ENTRY(TCGLabel) next; 260 }; 261 262 typedef struct TCGPool { 263 struct TCGPool *next; 264 int size; 265 uint8_t data[] __attribute__ ((aligned)); 266 } TCGPool; 267 268 #define TCG_POOL_CHUNK_SIZE 32768 269 270 #define TCG_MAX_TEMPS 512 271 #define TCG_MAX_INSNS 512 272 273 /* when the size of the arguments of a called function is smaller than 274 this value, they are statically allocated in the TB stack frame */ 275 #define TCG_STATIC_CALL_ARGS_SIZE 128 276 277 typedef enum TCGType { 278 TCG_TYPE_I32, 279 TCG_TYPE_I64, 280 281 TCG_TYPE_V64, 282 TCG_TYPE_V128, 283 TCG_TYPE_V256, 284 285 /* Number of different types (integer not enum) */ 286 #define TCG_TYPE_COUNT (TCG_TYPE_V256 + 1) 287 288 /* An alias for the size of the host register. */ 289 #if TCG_TARGET_REG_BITS == 32 290 TCG_TYPE_REG = TCG_TYPE_I32, 291 #else 292 TCG_TYPE_REG = TCG_TYPE_I64, 293 #endif 294 295 /* An alias for the size of the native pointer. */ 296 #if UINTPTR_MAX == UINT32_MAX 297 TCG_TYPE_PTR = TCG_TYPE_I32, 298 #else 299 TCG_TYPE_PTR = TCG_TYPE_I64, 300 #endif 301 302 /* An alias for the size of the target "long", aka register. */ 303 #if TARGET_LONG_BITS == 64 304 TCG_TYPE_TL = TCG_TYPE_I64, 305 #else 306 TCG_TYPE_TL = TCG_TYPE_I32, 307 #endif 308 } TCGType; 309 310 /** 311 * tcg_type_size 312 * @t: type 313 * 314 * Return the size of the type in bytes. 315 */ 316 static inline int tcg_type_size(TCGType t) 317 { 318 unsigned i = t; 319 if (i >= TCG_TYPE_V64) { 320 tcg_debug_assert(i < TCG_TYPE_COUNT); 321 i -= TCG_TYPE_V64 - 1; 322 } 323 return 4 << i; 324 } 325 326 /** 327 * get_alignment_bits 328 * @memop: MemOp value 329 * 330 * Extract the alignment size from the memop. 331 */ 332 static inline unsigned get_alignment_bits(MemOp memop) 333 { 334 unsigned a = memop & MO_AMASK; 335 336 if (a == MO_UNALN) { 337 /* No alignment required. */ 338 a = 0; 339 } else if (a == MO_ALIGN) { 340 /* A natural alignment requirement. */ 341 a = memop & MO_SIZE; 342 } else { 343 /* A specific alignment requirement. */ 344 a = a >> MO_ASHIFT; 345 } 346 #if defined(CONFIG_SOFTMMU) 347 /* The requested alignment cannot overlap the TLB flags. */ 348 tcg_debug_assert((TLB_FLAGS_MASK & ((1 << a) - 1)) == 0); 349 #endif 350 return a; 351 } 352 353 typedef tcg_target_ulong TCGArg; 354 355 /* Define type and accessor macros for TCG variables. 356 357 TCG variables are the inputs and outputs of TCG ops, as described 358 in tcg/README. Target CPU front-end code uses these types to deal 359 with TCG variables as it emits TCG code via the tcg_gen_* functions. 360 They come in several flavours: 361 * TCGv_i32 : 32 bit integer type 362 * TCGv_i64 : 64 bit integer type 363 * TCGv_ptr : a host pointer type 364 * TCGv_vec : a host vector type; the exact size is not exposed 365 to the CPU front-end code. 366 * TCGv : an integer type the same size as target_ulong 367 (an alias for either TCGv_i32 or TCGv_i64) 368 The compiler's type checking will complain if you mix them 369 up and pass the wrong sized TCGv to a function. 370 371 Users of tcg_gen_* don't need to know about any of the internal 372 details of these, and should treat them as opaque types. 373 You won't be able to look inside them in a debugger either. 374 375 Internal implementation details follow: 376 377 Note that there is no definition of the structs TCGv_i32_d etc anywhere. 378 This is deliberate, because the values we store in variables of type 379 TCGv_i32 are not really pointers-to-structures. They're just small 380 integers, but keeping them in pointer types like this means that the 381 compiler will complain if you accidentally pass a TCGv_i32 to a 382 function which takes a TCGv_i64, and so on. Only the internals of 383 TCG need to care about the actual contents of the types. */ 384 385 typedef struct TCGv_i32_d *TCGv_i32; 386 typedef struct TCGv_i64_d *TCGv_i64; 387 typedef struct TCGv_ptr_d *TCGv_ptr; 388 typedef struct TCGv_vec_d *TCGv_vec; 389 typedef TCGv_ptr TCGv_env; 390 #if TARGET_LONG_BITS == 32 391 #define TCGv TCGv_i32 392 #elif TARGET_LONG_BITS == 64 393 #define TCGv TCGv_i64 394 #else 395 #error Unhandled TARGET_LONG_BITS value 396 #endif 397 398 /* call flags */ 399 /* Helper does not read globals (either directly or through an exception). It 400 implies TCG_CALL_NO_WRITE_GLOBALS. */ 401 #define TCG_CALL_NO_READ_GLOBALS 0x0001 402 /* Helper does not write globals */ 403 #define TCG_CALL_NO_WRITE_GLOBALS 0x0002 404 /* Helper can be safely suppressed if the return value is not used. */ 405 #define TCG_CALL_NO_SIDE_EFFECTS 0x0004 406 /* Helper is G_NORETURN. */ 407 #define TCG_CALL_NO_RETURN 0x0008 408 409 /* convenience version of most used call flags */ 410 #define TCG_CALL_NO_RWG TCG_CALL_NO_READ_GLOBALS 411 #define TCG_CALL_NO_WG TCG_CALL_NO_WRITE_GLOBALS 412 #define TCG_CALL_NO_SE TCG_CALL_NO_SIDE_EFFECTS 413 #define TCG_CALL_NO_RWG_SE (TCG_CALL_NO_RWG | TCG_CALL_NO_SE) 414 #define TCG_CALL_NO_WG_SE (TCG_CALL_NO_WG | TCG_CALL_NO_SE) 415 416 /* 417 * Flags for the bswap opcodes. 418 * If IZ, the input is zero-extended, otherwise unknown. 419 * If OZ or OS, the output is zero- or sign-extended respectively, 420 * otherwise the high bits are undefined. 421 */ 422 enum { 423 TCG_BSWAP_IZ = 1, 424 TCG_BSWAP_OZ = 2, 425 TCG_BSWAP_OS = 4, 426 }; 427 428 typedef enum TCGTempVal { 429 TEMP_VAL_DEAD, 430 TEMP_VAL_REG, 431 TEMP_VAL_MEM, 432 TEMP_VAL_CONST, 433 } TCGTempVal; 434 435 typedef enum TCGTempKind { 436 /* Temp is dead at the end of all basic blocks. */ 437 TEMP_NORMAL, 438 /* Temp is live across conditional branch, but dead otherwise. */ 439 TEMP_EBB, 440 /* Temp is saved across basic blocks but dead at the end of TBs. */ 441 TEMP_LOCAL, 442 /* Temp is saved across both basic blocks and translation blocks. */ 443 TEMP_GLOBAL, 444 /* Temp is in a fixed register. */ 445 TEMP_FIXED, 446 /* Temp is a fixed constant. */ 447 TEMP_CONST, 448 } TCGTempKind; 449 450 typedef struct TCGTemp { 451 TCGReg reg:8; 452 TCGTempVal val_type:8; 453 TCGType base_type:8; 454 TCGType type:8; 455 TCGTempKind kind:3; 456 unsigned int indirect_reg:1; 457 unsigned int indirect_base:1; 458 unsigned int mem_coherent:1; 459 unsigned int mem_allocated:1; 460 unsigned int temp_allocated:1; 461 unsigned int temp_subindex:1; 462 463 int64_t val; 464 struct TCGTemp *mem_base; 465 intptr_t mem_offset; 466 const char *name; 467 468 /* Pass-specific information that can be stored for a temporary. 469 One word worth of integer data, and one pointer to data 470 allocated separately. */ 471 uintptr_t state; 472 void *state_ptr; 473 } TCGTemp; 474 475 typedef struct TCGContext TCGContext; 476 477 typedef struct TCGTempSet { 478 unsigned long l[BITS_TO_LONGS(TCG_MAX_TEMPS)]; 479 } TCGTempSet; 480 481 /* 482 * With 1 128-bit output, a 32-bit host requires 4 output parameters, 483 * which leaves a maximum of 28 other slots. Which is enough for 7 484 * 128-bit operands. 485 */ 486 #define DEAD_ARG (1 << 4) 487 #define SYNC_ARG (1 << 0) 488 typedef uint32_t TCGLifeData; 489 490 typedef struct TCGOp { 491 TCGOpcode opc : 8; 492 unsigned nargs : 8; 493 494 /* Parameters for this opcode. See below. */ 495 unsigned param1 : 8; 496 unsigned param2 : 8; 497 498 /* Lifetime data of the operands. */ 499 TCGLifeData life; 500 501 /* Next and previous opcodes. */ 502 QTAILQ_ENTRY(TCGOp) link; 503 504 /* Register preferences for the output(s). */ 505 TCGRegSet output_pref[2]; 506 507 /* Arguments for the opcode. */ 508 TCGArg args[]; 509 } TCGOp; 510 511 #define TCGOP_CALLI(X) (X)->param1 512 #define TCGOP_CALLO(X) (X)->param2 513 514 #define TCGOP_VECL(X) (X)->param1 515 #define TCGOP_VECE(X) (X)->param2 516 517 /* Make sure operands fit in the bitfields above. */ 518 QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8)); 519 520 static inline TCGRegSet output_pref(const TCGOp *op, unsigned i) 521 { 522 return i < ARRAY_SIZE(op->output_pref) ? op->output_pref[i] : 0; 523 } 524 525 typedef struct TCGProfile { 526 int64_t cpu_exec_time; 527 int64_t tb_count1; 528 int64_t tb_count; 529 int64_t op_count; /* total insn count */ 530 int op_count_max; /* max insn per TB */ 531 int temp_count_max; 532 int64_t temp_count; 533 int64_t del_op_count; 534 int64_t code_in_len; 535 int64_t code_out_len; 536 int64_t search_out_len; 537 int64_t interm_time; 538 int64_t code_time; 539 int64_t la_time; 540 int64_t opt_time; 541 int64_t restore_count; 542 int64_t restore_time; 543 int64_t table_op_count[NB_OPS]; 544 } TCGProfile; 545 546 struct TCGContext { 547 uint8_t *pool_cur, *pool_end; 548 TCGPool *pool_first, *pool_current, *pool_first_large; 549 int nb_labels; 550 int nb_globals; 551 int nb_temps; 552 int nb_indirects; 553 int nb_ops; 554 555 TCGRegSet reserved_regs; 556 intptr_t current_frame_offset; 557 intptr_t frame_start; 558 intptr_t frame_end; 559 TCGTemp *frame_temp; 560 561 TranslationBlock *gen_tb; /* tb for which code is being generated */ 562 tcg_insn_unit *code_buf; /* pointer for start of tb */ 563 tcg_insn_unit *code_ptr; /* pointer for running end of tb */ 564 565 #ifdef CONFIG_PROFILER 566 TCGProfile prof; 567 #endif 568 569 #ifdef CONFIG_DEBUG_TCG 570 int temps_in_use; 571 int goto_tb_issue_mask; 572 const TCGOpcode *vecop_list; 573 #endif 574 575 /* Code generation. Note that we specifically do not use tcg_insn_unit 576 here, because there's too much arithmetic throughout that relies 577 on addition and subtraction working on bytes. Rely on the GCC 578 extension that allows arithmetic on void*. */ 579 void *code_gen_buffer; 580 size_t code_gen_buffer_size; 581 void *code_gen_ptr; 582 void *data_gen_ptr; 583 584 /* Threshold to flush the translated code buffer. */ 585 void *code_gen_highwater; 586 587 /* Track which vCPU triggers events */ 588 CPUState *cpu; /* *_trans */ 589 590 /* These structures are private to tcg-target.c.inc. */ 591 #ifdef TCG_TARGET_NEED_LDST_LABELS 592 QSIMPLEQ_HEAD(, TCGLabelQemuLdst) ldst_labels; 593 #endif 594 #ifdef TCG_TARGET_NEED_POOL_LABELS 595 struct TCGLabelPoolData *pool_labels; 596 #endif 597 598 TCGLabel *exitreq_label; 599 600 #ifdef CONFIG_PLUGIN 601 /* 602 * We keep one plugin_tb struct per TCGContext. Note that on every TB 603 * translation we clear but do not free its contents; this way we 604 * avoid a lot of malloc/free churn, since after a few TB's it's 605 * unlikely that we'll need to allocate either more instructions or more 606 * space for instructions (for variable-instruction-length ISAs). 607 */ 608 struct qemu_plugin_tb *plugin_tb; 609 610 /* descriptor of the instruction being translated */ 611 struct qemu_plugin_insn *plugin_insn; 612 #endif 613 614 GHashTable *const_table[TCG_TYPE_COUNT]; 615 TCGTempSet free_temps[TCG_TYPE_COUNT * 2]; 616 TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */ 617 618 QTAILQ_HEAD(, TCGOp) ops, free_ops; 619 QSIMPLEQ_HEAD(, TCGLabel) labels; 620 621 /* Tells which temporary holds a given register. 622 It does not take into account fixed registers */ 623 TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS]; 624 625 uint16_t gen_insn_end_off[TCG_MAX_INSNS]; 626 target_ulong gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS]; 627 628 /* Exit to translator on overflow. */ 629 sigjmp_buf jmp_trans; 630 }; 631 632 static inline bool temp_readonly(TCGTemp *ts) 633 { 634 return ts->kind >= TEMP_FIXED; 635 } 636 637 extern __thread TCGContext *tcg_ctx; 638 extern const void *tcg_code_gen_epilogue; 639 extern uintptr_t tcg_splitwx_diff; 640 extern TCGv_env cpu_env; 641 642 bool in_code_gen_buffer(const void *p); 643 644 #ifdef CONFIG_DEBUG_TCG 645 const void *tcg_splitwx_to_rx(void *rw); 646 void *tcg_splitwx_to_rw(const void *rx); 647 #else 648 static inline const void *tcg_splitwx_to_rx(void *rw) 649 { 650 return rw ? rw + tcg_splitwx_diff : NULL; 651 } 652 653 static inline void *tcg_splitwx_to_rw(const void *rx) 654 { 655 return rx ? (void *)rx - tcg_splitwx_diff : NULL; 656 } 657 #endif 658 659 static inline size_t temp_idx(TCGTemp *ts) 660 { 661 ptrdiff_t n = ts - tcg_ctx->temps; 662 tcg_debug_assert(n >= 0 && n < tcg_ctx->nb_temps); 663 return n; 664 } 665 666 static inline TCGArg temp_arg(TCGTemp *ts) 667 { 668 return (uintptr_t)ts; 669 } 670 671 static inline TCGTemp *arg_temp(TCGArg a) 672 { 673 return (TCGTemp *)(uintptr_t)a; 674 } 675 676 /* Using the offset of a temporary, relative to TCGContext, rather than 677 its index means that we don't use 0. That leaves offset 0 free for 678 a NULL representation without having to leave index 0 unused. */ 679 static inline TCGTemp *tcgv_i32_temp(TCGv_i32 v) 680 { 681 uintptr_t o = (uintptr_t)v; 682 TCGTemp *t = (void *)tcg_ctx + o; 683 tcg_debug_assert(offsetof(TCGContext, temps[temp_idx(t)]) == o); 684 return t; 685 } 686 687 static inline TCGTemp *tcgv_i64_temp(TCGv_i64 v) 688 { 689 return tcgv_i32_temp((TCGv_i32)v); 690 } 691 692 static inline TCGTemp *tcgv_ptr_temp(TCGv_ptr v) 693 { 694 return tcgv_i32_temp((TCGv_i32)v); 695 } 696 697 static inline TCGTemp *tcgv_vec_temp(TCGv_vec v) 698 { 699 return tcgv_i32_temp((TCGv_i32)v); 700 } 701 702 static inline TCGArg tcgv_i32_arg(TCGv_i32 v) 703 { 704 return temp_arg(tcgv_i32_temp(v)); 705 } 706 707 static inline TCGArg tcgv_i64_arg(TCGv_i64 v) 708 { 709 return temp_arg(tcgv_i64_temp(v)); 710 } 711 712 static inline TCGArg tcgv_ptr_arg(TCGv_ptr v) 713 { 714 return temp_arg(tcgv_ptr_temp(v)); 715 } 716 717 static inline TCGArg tcgv_vec_arg(TCGv_vec v) 718 { 719 return temp_arg(tcgv_vec_temp(v)); 720 } 721 722 static inline TCGv_i32 temp_tcgv_i32(TCGTemp *t) 723 { 724 (void)temp_idx(t); /* trigger embedded assert */ 725 return (TCGv_i32)((void *)t - (void *)tcg_ctx); 726 } 727 728 static inline TCGv_i64 temp_tcgv_i64(TCGTemp *t) 729 { 730 return (TCGv_i64)temp_tcgv_i32(t); 731 } 732 733 static inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t) 734 { 735 return (TCGv_ptr)temp_tcgv_i32(t); 736 } 737 738 static inline TCGv_vec temp_tcgv_vec(TCGTemp *t) 739 { 740 return (TCGv_vec)temp_tcgv_i32(t); 741 } 742 743 static inline TCGArg tcg_get_insn_param(TCGOp *op, int arg) 744 { 745 return op->args[arg]; 746 } 747 748 static inline void tcg_set_insn_param(TCGOp *op, int arg, TCGArg v) 749 { 750 op->args[arg] = v; 751 } 752 753 static inline target_ulong tcg_get_insn_start_param(TCGOp *op, int arg) 754 { 755 #if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS 756 return tcg_get_insn_param(op, arg); 757 #else 758 return tcg_get_insn_param(op, arg * 2) | 759 ((uint64_t)tcg_get_insn_param(op, arg * 2 + 1) << 32); 760 #endif 761 } 762 763 static inline void tcg_set_insn_start_param(TCGOp *op, int arg, target_ulong v) 764 { 765 #if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS 766 tcg_set_insn_param(op, arg, v); 767 #else 768 tcg_set_insn_param(op, arg * 2, v); 769 tcg_set_insn_param(op, arg * 2 + 1, v >> 32); 770 #endif 771 } 772 773 /* The last op that was emitted. */ 774 static inline TCGOp *tcg_last_op(void) 775 { 776 return QTAILQ_LAST(&tcg_ctx->ops); 777 } 778 779 /* Test for whether to terminate the TB for using too many opcodes. */ 780 static inline bool tcg_op_buf_full(void) 781 { 782 /* This is not a hard limit, it merely stops translation when 783 * we have produced "enough" opcodes. We want to limit TB size 784 * such that a RISC host can reasonably use a 16-bit signed 785 * branch within the TB. We also need to be mindful of the 786 * 16-bit unsigned offsets, TranslationBlock.jmp_reset_offset[] 787 * and TCGContext.gen_insn_end_off[]. 788 */ 789 return tcg_ctx->nb_ops >= 4000; 790 } 791 792 /* pool based memory allocation */ 793 794 /* user-mode: mmap_lock must be held for tcg_malloc_internal. */ 795 void *tcg_malloc_internal(TCGContext *s, int size); 796 void tcg_pool_reset(TCGContext *s); 797 TranslationBlock *tcg_tb_alloc(TCGContext *s); 798 799 void tcg_region_reset_all(void); 800 801 size_t tcg_code_size(void); 802 size_t tcg_code_capacity(void); 803 804 void tcg_tb_insert(TranslationBlock *tb); 805 void tcg_tb_remove(TranslationBlock *tb); 806 TranslationBlock *tcg_tb_lookup(uintptr_t tc_ptr); 807 void tcg_tb_foreach(GTraverseFunc func, gpointer user_data); 808 size_t tcg_nb_tbs(void); 809 810 /* user-mode: Called with mmap_lock held. */ 811 static inline void *tcg_malloc(int size) 812 { 813 TCGContext *s = tcg_ctx; 814 uint8_t *ptr, *ptr_end; 815 816 /* ??? This is a weak placeholder for minimum malloc alignment. */ 817 size = QEMU_ALIGN_UP(size, 8); 818 819 ptr = s->pool_cur; 820 ptr_end = ptr + size; 821 if (unlikely(ptr_end > s->pool_end)) { 822 return tcg_malloc_internal(tcg_ctx, size); 823 } else { 824 s->pool_cur = ptr_end; 825 return ptr; 826 } 827 } 828 829 void tcg_init(size_t tb_size, int splitwx, unsigned max_cpus); 830 void tcg_register_thread(void); 831 void tcg_prologue_init(TCGContext *s); 832 void tcg_func_start(TCGContext *s); 833 834 int tcg_gen_code(TCGContext *s, TranslationBlock *tb, target_ulong pc_start); 835 836 void tb_target_set_jmp_target(const TranslationBlock *, int, 837 uintptr_t, uintptr_t); 838 839 void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size); 840 841 TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr, 842 intptr_t, const char *); 843 TCGTemp *tcg_temp_new_internal(TCGType, bool); 844 void tcg_temp_free_internal(TCGTemp *); 845 TCGv_vec tcg_temp_new_vec(TCGType type); 846 TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match); 847 848 static inline void tcg_temp_free_i32(TCGv_i32 arg) 849 { 850 tcg_temp_free_internal(tcgv_i32_temp(arg)); 851 } 852 853 static inline void tcg_temp_free_i64(TCGv_i64 arg) 854 { 855 tcg_temp_free_internal(tcgv_i64_temp(arg)); 856 } 857 858 static inline void tcg_temp_free_ptr(TCGv_ptr arg) 859 { 860 tcg_temp_free_internal(tcgv_ptr_temp(arg)); 861 } 862 863 static inline void tcg_temp_free_vec(TCGv_vec arg) 864 { 865 tcg_temp_free_internal(tcgv_vec_temp(arg)); 866 } 867 868 static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset, 869 const char *name) 870 { 871 TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name); 872 return temp_tcgv_i32(t); 873 } 874 875 static inline TCGv_i32 tcg_temp_new_i32(void) 876 { 877 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, false); 878 return temp_tcgv_i32(t); 879 } 880 881 static inline TCGv_i32 tcg_temp_local_new_i32(void) 882 { 883 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, true); 884 return temp_tcgv_i32(t); 885 } 886 887 static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset, 888 const char *name) 889 { 890 TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name); 891 return temp_tcgv_i64(t); 892 } 893 894 static inline TCGv_i64 tcg_temp_new_i64(void) 895 { 896 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, false); 897 return temp_tcgv_i64(t); 898 } 899 900 static inline TCGv_i64 tcg_temp_local_new_i64(void) 901 { 902 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, true); 903 return temp_tcgv_i64(t); 904 } 905 906 static inline TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t offset, 907 const char *name) 908 { 909 TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_PTR, reg, offset, name); 910 return temp_tcgv_ptr(t); 911 } 912 913 static inline TCGv_ptr tcg_temp_new_ptr(void) 914 { 915 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, false); 916 return temp_tcgv_ptr(t); 917 } 918 919 static inline TCGv_ptr tcg_temp_local_new_ptr(void) 920 { 921 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, true); 922 return temp_tcgv_ptr(t); 923 } 924 925 #if defined(CONFIG_DEBUG_TCG) 926 /* If you call tcg_clear_temp_count() at the start of a section of 927 * code which is not supposed to leak any TCG temporaries, then 928 * calling tcg_check_temp_count() at the end of the section will 929 * return 1 if the section did in fact leak a temporary. 930 */ 931 void tcg_clear_temp_count(void); 932 int tcg_check_temp_count(void); 933 #else 934 #define tcg_clear_temp_count() do { } while (0) 935 #define tcg_check_temp_count() 0 936 #endif 937 938 int64_t tcg_cpu_exec_time(void); 939 void tcg_dump_info(GString *buf); 940 void tcg_dump_op_count(GString *buf); 941 942 #define TCG_CT_CONST 1 /* any constant of register size */ 943 944 typedef struct TCGArgConstraint { 945 unsigned ct : 16; 946 unsigned alias_index : 4; 947 unsigned sort_index : 4; 948 unsigned pair_index : 4; 949 unsigned pair : 2; /* 0: none, 1: first, 2: second, 3: second alias */ 950 bool oalias : 1; 951 bool ialias : 1; 952 bool newreg : 1; 953 TCGRegSet regs; 954 } TCGArgConstraint; 955 956 #define TCG_MAX_OP_ARGS 16 957 958 /* Bits for TCGOpDef->flags, 8 bits available, all used. */ 959 enum { 960 /* Instruction exits the translation block. */ 961 TCG_OPF_BB_EXIT = 0x01, 962 /* Instruction defines the end of a basic block. */ 963 TCG_OPF_BB_END = 0x02, 964 /* Instruction clobbers call registers and potentially update globals. */ 965 TCG_OPF_CALL_CLOBBER = 0x04, 966 /* Instruction has side effects: it cannot be removed if its outputs 967 are not used, and might trigger exceptions. */ 968 TCG_OPF_SIDE_EFFECTS = 0x08, 969 /* Instruction operands are 64-bits (otherwise 32-bits). */ 970 TCG_OPF_64BIT = 0x10, 971 /* Instruction is optional and not implemented by the host, or insn 972 is generic and should not be implemened by the host. */ 973 TCG_OPF_NOT_PRESENT = 0x20, 974 /* Instruction operands are vectors. */ 975 TCG_OPF_VECTOR = 0x40, 976 /* Instruction is a conditional branch. */ 977 TCG_OPF_COND_BRANCH = 0x80 978 }; 979 980 typedef struct TCGOpDef { 981 const char *name; 982 uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args; 983 uint8_t flags; 984 TCGArgConstraint *args_ct; 985 } TCGOpDef; 986 987 extern TCGOpDef tcg_op_defs[]; 988 extern const size_t tcg_op_defs_max; 989 990 typedef struct TCGTargetOpDef { 991 TCGOpcode op; 992 const char *args_ct_str[TCG_MAX_OP_ARGS]; 993 } TCGTargetOpDef; 994 995 #define tcg_abort() \ 996 do {\ 997 fprintf(stderr, "%s:%d: tcg fatal error\n", __FILE__, __LINE__);\ 998 abort();\ 999 } while (0) 1000 1001 bool tcg_op_supported(TCGOpcode op); 1002 1003 void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args); 1004 1005 TCGOp *tcg_emit_op(TCGOpcode opc, unsigned nargs); 1006 void tcg_op_remove(TCGContext *s, TCGOp *op); 1007 TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *op, 1008 TCGOpcode opc, unsigned nargs); 1009 TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *op, 1010 TCGOpcode opc, unsigned nargs); 1011 1012 /** 1013 * tcg_remove_ops_after: 1014 * @op: target operation 1015 * 1016 * Discard any opcodes emitted since @op. Expected usage is to save 1017 * a starting point with tcg_last_op(), speculatively emit opcodes, 1018 * then decide whether or not to keep those opcodes after the fact. 1019 */ 1020 void tcg_remove_ops_after(TCGOp *op); 1021 1022 void tcg_optimize(TCGContext *s); 1023 1024 /* Allocate a new temporary and initialize it with a constant. */ 1025 TCGv_i32 tcg_const_i32(int32_t val); 1026 TCGv_i64 tcg_const_i64(int64_t val); 1027 TCGv_i32 tcg_const_local_i32(int32_t val); 1028 TCGv_i64 tcg_const_local_i64(int64_t val); 1029 TCGv_vec tcg_const_zeros_vec(TCGType); 1030 TCGv_vec tcg_const_ones_vec(TCGType); 1031 TCGv_vec tcg_const_zeros_vec_matching(TCGv_vec); 1032 TCGv_vec tcg_const_ones_vec_matching(TCGv_vec); 1033 1034 /* 1035 * Locate or create a read-only temporary that is a constant. 1036 * This kind of temporary need not be freed, but for convenience 1037 * will be silently ignored by tcg_temp_free_*. 1038 */ 1039 TCGTemp *tcg_constant_internal(TCGType type, int64_t val); 1040 1041 static inline TCGv_i32 tcg_constant_i32(int32_t val) 1042 { 1043 return temp_tcgv_i32(tcg_constant_internal(TCG_TYPE_I32, val)); 1044 } 1045 1046 static inline TCGv_i64 tcg_constant_i64(int64_t val) 1047 { 1048 return temp_tcgv_i64(tcg_constant_internal(TCG_TYPE_I64, val)); 1049 } 1050 1051 TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val); 1052 TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t val); 1053 1054 #if UINTPTR_MAX == UINT32_MAX 1055 # define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i32((intptr_t)(x))) 1056 # define tcg_const_local_ptr(x) ((TCGv_ptr)tcg_const_local_i32((intptr_t)(x))) 1057 # define tcg_constant_ptr(x) ((TCGv_ptr)tcg_constant_i32((intptr_t)(x))) 1058 #else 1059 # define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i64((intptr_t)(x))) 1060 # define tcg_const_local_ptr(x) ((TCGv_ptr)tcg_const_local_i64((intptr_t)(x))) 1061 # define tcg_constant_ptr(x) ((TCGv_ptr)tcg_constant_i64((intptr_t)(x))) 1062 #endif 1063 1064 TCGLabel *gen_new_label(void); 1065 1066 /** 1067 * label_arg 1068 * @l: label 1069 * 1070 * Encode a label for storage in the TCG opcode stream. 1071 */ 1072 1073 static inline TCGArg label_arg(TCGLabel *l) 1074 { 1075 return (uintptr_t)l; 1076 } 1077 1078 /** 1079 * arg_label 1080 * @i: value 1081 * 1082 * The opposite of label_arg. Retrieve a label from the 1083 * encoding of the TCG opcode stream. 1084 */ 1085 1086 static inline TCGLabel *arg_label(TCGArg i) 1087 { 1088 return (TCGLabel *)(uintptr_t)i; 1089 } 1090 1091 /** 1092 * tcg_ptr_byte_diff 1093 * @a, @b: addresses to be differenced 1094 * 1095 * There are many places within the TCG backends where we need a byte 1096 * difference between two pointers. While this can be accomplished 1097 * with local casting, it's easy to get wrong -- especially if one is 1098 * concerned with the signedness of the result. 1099 * 1100 * This version relies on GCC's void pointer arithmetic to get the 1101 * correct result. 1102 */ 1103 1104 static inline ptrdiff_t tcg_ptr_byte_diff(const void *a, const void *b) 1105 { 1106 return a - b; 1107 } 1108 1109 /** 1110 * tcg_pcrel_diff 1111 * @s: the tcg context 1112 * @target: address of the target 1113 * 1114 * Produce a pc-relative difference, from the current code_ptr 1115 * to the destination address. 1116 */ 1117 1118 static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, const void *target) 1119 { 1120 return tcg_ptr_byte_diff(target, tcg_splitwx_to_rx(s->code_ptr)); 1121 } 1122 1123 /** 1124 * tcg_tbrel_diff 1125 * @s: the tcg context 1126 * @target: address of the target 1127 * 1128 * Produce a difference, from the beginning of the current TB code 1129 * to the destination address. 1130 */ 1131 static inline ptrdiff_t tcg_tbrel_diff(TCGContext *s, const void *target) 1132 { 1133 return tcg_ptr_byte_diff(target, tcg_splitwx_to_rx(s->code_buf)); 1134 } 1135 1136 /** 1137 * tcg_current_code_size 1138 * @s: the tcg context 1139 * 1140 * Compute the current code size within the translation block. 1141 * This is used to fill in qemu's data structures for goto_tb. 1142 */ 1143 1144 static inline size_t tcg_current_code_size(TCGContext *s) 1145 { 1146 return tcg_ptr_byte_diff(s->code_ptr, s->code_buf); 1147 } 1148 1149 /** 1150 * tcg_qemu_tb_exec: 1151 * @env: pointer to CPUArchState for the CPU 1152 * @tb_ptr: address of generated code for the TB to execute 1153 * 1154 * Start executing code from a given translation block. 1155 * Where translation blocks have been linked, execution 1156 * may proceed from the given TB into successive ones. 1157 * Control eventually returns only when some action is needed 1158 * from the top-level loop: either control must pass to a TB 1159 * which has not yet been directly linked, or an asynchronous 1160 * event such as an interrupt needs handling. 1161 * 1162 * Return: The return value is the value passed to the corresponding 1163 * tcg_gen_exit_tb() at translation time of the last TB attempted to execute. 1164 * The value is either zero or a 4-byte aligned pointer to that TB combined 1165 * with additional information in its two least significant bits. The 1166 * additional information is encoded as follows: 1167 * 0, 1: the link between this TB and the next is via the specified 1168 * TB index (0 or 1). That is, we left the TB via (the equivalent 1169 * of) "goto_tb <index>". The main loop uses this to determine 1170 * how to link the TB just executed to the next. 1171 * 2: we are using instruction counting code generation, and we 1172 * did not start executing this TB because the instruction counter 1173 * would hit zero midway through it. In this case the pointer 1174 * returned is the TB we were about to execute, and the caller must 1175 * arrange to execute the remaining count of instructions. 1176 * 3: we stopped because the CPU's exit_request flag was set 1177 * (usually meaning that there is an interrupt that needs to be 1178 * handled). The pointer returned is the TB we were about to execute 1179 * when we noticed the pending exit request. 1180 * 1181 * If the bottom two bits indicate an exit-via-index then the CPU 1182 * state is correctly synchronised and ready for execution of the next 1183 * TB (and in particular the guest PC is the address to execute next). 1184 * Otherwise, we gave up on execution of this TB before it started, and 1185 * the caller must fix up the CPU state by calling the CPU's 1186 * synchronize_from_tb() method with the TB pointer we return (falling 1187 * back to calling the CPU's set_pc method with tb->pb if no 1188 * synchronize_from_tb() method exists). 1189 * 1190 * Note that TCG targets may use a different definition of tcg_qemu_tb_exec 1191 * to this default (which just calls the prologue.code emitted by 1192 * tcg_target_qemu_prologue()). 1193 */ 1194 #define TB_EXIT_MASK 3 1195 #define TB_EXIT_IDX0 0 1196 #define TB_EXIT_IDX1 1 1197 #define TB_EXIT_IDXMAX 1 1198 #define TB_EXIT_REQUESTED 3 1199 1200 #ifdef CONFIG_TCG_INTERPRETER 1201 uintptr_t tcg_qemu_tb_exec(CPUArchState *env, const void *tb_ptr); 1202 #else 1203 typedef uintptr_t tcg_prologue_fn(CPUArchState *env, const void *tb_ptr); 1204 extern tcg_prologue_fn *tcg_qemu_tb_exec; 1205 #endif 1206 1207 void tcg_register_jit(const void *buf, size_t buf_size); 1208 1209 #if TCG_TARGET_MAYBE_vec 1210 /* Return zero if the tuple (opc, type, vece) is unsupportable; 1211 return > 0 if it is directly supportable; 1212 return < 0 if we must call tcg_expand_vec_op. */ 1213 int tcg_can_emit_vec_op(TCGOpcode, TCGType, unsigned); 1214 #else 1215 static inline int tcg_can_emit_vec_op(TCGOpcode o, TCGType t, unsigned ve) 1216 { 1217 return 0; 1218 } 1219 #endif 1220 1221 /* Expand the tuple (opc, type, vece) on the given arguments. */ 1222 void tcg_expand_vec_op(TCGOpcode, TCGType, unsigned, TCGArg, ...); 1223 1224 /* Replicate a constant C accoring to the log2 of the element size. */ 1225 uint64_t dup_const(unsigned vece, uint64_t c); 1226 1227 #define dup_const(VECE, C) \ 1228 (__builtin_constant_p(VECE) \ 1229 ? ( (VECE) == MO_8 ? 0x0101010101010101ull * (uint8_t)(C) \ 1230 : (VECE) == MO_16 ? 0x0001000100010001ull * (uint16_t)(C) \ 1231 : (VECE) == MO_32 ? 0x0000000100000001ull * (uint32_t)(C) \ 1232 : (VECE) == MO_64 ? (uint64_t)(C) \ 1233 : (qemu_build_not_reached_always(), 0)) \ 1234 : dup_const(VECE, C)) 1235 1236 #if TARGET_LONG_BITS == 64 1237 # define dup_const_tl dup_const 1238 #else 1239 # define dup_const_tl(VECE, C) \ 1240 (__builtin_constant_p(VECE) \ 1241 ? ( (VECE) == MO_8 ? 0x01010101ul * (uint8_t)(C) \ 1242 : (VECE) == MO_16 ? 0x00010001ul * (uint16_t)(C) \ 1243 : (VECE) == MO_32 ? 0x00000001ul * (uint32_t)(C) \ 1244 : (qemu_build_not_reached_always(), 0)) \ 1245 : (target_long)dup_const(VECE, C)) 1246 #endif 1247 1248 #ifdef CONFIG_DEBUG_TCG 1249 void tcg_assert_listed_vecop(TCGOpcode); 1250 #else 1251 static inline void tcg_assert_listed_vecop(TCGOpcode op) { } 1252 #endif 1253 1254 static inline const TCGOpcode *tcg_swap_vecop_list(const TCGOpcode *n) 1255 { 1256 #ifdef CONFIG_DEBUG_TCG 1257 const TCGOpcode *o = tcg_ctx->vecop_list; 1258 tcg_ctx->vecop_list = n; 1259 return o; 1260 #else 1261 return NULL; 1262 #endif 1263 } 1264 1265 bool tcg_can_emit_vecop_list(const TCGOpcode *, TCGType, unsigned); 1266 1267 #endif /* TCG_H */ 1268