1 /* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #ifndef TCG_H 26 #define TCG_H 27 28 #include "cpu.h" 29 #include "exec/memop.h" 30 #include "exec/memopidx.h" 31 #include "qemu/bitops.h" 32 #include "qemu/plugin.h" 33 #include "qemu/queue.h" 34 #include "tcg/tcg-mo.h" 35 #include "tcg-target.h" 36 #include "tcg/tcg-cond.h" 37 #include "tcg/debug-assert.h" 38 39 /* XXX: make safe guess about sizes */ 40 #define MAX_OP_PER_INSTR 266 41 42 #define MAX_CALL_IARGS 7 43 44 #define CPU_TEMP_BUF_NLONGS 128 45 #define TCG_STATIC_FRAME_SIZE (CPU_TEMP_BUF_NLONGS * sizeof(long)) 46 47 /* Default target word size to pointer size. */ 48 #ifndef TCG_TARGET_REG_BITS 49 # if UINTPTR_MAX == UINT32_MAX 50 # define TCG_TARGET_REG_BITS 32 51 # elif UINTPTR_MAX == UINT64_MAX 52 # define TCG_TARGET_REG_BITS 64 53 # else 54 # error Unknown pointer size for tcg target 55 # endif 56 #endif 57 58 #if TCG_TARGET_REG_BITS == 32 59 typedef int32_t tcg_target_long; 60 typedef uint32_t tcg_target_ulong; 61 #define TCG_PRIlx PRIx32 62 #define TCG_PRIld PRId32 63 #elif TCG_TARGET_REG_BITS == 64 64 typedef int64_t tcg_target_long; 65 typedef uint64_t tcg_target_ulong; 66 #define TCG_PRIlx PRIx64 67 #define TCG_PRIld PRId64 68 #else 69 #error unsupported 70 #endif 71 72 /* Oversized TCG guests make things like MTTCG hard 73 * as we can't use atomics for cputlb updates. 74 */ 75 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS 76 #define TCG_OVERSIZED_GUEST 1 77 #else 78 #define TCG_OVERSIZED_GUEST 0 79 #endif 80 81 #if TCG_TARGET_NB_REGS <= 32 82 typedef uint32_t TCGRegSet; 83 #elif TCG_TARGET_NB_REGS <= 64 84 typedef uint64_t TCGRegSet; 85 #else 86 #error unsupported 87 #endif 88 89 #if TCG_TARGET_REG_BITS == 32 90 /* Turn some undef macros into false macros. */ 91 #define TCG_TARGET_HAS_extrl_i64_i32 0 92 #define TCG_TARGET_HAS_extrh_i64_i32 0 93 #define TCG_TARGET_HAS_div_i64 0 94 #define TCG_TARGET_HAS_rem_i64 0 95 #define TCG_TARGET_HAS_div2_i64 0 96 #define TCG_TARGET_HAS_rot_i64 0 97 #define TCG_TARGET_HAS_ext8s_i64 0 98 #define TCG_TARGET_HAS_ext16s_i64 0 99 #define TCG_TARGET_HAS_ext32s_i64 0 100 #define TCG_TARGET_HAS_ext8u_i64 0 101 #define TCG_TARGET_HAS_ext16u_i64 0 102 #define TCG_TARGET_HAS_ext32u_i64 0 103 #define TCG_TARGET_HAS_bswap16_i64 0 104 #define TCG_TARGET_HAS_bswap32_i64 0 105 #define TCG_TARGET_HAS_bswap64_i64 0 106 #define TCG_TARGET_HAS_neg_i64 0 107 #define TCG_TARGET_HAS_not_i64 0 108 #define TCG_TARGET_HAS_andc_i64 0 109 #define TCG_TARGET_HAS_orc_i64 0 110 #define TCG_TARGET_HAS_eqv_i64 0 111 #define TCG_TARGET_HAS_nand_i64 0 112 #define TCG_TARGET_HAS_nor_i64 0 113 #define TCG_TARGET_HAS_clz_i64 0 114 #define TCG_TARGET_HAS_ctz_i64 0 115 #define TCG_TARGET_HAS_ctpop_i64 0 116 #define TCG_TARGET_HAS_deposit_i64 0 117 #define TCG_TARGET_HAS_extract_i64 0 118 #define TCG_TARGET_HAS_sextract_i64 0 119 #define TCG_TARGET_HAS_extract2_i64 0 120 #define TCG_TARGET_HAS_movcond_i64 0 121 #define TCG_TARGET_HAS_add2_i64 0 122 #define TCG_TARGET_HAS_sub2_i64 0 123 #define TCG_TARGET_HAS_mulu2_i64 0 124 #define TCG_TARGET_HAS_muls2_i64 0 125 #define TCG_TARGET_HAS_muluh_i64 0 126 #define TCG_TARGET_HAS_mulsh_i64 0 127 /* Turn some undef macros into true macros. */ 128 #define TCG_TARGET_HAS_add2_i32 1 129 #define TCG_TARGET_HAS_sub2_i32 1 130 #endif 131 132 #ifndef TCG_TARGET_deposit_i32_valid 133 #define TCG_TARGET_deposit_i32_valid(ofs, len) 1 134 #endif 135 #ifndef TCG_TARGET_deposit_i64_valid 136 #define TCG_TARGET_deposit_i64_valid(ofs, len) 1 137 #endif 138 #ifndef TCG_TARGET_extract_i32_valid 139 #define TCG_TARGET_extract_i32_valid(ofs, len) 1 140 #endif 141 #ifndef TCG_TARGET_extract_i64_valid 142 #define TCG_TARGET_extract_i64_valid(ofs, len) 1 143 #endif 144 145 /* Only one of DIV or DIV2 should be defined. */ 146 #if defined(TCG_TARGET_HAS_div_i32) 147 #define TCG_TARGET_HAS_div2_i32 0 148 #elif defined(TCG_TARGET_HAS_div2_i32) 149 #define TCG_TARGET_HAS_div_i32 0 150 #define TCG_TARGET_HAS_rem_i32 0 151 #endif 152 #if defined(TCG_TARGET_HAS_div_i64) 153 #define TCG_TARGET_HAS_div2_i64 0 154 #elif defined(TCG_TARGET_HAS_div2_i64) 155 #define TCG_TARGET_HAS_div_i64 0 156 #define TCG_TARGET_HAS_rem_i64 0 157 #endif 158 159 #if !defined(TCG_TARGET_HAS_v64) \ 160 && !defined(TCG_TARGET_HAS_v128) \ 161 && !defined(TCG_TARGET_HAS_v256) 162 #define TCG_TARGET_MAYBE_vec 0 163 #define TCG_TARGET_HAS_abs_vec 0 164 #define TCG_TARGET_HAS_neg_vec 0 165 #define TCG_TARGET_HAS_not_vec 0 166 #define TCG_TARGET_HAS_andc_vec 0 167 #define TCG_TARGET_HAS_orc_vec 0 168 #define TCG_TARGET_HAS_nand_vec 0 169 #define TCG_TARGET_HAS_nor_vec 0 170 #define TCG_TARGET_HAS_eqv_vec 0 171 #define TCG_TARGET_HAS_roti_vec 0 172 #define TCG_TARGET_HAS_rots_vec 0 173 #define TCG_TARGET_HAS_rotv_vec 0 174 #define TCG_TARGET_HAS_shi_vec 0 175 #define TCG_TARGET_HAS_shs_vec 0 176 #define TCG_TARGET_HAS_shv_vec 0 177 #define TCG_TARGET_HAS_mul_vec 0 178 #define TCG_TARGET_HAS_sat_vec 0 179 #define TCG_TARGET_HAS_minmax_vec 0 180 #define TCG_TARGET_HAS_bitsel_vec 0 181 #define TCG_TARGET_HAS_cmpsel_vec 0 182 #else 183 #define TCG_TARGET_MAYBE_vec 1 184 #endif 185 #ifndef TCG_TARGET_HAS_v64 186 #define TCG_TARGET_HAS_v64 0 187 #endif 188 #ifndef TCG_TARGET_HAS_v128 189 #define TCG_TARGET_HAS_v128 0 190 #endif 191 #ifndef TCG_TARGET_HAS_v256 192 #define TCG_TARGET_HAS_v256 0 193 #endif 194 195 #ifndef TARGET_INSN_START_EXTRA_WORDS 196 # define TARGET_INSN_START_WORDS 1 197 #else 198 # define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS) 199 #endif 200 201 typedef enum TCGOpcode { 202 #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name, 203 #include "tcg/tcg-opc.h" 204 #undef DEF 205 NB_OPS, 206 } TCGOpcode; 207 208 #define tcg_regset_set_reg(d, r) ((d) |= (TCGRegSet)1 << (r)) 209 #define tcg_regset_reset_reg(d, r) ((d) &= ~((TCGRegSet)1 << (r))) 210 #define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1) 211 212 #ifndef TCG_TARGET_INSN_UNIT_SIZE 213 # error "Missing TCG_TARGET_INSN_UNIT_SIZE" 214 #elif TCG_TARGET_INSN_UNIT_SIZE == 1 215 typedef uint8_t tcg_insn_unit; 216 #elif TCG_TARGET_INSN_UNIT_SIZE == 2 217 typedef uint16_t tcg_insn_unit; 218 #elif TCG_TARGET_INSN_UNIT_SIZE == 4 219 typedef uint32_t tcg_insn_unit; 220 #elif TCG_TARGET_INSN_UNIT_SIZE == 8 221 typedef uint64_t tcg_insn_unit; 222 #else 223 /* The port better have done this. */ 224 #endif 225 226 typedef struct TCGRelocation TCGRelocation; 227 struct TCGRelocation { 228 QSIMPLEQ_ENTRY(TCGRelocation) next; 229 tcg_insn_unit *ptr; 230 intptr_t addend; 231 int type; 232 }; 233 234 typedef struct TCGOp TCGOp; 235 typedef struct TCGLabelUse TCGLabelUse; 236 struct TCGLabelUse { 237 QSIMPLEQ_ENTRY(TCGLabelUse) next; 238 TCGOp *op; 239 }; 240 241 typedef struct TCGLabel TCGLabel; 242 struct TCGLabel { 243 bool present; 244 bool has_value; 245 uint16_t id; 246 union { 247 uintptr_t value; 248 const tcg_insn_unit *value_ptr; 249 } u; 250 QSIMPLEQ_HEAD(, TCGLabelUse) branches; 251 QSIMPLEQ_HEAD(, TCGRelocation) relocs; 252 QSIMPLEQ_ENTRY(TCGLabel) next; 253 }; 254 255 typedef struct TCGPool { 256 struct TCGPool *next; 257 int size; 258 uint8_t data[] __attribute__ ((aligned)); 259 } TCGPool; 260 261 #define TCG_POOL_CHUNK_SIZE 32768 262 263 #define TCG_MAX_TEMPS 512 264 #define TCG_MAX_INSNS 512 265 266 /* when the size of the arguments of a called function is smaller than 267 this value, they are statically allocated in the TB stack frame */ 268 #define TCG_STATIC_CALL_ARGS_SIZE 128 269 270 typedef enum TCGType { 271 TCG_TYPE_I32, 272 TCG_TYPE_I64, 273 TCG_TYPE_I128, 274 275 TCG_TYPE_V64, 276 TCG_TYPE_V128, 277 TCG_TYPE_V256, 278 279 /* Number of different types (integer not enum) */ 280 #define TCG_TYPE_COUNT (TCG_TYPE_V256 + 1) 281 282 /* An alias for the size of the host register. */ 283 #if TCG_TARGET_REG_BITS == 32 284 TCG_TYPE_REG = TCG_TYPE_I32, 285 #else 286 TCG_TYPE_REG = TCG_TYPE_I64, 287 #endif 288 289 /* An alias for the size of the native pointer. */ 290 #if UINTPTR_MAX == UINT32_MAX 291 TCG_TYPE_PTR = TCG_TYPE_I32, 292 #else 293 TCG_TYPE_PTR = TCG_TYPE_I64, 294 #endif 295 296 /* An alias for the size of the target "long", aka register. */ 297 #if TARGET_LONG_BITS == 64 298 TCG_TYPE_TL = TCG_TYPE_I64, 299 #else 300 TCG_TYPE_TL = TCG_TYPE_I32, 301 #endif 302 } TCGType; 303 304 /** 305 * tcg_type_size 306 * @t: type 307 * 308 * Return the size of the type in bytes. 309 */ 310 static inline int tcg_type_size(TCGType t) 311 { 312 unsigned i = t; 313 if (i >= TCG_TYPE_V64) { 314 tcg_debug_assert(i < TCG_TYPE_COUNT); 315 i -= TCG_TYPE_V64 - 1; 316 } 317 return 4 << i; 318 } 319 320 /** 321 * get_alignment_bits 322 * @memop: MemOp value 323 * 324 * Extract the alignment size from the memop. 325 */ 326 static inline unsigned get_alignment_bits(MemOp memop) 327 { 328 unsigned a = memop & MO_AMASK; 329 330 if (a == MO_UNALN) { 331 /* No alignment required. */ 332 a = 0; 333 } else if (a == MO_ALIGN) { 334 /* A natural alignment requirement. */ 335 a = memop & MO_SIZE; 336 } else { 337 /* A specific alignment requirement. */ 338 a = a >> MO_ASHIFT; 339 } 340 #if defined(CONFIG_SOFTMMU) 341 /* The requested alignment cannot overlap the TLB flags. */ 342 tcg_debug_assert((TLB_FLAGS_MASK & ((1 << a) - 1)) == 0); 343 #endif 344 return a; 345 } 346 347 typedef tcg_target_ulong TCGArg; 348 349 /* Define type and accessor macros for TCG variables. 350 351 TCG variables are the inputs and outputs of TCG ops, as described 352 in tcg/README. Target CPU front-end code uses these types to deal 353 with TCG variables as it emits TCG code via the tcg_gen_* functions. 354 They come in several flavours: 355 * TCGv_i32 : 32 bit integer type 356 * TCGv_i64 : 64 bit integer type 357 * TCGv_i128 : 128 bit integer type 358 * TCGv_ptr : a host pointer type 359 * TCGv_vec : a host vector type; the exact size is not exposed 360 to the CPU front-end code. 361 * TCGv : an integer type the same size as target_ulong 362 (an alias for either TCGv_i32 or TCGv_i64) 363 The compiler's type checking will complain if you mix them 364 up and pass the wrong sized TCGv to a function. 365 366 Users of tcg_gen_* don't need to know about any of the internal 367 details of these, and should treat them as opaque types. 368 You won't be able to look inside them in a debugger either. 369 370 Internal implementation details follow: 371 372 Note that there is no definition of the structs TCGv_i32_d etc anywhere. 373 This is deliberate, because the values we store in variables of type 374 TCGv_i32 are not really pointers-to-structures. They're just small 375 integers, but keeping them in pointer types like this means that the 376 compiler will complain if you accidentally pass a TCGv_i32 to a 377 function which takes a TCGv_i64, and so on. Only the internals of 378 TCG need to care about the actual contents of the types. */ 379 380 typedef struct TCGv_i32_d *TCGv_i32; 381 typedef struct TCGv_i64_d *TCGv_i64; 382 typedef struct TCGv_i128_d *TCGv_i128; 383 typedef struct TCGv_ptr_d *TCGv_ptr; 384 typedef struct TCGv_vec_d *TCGv_vec; 385 typedef TCGv_ptr TCGv_env; 386 #if TARGET_LONG_BITS == 32 387 #define TCGv TCGv_i32 388 #elif TARGET_LONG_BITS == 64 389 #define TCGv TCGv_i64 390 #else 391 #error Unhandled TARGET_LONG_BITS value 392 #endif 393 394 /* call flags */ 395 /* Helper does not read globals (either directly or through an exception). It 396 implies TCG_CALL_NO_WRITE_GLOBALS. */ 397 #define TCG_CALL_NO_READ_GLOBALS 0x0001 398 /* Helper does not write globals */ 399 #define TCG_CALL_NO_WRITE_GLOBALS 0x0002 400 /* Helper can be safely suppressed if the return value is not used. */ 401 #define TCG_CALL_NO_SIDE_EFFECTS 0x0004 402 /* Helper is G_NORETURN. */ 403 #define TCG_CALL_NO_RETURN 0x0008 404 /* Helper is part of Plugins. */ 405 #define TCG_CALL_PLUGIN 0x0010 406 407 /* convenience version of most used call flags */ 408 #define TCG_CALL_NO_RWG TCG_CALL_NO_READ_GLOBALS 409 #define TCG_CALL_NO_WG TCG_CALL_NO_WRITE_GLOBALS 410 #define TCG_CALL_NO_SE TCG_CALL_NO_SIDE_EFFECTS 411 #define TCG_CALL_NO_RWG_SE (TCG_CALL_NO_RWG | TCG_CALL_NO_SE) 412 #define TCG_CALL_NO_WG_SE (TCG_CALL_NO_WG | TCG_CALL_NO_SE) 413 414 /* 415 * Flags for the bswap opcodes. 416 * If IZ, the input is zero-extended, otherwise unknown. 417 * If OZ or OS, the output is zero- or sign-extended respectively, 418 * otherwise the high bits are undefined. 419 */ 420 enum { 421 TCG_BSWAP_IZ = 1, 422 TCG_BSWAP_OZ = 2, 423 TCG_BSWAP_OS = 4, 424 }; 425 426 typedef enum TCGTempVal { 427 TEMP_VAL_DEAD, 428 TEMP_VAL_REG, 429 TEMP_VAL_MEM, 430 TEMP_VAL_CONST, 431 } TCGTempVal; 432 433 typedef enum TCGTempKind { 434 /* 435 * Temp is dead at the end of the extended basic block (EBB), 436 * the single-entry multiple-exit region that falls through 437 * conditional branches. 438 */ 439 TEMP_EBB, 440 /* Temp is live across the entire translation block, but dead at end. */ 441 TEMP_TB, 442 /* Temp is live across the entire translation block, and between them. */ 443 TEMP_GLOBAL, 444 /* Temp is in a fixed register. */ 445 TEMP_FIXED, 446 /* Temp is a fixed constant. */ 447 TEMP_CONST, 448 } TCGTempKind; 449 450 typedef struct TCGTemp { 451 TCGReg reg:8; 452 TCGTempVal val_type:8; 453 TCGType base_type:8; 454 TCGType type:8; 455 TCGTempKind kind:3; 456 unsigned int indirect_reg:1; 457 unsigned int indirect_base:1; 458 unsigned int mem_coherent:1; 459 unsigned int mem_allocated:1; 460 unsigned int temp_allocated:1; 461 unsigned int temp_subindex:1; 462 463 int64_t val; 464 struct TCGTemp *mem_base; 465 intptr_t mem_offset; 466 const char *name; 467 468 /* Pass-specific information that can be stored for a temporary. 469 One word worth of integer data, and one pointer to data 470 allocated separately. */ 471 uintptr_t state; 472 void *state_ptr; 473 } TCGTemp; 474 475 typedef struct TCGContext TCGContext; 476 477 typedef struct TCGTempSet { 478 unsigned long l[BITS_TO_LONGS(TCG_MAX_TEMPS)]; 479 } TCGTempSet; 480 481 /* 482 * With 1 128-bit output, a 32-bit host requires 4 output parameters, 483 * which leaves a maximum of 28 other slots. Which is enough for 7 484 * 128-bit operands. 485 */ 486 #define DEAD_ARG (1 << 4) 487 #define SYNC_ARG (1 << 0) 488 typedef uint32_t TCGLifeData; 489 490 struct TCGOp { 491 TCGOpcode opc : 8; 492 unsigned nargs : 8; 493 494 /* Parameters for this opcode. See below. */ 495 unsigned param1 : 8; 496 unsigned param2 : 8; 497 498 /* Lifetime data of the operands. */ 499 TCGLifeData life; 500 501 /* Next and previous opcodes. */ 502 QTAILQ_ENTRY(TCGOp) link; 503 504 /* Register preferences for the output(s). */ 505 TCGRegSet output_pref[2]; 506 507 /* Arguments for the opcode. */ 508 TCGArg args[]; 509 }; 510 511 #define TCGOP_CALLI(X) (X)->param1 512 #define TCGOP_CALLO(X) (X)->param2 513 514 #define TCGOP_VECL(X) (X)->param1 515 #define TCGOP_VECE(X) (X)->param2 516 517 /* Make sure operands fit in the bitfields above. */ 518 QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8)); 519 520 static inline TCGRegSet output_pref(const TCGOp *op, unsigned i) 521 { 522 return i < ARRAY_SIZE(op->output_pref) ? op->output_pref[i] : 0; 523 } 524 525 typedef struct TCGProfile { 526 int64_t cpu_exec_time; 527 int64_t tb_count1; 528 int64_t tb_count; 529 int64_t op_count; /* total insn count */ 530 int op_count_max; /* max insn per TB */ 531 int temp_count_max; 532 int64_t temp_count; 533 int64_t del_op_count; 534 int64_t code_in_len; 535 int64_t code_out_len; 536 int64_t search_out_len; 537 int64_t interm_time; 538 int64_t code_time; 539 int64_t la_time; 540 int64_t opt_time; 541 int64_t restore_count; 542 int64_t restore_time; 543 int64_t table_op_count[NB_OPS]; 544 } TCGProfile; 545 546 struct TCGContext { 547 uint8_t *pool_cur, *pool_end; 548 TCGPool *pool_first, *pool_current, *pool_first_large; 549 int nb_labels; 550 int nb_globals; 551 int nb_temps; 552 int nb_indirects; 553 int nb_ops; 554 TCGType addr_type; /* TCG_TYPE_I32 or TCG_TYPE_I64 */ 555 556 #ifdef CONFIG_SOFTMMU 557 int page_mask; 558 uint8_t page_bits; 559 uint8_t tlb_dyn_max_bits; 560 #endif 561 562 TCGRegSet reserved_regs; 563 intptr_t current_frame_offset; 564 intptr_t frame_start; 565 intptr_t frame_end; 566 TCGTemp *frame_temp; 567 568 TranslationBlock *gen_tb; /* tb for which code is being generated */ 569 tcg_insn_unit *code_buf; /* pointer for start of tb */ 570 tcg_insn_unit *code_ptr; /* pointer for running end of tb */ 571 572 #ifdef CONFIG_PROFILER 573 TCGProfile prof; 574 #endif 575 576 #ifdef CONFIG_DEBUG_TCG 577 int goto_tb_issue_mask; 578 const TCGOpcode *vecop_list; 579 #endif 580 581 /* Code generation. Note that we specifically do not use tcg_insn_unit 582 here, because there's too much arithmetic throughout that relies 583 on addition and subtraction working on bytes. Rely on the GCC 584 extension that allows arithmetic on void*. */ 585 void *code_gen_buffer; 586 size_t code_gen_buffer_size; 587 void *code_gen_ptr; 588 void *data_gen_ptr; 589 590 /* Threshold to flush the translated code buffer. */ 591 void *code_gen_highwater; 592 593 /* Track which vCPU triggers events */ 594 CPUState *cpu; /* *_trans */ 595 596 /* These structures are private to tcg-target.c.inc. */ 597 #ifdef TCG_TARGET_NEED_LDST_LABELS 598 QSIMPLEQ_HEAD(, TCGLabelQemuLdst) ldst_labels; 599 #endif 600 #ifdef TCG_TARGET_NEED_POOL_LABELS 601 struct TCGLabelPoolData *pool_labels; 602 #endif 603 604 TCGLabel *exitreq_label; 605 606 #ifdef CONFIG_PLUGIN 607 /* 608 * We keep one plugin_tb struct per TCGContext. Note that on every TB 609 * translation we clear but do not free its contents; this way we 610 * avoid a lot of malloc/free churn, since after a few TB's it's 611 * unlikely that we'll need to allocate either more instructions or more 612 * space for instructions (for variable-instruction-length ISAs). 613 */ 614 struct qemu_plugin_tb *plugin_tb; 615 616 /* descriptor of the instruction being translated */ 617 struct qemu_plugin_insn *plugin_insn; 618 #endif 619 620 GHashTable *const_table[TCG_TYPE_COUNT]; 621 TCGTempSet free_temps[TCG_TYPE_COUNT]; 622 TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */ 623 624 QTAILQ_HEAD(, TCGOp) ops, free_ops; 625 QSIMPLEQ_HEAD(, TCGLabel) labels; 626 627 /* Tells which temporary holds a given register. 628 It does not take into account fixed registers */ 629 TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS]; 630 631 uint16_t gen_insn_end_off[TCG_MAX_INSNS]; 632 uint64_t gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS]; 633 634 /* Exit to translator on overflow. */ 635 sigjmp_buf jmp_trans; 636 }; 637 638 static inline bool temp_readonly(TCGTemp *ts) 639 { 640 return ts->kind >= TEMP_FIXED; 641 } 642 643 extern __thread TCGContext *tcg_ctx; 644 extern const void *tcg_code_gen_epilogue; 645 extern uintptr_t tcg_splitwx_diff; 646 extern TCGv_env cpu_env; 647 648 bool in_code_gen_buffer(const void *p); 649 650 #ifdef CONFIG_DEBUG_TCG 651 const void *tcg_splitwx_to_rx(void *rw); 652 void *tcg_splitwx_to_rw(const void *rx); 653 #else 654 static inline const void *tcg_splitwx_to_rx(void *rw) 655 { 656 return rw ? rw + tcg_splitwx_diff : NULL; 657 } 658 659 static inline void *tcg_splitwx_to_rw(const void *rx) 660 { 661 return rx ? (void *)rx - tcg_splitwx_diff : NULL; 662 } 663 #endif 664 665 static inline size_t temp_idx(TCGTemp *ts) 666 { 667 ptrdiff_t n = ts - tcg_ctx->temps; 668 tcg_debug_assert(n >= 0 && n < tcg_ctx->nb_temps); 669 return n; 670 } 671 672 static inline TCGArg temp_arg(TCGTemp *ts) 673 { 674 return (uintptr_t)ts; 675 } 676 677 static inline TCGTemp *arg_temp(TCGArg a) 678 { 679 return (TCGTemp *)(uintptr_t)a; 680 } 681 682 /* Using the offset of a temporary, relative to TCGContext, rather than 683 its index means that we don't use 0. That leaves offset 0 free for 684 a NULL representation without having to leave index 0 unused. */ 685 static inline TCGTemp *tcgv_i32_temp(TCGv_i32 v) 686 { 687 uintptr_t o = (uintptr_t)v; 688 TCGTemp *t = (void *)tcg_ctx + o; 689 tcg_debug_assert(offsetof(TCGContext, temps[temp_idx(t)]) == o); 690 return t; 691 } 692 693 static inline TCGTemp *tcgv_i64_temp(TCGv_i64 v) 694 { 695 return tcgv_i32_temp((TCGv_i32)v); 696 } 697 698 static inline TCGTemp *tcgv_i128_temp(TCGv_i128 v) 699 { 700 return tcgv_i32_temp((TCGv_i32)v); 701 } 702 703 static inline TCGTemp *tcgv_ptr_temp(TCGv_ptr v) 704 { 705 return tcgv_i32_temp((TCGv_i32)v); 706 } 707 708 static inline TCGTemp *tcgv_vec_temp(TCGv_vec v) 709 { 710 return tcgv_i32_temp((TCGv_i32)v); 711 } 712 713 static inline TCGArg tcgv_i32_arg(TCGv_i32 v) 714 { 715 return temp_arg(tcgv_i32_temp(v)); 716 } 717 718 static inline TCGArg tcgv_i64_arg(TCGv_i64 v) 719 { 720 return temp_arg(tcgv_i64_temp(v)); 721 } 722 723 static inline TCGArg tcgv_i128_arg(TCGv_i128 v) 724 { 725 return temp_arg(tcgv_i128_temp(v)); 726 } 727 728 static inline TCGArg tcgv_ptr_arg(TCGv_ptr v) 729 { 730 return temp_arg(tcgv_ptr_temp(v)); 731 } 732 733 static inline TCGArg tcgv_vec_arg(TCGv_vec v) 734 { 735 return temp_arg(tcgv_vec_temp(v)); 736 } 737 738 static inline TCGv_i32 temp_tcgv_i32(TCGTemp *t) 739 { 740 (void)temp_idx(t); /* trigger embedded assert */ 741 return (TCGv_i32)((void *)t - (void *)tcg_ctx); 742 } 743 744 static inline TCGv_i64 temp_tcgv_i64(TCGTemp *t) 745 { 746 return (TCGv_i64)temp_tcgv_i32(t); 747 } 748 749 static inline TCGv_i128 temp_tcgv_i128(TCGTemp *t) 750 { 751 return (TCGv_i128)temp_tcgv_i32(t); 752 } 753 754 static inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t) 755 { 756 return (TCGv_ptr)temp_tcgv_i32(t); 757 } 758 759 static inline TCGv_vec temp_tcgv_vec(TCGTemp *t) 760 { 761 return (TCGv_vec)temp_tcgv_i32(t); 762 } 763 764 static inline TCGArg tcg_get_insn_param(TCGOp *op, int arg) 765 { 766 return op->args[arg]; 767 } 768 769 static inline void tcg_set_insn_param(TCGOp *op, int arg, TCGArg v) 770 { 771 op->args[arg] = v; 772 } 773 774 static inline uint64_t tcg_get_insn_start_param(TCGOp *op, int arg) 775 { 776 if (TCG_TARGET_REG_BITS == 64) { 777 return tcg_get_insn_param(op, arg); 778 } else { 779 return deposit64(tcg_get_insn_param(op, arg * 2), 32, 32, 780 tcg_get_insn_param(op, arg * 2 + 1)); 781 } 782 } 783 784 static inline void tcg_set_insn_start_param(TCGOp *op, int arg, uint64_t v) 785 { 786 if (TCG_TARGET_REG_BITS == 64) { 787 tcg_set_insn_param(op, arg, v); 788 } else { 789 tcg_set_insn_param(op, arg * 2, v); 790 tcg_set_insn_param(op, arg * 2 + 1, v >> 32); 791 } 792 } 793 794 /* The last op that was emitted. */ 795 static inline TCGOp *tcg_last_op(void) 796 { 797 return QTAILQ_LAST(&tcg_ctx->ops); 798 } 799 800 /* Test for whether to terminate the TB for using too many opcodes. */ 801 static inline bool tcg_op_buf_full(void) 802 { 803 /* This is not a hard limit, it merely stops translation when 804 * we have produced "enough" opcodes. We want to limit TB size 805 * such that a RISC host can reasonably use a 16-bit signed 806 * branch within the TB. We also need to be mindful of the 807 * 16-bit unsigned offsets, TranslationBlock.jmp_reset_offset[] 808 * and TCGContext.gen_insn_end_off[]. 809 */ 810 return tcg_ctx->nb_ops >= 4000; 811 } 812 813 /* pool based memory allocation */ 814 815 /* user-mode: mmap_lock must be held for tcg_malloc_internal. */ 816 void *tcg_malloc_internal(TCGContext *s, int size); 817 void tcg_pool_reset(TCGContext *s); 818 TranslationBlock *tcg_tb_alloc(TCGContext *s); 819 820 void tcg_region_reset_all(void); 821 822 size_t tcg_code_size(void); 823 size_t tcg_code_capacity(void); 824 825 void tcg_tb_insert(TranslationBlock *tb); 826 void tcg_tb_remove(TranslationBlock *tb); 827 TranslationBlock *tcg_tb_lookup(uintptr_t tc_ptr); 828 void tcg_tb_foreach(GTraverseFunc func, gpointer user_data); 829 size_t tcg_nb_tbs(void); 830 831 /* user-mode: Called with mmap_lock held. */ 832 static inline void *tcg_malloc(int size) 833 { 834 TCGContext *s = tcg_ctx; 835 uint8_t *ptr, *ptr_end; 836 837 /* ??? This is a weak placeholder for minimum malloc alignment. */ 838 size = QEMU_ALIGN_UP(size, 8); 839 840 ptr = s->pool_cur; 841 ptr_end = ptr + size; 842 if (unlikely(ptr_end > s->pool_end)) { 843 return tcg_malloc_internal(tcg_ctx, size); 844 } else { 845 s->pool_cur = ptr_end; 846 return ptr; 847 } 848 } 849 850 void tcg_init(size_t tb_size, int splitwx, unsigned max_cpus); 851 void tcg_register_thread(void); 852 void tcg_prologue_init(TCGContext *s); 853 void tcg_func_start(TCGContext *s); 854 855 int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start); 856 857 void tb_target_set_jmp_target(const TranslationBlock *, int, 858 uintptr_t, uintptr_t); 859 860 void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size); 861 862 TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr, 863 intptr_t, const char *); 864 TCGTemp *tcg_temp_new_internal(TCGType, TCGTempKind); 865 TCGv_vec tcg_temp_new_vec(TCGType type); 866 TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match); 867 868 static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset, 869 const char *name) 870 { 871 TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name); 872 return temp_tcgv_i32(t); 873 } 874 875 static inline TCGv_i32 tcg_temp_new_i32(void) 876 { 877 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, TEMP_TB); 878 return temp_tcgv_i32(t); 879 } 880 881 static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset, 882 const char *name) 883 { 884 TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name); 885 return temp_tcgv_i64(t); 886 } 887 888 static inline TCGv_i64 tcg_temp_new_i64(void) 889 { 890 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, TEMP_TB); 891 return temp_tcgv_i64(t); 892 } 893 894 static inline TCGv_i128 tcg_temp_new_i128(void) 895 { 896 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I128, TEMP_TB); 897 return temp_tcgv_i128(t); 898 } 899 900 static inline TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t offset, 901 const char *name) 902 { 903 TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_PTR, reg, offset, name); 904 return temp_tcgv_ptr(t); 905 } 906 907 static inline TCGv_ptr tcg_temp_new_ptr(void) 908 { 909 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, TEMP_TB); 910 return temp_tcgv_ptr(t); 911 } 912 913 int64_t tcg_cpu_exec_time(void); 914 void tcg_dump_info(GString *buf); 915 void tcg_dump_op_count(GString *buf); 916 917 #define TCG_CT_CONST 1 /* any constant of register size */ 918 919 typedef struct TCGArgConstraint { 920 unsigned ct : 16; 921 unsigned alias_index : 4; 922 unsigned sort_index : 4; 923 unsigned pair_index : 4; 924 unsigned pair : 2; /* 0: none, 1: first, 2: second, 3: second alias */ 925 bool oalias : 1; 926 bool ialias : 1; 927 bool newreg : 1; 928 TCGRegSet regs; 929 } TCGArgConstraint; 930 931 #define TCG_MAX_OP_ARGS 16 932 933 /* Bits for TCGOpDef->flags, 8 bits available, all used. */ 934 enum { 935 /* Instruction exits the translation block. */ 936 TCG_OPF_BB_EXIT = 0x01, 937 /* Instruction defines the end of a basic block. */ 938 TCG_OPF_BB_END = 0x02, 939 /* Instruction clobbers call registers and potentially update globals. */ 940 TCG_OPF_CALL_CLOBBER = 0x04, 941 /* Instruction has side effects: it cannot be removed if its outputs 942 are not used, and might trigger exceptions. */ 943 TCG_OPF_SIDE_EFFECTS = 0x08, 944 /* Instruction operands are 64-bits (otherwise 32-bits). */ 945 TCG_OPF_64BIT = 0x10, 946 /* Instruction is optional and not implemented by the host, or insn 947 is generic and should not be implemened by the host. */ 948 TCG_OPF_NOT_PRESENT = 0x20, 949 /* Instruction operands are vectors. */ 950 TCG_OPF_VECTOR = 0x40, 951 /* Instruction is a conditional branch. */ 952 TCG_OPF_COND_BRANCH = 0x80 953 }; 954 955 typedef struct TCGOpDef { 956 const char *name; 957 uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args; 958 uint8_t flags; 959 TCGArgConstraint *args_ct; 960 } TCGOpDef; 961 962 extern TCGOpDef tcg_op_defs[]; 963 extern const size_t tcg_op_defs_max; 964 965 typedef struct TCGTargetOpDef { 966 TCGOpcode op; 967 const char *args_ct_str[TCG_MAX_OP_ARGS]; 968 } TCGTargetOpDef; 969 970 bool tcg_op_supported(TCGOpcode op); 971 972 void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args); 973 974 TCGOp *tcg_emit_op(TCGOpcode opc, unsigned nargs); 975 void tcg_op_remove(TCGContext *s, TCGOp *op); 976 TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *op, 977 TCGOpcode opc, unsigned nargs); 978 TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *op, 979 TCGOpcode opc, unsigned nargs); 980 981 /** 982 * tcg_remove_ops_after: 983 * @op: target operation 984 * 985 * Discard any opcodes emitted since @op. Expected usage is to save 986 * a starting point with tcg_last_op(), speculatively emit opcodes, 987 * then decide whether or not to keep those opcodes after the fact. 988 */ 989 void tcg_remove_ops_after(TCGOp *op); 990 991 void tcg_optimize(TCGContext *s); 992 993 /* 994 * Locate or create a read-only temporary that is a constant. 995 * This kind of temporary need not be freed, but for convenience 996 * will be silently ignored by tcg_temp_free_*. 997 */ 998 TCGTemp *tcg_constant_internal(TCGType type, int64_t val); 999 1000 static inline TCGv_i32 tcg_constant_i32(int32_t val) 1001 { 1002 return temp_tcgv_i32(tcg_constant_internal(TCG_TYPE_I32, val)); 1003 } 1004 1005 static inline TCGv_i64 tcg_constant_i64(int64_t val) 1006 { 1007 return temp_tcgv_i64(tcg_constant_internal(TCG_TYPE_I64, val)); 1008 } 1009 1010 TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val); 1011 TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t val); 1012 1013 #if UINTPTR_MAX == UINT32_MAX 1014 # define tcg_constant_ptr(x) ((TCGv_ptr)tcg_constant_i32((intptr_t)(x))) 1015 #else 1016 # define tcg_constant_ptr(x) ((TCGv_ptr)tcg_constant_i64((intptr_t)(x))) 1017 #endif 1018 1019 TCGLabel *gen_new_label(void); 1020 1021 /** 1022 * label_arg 1023 * @l: label 1024 * 1025 * Encode a label for storage in the TCG opcode stream. 1026 */ 1027 1028 static inline TCGArg label_arg(TCGLabel *l) 1029 { 1030 return (uintptr_t)l; 1031 } 1032 1033 /** 1034 * arg_label 1035 * @i: value 1036 * 1037 * The opposite of label_arg. Retrieve a label from the 1038 * encoding of the TCG opcode stream. 1039 */ 1040 1041 static inline TCGLabel *arg_label(TCGArg i) 1042 { 1043 return (TCGLabel *)(uintptr_t)i; 1044 } 1045 1046 /** 1047 * tcg_ptr_byte_diff 1048 * @a, @b: addresses to be differenced 1049 * 1050 * There are many places within the TCG backends where we need a byte 1051 * difference between two pointers. While this can be accomplished 1052 * with local casting, it's easy to get wrong -- especially if one is 1053 * concerned with the signedness of the result. 1054 * 1055 * This version relies on GCC's void pointer arithmetic to get the 1056 * correct result. 1057 */ 1058 1059 static inline ptrdiff_t tcg_ptr_byte_diff(const void *a, const void *b) 1060 { 1061 return a - b; 1062 } 1063 1064 /** 1065 * tcg_pcrel_diff 1066 * @s: the tcg context 1067 * @target: address of the target 1068 * 1069 * Produce a pc-relative difference, from the current code_ptr 1070 * to the destination address. 1071 */ 1072 1073 static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, const void *target) 1074 { 1075 return tcg_ptr_byte_diff(target, tcg_splitwx_to_rx(s->code_ptr)); 1076 } 1077 1078 /** 1079 * tcg_tbrel_diff 1080 * @s: the tcg context 1081 * @target: address of the target 1082 * 1083 * Produce a difference, from the beginning of the current TB code 1084 * to the destination address. 1085 */ 1086 static inline ptrdiff_t tcg_tbrel_diff(TCGContext *s, const void *target) 1087 { 1088 return tcg_ptr_byte_diff(target, tcg_splitwx_to_rx(s->code_buf)); 1089 } 1090 1091 /** 1092 * tcg_current_code_size 1093 * @s: the tcg context 1094 * 1095 * Compute the current code size within the translation block. 1096 * This is used to fill in qemu's data structures for goto_tb. 1097 */ 1098 1099 static inline size_t tcg_current_code_size(TCGContext *s) 1100 { 1101 return tcg_ptr_byte_diff(s->code_ptr, s->code_buf); 1102 } 1103 1104 /** 1105 * tcg_qemu_tb_exec: 1106 * @env: pointer to CPUArchState for the CPU 1107 * @tb_ptr: address of generated code for the TB to execute 1108 * 1109 * Start executing code from a given translation block. 1110 * Where translation blocks have been linked, execution 1111 * may proceed from the given TB into successive ones. 1112 * Control eventually returns only when some action is needed 1113 * from the top-level loop: either control must pass to a TB 1114 * which has not yet been directly linked, or an asynchronous 1115 * event such as an interrupt needs handling. 1116 * 1117 * Return: The return value is the value passed to the corresponding 1118 * tcg_gen_exit_tb() at translation time of the last TB attempted to execute. 1119 * The value is either zero or a 4-byte aligned pointer to that TB combined 1120 * with additional information in its two least significant bits. The 1121 * additional information is encoded as follows: 1122 * 0, 1: the link between this TB and the next is via the specified 1123 * TB index (0 or 1). That is, we left the TB via (the equivalent 1124 * of) "goto_tb <index>". The main loop uses this to determine 1125 * how to link the TB just executed to the next. 1126 * 2: we are using instruction counting code generation, and we 1127 * did not start executing this TB because the instruction counter 1128 * would hit zero midway through it. In this case the pointer 1129 * returned is the TB we were about to execute, and the caller must 1130 * arrange to execute the remaining count of instructions. 1131 * 3: we stopped because the CPU's exit_request flag was set 1132 * (usually meaning that there is an interrupt that needs to be 1133 * handled). The pointer returned is the TB we were about to execute 1134 * when we noticed the pending exit request. 1135 * 1136 * If the bottom two bits indicate an exit-via-index then the CPU 1137 * state is correctly synchronised and ready for execution of the next 1138 * TB (and in particular the guest PC is the address to execute next). 1139 * Otherwise, we gave up on execution of this TB before it started, and 1140 * the caller must fix up the CPU state by calling the CPU's 1141 * synchronize_from_tb() method with the TB pointer we return (falling 1142 * back to calling the CPU's set_pc method with tb->pb if no 1143 * synchronize_from_tb() method exists). 1144 * 1145 * Note that TCG targets may use a different definition of tcg_qemu_tb_exec 1146 * to this default (which just calls the prologue.code emitted by 1147 * tcg_target_qemu_prologue()). 1148 */ 1149 #define TB_EXIT_MASK 3 1150 #define TB_EXIT_IDX0 0 1151 #define TB_EXIT_IDX1 1 1152 #define TB_EXIT_IDXMAX 1 1153 #define TB_EXIT_REQUESTED 3 1154 1155 #ifdef CONFIG_TCG_INTERPRETER 1156 uintptr_t tcg_qemu_tb_exec(CPUArchState *env, const void *tb_ptr); 1157 #else 1158 typedef uintptr_t tcg_prologue_fn(CPUArchState *env, const void *tb_ptr); 1159 extern tcg_prologue_fn *tcg_qemu_tb_exec; 1160 #endif 1161 1162 void tcg_register_jit(const void *buf, size_t buf_size); 1163 1164 #if TCG_TARGET_MAYBE_vec 1165 /* Return zero if the tuple (opc, type, vece) is unsupportable; 1166 return > 0 if it is directly supportable; 1167 return < 0 if we must call tcg_expand_vec_op. */ 1168 int tcg_can_emit_vec_op(TCGOpcode, TCGType, unsigned); 1169 #else 1170 static inline int tcg_can_emit_vec_op(TCGOpcode o, TCGType t, unsigned ve) 1171 { 1172 return 0; 1173 } 1174 #endif 1175 1176 /* Expand the tuple (opc, type, vece) on the given arguments. */ 1177 void tcg_expand_vec_op(TCGOpcode, TCGType, unsigned, TCGArg, ...); 1178 1179 /* Replicate a constant C accoring to the log2 of the element size. */ 1180 uint64_t dup_const(unsigned vece, uint64_t c); 1181 1182 #define dup_const(VECE, C) \ 1183 (__builtin_constant_p(VECE) \ 1184 ? ( (VECE) == MO_8 ? 0x0101010101010101ull * (uint8_t)(C) \ 1185 : (VECE) == MO_16 ? 0x0001000100010001ull * (uint16_t)(C) \ 1186 : (VECE) == MO_32 ? 0x0000000100000001ull * (uint32_t)(C) \ 1187 : (VECE) == MO_64 ? (uint64_t)(C) \ 1188 : (qemu_build_not_reached_always(), 0)) \ 1189 : dup_const(VECE, C)) 1190 1191 #if TARGET_LONG_BITS == 64 1192 # define dup_const_tl dup_const 1193 #else 1194 # define dup_const_tl(VECE, C) \ 1195 (__builtin_constant_p(VECE) \ 1196 ? ( (VECE) == MO_8 ? 0x01010101ul * (uint8_t)(C) \ 1197 : (VECE) == MO_16 ? 0x00010001ul * (uint16_t)(C) \ 1198 : (VECE) == MO_32 ? 0x00000001ul * (uint32_t)(C) \ 1199 : (qemu_build_not_reached_always(), 0)) \ 1200 : (target_long)dup_const(VECE, C)) 1201 #endif 1202 1203 #ifdef CONFIG_DEBUG_TCG 1204 void tcg_assert_listed_vecop(TCGOpcode); 1205 #else 1206 static inline void tcg_assert_listed_vecop(TCGOpcode op) { } 1207 #endif 1208 1209 static inline const TCGOpcode *tcg_swap_vecop_list(const TCGOpcode *n) 1210 { 1211 #ifdef CONFIG_DEBUG_TCG 1212 const TCGOpcode *o = tcg_ctx->vecop_list; 1213 tcg_ctx->vecop_list = n; 1214 return o; 1215 #else 1216 return NULL; 1217 #endif 1218 } 1219 1220 bool tcg_can_emit_vecop_list(const TCGOpcode *, TCGType, unsigned); 1221 1222 #endif /* TCG_H */ 1223