1 /* 2 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 3 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License, version 2, as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 17 */ 18 19 #ifndef __ARM_KVM_H__ 20 #define __ARM_KVM_H__ 21 22 #include <linux/types.h> 23 #include <linux/psci.h> 24 #include <asm/ptrace.h> 25 26 #define __KVM_HAVE_GUEST_DEBUG 27 #define __KVM_HAVE_IRQ_LINE 28 #define __KVM_HAVE_READONLY_MEM 29 30 #define KVM_REG_SIZE(id) \ 31 (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT)) 32 33 /* Valid for svc_regs, abt_regs, und_regs, irq_regs in struct kvm_regs */ 34 #define KVM_ARM_SVC_sp svc_regs[0] 35 #define KVM_ARM_SVC_lr svc_regs[1] 36 #define KVM_ARM_SVC_spsr svc_regs[2] 37 #define KVM_ARM_ABT_sp abt_regs[0] 38 #define KVM_ARM_ABT_lr abt_regs[1] 39 #define KVM_ARM_ABT_spsr abt_regs[2] 40 #define KVM_ARM_UND_sp und_regs[0] 41 #define KVM_ARM_UND_lr und_regs[1] 42 #define KVM_ARM_UND_spsr und_regs[2] 43 #define KVM_ARM_IRQ_sp irq_regs[0] 44 #define KVM_ARM_IRQ_lr irq_regs[1] 45 #define KVM_ARM_IRQ_spsr irq_regs[2] 46 47 /* Valid only for fiq_regs in struct kvm_regs */ 48 #define KVM_ARM_FIQ_r8 fiq_regs[0] 49 #define KVM_ARM_FIQ_r9 fiq_regs[1] 50 #define KVM_ARM_FIQ_r10 fiq_regs[2] 51 #define KVM_ARM_FIQ_fp fiq_regs[3] 52 #define KVM_ARM_FIQ_ip fiq_regs[4] 53 #define KVM_ARM_FIQ_sp fiq_regs[5] 54 #define KVM_ARM_FIQ_lr fiq_regs[6] 55 #define KVM_ARM_FIQ_spsr fiq_regs[7] 56 57 struct kvm_regs { 58 struct pt_regs usr_regs; /* R0_usr - R14_usr, PC, CPSR */ 59 unsigned long svc_regs[3]; /* SP_svc, LR_svc, SPSR_svc */ 60 unsigned long abt_regs[3]; /* SP_abt, LR_abt, SPSR_abt */ 61 unsigned long und_regs[3]; /* SP_und, LR_und, SPSR_und */ 62 unsigned long irq_regs[3]; /* SP_irq, LR_irq, SPSR_irq */ 63 unsigned long fiq_regs[8]; /* R8_fiq - R14_fiq, SPSR_fiq */ 64 }; 65 66 /* Supported Processor Types */ 67 #define KVM_ARM_TARGET_CORTEX_A15 0 68 #define KVM_ARM_TARGET_CORTEX_A7 1 69 #define KVM_ARM_NUM_TARGETS 2 70 71 /* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */ 72 #define KVM_ARM_DEVICE_TYPE_SHIFT 0 73 #define KVM_ARM_DEVICE_TYPE_MASK (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT) 74 #define KVM_ARM_DEVICE_ID_SHIFT 16 75 #define KVM_ARM_DEVICE_ID_MASK (0xffff << KVM_ARM_DEVICE_ID_SHIFT) 76 77 /* Supported device IDs */ 78 #define KVM_ARM_DEVICE_VGIC_V2 0 79 80 /* Supported VGIC address types */ 81 #define KVM_VGIC_V2_ADDR_TYPE_DIST 0 82 #define KVM_VGIC_V2_ADDR_TYPE_CPU 1 83 84 #define KVM_VGIC_V2_DIST_SIZE 0x1000 85 #define KVM_VGIC_V2_CPU_SIZE 0x2000 86 87 /* Supported VGICv3 address types */ 88 #define KVM_VGIC_V3_ADDR_TYPE_DIST 2 89 #define KVM_VGIC_V3_ADDR_TYPE_REDIST 3 90 #define KVM_VGIC_ITS_ADDR_TYPE 4 91 92 #define KVM_VGIC_V3_DIST_SIZE SZ_64K 93 #define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K) 94 #define KVM_VGIC_V3_ITS_SIZE (2 * SZ_64K) 95 96 #define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */ 97 #define KVM_ARM_VCPU_PSCI_0_2 1 /* CPU uses PSCI v0.2 */ 98 99 struct kvm_vcpu_init { 100 __u32 target; 101 __u32 features[7]; 102 }; 103 104 struct kvm_sregs { 105 }; 106 107 struct kvm_fpu { 108 }; 109 110 struct kvm_guest_debug_arch { 111 }; 112 113 struct kvm_debug_exit_arch { 114 }; 115 116 struct kvm_sync_regs { 117 }; 118 119 struct kvm_arch_memory_slot { 120 }; 121 122 /* If you need to interpret the index values, here is the key: */ 123 #define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000 124 #define KVM_REG_ARM_COPROC_SHIFT 16 125 #define KVM_REG_ARM_32_OPC2_MASK 0x0000000000000007 126 #define KVM_REG_ARM_32_OPC2_SHIFT 0 127 #define KVM_REG_ARM_OPC1_MASK 0x0000000000000078 128 #define KVM_REG_ARM_OPC1_SHIFT 3 129 #define KVM_REG_ARM_CRM_MASK 0x0000000000000780 130 #define KVM_REG_ARM_CRM_SHIFT 7 131 #define KVM_REG_ARM_32_CRN_MASK 0x0000000000007800 132 #define KVM_REG_ARM_32_CRN_SHIFT 11 133 134 #define ARM_CP15_REG_SHIFT_MASK(x,n) \ 135 (((x) << KVM_REG_ARM_ ## n ## _SHIFT) & KVM_REG_ARM_ ## n ## _MASK) 136 137 #define __ARM_CP15_REG(op1,crn,crm,op2) \ 138 (KVM_REG_ARM | (15 << KVM_REG_ARM_COPROC_SHIFT) | \ 139 ARM_CP15_REG_SHIFT_MASK(op1, OPC1) | \ 140 ARM_CP15_REG_SHIFT_MASK(crn, 32_CRN) | \ 141 ARM_CP15_REG_SHIFT_MASK(crm, CRM) | \ 142 ARM_CP15_REG_SHIFT_MASK(op2, 32_OPC2)) 143 144 #define ARM_CP15_REG32(...) (__ARM_CP15_REG(__VA_ARGS__) | KVM_REG_SIZE_U32) 145 146 #define __ARM_CP15_REG64(op1,crm) \ 147 (__ARM_CP15_REG(op1, 0, crm, 0) | KVM_REG_SIZE_U64) 148 #define ARM_CP15_REG64(...) __ARM_CP15_REG64(__VA_ARGS__) 149 150 #define KVM_REG_ARM_TIMER_CTL ARM_CP15_REG32(0, 14, 3, 1) 151 #define KVM_REG_ARM_TIMER_CNT ARM_CP15_REG64(1, 14) 152 #define KVM_REG_ARM_TIMER_CVAL ARM_CP15_REG64(3, 14) 153 154 /* Normal registers are mapped as coprocessor 16. */ 155 #define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT) 156 #define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / 4) 157 158 /* Some registers need more space to represent values. */ 159 #define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT) 160 #define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00 161 #define KVM_REG_ARM_DEMUX_ID_SHIFT 8 162 #define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT) 163 #define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF 164 #define KVM_REG_ARM_DEMUX_VAL_SHIFT 0 165 166 /* VFP registers: we could overload CP10 like ARM does, but that's ugly. */ 167 #define KVM_REG_ARM_VFP (0x0012 << KVM_REG_ARM_COPROC_SHIFT) 168 #define KVM_REG_ARM_VFP_MASK 0x000000000000FFFF 169 #define KVM_REG_ARM_VFP_BASE_REG 0x0 170 #define KVM_REG_ARM_VFP_FPSID 0x1000 171 #define KVM_REG_ARM_VFP_FPSCR 0x1001 172 #define KVM_REG_ARM_VFP_MVFR1 0x1006 173 #define KVM_REG_ARM_VFP_MVFR0 0x1007 174 #define KVM_REG_ARM_VFP_FPEXC 0x1008 175 #define KVM_REG_ARM_VFP_FPINST 0x1009 176 #define KVM_REG_ARM_VFP_FPINST2 0x100A 177 178 /* Device Control API: ARM VGIC */ 179 #define KVM_DEV_ARM_VGIC_GRP_ADDR 0 180 #define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1 181 #define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2 182 #define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32 183 #define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT) 184 #define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32 185 #define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \ 186 (0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT) 187 #define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0 188 #define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT) 189 #define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff) 190 #define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3 191 #define KVM_DEV_ARM_VGIC_GRP_CTRL 4 192 #define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5 193 #define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6 194 #define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7 195 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10 196 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \ 197 (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT) 198 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff 199 #define VGIC_LEVEL_INFO_LINE_LEVEL 0 200 201 #define KVM_DEV_ARM_VGIC_CTRL_INIT 0 202 203 /* KVM_IRQ_LINE irq field index values */ 204 #define KVM_ARM_IRQ_TYPE_SHIFT 24 205 #define KVM_ARM_IRQ_TYPE_MASK 0xff 206 #define KVM_ARM_IRQ_VCPU_SHIFT 16 207 #define KVM_ARM_IRQ_VCPU_MASK 0xff 208 #define KVM_ARM_IRQ_NUM_SHIFT 0 209 #define KVM_ARM_IRQ_NUM_MASK 0xffff 210 211 /* irq_type field */ 212 #define KVM_ARM_IRQ_TYPE_CPU 0 213 #define KVM_ARM_IRQ_TYPE_SPI 1 214 #define KVM_ARM_IRQ_TYPE_PPI 2 215 216 /* out-of-kernel GIC cpu interrupt injection irq_number field */ 217 #define KVM_ARM_IRQ_CPU_IRQ 0 218 #define KVM_ARM_IRQ_CPU_FIQ 1 219 220 /* 221 * This used to hold the highest supported SPI, but it is now obsolete 222 * and only here to provide source code level compatibility with older 223 * userland. The highest SPI number can be set via KVM_DEV_ARM_VGIC_GRP_NR_IRQS. 224 */ 225 #define KVM_ARM_IRQ_GIC_MAX 127 226 227 /* One single KVM irqchip, ie. the VGIC */ 228 #define KVM_NR_IRQCHIPS 1 229 230 /* PSCI interface */ 231 #define KVM_PSCI_FN_BASE 0x95c1ba5e 232 #define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n)) 233 234 #define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0) 235 #define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1) 236 #define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2) 237 #define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3) 238 239 #define KVM_PSCI_RET_SUCCESS PSCI_RET_SUCCESS 240 #define KVM_PSCI_RET_NI PSCI_RET_NOT_SUPPORTED 241 #define KVM_PSCI_RET_INVAL PSCI_RET_INVALID_PARAMS 242 #define KVM_PSCI_RET_DENIED PSCI_RET_DENIED 243 244 #endif /* __ARM_KVM_H__ */ 245