1 /* 2 * Copyright (C) 2012,2013 - ARM Ltd 3 * Author: Marc Zyngier <marc.zyngier@arm.com> 4 * 5 * Derived from arch/arm/include/uapi/asm/kvm.h: 6 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 7 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program. If not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #ifndef __ARM_KVM_H__ 23 #define __ARM_KVM_H__ 24 25 #define KVM_SPSR_EL1 0 26 #define KVM_SPSR_SVC KVM_SPSR_EL1 27 #define KVM_SPSR_ABT 1 28 #define KVM_SPSR_UND 2 29 #define KVM_SPSR_IRQ 3 30 #define KVM_SPSR_FIQ 4 31 #define KVM_NR_SPSR 5 32 33 #ifndef __ASSEMBLY__ 34 #include <linux/psci.h> 35 #include <linux/types.h> 36 #include <asm/ptrace.h> 37 38 #define __KVM_HAVE_GUEST_DEBUG 39 #define __KVM_HAVE_IRQ_LINE 40 #define __KVM_HAVE_READONLY_MEM 41 42 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 43 44 #define KVM_REG_SIZE(id) \ 45 (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT)) 46 47 struct kvm_regs { 48 struct user_pt_regs regs; /* sp = sp_el0 */ 49 50 __u64 sp_el1; 51 __u64 elr_el1; 52 53 __u64 spsr[KVM_NR_SPSR]; 54 55 struct user_fpsimd_state fp_regs; 56 }; 57 58 /* 59 * Supported CPU Targets - Adding a new target type is not recommended, 60 * unless there are some special registers not supported by the 61 * genericv8 syreg table. 62 */ 63 #define KVM_ARM_TARGET_AEM_V8 0 64 #define KVM_ARM_TARGET_FOUNDATION_V8 1 65 #define KVM_ARM_TARGET_CORTEX_A57 2 66 #define KVM_ARM_TARGET_XGENE_POTENZA 3 67 #define KVM_ARM_TARGET_CORTEX_A53 4 68 /* Generic ARM v8 target */ 69 #define KVM_ARM_TARGET_GENERIC_V8 5 70 71 #define KVM_ARM_NUM_TARGETS 6 72 73 /* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */ 74 #define KVM_ARM_DEVICE_TYPE_SHIFT 0 75 #define KVM_ARM_DEVICE_TYPE_MASK (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT) 76 #define KVM_ARM_DEVICE_ID_SHIFT 16 77 #define KVM_ARM_DEVICE_ID_MASK (0xffff << KVM_ARM_DEVICE_ID_SHIFT) 78 79 /* Supported device IDs */ 80 #define KVM_ARM_DEVICE_VGIC_V2 0 81 82 /* Supported VGIC address types */ 83 #define KVM_VGIC_V2_ADDR_TYPE_DIST 0 84 #define KVM_VGIC_V2_ADDR_TYPE_CPU 1 85 86 #define KVM_VGIC_V2_DIST_SIZE 0x1000 87 #define KVM_VGIC_V2_CPU_SIZE 0x2000 88 89 /* Supported VGICv3 address types */ 90 #define KVM_VGIC_V3_ADDR_TYPE_DIST 2 91 #define KVM_VGIC_V3_ADDR_TYPE_REDIST 3 92 #define KVM_VGIC_ITS_ADDR_TYPE 4 93 94 #define KVM_VGIC_V3_DIST_SIZE SZ_64K 95 #define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K) 96 #define KVM_VGIC_V3_ITS_SIZE (2 * SZ_64K) 97 98 #define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */ 99 #define KVM_ARM_VCPU_EL1_32BIT 1 /* CPU running a 32bit VM */ 100 #define KVM_ARM_VCPU_PSCI_0_2 2 /* CPU uses PSCI v0.2 */ 101 #define KVM_ARM_VCPU_PMU_V3 3 /* Support guest PMUv3 */ 102 103 struct kvm_vcpu_init { 104 __u32 target; 105 __u32 features[7]; 106 }; 107 108 struct kvm_sregs { 109 }; 110 111 struct kvm_fpu { 112 }; 113 114 /* 115 * See v8 ARM ARM D7.3: Debug Registers 116 * 117 * The architectural limit is 16 debug registers of each type although 118 * in practice there are usually less (see ID_AA64DFR0_EL1). 119 * 120 * Although the control registers are architecturally defined as 32 121 * bits wide we use a 64 bit structure here to keep parity with 122 * KVM_GET/SET_ONE_REG behaviour which treats all system registers as 123 * 64 bit values. It also allows for the possibility of the 124 * architecture expanding the control registers without having to 125 * change the userspace ABI. 126 */ 127 #define KVM_ARM_MAX_DBG_REGS 16 128 struct kvm_guest_debug_arch { 129 __u64 dbg_bcr[KVM_ARM_MAX_DBG_REGS]; 130 __u64 dbg_bvr[KVM_ARM_MAX_DBG_REGS]; 131 __u64 dbg_wcr[KVM_ARM_MAX_DBG_REGS]; 132 __u64 dbg_wvr[KVM_ARM_MAX_DBG_REGS]; 133 }; 134 135 struct kvm_debug_exit_arch { 136 __u32 hsr; 137 __u64 far; /* used for watchpoints */ 138 }; 139 140 /* 141 * Architecture specific defines for kvm_guest_debug->control 142 */ 143 144 #define KVM_GUESTDBG_USE_SW_BP (1 << 16) 145 #define KVM_GUESTDBG_USE_HW (1 << 17) 146 147 struct kvm_sync_regs { 148 /* Used with KVM_CAP_ARM_USER_IRQ */ 149 __u64 device_irq_level; 150 }; 151 152 struct kvm_arch_memory_slot { 153 }; 154 155 /* If you need to interpret the index values, here is the key: */ 156 #define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000 157 #define KVM_REG_ARM_COPROC_SHIFT 16 158 159 /* Normal registers are mapped as coprocessor 16. */ 160 #define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT) 161 #define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / sizeof(__u32)) 162 163 /* Some registers need more space to represent values. */ 164 #define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT) 165 #define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00 166 #define KVM_REG_ARM_DEMUX_ID_SHIFT 8 167 #define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT) 168 #define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF 169 #define KVM_REG_ARM_DEMUX_VAL_SHIFT 0 170 171 /* AArch64 system registers */ 172 #define KVM_REG_ARM64_SYSREG (0x0013 << KVM_REG_ARM_COPROC_SHIFT) 173 #define KVM_REG_ARM64_SYSREG_OP0_MASK 0x000000000000c000 174 #define KVM_REG_ARM64_SYSREG_OP0_SHIFT 14 175 #define KVM_REG_ARM64_SYSREG_OP1_MASK 0x0000000000003800 176 #define KVM_REG_ARM64_SYSREG_OP1_SHIFT 11 177 #define KVM_REG_ARM64_SYSREG_CRN_MASK 0x0000000000000780 178 #define KVM_REG_ARM64_SYSREG_CRN_SHIFT 7 179 #define KVM_REG_ARM64_SYSREG_CRM_MASK 0x0000000000000078 180 #define KVM_REG_ARM64_SYSREG_CRM_SHIFT 3 181 #define KVM_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007 182 #define KVM_REG_ARM64_SYSREG_OP2_SHIFT 0 183 184 #define ARM64_SYS_REG_SHIFT_MASK(x,n) \ 185 (((x) << KVM_REG_ARM64_SYSREG_ ## n ## _SHIFT) & \ 186 KVM_REG_ARM64_SYSREG_ ## n ## _MASK) 187 188 #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \ 189 (KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | \ 190 ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \ 191 ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \ 192 ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \ 193 ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \ 194 ARM64_SYS_REG_SHIFT_MASK(op2, OP2)) 195 196 #define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) | KVM_REG_SIZE_U64) 197 198 #define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1) 199 #define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2) 200 #define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2) 201 202 /* Device Control API: ARM VGIC */ 203 #define KVM_DEV_ARM_VGIC_GRP_ADDR 0 204 #define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1 205 #define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2 206 #define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32 207 #define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT) 208 #define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32 209 #define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \ 210 (0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT) 211 #define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0 212 #define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT) 213 #define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff) 214 #define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3 215 #define KVM_DEV_ARM_VGIC_GRP_CTRL 4 216 #define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5 217 #define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6 218 #define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7 219 #define KVM_DEV_ARM_VGIC_GRP_ITS_REGS 8 220 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10 221 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \ 222 (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT) 223 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff 224 #define VGIC_LEVEL_INFO_LINE_LEVEL 0 225 226 #define KVM_DEV_ARM_VGIC_CTRL_INIT 0 227 #define KVM_DEV_ARM_ITS_SAVE_TABLES 1 228 #define KVM_DEV_ARM_ITS_RESTORE_TABLES 2 229 #define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3 230 231 /* Device Control API on vcpu fd */ 232 #define KVM_ARM_VCPU_PMU_V3_CTRL 0 233 #define KVM_ARM_VCPU_PMU_V3_IRQ 0 234 #define KVM_ARM_VCPU_PMU_V3_INIT 1 235 #define KVM_ARM_VCPU_TIMER_CTRL 1 236 #define KVM_ARM_VCPU_TIMER_IRQ_VTIMER 0 237 #define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1 238 239 /* KVM_IRQ_LINE irq field index values */ 240 #define KVM_ARM_IRQ_TYPE_SHIFT 24 241 #define KVM_ARM_IRQ_TYPE_MASK 0xff 242 #define KVM_ARM_IRQ_VCPU_SHIFT 16 243 #define KVM_ARM_IRQ_VCPU_MASK 0xff 244 #define KVM_ARM_IRQ_NUM_SHIFT 0 245 #define KVM_ARM_IRQ_NUM_MASK 0xffff 246 247 /* irq_type field */ 248 #define KVM_ARM_IRQ_TYPE_CPU 0 249 #define KVM_ARM_IRQ_TYPE_SPI 1 250 #define KVM_ARM_IRQ_TYPE_PPI 2 251 252 /* out-of-kernel GIC cpu interrupt injection irq_number field */ 253 #define KVM_ARM_IRQ_CPU_IRQ 0 254 #define KVM_ARM_IRQ_CPU_FIQ 1 255 256 /* 257 * This used to hold the highest supported SPI, but it is now obsolete 258 * and only here to provide source code level compatibility with older 259 * userland. The highest SPI number can be set via KVM_DEV_ARM_VGIC_GRP_NR_IRQS. 260 */ 261 #define KVM_ARM_IRQ_GIC_MAX 127 262 263 /* One single KVM irqchip, ie. the VGIC */ 264 #define KVM_NR_IRQCHIPS 1 265 266 /* PSCI interface */ 267 #define KVM_PSCI_FN_BASE 0x95c1ba5e 268 #define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n)) 269 270 #define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0) 271 #define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1) 272 #define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2) 273 #define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3) 274 275 #define KVM_PSCI_RET_SUCCESS PSCI_RET_SUCCESS 276 #define KVM_PSCI_RET_NI PSCI_RET_NOT_SUPPORTED 277 #define KVM_PSCI_RET_INVAL PSCI_RET_INVALID_PARAMS 278 #define KVM_PSCI_RET_DENIED PSCI_RET_DENIED 279 280 #endif 281 282 #endif /* __ARM_KVM_H__ */ 283