1b91a0fa7SYifei Jiang /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2b91a0fa7SYifei Jiang /* 3b91a0fa7SYifei Jiang * Copyright (C) 2019 Western Digital Corporation or its affiliates. 4b91a0fa7SYifei Jiang * 5b91a0fa7SYifei Jiang * Authors: 6b91a0fa7SYifei Jiang * Anup Patel <anup.patel@wdc.com> 7b91a0fa7SYifei Jiang */ 8b91a0fa7SYifei Jiang 9b91a0fa7SYifei Jiang #ifndef __LINUX_KVM_RISCV_H 10b91a0fa7SYifei Jiang #define __LINUX_KVM_RISCV_H 11b91a0fa7SYifei Jiang 12b91a0fa7SYifei Jiang #ifndef __ASSEMBLY__ 13b91a0fa7SYifei Jiang 14b91a0fa7SYifei Jiang #include <linux/types.h> 15d0bf492fSCédric Le Goater #include <asm/bitsperlong.h> 16b91a0fa7SYifei Jiang #include <asm/ptrace.h> 17b91a0fa7SYifei Jiang 18d0bf492fSCédric Le Goater #define __KVM_HAVE_IRQ_LINE 19b91a0fa7SYifei Jiang #define __KVM_HAVE_READONLY_MEM 20b91a0fa7SYifei Jiang 21b91a0fa7SYifei Jiang #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 22b91a0fa7SYifei Jiang 23b91a0fa7SYifei Jiang #define KVM_INTERRUPT_SET -1U 24b91a0fa7SYifei Jiang #define KVM_INTERRUPT_UNSET -2U 25b91a0fa7SYifei Jiang 26b91a0fa7SYifei Jiang /* for KVM_GET_REGS and KVM_SET_REGS */ 27b91a0fa7SYifei Jiang struct kvm_regs { 28b91a0fa7SYifei Jiang }; 29b91a0fa7SYifei Jiang 30b91a0fa7SYifei Jiang /* for KVM_GET_FPU and KVM_SET_FPU */ 31b91a0fa7SYifei Jiang struct kvm_fpu { 32b91a0fa7SYifei Jiang }; 33b91a0fa7SYifei Jiang 34b91a0fa7SYifei Jiang /* KVM Debug exit structure */ 35b91a0fa7SYifei Jiang struct kvm_debug_exit_arch { 36b91a0fa7SYifei Jiang }; 37b91a0fa7SYifei Jiang 38b91a0fa7SYifei Jiang /* for KVM_SET_GUEST_DEBUG */ 39b91a0fa7SYifei Jiang struct kvm_guest_debug_arch { 40b91a0fa7SYifei Jiang }; 41b91a0fa7SYifei Jiang 42b91a0fa7SYifei Jiang /* definition of registers in kvm_run */ 43b91a0fa7SYifei Jiang struct kvm_sync_regs { 44b91a0fa7SYifei Jiang }; 45b91a0fa7SYifei Jiang 46b91a0fa7SYifei Jiang /* for KVM_GET_SREGS and KVM_SET_SREGS */ 47b91a0fa7SYifei Jiang struct kvm_sregs { 48b91a0fa7SYifei Jiang }; 49b91a0fa7SYifei Jiang 50b91a0fa7SYifei Jiang /* CONFIG registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ 51b91a0fa7SYifei Jiang struct kvm_riscv_config { 52b91a0fa7SYifei Jiang unsigned long isa; 5393e0932bSPeter Xu unsigned long zicbom_block_size; 5493d7620cSAvihai Horon unsigned long mvendorid; 5593d7620cSAvihai Horon unsigned long marchid; 5693d7620cSAvihai Horon unsigned long mimpid; 57d0bf492fSCédric Le Goater unsigned long zicboz_block_size; 58da3c22c7SThomas Huth unsigned long satp_mode; 59b91a0fa7SYifei Jiang }; 60b91a0fa7SYifei Jiang 61b91a0fa7SYifei Jiang /* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ 62b91a0fa7SYifei Jiang struct kvm_riscv_core { 63b91a0fa7SYifei Jiang struct user_regs_struct regs; 64b91a0fa7SYifei Jiang unsigned long mode; 65b91a0fa7SYifei Jiang }; 66b91a0fa7SYifei Jiang 67b91a0fa7SYifei Jiang /* Possible privilege modes for kvm_riscv_core */ 68b91a0fa7SYifei Jiang #define KVM_RISCV_MODE_S 1 69b91a0fa7SYifei Jiang #define KVM_RISCV_MODE_U 0 70b91a0fa7SYifei Jiang 71d0bf492fSCédric Le Goater /* General CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ 72b91a0fa7SYifei Jiang struct kvm_riscv_csr { 73b91a0fa7SYifei Jiang unsigned long sstatus; 74b91a0fa7SYifei Jiang unsigned long sie; 75b91a0fa7SYifei Jiang unsigned long stvec; 76b91a0fa7SYifei Jiang unsigned long sscratch; 77b91a0fa7SYifei Jiang unsigned long sepc; 78b91a0fa7SYifei Jiang unsigned long scause; 79b91a0fa7SYifei Jiang unsigned long stval; 80b91a0fa7SYifei Jiang unsigned long sip; 81b91a0fa7SYifei Jiang unsigned long satp; 82b91a0fa7SYifei Jiang unsigned long scounteren; 83efb91426SDaniel Henrique Barboza unsigned long senvcfg; 84b91a0fa7SYifei Jiang }; 85b91a0fa7SYifei Jiang 86d0bf492fSCédric Le Goater /* AIA CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ 87d0bf492fSCédric Le Goater struct kvm_riscv_aia_csr { 88d0bf492fSCédric Le Goater unsigned long siselect; 89d0bf492fSCédric Le Goater unsigned long iprio1; 90d0bf492fSCédric Le Goater unsigned long iprio2; 91d0bf492fSCédric Le Goater unsigned long sieh; 92d0bf492fSCédric Le Goater unsigned long siph; 93d0bf492fSCédric Le Goater unsigned long iprio1h; 94d0bf492fSCédric Le Goater unsigned long iprio2h; 95d0bf492fSCédric Le Goater }; 96d0bf492fSCédric Le Goater 97efb91426SDaniel Henrique Barboza /* Smstateen CSR for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ 98efb91426SDaniel Henrique Barboza struct kvm_riscv_smstateen_csr { 99efb91426SDaniel Henrique Barboza unsigned long sstateen0; 100efb91426SDaniel Henrique Barboza }; 101efb91426SDaniel Henrique Barboza 102b91a0fa7SYifei Jiang /* TIMER registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ 103b91a0fa7SYifei Jiang struct kvm_riscv_timer { 104b91a0fa7SYifei Jiang __u64 frequency; 105b91a0fa7SYifei Jiang __u64 time; 106b91a0fa7SYifei Jiang __u64 compare; 107b91a0fa7SYifei Jiang __u64 state; 108b91a0fa7SYifei Jiang }; 109b91a0fa7SYifei Jiang 110d525f73fSChenyi Qiang /* 111d525f73fSChenyi Qiang * ISA extension IDs specific to KVM. This is not the same as the host ISA 112d525f73fSChenyi Qiang * extension IDs as that is internal to the host and should not be exposed 113d525f73fSChenyi Qiang * to the guest. This should always be contiguous to keep the mapping simple 114d525f73fSChenyi Qiang * in KVM implementation. 115d525f73fSChenyi Qiang */ 116d525f73fSChenyi Qiang enum KVM_RISCV_ISA_EXT_ID { 117d525f73fSChenyi Qiang KVM_RISCV_ISA_EXT_A = 0, 118d525f73fSChenyi Qiang KVM_RISCV_ISA_EXT_C, 119d525f73fSChenyi Qiang KVM_RISCV_ISA_EXT_D, 120d525f73fSChenyi Qiang KVM_RISCV_ISA_EXT_F, 121d525f73fSChenyi Qiang KVM_RISCV_ISA_EXT_H, 122d525f73fSChenyi Qiang KVM_RISCV_ISA_EXT_I, 123d525f73fSChenyi Qiang KVM_RISCV_ISA_EXT_M, 124d525f73fSChenyi Qiang KVM_RISCV_ISA_EXT_SVPBMT, 125d525f73fSChenyi Qiang KVM_RISCV_ISA_EXT_SSTC, 12693e0932bSPeter Xu KVM_RISCV_ISA_EXT_SVINVAL, 12793e0932bSPeter Xu KVM_RISCV_ISA_EXT_ZIHINTPAUSE, 12893e0932bSPeter Xu KVM_RISCV_ISA_EXT_ZICBOM, 129d0bf492fSCédric Le Goater KVM_RISCV_ISA_EXT_ZICBOZ, 130d0bf492fSCédric Le Goater KVM_RISCV_ISA_EXT_ZBB, 131d0bf492fSCédric Le Goater KVM_RISCV_ISA_EXT_SSAIA, 132d0bf492fSCédric Le Goater KVM_RISCV_ISA_EXT_V, 133d0bf492fSCédric Le Goater KVM_RISCV_ISA_EXT_SVNAPOT, 134da3c22c7SThomas Huth KVM_RISCV_ISA_EXT_ZBA, 135da3c22c7SThomas Huth KVM_RISCV_ISA_EXT_ZBS, 136da3c22c7SThomas Huth KVM_RISCV_ISA_EXT_ZICNTR, 137da3c22c7SThomas Huth KVM_RISCV_ISA_EXT_ZICSR, 138da3c22c7SThomas Huth KVM_RISCV_ISA_EXT_ZIFENCEI, 139da3c22c7SThomas Huth KVM_RISCV_ISA_EXT_ZIHPM, 140efb91426SDaniel Henrique Barboza KVM_RISCV_ISA_EXT_SMSTATEEN, 141efb91426SDaniel Henrique Barboza KVM_RISCV_ISA_EXT_ZICOND, 142*6a02465fSDaniel Henrique Barboza KVM_RISCV_ISA_EXT_ZBC, 143*6a02465fSDaniel Henrique Barboza KVM_RISCV_ISA_EXT_ZBKB, 144*6a02465fSDaniel Henrique Barboza KVM_RISCV_ISA_EXT_ZBKC, 145*6a02465fSDaniel Henrique Barboza KVM_RISCV_ISA_EXT_ZBKX, 146*6a02465fSDaniel Henrique Barboza KVM_RISCV_ISA_EXT_ZKND, 147*6a02465fSDaniel Henrique Barboza KVM_RISCV_ISA_EXT_ZKNE, 148*6a02465fSDaniel Henrique Barboza KVM_RISCV_ISA_EXT_ZKNH, 149*6a02465fSDaniel Henrique Barboza KVM_RISCV_ISA_EXT_ZKR, 150*6a02465fSDaniel Henrique Barboza KVM_RISCV_ISA_EXT_ZKSED, 151*6a02465fSDaniel Henrique Barboza KVM_RISCV_ISA_EXT_ZKSH, 152*6a02465fSDaniel Henrique Barboza KVM_RISCV_ISA_EXT_ZKT, 153*6a02465fSDaniel Henrique Barboza KVM_RISCV_ISA_EXT_ZVBB, 154*6a02465fSDaniel Henrique Barboza KVM_RISCV_ISA_EXT_ZVBC, 155*6a02465fSDaniel Henrique Barboza KVM_RISCV_ISA_EXT_ZVKB, 156*6a02465fSDaniel Henrique Barboza KVM_RISCV_ISA_EXT_ZVKG, 157*6a02465fSDaniel Henrique Barboza KVM_RISCV_ISA_EXT_ZVKNED, 158*6a02465fSDaniel Henrique Barboza KVM_RISCV_ISA_EXT_ZVKNHA, 159*6a02465fSDaniel Henrique Barboza KVM_RISCV_ISA_EXT_ZVKNHB, 160*6a02465fSDaniel Henrique Barboza KVM_RISCV_ISA_EXT_ZVKSED, 161*6a02465fSDaniel Henrique Barboza KVM_RISCV_ISA_EXT_ZVKSH, 162*6a02465fSDaniel Henrique Barboza KVM_RISCV_ISA_EXT_ZVKT, 163*6a02465fSDaniel Henrique Barboza KVM_RISCV_ISA_EXT_ZFH, 164*6a02465fSDaniel Henrique Barboza KVM_RISCV_ISA_EXT_ZFHMIN, 165*6a02465fSDaniel Henrique Barboza KVM_RISCV_ISA_EXT_ZIHINTNTL, 166*6a02465fSDaniel Henrique Barboza KVM_RISCV_ISA_EXT_ZVFH, 167*6a02465fSDaniel Henrique Barboza KVM_RISCV_ISA_EXT_ZVFHMIN, 168*6a02465fSDaniel Henrique Barboza KVM_RISCV_ISA_EXT_ZFA, 169d525f73fSChenyi Qiang KVM_RISCV_ISA_EXT_MAX, 170d525f73fSChenyi Qiang }; 171d525f73fSChenyi Qiang 172d0bf492fSCédric Le Goater /* 173d0bf492fSCédric Le Goater * SBI extension IDs specific to KVM. This is not the same as the SBI 174d0bf492fSCédric Le Goater * extension IDs defined by the RISC-V SBI specification. 175d0bf492fSCédric Le Goater */ 176d0bf492fSCédric Le Goater enum KVM_RISCV_SBI_EXT_ID { 177d0bf492fSCédric Le Goater KVM_RISCV_SBI_EXT_V01 = 0, 178d0bf492fSCédric Le Goater KVM_RISCV_SBI_EXT_TIME, 179d0bf492fSCédric Le Goater KVM_RISCV_SBI_EXT_IPI, 180d0bf492fSCédric Le Goater KVM_RISCV_SBI_EXT_RFENCE, 181d0bf492fSCédric Le Goater KVM_RISCV_SBI_EXT_SRST, 182d0bf492fSCédric Le Goater KVM_RISCV_SBI_EXT_HSM, 183d0bf492fSCédric Le Goater KVM_RISCV_SBI_EXT_PMU, 184d0bf492fSCédric Le Goater KVM_RISCV_SBI_EXT_EXPERIMENTAL, 185d0bf492fSCédric Le Goater KVM_RISCV_SBI_EXT_VENDOR, 186efb91426SDaniel Henrique Barboza KVM_RISCV_SBI_EXT_DBCN, 187*6a02465fSDaniel Henrique Barboza KVM_RISCV_SBI_EXT_STA, 188d0bf492fSCédric Le Goater KVM_RISCV_SBI_EXT_MAX, 189d0bf492fSCédric Le Goater }; 190d0bf492fSCédric Le Goater 191*6a02465fSDaniel Henrique Barboza /* SBI STA extension registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ 192*6a02465fSDaniel Henrique Barboza struct kvm_riscv_sbi_sta { 193*6a02465fSDaniel Henrique Barboza unsigned long shmem_lo; 194*6a02465fSDaniel Henrique Barboza unsigned long shmem_hi; 195*6a02465fSDaniel Henrique Barboza }; 196*6a02465fSDaniel Henrique Barboza 197b91a0fa7SYifei Jiang /* Possible states for kvm_riscv_timer */ 198b91a0fa7SYifei Jiang #define KVM_RISCV_TIMER_STATE_OFF 0 199b91a0fa7SYifei Jiang #define KVM_RISCV_TIMER_STATE_ON 1 200b91a0fa7SYifei Jiang 201b91a0fa7SYifei Jiang #define KVM_REG_SIZE(id) \ 202b91a0fa7SYifei Jiang (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT)) 203b91a0fa7SYifei Jiang 204b91a0fa7SYifei Jiang /* If you need to interpret the index values, here is the key: */ 205b91a0fa7SYifei Jiang #define KVM_REG_RISCV_TYPE_MASK 0x00000000FF000000 206b91a0fa7SYifei Jiang #define KVM_REG_RISCV_TYPE_SHIFT 24 207d0bf492fSCédric Le Goater #define KVM_REG_RISCV_SUBTYPE_MASK 0x0000000000FF0000 208d0bf492fSCédric Le Goater #define KVM_REG_RISCV_SUBTYPE_SHIFT 16 209b91a0fa7SYifei Jiang 210b91a0fa7SYifei Jiang /* Config registers are mapped as type 1 */ 211b91a0fa7SYifei Jiang #define KVM_REG_RISCV_CONFIG (0x01 << KVM_REG_RISCV_TYPE_SHIFT) 212b91a0fa7SYifei Jiang #define KVM_REG_RISCV_CONFIG_REG(name) \ 213b91a0fa7SYifei Jiang (offsetof(struct kvm_riscv_config, name) / sizeof(unsigned long)) 214b91a0fa7SYifei Jiang 215b91a0fa7SYifei Jiang /* Core registers are mapped as type 2 */ 216b91a0fa7SYifei Jiang #define KVM_REG_RISCV_CORE (0x02 << KVM_REG_RISCV_TYPE_SHIFT) 217b91a0fa7SYifei Jiang #define KVM_REG_RISCV_CORE_REG(name) \ 218b91a0fa7SYifei Jiang (offsetof(struct kvm_riscv_core, name) / sizeof(unsigned long)) 219b91a0fa7SYifei Jiang 220b91a0fa7SYifei Jiang /* Control and status registers are mapped as type 3 */ 221b91a0fa7SYifei Jiang #define KVM_REG_RISCV_CSR (0x03 << KVM_REG_RISCV_TYPE_SHIFT) 222d0bf492fSCédric Le Goater #define KVM_REG_RISCV_CSR_GENERAL (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT) 223d0bf492fSCédric Le Goater #define KVM_REG_RISCV_CSR_AIA (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT) 224efb91426SDaniel Henrique Barboza #define KVM_REG_RISCV_CSR_SMSTATEEN (0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT) 225b91a0fa7SYifei Jiang #define KVM_REG_RISCV_CSR_REG(name) \ 226b91a0fa7SYifei Jiang (offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long)) 227d0bf492fSCédric Le Goater #define KVM_REG_RISCV_CSR_AIA_REG(name) \ 228d0bf492fSCédric Le Goater (offsetof(struct kvm_riscv_aia_csr, name) / sizeof(unsigned long)) 229efb91426SDaniel Henrique Barboza #define KVM_REG_RISCV_CSR_SMSTATEEN_REG(name) \ 230efb91426SDaniel Henrique Barboza (offsetof(struct kvm_riscv_smstateen_csr, name) / sizeof(unsigned long)) 231b91a0fa7SYifei Jiang 232b91a0fa7SYifei Jiang /* Timer registers are mapped as type 4 */ 233b91a0fa7SYifei Jiang #define KVM_REG_RISCV_TIMER (0x04 << KVM_REG_RISCV_TYPE_SHIFT) 234b91a0fa7SYifei Jiang #define KVM_REG_RISCV_TIMER_REG(name) \ 235b91a0fa7SYifei Jiang (offsetof(struct kvm_riscv_timer, name) / sizeof(__u64)) 236b91a0fa7SYifei Jiang 237b91a0fa7SYifei Jiang /* F extension registers are mapped as type 5 */ 238b91a0fa7SYifei Jiang #define KVM_REG_RISCV_FP_F (0x05 << KVM_REG_RISCV_TYPE_SHIFT) 239b91a0fa7SYifei Jiang #define KVM_REG_RISCV_FP_F_REG(name) \ 240b91a0fa7SYifei Jiang (offsetof(struct __riscv_f_ext_state, name) / sizeof(__u32)) 241b91a0fa7SYifei Jiang 242b91a0fa7SYifei Jiang /* D extension registers are mapped as type 6 */ 243b91a0fa7SYifei Jiang #define KVM_REG_RISCV_FP_D (0x06 << KVM_REG_RISCV_TYPE_SHIFT) 244b91a0fa7SYifei Jiang #define KVM_REG_RISCV_FP_D_REG(name) \ 245b91a0fa7SYifei Jiang (offsetof(struct __riscv_d_ext_state, name) / sizeof(__u64)) 246b91a0fa7SYifei Jiang 247d525f73fSChenyi Qiang /* ISA Extension registers are mapped as type 7 */ 248d525f73fSChenyi Qiang #define KVM_REG_RISCV_ISA_EXT (0x07 << KVM_REG_RISCV_TYPE_SHIFT) 249da3c22c7SThomas Huth #define KVM_REG_RISCV_ISA_SINGLE (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT) 250da3c22c7SThomas Huth #define KVM_REG_RISCV_ISA_MULTI_EN (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT) 251da3c22c7SThomas Huth #define KVM_REG_RISCV_ISA_MULTI_DIS (0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT) 252da3c22c7SThomas Huth #define KVM_REG_RISCV_ISA_MULTI_REG(__ext_id) \ 253da3c22c7SThomas Huth ((__ext_id) / __BITS_PER_LONG) 254da3c22c7SThomas Huth #define KVM_REG_RISCV_ISA_MULTI_MASK(__ext_id) \ 255da3c22c7SThomas Huth (1UL << ((__ext_id) % __BITS_PER_LONG)) 256da3c22c7SThomas Huth #define KVM_REG_RISCV_ISA_MULTI_REG_LAST \ 257da3c22c7SThomas Huth KVM_REG_RISCV_ISA_MULTI_REG(KVM_RISCV_ISA_EXT_MAX - 1) 258d525f73fSChenyi Qiang 259d0bf492fSCédric Le Goater /* SBI extension registers are mapped as type 8 */ 260d0bf492fSCédric Le Goater #define KVM_REG_RISCV_SBI_EXT (0x08 << KVM_REG_RISCV_TYPE_SHIFT) 261d0bf492fSCédric Le Goater #define KVM_REG_RISCV_SBI_SINGLE (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT) 262d0bf492fSCédric Le Goater #define KVM_REG_RISCV_SBI_MULTI_EN (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT) 263d0bf492fSCédric Le Goater #define KVM_REG_RISCV_SBI_MULTI_DIS (0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT) 264d0bf492fSCédric Le Goater #define KVM_REG_RISCV_SBI_MULTI_REG(__ext_id) \ 265d0bf492fSCédric Le Goater ((__ext_id) / __BITS_PER_LONG) 266d0bf492fSCédric Le Goater #define KVM_REG_RISCV_SBI_MULTI_MASK(__ext_id) \ 267d0bf492fSCédric Le Goater (1UL << ((__ext_id) % __BITS_PER_LONG)) 268d0bf492fSCédric Le Goater #define KVM_REG_RISCV_SBI_MULTI_REG_LAST \ 269d0bf492fSCédric Le Goater KVM_REG_RISCV_SBI_MULTI_REG(KVM_RISCV_SBI_EXT_MAX - 1) 270d0bf492fSCédric Le Goater 271d0bf492fSCédric Le Goater /* V extension registers are mapped as type 9 */ 272d0bf492fSCédric Le Goater #define KVM_REG_RISCV_VECTOR (0x09 << KVM_REG_RISCV_TYPE_SHIFT) 273d0bf492fSCédric Le Goater #define KVM_REG_RISCV_VECTOR_CSR_REG(name) \ 274d0bf492fSCédric Le Goater (offsetof(struct __riscv_v_ext_state, name) / sizeof(unsigned long)) 275d0bf492fSCédric Le Goater #define KVM_REG_RISCV_VECTOR_REG(n) \ 276d0bf492fSCédric Le Goater ((n) + sizeof(struct __riscv_v_ext_state) / sizeof(unsigned long)) 277d0bf492fSCédric Le Goater 278*6a02465fSDaniel Henrique Barboza /* Registers for specific SBI extensions are mapped as type 10 */ 279*6a02465fSDaniel Henrique Barboza #define KVM_REG_RISCV_SBI_STATE (0x0a << KVM_REG_RISCV_TYPE_SHIFT) 280*6a02465fSDaniel Henrique Barboza #define KVM_REG_RISCV_SBI_STA (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT) 281*6a02465fSDaniel Henrique Barboza #define KVM_REG_RISCV_SBI_STA_REG(name) \ 282*6a02465fSDaniel Henrique Barboza (offsetof(struct kvm_riscv_sbi_sta, name) / sizeof(unsigned long)) 283*6a02465fSDaniel Henrique Barboza 284d0bf492fSCédric Le Goater /* Device Control API: RISC-V AIA */ 285d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_APLIC_ALIGN 0x1000 286d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_APLIC_SIZE 0x4000 287d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_APLIC_MAX_HARTS 0x4000 288d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_IMSIC_ALIGN 0x1000 289d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_IMSIC_SIZE 0x1000 290d0bf492fSCédric Le Goater 291d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_GRP_CONFIG 0 292d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_CONFIG_MODE 0 293d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_CONFIG_IDS 1 294d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_CONFIG_SRCS 2 295d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS 3 296d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT 4 297d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_CONFIG_HART_BITS 5 298d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS 6 299d0bf492fSCédric Le Goater 300d0bf492fSCédric Le Goater /* 301d0bf492fSCédric Le Goater * Modes of RISC-V AIA device: 302d0bf492fSCédric Le Goater * 1) EMUL (aka Emulation): Trap-n-emulate IMSIC 303d0bf492fSCédric Le Goater * 2) HWACCEL (aka HW Acceleration): Virtualize IMSIC using IMSIC guest files 304d0bf492fSCédric Le Goater * 3) AUTO (aka Automatic): Virtualize IMSIC using IMSIC guest files whenever 305d0bf492fSCédric Le Goater * available otherwise fallback to trap-n-emulation 306d0bf492fSCédric Le Goater */ 307d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_MODE_EMUL 0 308d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_MODE_HWACCEL 1 309d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_MODE_AUTO 2 310d0bf492fSCédric Le Goater 311d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_IDS_MIN 63 312d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_IDS_MAX 2048 313d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_SRCS_MAX 1024 314d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_GROUP_BITS_MAX 8 315d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_GROUP_SHIFT_MIN 24 316d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_GROUP_SHIFT_MAX 56 317d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_HART_BITS_MAX 16 318d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_GUEST_BITS_MAX 8 319d0bf492fSCédric Le Goater 320d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_GRP_ADDR 1 321d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_ADDR_APLIC 0 322d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_ADDR_IMSIC(__vcpu) (1 + (__vcpu)) 323d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_ADDR_MAX \ 324d0bf492fSCédric Le Goater (1 + KVM_DEV_RISCV_APLIC_MAX_HARTS) 325d0bf492fSCédric Le Goater 326d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_GRP_CTRL 2 327d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_CTRL_INIT 0 328d0bf492fSCédric Le Goater 329d0bf492fSCédric Le Goater /* 330d0bf492fSCédric Le Goater * The device attribute type contains the memory mapped offset of the 331d0bf492fSCédric Le Goater * APLIC register (range 0x0000-0x3FFF) and it must be 4-byte aligned. 332d0bf492fSCédric Le Goater */ 333d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_GRP_APLIC 3 334d0bf492fSCédric Le Goater 335d0bf492fSCédric Le Goater /* 336d0bf492fSCédric Le Goater * The lower 12-bits of the device attribute type contains the iselect 337d0bf492fSCédric Le Goater * value of the IMSIC register (range 0x70-0xFF) whereas the higher order 338d0bf492fSCédric Le Goater * bits contains the VCPU id. 339d0bf492fSCédric Le Goater */ 340d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_GRP_IMSIC 4 341d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS 12 342d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK \ 343d0bf492fSCédric Le Goater ((1U << KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS) - 1) 344d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_IMSIC_MKATTR(__vcpu, __isel) \ 345d0bf492fSCédric Le Goater (((__vcpu) << KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS) | \ 346d0bf492fSCédric Le Goater ((__isel) & KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK)) 347d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_IMSIC_GET_ISEL(__attr) \ 348d0bf492fSCédric Le Goater ((__attr) & KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK) 349d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_IMSIC_GET_VCPU(__attr) \ 350d0bf492fSCédric Le Goater ((__attr) >> KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS) 351d0bf492fSCédric Le Goater 352d0bf492fSCédric Le Goater /* One single KVM irqchip, ie. the AIA */ 353d0bf492fSCédric Le Goater #define KVM_NR_IRQCHIPS 1 354d0bf492fSCédric Le Goater 355b91a0fa7SYifei Jiang #endif 356b91a0fa7SYifei Jiang 357b91a0fa7SYifei Jiang #endif /* __LINUX_KVM_RISCV_H */ 358