1b91a0fa7SYifei Jiang /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2b91a0fa7SYifei Jiang /* 3b91a0fa7SYifei Jiang * Copyright (C) 2019 Western Digital Corporation or its affiliates. 4b91a0fa7SYifei Jiang * 5b91a0fa7SYifei Jiang * Authors: 6b91a0fa7SYifei Jiang * Anup Patel <anup.patel@wdc.com> 7b91a0fa7SYifei Jiang */ 8b91a0fa7SYifei Jiang 9b91a0fa7SYifei Jiang #ifndef __LINUX_KVM_RISCV_H 10b91a0fa7SYifei Jiang #define __LINUX_KVM_RISCV_H 11b91a0fa7SYifei Jiang 12b91a0fa7SYifei Jiang #ifndef __ASSEMBLY__ 13b91a0fa7SYifei Jiang 14b91a0fa7SYifei Jiang #include <linux/types.h> 15*d0bf492fSCédric Le Goater #include <asm/bitsperlong.h> 16b91a0fa7SYifei Jiang #include <asm/ptrace.h> 17b91a0fa7SYifei Jiang 18*d0bf492fSCédric Le Goater #define __KVM_HAVE_IRQ_LINE 19b91a0fa7SYifei Jiang #define __KVM_HAVE_READONLY_MEM 20b91a0fa7SYifei Jiang 21b91a0fa7SYifei Jiang #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 22b91a0fa7SYifei Jiang 23b91a0fa7SYifei Jiang #define KVM_INTERRUPT_SET -1U 24b91a0fa7SYifei Jiang #define KVM_INTERRUPT_UNSET -2U 25b91a0fa7SYifei Jiang 26b91a0fa7SYifei Jiang /* for KVM_GET_REGS and KVM_SET_REGS */ 27b91a0fa7SYifei Jiang struct kvm_regs { 28b91a0fa7SYifei Jiang }; 29b91a0fa7SYifei Jiang 30b91a0fa7SYifei Jiang /* for KVM_GET_FPU and KVM_SET_FPU */ 31b91a0fa7SYifei Jiang struct kvm_fpu { 32b91a0fa7SYifei Jiang }; 33b91a0fa7SYifei Jiang 34b91a0fa7SYifei Jiang /* KVM Debug exit structure */ 35b91a0fa7SYifei Jiang struct kvm_debug_exit_arch { 36b91a0fa7SYifei Jiang }; 37b91a0fa7SYifei Jiang 38b91a0fa7SYifei Jiang /* for KVM_SET_GUEST_DEBUG */ 39b91a0fa7SYifei Jiang struct kvm_guest_debug_arch { 40b91a0fa7SYifei Jiang }; 41b91a0fa7SYifei Jiang 42b91a0fa7SYifei Jiang /* definition of registers in kvm_run */ 43b91a0fa7SYifei Jiang struct kvm_sync_regs { 44b91a0fa7SYifei Jiang }; 45b91a0fa7SYifei Jiang 46b91a0fa7SYifei Jiang /* for KVM_GET_SREGS and KVM_SET_SREGS */ 47b91a0fa7SYifei Jiang struct kvm_sregs { 48b91a0fa7SYifei Jiang }; 49b91a0fa7SYifei Jiang 50b91a0fa7SYifei Jiang /* CONFIG registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ 51b91a0fa7SYifei Jiang struct kvm_riscv_config { 52b91a0fa7SYifei Jiang unsigned long isa; 5393e0932bSPeter Xu unsigned long zicbom_block_size; 5493d7620cSAvihai Horon unsigned long mvendorid; 5593d7620cSAvihai Horon unsigned long marchid; 5693d7620cSAvihai Horon unsigned long mimpid; 57*d0bf492fSCédric Le Goater unsigned long zicboz_block_size; 58b91a0fa7SYifei Jiang }; 59b91a0fa7SYifei Jiang 60b91a0fa7SYifei Jiang /* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ 61b91a0fa7SYifei Jiang struct kvm_riscv_core { 62b91a0fa7SYifei Jiang struct user_regs_struct regs; 63b91a0fa7SYifei Jiang unsigned long mode; 64b91a0fa7SYifei Jiang }; 65b91a0fa7SYifei Jiang 66b91a0fa7SYifei Jiang /* Possible privilege modes for kvm_riscv_core */ 67b91a0fa7SYifei Jiang #define KVM_RISCV_MODE_S 1 68b91a0fa7SYifei Jiang #define KVM_RISCV_MODE_U 0 69b91a0fa7SYifei Jiang 70*d0bf492fSCédric Le Goater /* General CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ 71b91a0fa7SYifei Jiang struct kvm_riscv_csr { 72b91a0fa7SYifei Jiang unsigned long sstatus; 73b91a0fa7SYifei Jiang unsigned long sie; 74b91a0fa7SYifei Jiang unsigned long stvec; 75b91a0fa7SYifei Jiang unsigned long sscratch; 76b91a0fa7SYifei Jiang unsigned long sepc; 77b91a0fa7SYifei Jiang unsigned long scause; 78b91a0fa7SYifei Jiang unsigned long stval; 79b91a0fa7SYifei Jiang unsigned long sip; 80b91a0fa7SYifei Jiang unsigned long satp; 81b91a0fa7SYifei Jiang unsigned long scounteren; 82b91a0fa7SYifei Jiang }; 83b91a0fa7SYifei Jiang 84*d0bf492fSCédric Le Goater /* AIA CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ 85*d0bf492fSCédric Le Goater struct kvm_riscv_aia_csr { 86*d0bf492fSCédric Le Goater unsigned long siselect; 87*d0bf492fSCédric Le Goater unsigned long iprio1; 88*d0bf492fSCédric Le Goater unsigned long iprio2; 89*d0bf492fSCédric Le Goater unsigned long sieh; 90*d0bf492fSCédric Le Goater unsigned long siph; 91*d0bf492fSCédric Le Goater unsigned long iprio1h; 92*d0bf492fSCédric Le Goater unsigned long iprio2h; 93*d0bf492fSCédric Le Goater }; 94*d0bf492fSCédric Le Goater 95b91a0fa7SYifei Jiang /* TIMER registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ 96b91a0fa7SYifei Jiang struct kvm_riscv_timer { 97b91a0fa7SYifei Jiang __u64 frequency; 98b91a0fa7SYifei Jiang __u64 time; 99b91a0fa7SYifei Jiang __u64 compare; 100b91a0fa7SYifei Jiang __u64 state; 101b91a0fa7SYifei Jiang }; 102b91a0fa7SYifei Jiang 103d525f73fSChenyi Qiang /* 104d525f73fSChenyi Qiang * ISA extension IDs specific to KVM. This is not the same as the host ISA 105d525f73fSChenyi Qiang * extension IDs as that is internal to the host and should not be exposed 106d525f73fSChenyi Qiang * to the guest. This should always be contiguous to keep the mapping simple 107d525f73fSChenyi Qiang * in KVM implementation. 108d525f73fSChenyi Qiang */ 109d525f73fSChenyi Qiang enum KVM_RISCV_ISA_EXT_ID { 110d525f73fSChenyi Qiang KVM_RISCV_ISA_EXT_A = 0, 111d525f73fSChenyi Qiang KVM_RISCV_ISA_EXT_C, 112d525f73fSChenyi Qiang KVM_RISCV_ISA_EXT_D, 113d525f73fSChenyi Qiang KVM_RISCV_ISA_EXT_F, 114d525f73fSChenyi Qiang KVM_RISCV_ISA_EXT_H, 115d525f73fSChenyi Qiang KVM_RISCV_ISA_EXT_I, 116d525f73fSChenyi Qiang KVM_RISCV_ISA_EXT_M, 117d525f73fSChenyi Qiang KVM_RISCV_ISA_EXT_SVPBMT, 118d525f73fSChenyi Qiang KVM_RISCV_ISA_EXT_SSTC, 11993e0932bSPeter Xu KVM_RISCV_ISA_EXT_SVINVAL, 12093e0932bSPeter Xu KVM_RISCV_ISA_EXT_ZIHINTPAUSE, 12193e0932bSPeter Xu KVM_RISCV_ISA_EXT_ZICBOM, 122*d0bf492fSCédric Le Goater KVM_RISCV_ISA_EXT_ZICBOZ, 123*d0bf492fSCédric Le Goater KVM_RISCV_ISA_EXT_ZBB, 124*d0bf492fSCédric Le Goater KVM_RISCV_ISA_EXT_SSAIA, 125*d0bf492fSCédric Le Goater KVM_RISCV_ISA_EXT_V, 126*d0bf492fSCédric Le Goater KVM_RISCV_ISA_EXT_SVNAPOT, 127d525f73fSChenyi Qiang KVM_RISCV_ISA_EXT_MAX, 128d525f73fSChenyi Qiang }; 129d525f73fSChenyi Qiang 130*d0bf492fSCédric Le Goater /* 131*d0bf492fSCédric Le Goater * SBI extension IDs specific to KVM. This is not the same as the SBI 132*d0bf492fSCédric Le Goater * extension IDs defined by the RISC-V SBI specification. 133*d0bf492fSCédric Le Goater */ 134*d0bf492fSCédric Le Goater enum KVM_RISCV_SBI_EXT_ID { 135*d0bf492fSCédric Le Goater KVM_RISCV_SBI_EXT_V01 = 0, 136*d0bf492fSCédric Le Goater KVM_RISCV_SBI_EXT_TIME, 137*d0bf492fSCédric Le Goater KVM_RISCV_SBI_EXT_IPI, 138*d0bf492fSCédric Le Goater KVM_RISCV_SBI_EXT_RFENCE, 139*d0bf492fSCédric Le Goater KVM_RISCV_SBI_EXT_SRST, 140*d0bf492fSCédric Le Goater KVM_RISCV_SBI_EXT_HSM, 141*d0bf492fSCédric Le Goater KVM_RISCV_SBI_EXT_PMU, 142*d0bf492fSCédric Le Goater KVM_RISCV_SBI_EXT_EXPERIMENTAL, 143*d0bf492fSCédric Le Goater KVM_RISCV_SBI_EXT_VENDOR, 144*d0bf492fSCédric Le Goater KVM_RISCV_SBI_EXT_MAX, 145*d0bf492fSCédric Le Goater }; 146*d0bf492fSCédric Le Goater 147b91a0fa7SYifei Jiang /* Possible states for kvm_riscv_timer */ 148b91a0fa7SYifei Jiang #define KVM_RISCV_TIMER_STATE_OFF 0 149b91a0fa7SYifei Jiang #define KVM_RISCV_TIMER_STATE_ON 1 150b91a0fa7SYifei Jiang 151b91a0fa7SYifei Jiang #define KVM_REG_SIZE(id) \ 152b91a0fa7SYifei Jiang (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT)) 153b91a0fa7SYifei Jiang 154b91a0fa7SYifei Jiang /* If you need to interpret the index values, here is the key: */ 155b91a0fa7SYifei Jiang #define KVM_REG_RISCV_TYPE_MASK 0x00000000FF000000 156b91a0fa7SYifei Jiang #define KVM_REG_RISCV_TYPE_SHIFT 24 157*d0bf492fSCédric Le Goater #define KVM_REG_RISCV_SUBTYPE_MASK 0x0000000000FF0000 158*d0bf492fSCédric Le Goater #define KVM_REG_RISCV_SUBTYPE_SHIFT 16 159b91a0fa7SYifei Jiang 160b91a0fa7SYifei Jiang /* Config registers are mapped as type 1 */ 161b91a0fa7SYifei Jiang #define KVM_REG_RISCV_CONFIG (0x01 << KVM_REG_RISCV_TYPE_SHIFT) 162b91a0fa7SYifei Jiang #define KVM_REG_RISCV_CONFIG_REG(name) \ 163b91a0fa7SYifei Jiang (offsetof(struct kvm_riscv_config, name) / sizeof(unsigned long)) 164b91a0fa7SYifei Jiang 165b91a0fa7SYifei Jiang /* Core registers are mapped as type 2 */ 166b91a0fa7SYifei Jiang #define KVM_REG_RISCV_CORE (0x02 << KVM_REG_RISCV_TYPE_SHIFT) 167b91a0fa7SYifei Jiang #define KVM_REG_RISCV_CORE_REG(name) \ 168b91a0fa7SYifei Jiang (offsetof(struct kvm_riscv_core, name) / sizeof(unsigned long)) 169b91a0fa7SYifei Jiang 170b91a0fa7SYifei Jiang /* Control and status registers are mapped as type 3 */ 171b91a0fa7SYifei Jiang #define KVM_REG_RISCV_CSR (0x03 << KVM_REG_RISCV_TYPE_SHIFT) 172*d0bf492fSCédric Le Goater #define KVM_REG_RISCV_CSR_GENERAL (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT) 173*d0bf492fSCédric Le Goater #define KVM_REG_RISCV_CSR_AIA (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT) 174b91a0fa7SYifei Jiang #define KVM_REG_RISCV_CSR_REG(name) \ 175b91a0fa7SYifei Jiang (offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long)) 176*d0bf492fSCédric Le Goater #define KVM_REG_RISCV_CSR_AIA_REG(name) \ 177*d0bf492fSCédric Le Goater (offsetof(struct kvm_riscv_aia_csr, name) / sizeof(unsigned long)) 178b91a0fa7SYifei Jiang 179b91a0fa7SYifei Jiang /* Timer registers are mapped as type 4 */ 180b91a0fa7SYifei Jiang #define KVM_REG_RISCV_TIMER (0x04 << KVM_REG_RISCV_TYPE_SHIFT) 181b91a0fa7SYifei Jiang #define KVM_REG_RISCV_TIMER_REG(name) \ 182b91a0fa7SYifei Jiang (offsetof(struct kvm_riscv_timer, name) / sizeof(__u64)) 183b91a0fa7SYifei Jiang 184b91a0fa7SYifei Jiang /* F extension registers are mapped as type 5 */ 185b91a0fa7SYifei Jiang #define KVM_REG_RISCV_FP_F (0x05 << KVM_REG_RISCV_TYPE_SHIFT) 186b91a0fa7SYifei Jiang #define KVM_REG_RISCV_FP_F_REG(name) \ 187b91a0fa7SYifei Jiang (offsetof(struct __riscv_f_ext_state, name) / sizeof(__u32)) 188b91a0fa7SYifei Jiang 189b91a0fa7SYifei Jiang /* D extension registers are mapped as type 6 */ 190b91a0fa7SYifei Jiang #define KVM_REG_RISCV_FP_D (0x06 << KVM_REG_RISCV_TYPE_SHIFT) 191b91a0fa7SYifei Jiang #define KVM_REG_RISCV_FP_D_REG(name) \ 192b91a0fa7SYifei Jiang (offsetof(struct __riscv_d_ext_state, name) / sizeof(__u64)) 193b91a0fa7SYifei Jiang 194d525f73fSChenyi Qiang /* ISA Extension registers are mapped as type 7 */ 195d525f73fSChenyi Qiang #define KVM_REG_RISCV_ISA_EXT (0x07 << KVM_REG_RISCV_TYPE_SHIFT) 196d525f73fSChenyi Qiang 197*d0bf492fSCédric Le Goater /* SBI extension registers are mapped as type 8 */ 198*d0bf492fSCédric Le Goater #define KVM_REG_RISCV_SBI_EXT (0x08 << KVM_REG_RISCV_TYPE_SHIFT) 199*d0bf492fSCédric Le Goater #define KVM_REG_RISCV_SBI_SINGLE (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT) 200*d0bf492fSCédric Le Goater #define KVM_REG_RISCV_SBI_MULTI_EN (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT) 201*d0bf492fSCédric Le Goater #define KVM_REG_RISCV_SBI_MULTI_DIS (0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT) 202*d0bf492fSCédric Le Goater #define KVM_REG_RISCV_SBI_MULTI_REG(__ext_id) \ 203*d0bf492fSCédric Le Goater ((__ext_id) / __BITS_PER_LONG) 204*d0bf492fSCédric Le Goater #define KVM_REG_RISCV_SBI_MULTI_MASK(__ext_id) \ 205*d0bf492fSCédric Le Goater (1UL << ((__ext_id) % __BITS_PER_LONG)) 206*d0bf492fSCédric Le Goater #define KVM_REG_RISCV_SBI_MULTI_REG_LAST \ 207*d0bf492fSCédric Le Goater KVM_REG_RISCV_SBI_MULTI_REG(KVM_RISCV_SBI_EXT_MAX - 1) 208*d0bf492fSCédric Le Goater 209*d0bf492fSCédric Le Goater /* V extension registers are mapped as type 9 */ 210*d0bf492fSCédric Le Goater #define KVM_REG_RISCV_VECTOR (0x09 << KVM_REG_RISCV_TYPE_SHIFT) 211*d0bf492fSCédric Le Goater #define KVM_REG_RISCV_VECTOR_CSR_REG(name) \ 212*d0bf492fSCédric Le Goater (offsetof(struct __riscv_v_ext_state, name) / sizeof(unsigned long)) 213*d0bf492fSCédric Le Goater #define KVM_REG_RISCV_VECTOR_REG(n) \ 214*d0bf492fSCédric Le Goater ((n) + sizeof(struct __riscv_v_ext_state) / sizeof(unsigned long)) 215*d0bf492fSCédric Le Goater 216*d0bf492fSCédric Le Goater /* Device Control API: RISC-V AIA */ 217*d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_APLIC_ALIGN 0x1000 218*d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_APLIC_SIZE 0x4000 219*d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_APLIC_MAX_HARTS 0x4000 220*d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_IMSIC_ALIGN 0x1000 221*d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_IMSIC_SIZE 0x1000 222*d0bf492fSCédric Le Goater 223*d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_GRP_CONFIG 0 224*d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_CONFIG_MODE 0 225*d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_CONFIG_IDS 1 226*d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_CONFIG_SRCS 2 227*d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS 3 228*d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT 4 229*d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_CONFIG_HART_BITS 5 230*d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS 6 231*d0bf492fSCédric Le Goater 232*d0bf492fSCédric Le Goater /* 233*d0bf492fSCédric Le Goater * Modes of RISC-V AIA device: 234*d0bf492fSCédric Le Goater * 1) EMUL (aka Emulation): Trap-n-emulate IMSIC 235*d0bf492fSCédric Le Goater * 2) HWACCEL (aka HW Acceleration): Virtualize IMSIC using IMSIC guest files 236*d0bf492fSCédric Le Goater * 3) AUTO (aka Automatic): Virtualize IMSIC using IMSIC guest files whenever 237*d0bf492fSCédric Le Goater * available otherwise fallback to trap-n-emulation 238*d0bf492fSCédric Le Goater */ 239*d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_MODE_EMUL 0 240*d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_MODE_HWACCEL 1 241*d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_MODE_AUTO 2 242*d0bf492fSCédric Le Goater 243*d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_IDS_MIN 63 244*d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_IDS_MAX 2048 245*d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_SRCS_MAX 1024 246*d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_GROUP_BITS_MAX 8 247*d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_GROUP_SHIFT_MIN 24 248*d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_GROUP_SHIFT_MAX 56 249*d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_HART_BITS_MAX 16 250*d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_GUEST_BITS_MAX 8 251*d0bf492fSCédric Le Goater 252*d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_GRP_ADDR 1 253*d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_ADDR_APLIC 0 254*d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_ADDR_IMSIC(__vcpu) (1 + (__vcpu)) 255*d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_ADDR_MAX \ 256*d0bf492fSCédric Le Goater (1 + KVM_DEV_RISCV_APLIC_MAX_HARTS) 257*d0bf492fSCédric Le Goater 258*d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_GRP_CTRL 2 259*d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_CTRL_INIT 0 260*d0bf492fSCédric Le Goater 261*d0bf492fSCédric Le Goater /* 262*d0bf492fSCédric Le Goater * The device attribute type contains the memory mapped offset of the 263*d0bf492fSCédric Le Goater * APLIC register (range 0x0000-0x3FFF) and it must be 4-byte aligned. 264*d0bf492fSCédric Le Goater */ 265*d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_GRP_APLIC 3 266*d0bf492fSCédric Le Goater 267*d0bf492fSCédric Le Goater /* 268*d0bf492fSCédric Le Goater * The lower 12-bits of the device attribute type contains the iselect 269*d0bf492fSCédric Le Goater * value of the IMSIC register (range 0x70-0xFF) whereas the higher order 270*d0bf492fSCédric Le Goater * bits contains the VCPU id. 271*d0bf492fSCédric Le Goater */ 272*d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_GRP_IMSIC 4 273*d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS 12 274*d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK \ 275*d0bf492fSCédric Le Goater ((1U << KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS) - 1) 276*d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_IMSIC_MKATTR(__vcpu, __isel) \ 277*d0bf492fSCédric Le Goater (((__vcpu) << KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS) | \ 278*d0bf492fSCédric Le Goater ((__isel) & KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK)) 279*d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_IMSIC_GET_ISEL(__attr) \ 280*d0bf492fSCédric Le Goater ((__attr) & KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK) 281*d0bf492fSCédric Le Goater #define KVM_DEV_RISCV_AIA_IMSIC_GET_VCPU(__attr) \ 282*d0bf492fSCédric Le Goater ((__attr) >> KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS) 283*d0bf492fSCédric Le Goater 284*d0bf492fSCédric Le Goater /* One single KVM irqchip, ie. the AIA */ 285*d0bf492fSCédric Le Goater #define KVM_NR_IRQCHIPS 1 286*d0bf492fSCédric Le Goater 287b91a0fa7SYifei Jiang #endif 288b91a0fa7SYifei Jiang 289b91a0fa7SYifei Jiang #endif /* __LINUX_KVM_RISCV_H */ 290