13ebdd119Saurel32 /*
23ebdd119Saurel32 NetWinder Floating Point Emulator
33ebdd119Saurel32 (c) Rebel.COM, 1998,1999
43ebdd119Saurel32
53ebdd119Saurel32 Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
63ebdd119Saurel32
73ebdd119Saurel32 This program is free software; you can redistribute it and/or modify
83ebdd119Saurel32 it under the terms of the GNU General Public License as published by
93ebdd119Saurel32 the Free Software Foundation; either version 2 of the License, or
103ebdd119Saurel32 (at your option) any later version.
113ebdd119Saurel32
123ebdd119Saurel32 This program is distributed in the hope that it will be useful,
133ebdd119Saurel32 but WITHOUT ANY WARRANTY; without even the implied warranty of
143ebdd119Saurel32 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
153ebdd119Saurel32 GNU General Public License for more details.
163ebdd119Saurel32
173ebdd119Saurel32 You should have received a copy of the GNU General Public License
1870539e18SBlue Swirl along with this program; if not, see <http://www.gnu.org/licenses/>.
193ebdd119Saurel32 */
203ebdd119Saurel32
21*2a6a4076SMarkus Armbruster #ifndef FPOPCODE_H
22*2a6a4076SMarkus Armbruster #define FPOPCODE_H
233ebdd119Saurel32
243ebdd119Saurel32 /*
253ebdd119Saurel32 ARM Floating Point Instruction Classes
263ebdd119Saurel32 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
273ebdd119Saurel32 |c o n d|1 1 0 P|U|u|W|L| Rn |v| Fd |0|0|0|1| o f f s e t | CPDT
283ebdd119Saurel32 |c o n d|1 1 0 P|U|w|W|L| Rn |x| Fd |0|0|0|1| o f f s e t | CPDT
293ebdd119Saurel32 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
303ebdd119Saurel32 |c o n d|1 1 1 0|a|b|c|d|e| Fn |j| Fd |0|0|0|1|f|g|h|0|i| Fm | CPDO
313ebdd119Saurel32 |c o n d|1 1 1 0|a|b|c|L|e| Fn | Rd |0|0|0|1|f|g|h|1|i| Fm | CPRT
323ebdd119Saurel32 |c o n d|1 1 1 0|a|b|c|1|e| Fn |1|1|1|1|0|0|0|1|f|g|h|1|i| Fm | comparisons
333ebdd119Saurel32 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
343ebdd119Saurel32
353ebdd119Saurel32 CPDT data transfer instructions
363ebdd119Saurel32 LDF, STF, LFM, SFM
373ebdd119Saurel32
383ebdd119Saurel32 CPDO dyadic arithmetic instructions
393ebdd119Saurel32 ADF, MUF, SUF, RSF, DVF, RDF,
403ebdd119Saurel32 POW, RPW, RMF, FML, FDV, FRD, POL
413ebdd119Saurel32
423ebdd119Saurel32 CPDO monadic arithmetic instructions
433ebdd119Saurel32 MVF, MNF, ABS, RND, SQT, LOG, LGN, EXP,
443ebdd119Saurel32 SIN, COS, TAN, ASN, ACS, ATN, URD, NRM
453ebdd119Saurel32
463ebdd119Saurel32 CPRT joint arithmetic/data transfer instructions
473ebdd119Saurel32 FIX (arithmetic followed by load/store)
483ebdd119Saurel32 FLT (load/store followed by arithmetic)
493ebdd119Saurel32 CMF, CNF CMFE, CNFE (comparisons)
503ebdd119Saurel32 WFS, RFS (write/read floating point status register)
513ebdd119Saurel32 WFC, RFC (write/read floating point control register)
523ebdd119Saurel32
533ebdd119Saurel32 cond condition codes
543ebdd119Saurel32 P pre/post index bit: 0 = postindex, 1 = preindex
553ebdd119Saurel32 U up/down bit: 0 = stack grows down, 1 = stack grows up
563ebdd119Saurel32 W write back bit: 1 = update base register (Rn)
573ebdd119Saurel32 L load/store bit: 0 = store, 1 = load
583ebdd119Saurel32 Rn base register
593ebdd119Saurel32 Rd destination/source register
603ebdd119Saurel32 Fd floating point destination register
613ebdd119Saurel32 Fn floating point source register
623ebdd119Saurel32 Fm floating point source register or floating point constant
633ebdd119Saurel32
643ebdd119Saurel32 uv transfer length (TABLE 1)
653ebdd119Saurel32 wx register count (TABLE 2)
663ebdd119Saurel32 abcd arithmetic opcode (TABLES 3 & 4)
673ebdd119Saurel32 ef destination size (rounding precision) (TABLE 5)
683ebdd119Saurel32 gh rounding mode (TABLE 6)
693ebdd119Saurel32 j dyadic/monadic bit: 0 = dyadic, 1 = monadic
703ebdd119Saurel32 i constant bit: 1 = constant (TABLE 6)
713ebdd119Saurel32 */
723ebdd119Saurel32
733ebdd119Saurel32 /*
743ebdd119Saurel32 TABLE 1
753ebdd119Saurel32 +-------------------------+---+---+---------+---------+
763ebdd119Saurel32 | Precision | u | v | FPSR.EP | length |
773ebdd119Saurel32 +-------------------------+---+---+---------+---------+
7875dfbc16SPeter Maydell | Single | 0 | 0 | x | 1 words |
7975dfbc16SPeter Maydell | Double | 1 | 1 | x | 2 words |
8075dfbc16SPeter Maydell | Extended | 1 | 1 | x | 3 words |
8175dfbc16SPeter Maydell | Packed decimal | 1 | 1 | 0 | 3 words |
8275dfbc16SPeter Maydell | Expanded packed decimal | 1 | 1 | 1 | 4 words |
833ebdd119Saurel32 +-------------------------+---+---+---------+---------+
843ebdd119Saurel32 Note: x = don't care
853ebdd119Saurel32 */
863ebdd119Saurel32
873ebdd119Saurel32 /*
883ebdd119Saurel32 TABLE 2
893ebdd119Saurel32 +---+---+---------------------------------+
903ebdd119Saurel32 | w | x | Number of registers to transfer |
913ebdd119Saurel32 +---+---+---------------------------------+
9275dfbc16SPeter Maydell | 0 | 1 | 1 |
9375dfbc16SPeter Maydell | 1 | 0 | 2 |
9475dfbc16SPeter Maydell | 1 | 1 | 3 |
9575dfbc16SPeter Maydell | 0 | 0 | 4 |
963ebdd119Saurel32 +---+---+---------------------------------+
973ebdd119Saurel32 */
983ebdd119Saurel32
993ebdd119Saurel32 /*
1003ebdd119Saurel32 TABLE 3: Dyadic Floating Point Opcodes
1013ebdd119Saurel32 +---+---+---+---+----------+-----------------------+-----------------------+
1023ebdd119Saurel32 | a | b | c | d | Mnemonic | Description | Operation |
1033ebdd119Saurel32 +---+---+---+---+----------+-----------------------+-----------------------+
1043ebdd119Saurel32 | 0 | 0 | 0 | 0 | ADF | Add | Fd := Fn + Fm |
1053ebdd119Saurel32 | 0 | 0 | 0 | 1 | MUF | Multiply | Fd := Fn * Fm |
1063ebdd119Saurel32 | 0 | 0 | 1 | 0 | SUF | Subtract | Fd := Fn - Fm |
1073ebdd119Saurel32 | 0 | 0 | 1 | 1 | RSF | Reverse subtract | Fd := Fm - Fn |
1083ebdd119Saurel32 | 0 | 1 | 0 | 0 | DVF | Divide | Fd := Fn / Fm |
1093ebdd119Saurel32 | 0 | 1 | 0 | 1 | RDF | Reverse divide | Fd := Fm / Fn |
1103ebdd119Saurel32 | 0 | 1 | 1 | 0 | POW | Power | Fd := Fn ^ Fm |
1113ebdd119Saurel32 | 0 | 1 | 1 | 1 | RPW | Reverse power | Fd := Fm ^ Fn |
1123ebdd119Saurel32 | 1 | 0 | 0 | 0 | RMF | Remainder | Fd := IEEE rem(Fn/Fm) |
1133ebdd119Saurel32 | 1 | 0 | 0 | 1 | FML | Fast Multiply | Fd := Fn * Fm |
1143ebdd119Saurel32 | 1 | 0 | 1 | 0 | FDV | Fast Divide | Fd := Fn / Fm |
1153ebdd119Saurel32 | 1 | 0 | 1 | 1 | FRD | Fast reverse divide | Fd := Fm / Fn |
1163ebdd119Saurel32 | 1 | 1 | 0 | 0 | POL | Polar angle (ArcTan2) | Fd := arctan2(Fn,Fm) |
1173ebdd119Saurel32 | 1 | 1 | 0 | 1 | | undefined instruction | trap |
1183ebdd119Saurel32 | 1 | 1 | 1 | 0 | | undefined instruction | trap |
1193ebdd119Saurel32 | 1 | 1 | 1 | 1 | | undefined instruction | trap |
1203ebdd119Saurel32 +---+---+---+---+----------+-----------------------+-----------------------+
1213ebdd119Saurel32 Note: POW, RPW, POL are deprecated, and are available for backwards
1223ebdd119Saurel32 compatibility only.
1233ebdd119Saurel32 */
1243ebdd119Saurel32
1253ebdd119Saurel32 /*
1263ebdd119Saurel32 TABLE 4: Monadic Floating Point Opcodes
1273ebdd119Saurel32 +---+---+---+---+----------+-----------------------+-----------------------+
1283ebdd119Saurel32 | a | b | c | d | Mnemonic | Description | Operation |
1293ebdd119Saurel32 +---+---+---+---+----------+-----------------------+-----------------------+
1303ebdd119Saurel32 | 0 | 0 | 0 | 0 | MVF | Move | Fd := Fm |
1313ebdd119Saurel32 | 0 | 0 | 0 | 1 | MNF | Move negated | Fd := - Fm |
1323ebdd119Saurel32 | 0 | 0 | 1 | 0 | ABS | Absolute value | Fd := abs(Fm) |
1333ebdd119Saurel32 | 0 | 0 | 1 | 1 | RND | Round to integer | Fd := int(Fm) |
1343ebdd119Saurel32 | 0 | 1 | 0 | 0 | SQT | Square root | Fd := sqrt(Fm) |
1353ebdd119Saurel32 | 0 | 1 | 0 | 1 | LOG | Log base 10 | Fd := log10(Fm) |
1363ebdd119Saurel32 | 0 | 1 | 1 | 0 | LGN | Log base e | Fd := ln(Fm) |
1373ebdd119Saurel32 | 0 | 1 | 1 | 1 | EXP | Exponent | Fd := e ^ Fm |
1383ebdd119Saurel32 | 1 | 0 | 0 | 0 | SIN | Sine | Fd := sin(Fm) |
1393ebdd119Saurel32 | 1 | 0 | 0 | 1 | COS | Cosine | Fd := cos(Fm) |
1403ebdd119Saurel32 | 1 | 0 | 1 | 0 | TAN | Tangent | Fd := tan(Fm) |
1413ebdd119Saurel32 | 1 | 0 | 1 | 1 | ASN | Arc Sine | Fd := arcsin(Fm) |
1423ebdd119Saurel32 | 1 | 1 | 0 | 0 | ACS | Arc Cosine | Fd := arccos(Fm) |
1433ebdd119Saurel32 | 1 | 1 | 0 | 1 | ATN | Arc Tangent | Fd := arctan(Fm) |
1443ebdd119Saurel32 | 1 | 1 | 1 | 0 | URD | Unnormalized round | Fd := int(Fm) |
1453ebdd119Saurel32 | 1 | 1 | 1 | 1 | NRM | Normalize | Fd := norm(Fm) |
1463ebdd119Saurel32 +---+---+---+---+----------+-----------------------+-----------------------+
1473ebdd119Saurel32 Note: LOG, LGN, EXP, SIN, COS, TAN, ASN, ACS, ATN are deprecated, and are
1483ebdd119Saurel32 available for backwards compatibility only.
1493ebdd119Saurel32 */
1503ebdd119Saurel32
1513ebdd119Saurel32 /*
1523ebdd119Saurel32 TABLE 5
1533ebdd119Saurel32 +-------------------------+---+---+
1543ebdd119Saurel32 | Rounding Precision | e | f |
1553ebdd119Saurel32 +-------------------------+---+---+
15675dfbc16SPeter Maydell | IEEE Single precision | 0 | 0 |
15775dfbc16SPeter Maydell | IEEE Double precision | 0 | 1 |
15875dfbc16SPeter Maydell | IEEE Extended precision | 1 | 0 |
15975dfbc16SPeter Maydell | undefined (trap) | 1 | 1 |
1603ebdd119Saurel32 +-------------------------+---+---+
1613ebdd119Saurel32 */
1623ebdd119Saurel32
1633ebdd119Saurel32 /*
1643ebdd119Saurel32 TABLE 5
1653ebdd119Saurel32 +---------------------------------+---+---+
1663ebdd119Saurel32 | Rounding Mode | g | h |
1673ebdd119Saurel32 +---------------------------------+---+---+
16875dfbc16SPeter Maydell | Round to nearest (default) | 0 | 0 |
16975dfbc16SPeter Maydell | Round toward plus infinity | 0 | 1 |
17075dfbc16SPeter Maydell | Round toward negative infinity | 1 | 0 |
17175dfbc16SPeter Maydell | Round toward zero | 1 | 1 |
1723ebdd119Saurel32 +---------------------------------+---+---+
1733ebdd119Saurel32 */
1743ebdd119Saurel32
1753ebdd119Saurel32 /*
1763ebdd119Saurel32 ===
1773ebdd119Saurel32 === Definitions for load and store instructions
1783ebdd119Saurel32 ===
1793ebdd119Saurel32 */
1803ebdd119Saurel32
1813ebdd119Saurel32 /* bit masks */
1823ebdd119Saurel32 #define BIT_PREINDEX 0x01000000
1833ebdd119Saurel32 #define BIT_UP 0x00800000
1843ebdd119Saurel32 #define BIT_WRITE_BACK 0x00200000
1853ebdd119Saurel32 #define BIT_LOAD 0x00100000
1863ebdd119Saurel32
1873ebdd119Saurel32 /* masks for load/store */
1883ebdd119Saurel32 #define MASK_CPDT 0x0c000000 /* data processing opcode */
1893ebdd119Saurel32 #define MASK_OFFSET 0x000000ff
1903ebdd119Saurel32 #define MASK_TRANSFER_LENGTH 0x00408000
1913ebdd119Saurel32 #define MASK_REGISTER_COUNT MASK_TRANSFER_LENGTH
1923ebdd119Saurel32 #define MASK_COPROCESSOR 0x00000f00
1933ebdd119Saurel32
1943ebdd119Saurel32 /* Tests for transfer length */
1953ebdd119Saurel32 #define TRANSFER_SINGLE 0x00000000
1963ebdd119Saurel32 #define TRANSFER_DOUBLE 0x00008000
1973ebdd119Saurel32 #define TRANSFER_EXTENDED 0x00400000
1983ebdd119Saurel32 #define TRANSFER_PACKED MASK_TRANSFER_LENGTH
1993ebdd119Saurel32
2003ebdd119Saurel32 /* Get the coprocessor number from the opcode. */
2013ebdd119Saurel32 #define getCoprocessorNumber(opcode) ((opcode & MASK_COPROCESSOR) >> 8)
2023ebdd119Saurel32
2033ebdd119Saurel32 /* Get the offset from the opcode. */
2043ebdd119Saurel32 #define getOffset(opcode) (opcode & MASK_OFFSET)
2053ebdd119Saurel32
2063ebdd119Saurel32 /* Tests for specific data transfer load/store opcodes. */
2073ebdd119Saurel32 #define TEST_OPCODE(opcode,mask) (((opcode) & (mask)) == (mask))
2083ebdd119Saurel32
2093ebdd119Saurel32 #define LOAD_OP(opcode) TEST_OPCODE((opcode),MASK_CPDT | BIT_LOAD)
2103ebdd119Saurel32 #define STORE_OP(opcode) ((opcode & (MASK_CPDT | BIT_LOAD)) == MASK_CPDT)
2113ebdd119Saurel32
2123ebdd119Saurel32 #define LDF_OP(opcode) (LOAD_OP(opcode) && (getCoprocessorNumber(opcode) == 1))
2133ebdd119Saurel32 #define LFM_OP(opcode) (LOAD_OP(opcode) && (getCoprocessorNumber(opcode) == 2))
2143ebdd119Saurel32 #define STF_OP(opcode) (STORE_OP(opcode) && (getCoprocessorNumber(opcode) == 1))
2153ebdd119Saurel32 #define SFM_OP(opcode) (STORE_OP(opcode) && (getCoprocessorNumber(opcode) == 2))
2163ebdd119Saurel32
2173ebdd119Saurel32 #define PREINDEXED(opcode) ((opcode & BIT_PREINDEX) != 0)
2183ebdd119Saurel32 #define POSTINDEXED(opcode) ((opcode & BIT_PREINDEX) == 0)
2193ebdd119Saurel32 #define BIT_UP_SET(opcode) ((opcode & BIT_UP) != 0)
2203ebdd119Saurel32 #define BIT_UP_CLEAR(opcode) ((opcode & BIT_DOWN) == 0)
2213ebdd119Saurel32 #define WRITE_BACK(opcode) ((opcode & BIT_WRITE_BACK) != 0)
2223ebdd119Saurel32 #define LOAD(opcode) ((opcode & BIT_LOAD) != 0)
2233ebdd119Saurel32 #define STORE(opcode) ((opcode & BIT_LOAD) == 0)
2243ebdd119Saurel32
2253ebdd119Saurel32 /*
2263ebdd119Saurel32 ===
2273ebdd119Saurel32 === Definitions for arithmetic instructions
2283ebdd119Saurel32 ===
2293ebdd119Saurel32 */
2303ebdd119Saurel32 /* bit masks */
2313ebdd119Saurel32 #define BIT_MONADIC 0x00008000
2323ebdd119Saurel32 #define BIT_CONSTANT 0x00000008
2333ebdd119Saurel32
2343ebdd119Saurel32 #define CONSTANT_FM(opcode) ((opcode & BIT_CONSTANT) != 0)
2353ebdd119Saurel32 #define MONADIC_INSTRUCTION(opcode) ((opcode & BIT_MONADIC) != 0)
2363ebdd119Saurel32
2373ebdd119Saurel32 /* instruction identification masks */
2383ebdd119Saurel32 #define MASK_CPDO 0x0e000000 /* arithmetic opcode */
2393ebdd119Saurel32 #define MASK_ARITHMETIC_OPCODE 0x00f08000
2403ebdd119Saurel32 #define MASK_DESTINATION_SIZE 0x00080080
2413ebdd119Saurel32
2423ebdd119Saurel32 /* dyadic arithmetic opcodes. */
2433ebdd119Saurel32 #define ADF_CODE 0x00000000
2443ebdd119Saurel32 #define MUF_CODE 0x00100000
2453ebdd119Saurel32 #define SUF_CODE 0x00200000
2463ebdd119Saurel32 #define RSF_CODE 0x00300000
2473ebdd119Saurel32 #define DVF_CODE 0x00400000
2483ebdd119Saurel32 #define RDF_CODE 0x00500000
2493ebdd119Saurel32 #define POW_CODE 0x00600000
2503ebdd119Saurel32 #define RPW_CODE 0x00700000
2513ebdd119Saurel32 #define RMF_CODE 0x00800000
2523ebdd119Saurel32 #define FML_CODE 0x00900000
2533ebdd119Saurel32 #define FDV_CODE 0x00a00000
2543ebdd119Saurel32 #define FRD_CODE 0x00b00000
2553ebdd119Saurel32 #define POL_CODE 0x00c00000
2563ebdd119Saurel32 /* 0x00d00000 is an invalid dyadic arithmetic opcode */
2573ebdd119Saurel32 /* 0x00e00000 is an invalid dyadic arithmetic opcode */
2583ebdd119Saurel32 /* 0x00f00000 is an invalid dyadic arithmetic opcode */
2593ebdd119Saurel32
2603ebdd119Saurel32 /* monadic arithmetic opcodes. */
2613ebdd119Saurel32 #define MVF_CODE 0x00008000
2623ebdd119Saurel32 #define MNF_CODE 0x00108000
2633ebdd119Saurel32 #define ABS_CODE 0x00208000
2643ebdd119Saurel32 #define RND_CODE 0x00308000
2653ebdd119Saurel32 #define SQT_CODE 0x00408000
2663ebdd119Saurel32 #define LOG_CODE 0x00508000
2673ebdd119Saurel32 #define LGN_CODE 0x00608000
2683ebdd119Saurel32 #define EXP_CODE 0x00708000
2693ebdd119Saurel32 #define SIN_CODE 0x00808000
2703ebdd119Saurel32 #define COS_CODE 0x00908000
2713ebdd119Saurel32 #define TAN_CODE 0x00a08000
2723ebdd119Saurel32 #define ASN_CODE 0x00b08000
2733ebdd119Saurel32 #define ACS_CODE 0x00c08000
2743ebdd119Saurel32 #define ATN_CODE 0x00d08000
2753ebdd119Saurel32 #define URD_CODE 0x00e08000
2763ebdd119Saurel32 #define NRM_CODE 0x00f08000
2773ebdd119Saurel32
2783ebdd119Saurel32 /*
2793ebdd119Saurel32 ===
2803ebdd119Saurel32 === Definitions for register transfer and comparison instructions
2813ebdd119Saurel32 ===
2823ebdd119Saurel32 */
2833ebdd119Saurel32
2843ebdd119Saurel32 #define MASK_CPRT 0x0e000010 /* register transfer opcode */
2853ebdd119Saurel32 #define MASK_CPRT_CODE 0x00f00000
2863ebdd119Saurel32 #define FLT_CODE 0x00000000
2873ebdd119Saurel32 #define FIX_CODE 0x00100000
2883ebdd119Saurel32 #define WFS_CODE 0x00200000
2893ebdd119Saurel32 #define RFS_CODE 0x00300000
2903ebdd119Saurel32 #define WFC_CODE 0x00400000
2913ebdd119Saurel32 #define RFC_CODE 0x00500000
2923ebdd119Saurel32 #define CMF_CODE 0x00900000
2933ebdd119Saurel32 #define CNF_CODE 0x00b00000
2943ebdd119Saurel32 #define CMFE_CODE 0x00d00000
2953ebdd119Saurel32 #define CNFE_CODE 0x00f00000
2963ebdd119Saurel32
2973ebdd119Saurel32 /*
2983ebdd119Saurel32 ===
2993ebdd119Saurel32 === Common definitions
3003ebdd119Saurel32 ===
3013ebdd119Saurel32 */
3023ebdd119Saurel32
3033ebdd119Saurel32 /* register masks */
3043ebdd119Saurel32 #define MASK_Rd 0x0000f000
3053ebdd119Saurel32 #define MASK_Rn 0x000f0000
3063ebdd119Saurel32 #define MASK_Fd 0x00007000
3073ebdd119Saurel32 #define MASK_Fm 0x00000007
3083ebdd119Saurel32 #define MASK_Fn 0x00070000
3093ebdd119Saurel32
3103ebdd119Saurel32 /* condition code masks */
3113ebdd119Saurel32 #define CC_MASK 0xf0000000
3123ebdd119Saurel32 #define CC_NEGATIVE 0x80000000
3133ebdd119Saurel32 #define CC_ZERO 0x40000000
3143ebdd119Saurel32 #define CC_CARRY 0x20000000
3153ebdd119Saurel32 #define CC_OVERFLOW 0x10000000
3163ebdd119Saurel32 #define CC_EQ 0x00000000
3173ebdd119Saurel32 #define CC_NE 0x10000000
3183ebdd119Saurel32 #define CC_CS 0x20000000
3193ebdd119Saurel32 #define CC_HS CC_CS
3203ebdd119Saurel32 #define CC_CC 0x30000000
3213ebdd119Saurel32 #define CC_LO CC_CC
3223ebdd119Saurel32 #define CC_MI 0x40000000
3233ebdd119Saurel32 #define CC_PL 0x50000000
3243ebdd119Saurel32 #define CC_VS 0x60000000
3253ebdd119Saurel32 #define CC_VC 0x70000000
3263ebdd119Saurel32 #define CC_HI 0x80000000
3273ebdd119Saurel32 #define CC_LS 0x90000000
3283ebdd119Saurel32 #define CC_GE 0xa0000000
3293ebdd119Saurel32 #define CC_LT 0xb0000000
3303ebdd119Saurel32 #define CC_GT 0xc0000000
3313ebdd119Saurel32 #define CC_LE 0xd0000000
3323ebdd119Saurel32 #define CC_AL 0xe0000000
3333ebdd119Saurel32 #define CC_NV 0xf0000000
3343ebdd119Saurel32
3353ebdd119Saurel32 /* rounding masks/values */
3363ebdd119Saurel32 #define MASK_ROUNDING_MODE 0x00000060
3373ebdd119Saurel32 #define ROUND_TO_NEAREST 0x00000000
3383ebdd119Saurel32 #define ROUND_TO_PLUS_INFINITY 0x00000020
3393ebdd119Saurel32 #define ROUND_TO_MINUS_INFINITY 0x00000040
3403ebdd119Saurel32 #define ROUND_TO_ZERO 0x00000060
3413ebdd119Saurel32
3423ebdd119Saurel32 #define MASK_ROUNDING_PRECISION 0x00080080
3433ebdd119Saurel32 #define ROUND_SINGLE 0x00000000
3443ebdd119Saurel32 #define ROUND_DOUBLE 0x00000080
3453ebdd119Saurel32 #define ROUND_EXTENDED 0x00080000
3463ebdd119Saurel32
3473ebdd119Saurel32 /* Get the condition code from the opcode. */
3483ebdd119Saurel32 #define getCondition(opcode) (opcode >> 28)
3493ebdd119Saurel32
3503ebdd119Saurel32 /* Get the source register from the opcode. */
3513ebdd119Saurel32 #define getRn(opcode) ((opcode & MASK_Rn) >> 16)
3523ebdd119Saurel32
3533ebdd119Saurel32 /* Get the destination floating point register from the opcode. */
3543ebdd119Saurel32 #define getFd(opcode) ((opcode & MASK_Fd) >> 12)
3553ebdd119Saurel32
3563ebdd119Saurel32 /* Get the first source floating point register from the opcode. */
3573ebdd119Saurel32 #define getFn(opcode) ((opcode & MASK_Fn) >> 16)
3583ebdd119Saurel32
3593ebdd119Saurel32 /* Get the second source floating point register from the opcode. */
3603ebdd119Saurel32 #define getFm(opcode) (opcode & MASK_Fm)
3613ebdd119Saurel32
3623ebdd119Saurel32 /* Get the destination register from the opcode. */
3633ebdd119Saurel32 #define getRd(opcode) ((opcode & MASK_Rd) >> 12)
3643ebdd119Saurel32
3653ebdd119Saurel32 /* Get the rounding mode from the opcode. */
3663ebdd119Saurel32 #define getRoundingMode(opcode) ((opcode & MASK_ROUNDING_MODE) >> 5)
3673ebdd119Saurel32
368d4fa8d90SBlue Swirl extern const floatx80 floatx80Constant[];
369d4fa8d90SBlue Swirl extern const float64 float64Constant[];
370d4fa8d90SBlue Swirl extern const float32 float32Constant[];
371d4fa8d90SBlue Swirl
getExtendedConstant(const unsigned int nIndex)3727ccfb2ebSblueswir1 static inline floatx80 getExtendedConstant(const unsigned int nIndex)
3733ebdd119Saurel32 {
3743ebdd119Saurel32 return floatx80Constant[nIndex];
3753ebdd119Saurel32 }
3763ebdd119Saurel32
getDoubleConstant(const unsigned int nIndex)3777ccfb2ebSblueswir1 static inline float64 getDoubleConstant(const unsigned int nIndex)
3783ebdd119Saurel32 {
3793ebdd119Saurel32 return float64Constant[nIndex];
3803ebdd119Saurel32 }
3813ebdd119Saurel32
getSingleConstant(const unsigned int nIndex)3827ccfb2ebSblueswir1 static inline float32 getSingleConstant(const unsigned int nIndex)
3833ebdd119Saurel32 {
3843ebdd119Saurel32 return float32Constant[nIndex];
3853ebdd119Saurel32 }
3863ebdd119Saurel32
38764b85a8fSBlue Swirl unsigned int getRegisterCount(const unsigned int opcode);
38864b85a8fSBlue Swirl unsigned int getDestinationSize(const unsigned int opcode);
3893ebdd119Saurel32
3903ebdd119Saurel32 #endif
391