1*3ebdd119Saurel32 /* 2*3ebdd119Saurel32 NetWinder Floating Point Emulator 3*3ebdd119Saurel32 (c) Rebel.COM, 1998,1999 4*3ebdd119Saurel32 5*3ebdd119Saurel32 Direct questions, comments to Scott Bambrough <scottb@netwinder.org> 6*3ebdd119Saurel32 7*3ebdd119Saurel32 This program is free software; you can redistribute it and/or modify 8*3ebdd119Saurel32 it under the terms of the GNU General Public License as published by 9*3ebdd119Saurel32 the Free Software Foundation; either version 2 of the License, or 10*3ebdd119Saurel32 (at your option) any later version. 11*3ebdd119Saurel32 12*3ebdd119Saurel32 This program is distributed in the hope that it will be useful, 13*3ebdd119Saurel32 but WITHOUT ANY WARRANTY; without even the implied warranty of 14*3ebdd119Saurel32 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15*3ebdd119Saurel32 GNU General Public License for more details. 16*3ebdd119Saurel32 17*3ebdd119Saurel32 You should have received a copy of the GNU General Public License 18*3ebdd119Saurel32 along with this program; if not, write to the Free Software 19*3ebdd119Saurel32 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20*3ebdd119Saurel32 */ 21*3ebdd119Saurel32 22*3ebdd119Saurel32 #ifndef __FPOPCODE_H__ 23*3ebdd119Saurel32 #define __FPOPCODE_H__ 24*3ebdd119Saurel32 25*3ebdd119Saurel32 /* 26*3ebdd119Saurel32 ARM Floating Point Instruction Classes 27*3ebdd119Saurel32 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 28*3ebdd119Saurel32 |c o n d|1 1 0 P|U|u|W|L| Rn |v| Fd |0|0|0|1| o f f s e t | CPDT 29*3ebdd119Saurel32 |c o n d|1 1 0 P|U|w|W|L| Rn |x| Fd |0|0|0|1| o f f s e t | CPDT 30*3ebdd119Saurel32 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 31*3ebdd119Saurel32 |c o n d|1 1 1 0|a|b|c|d|e| Fn |j| Fd |0|0|0|1|f|g|h|0|i| Fm | CPDO 32*3ebdd119Saurel32 |c o n d|1 1 1 0|a|b|c|L|e| Fn | Rd |0|0|0|1|f|g|h|1|i| Fm | CPRT 33*3ebdd119Saurel32 |c o n d|1 1 1 0|a|b|c|1|e| Fn |1|1|1|1|0|0|0|1|f|g|h|1|i| Fm | comparisons 34*3ebdd119Saurel32 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 35*3ebdd119Saurel32 36*3ebdd119Saurel32 CPDT data transfer instructions 37*3ebdd119Saurel32 LDF, STF, LFM, SFM 38*3ebdd119Saurel32 39*3ebdd119Saurel32 CPDO dyadic arithmetic instructions 40*3ebdd119Saurel32 ADF, MUF, SUF, RSF, DVF, RDF, 41*3ebdd119Saurel32 POW, RPW, RMF, FML, FDV, FRD, POL 42*3ebdd119Saurel32 43*3ebdd119Saurel32 CPDO monadic arithmetic instructions 44*3ebdd119Saurel32 MVF, MNF, ABS, RND, SQT, LOG, LGN, EXP, 45*3ebdd119Saurel32 SIN, COS, TAN, ASN, ACS, ATN, URD, NRM 46*3ebdd119Saurel32 47*3ebdd119Saurel32 CPRT joint arithmetic/data transfer instructions 48*3ebdd119Saurel32 FIX (arithmetic followed by load/store) 49*3ebdd119Saurel32 FLT (load/store followed by arithmetic) 50*3ebdd119Saurel32 CMF, CNF CMFE, CNFE (comparisons) 51*3ebdd119Saurel32 WFS, RFS (write/read floating point status register) 52*3ebdd119Saurel32 WFC, RFC (write/read floating point control register) 53*3ebdd119Saurel32 54*3ebdd119Saurel32 cond condition codes 55*3ebdd119Saurel32 P pre/post index bit: 0 = postindex, 1 = preindex 56*3ebdd119Saurel32 U up/down bit: 0 = stack grows down, 1 = stack grows up 57*3ebdd119Saurel32 W write back bit: 1 = update base register (Rn) 58*3ebdd119Saurel32 L load/store bit: 0 = store, 1 = load 59*3ebdd119Saurel32 Rn base register 60*3ebdd119Saurel32 Rd destination/source register 61*3ebdd119Saurel32 Fd floating point destination register 62*3ebdd119Saurel32 Fn floating point source register 63*3ebdd119Saurel32 Fm floating point source register or floating point constant 64*3ebdd119Saurel32 65*3ebdd119Saurel32 uv transfer length (TABLE 1) 66*3ebdd119Saurel32 wx register count (TABLE 2) 67*3ebdd119Saurel32 abcd arithmetic opcode (TABLES 3 & 4) 68*3ebdd119Saurel32 ef destination size (rounding precision) (TABLE 5) 69*3ebdd119Saurel32 gh rounding mode (TABLE 6) 70*3ebdd119Saurel32 j dyadic/monadic bit: 0 = dyadic, 1 = monadic 71*3ebdd119Saurel32 i constant bit: 1 = constant (TABLE 6) 72*3ebdd119Saurel32 */ 73*3ebdd119Saurel32 74*3ebdd119Saurel32 /* 75*3ebdd119Saurel32 TABLE 1 76*3ebdd119Saurel32 +-------------------------+---+---+---------+---------+ 77*3ebdd119Saurel32 | Precision | u | v | FPSR.EP | length | 78*3ebdd119Saurel32 +-------------------------+---+---+---------+---------+ 79*3ebdd119Saurel32 | Single | 0 � 0 | x | 1 words | 80*3ebdd119Saurel32 | Double | 1 � 1 | x | 2 words | 81*3ebdd119Saurel32 | Extended | 1 � 1 | x | 3 words | 82*3ebdd119Saurel32 | Packed decimal | 1 � 1 | 0 | 3 words | 83*3ebdd119Saurel32 | Expanded packed decimal | 1 � 1 | 1 | 4 words | 84*3ebdd119Saurel32 +-------------------------+---+---+---------+---------+ 85*3ebdd119Saurel32 Note: x = don't care 86*3ebdd119Saurel32 */ 87*3ebdd119Saurel32 88*3ebdd119Saurel32 /* 89*3ebdd119Saurel32 TABLE 2 90*3ebdd119Saurel32 +---+---+---------------------------------+ 91*3ebdd119Saurel32 | w | x | Number of registers to transfer | 92*3ebdd119Saurel32 +---+---+---------------------------------+ 93*3ebdd119Saurel32 | 0 � 1 | 1 | 94*3ebdd119Saurel32 | 1 � 0 | 2 | 95*3ebdd119Saurel32 | 1 � 1 | 3 | 96*3ebdd119Saurel32 | 0 � 0 | 4 | 97*3ebdd119Saurel32 +---+---+---------------------------------+ 98*3ebdd119Saurel32 */ 99*3ebdd119Saurel32 100*3ebdd119Saurel32 /* 101*3ebdd119Saurel32 TABLE 3: Dyadic Floating Point Opcodes 102*3ebdd119Saurel32 +---+---+---+---+----------+-----------------------+-----------------------+ 103*3ebdd119Saurel32 | a | b | c | d | Mnemonic | Description | Operation | 104*3ebdd119Saurel32 +---+---+---+---+----------+-----------------------+-----------------------+ 105*3ebdd119Saurel32 | 0 | 0 | 0 | 0 | ADF | Add | Fd := Fn + Fm | 106*3ebdd119Saurel32 | 0 | 0 | 0 | 1 | MUF | Multiply | Fd := Fn * Fm | 107*3ebdd119Saurel32 | 0 | 0 | 1 | 0 | SUF | Subtract | Fd := Fn - Fm | 108*3ebdd119Saurel32 | 0 | 0 | 1 | 1 | RSF | Reverse subtract | Fd := Fm - Fn | 109*3ebdd119Saurel32 | 0 | 1 | 0 | 0 | DVF | Divide | Fd := Fn / Fm | 110*3ebdd119Saurel32 | 0 | 1 | 0 | 1 | RDF | Reverse divide | Fd := Fm / Fn | 111*3ebdd119Saurel32 | 0 | 1 | 1 | 0 | POW | Power | Fd := Fn ^ Fm | 112*3ebdd119Saurel32 | 0 | 1 | 1 | 1 | RPW | Reverse power | Fd := Fm ^ Fn | 113*3ebdd119Saurel32 | 1 | 0 | 0 | 0 | RMF | Remainder | Fd := IEEE rem(Fn/Fm) | 114*3ebdd119Saurel32 | 1 | 0 | 0 | 1 | FML | Fast Multiply | Fd := Fn * Fm | 115*3ebdd119Saurel32 | 1 | 0 | 1 | 0 | FDV | Fast Divide | Fd := Fn / Fm | 116*3ebdd119Saurel32 | 1 | 0 | 1 | 1 | FRD | Fast reverse divide | Fd := Fm / Fn | 117*3ebdd119Saurel32 | 1 | 1 | 0 | 0 | POL | Polar angle (ArcTan2) | Fd := arctan2(Fn,Fm) | 118*3ebdd119Saurel32 | 1 | 1 | 0 | 1 | | undefined instruction | trap | 119*3ebdd119Saurel32 | 1 | 1 | 1 | 0 | | undefined instruction | trap | 120*3ebdd119Saurel32 | 1 | 1 | 1 | 1 | | undefined instruction | trap | 121*3ebdd119Saurel32 +---+---+---+---+----------+-----------------------+-----------------------+ 122*3ebdd119Saurel32 Note: POW, RPW, POL are deprecated, and are available for backwards 123*3ebdd119Saurel32 compatibility only. 124*3ebdd119Saurel32 */ 125*3ebdd119Saurel32 126*3ebdd119Saurel32 /* 127*3ebdd119Saurel32 TABLE 4: Monadic Floating Point Opcodes 128*3ebdd119Saurel32 +---+---+---+---+----------+-----------------------+-----------------------+ 129*3ebdd119Saurel32 | a | b | c | d | Mnemonic | Description | Operation | 130*3ebdd119Saurel32 +---+---+---+---+----------+-----------------------+-----------------------+ 131*3ebdd119Saurel32 | 0 | 0 | 0 | 0 | MVF | Move | Fd := Fm | 132*3ebdd119Saurel32 | 0 | 0 | 0 | 1 | MNF | Move negated | Fd := - Fm | 133*3ebdd119Saurel32 | 0 | 0 | 1 | 0 | ABS | Absolute value | Fd := abs(Fm) | 134*3ebdd119Saurel32 | 0 | 0 | 1 | 1 | RND | Round to integer | Fd := int(Fm) | 135*3ebdd119Saurel32 | 0 | 1 | 0 | 0 | SQT | Square root | Fd := sqrt(Fm) | 136*3ebdd119Saurel32 | 0 | 1 | 0 | 1 | LOG | Log base 10 | Fd := log10(Fm) | 137*3ebdd119Saurel32 | 0 | 1 | 1 | 0 | LGN | Log base e | Fd := ln(Fm) | 138*3ebdd119Saurel32 | 0 | 1 | 1 | 1 | EXP | Exponent | Fd := e ^ Fm | 139*3ebdd119Saurel32 | 1 | 0 | 0 | 0 | SIN | Sine | Fd := sin(Fm) | 140*3ebdd119Saurel32 | 1 | 0 | 0 | 1 | COS | Cosine | Fd := cos(Fm) | 141*3ebdd119Saurel32 | 1 | 0 | 1 | 0 | TAN | Tangent | Fd := tan(Fm) | 142*3ebdd119Saurel32 | 1 | 0 | 1 | 1 | ASN | Arc Sine | Fd := arcsin(Fm) | 143*3ebdd119Saurel32 | 1 | 1 | 0 | 0 | ACS | Arc Cosine | Fd := arccos(Fm) | 144*3ebdd119Saurel32 | 1 | 1 | 0 | 1 | ATN | Arc Tangent | Fd := arctan(Fm) | 145*3ebdd119Saurel32 | 1 | 1 | 1 | 0 | URD | Unnormalized round | Fd := int(Fm) | 146*3ebdd119Saurel32 | 1 | 1 | 1 | 1 | NRM | Normalize | Fd := norm(Fm) | 147*3ebdd119Saurel32 +---+---+---+---+----------+-----------------------+-----------------------+ 148*3ebdd119Saurel32 Note: LOG, LGN, EXP, SIN, COS, TAN, ASN, ACS, ATN are deprecated, and are 149*3ebdd119Saurel32 available for backwards compatibility only. 150*3ebdd119Saurel32 */ 151*3ebdd119Saurel32 152*3ebdd119Saurel32 /* 153*3ebdd119Saurel32 TABLE 5 154*3ebdd119Saurel32 +-------------------------+---+---+ 155*3ebdd119Saurel32 | Rounding Precision | e | f | 156*3ebdd119Saurel32 +-------------------------+---+---+ 157*3ebdd119Saurel32 | IEEE Single precision | 0 � 0 | 158*3ebdd119Saurel32 | IEEE Double precision | 0 � 1 | 159*3ebdd119Saurel32 | IEEE Extended precision | 1 � 0 | 160*3ebdd119Saurel32 | undefined (trap) | 1 � 1 | 161*3ebdd119Saurel32 +-------------------------+---+---+ 162*3ebdd119Saurel32 */ 163*3ebdd119Saurel32 164*3ebdd119Saurel32 /* 165*3ebdd119Saurel32 TABLE 5 166*3ebdd119Saurel32 +---------------------------------+---+---+ 167*3ebdd119Saurel32 | Rounding Mode | g | h | 168*3ebdd119Saurel32 +---------------------------------+---+---+ 169*3ebdd119Saurel32 | Round to nearest (default) | 0 � 0 | 170*3ebdd119Saurel32 | Round toward plus infinity | 0 � 1 | 171*3ebdd119Saurel32 | Round toward negative infinity | 1 � 0 | 172*3ebdd119Saurel32 | Round toward zero | 1 � 1 | 173*3ebdd119Saurel32 +---------------------------------+---+---+ 174*3ebdd119Saurel32 */ 175*3ebdd119Saurel32 176*3ebdd119Saurel32 /* 177*3ebdd119Saurel32 === 178*3ebdd119Saurel32 === Definitions for load and store instructions 179*3ebdd119Saurel32 === 180*3ebdd119Saurel32 */ 181*3ebdd119Saurel32 182*3ebdd119Saurel32 /* bit masks */ 183*3ebdd119Saurel32 #define BIT_PREINDEX 0x01000000 184*3ebdd119Saurel32 #define BIT_UP 0x00800000 185*3ebdd119Saurel32 #define BIT_WRITE_BACK 0x00200000 186*3ebdd119Saurel32 #define BIT_LOAD 0x00100000 187*3ebdd119Saurel32 188*3ebdd119Saurel32 /* masks for load/store */ 189*3ebdd119Saurel32 #define MASK_CPDT 0x0c000000 /* data processing opcode */ 190*3ebdd119Saurel32 #define MASK_OFFSET 0x000000ff 191*3ebdd119Saurel32 #define MASK_TRANSFER_LENGTH 0x00408000 192*3ebdd119Saurel32 #define MASK_REGISTER_COUNT MASK_TRANSFER_LENGTH 193*3ebdd119Saurel32 #define MASK_COPROCESSOR 0x00000f00 194*3ebdd119Saurel32 195*3ebdd119Saurel32 /* Tests for transfer length */ 196*3ebdd119Saurel32 #define TRANSFER_SINGLE 0x00000000 197*3ebdd119Saurel32 #define TRANSFER_DOUBLE 0x00008000 198*3ebdd119Saurel32 #define TRANSFER_EXTENDED 0x00400000 199*3ebdd119Saurel32 #define TRANSFER_PACKED MASK_TRANSFER_LENGTH 200*3ebdd119Saurel32 201*3ebdd119Saurel32 /* Get the coprocessor number from the opcode. */ 202*3ebdd119Saurel32 #define getCoprocessorNumber(opcode) ((opcode & MASK_COPROCESSOR) >> 8) 203*3ebdd119Saurel32 204*3ebdd119Saurel32 /* Get the offset from the opcode. */ 205*3ebdd119Saurel32 #define getOffset(opcode) (opcode & MASK_OFFSET) 206*3ebdd119Saurel32 207*3ebdd119Saurel32 /* Tests for specific data transfer load/store opcodes. */ 208*3ebdd119Saurel32 #define TEST_OPCODE(opcode,mask) (((opcode) & (mask)) == (mask)) 209*3ebdd119Saurel32 210*3ebdd119Saurel32 #define LOAD_OP(opcode) TEST_OPCODE((opcode),MASK_CPDT | BIT_LOAD) 211*3ebdd119Saurel32 #define STORE_OP(opcode) ((opcode & (MASK_CPDT | BIT_LOAD)) == MASK_CPDT) 212*3ebdd119Saurel32 213*3ebdd119Saurel32 #define LDF_OP(opcode) (LOAD_OP(opcode) && (getCoprocessorNumber(opcode) == 1)) 214*3ebdd119Saurel32 #define LFM_OP(opcode) (LOAD_OP(opcode) && (getCoprocessorNumber(opcode) == 2)) 215*3ebdd119Saurel32 #define STF_OP(opcode) (STORE_OP(opcode) && (getCoprocessorNumber(opcode) == 1)) 216*3ebdd119Saurel32 #define SFM_OP(opcode) (STORE_OP(opcode) && (getCoprocessorNumber(opcode) == 2)) 217*3ebdd119Saurel32 218*3ebdd119Saurel32 #define PREINDEXED(opcode) ((opcode & BIT_PREINDEX) != 0) 219*3ebdd119Saurel32 #define POSTINDEXED(opcode) ((opcode & BIT_PREINDEX) == 0) 220*3ebdd119Saurel32 #define BIT_UP_SET(opcode) ((opcode & BIT_UP) != 0) 221*3ebdd119Saurel32 #define BIT_UP_CLEAR(opcode) ((opcode & BIT_DOWN) == 0) 222*3ebdd119Saurel32 #define WRITE_BACK(opcode) ((opcode & BIT_WRITE_BACK) != 0) 223*3ebdd119Saurel32 #define LOAD(opcode) ((opcode & BIT_LOAD) != 0) 224*3ebdd119Saurel32 #define STORE(opcode) ((opcode & BIT_LOAD) == 0) 225*3ebdd119Saurel32 226*3ebdd119Saurel32 /* 227*3ebdd119Saurel32 === 228*3ebdd119Saurel32 === Definitions for arithmetic instructions 229*3ebdd119Saurel32 === 230*3ebdd119Saurel32 */ 231*3ebdd119Saurel32 /* bit masks */ 232*3ebdd119Saurel32 #define BIT_MONADIC 0x00008000 233*3ebdd119Saurel32 #define BIT_CONSTANT 0x00000008 234*3ebdd119Saurel32 235*3ebdd119Saurel32 #define CONSTANT_FM(opcode) ((opcode & BIT_CONSTANT) != 0) 236*3ebdd119Saurel32 #define MONADIC_INSTRUCTION(opcode) ((opcode & BIT_MONADIC) != 0) 237*3ebdd119Saurel32 238*3ebdd119Saurel32 /* instruction identification masks */ 239*3ebdd119Saurel32 #define MASK_CPDO 0x0e000000 /* arithmetic opcode */ 240*3ebdd119Saurel32 #define MASK_ARITHMETIC_OPCODE 0x00f08000 241*3ebdd119Saurel32 #define MASK_DESTINATION_SIZE 0x00080080 242*3ebdd119Saurel32 243*3ebdd119Saurel32 /* dyadic arithmetic opcodes. */ 244*3ebdd119Saurel32 #define ADF_CODE 0x00000000 245*3ebdd119Saurel32 #define MUF_CODE 0x00100000 246*3ebdd119Saurel32 #define SUF_CODE 0x00200000 247*3ebdd119Saurel32 #define RSF_CODE 0x00300000 248*3ebdd119Saurel32 #define DVF_CODE 0x00400000 249*3ebdd119Saurel32 #define RDF_CODE 0x00500000 250*3ebdd119Saurel32 #define POW_CODE 0x00600000 251*3ebdd119Saurel32 #define RPW_CODE 0x00700000 252*3ebdd119Saurel32 #define RMF_CODE 0x00800000 253*3ebdd119Saurel32 #define FML_CODE 0x00900000 254*3ebdd119Saurel32 #define FDV_CODE 0x00a00000 255*3ebdd119Saurel32 #define FRD_CODE 0x00b00000 256*3ebdd119Saurel32 #define POL_CODE 0x00c00000 257*3ebdd119Saurel32 /* 0x00d00000 is an invalid dyadic arithmetic opcode */ 258*3ebdd119Saurel32 /* 0x00e00000 is an invalid dyadic arithmetic opcode */ 259*3ebdd119Saurel32 /* 0x00f00000 is an invalid dyadic arithmetic opcode */ 260*3ebdd119Saurel32 261*3ebdd119Saurel32 /* monadic arithmetic opcodes. */ 262*3ebdd119Saurel32 #define MVF_CODE 0x00008000 263*3ebdd119Saurel32 #define MNF_CODE 0x00108000 264*3ebdd119Saurel32 #define ABS_CODE 0x00208000 265*3ebdd119Saurel32 #define RND_CODE 0x00308000 266*3ebdd119Saurel32 #define SQT_CODE 0x00408000 267*3ebdd119Saurel32 #define LOG_CODE 0x00508000 268*3ebdd119Saurel32 #define LGN_CODE 0x00608000 269*3ebdd119Saurel32 #define EXP_CODE 0x00708000 270*3ebdd119Saurel32 #define SIN_CODE 0x00808000 271*3ebdd119Saurel32 #define COS_CODE 0x00908000 272*3ebdd119Saurel32 #define TAN_CODE 0x00a08000 273*3ebdd119Saurel32 #define ASN_CODE 0x00b08000 274*3ebdd119Saurel32 #define ACS_CODE 0x00c08000 275*3ebdd119Saurel32 #define ATN_CODE 0x00d08000 276*3ebdd119Saurel32 #define URD_CODE 0x00e08000 277*3ebdd119Saurel32 #define NRM_CODE 0x00f08000 278*3ebdd119Saurel32 279*3ebdd119Saurel32 /* 280*3ebdd119Saurel32 === 281*3ebdd119Saurel32 === Definitions for register transfer and comparison instructions 282*3ebdd119Saurel32 === 283*3ebdd119Saurel32 */ 284*3ebdd119Saurel32 285*3ebdd119Saurel32 #define MASK_CPRT 0x0e000010 /* register transfer opcode */ 286*3ebdd119Saurel32 #define MASK_CPRT_CODE 0x00f00000 287*3ebdd119Saurel32 #define FLT_CODE 0x00000000 288*3ebdd119Saurel32 #define FIX_CODE 0x00100000 289*3ebdd119Saurel32 #define WFS_CODE 0x00200000 290*3ebdd119Saurel32 #define RFS_CODE 0x00300000 291*3ebdd119Saurel32 #define WFC_CODE 0x00400000 292*3ebdd119Saurel32 #define RFC_CODE 0x00500000 293*3ebdd119Saurel32 #define CMF_CODE 0x00900000 294*3ebdd119Saurel32 #define CNF_CODE 0x00b00000 295*3ebdd119Saurel32 #define CMFE_CODE 0x00d00000 296*3ebdd119Saurel32 #define CNFE_CODE 0x00f00000 297*3ebdd119Saurel32 298*3ebdd119Saurel32 /* 299*3ebdd119Saurel32 === 300*3ebdd119Saurel32 === Common definitions 301*3ebdd119Saurel32 === 302*3ebdd119Saurel32 */ 303*3ebdd119Saurel32 304*3ebdd119Saurel32 /* register masks */ 305*3ebdd119Saurel32 #define MASK_Rd 0x0000f000 306*3ebdd119Saurel32 #define MASK_Rn 0x000f0000 307*3ebdd119Saurel32 #define MASK_Fd 0x00007000 308*3ebdd119Saurel32 #define MASK_Fm 0x00000007 309*3ebdd119Saurel32 #define MASK_Fn 0x00070000 310*3ebdd119Saurel32 311*3ebdd119Saurel32 /* condition code masks */ 312*3ebdd119Saurel32 #define CC_MASK 0xf0000000 313*3ebdd119Saurel32 #define CC_NEGATIVE 0x80000000 314*3ebdd119Saurel32 #define CC_ZERO 0x40000000 315*3ebdd119Saurel32 #define CC_CARRY 0x20000000 316*3ebdd119Saurel32 #define CC_OVERFLOW 0x10000000 317*3ebdd119Saurel32 #define CC_EQ 0x00000000 318*3ebdd119Saurel32 #define CC_NE 0x10000000 319*3ebdd119Saurel32 #define CC_CS 0x20000000 320*3ebdd119Saurel32 #define CC_HS CC_CS 321*3ebdd119Saurel32 #define CC_CC 0x30000000 322*3ebdd119Saurel32 #define CC_LO CC_CC 323*3ebdd119Saurel32 #define CC_MI 0x40000000 324*3ebdd119Saurel32 #define CC_PL 0x50000000 325*3ebdd119Saurel32 #define CC_VS 0x60000000 326*3ebdd119Saurel32 #define CC_VC 0x70000000 327*3ebdd119Saurel32 #define CC_HI 0x80000000 328*3ebdd119Saurel32 #define CC_LS 0x90000000 329*3ebdd119Saurel32 #define CC_GE 0xa0000000 330*3ebdd119Saurel32 #define CC_LT 0xb0000000 331*3ebdd119Saurel32 #define CC_GT 0xc0000000 332*3ebdd119Saurel32 #define CC_LE 0xd0000000 333*3ebdd119Saurel32 #define CC_AL 0xe0000000 334*3ebdd119Saurel32 #define CC_NV 0xf0000000 335*3ebdd119Saurel32 336*3ebdd119Saurel32 /* rounding masks/values */ 337*3ebdd119Saurel32 #define MASK_ROUNDING_MODE 0x00000060 338*3ebdd119Saurel32 #define ROUND_TO_NEAREST 0x00000000 339*3ebdd119Saurel32 #define ROUND_TO_PLUS_INFINITY 0x00000020 340*3ebdd119Saurel32 #define ROUND_TO_MINUS_INFINITY 0x00000040 341*3ebdd119Saurel32 #define ROUND_TO_ZERO 0x00000060 342*3ebdd119Saurel32 343*3ebdd119Saurel32 #define MASK_ROUNDING_PRECISION 0x00080080 344*3ebdd119Saurel32 #define ROUND_SINGLE 0x00000000 345*3ebdd119Saurel32 #define ROUND_DOUBLE 0x00000080 346*3ebdd119Saurel32 #define ROUND_EXTENDED 0x00080000 347*3ebdd119Saurel32 348*3ebdd119Saurel32 /* Get the condition code from the opcode. */ 349*3ebdd119Saurel32 #define getCondition(opcode) (opcode >> 28) 350*3ebdd119Saurel32 351*3ebdd119Saurel32 /* Get the source register from the opcode. */ 352*3ebdd119Saurel32 #define getRn(opcode) ((opcode & MASK_Rn) >> 16) 353*3ebdd119Saurel32 354*3ebdd119Saurel32 /* Get the destination floating point register from the opcode. */ 355*3ebdd119Saurel32 #define getFd(opcode) ((opcode & MASK_Fd) >> 12) 356*3ebdd119Saurel32 357*3ebdd119Saurel32 /* Get the first source floating point register from the opcode. */ 358*3ebdd119Saurel32 #define getFn(opcode) ((opcode & MASK_Fn) >> 16) 359*3ebdd119Saurel32 360*3ebdd119Saurel32 /* Get the second source floating point register from the opcode. */ 361*3ebdd119Saurel32 #define getFm(opcode) (opcode & MASK_Fm) 362*3ebdd119Saurel32 363*3ebdd119Saurel32 /* Get the destination register from the opcode. */ 364*3ebdd119Saurel32 #define getRd(opcode) ((opcode & MASK_Rd) >> 12) 365*3ebdd119Saurel32 366*3ebdd119Saurel32 /* Get the rounding mode from the opcode. */ 367*3ebdd119Saurel32 #define getRoundingMode(opcode) ((opcode & MASK_ROUNDING_MODE) >> 5) 368*3ebdd119Saurel32 369*3ebdd119Saurel32 static inline const floatx80 getExtendedConstant(const unsigned int nIndex) 370*3ebdd119Saurel32 { 371*3ebdd119Saurel32 extern const floatx80 floatx80Constant[]; 372*3ebdd119Saurel32 return floatx80Constant[nIndex]; 373*3ebdd119Saurel32 } 374*3ebdd119Saurel32 375*3ebdd119Saurel32 static inline const float64 getDoubleConstant(const unsigned int nIndex) 376*3ebdd119Saurel32 { 377*3ebdd119Saurel32 extern const float64 float64Constant[]; 378*3ebdd119Saurel32 return float64Constant[nIndex]; 379*3ebdd119Saurel32 } 380*3ebdd119Saurel32 381*3ebdd119Saurel32 static inline const float32 getSingleConstant(const unsigned int nIndex) 382*3ebdd119Saurel32 { 383*3ebdd119Saurel32 extern const float32 float32Constant[]; 384*3ebdd119Saurel32 return float32Constant[nIndex]; 385*3ebdd119Saurel32 } 386*3ebdd119Saurel32 387*3ebdd119Saurel32 extern unsigned int getRegisterCount(const unsigned int opcode); 388*3ebdd119Saurel32 extern unsigned int getDestinationSize(const unsigned int opcode); 389*3ebdd119Saurel32 390*3ebdd119Saurel32 #endif 391