13ebdd119Saurel32 /* 23ebdd119Saurel32 NetWinder Floating Point Emulator 33ebdd119Saurel32 (c) Rebel.COM, 1998,1999 43ebdd119Saurel32 53ebdd119Saurel32 Direct questions, comments to Scott Bambrough <scottb@netwinder.org> 63ebdd119Saurel32 73ebdd119Saurel32 This program is free software; you can redistribute it and/or modify 83ebdd119Saurel32 it under the terms of the GNU General Public License as published by 93ebdd119Saurel32 the Free Software Foundation; either version 2 of the License, or 103ebdd119Saurel32 (at your option) any later version. 113ebdd119Saurel32 123ebdd119Saurel32 This program is distributed in the hope that it will be useful, 133ebdd119Saurel32 but WITHOUT ANY WARRANTY; without even the implied warranty of 143ebdd119Saurel32 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 153ebdd119Saurel32 GNU General Public License for more details. 163ebdd119Saurel32 173ebdd119Saurel32 You should have received a copy of the GNU General Public License 183ebdd119Saurel32 along with this program; if not, write to the Free Software 193ebdd119Saurel32 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 203ebdd119Saurel32 */ 213ebdd119Saurel32 223ebdd119Saurel32 #ifndef __FPOPCODE_H__ 233ebdd119Saurel32 #define __FPOPCODE_H__ 243ebdd119Saurel32 253ebdd119Saurel32 /* 263ebdd119Saurel32 ARM Floating Point Instruction Classes 273ebdd119Saurel32 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 283ebdd119Saurel32 |c o n d|1 1 0 P|U|u|W|L| Rn |v| Fd |0|0|0|1| o f f s e t | CPDT 293ebdd119Saurel32 |c o n d|1 1 0 P|U|w|W|L| Rn |x| Fd |0|0|0|1| o f f s e t | CPDT 303ebdd119Saurel32 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 313ebdd119Saurel32 |c o n d|1 1 1 0|a|b|c|d|e| Fn |j| Fd |0|0|0|1|f|g|h|0|i| Fm | CPDO 323ebdd119Saurel32 |c o n d|1 1 1 0|a|b|c|L|e| Fn | Rd |0|0|0|1|f|g|h|1|i| Fm | CPRT 333ebdd119Saurel32 |c o n d|1 1 1 0|a|b|c|1|e| Fn |1|1|1|1|0|0|0|1|f|g|h|1|i| Fm | comparisons 343ebdd119Saurel32 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 353ebdd119Saurel32 363ebdd119Saurel32 CPDT data transfer instructions 373ebdd119Saurel32 LDF, STF, LFM, SFM 383ebdd119Saurel32 393ebdd119Saurel32 CPDO dyadic arithmetic instructions 403ebdd119Saurel32 ADF, MUF, SUF, RSF, DVF, RDF, 413ebdd119Saurel32 POW, RPW, RMF, FML, FDV, FRD, POL 423ebdd119Saurel32 433ebdd119Saurel32 CPDO monadic arithmetic instructions 443ebdd119Saurel32 MVF, MNF, ABS, RND, SQT, LOG, LGN, EXP, 453ebdd119Saurel32 SIN, COS, TAN, ASN, ACS, ATN, URD, NRM 463ebdd119Saurel32 473ebdd119Saurel32 CPRT joint arithmetic/data transfer instructions 483ebdd119Saurel32 FIX (arithmetic followed by load/store) 493ebdd119Saurel32 FLT (load/store followed by arithmetic) 503ebdd119Saurel32 CMF, CNF CMFE, CNFE (comparisons) 513ebdd119Saurel32 WFS, RFS (write/read floating point status register) 523ebdd119Saurel32 WFC, RFC (write/read floating point control register) 533ebdd119Saurel32 543ebdd119Saurel32 cond condition codes 553ebdd119Saurel32 P pre/post index bit: 0 = postindex, 1 = preindex 563ebdd119Saurel32 U up/down bit: 0 = stack grows down, 1 = stack grows up 573ebdd119Saurel32 W write back bit: 1 = update base register (Rn) 583ebdd119Saurel32 L load/store bit: 0 = store, 1 = load 593ebdd119Saurel32 Rn base register 603ebdd119Saurel32 Rd destination/source register 613ebdd119Saurel32 Fd floating point destination register 623ebdd119Saurel32 Fn floating point source register 633ebdd119Saurel32 Fm floating point source register or floating point constant 643ebdd119Saurel32 653ebdd119Saurel32 uv transfer length (TABLE 1) 663ebdd119Saurel32 wx register count (TABLE 2) 673ebdd119Saurel32 abcd arithmetic opcode (TABLES 3 & 4) 683ebdd119Saurel32 ef destination size (rounding precision) (TABLE 5) 693ebdd119Saurel32 gh rounding mode (TABLE 6) 703ebdd119Saurel32 j dyadic/monadic bit: 0 = dyadic, 1 = monadic 713ebdd119Saurel32 i constant bit: 1 = constant (TABLE 6) 723ebdd119Saurel32 */ 733ebdd119Saurel32 743ebdd119Saurel32 /* 753ebdd119Saurel32 TABLE 1 763ebdd119Saurel32 +-------------------------+---+---+---------+---------+ 773ebdd119Saurel32 | Precision | u | v | FPSR.EP | length | 783ebdd119Saurel32 +-------------------------+---+---+---------+---------+ 793ebdd119Saurel32 | Single | 0 � 0 | x | 1 words | 803ebdd119Saurel32 | Double | 1 � 1 | x | 2 words | 813ebdd119Saurel32 | Extended | 1 � 1 | x | 3 words | 823ebdd119Saurel32 | Packed decimal | 1 � 1 | 0 | 3 words | 833ebdd119Saurel32 | Expanded packed decimal | 1 � 1 | 1 | 4 words | 843ebdd119Saurel32 +-------------------------+---+---+---------+---------+ 853ebdd119Saurel32 Note: x = don't care 863ebdd119Saurel32 */ 873ebdd119Saurel32 883ebdd119Saurel32 /* 893ebdd119Saurel32 TABLE 2 903ebdd119Saurel32 +---+---+---------------------------------+ 913ebdd119Saurel32 | w | x | Number of registers to transfer | 923ebdd119Saurel32 +---+---+---------------------------------+ 933ebdd119Saurel32 | 0 � 1 | 1 | 943ebdd119Saurel32 | 1 � 0 | 2 | 953ebdd119Saurel32 | 1 � 1 | 3 | 963ebdd119Saurel32 | 0 � 0 | 4 | 973ebdd119Saurel32 +---+---+---------------------------------+ 983ebdd119Saurel32 */ 993ebdd119Saurel32 1003ebdd119Saurel32 /* 1013ebdd119Saurel32 TABLE 3: Dyadic Floating Point Opcodes 1023ebdd119Saurel32 +---+---+---+---+----------+-----------------------+-----------------------+ 1033ebdd119Saurel32 | a | b | c | d | Mnemonic | Description | Operation | 1043ebdd119Saurel32 +---+---+---+---+----------+-----------------------+-----------------------+ 1053ebdd119Saurel32 | 0 | 0 | 0 | 0 | ADF | Add | Fd := Fn + Fm | 1063ebdd119Saurel32 | 0 | 0 | 0 | 1 | MUF | Multiply | Fd := Fn * Fm | 1073ebdd119Saurel32 | 0 | 0 | 1 | 0 | SUF | Subtract | Fd := Fn - Fm | 1083ebdd119Saurel32 | 0 | 0 | 1 | 1 | RSF | Reverse subtract | Fd := Fm - Fn | 1093ebdd119Saurel32 | 0 | 1 | 0 | 0 | DVF | Divide | Fd := Fn / Fm | 1103ebdd119Saurel32 | 0 | 1 | 0 | 1 | RDF | Reverse divide | Fd := Fm / Fn | 1113ebdd119Saurel32 | 0 | 1 | 1 | 0 | POW | Power | Fd := Fn ^ Fm | 1123ebdd119Saurel32 | 0 | 1 | 1 | 1 | RPW | Reverse power | Fd := Fm ^ Fn | 1133ebdd119Saurel32 | 1 | 0 | 0 | 0 | RMF | Remainder | Fd := IEEE rem(Fn/Fm) | 1143ebdd119Saurel32 | 1 | 0 | 0 | 1 | FML | Fast Multiply | Fd := Fn * Fm | 1153ebdd119Saurel32 | 1 | 0 | 1 | 0 | FDV | Fast Divide | Fd := Fn / Fm | 1163ebdd119Saurel32 | 1 | 0 | 1 | 1 | FRD | Fast reverse divide | Fd := Fm / Fn | 1173ebdd119Saurel32 | 1 | 1 | 0 | 0 | POL | Polar angle (ArcTan2) | Fd := arctan2(Fn,Fm) | 1183ebdd119Saurel32 | 1 | 1 | 0 | 1 | | undefined instruction | trap | 1193ebdd119Saurel32 | 1 | 1 | 1 | 0 | | undefined instruction | trap | 1203ebdd119Saurel32 | 1 | 1 | 1 | 1 | | undefined instruction | trap | 1213ebdd119Saurel32 +---+---+---+---+----------+-----------------------+-----------------------+ 1223ebdd119Saurel32 Note: POW, RPW, POL are deprecated, and are available for backwards 1233ebdd119Saurel32 compatibility only. 1243ebdd119Saurel32 */ 1253ebdd119Saurel32 1263ebdd119Saurel32 /* 1273ebdd119Saurel32 TABLE 4: Monadic Floating Point Opcodes 1283ebdd119Saurel32 +---+---+---+---+----------+-----------------------+-----------------------+ 1293ebdd119Saurel32 | a | b | c | d | Mnemonic | Description | Operation | 1303ebdd119Saurel32 +---+---+---+---+----------+-----------------------+-----------------------+ 1313ebdd119Saurel32 | 0 | 0 | 0 | 0 | MVF | Move | Fd := Fm | 1323ebdd119Saurel32 | 0 | 0 | 0 | 1 | MNF | Move negated | Fd := - Fm | 1333ebdd119Saurel32 | 0 | 0 | 1 | 0 | ABS | Absolute value | Fd := abs(Fm) | 1343ebdd119Saurel32 | 0 | 0 | 1 | 1 | RND | Round to integer | Fd := int(Fm) | 1353ebdd119Saurel32 | 0 | 1 | 0 | 0 | SQT | Square root | Fd := sqrt(Fm) | 1363ebdd119Saurel32 | 0 | 1 | 0 | 1 | LOG | Log base 10 | Fd := log10(Fm) | 1373ebdd119Saurel32 | 0 | 1 | 1 | 0 | LGN | Log base e | Fd := ln(Fm) | 1383ebdd119Saurel32 | 0 | 1 | 1 | 1 | EXP | Exponent | Fd := e ^ Fm | 1393ebdd119Saurel32 | 1 | 0 | 0 | 0 | SIN | Sine | Fd := sin(Fm) | 1403ebdd119Saurel32 | 1 | 0 | 0 | 1 | COS | Cosine | Fd := cos(Fm) | 1413ebdd119Saurel32 | 1 | 0 | 1 | 0 | TAN | Tangent | Fd := tan(Fm) | 1423ebdd119Saurel32 | 1 | 0 | 1 | 1 | ASN | Arc Sine | Fd := arcsin(Fm) | 1433ebdd119Saurel32 | 1 | 1 | 0 | 0 | ACS | Arc Cosine | Fd := arccos(Fm) | 1443ebdd119Saurel32 | 1 | 1 | 0 | 1 | ATN | Arc Tangent | Fd := arctan(Fm) | 1453ebdd119Saurel32 | 1 | 1 | 1 | 0 | URD | Unnormalized round | Fd := int(Fm) | 1463ebdd119Saurel32 | 1 | 1 | 1 | 1 | NRM | Normalize | Fd := norm(Fm) | 1473ebdd119Saurel32 +---+---+---+---+----------+-----------------------+-----------------------+ 1483ebdd119Saurel32 Note: LOG, LGN, EXP, SIN, COS, TAN, ASN, ACS, ATN are deprecated, and are 1493ebdd119Saurel32 available for backwards compatibility only. 1503ebdd119Saurel32 */ 1513ebdd119Saurel32 1523ebdd119Saurel32 /* 1533ebdd119Saurel32 TABLE 5 1543ebdd119Saurel32 +-------------------------+---+---+ 1553ebdd119Saurel32 | Rounding Precision | e | f | 1563ebdd119Saurel32 +-------------------------+---+---+ 1573ebdd119Saurel32 | IEEE Single precision | 0 � 0 | 1583ebdd119Saurel32 | IEEE Double precision | 0 � 1 | 1593ebdd119Saurel32 | IEEE Extended precision | 1 � 0 | 1603ebdd119Saurel32 | undefined (trap) | 1 � 1 | 1613ebdd119Saurel32 +-------------------------+---+---+ 1623ebdd119Saurel32 */ 1633ebdd119Saurel32 1643ebdd119Saurel32 /* 1653ebdd119Saurel32 TABLE 5 1663ebdd119Saurel32 +---------------------------------+---+---+ 1673ebdd119Saurel32 | Rounding Mode | g | h | 1683ebdd119Saurel32 +---------------------------------+---+---+ 1693ebdd119Saurel32 | Round to nearest (default) | 0 � 0 | 1703ebdd119Saurel32 | Round toward plus infinity | 0 � 1 | 1713ebdd119Saurel32 | Round toward negative infinity | 1 � 0 | 1723ebdd119Saurel32 | Round toward zero | 1 � 1 | 1733ebdd119Saurel32 +---------------------------------+---+---+ 1743ebdd119Saurel32 */ 1753ebdd119Saurel32 1763ebdd119Saurel32 /* 1773ebdd119Saurel32 === 1783ebdd119Saurel32 === Definitions for load and store instructions 1793ebdd119Saurel32 === 1803ebdd119Saurel32 */ 1813ebdd119Saurel32 1823ebdd119Saurel32 /* bit masks */ 1833ebdd119Saurel32 #define BIT_PREINDEX 0x01000000 1843ebdd119Saurel32 #define BIT_UP 0x00800000 1853ebdd119Saurel32 #define BIT_WRITE_BACK 0x00200000 1863ebdd119Saurel32 #define BIT_LOAD 0x00100000 1873ebdd119Saurel32 1883ebdd119Saurel32 /* masks for load/store */ 1893ebdd119Saurel32 #define MASK_CPDT 0x0c000000 /* data processing opcode */ 1903ebdd119Saurel32 #define MASK_OFFSET 0x000000ff 1913ebdd119Saurel32 #define MASK_TRANSFER_LENGTH 0x00408000 1923ebdd119Saurel32 #define MASK_REGISTER_COUNT MASK_TRANSFER_LENGTH 1933ebdd119Saurel32 #define MASK_COPROCESSOR 0x00000f00 1943ebdd119Saurel32 1953ebdd119Saurel32 /* Tests for transfer length */ 1963ebdd119Saurel32 #define TRANSFER_SINGLE 0x00000000 1973ebdd119Saurel32 #define TRANSFER_DOUBLE 0x00008000 1983ebdd119Saurel32 #define TRANSFER_EXTENDED 0x00400000 1993ebdd119Saurel32 #define TRANSFER_PACKED MASK_TRANSFER_LENGTH 2003ebdd119Saurel32 2013ebdd119Saurel32 /* Get the coprocessor number from the opcode. */ 2023ebdd119Saurel32 #define getCoprocessorNumber(opcode) ((opcode & MASK_COPROCESSOR) >> 8) 2033ebdd119Saurel32 2043ebdd119Saurel32 /* Get the offset from the opcode. */ 2053ebdd119Saurel32 #define getOffset(opcode) (opcode & MASK_OFFSET) 2063ebdd119Saurel32 2073ebdd119Saurel32 /* Tests for specific data transfer load/store opcodes. */ 2083ebdd119Saurel32 #define TEST_OPCODE(opcode,mask) (((opcode) & (mask)) == (mask)) 2093ebdd119Saurel32 2103ebdd119Saurel32 #define LOAD_OP(opcode) TEST_OPCODE((opcode),MASK_CPDT | BIT_LOAD) 2113ebdd119Saurel32 #define STORE_OP(opcode) ((opcode & (MASK_CPDT | BIT_LOAD)) == MASK_CPDT) 2123ebdd119Saurel32 2133ebdd119Saurel32 #define LDF_OP(opcode) (LOAD_OP(opcode) && (getCoprocessorNumber(opcode) == 1)) 2143ebdd119Saurel32 #define LFM_OP(opcode) (LOAD_OP(opcode) && (getCoprocessorNumber(opcode) == 2)) 2153ebdd119Saurel32 #define STF_OP(opcode) (STORE_OP(opcode) && (getCoprocessorNumber(opcode) == 1)) 2163ebdd119Saurel32 #define SFM_OP(opcode) (STORE_OP(opcode) && (getCoprocessorNumber(opcode) == 2)) 2173ebdd119Saurel32 2183ebdd119Saurel32 #define PREINDEXED(opcode) ((opcode & BIT_PREINDEX) != 0) 2193ebdd119Saurel32 #define POSTINDEXED(opcode) ((opcode & BIT_PREINDEX) == 0) 2203ebdd119Saurel32 #define BIT_UP_SET(opcode) ((opcode & BIT_UP) != 0) 2213ebdd119Saurel32 #define BIT_UP_CLEAR(opcode) ((opcode & BIT_DOWN) == 0) 2223ebdd119Saurel32 #define WRITE_BACK(opcode) ((opcode & BIT_WRITE_BACK) != 0) 2233ebdd119Saurel32 #define LOAD(opcode) ((opcode & BIT_LOAD) != 0) 2243ebdd119Saurel32 #define STORE(opcode) ((opcode & BIT_LOAD) == 0) 2253ebdd119Saurel32 2263ebdd119Saurel32 /* 2273ebdd119Saurel32 === 2283ebdd119Saurel32 === Definitions for arithmetic instructions 2293ebdd119Saurel32 === 2303ebdd119Saurel32 */ 2313ebdd119Saurel32 /* bit masks */ 2323ebdd119Saurel32 #define BIT_MONADIC 0x00008000 2333ebdd119Saurel32 #define BIT_CONSTANT 0x00000008 2343ebdd119Saurel32 2353ebdd119Saurel32 #define CONSTANT_FM(opcode) ((opcode & BIT_CONSTANT) != 0) 2363ebdd119Saurel32 #define MONADIC_INSTRUCTION(opcode) ((opcode & BIT_MONADIC) != 0) 2373ebdd119Saurel32 2383ebdd119Saurel32 /* instruction identification masks */ 2393ebdd119Saurel32 #define MASK_CPDO 0x0e000000 /* arithmetic opcode */ 2403ebdd119Saurel32 #define MASK_ARITHMETIC_OPCODE 0x00f08000 2413ebdd119Saurel32 #define MASK_DESTINATION_SIZE 0x00080080 2423ebdd119Saurel32 2433ebdd119Saurel32 /* dyadic arithmetic opcodes. */ 2443ebdd119Saurel32 #define ADF_CODE 0x00000000 2453ebdd119Saurel32 #define MUF_CODE 0x00100000 2463ebdd119Saurel32 #define SUF_CODE 0x00200000 2473ebdd119Saurel32 #define RSF_CODE 0x00300000 2483ebdd119Saurel32 #define DVF_CODE 0x00400000 2493ebdd119Saurel32 #define RDF_CODE 0x00500000 2503ebdd119Saurel32 #define POW_CODE 0x00600000 2513ebdd119Saurel32 #define RPW_CODE 0x00700000 2523ebdd119Saurel32 #define RMF_CODE 0x00800000 2533ebdd119Saurel32 #define FML_CODE 0x00900000 2543ebdd119Saurel32 #define FDV_CODE 0x00a00000 2553ebdd119Saurel32 #define FRD_CODE 0x00b00000 2563ebdd119Saurel32 #define POL_CODE 0x00c00000 2573ebdd119Saurel32 /* 0x00d00000 is an invalid dyadic arithmetic opcode */ 2583ebdd119Saurel32 /* 0x00e00000 is an invalid dyadic arithmetic opcode */ 2593ebdd119Saurel32 /* 0x00f00000 is an invalid dyadic arithmetic opcode */ 2603ebdd119Saurel32 2613ebdd119Saurel32 /* monadic arithmetic opcodes. */ 2623ebdd119Saurel32 #define MVF_CODE 0x00008000 2633ebdd119Saurel32 #define MNF_CODE 0x00108000 2643ebdd119Saurel32 #define ABS_CODE 0x00208000 2653ebdd119Saurel32 #define RND_CODE 0x00308000 2663ebdd119Saurel32 #define SQT_CODE 0x00408000 2673ebdd119Saurel32 #define LOG_CODE 0x00508000 2683ebdd119Saurel32 #define LGN_CODE 0x00608000 2693ebdd119Saurel32 #define EXP_CODE 0x00708000 2703ebdd119Saurel32 #define SIN_CODE 0x00808000 2713ebdd119Saurel32 #define COS_CODE 0x00908000 2723ebdd119Saurel32 #define TAN_CODE 0x00a08000 2733ebdd119Saurel32 #define ASN_CODE 0x00b08000 2743ebdd119Saurel32 #define ACS_CODE 0x00c08000 2753ebdd119Saurel32 #define ATN_CODE 0x00d08000 2763ebdd119Saurel32 #define URD_CODE 0x00e08000 2773ebdd119Saurel32 #define NRM_CODE 0x00f08000 2783ebdd119Saurel32 2793ebdd119Saurel32 /* 2803ebdd119Saurel32 === 2813ebdd119Saurel32 === Definitions for register transfer and comparison instructions 2823ebdd119Saurel32 === 2833ebdd119Saurel32 */ 2843ebdd119Saurel32 2853ebdd119Saurel32 #define MASK_CPRT 0x0e000010 /* register transfer opcode */ 2863ebdd119Saurel32 #define MASK_CPRT_CODE 0x00f00000 2873ebdd119Saurel32 #define FLT_CODE 0x00000000 2883ebdd119Saurel32 #define FIX_CODE 0x00100000 2893ebdd119Saurel32 #define WFS_CODE 0x00200000 2903ebdd119Saurel32 #define RFS_CODE 0x00300000 2913ebdd119Saurel32 #define WFC_CODE 0x00400000 2923ebdd119Saurel32 #define RFC_CODE 0x00500000 2933ebdd119Saurel32 #define CMF_CODE 0x00900000 2943ebdd119Saurel32 #define CNF_CODE 0x00b00000 2953ebdd119Saurel32 #define CMFE_CODE 0x00d00000 2963ebdd119Saurel32 #define CNFE_CODE 0x00f00000 2973ebdd119Saurel32 2983ebdd119Saurel32 /* 2993ebdd119Saurel32 === 3003ebdd119Saurel32 === Common definitions 3013ebdd119Saurel32 === 3023ebdd119Saurel32 */ 3033ebdd119Saurel32 3043ebdd119Saurel32 /* register masks */ 3053ebdd119Saurel32 #define MASK_Rd 0x0000f000 3063ebdd119Saurel32 #define MASK_Rn 0x000f0000 3073ebdd119Saurel32 #define MASK_Fd 0x00007000 3083ebdd119Saurel32 #define MASK_Fm 0x00000007 3093ebdd119Saurel32 #define MASK_Fn 0x00070000 3103ebdd119Saurel32 3113ebdd119Saurel32 /* condition code masks */ 3123ebdd119Saurel32 #define CC_MASK 0xf0000000 3133ebdd119Saurel32 #define CC_NEGATIVE 0x80000000 3143ebdd119Saurel32 #define CC_ZERO 0x40000000 3153ebdd119Saurel32 #define CC_CARRY 0x20000000 3163ebdd119Saurel32 #define CC_OVERFLOW 0x10000000 3173ebdd119Saurel32 #define CC_EQ 0x00000000 3183ebdd119Saurel32 #define CC_NE 0x10000000 3193ebdd119Saurel32 #define CC_CS 0x20000000 3203ebdd119Saurel32 #define CC_HS CC_CS 3213ebdd119Saurel32 #define CC_CC 0x30000000 3223ebdd119Saurel32 #define CC_LO CC_CC 3233ebdd119Saurel32 #define CC_MI 0x40000000 3243ebdd119Saurel32 #define CC_PL 0x50000000 3253ebdd119Saurel32 #define CC_VS 0x60000000 3263ebdd119Saurel32 #define CC_VC 0x70000000 3273ebdd119Saurel32 #define CC_HI 0x80000000 3283ebdd119Saurel32 #define CC_LS 0x90000000 3293ebdd119Saurel32 #define CC_GE 0xa0000000 3303ebdd119Saurel32 #define CC_LT 0xb0000000 3313ebdd119Saurel32 #define CC_GT 0xc0000000 3323ebdd119Saurel32 #define CC_LE 0xd0000000 3333ebdd119Saurel32 #define CC_AL 0xe0000000 3343ebdd119Saurel32 #define CC_NV 0xf0000000 3353ebdd119Saurel32 3363ebdd119Saurel32 /* rounding masks/values */ 3373ebdd119Saurel32 #define MASK_ROUNDING_MODE 0x00000060 3383ebdd119Saurel32 #define ROUND_TO_NEAREST 0x00000000 3393ebdd119Saurel32 #define ROUND_TO_PLUS_INFINITY 0x00000020 3403ebdd119Saurel32 #define ROUND_TO_MINUS_INFINITY 0x00000040 3413ebdd119Saurel32 #define ROUND_TO_ZERO 0x00000060 3423ebdd119Saurel32 3433ebdd119Saurel32 #define MASK_ROUNDING_PRECISION 0x00080080 3443ebdd119Saurel32 #define ROUND_SINGLE 0x00000000 3453ebdd119Saurel32 #define ROUND_DOUBLE 0x00000080 3463ebdd119Saurel32 #define ROUND_EXTENDED 0x00080000 3473ebdd119Saurel32 3483ebdd119Saurel32 /* Get the condition code from the opcode. */ 3493ebdd119Saurel32 #define getCondition(opcode) (opcode >> 28) 3503ebdd119Saurel32 3513ebdd119Saurel32 /* Get the source register from the opcode. */ 3523ebdd119Saurel32 #define getRn(opcode) ((opcode & MASK_Rn) >> 16) 3533ebdd119Saurel32 3543ebdd119Saurel32 /* Get the destination floating point register from the opcode. */ 3553ebdd119Saurel32 #define getFd(opcode) ((opcode & MASK_Fd) >> 12) 3563ebdd119Saurel32 3573ebdd119Saurel32 /* Get the first source floating point register from the opcode. */ 3583ebdd119Saurel32 #define getFn(opcode) ((opcode & MASK_Fn) >> 16) 3593ebdd119Saurel32 3603ebdd119Saurel32 /* Get the second source floating point register from the opcode. */ 3613ebdd119Saurel32 #define getFm(opcode) (opcode & MASK_Fm) 3623ebdd119Saurel32 3633ebdd119Saurel32 /* Get the destination register from the opcode. */ 3643ebdd119Saurel32 #define getRd(opcode) ((opcode & MASK_Rd) >> 12) 3653ebdd119Saurel32 3663ebdd119Saurel32 /* Get the rounding mode from the opcode. */ 3673ebdd119Saurel32 #define getRoundingMode(opcode) ((opcode & MASK_ROUNDING_MODE) >> 5) 3683ebdd119Saurel32 369*d4fa8d90SBlue Swirl extern const floatx80 floatx80Constant[]; 370*d4fa8d90SBlue Swirl extern const float64 float64Constant[]; 371*d4fa8d90SBlue Swirl extern const float32 float32Constant[]; 372*d4fa8d90SBlue Swirl 3737ccfb2ebSblueswir1 static inline floatx80 getExtendedConstant(const unsigned int nIndex) 3743ebdd119Saurel32 { 3753ebdd119Saurel32 return floatx80Constant[nIndex]; 3763ebdd119Saurel32 } 3773ebdd119Saurel32 3787ccfb2ebSblueswir1 static inline float64 getDoubleConstant(const unsigned int nIndex) 3793ebdd119Saurel32 { 3803ebdd119Saurel32 return float64Constant[nIndex]; 3813ebdd119Saurel32 } 3823ebdd119Saurel32 3837ccfb2ebSblueswir1 static inline float32 getSingleConstant(const unsigned int nIndex) 3843ebdd119Saurel32 { 3853ebdd119Saurel32 return float32Constant[nIndex]; 3863ebdd119Saurel32 } 3873ebdd119Saurel32 3883ebdd119Saurel32 extern unsigned int getRegisterCount(const unsigned int opcode); 3893ebdd119Saurel32 extern unsigned int getDestinationSize(const unsigned int opcode); 3903ebdd119Saurel32 3913ebdd119Saurel32 #endif 392