1 /*
2  * host-signal.h: signal info dependent on the host architecture
3  *
4  * Copyright (c) 2003-2005 Fabrice Bellard
5  * Copyright (c) 2021 Linaro Limited
6  *
7  * This work is licensed under the terms of the GNU LGPL, version 2.1 or later.
8  * See the COPYING file in the top-level directory.
9  */
10 
11 #ifndef RISCV_HOST_SIGNAL_H
12 #define RISCV_HOST_SIGNAL_H
13 
14 static inline uintptr_t host_signal_pc(ucontext_t *uc)
15 {
16     return uc->uc_mcontext.__gregs[REG_PC];
17 }
18 
19 static inline void host_signal_set_pc(ucontext_t *uc, uintptr_t pc)
20 {
21     uc->uc_mcontext.__gregs[REG_PC] = pc;
22 }
23 
24 static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc)
25 {
26     /*
27      * Detect store by reading the instruction at the program counter.
28      * Do not read more than 16 bits, because we have not yet determined
29      * the size of the instruction.
30      */
31     const uint16_t *pinsn = (const uint16_t *)host_signal_pc(uc);
32     uint16_t insn = pinsn[0];
33 
34     /* 16-bit instructions */
35     switch (insn & 0xe003) {
36     case 0xa000: /* c.fsd */
37     case 0xc000: /* c.sw */
38     case 0xe000: /* c.sd (rv64) / c.fsw (rv32) */
39     case 0xa002: /* c.fsdsp */
40     case 0xc002: /* c.swsp */
41     case 0xe002: /* c.sdsp (rv64) / c.fswsp (rv32) */
42         return true;
43     }
44 
45     /* 32-bit instructions, major opcodes */
46     switch (insn & 0x7f) {
47     case 0x23: /* store */
48     case 0x27: /* store-fp */
49         return true;
50     case 0x2f: /* amo */
51         /*
52          * The AMO function code is in bits 25-31, unread as yet.
53          * The AMO functions are LR (read), SC (write), and the
54          * rest are all read-modify-write.
55          */
56         insn = pinsn[1];
57         return (insn >> 11) != 2; /* LR */
58     }
59 
60     return false;
61 }
62 
63 #endif
64