174433bf0SRichard Henderson /* 274433bf0SRichard Henderson * ARM cpu parameters for qemu. 374433bf0SRichard Henderson * 474433bf0SRichard Henderson * Copyright (c) 2003 Fabrice Bellard 574433bf0SRichard Henderson * SPDX-License-Identifier: LGPL-2.0+ 674433bf0SRichard Henderson */ 774433bf0SRichard Henderson 874433bf0SRichard Henderson #ifndef ARM_CPU_PARAM_H 94f31b54bSMarkus Armbruster #define ARM_CPU_PARAM_H 1074433bf0SRichard Henderson 1174433bf0SRichard Henderson #ifdef TARGET_AARCH64 1274433bf0SRichard Henderson # define TARGET_LONG_BITS 64 137a928f43SRichard Henderson # define TARGET_PHYS_ADDR_SPACE_BITS 52 140af312b6SRichard Henderson # define TARGET_VIRT_ADDR_SPACE_BITS 52 1574433bf0SRichard Henderson #else 1674433bf0SRichard Henderson # define TARGET_LONG_BITS 32 1774433bf0SRichard Henderson # define TARGET_PHYS_ADDR_SPACE_BITS 40 1874433bf0SRichard Henderson # define TARGET_VIRT_ADDR_SPACE_BITS 32 1974433bf0SRichard Henderson #endif 2074433bf0SRichard Henderson 2174433bf0SRichard Henderson #ifdef CONFIG_USER_ONLY 2274433bf0SRichard Henderson #define TARGET_PAGE_BITS 12 230e0c030cSRichard Henderson # ifdef TARGET_AARCH64 240e0c030cSRichard Henderson # define TARGET_TAGGED_ADDRESSES 250e0c030cSRichard Henderson # endif 2674433bf0SRichard Henderson #else 2774433bf0SRichard Henderson /* 2874433bf0SRichard Henderson * ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6 2974433bf0SRichard Henderson * have to support 1K tiny pages. 3074433bf0SRichard Henderson */ 3174433bf0SRichard Henderson # define TARGET_PAGE_BITS_VARY 3274433bf0SRichard Henderson # define TARGET_PAGE_BITS_MIN 10 33*24d18d5dSRichard Henderson 34*24d18d5dSRichard Henderson /* 35*24d18d5dSRichard Henderson * Cache the attrs and shareability fields from the page table entry. 36*24d18d5dSRichard Henderson * 37*24d18d5dSRichard Henderson * For ARMMMUIdx_Stage2*, pte_attrs is the S2 descriptor bits [5:2]. 38*24d18d5dSRichard Henderson * Otherwise, pte_attrs is the same as the MAIR_EL1 8-bit format. 39*24d18d5dSRichard Henderson * For shareability, as in the SH field of the VMSAv8-64 PTEs. 40*24d18d5dSRichard Henderson */ 41*24d18d5dSRichard Henderson # define TARGET_PAGE_ENTRY_EXTRA \ 42*24d18d5dSRichard Henderson uint8_t pte_attrs; \ 43*24d18d5dSRichard Henderson uint8_t shareability; 44*24d18d5dSRichard Henderson 4574433bf0SRichard Henderson #endif 4674433bf0SRichard Henderson 47d902ae75SRichard Henderson #define NB_MMU_MODES 8 4874433bf0SRichard Henderson 4974433bf0SRichard Henderson #endif 50