1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 #ifndef QEMU_ARM_CPU_QOM_H 21 #define QEMU_ARM_CPU_QOM_H 22 23 #include "hw/core/cpu.h" 24 #include "qom/object.h" 25 26 struct arm_boot_info; 27 28 #define TYPE_ARM_CPU "arm-cpu" 29 30 typedef struct ARMCPU ARMCPU; 31 typedef struct ARMCPUClass ARMCPUClass; 32 DECLARE_OBJ_CHECKERS(ARMCPU, ARMCPUClass, 33 ARM_CPU, TYPE_ARM_CPU) 34 35 #define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU 36 37 typedef struct ARMCPUInfo { 38 const char *name; 39 void (*initfn)(Object *obj); 40 void (*class_init)(ObjectClass *oc, void *data); 41 } ARMCPUInfo; 42 43 void arm_cpu_register(const ARMCPUInfo *info); 44 void aarch64_cpu_register(const ARMCPUInfo *info); 45 46 /** 47 * ARMCPUClass: 48 * @parent_realize: The parent class' realize handler. 49 * @parent_reset: The parent class' reset handler. 50 * 51 * An ARM CPU model. 52 */ 53 struct ARMCPUClass { 54 /*< private >*/ 55 CPUClass parent_class; 56 /*< public >*/ 57 58 const ARMCPUInfo *info; 59 DeviceRealize parent_realize; 60 DeviceReset parent_reset; 61 }; 62 63 64 #define TYPE_AARCH64_CPU "aarch64-cpu" 65 typedef struct AArch64CPUClass AArch64CPUClass; 66 DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU, 67 TYPE_AARCH64_CPU) 68 69 struct AArch64CPUClass { 70 /*< private >*/ 71 ARMCPUClass parent_class; 72 /*< public >*/ 73 }; 74 75 void register_cp_regs_for_features(ARMCPU *cpu); 76 void init_cpreg_list(ARMCPU *cpu); 77 78 /* Callback functions for the generic timer's timers. */ 79 void arm_gt_ptimer_cb(void *opaque); 80 void arm_gt_vtimer_cb(void *opaque); 81 void arm_gt_htimer_cb(void *opaque); 82 void arm_gt_stimer_cb(void *opaque); 83 void arm_gt_hvtimer_cb(void *opaque); 84 85 #define ARM_AFF0_SHIFT 0 86 #define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) 87 #define ARM_AFF1_SHIFT 8 88 #define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT) 89 #define ARM_AFF2_SHIFT 16 90 #define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT) 91 #define ARM_AFF3_SHIFT 32 92 #define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT) 93 #define ARM_DEFAULT_CPUS_PER_CLUSTER 8 94 95 #define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK) 96 #define ARM64_AFFINITY_MASK \ 97 (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK) 98 #define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK) 99 100 #endif 101