1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/qemu-print.h" 23 #include "qemu/timer.h" 24 #include "qemu/log.h" 25 #include "exec/page-vary.h" 26 #include "target/arm/idau.h" 27 #include "qemu/module.h" 28 #include "qapi/error.h" 29 #include "qapi/visitor.h" 30 #include "cpu.h" 31 #ifdef CONFIG_TCG 32 #include "hw/core/tcg-cpu-ops.h" 33 #endif /* CONFIG_TCG */ 34 #include "internals.h" 35 #include "exec/exec-all.h" 36 #include "hw/qdev-properties.h" 37 #if !defined(CONFIG_USER_ONLY) 38 #include "hw/loader.h" 39 #include "hw/boards.h" 40 #endif 41 #include "sysemu/tcg.h" 42 #include "sysemu/qtest.h" 43 #include "sysemu/hw_accel.h" 44 #include "kvm_arm.h" 45 #include "disas/capstone.h" 46 #include "fpu/softfloat.h" 47 #include "cpregs.h" 48 49 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 50 { 51 ARMCPU *cpu = ARM_CPU(cs); 52 CPUARMState *env = &cpu->env; 53 54 if (is_a64(env)) { 55 env->pc = value; 56 env->thumb = false; 57 } else { 58 env->regs[15] = value & ~1; 59 env->thumb = value & 1; 60 } 61 } 62 63 static vaddr arm_cpu_get_pc(CPUState *cs) 64 { 65 ARMCPU *cpu = ARM_CPU(cs); 66 CPUARMState *env = &cpu->env; 67 68 if (is_a64(env)) { 69 return env->pc; 70 } else { 71 return env->regs[15]; 72 } 73 } 74 75 #ifdef CONFIG_TCG 76 void arm_cpu_synchronize_from_tb(CPUState *cs, 77 const TranslationBlock *tb) 78 { 79 /* The program counter is always up to date with TARGET_TB_PCREL. */ 80 if (!TARGET_TB_PCREL) { 81 CPUARMState *env = cs->env_ptr; 82 /* 83 * It's OK to look at env for the current mode here, because it's 84 * never possible for an AArch64 TB to chain to an AArch32 TB. 85 */ 86 if (is_a64(env)) { 87 env->pc = tb_pc(tb); 88 } else { 89 env->regs[15] = tb_pc(tb); 90 } 91 } 92 } 93 94 void arm_restore_state_to_opc(CPUState *cs, 95 const TranslationBlock *tb, 96 const uint64_t *data) 97 { 98 CPUARMState *env = cs->env_ptr; 99 100 if (is_a64(env)) { 101 if (TARGET_TB_PCREL) { 102 env->pc = (env->pc & TARGET_PAGE_MASK) | data[0]; 103 } else { 104 env->pc = data[0]; 105 } 106 env->condexec_bits = 0; 107 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT; 108 } else { 109 if (TARGET_TB_PCREL) { 110 env->regs[15] = (env->regs[15] & TARGET_PAGE_MASK) | data[0]; 111 } else { 112 env->regs[15] = data[0]; 113 } 114 env->condexec_bits = data[1]; 115 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT; 116 } 117 } 118 #endif /* CONFIG_TCG */ 119 120 static bool arm_cpu_has_work(CPUState *cs) 121 { 122 ARMCPU *cpu = ARM_CPU(cs); 123 124 return (cpu->power_state != PSCI_OFF) 125 && cs->interrupt_request & 126 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 127 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR 128 | CPU_INTERRUPT_EXITTB); 129 } 130 131 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 132 void *opaque) 133 { 134 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 135 136 entry->hook = hook; 137 entry->opaque = opaque; 138 139 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 140 } 141 142 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 143 void *opaque) 144 { 145 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 146 147 entry->hook = hook; 148 entry->opaque = opaque; 149 150 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 151 } 152 153 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 154 { 155 /* Reset a single ARMCPRegInfo register */ 156 ARMCPRegInfo *ri = value; 157 ARMCPU *cpu = opaque; 158 159 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS)) { 160 return; 161 } 162 163 if (ri->resetfn) { 164 ri->resetfn(&cpu->env, ri); 165 return; 166 } 167 168 /* A zero offset is never possible as it would be regs[0] 169 * so we use it to indicate that reset is being handled elsewhere. 170 * This is basically only used for fields in non-core coprocessors 171 * (like the pxa2xx ones). 172 */ 173 if (!ri->fieldoffset) { 174 return; 175 } 176 177 if (cpreg_field_is_64bit(ri)) { 178 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 179 } else { 180 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 181 } 182 } 183 184 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 185 { 186 /* Purely an assertion check: we've already done reset once, 187 * so now check that running the reset for the cpreg doesn't 188 * change its value. This traps bugs where two different cpregs 189 * both try to reset the same state field but to different values. 190 */ 191 ARMCPRegInfo *ri = value; 192 ARMCPU *cpu = opaque; 193 uint64_t oldvalue, newvalue; 194 195 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 196 return; 197 } 198 199 oldvalue = read_raw_cp_reg(&cpu->env, ri); 200 cp_reg_reset(key, value, opaque); 201 newvalue = read_raw_cp_reg(&cpu->env, ri); 202 assert(oldvalue == newvalue); 203 } 204 205 static void arm_cpu_reset_hold(Object *obj) 206 { 207 CPUState *s = CPU(obj); 208 ARMCPU *cpu = ARM_CPU(s); 209 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 210 CPUARMState *env = &cpu->env; 211 212 if (acc->parent_phases.hold) { 213 acc->parent_phases.hold(obj); 214 } 215 216 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 217 218 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 219 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 220 221 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 222 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 223 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 224 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 225 226 cpu->power_state = s->start_powered_off ? PSCI_OFF : PSCI_ON; 227 228 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 229 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 230 } 231 232 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 233 /* 64 bit CPUs always start in 64 bit mode */ 234 env->aarch64 = true; 235 #if defined(CONFIG_USER_ONLY) 236 env->pstate = PSTATE_MODE_EL0t; 237 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 238 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 239 /* Enable all PAC keys. */ 240 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | 241 SCTLR_EnDA | SCTLR_EnDB); 242 /* Trap on btype=3 for PACIxSP. */ 243 env->cp15.sctlr_el[1] |= SCTLR_BT0; 244 /* and to the FP/Neon instructions */ 245 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 246 CPACR_EL1, FPEN, 3); 247 /* and to the SVE instructions, with default vector length */ 248 if (cpu_isar_feature(aa64_sve, cpu)) { 249 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 250 CPACR_EL1, ZEN, 3); 251 env->vfp.zcr_el[1] = cpu->sve_default_vq - 1; 252 } 253 /* and for SME instructions, with default vector length, and TPIDR2 */ 254 if (cpu_isar_feature(aa64_sme, cpu)) { 255 env->cp15.sctlr_el[1] |= SCTLR_EnTP2; 256 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 257 CPACR_EL1, SMEN, 3); 258 env->vfp.smcr_el[1] = cpu->sme_default_vq - 1; 259 if (cpu_isar_feature(aa64_sme_fa64, cpu)) { 260 env->vfp.smcr_el[1] = FIELD_DP64(env->vfp.smcr_el[1], 261 SMCR, FA64, 1); 262 } 263 } 264 /* 265 * Enable 48-bit address space (TODO: take reserved_va into account). 266 * Enable TBI0 but not TBI1. 267 * Note that this must match useronly_clean_ptr. 268 */ 269 env->cp15.tcr_el[1] = 5 | (1ULL << 37); 270 271 /* Enable MTE */ 272 if (cpu_isar_feature(aa64_mte, cpu)) { 273 /* Enable tag access, but leave TCF0 as No Effect (0). */ 274 env->cp15.sctlr_el[1] |= SCTLR_ATA0; 275 /* 276 * Exclude all tags, so that tag 0 is always used. 277 * This corresponds to Linux current->thread.gcr_incl = 0. 278 * 279 * Set RRND, so that helper_irg() will generate a seed later. 280 * Here in cpu_reset(), the crypto subsystem has not yet been 281 * initialized. 282 */ 283 env->cp15.gcr_el1 = 0x1ffff; 284 } 285 /* 286 * Disable access to SCXTNUM_EL0 from CSV2_1p2. 287 * This is not yet exposed from the Linux kernel in any way. 288 */ 289 env->cp15.sctlr_el[1] |= SCTLR_TSCXT; 290 #else 291 /* Reset into the highest available EL */ 292 if (arm_feature(env, ARM_FEATURE_EL3)) { 293 env->pstate = PSTATE_MODE_EL3h; 294 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 295 env->pstate = PSTATE_MODE_EL2h; 296 } else { 297 env->pstate = PSTATE_MODE_EL1h; 298 } 299 300 /* Sample rvbar at reset. */ 301 env->cp15.rvbar = cpu->rvbar_prop; 302 env->pc = env->cp15.rvbar; 303 #endif 304 } else { 305 #if defined(CONFIG_USER_ONLY) 306 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 307 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 308 CPACR, CP10, 3); 309 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 310 CPACR, CP11, 3); 311 #endif 312 } 313 314 #if defined(CONFIG_USER_ONLY) 315 env->uncached_cpsr = ARM_CPU_MODE_USR; 316 /* For user mode we must enable access to coprocessors */ 317 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 318 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 319 env->cp15.c15_cpar = 3; 320 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 321 env->cp15.c15_cpar = 1; 322 } 323 #else 324 325 /* 326 * If the highest available EL is EL2, AArch32 will start in Hyp 327 * mode; otherwise it starts in SVC. Note that if we start in 328 * AArch64 then these values in the uncached_cpsr will be ignored. 329 */ 330 if (arm_feature(env, ARM_FEATURE_EL2) && 331 !arm_feature(env, ARM_FEATURE_EL3)) { 332 env->uncached_cpsr = ARM_CPU_MODE_HYP; 333 } else { 334 env->uncached_cpsr = ARM_CPU_MODE_SVC; 335 } 336 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 337 338 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 339 * executing as AArch32 then check if highvecs are enabled and 340 * adjust the PC accordingly. 341 */ 342 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 343 env->regs[15] = 0xFFFF0000; 344 } 345 346 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 347 #endif 348 349 if (arm_feature(env, ARM_FEATURE_M)) { 350 #ifndef CONFIG_USER_ONLY 351 uint32_t initial_msp; /* Loaded from 0x0 */ 352 uint32_t initial_pc; /* Loaded from 0x4 */ 353 uint8_t *rom; 354 uint32_t vecbase; 355 #endif 356 357 if (cpu_isar_feature(aa32_lob, cpu)) { 358 /* 359 * LTPSIZE is constant 4 if MVE not implemented, and resets 360 * to an UNKNOWN value if MVE is implemented. We choose to 361 * always reset to 4. 362 */ 363 env->v7m.ltpsize = 4; 364 /* The LTPSIZE field in FPDSCR is constant and reads as 4. */ 365 env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT; 366 env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT; 367 } 368 369 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 370 env->v7m.secure = true; 371 } else { 372 /* This bit resets to 0 if security is supported, but 1 if 373 * it is not. The bit is not present in v7M, but we set it 374 * here so we can avoid having to make checks on it conditional 375 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 376 */ 377 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 378 /* 379 * Set NSACR to indicate "NS access permitted to everything"; 380 * this avoids having to have all the tests of it being 381 * conditional on ARM_FEATURE_M_SECURITY. Note also that from 382 * v8.1M the guest-visible value of NSACR in a CPU without the 383 * Security Extension is 0xcff. 384 */ 385 env->v7m.nsacr = 0xcff; 386 } 387 388 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 389 * that it resets to 1, so QEMU always does that rather than making 390 * it dependent on CPU model. In v8M it is RES1. 391 */ 392 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 393 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 394 if (arm_feature(env, ARM_FEATURE_V8)) { 395 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 396 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 397 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 398 } 399 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 400 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 401 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 402 } 403 404 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 405 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; 406 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | 407 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; 408 } 409 410 #ifndef CONFIG_USER_ONLY 411 /* Unlike A/R profile, M profile defines the reset LR value */ 412 env->regs[14] = 0xffffffff; 413 414 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 415 env->v7m.vecbase[M_REG_NS] = cpu->init_nsvtor & 0xffffff80; 416 417 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 418 vecbase = env->v7m.vecbase[env->v7m.secure]; 419 rom = rom_ptr_for_as(s->as, vecbase, 8); 420 if (rom) { 421 /* Address zero is covered by ROM which hasn't yet been 422 * copied into physical memory. 423 */ 424 initial_msp = ldl_p(rom); 425 initial_pc = ldl_p(rom + 4); 426 } else { 427 /* Address zero not covered by a ROM blob, or the ROM blob 428 * is in non-modifiable memory and this is a second reset after 429 * it got copied into memory. In the latter case, rom_ptr 430 * will return a NULL pointer and we should use ldl_phys instead. 431 */ 432 initial_msp = ldl_phys(s->as, vecbase); 433 initial_pc = ldl_phys(s->as, vecbase + 4); 434 } 435 436 qemu_log_mask(CPU_LOG_INT, 437 "Loaded reset SP 0x%x PC 0x%x from vector table\n", 438 initial_msp, initial_pc); 439 440 env->regs[13] = initial_msp & 0xFFFFFFFC; 441 env->regs[15] = initial_pc & ~1; 442 env->thumb = initial_pc & 1; 443 #else 444 /* 445 * For user mode we run non-secure and with access to the FPU. 446 * The FPU context is active (ie does not need further setup) 447 * and is owned by non-secure. 448 */ 449 env->v7m.secure = false; 450 env->v7m.nsacr = 0xcff; 451 env->v7m.cpacr[M_REG_NS] = 0xf0ffff; 452 env->v7m.fpccr[M_REG_S] &= 453 ~(R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK); 454 env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK; 455 #endif 456 } 457 458 /* M profile requires that reset clears the exclusive monitor; 459 * A profile does not, but clearing it makes more sense than having it 460 * set with an exclusive access on address zero. 461 */ 462 arm_clear_exclusive(env); 463 464 if (arm_feature(env, ARM_FEATURE_PMSA)) { 465 if (cpu->pmsav7_dregion > 0) { 466 if (arm_feature(env, ARM_FEATURE_V8)) { 467 memset(env->pmsav8.rbar[M_REG_NS], 0, 468 sizeof(*env->pmsav8.rbar[M_REG_NS]) 469 * cpu->pmsav7_dregion); 470 memset(env->pmsav8.rlar[M_REG_NS], 0, 471 sizeof(*env->pmsav8.rlar[M_REG_NS]) 472 * cpu->pmsav7_dregion); 473 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 474 memset(env->pmsav8.rbar[M_REG_S], 0, 475 sizeof(*env->pmsav8.rbar[M_REG_S]) 476 * cpu->pmsav7_dregion); 477 memset(env->pmsav8.rlar[M_REG_S], 0, 478 sizeof(*env->pmsav8.rlar[M_REG_S]) 479 * cpu->pmsav7_dregion); 480 } 481 } else if (arm_feature(env, ARM_FEATURE_V7)) { 482 memset(env->pmsav7.drbar, 0, 483 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 484 memset(env->pmsav7.drsr, 0, 485 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 486 memset(env->pmsav7.dracr, 0, 487 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 488 } 489 } 490 env->pmsav7.rnr[M_REG_NS] = 0; 491 env->pmsav7.rnr[M_REG_S] = 0; 492 env->pmsav8.mair0[M_REG_NS] = 0; 493 env->pmsav8.mair0[M_REG_S] = 0; 494 env->pmsav8.mair1[M_REG_NS] = 0; 495 env->pmsav8.mair1[M_REG_S] = 0; 496 } 497 498 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 499 if (cpu->sau_sregion > 0) { 500 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 501 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 502 } 503 env->sau.rnr = 0; 504 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 505 * the Cortex-M33 does. 506 */ 507 env->sau.ctrl = 0; 508 } 509 510 set_flush_to_zero(1, &env->vfp.standard_fp_status); 511 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 512 set_default_nan_mode(1, &env->vfp.standard_fp_status); 513 set_default_nan_mode(1, &env->vfp.standard_fp_status_f16); 514 set_float_detect_tininess(float_tininess_before_rounding, 515 &env->vfp.fp_status); 516 set_float_detect_tininess(float_tininess_before_rounding, 517 &env->vfp.standard_fp_status); 518 set_float_detect_tininess(float_tininess_before_rounding, 519 &env->vfp.fp_status_f16); 520 set_float_detect_tininess(float_tininess_before_rounding, 521 &env->vfp.standard_fp_status_f16); 522 #ifndef CONFIG_USER_ONLY 523 if (kvm_enabled()) { 524 kvm_arm_reset_vcpu(cpu); 525 } 526 #endif 527 528 hw_breakpoint_update_all(cpu); 529 hw_watchpoint_update_all(cpu); 530 arm_rebuild_hflags(env); 531 } 532 533 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 534 535 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 536 unsigned int target_el, 537 unsigned int cur_el, bool secure, 538 uint64_t hcr_el2) 539 { 540 CPUARMState *env = cs->env_ptr; 541 bool pstate_unmasked; 542 bool unmasked = false; 543 544 /* 545 * Don't take exceptions if they target a lower EL. 546 * This check should catch any exceptions that would not be taken 547 * but left pending. 548 */ 549 if (cur_el > target_el) { 550 return false; 551 } 552 553 switch (excp_idx) { 554 case EXCP_FIQ: 555 pstate_unmasked = !(env->daif & PSTATE_F); 556 break; 557 558 case EXCP_IRQ: 559 pstate_unmasked = !(env->daif & PSTATE_I); 560 break; 561 562 case EXCP_VFIQ: 563 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 564 /* VFIQs are only taken when hypervized. */ 565 return false; 566 } 567 return !(env->daif & PSTATE_F); 568 case EXCP_VIRQ: 569 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 570 /* VIRQs are only taken when hypervized. */ 571 return false; 572 } 573 return !(env->daif & PSTATE_I); 574 case EXCP_VSERR: 575 if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) { 576 /* VIRQs are only taken when hypervized. */ 577 return false; 578 } 579 return !(env->daif & PSTATE_A); 580 default: 581 g_assert_not_reached(); 582 } 583 584 /* 585 * Use the target EL, current execution state and SCR/HCR settings to 586 * determine whether the corresponding CPSR bit is used to mask the 587 * interrupt. 588 */ 589 if ((target_el > cur_el) && (target_el != 1)) { 590 /* Exceptions targeting a higher EL may not be maskable */ 591 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 592 switch (target_el) { 593 case 2: 594 /* 595 * According to ARM DDI 0487H.a, an interrupt can be masked 596 * when HCR_E2H and HCR_TGE are both set regardless of the 597 * current Security state. Note that we need to revisit this 598 * part again once we need to support NMI. 599 */ 600 if ((hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { 601 unmasked = true; 602 } 603 break; 604 case 3: 605 /* Interrupt cannot be masked when the target EL is 3 */ 606 unmasked = true; 607 break; 608 default: 609 g_assert_not_reached(); 610 } 611 } else { 612 /* 613 * The old 32-bit-only environment has a more complicated 614 * masking setup. HCR and SCR bits not only affect interrupt 615 * routing but also change the behaviour of masking. 616 */ 617 bool hcr, scr; 618 619 switch (excp_idx) { 620 case EXCP_FIQ: 621 /* 622 * If FIQs are routed to EL3 or EL2 then there are cases where 623 * we override the CPSR.F in determining if the exception is 624 * masked or not. If neither of these are set then we fall back 625 * to the CPSR.F setting otherwise we further assess the state 626 * below. 627 */ 628 hcr = hcr_el2 & HCR_FMO; 629 scr = (env->cp15.scr_el3 & SCR_FIQ); 630 631 /* 632 * When EL3 is 32-bit, the SCR.FW bit controls whether the 633 * CPSR.F bit masks FIQ interrupts when taken in non-secure 634 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 635 * when non-secure but only when FIQs are only routed to EL3. 636 */ 637 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 638 break; 639 case EXCP_IRQ: 640 /* 641 * When EL3 execution state is 32-bit, if HCR.IMO is set then 642 * we may override the CPSR.I masking when in non-secure state. 643 * The SCR.IRQ setting has already been taken into consideration 644 * when setting the target EL, so it does not have a further 645 * affect here. 646 */ 647 hcr = hcr_el2 & HCR_IMO; 648 scr = false; 649 break; 650 default: 651 g_assert_not_reached(); 652 } 653 654 if ((scr || hcr) && !secure) { 655 unmasked = true; 656 } 657 } 658 } 659 660 /* 661 * The PSTATE bits only mask the interrupt if we have not overriden the 662 * ability above. 663 */ 664 return unmasked || pstate_unmasked; 665 } 666 667 static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 668 { 669 CPUClass *cc = CPU_GET_CLASS(cs); 670 CPUARMState *env = cs->env_ptr; 671 uint32_t cur_el = arm_current_el(env); 672 bool secure = arm_is_secure(env); 673 uint64_t hcr_el2 = arm_hcr_el2_eff(env); 674 uint32_t target_el; 675 uint32_t excp_idx; 676 677 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ 678 679 if (interrupt_request & CPU_INTERRUPT_FIQ) { 680 excp_idx = EXCP_FIQ; 681 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 682 if (arm_excp_unmasked(cs, excp_idx, target_el, 683 cur_el, secure, hcr_el2)) { 684 goto found; 685 } 686 } 687 if (interrupt_request & CPU_INTERRUPT_HARD) { 688 excp_idx = EXCP_IRQ; 689 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 690 if (arm_excp_unmasked(cs, excp_idx, target_el, 691 cur_el, secure, hcr_el2)) { 692 goto found; 693 } 694 } 695 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 696 excp_idx = EXCP_VIRQ; 697 target_el = 1; 698 if (arm_excp_unmasked(cs, excp_idx, target_el, 699 cur_el, secure, hcr_el2)) { 700 goto found; 701 } 702 } 703 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 704 excp_idx = EXCP_VFIQ; 705 target_el = 1; 706 if (arm_excp_unmasked(cs, excp_idx, target_el, 707 cur_el, secure, hcr_el2)) { 708 goto found; 709 } 710 } 711 if (interrupt_request & CPU_INTERRUPT_VSERR) { 712 excp_idx = EXCP_VSERR; 713 target_el = 1; 714 if (arm_excp_unmasked(cs, excp_idx, target_el, 715 cur_el, secure, hcr_el2)) { 716 /* Taking a virtual abort clears HCR_EL2.VSE */ 717 env->cp15.hcr_el2 &= ~HCR_VSE; 718 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); 719 goto found; 720 } 721 } 722 return false; 723 724 found: 725 cs->exception_index = excp_idx; 726 env->exception.target_el = target_el; 727 cc->tcg_ops->do_interrupt(cs); 728 return true; 729 } 730 731 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ 732 733 void arm_cpu_update_virq(ARMCPU *cpu) 734 { 735 /* 736 * Update the interrupt level for VIRQ, which is the logical OR of 737 * the HCR_EL2.VI bit and the input line level from the GIC. 738 */ 739 CPUARMState *env = &cpu->env; 740 CPUState *cs = CPU(cpu); 741 742 bool new_state = (env->cp15.hcr_el2 & HCR_VI) || 743 (env->irq_line_state & CPU_INTERRUPT_VIRQ); 744 745 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { 746 if (new_state) { 747 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); 748 } else { 749 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); 750 } 751 } 752 } 753 754 void arm_cpu_update_vfiq(ARMCPU *cpu) 755 { 756 /* 757 * Update the interrupt level for VFIQ, which is the logical OR of 758 * the HCR_EL2.VF bit and the input line level from the GIC. 759 */ 760 CPUARMState *env = &cpu->env; 761 CPUState *cs = CPU(cpu); 762 763 bool new_state = (env->cp15.hcr_el2 & HCR_VF) || 764 (env->irq_line_state & CPU_INTERRUPT_VFIQ); 765 766 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { 767 if (new_state) { 768 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); 769 } else { 770 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); 771 } 772 } 773 } 774 775 void arm_cpu_update_vserr(ARMCPU *cpu) 776 { 777 /* 778 * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit. 779 */ 780 CPUARMState *env = &cpu->env; 781 CPUState *cs = CPU(cpu); 782 783 bool new_state = env->cp15.hcr_el2 & HCR_VSE; 784 785 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) { 786 if (new_state) { 787 cpu_interrupt(cs, CPU_INTERRUPT_VSERR); 788 } else { 789 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); 790 } 791 } 792 } 793 794 #ifndef CONFIG_USER_ONLY 795 static void arm_cpu_set_irq(void *opaque, int irq, int level) 796 { 797 ARMCPU *cpu = opaque; 798 CPUARMState *env = &cpu->env; 799 CPUState *cs = CPU(cpu); 800 static const int mask[] = { 801 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 802 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 803 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 804 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 805 }; 806 807 if (!arm_feature(env, ARM_FEATURE_EL2) && 808 (irq == ARM_CPU_VIRQ || irq == ARM_CPU_VFIQ)) { 809 /* 810 * The GIC might tell us about VIRQ and VFIQ state, but if we don't 811 * have EL2 support we don't care. (Unless the guest is doing something 812 * silly this will only be calls saying "level is still 0".) 813 */ 814 return; 815 } 816 817 if (level) { 818 env->irq_line_state |= mask[irq]; 819 } else { 820 env->irq_line_state &= ~mask[irq]; 821 } 822 823 switch (irq) { 824 case ARM_CPU_VIRQ: 825 arm_cpu_update_virq(cpu); 826 break; 827 case ARM_CPU_VFIQ: 828 arm_cpu_update_vfiq(cpu); 829 break; 830 case ARM_CPU_IRQ: 831 case ARM_CPU_FIQ: 832 if (level) { 833 cpu_interrupt(cs, mask[irq]); 834 } else { 835 cpu_reset_interrupt(cs, mask[irq]); 836 } 837 break; 838 default: 839 g_assert_not_reached(); 840 } 841 } 842 843 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 844 { 845 #ifdef CONFIG_KVM 846 ARMCPU *cpu = opaque; 847 CPUARMState *env = &cpu->env; 848 CPUState *cs = CPU(cpu); 849 uint32_t linestate_bit; 850 int irq_id; 851 852 switch (irq) { 853 case ARM_CPU_IRQ: 854 irq_id = KVM_ARM_IRQ_CPU_IRQ; 855 linestate_bit = CPU_INTERRUPT_HARD; 856 break; 857 case ARM_CPU_FIQ: 858 irq_id = KVM_ARM_IRQ_CPU_FIQ; 859 linestate_bit = CPU_INTERRUPT_FIQ; 860 break; 861 default: 862 g_assert_not_reached(); 863 } 864 865 if (level) { 866 env->irq_line_state |= linestate_bit; 867 } else { 868 env->irq_line_state &= ~linestate_bit; 869 } 870 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); 871 #endif 872 } 873 874 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 875 { 876 ARMCPU *cpu = ARM_CPU(cs); 877 CPUARMState *env = &cpu->env; 878 879 cpu_synchronize_state(cs); 880 return arm_cpu_data_is_big_endian(env); 881 } 882 883 #endif 884 885 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 886 { 887 ARMCPU *ac = ARM_CPU(cpu); 888 CPUARMState *env = &ac->env; 889 bool sctlr_b; 890 891 if (is_a64(env)) { 892 info->cap_arch = CS_ARCH_ARM64; 893 info->cap_insn_unit = 4; 894 info->cap_insn_split = 4; 895 } else { 896 int cap_mode; 897 if (env->thumb) { 898 info->cap_insn_unit = 2; 899 info->cap_insn_split = 4; 900 cap_mode = CS_MODE_THUMB; 901 } else { 902 info->cap_insn_unit = 4; 903 info->cap_insn_split = 4; 904 cap_mode = CS_MODE_ARM; 905 } 906 if (arm_feature(env, ARM_FEATURE_V8)) { 907 cap_mode |= CS_MODE_V8; 908 } 909 if (arm_feature(env, ARM_FEATURE_M)) { 910 cap_mode |= CS_MODE_MCLASS; 911 } 912 info->cap_arch = CS_ARCH_ARM; 913 info->cap_mode = cap_mode; 914 } 915 916 sctlr_b = arm_sctlr_b(env); 917 if (bswap_code(sctlr_b)) { 918 #if TARGET_BIG_ENDIAN 919 info->endian = BFD_ENDIAN_LITTLE; 920 #else 921 info->endian = BFD_ENDIAN_BIG; 922 #endif 923 } 924 info->flags &= ~INSN_ARM_BE32; 925 #ifndef CONFIG_USER_ONLY 926 if (sctlr_b) { 927 info->flags |= INSN_ARM_BE32; 928 } 929 #endif 930 } 931 932 #ifdef TARGET_AARCH64 933 934 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 935 { 936 ARMCPU *cpu = ARM_CPU(cs); 937 CPUARMState *env = &cpu->env; 938 uint32_t psr = pstate_read(env); 939 int i; 940 int el = arm_current_el(env); 941 const char *ns_status; 942 bool sve; 943 944 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 945 for (i = 0; i < 32; i++) { 946 if (i == 31) { 947 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); 948 } else { 949 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], 950 (i + 2) % 3 ? " " : "\n"); 951 } 952 } 953 954 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { 955 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 956 } else { 957 ns_status = ""; 958 } 959 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c", 960 psr, 961 psr & PSTATE_N ? 'N' : '-', 962 psr & PSTATE_Z ? 'Z' : '-', 963 psr & PSTATE_C ? 'C' : '-', 964 psr & PSTATE_V ? 'V' : '-', 965 ns_status, 966 el, 967 psr & PSTATE_SP ? 'h' : 't'); 968 969 if (cpu_isar_feature(aa64_sme, cpu)) { 970 qemu_fprintf(f, " SVCR=%08" PRIx64 " %c%c", 971 env->svcr, 972 (FIELD_EX64(env->svcr, SVCR, ZA) ? 'Z' : '-'), 973 (FIELD_EX64(env->svcr, SVCR, SM) ? 'S' : '-')); 974 } 975 if (cpu_isar_feature(aa64_bti, cpu)) { 976 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); 977 } 978 if (!(flags & CPU_DUMP_FPU)) { 979 qemu_fprintf(f, "\n"); 980 return; 981 } 982 if (fp_exception_el(env, el) != 0) { 983 qemu_fprintf(f, " FPU disabled\n"); 984 return; 985 } 986 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", 987 vfp_get_fpcr(env), vfp_get_fpsr(env)); 988 989 if (cpu_isar_feature(aa64_sme, cpu) && FIELD_EX64(env->svcr, SVCR, SM)) { 990 sve = sme_exception_el(env, el) == 0; 991 } else if (cpu_isar_feature(aa64_sve, cpu)) { 992 sve = sve_exception_el(env, el) == 0; 993 } else { 994 sve = false; 995 } 996 997 if (sve) { 998 int j, zcr_len = sve_vqm1_for_el(env, el); 999 1000 for (i = 0; i <= FFR_PRED_NUM; i++) { 1001 bool eol; 1002 if (i == FFR_PRED_NUM) { 1003 qemu_fprintf(f, "FFR="); 1004 /* It's last, so end the line. */ 1005 eol = true; 1006 } else { 1007 qemu_fprintf(f, "P%02d=", i); 1008 switch (zcr_len) { 1009 case 0: 1010 eol = i % 8 == 7; 1011 break; 1012 case 1: 1013 eol = i % 6 == 5; 1014 break; 1015 case 2: 1016 case 3: 1017 eol = i % 3 == 2; 1018 break; 1019 default: 1020 /* More than one quadword per predicate. */ 1021 eol = true; 1022 break; 1023 } 1024 } 1025 for (j = zcr_len / 4; j >= 0; j--) { 1026 int digits; 1027 if (j * 4 + 4 <= zcr_len + 1) { 1028 digits = 16; 1029 } else { 1030 digits = (zcr_len % 4 + 1) * 4; 1031 } 1032 qemu_fprintf(f, "%0*" PRIx64 "%s", digits, 1033 env->vfp.pregs[i].p[j], 1034 j ? ":" : eol ? "\n" : " "); 1035 } 1036 } 1037 1038 for (i = 0; i < 32; i++) { 1039 if (zcr_len == 0) { 1040 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", 1041 i, env->vfp.zregs[i].d[1], 1042 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); 1043 } else if (zcr_len == 1) { 1044 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 1045 ":%016" PRIx64 ":%016" PRIx64 "\n", 1046 i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2], 1047 env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]); 1048 } else { 1049 for (j = zcr_len; j >= 0; j--) { 1050 bool odd = (zcr_len - j) % 2 != 0; 1051 if (j == zcr_len) { 1052 qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1); 1053 } else if (!odd) { 1054 if (j > 0) { 1055 qemu_fprintf(f, " [%x-%x]=", j, j - 1); 1056 } else { 1057 qemu_fprintf(f, " [%x]=", j); 1058 } 1059 } 1060 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", 1061 env->vfp.zregs[i].d[j * 2 + 1], 1062 env->vfp.zregs[i].d[j * 2], 1063 odd || j == 0 ? "\n" : ":"); 1064 } 1065 } 1066 } 1067 } else { 1068 for (i = 0; i < 32; i++) { 1069 uint64_t *q = aa64_vfp_qreg(env, i); 1070 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", 1071 i, q[1], q[0], (i & 1 ? "\n" : " ")); 1072 } 1073 } 1074 } 1075 1076 #else 1077 1078 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1079 { 1080 g_assert_not_reached(); 1081 } 1082 1083 #endif 1084 1085 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1086 { 1087 ARMCPU *cpu = ARM_CPU(cs); 1088 CPUARMState *env = &cpu->env; 1089 int i; 1090 1091 if (is_a64(env)) { 1092 aarch64_cpu_dump_state(cs, f, flags); 1093 return; 1094 } 1095 1096 for (i = 0; i < 16; i++) { 1097 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]); 1098 if ((i % 4) == 3) { 1099 qemu_fprintf(f, "\n"); 1100 } else { 1101 qemu_fprintf(f, " "); 1102 } 1103 } 1104 1105 if (arm_feature(env, ARM_FEATURE_M)) { 1106 uint32_t xpsr = xpsr_read(env); 1107 const char *mode; 1108 const char *ns_status = ""; 1109 1110 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1111 ns_status = env->v7m.secure ? "S " : "NS "; 1112 } 1113 1114 if (xpsr & XPSR_EXCP) { 1115 mode = "handler"; 1116 } else { 1117 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { 1118 mode = "unpriv-thread"; 1119 } else { 1120 mode = "priv-thread"; 1121 } 1122 } 1123 1124 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", 1125 xpsr, 1126 xpsr & XPSR_N ? 'N' : '-', 1127 xpsr & XPSR_Z ? 'Z' : '-', 1128 xpsr & XPSR_C ? 'C' : '-', 1129 xpsr & XPSR_V ? 'V' : '-', 1130 xpsr & XPSR_T ? 'T' : 'A', 1131 ns_status, 1132 mode); 1133 } else { 1134 uint32_t psr = cpsr_read(env); 1135 const char *ns_status = ""; 1136 1137 if (arm_feature(env, ARM_FEATURE_EL3) && 1138 (psr & CPSR_M) != ARM_CPU_MODE_MON) { 1139 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 1140 } 1141 1142 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", 1143 psr, 1144 psr & CPSR_N ? 'N' : '-', 1145 psr & CPSR_Z ? 'Z' : '-', 1146 psr & CPSR_C ? 'C' : '-', 1147 psr & CPSR_V ? 'V' : '-', 1148 psr & CPSR_T ? 'T' : 'A', 1149 ns_status, 1150 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); 1151 } 1152 1153 if (flags & CPU_DUMP_FPU) { 1154 int numvfpregs = 0; 1155 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1156 numvfpregs = 32; 1157 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 1158 numvfpregs = 16; 1159 } 1160 for (i = 0; i < numvfpregs; i++) { 1161 uint64_t v = *aa32_vfp_dreg(env, i); 1162 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", 1163 i * 2, (uint32_t)v, 1164 i * 2 + 1, (uint32_t)(v >> 32), 1165 i, v); 1166 } 1167 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); 1168 if (cpu_isar_feature(aa32_mve, cpu)) { 1169 qemu_fprintf(f, "VPR: %08x\n", env->v7m.vpr); 1170 } 1171 } 1172 } 1173 1174 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 1175 { 1176 uint32_t Aff1 = idx / clustersz; 1177 uint32_t Aff0 = idx % clustersz; 1178 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 1179 } 1180 1181 static void arm_cpu_initfn(Object *obj) 1182 { 1183 ARMCPU *cpu = ARM_CPU(obj); 1184 1185 cpu_set_cpustate_pointers(cpu); 1186 cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal, 1187 NULL, g_free); 1188 1189 QLIST_INIT(&cpu->pre_el_change_hooks); 1190 QLIST_INIT(&cpu->el_change_hooks); 1191 1192 #ifdef CONFIG_USER_ONLY 1193 # ifdef TARGET_AARCH64 1194 /* 1195 * The linux kernel defaults to 512-bit for SVE, and 256-bit for SME. 1196 * These values were chosen to fit within the default signal frame. 1197 * See documentation for /proc/sys/abi/{sve,sme}_default_vector_length, 1198 * and our corresponding cpu property. 1199 */ 1200 cpu->sve_default_vq = 4; 1201 cpu->sme_default_vq = 2; 1202 # endif 1203 #else 1204 /* Our inbound IRQ and FIQ lines */ 1205 if (kvm_enabled()) { 1206 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 1207 * the same interface as non-KVM CPUs. 1208 */ 1209 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 1210 } else { 1211 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 1212 } 1213 1214 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 1215 ARRAY_SIZE(cpu->gt_timer_outputs)); 1216 1217 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 1218 "gicv3-maintenance-interrupt", 1); 1219 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 1220 "pmu-interrupt", 1); 1221 #endif 1222 1223 /* DTB consumers generally don't in fact care what the 'compatible' 1224 * string is, so always provide some string and trust that a hypothetical 1225 * picky DTB consumer will also provide a helpful error message. 1226 */ 1227 cpu->dtb_compatible = "qemu,unknown"; 1228 cpu->psci_version = QEMU_PSCI_VERSION_0_1; /* By default assume PSCI v0.1 */ 1229 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 1230 1231 if (tcg_enabled() || hvf_enabled()) { 1232 /* TCG and HVF implement PSCI 1.1 */ 1233 cpu->psci_version = QEMU_PSCI_VERSION_1_1; 1234 } 1235 } 1236 1237 static Property arm_cpu_gt_cntfrq_property = 1238 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 1239 NANOSECONDS_PER_SECOND / GTIMER_SCALE); 1240 1241 static Property arm_cpu_reset_cbar_property = 1242 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 1243 1244 static Property arm_cpu_reset_hivecs_property = 1245 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 1246 1247 #ifndef CONFIG_USER_ONLY 1248 static Property arm_cpu_has_el2_property = 1249 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 1250 1251 static Property arm_cpu_has_el3_property = 1252 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 1253 #endif 1254 1255 static Property arm_cpu_cfgend_property = 1256 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 1257 1258 static Property arm_cpu_has_vfp_property = 1259 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); 1260 1261 static Property arm_cpu_has_neon_property = 1262 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); 1263 1264 static Property arm_cpu_has_dsp_property = 1265 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); 1266 1267 static Property arm_cpu_has_mpu_property = 1268 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 1269 1270 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 1271 * because the CPU initfn will have already set cpu->pmsav7_dregion to 1272 * the right value for that particular CPU type, and we don't want 1273 * to override that with an incorrect constant value. 1274 */ 1275 static Property arm_cpu_pmsav7_dregion_property = 1276 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 1277 pmsav7_dregion, 1278 qdev_prop_uint32, uint32_t); 1279 1280 static bool arm_get_pmu(Object *obj, Error **errp) 1281 { 1282 ARMCPU *cpu = ARM_CPU(obj); 1283 1284 return cpu->has_pmu; 1285 } 1286 1287 static void arm_set_pmu(Object *obj, bool value, Error **errp) 1288 { 1289 ARMCPU *cpu = ARM_CPU(obj); 1290 1291 if (value) { 1292 if (kvm_enabled() && !kvm_arm_pmu_supported()) { 1293 error_setg(errp, "'pmu' feature not supported by KVM on this host"); 1294 return; 1295 } 1296 set_feature(&cpu->env, ARM_FEATURE_PMU); 1297 } else { 1298 unset_feature(&cpu->env, ARM_FEATURE_PMU); 1299 } 1300 cpu->has_pmu = value; 1301 } 1302 1303 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) 1304 { 1305 /* 1306 * The exact approach to calculating guest ticks is: 1307 * 1308 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz, 1309 * NANOSECONDS_PER_SECOND); 1310 * 1311 * We don't do that. Rather we intentionally use integer division 1312 * truncation below and in the caller for the conversion of host monotonic 1313 * time to guest ticks to provide the exact inverse for the semantics of 1314 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so 1315 * it loses precision when representing frequencies where 1316 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to 1317 * provide an exact inverse leads to scheduling timers with negative 1318 * periods, which in turn leads to sticky behaviour in the guest. 1319 * 1320 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor 1321 * cannot become zero. 1322 */ 1323 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ? 1324 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; 1325 } 1326 1327 void arm_cpu_post_init(Object *obj) 1328 { 1329 ARMCPU *cpu = ARM_CPU(obj); 1330 1331 /* M profile implies PMSA. We have to do this here rather than 1332 * in realize with the other feature-implication checks because 1333 * we look at the PMSA bit to see if we should add some properties. 1334 */ 1335 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1336 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1337 } 1338 1339 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 1340 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 1341 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); 1342 } 1343 1344 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 1345 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); 1346 } 1347 1348 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1349 object_property_add_uint64_ptr(obj, "rvbar", 1350 &cpu->rvbar_prop, 1351 OBJ_PROP_FLAG_READWRITE); 1352 } 1353 1354 #ifndef CONFIG_USER_ONLY 1355 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1356 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 1357 * prevent "has_el3" from existing on CPUs which cannot support EL3. 1358 */ 1359 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); 1360 1361 object_property_add_link(obj, "secure-memory", 1362 TYPE_MEMORY_REGION, 1363 (Object **)&cpu->secure_memory, 1364 qdev_prop_allow_set_link_before_realize, 1365 OBJ_PROP_LINK_STRONG); 1366 } 1367 1368 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 1369 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); 1370 } 1371 #endif 1372 1373 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 1374 cpu->has_pmu = true; 1375 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu); 1376 } 1377 1378 /* 1379 * Allow user to turn off VFP and Neon support, but only for TCG -- 1380 * KVM does not currently allow us to lie to the guest about its 1381 * ID/feature registers, so the guest always sees what the host has. 1382 */ 1383 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) 1384 ? cpu_isar_feature(aa64_fp_simd, cpu) 1385 : cpu_isar_feature(aa32_vfp, cpu)) { 1386 cpu->has_vfp = true; 1387 if (!kvm_enabled()) { 1388 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property); 1389 } 1390 } 1391 1392 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { 1393 cpu->has_neon = true; 1394 if (!kvm_enabled()) { 1395 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property); 1396 } 1397 } 1398 1399 if (arm_feature(&cpu->env, ARM_FEATURE_M) && 1400 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { 1401 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property); 1402 } 1403 1404 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 1405 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); 1406 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1407 qdev_property_add_static(DEVICE(obj), 1408 &arm_cpu_pmsav7_dregion_property); 1409 } 1410 } 1411 1412 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 1413 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 1414 qdev_prop_allow_set_link_before_realize, 1415 OBJ_PROP_LINK_STRONG); 1416 /* 1417 * M profile: initial value of the Secure VTOR. We can't just use 1418 * a simple DEFINE_PROP_UINT32 for this because we want to permit 1419 * the property to be set after realize. 1420 */ 1421 object_property_add_uint32_ptr(obj, "init-svtor", 1422 &cpu->init_svtor, 1423 OBJ_PROP_FLAG_READWRITE); 1424 } 1425 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1426 /* 1427 * Initial value of the NS VTOR (for cores without the Security 1428 * extension, this is the only VTOR) 1429 */ 1430 object_property_add_uint32_ptr(obj, "init-nsvtor", 1431 &cpu->init_nsvtor, 1432 OBJ_PROP_FLAG_READWRITE); 1433 } 1434 1435 /* Not DEFINE_PROP_UINT32: we want this to be settable after realize */ 1436 object_property_add_uint32_ptr(obj, "psci-conduit", 1437 &cpu->psci_conduit, 1438 OBJ_PROP_FLAG_READWRITE); 1439 1440 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); 1441 1442 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { 1443 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); 1444 } 1445 1446 if (kvm_enabled()) { 1447 kvm_arm_add_vcpu_properties(obj); 1448 } 1449 1450 #ifndef CONFIG_USER_ONLY 1451 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && 1452 cpu_isar_feature(aa64_mte, cpu)) { 1453 object_property_add_link(obj, "tag-memory", 1454 TYPE_MEMORY_REGION, 1455 (Object **)&cpu->tag_memory, 1456 qdev_prop_allow_set_link_before_realize, 1457 OBJ_PROP_LINK_STRONG); 1458 1459 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1460 object_property_add_link(obj, "secure-tag-memory", 1461 TYPE_MEMORY_REGION, 1462 (Object **)&cpu->secure_tag_memory, 1463 qdev_prop_allow_set_link_before_realize, 1464 OBJ_PROP_LINK_STRONG); 1465 } 1466 } 1467 #endif 1468 } 1469 1470 static void arm_cpu_finalizefn(Object *obj) 1471 { 1472 ARMCPU *cpu = ARM_CPU(obj); 1473 ARMELChangeHook *hook, *next; 1474 1475 g_hash_table_destroy(cpu->cp_regs); 1476 1477 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 1478 QLIST_REMOVE(hook, node); 1479 g_free(hook); 1480 } 1481 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 1482 QLIST_REMOVE(hook, node); 1483 g_free(hook); 1484 } 1485 #ifndef CONFIG_USER_ONLY 1486 if (cpu->pmu_timer) { 1487 timer_free(cpu->pmu_timer); 1488 } 1489 #endif 1490 } 1491 1492 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) 1493 { 1494 Error *local_err = NULL; 1495 1496 #ifdef TARGET_AARCH64 1497 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1498 arm_cpu_sve_finalize(cpu, &local_err); 1499 if (local_err != NULL) { 1500 error_propagate(errp, local_err); 1501 return; 1502 } 1503 1504 arm_cpu_sme_finalize(cpu, &local_err); 1505 if (local_err != NULL) { 1506 error_propagate(errp, local_err); 1507 return; 1508 } 1509 1510 arm_cpu_pauth_finalize(cpu, &local_err); 1511 if (local_err != NULL) { 1512 error_propagate(errp, local_err); 1513 return; 1514 } 1515 1516 arm_cpu_lpa2_finalize(cpu, &local_err); 1517 if (local_err != NULL) { 1518 error_propagate(errp, local_err); 1519 return; 1520 } 1521 } 1522 #endif 1523 1524 if (kvm_enabled()) { 1525 kvm_arm_steal_time_finalize(cpu, &local_err); 1526 if (local_err != NULL) { 1527 error_propagate(errp, local_err); 1528 return; 1529 } 1530 } 1531 } 1532 1533 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 1534 { 1535 CPUState *cs = CPU(dev); 1536 ARMCPU *cpu = ARM_CPU(dev); 1537 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 1538 CPUARMState *env = &cpu->env; 1539 int pagebits; 1540 Error *local_err = NULL; 1541 bool no_aa32 = false; 1542 1543 /* If we needed to query the host kernel for the CPU features 1544 * then it's possible that might have failed in the initfn, but 1545 * this is the first point where we can report it. 1546 */ 1547 if (cpu->host_cpu_probe_failed) { 1548 if (!kvm_enabled() && !hvf_enabled()) { 1549 error_setg(errp, "The 'host' CPU type can only be used with KVM or HVF"); 1550 } else { 1551 error_setg(errp, "Failed to retrieve host CPU features"); 1552 } 1553 return; 1554 } 1555 1556 #ifndef CONFIG_USER_ONLY 1557 /* The NVIC and M-profile CPU are two halves of a single piece of 1558 * hardware; trying to use one without the other is a command line 1559 * error and will result in segfaults if not caught here. 1560 */ 1561 if (arm_feature(env, ARM_FEATURE_M)) { 1562 if (!env->nvic) { 1563 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 1564 return; 1565 } 1566 } else { 1567 if (env->nvic) { 1568 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 1569 return; 1570 } 1571 } 1572 1573 if (!tcg_enabled() && !qtest_enabled()) { 1574 /* 1575 * We assume that no accelerator except TCG (and the "not really an 1576 * accelerator" qtest) can handle these features, because Arm hardware 1577 * virtualization can't virtualize them. 1578 * 1579 * Catch all the cases which might cause us to create more than one 1580 * address space for the CPU (otherwise we will assert() later in 1581 * cpu_address_space_init()). 1582 */ 1583 if (arm_feature(env, ARM_FEATURE_M)) { 1584 error_setg(errp, 1585 "Cannot enable %s when using an M-profile guest CPU", 1586 current_accel_name()); 1587 return; 1588 } 1589 if (cpu->has_el3) { 1590 error_setg(errp, 1591 "Cannot enable %s when guest CPU has EL3 enabled", 1592 current_accel_name()); 1593 return; 1594 } 1595 if (cpu->tag_memory) { 1596 error_setg(errp, 1597 "Cannot enable %s when guest CPUs has MTE enabled", 1598 current_accel_name()); 1599 return; 1600 } 1601 } 1602 1603 { 1604 uint64_t scale; 1605 1606 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { 1607 if (!cpu->gt_cntfrq_hz) { 1608 error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", 1609 cpu->gt_cntfrq_hz); 1610 return; 1611 } 1612 scale = gt_cntfrq_period_ns(cpu); 1613 } else { 1614 scale = GTIMER_SCALE; 1615 } 1616 1617 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1618 arm_gt_ptimer_cb, cpu); 1619 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1620 arm_gt_vtimer_cb, cpu); 1621 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1622 arm_gt_htimer_cb, cpu); 1623 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1624 arm_gt_stimer_cb, cpu); 1625 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1626 arm_gt_hvtimer_cb, cpu); 1627 } 1628 #endif 1629 1630 cpu_exec_realizefn(cs, &local_err); 1631 if (local_err != NULL) { 1632 error_propagate(errp, local_err); 1633 return; 1634 } 1635 1636 arm_cpu_finalize_features(cpu, &local_err); 1637 if (local_err != NULL) { 1638 error_propagate(errp, local_err); 1639 return; 1640 } 1641 1642 if (arm_feature(env, ARM_FEATURE_AARCH64) && 1643 cpu->has_vfp != cpu->has_neon) { 1644 /* 1645 * This is an architectural requirement for AArch64; AArch32 is 1646 * more flexible and permits VFP-no-Neon and Neon-no-VFP. 1647 */ 1648 error_setg(errp, 1649 "AArch64 CPUs must have both VFP and Neon or neither"); 1650 return; 1651 } 1652 1653 if (!cpu->has_vfp) { 1654 uint64_t t; 1655 uint32_t u; 1656 1657 t = cpu->isar.id_aa64isar1; 1658 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); 1659 cpu->isar.id_aa64isar1 = t; 1660 1661 t = cpu->isar.id_aa64pfr0; 1662 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); 1663 cpu->isar.id_aa64pfr0 = t; 1664 1665 u = cpu->isar.id_isar6; 1666 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); 1667 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 1668 cpu->isar.id_isar6 = u; 1669 1670 u = cpu->isar.mvfr0; 1671 u = FIELD_DP32(u, MVFR0, FPSP, 0); 1672 u = FIELD_DP32(u, MVFR0, FPDP, 0); 1673 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); 1674 u = FIELD_DP32(u, MVFR0, FPSQRT, 0); 1675 u = FIELD_DP32(u, MVFR0, FPROUND, 0); 1676 if (!arm_feature(env, ARM_FEATURE_M)) { 1677 u = FIELD_DP32(u, MVFR0, FPTRAP, 0); 1678 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); 1679 } 1680 cpu->isar.mvfr0 = u; 1681 1682 u = cpu->isar.mvfr1; 1683 u = FIELD_DP32(u, MVFR1, FPFTZ, 0); 1684 u = FIELD_DP32(u, MVFR1, FPDNAN, 0); 1685 u = FIELD_DP32(u, MVFR1, FPHP, 0); 1686 if (arm_feature(env, ARM_FEATURE_M)) { 1687 u = FIELD_DP32(u, MVFR1, FP16, 0); 1688 } 1689 cpu->isar.mvfr1 = u; 1690 1691 u = cpu->isar.mvfr2; 1692 u = FIELD_DP32(u, MVFR2, FPMISC, 0); 1693 cpu->isar.mvfr2 = u; 1694 } 1695 1696 if (!cpu->has_neon) { 1697 uint64_t t; 1698 uint32_t u; 1699 1700 unset_feature(env, ARM_FEATURE_NEON); 1701 1702 t = cpu->isar.id_aa64isar0; 1703 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 0); 1704 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0); 1705 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0); 1706 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 0); 1707 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 0); 1708 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 0); 1709 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); 1710 cpu->isar.id_aa64isar0 = t; 1711 1712 t = cpu->isar.id_aa64isar1; 1713 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); 1714 t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 0); 1715 t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0); 1716 cpu->isar.id_aa64isar1 = t; 1717 1718 t = cpu->isar.id_aa64pfr0; 1719 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); 1720 cpu->isar.id_aa64pfr0 = t; 1721 1722 u = cpu->isar.id_isar5; 1723 u = FIELD_DP32(u, ID_ISAR5, AES, 0); 1724 u = FIELD_DP32(u, ID_ISAR5, SHA1, 0); 1725 u = FIELD_DP32(u, ID_ISAR5, SHA2, 0); 1726 u = FIELD_DP32(u, ID_ISAR5, RDM, 0); 1727 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); 1728 cpu->isar.id_isar5 = u; 1729 1730 u = cpu->isar.id_isar6; 1731 u = FIELD_DP32(u, ID_ISAR6, DP, 0); 1732 u = FIELD_DP32(u, ID_ISAR6, FHM, 0); 1733 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 1734 u = FIELD_DP32(u, ID_ISAR6, I8MM, 0); 1735 cpu->isar.id_isar6 = u; 1736 1737 if (!arm_feature(env, ARM_FEATURE_M)) { 1738 u = cpu->isar.mvfr1; 1739 u = FIELD_DP32(u, MVFR1, SIMDLS, 0); 1740 u = FIELD_DP32(u, MVFR1, SIMDINT, 0); 1741 u = FIELD_DP32(u, MVFR1, SIMDSP, 0); 1742 u = FIELD_DP32(u, MVFR1, SIMDHP, 0); 1743 cpu->isar.mvfr1 = u; 1744 1745 u = cpu->isar.mvfr2; 1746 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0); 1747 cpu->isar.mvfr2 = u; 1748 } 1749 } 1750 1751 if (!cpu->has_neon && !cpu->has_vfp) { 1752 uint64_t t; 1753 uint32_t u; 1754 1755 t = cpu->isar.id_aa64isar0; 1756 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); 1757 cpu->isar.id_aa64isar0 = t; 1758 1759 t = cpu->isar.id_aa64isar1; 1760 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); 1761 cpu->isar.id_aa64isar1 = t; 1762 1763 u = cpu->isar.mvfr0; 1764 u = FIELD_DP32(u, MVFR0, SIMDREG, 0); 1765 cpu->isar.mvfr0 = u; 1766 1767 /* Despite the name, this field covers both VFP and Neon */ 1768 u = cpu->isar.mvfr1; 1769 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); 1770 cpu->isar.mvfr1 = u; 1771 } 1772 1773 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { 1774 uint32_t u; 1775 1776 unset_feature(env, ARM_FEATURE_THUMB_DSP); 1777 1778 u = cpu->isar.id_isar1; 1779 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1); 1780 cpu->isar.id_isar1 = u; 1781 1782 u = cpu->isar.id_isar2; 1783 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); 1784 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); 1785 cpu->isar.id_isar2 = u; 1786 1787 u = cpu->isar.id_isar3; 1788 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); 1789 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); 1790 cpu->isar.id_isar3 = u; 1791 } 1792 1793 /* Some features automatically imply others: */ 1794 if (arm_feature(env, ARM_FEATURE_V8)) { 1795 if (arm_feature(env, ARM_FEATURE_M)) { 1796 set_feature(env, ARM_FEATURE_V7); 1797 } else { 1798 set_feature(env, ARM_FEATURE_V7VE); 1799 } 1800 } 1801 1802 /* 1803 * There exist AArch64 cpus without AArch32 support. When KVM 1804 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 1805 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 1806 * As a general principle, we also do not make ID register 1807 * consistency checks anywhere unless using TCG, because only 1808 * for TCG would a consistency-check failure be a QEMU bug. 1809 */ 1810 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1811 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 1812 } 1813 1814 if (arm_feature(env, ARM_FEATURE_V7VE)) { 1815 /* v7 Virtualization Extensions. In real hardware this implies 1816 * EL2 and also the presence of the Security Extensions. 1817 * For QEMU, for backwards-compatibility we implement some 1818 * CPUs or CPU configs which have no actual EL2 or EL3 but do 1819 * include the various other features that V7VE implies. 1820 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 1821 * Security Extensions is ARM_FEATURE_EL3. 1822 */ 1823 assert(!tcg_enabled() || no_aa32 || 1824 cpu_isar_feature(aa32_arm_div, cpu)); 1825 set_feature(env, ARM_FEATURE_LPAE); 1826 set_feature(env, ARM_FEATURE_V7); 1827 } 1828 if (arm_feature(env, ARM_FEATURE_V7)) { 1829 set_feature(env, ARM_FEATURE_VAPA); 1830 set_feature(env, ARM_FEATURE_THUMB2); 1831 set_feature(env, ARM_FEATURE_MPIDR); 1832 if (!arm_feature(env, ARM_FEATURE_M)) { 1833 set_feature(env, ARM_FEATURE_V6K); 1834 } else { 1835 set_feature(env, ARM_FEATURE_V6); 1836 } 1837 1838 /* Always define VBAR for V7 CPUs even if it doesn't exist in 1839 * non-EL3 configs. This is needed by some legacy boards. 1840 */ 1841 set_feature(env, ARM_FEATURE_VBAR); 1842 } 1843 if (arm_feature(env, ARM_FEATURE_V6K)) { 1844 set_feature(env, ARM_FEATURE_V6); 1845 set_feature(env, ARM_FEATURE_MVFR); 1846 } 1847 if (arm_feature(env, ARM_FEATURE_V6)) { 1848 set_feature(env, ARM_FEATURE_V5); 1849 if (!arm_feature(env, ARM_FEATURE_M)) { 1850 assert(!tcg_enabled() || no_aa32 || 1851 cpu_isar_feature(aa32_jazelle, cpu)); 1852 set_feature(env, ARM_FEATURE_AUXCR); 1853 } 1854 } 1855 if (arm_feature(env, ARM_FEATURE_V5)) { 1856 set_feature(env, ARM_FEATURE_V4T); 1857 } 1858 if (arm_feature(env, ARM_FEATURE_LPAE)) { 1859 set_feature(env, ARM_FEATURE_V7MP); 1860 } 1861 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 1862 set_feature(env, ARM_FEATURE_CBAR); 1863 } 1864 if (arm_feature(env, ARM_FEATURE_THUMB2) && 1865 !arm_feature(env, ARM_FEATURE_M)) { 1866 set_feature(env, ARM_FEATURE_THUMB_DSP); 1867 } 1868 1869 /* 1870 * We rely on no XScale CPU having VFP so we can use the same bits in the 1871 * TB flags field for VECSTRIDE and XSCALE_CPAR. 1872 */ 1873 assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) || 1874 !cpu_isar_feature(aa32_vfp_simd, cpu) || 1875 !arm_feature(env, ARM_FEATURE_XSCALE)); 1876 1877 if (arm_feature(env, ARM_FEATURE_V7) && 1878 !arm_feature(env, ARM_FEATURE_M) && 1879 !arm_feature(env, ARM_FEATURE_PMSA)) { 1880 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 1881 * can use 4K pages. 1882 */ 1883 pagebits = 12; 1884 } else { 1885 /* For CPUs which might have tiny 1K pages, or which have an 1886 * MPU and might have small region sizes, stick with 1K pages. 1887 */ 1888 pagebits = 10; 1889 } 1890 if (!set_preferred_target_page_bits(pagebits)) { 1891 /* This can only ever happen for hotplugging a CPU, or if 1892 * the board code incorrectly creates a CPU which it has 1893 * promised via minimum_page_size that it will not. 1894 */ 1895 error_setg(errp, "This CPU requires a smaller page size than the " 1896 "system is using"); 1897 return; 1898 } 1899 1900 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 1901 * We don't support setting cluster ID ([16..23]) (known as Aff2 1902 * in later ARM ARM versions), or any of the higher affinity level fields, 1903 * so these bits always RAZ. 1904 */ 1905 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 1906 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 1907 ARM_DEFAULT_CPUS_PER_CLUSTER); 1908 } 1909 1910 if (cpu->reset_hivecs) { 1911 cpu->reset_sctlr |= (1 << 13); 1912 } 1913 1914 if (cpu->cfgend) { 1915 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1916 cpu->reset_sctlr |= SCTLR_EE; 1917 } else { 1918 cpu->reset_sctlr |= SCTLR_B; 1919 } 1920 } 1921 1922 if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) { 1923 /* If the has_el3 CPU property is disabled then we need to disable the 1924 * feature. 1925 */ 1926 unset_feature(env, ARM_FEATURE_EL3); 1927 1928 /* 1929 * Disable the security extension feature bits in the processor 1930 * feature registers as well. 1931 */ 1932 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0); 1933 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0); 1934 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 1935 ID_AA64PFR0, EL3, 0); 1936 } 1937 1938 if (!cpu->has_el2) { 1939 unset_feature(env, ARM_FEATURE_EL2); 1940 } 1941 1942 if (!cpu->has_pmu) { 1943 unset_feature(env, ARM_FEATURE_PMU); 1944 } 1945 if (arm_feature(env, ARM_FEATURE_PMU)) { 1946 pmu_init(cpu); 1947 1948 if (!kvm_enabled()) { 1949 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); 1950 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); 1951 } 1952 1953 #ifndef CONFIG_USER_ONLY 1954 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, 1955 cpu); 1956 #endif 1957 } else { 1958 cpu->isar.id_aa64dfr0 = 1959 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); 1960 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0); 1961 cpu->pmceid0 = 0; 1962 cpu->pmceid1 = 0; 1963 } 1964 1965 if (!arm_feature(env, ARM_FEATURE_EL2)) { 1966 /* 1967 * Disable the hypervisor feature bits in the processor feature 1968 * registers if we don't have EL2. 1969 */ 1970 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 1971 ID_AA64PFR0, EL2, 0); 1972 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, 1973 ID_PFR1, VIRTUALIZATION, 0); 1974 } 1975 1976 #ifndef CONFIG_USER_ONLY 1977 if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) { 1978 /* 1979 * Disable the MTE feature bits if we do not have tag-memory 1980 * provided by the machine. 1981 */ 1982 cpu->isar.id_aa64pfr1 = 1983 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); 1984 } 1985 #endif 1986 1987 if (tcg_enabled()) { 1988 /* 1989 * Don't report the Statistical Profiling Extension in the ID 1990 * registers, because TCG doesn't implement it yet (not even a 1991 * minimal stub version) and guests will fall over when they 1992 * try to access the non-existent system registers for it. 1993 */ 1994 cpu->isar.id_aa64dfr0 = 1995 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0); 1996 } 1997 1998 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 1999 * to false or by setting pmsav7-dregion to 0. 2000 */ 2001 if (!cpu->has_mpu) { 2002 cpu->pmsav7_dregion = 0; 2003 } 2004 if (cpu->pmsav7_dregion == 0) { 2005 cpu->has_mpu = false; 2006 } 2007 2008 if (arm_feature(env, ARM_FEATURE_PMSA) && 2009 arm_feature(env, ARM_FEATURE_V7)) { 2010 uint32_t nr = cpu->pmsav7_dregion; 2011 2012 if (nr > 0xff) { 2013 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 2014 return; 2015 } 2016 2017 if (nr) { 2018 if (arm_feature(env, ARM_FEATURE_V8)) { 2019 /* PMSAv8 */ 2020 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 2021 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 2022 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 2023 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 2024 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 2025 } 2026 } else { 2027 env->pmsav7.drbar = g_new0(uint32_t, nr); 2028 env->pmsav7.drsr = g_new0(uint32_t, nr); 2029 env->pmsav7.dracr = g_new0(uint32_t, nr); 2030 } 2031 } 2032 } 2033 2034 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 2035 uint32_t nr = cpu->sau_sregion; 2036 2037 if (nr > 0xff) { 2038 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 2039 return; 2040 } 2041 2042 if (nr) { 2043 env->sau.rbar = g_new0(uint32_t, nr); 2044 env->sau.rlar = g_new0(uint32_t, nr); 2045 } 2046 } 2047 2048 if (arm_feature(env, ARM_FEATURE_EL3)) { 2049 set_feature(env, ARM_FEATURE_VBAR); 2050 } 2051 2052 register_cp_regs_for_features(cpu); 2053 arm_cpu_register_gdb_regs_for_features(cpu); 2054 2055 init_cpreg_list(cpu); 2056 2057 #ifndef CONFIG_USER_ONLY 2058 MachineState *ms = MACHINE(qdev_get_machine()); 2059 unsigned int smp_cpus = ms->smp.cpus; 2060 bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY); 2061 2062 /* 2063 * We must set cs->num_ases to the final value before 2064 * the first call to cpu_address_space_init. 2065 */ 2066 if (cpu->tag_memory != NULL) { 2067 cs->num_ases = 3 + has_secure; 2068 } else { 2069 cs->num_ases = 1 + has_secure; 2070 } 2071 2072 if (has_secure) { 2073 if (!cpu->secure_memory) { 2074 cpu->secure_memory = cs->memory; 2075 } 2076 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 2077 cpu->secure_memory); 2078 } 2079 2080 if (cpu->tag_memory != NULL) { 2081 cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory", 2082 cpu->tag_memory); 2083 if (has_secure) { 2084 cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory", 2085 cpu->secure_tag_memory); 2086 } 2087 } 2088 2089 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 2090 2091 /* No core_count specified, default to smp_cpus. */ 2092 if (cpu->core_count == -1) { 2093 cpu->core_count = smp_cpus; 2094 } 2095 #endif 2096 2097 if (tcg_enabled()) { 2098 int dcz_blocklen = 4 << cpu->dcz_blocksize; 2099 2100 /* 2101 * We only support DCZ blocklen that fits on one page. 2102 * 2103 * Architectually this is always true. However TARGET_PAGE_SIZE 2104 * is variable and, for compatibility with -machine virt-2.7, 2105 * is only 1KiB, as an artifact of legacy ARMv5 subpage support. 2106 * But even then, while the largest architectural DCZ blocklen 2107 * is 2KiB, no cpu actually uses such a large blocklen. 2108 */ 2109 assert(dcz_blocklen <= TARGET_PAGE_SIZE); 2110 2111 /* 2112 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say 2113 * both nibbles of each byte storing tag data may be written at once. 2114 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32. 2115 */ 2116 if (cpu_isar_feature(aa64_mte, cpu)) { 2117 assert(dcz_blocklen >= 2 * TAG_GRANULE); 2118 } 2119 } 2120 2121 qemu_init_vcpu(cs); 2122 cpu_reset(cs); 2123 2124 acc->parent_realize(dev, errp); 2125 } 2126 2127 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 2128 { 2129 ObjectClass *oc; 2130 char *typename; 2131 char **cpuname; 2132 const char *cpunamestr; 2133 2134 cpuname = g_strsplit(cpu_model, ",", 1); 2135 cpunamestr = cpuname[0]; 2136 #ifdef CONFIG_USER_ONLY 2137 /* For backwards compatibility usermode emulation allows "-cpu any", 2138 * which has the same semantics as "-cpu max". 2139 */ 2140 if (!strcmp(cpunamestr, "any")) { 2141 cpunamestr = "max"; 2142 } 2143 #endif 2144 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 2145 oc = object_class_by_name(typename); 2146 g_strfreev(cpuname); 2147 g_free(typename); 2148 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 2149 object_class_is_abstract(oc)) { 2150 return NULL; 2151 } 2152 return oc; 2153 } 2154 2155 static Property arm_cpu_properties[] = { 2156 DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), 2157 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 2158 mp_affinity, ARM64_AFFINITY_INVALID), 2159 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 2160 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 2161 DEFINE_PROP_END_OF_LIST() 2162 }; 2163 2164 static gchar *arm_gdb_arch_name(CPUState *cs) 2165 { 2166 ARMCPU *cpu = ARM_CPU(cs); 2167 CPUARMState *env = &cpu->env; 2168 2169 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 2170 return g_strdup("iwmmxt"); 2171 } 2172 return g_strdup("arm"); 2173 } 2174 2175 #ifndef CONFIG_USER_ONLY 2176 #include "hw/core/sysemu-cpu-ops.h" 2177 2178 static const struct SysemuCPUOps arm_sysemu_ops = { 2179 .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug, 2180 .asidx_from_attrs = arm_asidx_from_attrs, 2181 .write_elf32_note = arm_cpu_write_elf32_note, 2182 .write_elf64_note = arm_cpu_write_elf64_note, 2183 .virtio_is_big_endian = arm_cpu_virtio_is_big_endian, 2184 .legacy_vmsd = &vmstate_arm_cpu, 2185 }; 2186 #endif 2187 2188 #ifdef CONFIG_TCG 2189 static const struct TCGCPUOps arm_tcg_ops = { 2190 .initialize = arm_translate_init, 2191 .synchronize_from_tb = arm_cpu_synchronize_from_tb, 2192 .debug_excp_handler = arm_debug_excp_handler, 2193 .restore_state_to_opc = arm_restore_state_to_opc, 2194 2195 #ifdef CONFIG_USER_ONLY 2196 .record_sigsegv = arm_cpu_record_sigsegv, 2197 .record_sigbus = arm_cpu_record_sigbus, 2198 #else 2199 .tlb_fill = arm_cpu_tlb_fill, 2200 .cpu_exec_interrupt = arm_cpu_exec_interrupt, 2201 .do_interrupt = arm_cpu_do_interrupt, 2202 .do_transaction_failed = arm_cpu_do_transaction_failed, 2203 .do_unaligned_access = arm_cpu_do_unaligned_access, 2204 .adjust_watchpoint_address = arm_adjust_watchpoint_address, 2205 .debug_check_watchpoint = arm_debug_check_watchpoint, 2206 .debug_check_breakpoint = arm_debug_check_breakpoint, 2207 #endif /* !CONFIG_USER_ONLY */ 2208 }; 2209 #endif /* CONFIG_TCG */ 2210 2211 static void arm_cpu_class_init(ObjectClass *oc, void *data) 2212 { 2213 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2214 CPUClass *cc = CPU_CLASS(acc); 2215 DeviceClass *dc = DEVICE_CLASS(oc); 2216 ResettableClass *rc = RESETTABLE_CLASS(oc); 2217 2218 device_class_set_parent_realize(dc, arm_cpu_realizefn, 2219 &acc->parent_realize); 2220 2221 device_class_set_props(dc, arm_cpu_properties); 2222 2223 resettable_class_set_parent_phases(rc, NULL, arm_cpu_reset_hold, NULL, 2224 &acc->parent_phases); 2225 2226 cc->class_by_name = arm_cpu_class_by_name; 2227 cc->has_work = arm_cpu_has_work; 2228 cc->dump_state = arm_cpu_dump_state; 2229 cc->set_pc = arm_cpu_set_pc; 2230 cc->get_pc = arm_cpu_get_pc; 2231 cc->gdb_read_register = arm_cpu_gdb_read_register; 2232 cc->gdb_write_register = arm_cpu_gdb_write_register; 2233 #ifndef CONFIG_USER_ONLY 2234 cc->sysemu_ops = &arm_sysemu_ops; 2235 #endif 2236 cc->gdb_num_core_regs = 26; 2237 cc->gdb_core_xml_file = "arm-core.xml"; 2238 cc->gdb_arch_name = arm_gdb_arch_name; 2239 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; 2240 cc->gdb_stop_before_watchpoint = true; 2241 cc->disas_set_info = arm_disas_set_info; 2242 2243 #ifdef CONFIG_TCG 2244 cc->tcg_ops = &arm_tcg_ops; 2245 #endif /* CONFIG_TCG */ 2246 } 2247 2248 static void arm_cpu_instance_init(Object *obj) 2249 { 2250 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 2251 2252 acc->info->initfn(obj); 2253 arm_cpu_post_init(obj); 2254 } 2255 2256 static void cpu_register_class_init(ObjectClass *oc, void *data) 2257 { 2258 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2259 2260 acc->info = data; 2261 } 2262 2263 void arm_cpu_register(const ARMCPUInfo *info) 2264 { 2265 TypeInfo type_info = { 2266 .parent = TYPE_ARM_CPU, 2267 .instance_size = sizeof(ARMCPU), 2268 .instance_align = __alignof__(ARMCPU), 2269 .instance_init = arm_cpu_instance_init, 2270 .class_size = sizeof(ARMCPUClass), 2271 .class_init = info->class_init ?: cpu_register_class_init, 2272 .class_data = (void *)info, 2273 }; 2274 2275 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2276 type_register(&type_info); 2277 g_free((void *)type_info.name); 2278 } 2279 2280 static const TypeInfo arm_cpu_type_info = { 2281 .name = TYPE_ARM_CPU, 2282 .parent = TYPE_CPU, 2283 .instance_size = sizeof(ARMCPU), 2284 .instance_align = __alignof__(ARMCPU), 2285 .instance_init = arm_cpu_initfn, 2286 .instance_finalize = arm_cpu_finalizefn, 2287 .abstract = true, 2288 .class_size = sizeof(ARMCPUClass), 2289 .class_init = arm_cpu_class_init, 2290 }; 2291 2292 static void arm_cpu_register_types(void) 2293 { 2294 type_register_static(&arm_cpu_type_info); 2295 } 2296 2297 type_init(arm_cpu_register_types) 2298