1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/qemu-print.h" 23 #include "qemu/timer.h" 24 #include "qemu/log.h" 25 #include "exec/page-vary.h" 26 #include "target/arm/idau.h" 27 #include "qemu/module.h" 28 #include "qapi/error.h" 29 #include "qapi/visitor.h" 30 #include "cpu.h" 31 #ifdef CONFIG_TCG 32 #include "hw/core/tcg-cpu-ops.h" 33 #endif /* CONFIG_TCG */ 34 #include "internals.h" 35 #include "exec/exec-all.h" 36 #include "hw/qdev-properties.h" 37 #if !defined(CONFIG_USER_ONLY) 38 #include "hw/loader.h" 39 #include "hw/boards.h" 40 #endif 41 #include "sysemu/tcg.h" 42 #include "sysemu/qtest.h" 43 #include "sysemu/hw_accel.h" 44 #include "kvm_arm.h" 45 #include "disas/capstone.h" 46 #include "fpu/softfloat.h" 47 #include "cpregs.h" 48 49 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 50 { 51 ARMCPU *cpu = ARM_CPU(cs); 52 CPUARMState *env = &cpu->env; 53 54 if (is_a64(env)) { 55 env->pc = value; 56 env->thumb = false; 57 } else { 58 env->regs[15] = value & ~1; 59 env->thumb = value & 1; 60 } 61 } 62 63 static vaddr arm_cpu_get_pc(CPUState *cs) 64 { 65 ARMCPU *cpu = ARM_CPU(cs); 66 CPUARMState *env = &cpu->env; 67 68 if (is_a64(env)) { 69 return env->pc; 70 } else { 71 return env->regs[15]; 72 } 73 } 74 75 #ifdef CONFIG_TCG 76 void arm_cpu_synchronize_from_tb(CPUState *cs, 77 const TranslationBlock *tb) 78 { 79 /* The program counter is always up to date with TARGET_TB_PCREL. */ 80 if (!TARGET_TB_PCREL) { 81 CPUARMState *env = cs->env_ptr; 82 /* 83 * It's OK to look at env for the current mode here, because it's 84 * never possible for an AArch64 TB to chain to an AArch32 TB. 85 */ 86 if (is_a64(env)) { 87 env->pc = tb_pc(tb); 88 } else { 89 env->regs[15] = tb_pc(tb); 90 } 91 } 92 } 93 94 void arm_restore_state_to_opc(CPUState *cs, 95 const TranslationBlock *tb, 96 const uint64_t *data) 97 { 98 CPUARMState *env = cs->env_ptr; 99 100 if (is_a64(env)) { 101 if (TARGET_TB_PCREL) { 102 env->pc = (env->pc & TARGET_PAGE_MASK) | data[0]; 103 } else { 104 env->pc = data[0]; 105 } 106 env->condexec_bits = 0; 107 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT; 108 } else { 109 if (TARGET_TB_PCREL) { 110 env->regs[15] = (env->regs[15] & TARGET_PAGE_MASK) | data[0]; 111 } else { 112 env->regs[15] = data[0]; 113 } 114 env->condexec_bits = data[1]; 115 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT; 116 } 117 } 118 #endif /* CONFIG_TCG */ 119 120 static bool arm_cpu_has_work(CPUState *cs) 121 { 122 ARMCPU *cpu = ARM_CPU(cs); 123 124 return (cpu->power_state != PSCI_OFF) 125 && cs->interrupt_request & 126 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 127 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR 128 | CPU_INTERRUPT_EXITTB); 129 } 130 131 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 132 void *opaque) 133 { 134 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 135 136 entry->hook = hook; 137 entry->opaque = opaque; 138 139 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 140 } 141 142 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 143 void *opaque) 144 { 145 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 146 147 entry->hook = hook; 148 entry->opaque = opaque; 149 150 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 151 } 152 153 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 154 { 155 /* Reset a single ARMCPRegInfo register */ 156 ARMCPRegInfo *ri = value; 157 ARMCPU *cpu = opaque; 158 159 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS)) { 160 return; 161 } 162 163 if (ri->resetfn) { 164 ri->resetfn(&cpu->env, ri); 165 return; 166 } 167 168 /* A zero offset is never possible as it would be regs[0] 169 * so we use it to indicate that reset is being handled elsewhere. 170 * This is basically only used for fields in non-core coprocessors 171 * (like the pxa2xx ones). 172 */ 173 if (!ri->fieldoffset) { 174 return; 175 } 176 177 if (cpreg_field_is_64bit(ri)) { 178 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 179 } else { 180 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 181 } 182 } 183 184 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 185 { 186 /* Purely an assertion check: we've already done reset once, 187 * so now check that running the reset for the cpreg doesn't 188 * change its value. This traps bugs where two different cpregs 189 * both try to reset the same state field but to different values. 190 */ 191 ARMCPRegInfo *ri = value; 192 ARMCPU *cpu = opaque; 193 uint64_t oldvalue, newvalue; 194 195 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 196 return; 197 } 198 199 oldvalue = read_raw_cp_reg(&cpu->env, ri); 200 cp_reg_reset(key, value, opaque); 201 newvalue = read_raw_cp_reg(&cpu->env, ri); 202 assert(oldvalue == newvalue); 203 } 204 205 static void arm_cpu_reset(DeviceState *dev) 206 { 207 CPUState *s = CPU(dev); 208 ARMCPU *cpu = ARM_CPU(s); 209 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 210 CPUARMState *env = &cpu->env; 211 212 acc->parent_reset(dev); 213 214 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 215 216 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 217 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 218 219 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 220 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 221 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 222 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 223 224 cpu->power_state = s->start_powered_off ? PSCI_OFF : PSCI_ON; 225 226 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 227 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 228 } 229 230 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 231 /* 64 bit CPUs always start in 64 bit mode */ 232 env->aarch64 = true; 233 #if defined(CONFIG_USER_ONLY) 234 env->pstate = PSTATE_MODE_EL0t; 235 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 236 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 237 /* Enable all PAC keys. */ 238 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | 239 SCTLR_EnDA | SCTLR_EnDB); 240 /* Trap on btype=3 for PACIxSP. */ 241 env->cp15.sctlr_el[1] |= SCTLR_BT0; 242 /* and to the FP/Neon instructions */ 243 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 244 CPACR_EL1, FPEN, 3); 245 /* and to the SVE instructions, with default vector length */ 246 if (cpu_isar_feature(aa64_sve, cpu)) { 247 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 248 CPACR_EL1, ZEN, 3); 249 env->vfp.zcr_el[1] = cpu->sve_default_vq - 1; 250 } 251 /* and for SME instructions, with default vector length, and TPIDR2 */ 252 if (cpu_isar_feature(aa64_sme, cpu)) { 253 env->cp15.sctlr_el[1] |= SCTLR_EnTP2; 254 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 255 CPACR_EL1, SMEN, 3); 256 env->vfp.smcr_el[1] = cpu->sme_default_vq - 1; 257 if (cpu_isar_feature(aa64_sme_fa64, cpu)) { 258 env->vfp.smcr_el[1] = FIELD_DP64(env->vfp.smcr_el[1], 259 SMCR, FA64, 1); 260 } 261 } 262 /* 263 * Enable 48-bit address space (TODO: take reserved_va into account). 264 * Enable TBI0 but not TBI1. 265 * Note that this must match useronly_clean_ptr. 266 */ 267 env->cp15.tcr_el[1] = 5 | (1ULL << 37); 268 269 /* Enable MTE */ 270 if (cpu_isar_feature(aa64_mte, cpu)) { 271 /* Enable tag access, but leave TCF0 as No Effect (0). */ 272 env->cp15.sctlr_el[1] |= SCTLR_ATA0; 273 /* 274 * Exclude all tags, so that tag 0 is always used. 275 * This corresponds to Linux current->thread.gcr_incl = 0. 276 * 277 * Set RRND, so that helper_irg() will generate a seed later. 278 * Here in cpu_reset(), the crypto subsystem has not yet been 279 * initialized. 280 */ 281 env->cp15.gcr_el1 = 0x1ffff; 282 } 283 /* 284 * Disable access to SCXTNUM_EL0 from CSV2_1p2. 285 * This is not yet exposed from the Linux kernel in any way. 286 */ 287 env->cp15.sctlr_el[1] |= SCTLR_TSCXT; 288 #else 289 /* Reset into the highest available EL */ 290 if (arm_feature(env, ARM_FEATURE_EL3)) { 291 env->pstate = PSTATE_MODE_EL3h; 292 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 293 env->pstate = PSTATE_MODE_EL2h; 294 } else { 295 env->pstate = PSTATE_MODE_EL1h; 296 } 297 298 /* Sample rvbar at reset. */ 299 env->cp15.rvbar = cpu->rvbar_prop; 300 env->pc = env->cp15.rvbar; 301 #endif 302 } else { 303 #if defined(CONFIG_USER_ONLY) 304 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 305 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 306 CPACR, CP10, 3); 307 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 308 CPACR, CP11, 3); 309 #endif 310 } 311 312 #if defined(CONFIG_USER_ONLY) 313 env->uncached_cpsr = ARM_CPU_MODE_USR; 314 /* For user mode we must enable access to coprocessors */ 315 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 316 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 317 env->cp15.c15_cpar = 3; 318 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 319 env->cp15.c15_cpar = 1; 320 } 321 #else 322 323 /* 324 * If the highest available EL is EL2, AArch32 will start in Hyp 325 * mode; otherwise it starts in SVC. Note that if we start in 326 * AArch64 then these values in the uncached_cpsr will be ignored. 327 */ 328 if (arm_feature(env, ARM_FEATURE_EL2) && 329 !arm_feature(env, ARM_FEATURE_EL3)) { 330 env->uncached_cpsr = ARM_CPU_MODE_HYP; 331 } else { 332 env->uncached_cpsr = ARM_CPU_MODE_SVC; 333 } 334 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 335 336 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 337 * executing as AArch32 then check if highvecs are enabled and 338 * adjust the PC accordingly. 339 */ 340 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 341 env->regs[15] = 0xFFFF0000; 342 } 343 344 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 345 #endif 346 347 if (arm_feature(env, ARM_FEATURE_M)) { 348 #ifndef CONFIG_USER_ONLY 349 uint32_t initial_msp; /* Loaded from 0x0 */ 350 uint32_t initial_pc; /* Loaded from 0x4 */ 351 uint8_t *rom; 352 uint32_t vecbase; 353 #endif 354 355 if (cpu_isar_feature(aa32_lob, cpu)) { 356 /* 357 * LTPSIZE is constant 4 if MVE not implemented, and resets 358 * to an UNKNOWN value if MVE is implemented. We choose to 359 * always reset to 4. 360 */ 361 env->v7m.ltpsize = 4; 362 /* The LTPSIZE field in FPDSCR is constant and reads as 4. */ 363 env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT; 364 env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT; 365 } 366 367 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 368 env->v7m.secure = true; 369 } else { 370 /* This bit resets to 0 if security is supported, but 1 if 371 * it is not. The bit is not present in v7M, but we set it 372 * here so we can avoid having to make checks on it conditional 373 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 374 */ 375 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 376 /* 377 * Set NSACR to indicate "NS access permitted to everything"; 378 * this avoids having to have all the tests of it being 379 * conditional on ARM_FEATURE_M_SECURITY. Note also that from 380 * v8.1M the guest-visible value of NSACR in a CPU without the 381 * Security Extension is 0xcff. 382 */ 383 env->v7m.nsacr = 0xcff; 384 } 385 386 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 387 * that it resets to 1, so QEMU always does that rather than making 388 * it dependent on CPU model. In v8M it is RES1. 389 */ 390 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 391 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 392 if (arm_feature(env, ARM_FEATURE_V8)) { 393 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 394 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 395 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 396 } 397 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 398 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 399 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 400 } 401 402 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 403 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; 404 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | 405 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; 406 } 407 408 #ifndef CONFIG_USER_ONLY 409 /* Unlike A/R profile, M profile defines the reset LR value */ 410 env->regs[14] = 0xffffffff; 411 412 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 413 env->v7m.vecbase[M_REG_NS] = cpu->init_nsvtor & 0xffffff80; 414 415 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 416 vecbase = env->v7m.vecbase[env->v7m.secure]; 417 rom = rom_ptr_for_as(s->as, vecbase, 8); 418 if (rom) { 419 /* Address zero is covered by ROM which hasn't yet been 420 * copied into physical memory. 421 */ 422 initial_msp = ldl_p(rom); 423 initial_pc = ldl_p(rom + 4); 424 } else { 425 /* Address zero not covered by a ROM blob, or the ROM blob 426 * is in non-modifiable memory and this is a second reset after 427 * it got copied into memory. In the latter case, rom_ptr 428 * will return a NULL pointer and we should use ldl_phys instead. 429 */ 430 initial_msp = ldl_phys(s->as, vecbase); 431 initial_pc = ldl_phys(s->as, vecbase + 4); 432 } 433 434 qemu_log_mask(CPU_LOG_INT, 435 "Loaded reset SP 0x%x PC 0x%x from vector table\n", 436 initial_msp, initial_pc); 437 438 env->regs[13] = initial_msp & 0xFFFFFFFC; 439 env->regs[15] = initial_pc & ~1; 440 env->thumb = initial_pc & 1; 441 #else 442 /* 443 * For user mode we run non-secure and with access to the FPU. 444 * The FPU context is active (ie does not need further setup) 445 * and is owned by non-secure. 446 */ 447 env->v7m.secure = false; 448 env->v7m.nsacr = 0xcff; 449 env->v7m.cpacr[M_REG_NS] = 0xf0ffff; 450 env->v7m.fpccr[M_REG_S] &= 451 ~(R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK); 452 env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK; 453 #endif 454 } 455 456 /* M profile requires that reset clears the exclusive monitor; 457 * A profile does not, but clearing it makes more sense than having it 458 * set with an exclusive access on address zero. 459 */ 460 arm_clear_exclusive(env); 461 462 if (arm_feature(env, ARM_FEATURE_PMSA)) { 463 if (cpu->pmsav7_dregion > 0) { 464 if (arm_feature(env, ARM_FEATURE_V8)) { 465 memset(env->pmsav8.rbar[M_REG_NS], 0, 466 sizeof(*env->pmsav8.rbar[M_REG_NS]) 467 * cpu->pmsav7_dregion); 468 memset(env->pmsav8.rlar[M_REG_NS], 0, 469 sizeof(*env->pmsav8.rlar[M_REG_NS]) 470 * cpu->pmsav7_dregion); 471 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 472 memset(env->pmsav8.rbar[M_REG_S], 0, 473 sizeof(*env->pmsav8.rbar[M_REG_S]) 474 * cpu->pmsav7_dregion); 475 memset(env->pmsav8.rlar[M_REG_S], 0, 476 sizeof(*env->pmsav8.rlar[M_REG_S]) 477 * cpu->pmsav7_dregion); 478 } 479 } else if (arm_feature(env, ARM_FEATURE_V7)) { 480 memset(env->pmsav7.drbar, 0, 481 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 482 memset(env->pmsav7.drsr, 0, 483 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 484 memset(env->pmsav7.dracr, 0, 485 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 486 } 487 } 488 env->pmsav7.rnr[M_REG_NS] = 0; 489 env->pmsav7.rnr[M_REG_S] = 0; 490 env->pmsav8.mair0[M_REG_NS] = 0; 491 env->pmsav8.mair0[M_REG_S] = 0; 492 env->pmsav8.mair1[M_REG_NS] = 0; 493 env->pmsav8.mair1[M_REG_S] = 0; 494 } 495 496 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 497 if (cpu->sau_sregion > 0) { 498 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 499 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 500 } 501 env->sau.rnr = 0; 502 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 503 * the Cortex-M33 does. 504 */ 505 env->sau.ctrl = 0; 506 } 507 508 set_flush_to_zero(1, &env->vfp.standard_fp_status); 509 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 510 set_default_nan_mode(1, &env->vfp.standard_fp_status); 511 set_default_nan_mode(1, &env->vfp.standard_fp_status_f16); 512 set_float_detect_tininess(float_tininess_before_rounding, 513 &env->vfp.fp_status); 514 set_float_detect_tininess(float_tininess_before_rounding, 515 &env->vfp.standard_fp_status); 516 set_float_detect_tininess(float_tininess_before_rounding, 517 &env->vfp.fp_status_f16); 518 set_float_detect_tininess(float_tininess_before_rounding, 519 &env->vfp.standard_fp_status_f16); 520 #ifndef CONFIG_USER_ONLY 521 if (kvm_enabled()) { 522 kvm_arm_reset_vcpu(cpu); 523 } 524 #endif 525 526 hw_breakpoint_update_all(cpu); 527 hw_watchpoint_update_all(cpu); 528 arm_rebuild_hflags(env); 529 } 530 531 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 532 533 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 534 unsigned int target_el, 535 unsigned int cur_el, bool secure, 536 uint64_t hcr_el2) 537 { 538 CPUARMState *env = cs->env_ptr; 539 bool pstate_unmasked; 540 bool unmasked = false; 541 542 /* 543 * Don't take exceptions if they target a lower EL. 544 * This check should catch any exceptions that would not be taken 545 * but left pending. 546 */ 547 if (cur_el > target_el) { 548 return false; 549 } 550 551 switch (excp_idx) { 552 case EXCP_FIQ: 553 pstate_unmasked = !(env->daif & PSTATE_F); 554 break; 555 556 case EXCP_IRQ: 557 pstate_unmasked = !(env->daif & PSTATE_I); 558 break; 559 560 case EXCP_VFIQ: 561 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 562 /* VFIQs are only taken when hypervized. */ 563 return false; 564 } 565 return !(env->daif & PSTATE_F); 566 case EXCP_VIRQ: 567 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 568 /* VIRQs are only taken when hypervized. */ 569 return false; 570 } 571 return !(env->daif & PSTATE_I); 572 case EXCP_VSERR: 573 if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) { 574 /* VIRQs are only taken when hypervized. */ 575 return false; 576 } 577 return !(env->daif & PSTATE_A); 578 default: 579 g_assert_not_reached(); 580 } 581 582 /* 583 * Use the target EL, current execution state and SCR/HCR settings to 584 * determine whether the corresponding CPSR bit is used to mask the 585 * interrupt. 586 */ 587 if ((target_el > cur_el) && (target_el != 1)) { 588 /* Exceptions targeting a higher EL may not be maskable */ 589 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 590 switch (target_el) { 591 case 2: 592 /* 593 * According to ARM DDI 0487H.a, an interrupt can be masked 594 * when HCR_E2H and HCR_TGE are both set regardless of the 595 * current Security state. Note that we need to revisit this 596 * part again once we need to support NMI. 597 */ 598 if ((hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { 599 unmasked = true; 600 } 601 break; 602 case 3: 603 /* Interrupt cannot be masked when the target EL is 3 */ 604 unmasked = true; 605 break; 606 default: 607 g_assert_not_reached(); 608 } 609 } else { 610 /* 611 * The old 32-bit-only environment has a more complicated 612 * masking setup. HCR and SCR bits not only affect interrupt 613 * routing but also change the behaviour of masking. 614 */ 615 bool hcr, scr; 616 617 switch (excp_idx) { 618 case EXCP_FIQ: 619 /* 620 * If FIQs are routed to EL3 or EL2 then there are cases where 621 * we override the CPSR.F in determining if the exception is 622 * masked or not. If neither of these are set then we fall back 623 * to the CPSR.F setting otherwise we further assess the state 624 * below. 625 */ 626 hcr = hcr_el2 & HCR_FMO; 627 scr = (env->cp15.scr_el3 & SCR_FIQ); 628 629 /* 630 * When EL3 is 32-bit, the SCR.FW bit controls whether the 631 * CPSR.F bit masks FIQ interrupts when taken in non-secure 632 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 633 * when non-secure but only when FIQs are only routed to EL3. 634 */ 635 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 636 break; 637 case EXCP_IRQ: 638 /* 639 * When EL3 execution state is 32-bit, if HCR.IMO is set then 640 * we may override the CPSR.I masking when in non-secure state. 641 * The SCR.IRQ setting has already been taken into consideration 642 * when setting the target EL, so it does not have a further 643 * affect here. 644 */ 645 hcr = hcr_el2 & HCR_IMO; 646 scr = false; 647 break; 648 default: 649 g_assert_not_reached(); 650 } 651 652 if ((scr || hcr) && !secure) { 653 unmasked = true; 654 } 655 } 656 } 657 658 /* 659 * The PSTATE bits only mask the interrupt if we have not overriden the 660 * ability above. 661 */ 662 return unmasked || pstate_unmasked; 663 } 664 665 static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 666 { 667 CPUClass *cc = CPU_GET_CLASS(cs); 668 CPUARMState *env = cs->env_ptr; 669 uint32_t cur_el = arm_current_el(env); 670 bool secure = arm_is_secure(env); 671 uint64_t hcr_el2 = arm_hcr_el2_eff(env); 672 uint32_t target_el; 673 uint32_t excp_idx; 674 675 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ 676 677 if (interrupt_request & CPU_INTERRUPT_FIQ) { 678 excp_idx = EXCP_FIQ; 679 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 680 if (arm_excp_unmasked(cs, excp_idx, target_el, 681 cur_el, secure, hcr_el2)) { 682 goto found; 683 } 684 } 685 if (interrupt_request & CPU_INTERRUPT_HARD) { 686 excp_idx = EXCP_IRQ; 687 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 688 if (arm_excp_unmasked(cs, excp_idx, target_el, 689 cur_el, secure, hcr_el2)) { 690 goto found; 691 } 692 } 693 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 694 excp_idx = EXCP_VIRQ; 695 target_el = 1; 696 if (arm_excp_unmasked(cs, excp_idx, target_el, 697 cur_el, secure, hcr_el2)) { 698 goto found; 699 } 700 } 701 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 702 excp_idx = EXCP_VFIQ; 703 target_el = 1; 704 if (arm_excp_unmasked(cs, excp_idx, target_el, 705 cur_el, secure, hcr_el2)) { 706 goto found; 707 } 708 } 709 if (interrupt_request & CPU_INTERRUPT_VSERR) { 710 excp_idx = EXCP_VSERR; 711 target_el = 1; 712 if (arm_excp_unmasked(cs, excp_idx, target_el, 713 cur_el, secure, hcr_el2)) { 714 /* Taking a virtual abort clears HCR_EL2.VSE */ 715 env->cp15.hcr_el2 &= ~HCR_VSE; 716 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); 717 goto found; 718 } 719 } 720 return false; 721 722 found: 723 cs->exception_index = excp_idx; 724 env->exception.target_el = target_el; 725 cc->tcg_ops->do_interrupt(cs); 726 return true; 727 } 728 729 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ 730 731 void arm_cpu_update_virq(ARMCPU *cpu) 732 { 733 /* 734 * Update the interrupt level for VIRQ, which is the logical OR of 735 * the HCR_EL2.VI bit and the input line level from the GIC. 736 */ 737 CPUARMState *env = &cpu->env; 738 CPUState *cs = CPU(cpu); 739 740 bool new_state = (env->cp15.hcr_el2 & HCR_VI) || 741 (env->irq_line_state & CPU_INTERRUPT_VIRQ); 742 743 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { 744 if (new_state) { 745 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); 746 } else { 747 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); 748 } 749 } 750 } 751 752 void arm_cpu_update_vfiq(ARMCPU *cpu) 753 { 754 /* 755 * Update the interrupt level for VFIQ, which is the logical OR of 756 * the HCR_EL2.VF bit and the input line level from the GIC. 757 */ 758 CPUARMState *env = &cpu->env; 759 CPUState *cs = CPU(cpu); 760 761 bool new_state = (env->cp15.hcr_el2 & HCR_VF) || 762 (env->irq_line_state & CPU_INTERRUPT_VFIQ); 763 764 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { 765 if (new_state) { 766 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); 767 } else { 768 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); 769 } 770 } 771 } 772 773 void arm_cpu_update_vserr(ARMCPU *cpu) 774 { 775 /* 776 * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit. 777 */ 778 CPUARMState *env = &cpu->env; 779 CPUState *cs = CPU(cpu); 780 781 bool new_state = env->cp15.hcr_el2 & HCR_VSE; 782 783 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) { 784 if (new_state) { 785 cpu_interrupt(cs, CPU_INTERRUPT_VSERR); 786 } else { 787 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); 788 } 789 } 790 } 791 792 #ifndef CONFIG_USER_ONLY 793 static void arm_cpu_set_irq(void *opaque, int irq, int level) 794 { 795 ARMCPU *cpu = opaque; 796 CPUARMState *env = &cpu->env; 797 CPUState *cs = CPU(cpu); 798 static const int mask[] = { 799 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 800 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 801 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 802 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 803 }; 804 805 if (!arm_feature(env, ARM_FEATURE_EL2) && 806 (irq == ARM_CPU_VIRQ || irq == ARM_CPU_VFIQ)) { 807 /* 808 * The GIC might tell us about VIRQ and VFIQ state, but if we don't 809 * have EL2 support we don't care. (Unless the guest is doing something 810 * silly this will only be calls saying "level is still 0".) 811 */ 812 return; 813 } 814 815 if (level) { 816 env->irq_line_state |= mask[irq]; 817 } else { 818 env->irq_line_state &= ~mask[irq]; 819 } 820 821 switch (irq) { 822 case ARM_CPU_VIRQ: 823 arm_cpu_update_virq(cpu); 824 break; 825 case ARM_CPU_VFIQ: 826 arm_cpu_update_vfiq(cpu); 827 break; 828 case ARM_CPU_IRQ: 829 case ARM_CPU_FIQ: 830 if (level) { 831 cpu_interrupt(cs, mask[irq]); 832 } else { 833 cpu_reset_interrupt(cs, mask[irq]); 834 } 835 break; 836 default: 837 g_assert_not_reached(); 838 } 839 } 840 841 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 842 { 843 #ifdef CONFIG_KVM 844 ARMCPU *cpu = opaque; 845 CPUARMState *env = &cpu->env; 846 CPUState *cs = CPU(cpu); 847 uint32_t linestate_bit; 848 int irq_id; 849 850 switch (irq) { 851 case ARM_CPU_IRQ: 852 irq_id = KVM_ARM_IRQ_CPU_IRQ; 853 linestate_bit = CPU_INTERRUPT_HARD; 854 break; 855 case ARM_CPU_FIQ: 856 irq_id = KVM_ARM_IRQ_CPU_FIQ; 857 linestate_bit = CPU_INTERRUPT_FIQ; 858 break; 859 default: 860 g_assert_not_reached(); 861 } 862 863 if (level) { 864 env->irq_line_state |= linestate_bit; 865 } else { 866 env->irq_line_state &= ~linestate_bit; 867 } 868 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); 869 #endif 870 } 871 872 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 873 { 874 ARMCPU *cpu = ARM_CPU(cs); 875 CPUARMState *env = &cpu->env; 876 877 cpu_synchronize_state(cs); 878 return arm_cpu_data_is_big_endian(env); 879 } 880 881 #endif 882 883 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 884 { 885 ARMCPU *ac = ARM_CPU(cpu); 886 CPUARMState *env = &ac->env; 887 bool sctlr_b; 888 889 if (is_a64(env)) { 890 info->cap_arch = CS_ARCH_ARM64; 891 info->cap_insn_unit = 4; 892 info->cap_insn_split = 4; 893 } else { 894 int cap_mode; 895 if (env->thumb) { 896 info->cap_insn_unit = 2; 897 info->cap_insn_split = 4; 898 cap_mode = CS_MODE_THUMB; 899 } else { 900 info->cap_insn_unit = 4; 901 info->cap_insn_split = 4; 902 cap_mode = CS_MODE_ARM; 903 } 904 if (arm_feature(env, ARM_FEATURE_V8)) { 905 cap_mode |= CS_MODE_V8; 906 } 907 if (arm_feature(env, ARM_FEATURE_M)) { 908 cap_mode |= CS_MODE_MCLASS; 909 } 910 info->cap_arch = CS_ARCH_ARM; 911 info->cap_mode = cap_mode; 912 } 913 914 sctlr_b = arm_sctlr_b(env); 915 if (bswap_code(sctlr_b)) { 916 #if TARGET_BIG_ENDIAN 917 info->endian = BFD_ENDIAN_LITTLE; 918 #else 919 info->endian = BFD_ENDIAN_BIG; 920 #endif 921 } 922 info->flags &= ~INSN_ARM_BE32; 923 #ifndef CONFIG_USER_ONLY 924 if (sctlr_b) { 925 info->flags |= INSN_ARM_BE32; 926 } 927 #endif 928 } 929 930 #ifdef TARGET_AARCH64 931 932 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 933 { 934 ARMCPU *cpu = ARM_CPU(cs); 935 CPUARMState *env = &cpu->env; 936 uint32_t psr = pstate_read(env); 937 int i; 938 int el = arm_current_el(env); 939 const char *ns_status; 940 bool sve; 941 942 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 943 for (i = 0; i < 32; i++) { 944 if (i == 31) { 945 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); 946 } else { 947 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], 948 (i + 2) % 3 ? " " : "\n"); 949 } 950 } 951 952 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { 953 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 954 } else { 955 ns_status = ""; 956 } 957 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c", 958 psr, 959 psr & PSTATE_N ? 'N' : '-', 960 psr & PSTATE_Z ? 'Z' : '-', 961 psr & PSTATE_C ? 'C' : '-', 962 psr & PSTATE_V ? 'V' : '-', 963 ns_status, 964 el, 965 psr & PSTATE_SP ? 'h' : 't'); 966 967 if (cpu_isar_feature(aa64_sme, cpu)) { 968 qemu_fprintf(f, " SVCR=%08" PRIx64 " %c%c", 969 env->svcr, 970 (FIELD_EX64(env->svcr, SVCR, ZA) ? 'Z' : '-'), 971 (FIELD_EX64(env->svcr, SVCR, SM) ? 'S' : '-')); 972 } 973 if (cpu_isar_feature(aa64_bti, cpu)) { 974 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); 975 } 976 if (!(flags & CPU_DUMP_FPU)) { 977 qemu_fprintf(f, "\n"); 978 return; 979 } 980 if (fp_exception_el(env, el) != 0) { 981 qemu_fprintf(f, " FPU disabled\n"); 982 return; 983 } 984 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", 985 vfp_get_fpcr(env), vfp_get_fpsr(env)); 986 987 if (cpu_isar_feature(aa64_sme, cpu) && FIELD_EX64(env->svcr, SVCR, SM)) { 988 sve = sme_exception_el(env, el) == 0; 989 } else if (cpu_isar_feature(aa64_sve, cpu)) { 990 sve = sve_exception_el(env, el) == 0; 991 } else { 992 sve = false; 993 } 994 995 if (sve) { 996 int j, zcr_len = sve_vqm1_for_el(env, el); 997 998 for (i = 0; i <= FFR_PRED_NUM; i++) { 999 bool eol; 1000 if (i == FFR_PRED_NUM) { 1001 qemu_fprintf(f, "FFR="); 1002 /* It's last, so end the line. */ 1003 eol = true; 1004 } else { 1005 qemu_fprintf(f, "P%02d=", i); 1006 switch (zcr_len) { 1007 case 0: 1008 eol = i % 8 == 7; 1009 break; 1010 case 1: 1011 eol = i % 6 == 5; 1012 break; 1013 case 2: 1014 case 3: 1015 eol = i % 3 == 2; 1016 break; 1017 default: 1018 /* More than one quadword per predicate. */ 1019 eol = true; 1020 break; 1021 } 1022 } 1023 for (j = zcr_len / 4; j >= 0; j--) { 1024 int digits; 1025 if (j * 4 + 4 <= zcr_len + 1) { 1026 digits = 16; 1027 } else { 1028 digits = (zcr_len % 4 + 1) * 4; 1029 } 1030 qemu_fprintf(f, "%0*" PRIx64 "%s", digits, 1031 env->vfp.pregs[i].p[j], 1032 j ? ":" : eol ? "\n" : " "); 1033 } 1034 } 1035 1036 for (i = 0; i < 32; i++) { 1037 if (zcr_len == 0) { 1038 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", 1039 i, env->vfp.zregs[i].d[1], 1040 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); 1041 } else if (zcr_len == 1) { 1042 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 1043 ":%016" PRIx64 ":%016" PRIx64 "\n", 1044 i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2], 1045 env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]); 1046 } else { 1047 for (j = zcr_len; j >= 0; j--) { 1048 bool odd = (zcr_len - j) % 2 != 0; 1049 if (j == zcr_len) { 1050 qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1); 1051 } else if (!odd) { 1052 if (j > 0) { 1053 qemu_fprintf(f, " [%x-%x]=", j, j - 1); 1054 } else { 1055 qemu_fprintf(f, " [%x]=", j); 1056 } 1057 } 1058 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", 1059 env->vfp.zregs[i].d[j * 2 + 1], 1060 env->vfp.zregs[i].d[j * 2], 1061 odd || j == 0 ? "\n" : ":"); 1062 } 1063 } 1064 } 1065 } else { 1066 for (i = 0; i < 32; i++) { 1067 uint64_t *q = aa64_vfp_qreg(env, i); 1068 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", 1069 i, q[1], q[0], (i & 1 ? "\n" : " ")); 1070 } 1071 } 1072 } 1073 1074 #else 1075 1076 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1077 { 1078 g_assert_not_reached(); 1079 } 1080 1081 #endif 1082 1083 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1084 { 1085 ARMCPU *cpu = ARM_CPU(cs); 1086 CPUARMState *env = &cpu->env; 1087 int i; 1088 1089 if (is_a64(env)) { 1090 aarch64_cpu_dump_state(cs, f, flags); 1091 return; 1092 } 1093 1094 for (i = 0; i < 16; i++) { 1095 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]); 1096 if ((i % 4) == 3) { 1097 qemu_fprintf(f, "\n"); 1098 } else { 1099 qemu_fprintf(f, " "); 1100 } 1101 } 1102 1103 if (arm_feature(env, ARM_FEATURE_M)) { 1104 uint32_t xpsr = xpsr_read(env); 1105 const char *mode; 1106 const char *ns_status = ""; 1107 1108 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1109 ns_status = env->v7m.secure ? "S " : "NS "; 1110 } 1111 1112 if (xpsr & XPSR_EXCP) { 1113 mode = "handler"; 1114 } else { 1115 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { 1116 mode = "unpriv-thread"; 1117 } else { 1118 mode = "priv-thread"; 1119 } 1120 } 1121 1122 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", 1123 xpsr, 1124 xpsr & XPSR_N ? 'N' : '-', 1125 xpsr & XPSR_Z ? 'Z' : '-', 1126 xpsr & XPSR_C ? 'C' : '-', 1127 xpsr & XPSR_V ? 'V' : '-', 1128 xpsr & XPSR_T ? 'T' : 'A', 1129 ns_status, 1130 mode); 1131 } else { 1132 uint32_t psr = cpsr_read(env); 1133 const char *ns_status = ""; 1134 1135 if (arm_feature(env, ARM_FEATURE_EL3) && 1136 (psr & CPSR_M) != ARM_CPU_MODE_MON) { 1137 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 1138 } 1139 1140 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", 1141 psr, 1142 psr & CPSR_N ? 'N' : '-', 1143 psr & CPSR_Z ? 'Z' : '-', 1144 psr & CPSR_C ? 'C' : '-', 1145 psr & CPSR_V ? 'V' : '-', 1146 psr & CPSR_T ? 'T' : 'A', 1147 ns_status, 1148 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); 1149 } 1150 1151 if (flags & CPU_DUMP_FPU) { 1152 int numvfpregs = 0; 1153 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1154 numvfpregs = 32; 1155 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 1156 numvfpregs = 16; 1157 } 1158 for (i = 0; i < numvfpregs; i++) { 1159 uint64_t v = *aa32_vfp_dreg(env, i); 1160 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", 1161 i * 2, (uint32_t)v, 1162 i * 2 + 1, (uint32_t)(v >> 32), 1163 i, v); 1164 } 1165 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); 1166 if (cpu_isar_feature(aa32_mve, cpu)) { 1167 qemu_fprintf(f, "VPR: %08x\n", env->v7m.vpr); 1168 } 1169 } 1170 } 1171 1172 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 1173 { 1174 uint32_t Aff1 = idx / clustersz; 1175 uint32_t Aff0 = idx % clustersz; 1176 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 1177 } 1178 1179 static void arm_cpu_initfn(Object *obj) 1180 { 1181 ARMCPU *cpu = ARM_CPU(obj); 1182 1183 cpu_set_cpustate_pointers(cpu); 1184 cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal, 1185 NULL, g_free); 1186 1187 QLIST_INIT(&cpu->pre_el_change_hooks); 1188 QLIST_INIT(&cpu->el_change_hooks); 1189 1190 #ifdef CONFIG_USER_ONLY 1191 # ifdef TARGET_AARCH64 1192 /* 1193 * The linux kernel defaults to 512-bit for SVE, and 256-bit for SME. 1194 * These values were chosen to fit within the default signal frame. 1195 * See documentation for /proc/sys/abi/{sve,sme}_default_vector_length, 1196 * and our corresponding cpu property. 1197 */ 1198 cpu->sve_default_vq = 4; 1199 cpu->sme_default_vq = 2; 1200 # endif 1201 #else 1202 /* Our inbound IRQ and FIQ lines */ 1203 if (kvm_enabled()) { 1204 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 1205 * the same interface as non-KVM CPUs. 1206 */ 1207 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 1208 } else { 1209 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 1210 } 1211 1212 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 1213 ARRAY_SIZE(cpu->gt_timer_outputs)); 1214 1215 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 1216 "gicv3-maintenance-interrupt", 1); 1217 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 1218 "pmu-interrupt", 1); 1219 #endif 1220 1221 /* DTB consumers generally don't in fact care what the 'compatible' 1222 * string is, so always provide some string and trust that a hypothetical 1223 * picky DTB consumer will also provide a helpful error message. 1224 */ 1225 cpu->dtb_compatible = "qemu,unknown"; 1226 cpu->psci_version = QEMU_PSCI_VERSION_0_1; /* By default assume PSCI v0.1 */ 1227 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 1228 1229 if (tcg_enabled() || hvf_enabled()) { 1230 /* TCG and HVF implement PSCI 1.1 */ 1231 cpu->psci_version = QEMU_PSCI_VERSION_1_1; 1232 } 1233 } 1234 1235 static Property arm_cpu_gt_cntfrq_property = 1236 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 1237 NANOSECONDS_PER_SECOND / GTIMER_SCALE); 1238 1239 static Property arm_cpu_reset_cbar_property = 1240 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 1241 1242 static Property arm_cpu_reset_hivecs_property = 1243 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 1244 1245 #ifndef CONFIG_USER_ONLY 1246 static Property arm_cpu_has_el2_property = 1247 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 1248 1249 static Property arm_cpu_has_el3_property = 1250 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 1251 #endif 1252 1253 static Property arm_cpu_cfgend_property = 1254 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 1255 1256 static Property arm_cpu_has_vfp_property = 1257 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); 1258 1259 static Property arm_cpu_has_neon_property = 1260 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); 1261 1262 static Property arm_cpu_has_dsp_property = 1263 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); 1264 1265 static Property arm_cpu_has_mpu_property = 1266 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 1267 1268 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 1269 * because the CPU initfn will have already set cpu->pmsav7_dregion to 1270 * the right value for that particular CPU type, and we don't want 1271 * to override that with an incorrect constant value. 1272 */ 1273 static Property arm_cpu_pmsav7_dregion_property = 1274 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 1275 pmsav7_dregion, 1276 qdev_prop_uint32, uint32_t); 1277 1278 static bool arm_get_pmu(Object *obj, Error **errp) 1279 { 1280 ARMCPU *cpu = ARM_CPU(obj); 1281 1282 return cpu->has_pmu; 1283 } 1284 1285 static void arm_set_pmu(Object *obj, bool value, Error **errp) 1286 { 1287 ARMCPU *cpu = ARM_CPU(obj); 1288 1289 if (value) { 1290 if (kvm_enabled() && !kvm_arm_pmu_supported()) { 1291 error_setg(errp, "'pmu' feature not supported by KVM on this host"); 1292 return; 1293 } 1294 set_feature(&cpu->env, ARM_FEATURE_PMU); 1295 } else { 1296 unset_feature(&cpu->env, ARM_FEATURE_PMU); 1297 } 1298 cpu->has_pmu = value; 1299 } 1300 1301 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) 1302 { 1303 /* 1304 * The exact approach to calculating guest ticks is: 1305 * 1306 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz, 1307 * NANOSECONDS_PER_SECOND); 1308 * 1309 * We don't do that. Rather we intentionally use integer division 1310 * truncation below and in the caller for the conversion of host monotonic 1311 * time to guest ticks to provide the exact inverse for the semantics of 1312 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so 1313 * it loses precision when representing frequencies where 1314 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to 1315 * provide an exact inverse leads to scheduling timers with negative 1316 * periods, which in turn leads to sticky behaviour in the guest. 1317 * 1318 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor 1319 * cannot become zero. 1320 */ 1321 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ? 1322 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; 1323 } 1324 1325 void arm_cpu_post_init(Object *obj) 1326 { 1327 ARMCPU *cpu = ARM_CPU(obj); 1328 1329 /* M profile implies PMSA. We have to do this here rather than 1330 * in realize with the other feature-implication checks because 1331 * we look at the PMSA bit to see if we should add some properties. 1332 */ 1333 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1334 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1335 } 1336 1337 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 1338 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 1339 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); 1340 } 1341 1342 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 1343 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); 1344 } 1345 1346 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1347 object_property_add_uint64_ptr(obj, "rvbar", 1348 &cpu->rvbar_prop, 1349 OBJ_PROP_FLAG_READWRITE); 1350 } 1351 1352 #ifndef CONFIG_USER_ONLY 1353 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1354 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 1355 * prevent "has_el3" from existing on CPUs which cannot support EL3. 1356 */ 1357 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); 1358 1359 object_property_add_link(obj, "secure-memory", 1360 TYPE_MEMORY_REGION, 1361 (Object **)&cpu->secure_memory, 1362 qdev_prop_allow_set_link_before_realize, 1363 OBJ_PROP_LINK_STRONG); 1364 } 1365 1366 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 1367 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); 1368 } 1369 #endif 1370 1371 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 1372 cpu->has_pmu = true; 1373 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu); 1374 } 1375 1376 /* 1377 * Allow user to turn off VFP and Neon support, but only for TCG -- 1378 * KVM does not currently allow us to lie to the guest about its 1379 * ID/feature registers, so the guest always sees what the host has. 1380 */ 1381 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) 1382 ? cpu_isar_feature(aa64_fp_simd, cpu) 1383 : cpu_isar_feature(aa32_vfp, cpu)) { 1384 cpu->has_vfp = true; 1385 if (!kvm_enabled()) { 1386 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property); 1387 } 1388 } 1389 1390 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { 1391 cpu->has_neon = true; 1392 if (!kvm_enabled()) { 1393 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property); 1394 } 1395 } 1396 1397 if (arm_feature(&cpu->env, ARM_FEATURE_M) && 1398 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { 1399 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property); 1400 } 1401 1402 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 1403 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); 1404 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1405 qdev_property_add_static(DEVICE(obj), 1406 &arm_cpu_pmsav7_dregion_property); 1407 } 1408 } 1409 1410 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 1411 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 1412 qdev_prop_allow_set_link_before_realize, 1413 OBJ_PROP_LINK_STRONG); 1414 /* 1415 * M profile: initial value of the Secure VTOR. We can't just use 1416 * a simple DEFINE_PROP_UINT32 for this because we want to permit 1417 * the property to be set after realize. 1418 */ 1419 object_property_add_uint32_ptr(obj, "init-svtor", 1420 &cpu->init_svtor, 1421 OBJ_PROP_FLAG_READWRITE); 1422 } 1423 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1424 /* 1425 * Initial value of the NS VTOR (for cores without the Security 1426 * extension, this is the only VTOR) 1427 */ 1428 object_property_add_uint32_ptr(obj, "init-nsvtor", 1429 &cpu->init_nsvtor, 1430 OBJ_PROP_FLAG_READWRITE); 1431 } 1432 1433 /* Not DEFINE_PROP_UINT32: we want this to be settable after realize */ 1434 object_property_add_uint32_ptr(obj, "psci-conduit", 1435 &cpu->psci_conduit, 1436 OBJ_PROP_FLAG_READWRITE); 1437 1438 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); 1439 1440 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { 1441 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); 1442 } 1443 1444 if (kvm_enabled()) { 1445 kvm_arm_add_vcpu_properties(obj); 1446 } 1447 1448 #ifndef CONFIG_USER_ONLY 1449 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && 1450 cpu_isar_feature(aa64_mte, cpu)) { 1451 object_property_add_link(obj, "tag-memory", 1452 TYPE_MEMORY_REGION, 1453 (Object **)&cpu->tag_memory, 1454 qdev_prop_allow_set_link_before_realize, 1455 OBJ_PROP_LINK_STRONG); 1456 1457 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1458 object_property_add_link(obj, "secure-tag-memory", 1459 TYPE_MEMORY_REGION, 1460 (Object **)&cpu->secure_tag_memory, 1461 qdev_prop_allow_set_link_before_realize, 1462 OBJ_PROP_LINK_STRONG); 1463 } 1464 } 1465 #endif 1466 } 1467 1468 static void arm_cpu_finalizefn(Object *obj) 1469 { 1470 ARMCPU *cpu = ARM_CPU(obj); 1471 ARMELChangeHook *hook, *next; 1472 1473 g_hash_table_destroy(cpu->cp_regs); 1474 1475 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 1476 QLIST_REMOVE(hook, node); 1477 g_free(hook); 1478 } 1479 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 1480 QLIST_REMOVE(hook, node); 1481 g_free(hook); 1482 } 1483 #ifndef CONFIG_USER_ONLY 1484 if (cpu->pmu_timer) { 1485 timer_free(cpu->pmu_timer); 1486 } 1487 #endif 1488 } 1489 1490 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) 1491 { 1492 Error *local_err = NULL; 1493 1494 #ifdef TARGET_AARCH64 1495 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1496 arm_cpu_sve_finalize(cpu, &local_err); 1497 if (local_err != NULL) { 1498 error_propagate(errp, local_err); 1499 return; 1500 } 1501 1502 arm_cpu_sme_finalize(cpu, &local_err); 1503 if (local_err != NULL) { 1504 error_propagate(errp, local_err); 1505 return; 1506 } 1507 1508 arm_cpu_pauth_finalize(cpu, &local_err); 1509 if (local_err != NULL) { 1510 error_propagate(errp, local_err); 1511 return; 1512 } 1513 1514 arm_cpu_lpa2_finalize(cpu, &local_err); 1515 if (local_err != NULL) { 1516 error_propagate(errp, local_err); 1517 return; 1518 } 1519 } 1520 #endif 1521 1522 if (kvm_enabled()) { 1523 kvm_arm_steal_time_finalize(cpu, &local_err); 1524 if (local_err != NULL) { 1525 error_propagate(errp, local_err); 1526 return; 1527 } 1528 } 1529 } 1530 1531 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 1532 { 1533 CPUState *cs = CPU(dev); 1534 ARMCPU *cpu = ARM_CPU(dev); 1535 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 1536 CPUARMState *env = &cpu->env; 1537 int pagebits; 1538 Error *local_err = NULL; 1539 bool no_aa32 = false; 1540 1541 /* If we needed to query the host kernel for the CPU features 1542 * then it's possible that might have failed in the initfn, but 1543 * this is the first point where we can report it. 1544 */ 1545 if (cpu->host_cpu_probe_failed) { 1546 if (!kvm_enabled() && !hvf_enabled()) { 1547 error_setg(errp, "The 'host' CPU type can only be used with KVM or HVF"); 1548 } else { 1549 error_setg(errp, "Failed to retrieve host CPU features"); 1550 } 1551 return; 1552 } 1553 1554 #ifndef CONFIG_USER_ONLY 1555 /* The NVIC and M-profile CPU are two halves of a single piece of 1556 * hardware; trying to use one without the other is a command line 1557 * error and will result in segfaults if not caught here. 1558 */ 1559 if (arm_feature(env, ARM_FEATURE_M)) { 1560 if (!env->nvic) { 1561 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 1562 return; 1563 } 1564 } else { 1565 if (env->nvic) { 1566 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 1567 return; 1568 } 1569 } 1570 1571 if (!tcg_enabled() && !qtest_enabled()) { 1572 /* 1573 * We assume that no accelerator except TCG (and the "not really an 1574 * accelerator" qtest) can handle these features, because Arm hardware 1575 * virtualization can't virtualize them. 1576 * 1577 * Catch all the cases which might cause us to create more than one 1578 * address space for the CPU (otherwise we will assert() later in 1579 * cpu_address_space_init()). 1580 */ 1581 if (arm_feature(env, ARM_FEATURE_M)) { 1582 error_setg(errp, 1583 "Cannot enable %s when using an M-profile guest CPU", 1584 current_accel_name()); 1585 return; 1586 } 1587 if (cpu->has_el3) { 1588 error_setg(errp, 1589 "Cannot enable %s when guest CPU has EL3 enabled", 1590 current_accel_name()); 1591 return; 1592 } 1593 if (cpu->tag_memory) { 1594 error_setg(errp, 1595 "Cannot enable %s when guest CPUs has MTE enabled", 1596 current_accel_name()); 1597 return; 1598 } 1599 } 1600 1601 { 1602 uint64_t scale; 1603 1604 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { 1605 if (!cpu->gt_cntfrq_hz) { 1606 error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", 1607 cpu->gt_cntfrq_hz); 1608 return; 1609 } 1610 scale = gt_cntfrq_period_ns(cpu); 1611 } else { 1612 scale = GTIMER_SCALE; 1613 } 1614 1615 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1616 arm_gt_ptimer_cb, cpu); 1617 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1618 arm_gt_vtimer_cb, cpu); 1619 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1620 arm_gt_htimer_cb, cpu); 1621 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1622 arm_gt_stimer_cb, cpu); 1623 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1624 arm_gt_hvtimer_cb, cpu); 1625 } 1626 #endif 1627 1628 cpu_exec_realizefn(cs, &local_err); 1629 if (local_err != NULL) { 1630 error_propagate(errp, local_err); 1631 return; 1632 } 1633 1634 arm_cpu_finalize_features(cpu, &local_err); 1635 if (local_err != NULL) { 1636 error_propagate(errp, local_err); 1637 return; 1638 } 1639 1640 if (arm_feature(env, ARM_FEATURE_AARCH64) && 1641 cpu->has_vfp != cpu->has_neon) { 1642 /* 1643 * This is an architectural requirement for AArch64; AArch32 is 1644 * more flexible and permits VFP-no-Neon and Neon-no-VFP. 1645 */ 1646 error_setg(errp, 1647 "AArch64 CPUs must have both VFP and Neon or neither"); 1648 return; 1649 } 1650 1651 if (!cpu->has_vfp) { 1652 uint64_t t; 1653 uint32_t u; 1654 1655 t = cpu->isar.id_aa64isar1; 1656 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); 1657 cpu->isar.id_aa64isar1 = t; 1658 1659 t = cpu->isar.id_aa64pfr0; 1660 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); 1661 cpu->isar.id_aa64pfr0 = t; 1662 1663 u = cpu->isar.id_isar6; 1664 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); 1665 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 1666 cpu->isar.id_isar6 = u; 1667 1668 u = cpu->isar.mvfr0; 1669 u = FIELD_DP32(u, MVFR0, FPSP, 0); 1670 u = FIELD_DP32(u, MVFR0, FPDP, 0); 1671 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); 1672 u = FIELD_DP32(u, MVFR0, FPSQRT, 0); 1673 u = FIELD_DP32(u, MVFR0, FPROUND, 0); 1674 if (!arm_feature(env, ARM_FEATURE_M)) { 1675 u = FIELD_DP32(u, MVFR0, FPTRAP, 0); 1676 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); 1677 } 1678 cpu->isar.mvfr0 = u; 1679 1680 u = cpu->isar.mvfr1; 1681 u = FIELD_DP32(u, MVFR1, FPFTZ, 0); 1682 u = FIELD_DP32(u, MVFR1, FPDNAN, 0); 1683 u = FIELD_DP32(u, MVFR1, FPHP, 0); 1684 if (arm_feature(env, ARM_FEATURE_M)) { 1685 u = FIELD_DP32(u, MVFR1, FP16, 0); 1686 } 1687 cpu->isar.mvfr1 = u; 1688 1689 u = cpu->isar.mvfr2; 1690 u = FIELD_DP32(u, MVFR2, FPMISC, 0); 1691 cpu->isar.mvfr2 = u; 1692 } 1693 1694 if (!cpu->has_neon) { 1695 uint64_t t; 1696 uint32_t u; 1697 1698 unset_feature(env, ARM_FEATURE_NEON); 1699 1700 t = cpu->isar.id_aa64isar0; 1701 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 0); 1702 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0); 1703 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0); 1704 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 0); 1705 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 0); 1706 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 0); 1707 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); 1708 cpu->isar.id_aa64isar0 = t; 1709 1710 t = cpu->isar.id_aa64isar1; 1711 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); 1712 t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 0); 1713 t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0); 1714 cpu->isar.id_aa64isar1 = t; 1715 1716 t = cpu->isar.id_aa64pfr0; 1717 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); 1718 cpu->isar.id_aa64pfr0 = t; 1719 1720 u = cpu->isar.id_isar5; 1721 u = FIELD_DP32(u, ID_ISAR5, AES, 0); 1722 u = FIELD_DP32(u, ID_ISAR5, SHA1, 0); 1723 u = FIELD_DP32(u, ID_ISAR5, SHA2, 0); 1724 u = FIELD_DP32(u, ID_ISAR5, RDM, 0); 1725 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); 1726 cpu->isar.id_isar5 = u; 1727 1728 u = cpu->isar.id_isar6; 1729 u = FIELD_DP32(u, ID_ISAR6, DP, 0); 1730 u = FIELD_DP32(u, ID_ISAR6, FHM, 0); 1731 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 1732 u = FIELD_DP32(u, ID_ISAR6, I8MM, 0); 1733 cpu->isar.id_isar6 = u; 1734 1735 if (!arm_feature(env, ARM_FEATURE_M)) { 1736 u = cpu->isar.mvfr1; 1737 u = FIELD_DP32(u, MVFR1, SIMDLS, 0); 1738 u = FIELD_DP32(u, MVFR1, SIMDINT, 0); 1739 u = FIELD_DP32(u, MVFR1, SIMDSP, 0); 1740 u = FIELD_DP32(u, MVFR1, SIMDHP, 0); 1741 cpu->isar.mvfr1 = u; 1742 1743 u = cpu->isar.mvfr2; 1744 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0); 1745 cpu->isar.mvfr2 = u; 1746 } 1747 } 1748 1749 if (!cpu->has_neon && !cpu->has_vfp) { 1750 uint64_t t; 1751 uint32_t u; 1752 1753 t = cpu->isar.id_aa64isar0; 1754 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); 1755 cpu->isar.id_aa64isar0 = t; 1756 1757 t = cpu->isar.id_aa64isar1; 1758 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); 1759 cpu->isar.id_aa64isar1 = t; 1760 1761 u = cpu->isar.mvfr0; 1762 u = FIELD_DP32(u, MVFR0, SIMDREG, 0); 1763 cpu->isar.mvfr0 = u; 1764 1765 /* Despite the name, this field covers both VFP and Neon */ 1766 u = cpu->isar.mvfr1; 1767 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); 1768 cpu->isar.mvfr1 = u; 1769 } 1770 1771 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { 1772 uint32_t u; 1773 1774 unset_feature(env, ARM_FEATURE_THUMB_DSP); 1775 1776 u = cpu->isar.id_isar1; 1777 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1); 1778 cpu->isar.id_isar1 = u; 1779 1780 u = cpu->isar.id_isar2; 1781 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); 1782 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); 1783 cpu->isar.id_isar2 = u; 1784 1785 u = cpu->isar.id_isar3; 1786 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); 1787 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); 1788 cpu->isar.id_isar3 = u; 1789 } 1790 1791 /* Some features automatically imply others: */ 1792 if (arm_feature(env, ARM_FEATURE_V8)) { 1793 if (arm_feature(env, ARM_FEATURE_M)) { 1794 set_feature(env, ARM_FEATURE_V7); 1795 } else { 1796 set_feature(env, ARM_FEATURE_V7VE); 1797 } 1798 } 1799 1800 /* 1801 * There exist AArch64 cpus without AArch32 support. When KVM 1802 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 1803 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 1804 * As a general principle, we also do not make ID register 1805 * consistency checks anywhere unless using TCG, because only 1806 * for TCG would a consistency-check failure be a QEMU bug. 1807 */ 1808 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1809 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 1810 } 1811 1812 if (arm_feature(env, ARM_FEATURE_V7VE)) { 1813 /* v7 Virtualization Extensions. In real hardware this implies 1814 * EL2 and also the presence of the Security Extensions. 1815 * For QEMU, for backwards-compatibility we implement some 1816 * CPUs or CPU configs which have no actual EL2 or EL3 but do 1817 * include the various other features that V7VE implies. 1818 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 1819 * Security Extensions is ARM_FEATURE_EL3. 1820 */ 1821 assert(!tcg_enabled() || no_aa32 || 1822 cpu_isar_feature(aa32_arm_div, cpu)); 1823 set_feature(env, ARM_FEATURE_LPAE); 1824 set_feature(env, ARM_FEATURE_V7); 1825 } 1826 if (arm_feature(env, ARM_FEATURE_V7)) { 1827 set_feature(env, ARM_FEATURE_VAPA); 1828 set_feature(env, ARM_FEATURE_THUMB2); 1829 set_feature(env, ARM_FEATURE_MPIDR); 1830 if (!arm_feature(env, ARM_FEATURE_M)) { 1831 set_feature(env, ARM_FEATURE_V6K); 1832 } else { 1833 set_feature(env, ARM_FEATURE_V6); 1834 } 1835 1836 /* Always define VBAR for V7 CPUs even if it doesn't exist in 1837 * non-EL3 configs. This is needed by some legacy boards. 1838 */ 1839 set_feature(env, ARM_FEATURE_VBAR); 1840 } 1841 if (arm_feature(env, ARM_FEATURE_V6K)) { 1842 set_feature(env, ARM_FEATURE_V6); 1843 set_feature(env, ARM_FEATURE_MVFR); 1844 } 1845 if (arm_feature(env, ARM_FEATURE_V6)) { 1846 set_feature(env, ARM_FEATURE_V5); 1847 if (!arm_feature(env, ARM_FEATURE_M)) { 1848 assert(!tcg_enabled() || no_aa32 || 1849 cpu_isar_feature(aa32_jazelle, cpu)); 1850 set_feature(env, ARM_FEATURE_AUXCR); 1851 } 1852 } 1853 if (arm_feature(env, ARM_FEATURE_V5)) { 1854 set_feature(env, ARM_FEATURE_V4T); 1855 } 1856 if (arm_feature(env, ARM_FEATURE_LPAE)) { 1857 set_feature(env, ARM_FEATURE_V7MP); 1858 } 1859 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 1860 set_feature(env, ARM_FEATURE_CBAR); 1861 } 1862 if (arm_feature(env, ARM_FEATURE_THUMB2) && 1863 !arm_feature(env, ARM_FEATURE_M)) { 1864 set_feature(env, ARM_FEATURE_THUMB_DSP); 1865 } 1866 1867 /* 1868 * We rely on no XScale CPU having VFP so we can use the same bits in the 1869 * TB flags field for VECSTRIDE and XSCALE_CPAR. 1870 */ 1871 assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) || 1872 !cpu_isar_feature(aa32_vfp_simd, cpu) || 1873 !arm_feature(env, ARM_FEATURE_XSCALE)); 1874 1875 if (arm_feature(env, ARM_FEATURE_V7) && 1876 !arm_feature(env, ARM_FEATURE_M) && 1877 !arm_feature(env, ARM_FEATURE_PMSA)) { 1878 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 1879 * can use 4K pages. 1880 */ 1881 pagebits = 12; 1882 } else { 1883 /* For CPUs which might have tiny 1K pages, or which have an 1884 * MPU and might have small region sizes, stick with 1K pages. 1885 */ 1886 pagebits = 10; 1887 } 1888 if (!set_preferred_target_page_bits(pagebits)) { 1889 /* This can only ever happen for hotplugging a CPU, or if 1890 * the board code incorrectly creates a CPU which it has 1891 * promised via minimum_page_size that it will not. 1892 */ 1893 error_setg(errp, "This CPU requires a smaller page size than the " 1894 "system is using"); 1895 return; 1896 } 1897 1898 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 1899 * We don't support setting cluster ID ([16..23]) (known as Aff2 1900 * in later ARM ARM versions), or any of the higher affinity level fields, 1901 * so these bits always RAZ. 1902 */ 1903 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 1904 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 1905 ARM_DEFAULT_CPUS_PER_CLUSTER); 1906 } 1907 1908 if (cpu->reset_hivecs) { 1909 cpu->reset_sctlr |= (1 << 13); 1910 } 1911 1912 if (cpu->cfgend) { 1913 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1914 cpu->reset_sctlr |= SCTLR_EE; 1915 } else { 1916 cpu->reset_sctlr |= SCTLR_B; 1917 } 1918 } 1919 1920 if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) { 1921 /* If the has_el3 CPU property is disabled then we need to disable the 1922 * feature. 1923 */ 1924 unset_feature(env, ARM_FEATURE_EL3); 1925 1926 /* 1927 * Disable the security extension feature bits in the processor 1928 * feature registers as well. 1929 */ 1930 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0); 1931 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0); 1932 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 1933 ID_AA64PFR0, EL3, 0); 1934 } 1935 1936 if (!cpu->has_el2) { 1937 unset_feature(env, ARM_FEATURE_EL2); 1938 } 1939 1940 if (!cpu->has_pmu) { 1941 unset_feature(env, ARM_FEATURE_PMU); 1942 } 1943 if (arm_feature(env, ARM_FEATURE_PMU)) { 1944 pmu_init(cpu); 1945 1946 if (!kvm_enabled()) { 1947 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); 1948 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); 1949 } 1950 1951 #ifndef CONFIG_USER_ONLY 1952 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, 1953 cpu); 1954 #endif 1955 } else { 1956 cpu->isar.id_aa64dfr0 = 1957 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); 1958 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0); 1959 cpu->pmceid0 = 0; 1960 cpu->pmceid1 = 0; 1961 } 1962 1963 if (!arm_feature(env, ARM_FEATURE_EL2)) { 1964 /* 1965 * Disable the hypervisor feature bits in the processor feature 1966 * registers if we don't have EL2. 1967 */ 1968 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 1969 ID_AA64PFR0, EL2, 0); 1970 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, 1971 ID_PFR1, VIRTUALIZATION, 0); 1972 } 1973 1974 #ifndef CONFIG_USER_ONLY 1975 if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) { 1976 /* 1977 * Disable the MTE feature bits if we do not have tag-memory 1978 * provided by the machine. 1979 */ 1980 cpu->isar.id_aa64pfr1 = 1981 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); 1982 } 1983 #endif 1984 1985 if (tcg_enabled()) { 1986 /* 1987 * Don't report the Statistical Profiling Extension in the ID 1988 * registers, because TCG doesn't implement it yet (not even a 1989 * minimal stub version) and guests will fall over when they 1990 * try to access the non-existent system registers for it. 1991 */ 1992 cpu->isar.id_aa64dfr0 = 1993 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0); 1994 } 1995 1996 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 1997 * to false or by setting pmsav7-dregion to 0. 1998 */ 1999 if (!cpu->has_mpu) { 2000 cpu->pmsav7_dregion = 0; 2001 } 2002 if (cpu->pmsav7_dregion == 0) { 2003 cpu->has_mpu = false; 2004 } 2005 2006 if (arm_feature(env, ARM_FEATURE_PMSA) && 2007 arm_feature(env, ARM_FEATURE_V7)) { 2008 uint32_t nr = cpu->pmsav7_dregion; 2009 2010 if (nr > 0xff) { 2011 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 2012 return; 2013 } 2014 2015 if (nr) { 2016 if (arm_feature(env, ARM_FEATURE_V8)) { 2017 /* PMSAv8 */ 2018 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 2019 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 2020 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 2021 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 2022 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 2023 } 2024 } else { 2025 env->pmsav7.drbar = g_new0(uint32_t, nr); 2026 env->pmsav7.drsr = g_new0(uint32_t, nr); 2027 env->pmsav7.dracr = g_new0(uint32_t, nr); 2028 } 2029 } 2030 } 2031 2032 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 2033 uint32_t nr = cpu->sau_sregion; 2034 2035 if (nr > 0xff) { 2036 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 2037 return; 2038 } 2039 2040 if (nr) { 2041 env->sau.rbar = g_new0(uint32_t, nr); 2042 env->sau.rlar = g_new0(uint32_t, nr); 2043 } 2044 } 2045 2046 if (arm_feature(env, ARM_FEATURE_EL3)) { 2047 set_feature(env, ARM_FEATURE_VBAR); 2048 } 2049 2050 register_cp_regs_for_features(cpu); 2051 arm_cpu_register_gdb_regs_for_features(cpu); 2052 2053 init_cpreg_list(cpu); 2054 2055 #ifndef CONFIG_USER_ONLY 2056 MachineState *ms = MACHINE(qdev_get_machine()); 2057 unsigned int smp_cpus = ms->smp.cpus; 2058 bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY); 2059 2060 /* 2061 * We must set cs->num_ases to the final value before 2062 * the first call to cpu_address_space_init. 2063 */ 2064 if (cpu->tag_memory != NULL) { 2065 cs->num_ases = 3 + has_secure; 2066 } else { 2067 cs->num_ases = 1 + has_secure; 2068 } 2069 2070 if (has_secure) { 2071 if (!cpu->secure_memory) { 2072 cpu->secure_memory = cs->memory; 2073 } 2074 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 2075 cpu->secure_memory); 2076 } 2077 2078 if (cpu->tag_memory != NULL) { 2079 cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory", 2080 cpu->tag_memory); 2081 if (has_secure) { 2082 cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory", 2083 cpu->secure_tag_memory); 2084 } 2085 } 2086 2087 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 2088 2089 /* No core_count specified, default to smp_cpus. */ 2090 if (cpu->core_count == -1) { 2091 cpu->core_count = smp_cpus; 2092 } 2093 #endif 2094 2095 if (tcg_enabled()) { 2096 int dcz_blocklen = 4 << cpu->dcz_blocksize; 2097 2098 /* 2099 * We only support DCZ blocklen that fits on one page. 2100 * 2101 * Architectually this is always true. However TARGET_PAGE_SIZE 2102 * is variable and, for compatibility with -machine virt-2.7, 2103 * is only 1KiB, as an artifact of legacy ARMv5 subpage support. 2104 * But even then, while the largest architectural DCZ blocklen 2105 * is 2KiB, no cpu actually uses such a large blocklen. 2106 */ 2107 assert(dcz_blocklen <= TARGET_PAGE_SIZE); 2108 2109 /* 2110 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say 2111 * both nibbles of each byte storing tag data may be written at once. 2112 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32. 2113 */ 2114 if (cpu_isar_feature(aa64_mte, cpu)) { 2115 assert(dcz_blocklen >= 2 * TAG_GRANULE); 2116 } 2117 } 2118 2119 qemu_init_vcpu(cs); 2120 cpu_reset(cs); 2121 2122 acc->parent_realize(dev, errp); 2123 } 2124 2125 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 2126 { 2127 ObjectClass *oc; 2128 char *typename; 2129 char **cpuname; 2130 const char *cpunamestr; 2131 2132 cpuname = g_strsplit(cpu_model, ",", 1); 2133 cpunamestr = cpuname[0]; 2134 #ifdef CONFIG_USER_ONLY 2135 /* For backwards compatibility usermode emulation allows "-cpu any", 2136 * which has the same semantics as "-cpu max". 2137 */ 2138 if (!strcmp(cpunamestr, "any")) { 2139 cpunamestr = "max"; 2140 } 2141 #endif 2142 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 2143 oc = object_class_by_name(typename); 2144 g_strfreev(cpuname); 2145 g_free(typename); 2146 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 2147 object_class_is_abstract(oc)) { 2148 return NULL; 2149 } 2150 return oc; 2151 } 2152 2153 static Property arm_cpu_properties[] = { 2154 DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), 2155 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 2156 mp_affinity, ARM64_AFFINITY_INVALID), 2157 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 2158 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 2159 DEFINE_PROP_END_OF_LIST() 2160 }; 2161 2162 static gchar *arm_gdb_arch_name(CPUState *cs) 2163 { 2164 ARMCPU *cpu = ARM_CPU(cs); 2165 CPUARMState *env = &cpu->env; 2166 2167 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 2168 return g_strdup("iwmmxt"); 2169 } 2170 return g_strdup("arm"); 2171 } 2172 2173 #ifndef CONFIG_USER_ONLY 2174 #include "hw/core/sysemu-cpu-ops.h" 2175 2176 static const struct SysemuCPUOps arm_sysemu_ops = { 2177 .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug, 2178 .asidx_from_attrs = arm_asidx_from_attrs, 2179 .write_elf32_note = arm_cpu_write_elf32_note, 2180 .write_elf64_note = arm_cpu_write_elf64_note, 2181 .virtio_is_big_endian = arm_cpu_virtio_is_big_endian, 2182 .legacy_vmsd = &vmstate_arm_cpu, 2183 }; 2184 #endif 2185 2186 #ifdef CONFIG_TCG 2187 static const struct TCGCPUOps arm_tcg_ops = { 2188 .initialize = arm_translate_init, 2189 .synchronize_from_tb = arm_cpu_synchronize_from_tb, 2190 .debug_excp_handler = arm_debug_excp_handler, 2191 .restore_state_to_opc = arm_restore_state_to_opc, 2192 2193 #ifdef CONFIG_USER_ONLY 2194 .record_sigsegv = arm_cpu_record_sigsegv, 2195 .record_sigbus = arm_cpu_record_sigbus, 2196 #else 2197 .tlb_fill = arm_cpu_tlb_fill, 2198 .cpu_exec_interrupt = arm_cpu_exec_interrupt, 2199 .do_interrupt = arm_cpu_do_interrupt, 2200 .do_transaction_failed = arm_cpu_do_transaction_failed, 2201 .do_unaligned_access = arm_cpu_do_unaligned_access, 2202 .adjust_watchpoint_address = arm_adjust_watchpoint_address, 2203 .debug_check_watchpoint = arm_debug_check_watchpoint, 2204 .debug_check_breakpoint = arm_debug_check_breakpoint, 2205 #endif /* !CONFIG_USER_ONLY */ 2206 }; 2207 #endif /* CONFIG_TCG */ 2208 2209 static void arm_cpu_class_init(ObjectClass *oc, void *data) 2210 { 2211 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2212 CPUClass *cc = CPU_CLASS(acc); 2213 DeviceClass *dc = DEVICE_CLASS(oc); 2214 2215 device_class_set_parent_realize(dc, arm_cpu_realizefn, 2216 &acc->parent_realize); 2217 2218 device_class_set_props(dc, arm_cpu_properties); 2219 device_class_set_parent_reset(dc, arm_cpu_reset, &acc->parent_reset); 2220 2221 cc->class_by_name = arm_cpu_class_by_name; 2222 cc->has_work = arm_cpu_has_work; 2223 cc->dump_state = arm_cpu_dump_state; 2224 cc->set_pc = arm_cpu_set_pc; 2225 cc->get_pc = arm_cpu_get_pc; 2226 cc->gdb_read_register = arm_cpu_gdb_read_register; 2227 cc->gdb_write_register = arm_cpu_gdb_write_register; 2228 #ifndef CONFIG_USER_ONLY 2229 cc->sysemu_ops = &arm_sysemu_ops; 2230 #endif 2231 cc->gdb_num_core_regs = 26; 2232 cc->gdb_core_xml_file = "arm-core.xml"; 2233 cc->gdb_arch_name = arm_gdb_arch_name; 2234 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; 2235 cc->gdb_stop_before_watchpoint = true; 2236 cc->disas_set_info = arm_disas_set_info; 2237 2238 #ifdef CONFIG_TCG 2239 cc->tcg_ops = &arm_tcg_ops; 2240 #endif /* CONFIG_TCG */ 2241 } 2242 2243 static void arm_cpu_instance_init(Object *obj) 2244 { 2245 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 2246 2247 acc->info->initfn(obj); 2248 arm_cpu_post_init(obj); 2249 } 2250 2251 static void cpu_register_class_init(ObjectClass *oc, void *data) 2252 { 2253 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2254 2255 acc->info = data; 2256 } 2257 2258 void arm_cpu_register(const ARMCPUInfo *info) 2259 { 2260 TypeInfo type_info = { 2261 .parent = TYPE_ARM_CPU, 2262 .instance_size = sizeof(ARMCPU), 2263 .instance_align = __alignof__(ARMCPU), 2264 .instance_init = arm_cpu_instance_init, 2265 .class_size = sizeof(ARMCPUClass), 2266 .class_init = info->class_init ?: cpu_register_class_init, 2267 .class_data = (void *)info, 2268 }; 2269 2270 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2271 type_register(&type_info); 2272 g_free((void *)type_info.name); 2273 } 2274 2275 static const TypeInfo arm_cpu_type_info = { 2276 .name = TYPE_ARM_CPU, 2277 .parent = TYPE_CPU, 2278 .instance_size = sizeof(ARMCPU), 2279 .instance_align = __alignof__(ARMCPU), 2280 .instance_init = arm_cpu_initfn, 2281 .instance_finalize = arm_cpu_finalizefn, 2282 .abstract = true, 2283 .class_size = sizeof(ARMCPUClass), 2284 .class_init = arm_cpu_class_init, 2285 }; 2286 2287 static void arm_cpu_register_types(void) 2288 { 2289 type_register_static(&arm_cpu_type_info); 2290 } 2291 2292 type_init(arm_cpu_register_types) 2293