1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/error-report.h" 23 #include "qapi/error.h" 24 #include "cpu.h" 25 #include "internals.h" 26 #include "qemu-common.h" 27 #include "exec/exec-all.h" 28 #include "hw/qdev-properties.h" 29 #if !defined(CONFIG_USER_ONLY) 30 #include "hw/loader.h" 31 #endif 32 #include "hw/arm/arm.h" 33 #include "sysemu/sysemu.h" 34 #include "sysemu/hw_accel.h" 35 #include "kvm_arm.h" 36 37 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 38 { 39 ARMCPU *cpu = ARM_CPU(cs); 40 41 cpu->env.regs[15] = value; 42 } 43 44 static bool arm_cpu_has_work(CPUState *cs) 45 { 46 ARMCPU *cpu = ARM_CPU(cs); 47 48 return !cpu->powered_off 49 && cs->interrupt_request & 50 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 51 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ 52 | CPU_INTERRUPT_EXITTB); 53 } 54 55 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook, 56 void *opaque) 57 { 58 /* We currently only support registering a single hook function */ 59 assert(!cpu->el_change_hook); 60 cpu->el_change_hook = hook; 61 cpu->el_change_hook_opaque = opaque; 62 } 63 64 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 65 { 66 /* Reset a single ARMCPRegInfo register */ 67 ARMCPRegInfo *ri = value; 68 ARMCPU *cpu = opaque; 69 70 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { 71 return; 72 } 73 74 if (ri->resetfn) { 75 ri->resetfn(&cpu->env, ri); 76 return; 77 } 78 79 /* A zero offset is never possible as it would be regs[0] 80 * so we use it to indicate that reset is being handled elsewhere. 81 * This is basically only used for fields in non-core coprocessors 82 * (like the pxa2xx ones). 83 */ 84 if (!ri->fieldoffset) { 85 return; 86 } 87 88 if (cpreg_field_is_64bit(ri)) { 89 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 90 } else { 91 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 92 } 93 } 94 95 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 96 { 97 /* Purely an assertion check: we've already done reset once, 98 * so now check that running the reset for the cpreg doesn't 99 * change its value. This traps bugs where two different cpregs 100 * both try to reset the same state field but to different values. 101 */ 102 ARMCPRegInfo *ri = value; 103 ARMCPU *cpu = opaque; 104 uint64_t oldvalue, newvalue; 105 106 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 107 return; 108 } 109 110 oldvalue = read_raw_cp_reg(&cpu->env, ri); 111 cp_reg_reset(key, value, opaque); 112 newvalue = read_raw_cp_reg(&cpu->env, ri); 113 assert(oldvalue == newvalue); 114 } 115 116 /* CPUClass::reset() */ 117 static void arm_cpu_reset(CPUState *s) 118 { 119 ARMCPU *cpu = ARM_CPU(s); 120 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 121 CPUARMState *env = &cpu->env; 122 123 acc->parent_reset(s); 124 125 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 126 127 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 128 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 129 130 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 131 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; 132 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; 133 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2; 134 135 cpu->powered_off = cpu->start_powered_off; 136 s->halted = cpu->start_powered_off; 137 138 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 139 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 140 } 141 142 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 143 /* 64 bit CPUs always start in 64 bit mode */ 144 env->aarch64 = 1; 145 #if defined(CONFIG_USER_ONLY) 146 env->pstate = PSTATE_MODE_EL0t; 147 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 148 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 149 /* and to the FP/Neon instructions */ 150 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); 151 #else 152 /* Reset into the highest available EL */ 153 if (arm_feature(env, ARM_FEATURE_EL3)) { 154 env->pstate = PSTATE_MODE_EL3h; 155 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 156 env->pstate = PSTATE_MODE_EL2h; 157 } else { 158 env->pstate = PSTATE_MODE_EL1h; 159 } 160 env->pc = cpu->rvbar; 161 #endif 162 } else { 163 #if defined(CONFIG_USER_ONLY) 164 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 165 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); 166 #endif 167 } 168 169 #if defined(CONFIG_USER_ONLY) 170 env->uncached_cpsr = ARM_CPU_MODE_USR; 171 /* For user mode we must enable access to coprocessors */ 172 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 173 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 174 env->cp15.c15_cpar = 3; 175 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 176 env->cp15.c15_cpar = 1; 177 } 178 #else 179 /* SVC mode with interrupts disabled. */ 180 env->uncached_cpsr = ARM_CPU_MODE_SVC; 181 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 182 183 if (arm_feature(env, ARM_FEATURE_M)) { 184 uint32_t initial_msp; /* Loaded from 0x0 */ 185 uint32_t initial_pc; /* Loaded from 0x4 */ 186 uint8_t *rom; 187 188 /* For M profile we store FAULTMASK and PRIMASK in the 189 * PSTATE F and I bits; these are both clear at reset. 190 */ 191 env->daif &= ~(PSTATE_I | PSTATE_F); 192 193 /* The reset value of this bit is IMPDEF, but ARM recommends 194 * that it resets to 1, so QEMU always does that rather than making 195 * it dependent on CPU model. 196 */ 197 env->v7m.ccr = R_V7M_CCR_STKALIGN_MASK; 198 199 /* Unlike A/R profile, M profile defines the reset LR value */ 200 env->regs[14] = 0xffffffff; 201 202 /* Load the initial SP and PC from the vector table at address 0 */ 203 rom = rom_ptr(0); 204 if (rom) { 205 /* Address zero is covered by ROM which hasn't yet been 206 * copied into physical memory. 207 */ 208 initial_msp = ldl_p(rom); 209 initial_pc = ldl_p(rom + 4); 210 } else { 211 /* Address zero not covered by a ROM blob, or the ROM blob 212 * is in non-modifiable memory and this is a second reset after 213 * it got copied into memory. In the latter case, rom_ptr 214 * will return a NULL pointer and we should use ldl_phys instead. 215 */ 216 initial_msp = ldl_phys(s->as, 0); 217 initial_pc = ldl_phys(s->as, 4); 218 } 219 220 env->regs[13] = initial_msp & 0xFFFFFFFC; 221 env->regs[15] = initial_pc & ~1; 222 env->thumb = initial_pc & 1; 223 } 224 225 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 226 * executing as AArch32 then check if highvecs are enabled and 227 * adjust the PC accordingly. 228 */ 229 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 230 env->regs[15] = 0xFFFF0000; 231 } 232 233 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 234 #endif 235 set_flush_to_zero(1, &env->vfp.standard_fp_status); 236 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 237 set_default_nan_mode(1, &env->vfp.standard_fp_status); 238 set_float_detect_tininess(float_tininess_before_rounding, 239 &env->vfp.fp_status); 240 set_float_detect_tininess(float_tininess_before_rounding, 241 &env->vfp.standard_fp_status); 242 #ifndef CONFIG_USER_ONLY 243 if (kvm_enabled()) { 244 kvm_arm_reset_vcpu(cpu); 245 } 246 #endif 247 248 hw_breakpoint_update_all(cpu); 249 hw_watchpoint_update_all(cpu); 250 } 251 252 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 253 { 254 CPUClass *cc = CPU_GET_CLASS(cs); 255 CPUARMState *env = cs->env_ptr; 256 uint32_t cur_el = arm_current_el(env); 257 bool secure = arm_is_secure(env); 258 uint32_t target_el; 259 uint32_t excp_idx; 260 bool ret = false; 261 262 if (interrupt_request & CPU_INTERRUPT_FIQ) { 263 excp_idx = EXCP_FIQ; 264 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 265 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 266 cs->exception_index = excp_idx; 267 env->exception.target_el = target_el; 268 cc->do_interrupt(cs); 269 ret = true; 270 } 271 } 272 if (interrupt_request & CPU_INTERRUPT_HARD) { 273 excp_idx = EXCP_IRQ; 274 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 275 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 276 cs->exception_index = excp_idx; 277 env->exception.target_el = target_el; 278 cc->do_interrupt(cs); 279 ret = true; 280 } 281 } 282 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 283 excp_idx = EXCP_VIRQ; 284 target_el = 1; 285 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 286 cs->exception_index = excp_idx; 287 env->exception.target_el = target_el; 288 cc->do_interrupt(cs); 289 ret = true; 290 } 291 } 292 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 293 excp_idx = EXCP_VFIQ; 294 target_el = 1; 295 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 296 cs->exception_index = excp_idx; 297 env->exception.target_el = target_el; 298 cc->do_interrupt(cs); 299 ret = true; 300 } 301 } 302 303 return ret; 304 } 305 306 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 307 static void arm_v7m_unassigned_access(CPUState *cpu, hwaddr addr, 308 bool is_write, bool is_exec, int opaque, 309 unsigned size) 310 { 311 ARMCPU *arm = ARM_CPU(cpu); 312 CPUARMState *env = &arm->env; 313 314 /* ARMv7-M interrupt return works by loading a magic value into the PC. 315 * On real hardware the load causes the return to occur. The qemu 316 * implementation performs the jump normally, then does the exception 317 * return by throwing a special exception when when the CPU tries to 318 * execute code at the magic address. 319 */ 320 if (env->v7m.exception != 0 && addr >= 0xfffffff0 && is_exec) { 321 cpu->exception_index = EXCP_EXCEPTION_EXIT; 322 cpu_loop_exit(cpu); 323 } 324 325 /* In real hardware an attempt to access parts of the address space 326 * with nothing there will usually cause an external abort. 327 * However our QEMU board models are often missing device models where 328 * the guest can boot anyway with the default read-as-zero/writes-ignored 329 * behaviour that you get without a QEMU unassigned_access hook. 330 * So just return here to retain that default behaviour. 331 */ 332 } 333 334 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 335 { 336 CPUClass *cc = CPU_GET_CLASS(cs); 337 ARMCPU *cpu = ARM_CPU(cs); 338 CPUARMState *env = &cpu->env; 339 bool ret = false; 340 341 342 if (interrupt_request & CPU_INTERRUPT_FIQ 343 && !(env->daif & PSTATE_F)) { 344 cs->exception_index = EXCP_FIQ; 345 cc->do_interrupt(cs); 346 ret = true; 347 } 348 /* ARMv7-M interrupt return works by loading a magic value 349 * into the PC. On real hardware the load causes the 350 * return to occur. The qemu implementation performs the 351 * jump normally, then does the exception return when the 352 * CPU tries to execute code at the magic address. 353 * This will cause the magic PC value to be pushed to 354 * the stack if an interrupt occurred at the wrong time. 355 * We avoid this by disabling interrupts when 356 * pc contains a magic address. 357 */ 358 if (interrupt_request & CPU_INTERRUPT_HARD 359 && !(env->daif & PSTATE_I) 360 && (env->regs[15] < 0xfffffff0)) { 361 cs->exception_index = EXCP_IRQ; 362 cc->do_interrupt(cs); 363 ret = true; 364 } 365 return ret; 366 } 367 #endif 368 369 #ifndef CONFIG_USER_ONLY 370 static void arm_cpu_set_irq(void *opaque, int irq, int level) 371 { 372 ARMCPU *cpu = opaque; 373 CPUARMState *env = &cpu->env; 374 CPUState *cs = CPU(cpu); 375 static const int mask[] = { 376 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 377 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 378 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 379 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 380 }; 381 382 switch (irq) { 383 case ARM_CPU_VIRQ: 384 case ARM_CPU_VFIQ: 385 assert(arm_feature(env, ARM_FEATURE_EL2)); 386 /* fall through */ 387 case ARM_CPU_IRQ: 388 case ARM_CPU_FIQ: 389 if (level) { 390 cpu_interrupt(cs, mask[irq]); 391 } else { 392 cpu_reset_interrupt(cs, mask[irq]); 393 } 394 break; 395 default: 396 g_assert_not_reached(); 397 } 398 } 399 400 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 401 { 402 #ifdef CONFIG_KVM 403 ARMCPU *cpu = opaque; 404 CPUState *cs = CPU(cpu); 405 int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT; 406 407 switch (irq) { 408 case ARM_CPU_IRQ: 409 kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; 410 break; 411 case ARM_CPU_FIQ: 412 kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; 413 break; 414 default: 415 g_assert_not_reached(); 416 } 417 kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; 418 kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); 419 #endif 420 } 421 422 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 423 { 424 ARMCPU *cpu = ARM_CPU(cs); 425 CPUARMState *env = &cpu->env; 426 427 cpu_synchronize_state(cs); 428 return arm_cpu_data_is_big_endian(env); 429 } 430 431 #endif 432 433 static inline void set_feature(CPUARMState *env, int feature) 434 { 435 env->features |= 1ULL << feature; 436 } 437 438 static inline void unset_feature(CPUARMState *env, int feature) 439 { 440 env->features &= ~(1ULL << feature); 441 } 442 443 static int 444 print_insn_thumb1(bfd_vma pc, disassemble_info *info) 445 { 446 return print_insn_arm(pc | 1, info); 447 } 448 449 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 450 { 451 ARMCPU *ac = ARM_CPU(cpu); 452 CPUARMState *env = &ac->env; 453 454 if (is_a64(env)) { 455 /* We might not be compiled with the A64 disassembler 456 * because it needs a C++ compiler. Leave print_insn 457 * unset in this case to use the caller default behaviour. 458 */ 459 #if defined(CONFIG_ARM_A64_DIS) 460 info->print_insn = print_insn_arm_a64; 461 #endif 462 } else if (env->thumb) { 463 info->print_insn = print_insn_thumb1; 464 } else { 465 info->print_insn = print_insn_arm; 466 } 467 if (bswap_code(arm_sctlr_b(env))) { 468 #ifdef TARGET_WORDS_BIGENDIAN 469 info->endian = BFD_ENDIAN_LITTLE; 470 #else 471 info->endian = BFD_ENDIAN_BIG; 472 #endif 473 } 474 } 475 476 static void arm_cpu_initfn(Object *obj) 477 { 478 CPUState *cs = CPU(obj); 479 ARMCPU *cpu = ARM_CPU(obj); 480 static bool inited; 481 482 cs->env_ptr = &cpu->env; 483 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, 484 g_free, g_free); 485 486 #ifndef CONFIG_USER_ONLY 487 /* Our inbound IRQ and FIQ lines */ 488 if (kvm_enabled()) { 489 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 490 * the same interface as non-KVM CPUs. 491 */ 492 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 493 } else { 494 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 495 } 496 497 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 498 arm_gt_ptimer_cb, cpu); 499 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 500 arm_gt_vtimer_cb, cpu); 501 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 502 arm_gt_htimer_cb, cpu); 503 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 504 arm_gt_stimer_cb, cpu); 505 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 506 ARRAY_SIZE(cpu->gt_timer_outputs)); 507 508 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 509 "gicv3-maintenance-interrupt", 1); 510 #endif 511 512 /* DTB consumers generally don't in fact care what the 'compatible' 513 * string is, so always provide some string and trust that a hypothetical 514 * picky DTB consumer will also provide a helpful error message. 515 */ 516 cpu->dtb_compatible = "qemu,unknown"; 517 cpu->psci_version = 1; /* By default assume PSCI v0.1 */ 518 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 519 520 if (tcg_enabled()) { 521 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ 522 if (!inited) { 523 inited = true; 524 arm_translate_init(); 525 } 526 } 527 } 528 529 static Property arm_cpu_reset_cbar_property = 530 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 531 532 static Property arm_cpu_reset_hivecs_property = 533 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 534 535 static Property arm_cpu_rvbar_property = 536 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); 537 538 static Property arm_cpu_has_el2_property = 539 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 540 541 static Property arm_cpu_has_el3_property = 542 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 543 544 /* use property name "pmu" to match other archs and virt tools */ 545 static Property arm_cpu_has_pmu_property = 546 DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true); 547 548 static Property arm_cpu_has_mpu_property = 549 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 550 551 static Property arm_cpu_pmsav7_dregion_property = 552 DEFINE_PROP_UINT32("pmsav7-dregion", ARMCPU, pmsav7_dregion, 16); 553 554 static void arm_cpu_post_init(Object *obj) 555 { 556 ARMCPU *cpu = ARM_CPU(obj); 557 558 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 559 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 560 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, 561 &error_abort); 562 } 563 564 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 565 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property, 566 &error_abort); 567 } 568 569 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 570 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property, 571 &error_abort); 572 } 573 574 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 575 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 576 * prevent "has_el3" from existing on CPUs which cannot support EL3. 577 */ 578 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property, 579 &error_abort); 580 581 #ifndef CONFIG_USER_ONLY 582 object_property_add_link(obj, "secure-memory", 583 TYPE_MEMORY_REGION, 584 (Object **)&cpu->secure_memory, 585 qdev_prop_allow_set_link_before_realize, 586 OBJ_PROP_LINK_UNREF_ON_RELEASE, 587 &error_abort); 588 #endif 589 } 590 591 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 592 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property, 593 &error_abort); 594 } 595 596 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 597 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property, 598 &error_abort); 599 } 600 601 if (arm_feature(&cpu->env, ARM_FEATURE_MPU)) { 602 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, 603 &error_abort); 604 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 605 qdev_property_add_static(DEVICE(obj), 606 &arm_cpu_pmsav7_dregion_property, 607 &error_abort); 608 } 609 } 610 611 } 612 613 static void arm_cpu_finalizefn(Object *obj) 614 { 615 ARMCPU *cpu = ARM_CPU(obj); 616 g_hash_table_destroy(cpu->cp_regs); 617 } 618 619 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 620 { 621 CPUState *cs = CPU(dev); 622 ARMCPU *cpu = ARM_CPU(dev); 623 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 624 CPUARMState *env = &cpu->env; 625 int pagebits; 626 Error *local_err = NULL; 627 628 cpu_exec_realizefn(cs, &local_err); 629 if (local_err != NULL) { 630 error_propagate(errp, local_err); 631 return; 632 } 633 634 /* Some features automatically imply others: */ 635 if (arm_feature(env, ARM_FEATURE_V8)) { 636 set_feature(env, ARM_FEATURE_V7); 637 set_feature(env, ARM_FEATURE_ARM_DIV); 638 set_feature(env, ARM_FEATURE_LPAE); 639 } 640 if (arm_feature(env, ARM_FEATURE_V7)) { 641 set_feature(env, ARM_FEATURE_VAPA); 642 set_feature(env, ARM_FEATURE_THUMB2); 643 set_feature(env, ARM_FEATURE_MPIDR); 644 if (!arm_feature(env, ARM_FEATURE_M)) { 645 set_feature(env, ARM_FEATURE_V6K); 646 } else { 647 set_feature(env, ARM_FEATURE_V6); 648 } 649 650 /* Always define VBAR for V7 CPUs even if it doesn't exist in 651 * non-EL3 configs. This is needed by some legacy boards. 652 */ 653 set_feature(env, ARM_FEATURE_VBAR); 654 } 655 if (arm_feature(env, ARM_FEATURE_V6K)) { 656 set_feature(env, ARM_FEATURE_V6); 657 set_feature(env, ARM_FEATURE_MVFR); 658 } 659 if (arm_feature(env, ARM_FEATURE_V6)) { 660 set_feature(env, ARM_FEATURE_V5); 661 if (!arm_feature(env, ARM_FEATURE_M)) { 662 set_feature(env, ARM_FEATURE_AUXCR); 663 } 664 } 665 if (arm_feature(env, ARM_FEATURE_V5)) { 666 set_feature(env, ARM_FEATURE_V4T); 667 } 668 if (arm_feature(env, ARM_FEATURE_M)) { 669 set_feature(env, ARM_FEATURE_THUMB_DIV); 670 } 671 if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { 672 set_feature(env, ARM_FEATURE_THUMB_DIV); 673 } 674 if (arm_feature(env, ARM_FEATURE_VFP4)) { 675 set_feature(env, ARM_FEATURE_VFP3); 676 set_feature(env, ARM_FEATURE_VFP_FP16); 677 } 678 if (arm_feature(env, ARM_FEATURE_VFP3)) { 679 set_feature(env, ARM_FEATURE_VFP); 680 } 681 if (arm_feature(env, ARM_FEATURE_LPAE)) { 682 set_feature(env, ARM_FEATURE_V7MP); 683 set_feature(env, ARM_FEATURE_PXN); 684 } 685 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 686 set_feature(env, ARM_FEATURE_CBAR); 687 } 688 if (arm_feature(env, ARM_FEATURE_THUMB2) && 689 !arm_feature(env, ARM_FEATURE_M)) { 690 set_feature(env, ARM_FEATURE_THUMB_DSP); 691 } 692 693 if (arm_feature(env, ARM_FEATURE_V7) && 694 !arm_feature(env, ARM_FEATURE_M) && 695 !arm_feature(env, ARM_FEATURE_MPU)) { 696 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 697 * can use 4K pages. 698 */ 699 pagebits = 12; 700 } else { 701 /* For CPUs which might have tiny 1K pages, or which have an 702 * MPU and might have small region sizes, stick with 1K pages. 703 */ 704 pagebits = 10; 705 } 706 if (!set_preferred_target_page_bits(pagebits)) { 707 /* This can only ever happen for hotplugging a CPU, or if 708 * the board code incorrectly creates a CPU which it has 709 * promised via minimum_page_size that it will not. 710 */ 711 error_setg(errp, "This CPU requires a smaller page size than the " 712 "system is using"); 713 return; 714 } 715 716 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 717 * We don't support setting cluster ID ([16..23]) (known as Aff2 718 * in later ARM ARM versions), or any of the higher affinity level fields, 719 * so these bits always RAZ. 720 */ 721 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 722 uint32_t Aff1 = cs->cpu_index / ARM_DEFAULT_CPUS_PER_CLUSTER; 723 uint32_t Aff0 = cs->cpu_index % ARM_DEFAULT_CPUS_PER_CLUSTER; 724 cpu->mp_affinity = (Aff1 << ARM_AFF1_SHIFT) | Aff0; 725 } 726 727 if (cpu->reset_hivecs) { 728 cpu->reset_sctlr |= (1 << 13); 729 } 730 731 if (!cpu->has_el3) { 732 /* If the has_el3 CPU property is disabled then we need to disable the 733 * feature. 734 */ 735 unset_feature(env, ARM_FEATURE_EL3); 736 737 /* Disable the security extension feature bits in the processor feature 738 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. 739 */ 740 cpu->id_pfr1 &= ~0xf0; 741 cpu->id_aa64pfr0 &= ~0xf000; 742 } 743 744 if (!cpu->has_el2) { 745 unset_feature(env, ARM_FEATURE_EL2); 746 } 747 748 if (!cpu->has_pmu || !kvm_enabled()) { 749 cpu->has_pmu = false; 750 unset_feature(env, ARM_FEATURE_PMU); 751 } 752 753 if (!arm_feature(env, ARM_FEATURE_EL2)) { 754 /* Disable the hypervisor feature bits in the processor feature 755 * registers if we don't have EL2. These are id_pfr1[15:12] and 756 * id_aa64pfr0_el1[11:8]. 757 */ 758 cpu->id_aa64pfr0 &= ~0xf00; 759 cpu->id_pfr1 &= ~0xf000; 760 } 761 762 if (!cpu->has_mpu) { 763 unset_feature(env, ARM_FEATURE_MPU); 764 } 765 766 if (arm_feature(env, ARM_FEATURE_MPU) && 767 arm_feature(env, ARM_FEATURE_V7)) { 768 uint32_t nr = cpu->pmsav7_dregion; 769 770 if (nr > 0xff) { 771 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 772 return; 773 } 774 775 if (nr) { 776 env->pmsav7.drbar = g_new0(uint32_t, nr); 777 env->pmsav7.drsr = g_new0(uint32_t, nr); 778 env->pmsav7.dracr = g_new0(uint32_t, nr); 779 } 780 } 781 782 if (arm_feature(env, ARM_FEATURE_EL3)) { 783 set_feature(env, ARM_FEATURE_VBAR); 784 } 785 786 register_cp_regs_for_features(cpu); 787 arm_cpu_register_gdb_regs_for_features(cpu); 788 789 init_cpreg_list(cpu); 790 791 #ifndef CONFIG_USER_ONLY 792 if (cpu->has_el3) { 793 cs->num_ases = 2; 794 } else { 795 cs->num_ases = 1; 796 } 797 798 if (cpu->has_el3) { 799 AddressSpace *as; 800 801 if (!cpu->secure_memory) { 802 cpu->secure_memory = cs->memory; 803 } 804 as = address_space_init_shareable(cpu->secure_memory, 805 "cpu-secure-memory"); 806 cpu_address_space_init(cs, as, ARMASIdx_S); 807 } 808 cpu_address_space_init(cs, 809 address_space_init_shareable(cs->memory, 810 "cpu-memory"), 811 ARMASIdx_NS); 812 #endif 813 814 qemu_init_vcpu(cs); 815 cpu_reset(cs); 816 817 acc->parent_realize(dev, errp); 818 } 819 820 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 821 { 822 ObjectClass *oc; 823 char *typename; 824 char **cpuname; 825 826 if (!cpu_model) { 827 return NULL; 828 } 829 830 cpuname = g_strsplit(cpu_model, ",", 1); 831 typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpuname[0]); 832 oc = object_class_by_name(typename); 833 g_strfreev(cpuname); 834 g_free(typename); 835 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 836 object_class_is_abstract(oc)) { 837 return NULL; 838 } 839 return oc; 840 } 841 842 /* CPU models. These are not needed for the AArch64 linux-user build. */ 843 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 844 845 static void arm926_initfn(Object *obj) 846 { 847 ARMCPU *cpu = ARM_CPU(obj); 848 849 cpu->dtb_compatible = "arm,arm926"; 850 set_feature(&cpu->env, ARM_FEATURE_V5); 851 set_feature(&cpu->env, ARM_FEATURE_VFP); 852 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 853 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 854 cpu->midr = 0x41069265; 855 cpu->reset_fpsid = 0x41011090; 856 cpu->ctr = 0x1dd20d2; 857 cpu->reset_sctlr = 0x00090078; 858 } 859 860 static void arm946_initfn(Object *obj) 861 { 862 ARMCPU *cpu = ARM_CPU(obj); 863 864 cpu->dtb_compatible = "arm,arm946"; 865 set_feature(&cpu->env, ARM_FEATURE_V5); 866 set_feature(&cpu->env, ARM_FEATURE_MPU); 867 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 868 cpu->midr = 0x41059461; 869 cpu->ctr = 0x0f004006; 870 cpu->reset_sctlr = 0x00000078; 871 } 872 873 static void arm1026_initfn(Object *obj) 874 { 875 ARMCPU *cpu = ARM_CPU(obj); 876 877 cpu->dtb_compatible = "arm,arm1026"; 878 set_feature(&cpu->env, ARM_FEATURE_V5); 879 set_feature(&cpu->env, ARM_FEATURE_VFP); 880 set_feature(&cpu->env, ARM_FEATURE_AUXCR); 881 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 882 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 883 cpu->midr = 0x4106a262; 884 cpu->reset_fpsid = 0x410110a0; 885 cpu->ctr = 0x1dd20d2; 886 cpu->reset_sctlr = 0x00090078; 887 cpu->reset_auxcr = 1; 888 { 889 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ 890 ARMCPRegInfo ifar = { 891 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, 892 .access = PL1_RW, 893 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), 894 .resetvalue = 0 895 }; 896 define_one_arm_cp_reg(cpu, &ifar); 897 } 898 } 899 900 static void arm1136_r2_initfn(Object *obj) 901 { 902 ARMCPU *cpu = ARM_CPU(obj); 903 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an 904 * older core than plain "arm1136". In particular this does not 905 * have the v6K features. 906 * These ID register values are correct for 1136 but may be wrong 907 * for 1136_r2 (in particular r0p2 does not actually implement most 908 * of the ID registers). 909 */ 910 911 cpu->dtb_compatible = "arm,arm1136"; 912 set_feature(&cpu->env, ARM_FEATURE_V6); 913 set_feature(&cpu->env, ARM_FEATURE_VFP); 914 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 915 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 916 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 917 cpu->midr = 0x4107b362; 918 cpu->reset_fpsid = 0x410120b4; 919 cpu->mvfr0 = 0x11111111; 920 cpu->mvfr1 = 0x00000000; 921 cpu->ctr = 0x1dd20d2; 922 cpu->reset_sctlr = 0x00050078; 923 cpu->id_pfr0 = 0x111; 924 cpu->id_pfr1 = 0x1; 925 cpu->id_dfr0 = 0x2; 926 cpu->id_afr0 = 0x3; 927 cpu->id_mmfr0 = 0x01130003; 928 cpu->id_mmfr1 = 0x10030302; 929 cpu->id_mmfr2 = 0x01222110; 930 cpu->id_isar0 = 0x00140011; 931 cpu->id_isar1 = 0x12002111; 932 cpu->id_isar2 = 0x11231111; 933 cpu->id_isar3 = 0x01102131; 934 cpu->id_isar4 = 0x141; 935 cpu->reset_auxcr = 7; 936 } 937 938 static void arm1136_initfn(Object *obj) 939 { 940 ARMCPU *cpu = ARM_CPU(obj); 941 942 cpu->dtb_compatible = "arm,arm1136"; 943 set_feature(&cpu->env, ARM_FEATURE_V6K); 944 set_feature(&cpu->env, ARM_FEATURE_V6); 945 set_feature(&cpu->env, ARM_FEATURE_VFP); 946 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 947 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 948 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 949 cpu->midr = 0x4117b363; 950 cpu->reset_fpsid = 0x410120b4; 951 cpu->mvfr0 = 0x11111111; 952 cpu->mvfr1 = 0x00000000; 953 cpu->ctr = 0x1dd20d2; 954 cpu->reset_sctlr = 0x00050078; 955 cpu->id_pfr0 = 0x111; 956 cpu->id_pfr1 = 0x1; 957 cpu->id_dfr0 = 0x2; 958 cpu->id_afr0 = 0x3; 959 cpu->id_mmfr0 = 0x01130003; 960 cpu->id_mmfr1 = 0x10030302; 961 cpu->id_mmfr2 = 0x01222110; 962 cpu->id_isar0 = 0x00140011; 963 cpu->id_isar1 = 0x12002111; 964 cpu->id_isar2 = 0x11231111; 965 cpu->id_isar3 = 0x01102131; 966 cpu->id_isar4 = 0x141; 967 cpu->reset_auxcr = 7; 968 } 969 970 static void arm1176_initfn(Object *obj) 971 { 972 ARMCPU *cpu = ARM_CPU(obj); 973 974 cpu->dtb_compatible = "arm,arm1176"; 975 set_feature(&cpu->env, ARM_FEATURE_V6K); 976 set_feature(&cpu->env, ARM_FEATURE_VFP); 977 set_feature(&cpu->env, ARM_FEATURE_VAPA); 978 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 979 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 980 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 981 set_feature(&cpu->env, ARM_FEATURE_EL3); 982 cpu->midr = 0x410fb767; 983 cpu->reset_fpsid = 0x410120b5; 984 cpu->mvfr0 = 0x11111111; 985 cpu->mvfr1 = 0x00000000; 986 cpu->ctr = 0x1dd20d2; 987 cpu->reset_sctlr = 0x00050078; 988 cpu->id_pfr0 = 0x111; 989 cpu->id_pfr1 = 0x11; 990 cpu->id_dfr0 = 0x33; 991 cpu->id_afr0 = 0; 992 cpu->id_mmfr0 = 0x01130003; 993 cpu->id_mmfr1 = 0x10030302; 994 cpu->id_mmfr2 = 0x01222100; 995 cpu->id_isar0 = 0x0140011; 996 cpu->id_isar1 = 0x12002111; 997 cpu->id_isar2 = 0x11231121; 998 cpu->id_isar3 = 0x01102131; 999 cpu->id_isar4 = 0x01141; 1000 cpu->reset_auxcr = 7; 1001 } 1002 1003 static void arm11mpcore_initfn(Object *obj) 1004 { 1005 ARMCPU *cpu = ARM_CPU(obj); 1006 1007 cpu->dtb_compatible = "arm,arm11mpcore"; 1008 set_feature(&cpu->env, ARM_FEATURE_V6K); 1009 set_feature(&cpu->env, ARM_FEATURE_VFP); 1010 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1011 set_feature(&cpu->env, ARM_FEATURE_MPIDR); 1012 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1013 cpu->midr = 0x410fb022; 1014 cpu->reset_fpsid = 0x410120b4; 1015 cpu->mvfr0 = 0x11111111; 1016 cpu->mvfr1 = 0x00000000; 1017 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ 1018 cpu->id_pfr0 = 0x111; 1019 cpu->id_pfr1 = 0x1; 1020 cpu->id_dfr0 = 0; 1021 cpu->id_afr0 = 0x2; 1022 cpu->id_mmfr0 = 0x01100103; 1023 cpu->id_mmfr1 = 0x10020302; 1024 cpu->id_mmfr2 = 0x01222000; 1025 cpu->id_isar0 = 0x00100011; 1026 cpu->id_isar1 = 0x12002111; 1027 cpu->id_isar2 = 0x11221011; 1028 cpu->id_isar3 = 0x01102131; 1029 cpu->id_isar4 = 0x141; 1030 cpu->reset_auxcr = 1; 1031 } 1032 1033 static void cortex_m3_initfn(Object *obj) 1034 { 1035 ARMCPU *cpu = ARM_CPU(obj); 1036 set_feature(&cpu->env, ARM_FEATURE_V7); 1037 set_feature(&cpu->env, ARM_FEATURE_M); 1038 cpu->midr = 0x410fc231; 1039 } 1040 1041 static void cortex_m4_initfn(Object *obj) 1042 { 1043 ARMCPU *cpu = ARM_CPU(obj); 1044 1045 set_feature(&cpu->env, ARM_FEATURE_V7); 1046 set_feature(&cpu->env, ARM_FEATURE_M); 1047 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 1048 cpu->midr = 0x410fc240; /* r0p0 */ 1049 } 1050 static void arm_v7m_class_init(ObjectClass *oc, void *data) 1051 { 1052 CPUClass *cc = CPU_CLASS(oc); 1053 1054 #ifndef CONFIG_USER_ONLY 1055 cc->do_interrupt = arm_v7m_cpu_do_interrupt; 1056 #endif 1057 1058 cc->do_unassigned_access = arm_v7m_unassigned_access; 1059 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; 1060 } 1061 1062 static const ARMCPRegInfo cortexr5_cp_reginfo[] = { 1063 /* Dummy the TCM region regs for the moment */ 1064 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, 1065 .access = PL1_RW, .type = ARM_CP_CONST }, 1066 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, 1067 .access = PL1_RW, .type = ARM_CP_CONST }, 1068 REGINFO_SENTINEL 1069 }; 1070 1071 static void cortex_r5_initfn(Object *obj) 1072 { 1073 ARMCPU *cpu = ARM_CPU(obj); 1074 1075 set_feature(&cpu->env, ARM_FEATURE_V7); 1076 set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV); 1077 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1078 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1079 set_feature(&cpu->env, ARM_FEATURE_MPU); 1080 cpu->midr = 0x411fc153; /* r1p3 */ 1081 cpu->id_pfr0 = 0x0131; 1082 cpu->id_pfr1 = 0x001; 1083 cpu->id_dfr0 = 0x010400; 1084 cpu->id_afr0 = 0x0; 1085 cpu->id_mmfr0 = 0x0210030; 1086 cpu->id_mmfr1 = 0x00000000; 1087 cpu->id_mmfr2 = 0x01200000; 1088 cpu->id_mmfr3 = 0x0211; 1089 cpu->id_isar0 = 0x2101111; 1090 cpu->id_isar1 = 0x13112111; 1091 cpu->id_isar2 = 0x21232141; 1092 cpu->id_isar3 = 0x01112131; 1093 cpu->id_isar4 = 0x0010142; 1094 cpu->id_isar5 = 0x0; 1095 cpu->mp_is_up = true; 1096 define_arm_cp_regs(cpu, cortexr5_cp_reginfo); 1097 } 1098 1099 static const ARMCPRegInfo cortexa8_cp_reginfo[] = { 1100 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, 1101 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1102 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1103 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1104 REGINFO_SENTINEL 1105 }; 1106 1107 static void cortex_a8_initfn(Object *obj) 1108 { 1109 ARMCPU *cpu = ARM_CPU(obj); 1110 1111 cpu->dtb_compatible = "arm,cortex-a8"; 1112 set_feature(&cpu->env, ARM_FEATURE_V7); 1113 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1114 set_feature(&cpu->env, ARM_FEATURE_NEON); 1115 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1116 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1117 set_feature(&cpu->env, ARM_FEATURE_EL3); 1118 cpu->midr = 0x410fc080; 1119 cpu->reset_fpsid = 0x410330c0; 1120 cpu->mvfr0 = 0x11110222; 1121 cpu->mvfr1 = 0x00011111; 1122 cpu->ctr = 0x82048004; 1123 cpu->reset_sctlr = 0x00c50078; 1124 cpu->id_pfr0 = 0x1031; 1125 cpu->id_pfr1 = 0x11; 1126 cpu->id_dfr0 = 0x400; 1127 cpu->id_afr0 = 0; 1128 cpu->id_mmfr0 = 0x31100003; 1129 cpu->id_mmfr1 = 0x20000000; 1130 cpu->id_mmfr2 = 0x01202000; 1131 cpu->id_mmfr3 = 0x11; 1132 cpu->id_isar0 = 0x00101111; 1133 cpu->id_isar1 = 0x12112111; 1134 cpu->id_isar2 = 0x21232031; 1135 cpu->id_isar3 = 0x11112131; 1136 cpu->id_isar4 = 0x00111142; 1137 cpu->dbgdidr = 0x15141000; 1138 cpu->clidr = (1 << 27) | (2 << 24) | 3; 1139 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ 1140 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ 1141 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ 1142 cpu->reset_auxcr = 2; 1143 define_arm_cp_regs(cpu, cortexa8_cp_reginfo); 1144 } 1145 1146 static const ARMCPRegInfo cortexa9_cp_reginfo[] = { 1147 /* power_control should be set to maximum latency. Again, 1148 * default to 0 and set by private hook 1149 */ 1150 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 1151 .access = PL1_RW, .resetvalue = 0, 1152 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, 1153 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, 1154 .access = PL1_RW, .resetvalue = 0, 1155 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, 1156 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, 1157 .access = PL1_RW, .resetvalue = 0, 1158 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, 1159 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 1160 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1161 /* TLB lockdown control */ 1162 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, 1163 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1164 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, 1165 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1166 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, 1167 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1168 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, 1169 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1170 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, 1171 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1172 REGINFO_SENTINEL 1173 }; 1174 1175 static void cortex_a9_initfn(Object *obj) 1176 { 1177 ARMCPU *cpu = ARM_CPU(obj); 1178 1179 cpu->dtb_compatible = "arm,cortex-a9"; 1180 set_feature(&cpu->env, ARM_FEATURE_V7); 1181 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1182 set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); 1183 set_feature(&cpu->env, ARM_FEATURE_NEON); 1184 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1185 set_feature(&cpu->env, ARM_FEATURE_EL3); 1186 /* Note that A9 supports the MP extensions even for 1187 * A9UP and single-core A9MP (which are both different 1188 * and valid configurations; we don't model A9UP). 1189 */ 1190 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1191 set_feature(&cpu->env, ARM_FEATURE_CBAR); 1192 cpu->midr = 0x410fc090; 1193 cpu->reset_fpsid = 0x41033090; 1194 cpu->mvfr0 = 0x11110222; 1195 cpu->mvfr1 = 0x01111111; 1196 cpu->ctr = 0x80038003; 1197 cpu->reset_sctlr = 0x00c50078; 1198 cpu->id_pfr0 = 0x1031; 1199 cpu->id_pfr1 = 0x11; 1200 cpu->id_dfr0 = 0x000; 1201 cpu->id_afr0 = 0; 1202 cpu->id_mmfr0 = 0x00100103; 1203 cpu->id_mmfr1 = 0x20000000; 1204 cpu->id_mmfr2 = 0x01230000; 1205 cpu->id_mmfr3 = 0x00002111; 1206 cpu->id_isar0 = 0x00101111; 1207 cpu->id_isar1 = 0x13112111; 1208 cpu->id_isar2 = 0x21232041; 1209 cpu->id_isar3 = 0x11112131; 1210 cpu->id_isar4 = 0x00111142; 1211 cpu->dbgdidr = 0x35141000; 1212 cpu->clidr = (1 << 27) | (1 << 24) | 3; 1213 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ 1214 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ 1215 define_arm_cp_regs(cpu, cortexa9_cp_reginfo); 1216 } 1217 1218 #ifndef CONFIG_USER_ONLY 1219 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1220 { 1221 /* Linux wants the number of processors from here. 1222 * Might as well set the interrupt-controller bit too. 1223 */ 1224 return ((smp_cpus - 1) << 24) | (1 << 23); 1225 } 1226 #endif 1227 1228 static const ARMCPRegInfo cortexa15_cp_reginfo[] = { 1229 #ifndef CONFIG_USER_ONLY 1230 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1231 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, 1232 .writefn = arm_cp_write_ignore, }, 1233 #endif 1234 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, 1235 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1236 REGINFO_SENTINEL 1237 }; 1238 1239 static void cortex_a7_initfn(Object *obj) 1240 { 1241 ARMCPU *cpu = ARM_CPU(obj); 1242 1243 cpu->dtb_compatible = "arm,cortex-a7"; 1244 set_feature(&cpu->env, ARM_FEATURE_V7); 1245 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1246 set_feature(&cpu->env, ARM_FEATURE_NEON); 1247 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1248 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1249 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1250 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1251 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1252 set_feature(&cpu->env, ARM_FEATURE_LPAE); 1253 set_feature(&cpu->env, ARM_FEATURE_EL3); 1254 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; 1255 cpu->midr = 0x410fc075; 1256 cpu->reset_fpsid = 0x41023075; 1257 cpu->mvfr0 = 0x10110222; 1258 cpu->mvfr1 = 0x11111111; 1259 cpu->ctr = 0x84448003; 1260 cpu->reset_sctlr = 0x00c50078; 1261 cpu->id_pfr0 = 0x00001131; 1262 cpu->id_pfr1 = 0x00011011; 1263 cpu->id_dfr0 = 0x02010555; 1264 cpu->pmceid0 = 0x00000000; 1265 cpu->pmceid1 = 0x00000000; 1266 cpu->id_afr0 = 0x00000000; 1267 cpu->id_mmfr0 = 0x10101105; 1268 cpu->id_mmfr1 = 0x40000000; 1269 cpu->id_mmfr2 = 0x01240000; 1270 cpu->id_mmfr3 = 0x02102211; 1271 cpu->id_isar0 = 0x01101110; 1272 cpu->id_isar1 = 0x13112111; 1273 cpu->id_isar2 = 0x21232041; 1274 cpu->id_isar3 = 0x11112131; 1275 cpu->id_isar4 = 0x10011142; 1276 cpu->dbgdidr = 0x3515f005; 1277 cpu->clidr = 0x0a200023; 1278 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1279 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1280 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1281 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ 1282 } 1283 1284 static void cortex_a15_initfn(Object *obj) 1285 { 1286 ARMCPU *cpu = ARM_CPU(obj); 1287 1288 cpu->dtb_compatible = "arm,cortex-a15"; 1289 set_feature(&cpu->env, ARM_FEATURE_V7); 1290 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1291 set_feature(&cpu->env, ARM_FEATURE_NEON); 1292 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1293 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1294 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1295 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1296 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1297 set_feature(&cpu->env, ARM_FEATURE_LPAE); 1298 set_feature(&cpu->env, ARM_FEATURE_EL3); 1299 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; 1300 cpu->midr = 0x412fc0f1; 1301 cpu->reset_fpsid = 0x410430f0; 1302 cpu->mvfr0 = 0x10110222; 1303 cpu->mvfr1 = 0x11111111; 1304 cpu->ctr = 0x8444c004; 1305 cpu->reset_sctlr = 0x00c50078; 1306 cpu->id_pfr0 = 0x00001131; 1307 cpu->id_pfr1 = 0x00011011; 1308 cpu->id_dfr0 = 0x02010555; 1309 cpu->pmceid0 = 0x0000000; 1310 cpu->pmceid1 = 0x00000000; 1311 cpu->id_afr0 = 0x00000000; 1312 cpu->id_mmfr0 = 0x10201105; 1313 cpu->id_mmfr1 = 0x20000000; 1314 cpu->id_mmfr2 = 0x01240000; 1315 cpu->id_mmfr3 = 0x02102211; 1316 cpu->id_isar0 = 0x02101110; 1317 cpu->id_isar1 = 0x13112111; 1318 cpu->id_isar2 = 0x21232041; 1319 cpu->id_isar3 = 0x11112131; 1320 cpu->id_isar4 = 0x10011142; 1321 cpu->dbgdidr = 0x3515f021; 1322 cpu->clidr = 0x0a200023; 1323 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1324 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1325 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1326 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); 1327 } 1328 1329 static void ti925t_initfn(Object *obj) 1330 { 1331 ARMCPU *cpu = ARM_CPU(obj); 1332 set_feature(&cpu->env, ARM_FEATURE_V4T); 1333 set_feature(&cpu->env, ARM_FEATURE_OMAPCP); 1334 cpu->midr = ARM_CPUID_TI925T; 1335 cpu->ctr = 0x5109149; 1336 cpu->reset_sctlr = 0x00000070; 1337 } 1338 1339 static void sa1100_initfn(Object *obj) 1340 { 1341 ARMCPU *cpu = ARM_CPU(obj); 1342 1343 cpu->dtb_compatible = "intel,sa1100"; 1344 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1345 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1346 cpu->midr = 0x4401A11B; 1347 cpu->reset_sctlr = 0x00000070; 1348 } 1349 1350 static void sa1110_initfn(Object *obj) 1351 { 1352 ARMCPU *cpu = ARM_CPU(obj); 1353 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1354 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1355 cpu->midr = 0x6901B119; 1356 cpu->reset_sctlr = 0x00000070; 1357 } 1358 1359 static void pxa250_initfn(Object *obj) 1360 { 1361 ARMCPU *cpu = ARM_CPU(obj); 1362 1363 cpu->dtb_compatible = "marvell,xscale"; 1364 set_feature(&cpu->env, ARM_FEATURE_V5); 1365 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1366 cpu->midr = 0x69052100; 1367 cpu->ctr = 0xd172172; 1368 cpu->reset_sctlr = 0x00000078; 1369 } 1370 1371 static void pxa255_initfn(Object *obj) 1372 { 1373 ARMCPU *cpu = ARM_CPU(obj); 1374 1375 cpu->dtb_compatible = "marvell,xscale"; 1376 set_feature(&cpu->env, ARM_FEATURE_V5); 1377 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1378 cpu->midr = 0x69052d00; 1379 cpu->ctr = 0xd172172; 1380 cpu->reset_sctlr = 0x00000078; 1381 } 1382 1383 static void pxa260_initfn(Object *obj) 1384 { 1385 ARMCPU *cpu = ARM_CPU(obj); 1386 1387 cpu->dtb_compatible = "marvell,xscale"; 1388 set_feature(&cpu->env, ARM_FEATURE_V5); 1389 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1390 cpu->midr = 0x69052903; 1391 cpu->ctr = 0xd172172; 1392 cpu->reset_sctlr = 0x00000078; 1393 } 1394 1395 static void pxa261_initfn(Object *obj) 1396 { 1397 ARMCPU *cpu = ARM_CPU(obj); 1398 1399 cpu->dtb_compatible = "marvell,xscale"; 1400 set_feature(&cpu->env, ARM_FEATURE_V5); 1401 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1402 cpu->midr = 0x69052d05; 1403 cpu->ctr = 0xd172172; 1404 cpu->reset_sctlr = 0x00000078; 1405 } 1406 1407 static void pxa262_initfn(Object *obj) 1408 { 1409 ARMCPU *cpu = ARM_CPU(obj); 1410 1411 cpu->dtb_compatible = "marvell,xscale"; 1412 set_feature(&cpu->env, ARM_FEATURE_V5); 1413 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1414 cpu->midr = 0x69052d06; 1415 cpu->ctr = 0xd172172; 1416 cpu->reset_sctlr = 0x00000078; 1417 } 1418 1419 static void pxa270a0_initfn(Object *obj) 1420 { 1421 ARMCPU *cpu = ARM_CPU(obj); 1422 1423 cpu->dtb_compatible = "marvell,xscale"; 1424 set_feature(&cpu->env, ARM_FEATURE_V5); 1425 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1426 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1427 cpu->midr = 0x69054110; 1428 cpu->ctr = 0xd172172; 1429 cpu->reset_sctlr = 0x00000078; 1430 } 1431 1432 static void pxa270a1_initfn(Object *obj) 1433 { 1434 ARMCPU *cpu = ARM_CPU(obj); 1435 1436 cpu->dtb_compatible = "marvell,xscale"; 1437 set_feature(&cpu->env, ARM_FEATURE_V5); 1438 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1439 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1440 cpu->midr = 0x69054111; 1441 cpu->ctr = 0xd172172; 1442 cpu->reset_sctlr = 0x00000078; 1443 } 1444 1445 static void pxa270b0_initfn(Object *obj) 1446 { 1447 ARMCPU *cpu = ARM_CPU(obj); 1448 1449 cpu->dtb_compatible = "marvell,xscale"; 1450 set_feature(&cpu->env, ARM_FEATURE_V5); 1451 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1452 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1453 cpu->midr = 0x69054112; 1454 cpu->ctr = 0xd172172; 1455 cpu->reset_sctlr = 0x00000078; 1456 } 1457 1458 static void pxa270b1_initfn(Object *obj) 1459 { 1460 ARMCPU *cpu = ARM_CPU(obj); 1461 1462 cpu->dtb_compatible = "marvell,xscale"; 1463 set_feature(&cpu->env, ARM_FEATURE_V5); 1464 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1465 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1466 cpu->midr = 0x69054113; 1467 cpu->ctr = 0xd172172; 1468 cpu->reset_sctlr = 0x00000078; 1469 } 1470 1471 static void pxa270c0_initfn(Object *obj) 1472 { 1473 ARMCPU *cpu = ARM_CPU(obj); 1474 1475 cpu->dtb_compatible = "marvell,xscale"; 1476 set_feature(&cpu->env, ARM_FEATURE_V5); 1477 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1478 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1479 cpu->midr = 0x69054114; 1480 cpu->ctr = 0xd172172; 1481 cpu->reset_sctlr = 0x00000078; 1482 } 1483 1484 static void pxa270c5_initfn(Object *obj) 1485 { 1486 ARMCPU *cpu = ARM_CPU(obj); 1487 1488 cpu->dtb_compatible = "marvell,xscale"; 1489 set_feature(&cpu->env, ARM_FEATURE_V5); 1490 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1491 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1492 cpu->midr = 0x69054117; 1493 cpu->ctr = 0xd172172; 1494 cpu->reset_sctlr = 0x00000078; 1495 } 1496 1497 #ifdef CONFIG_USER_ONLY 1498 static void arm_any_initfn(Object *obj) 1499 { 1500 ARMCPU *cpu = ARM_CPU(obj); 1501 set_feature(&cpu->env, ARM_FEATURE_V8); 1502 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1503 set_feature(&cpu->env, ARM_FEATURE_NEON); 1504 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1505 set_feature(&cpu->env, ARM_FEATURE_V8_AES); 1506 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); 1507 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); 1508 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); 1509 set_feature(&cpu->env, ARM_FEATURE_CRC); 1510 cpu->midr = 0xffffffff; 1511 } 1512 #endif 1513 1514 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ 1515 1516 typedef struct ARMCPUInfo { 1517 const char *name; 1518 void (*initfn)(Object *obj); 1519 void (*class_init)(ObjectClass *oc, void *data); 1520 } ARMCPUInfo; 1521 1522 static const ARMCPUInfo arm_cpus[] = { 1523 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 1524 { .name = "arm926", .initfn = arm926_initfn }, 1525 { .name = "arm946", .initfn = arm946_initfn }, 1526 { .name = "arm1026", .initfn = arm1026_initfn }, 1527 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an 1528 * older core than plain "arm1136". In particular this does not 1529 * have the v6K features. 1530 */ 1531 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, 1532 { .name = "arm1136", .initfn = arm1136_initfn }, 1533 { .name = "arm1176", .initfn = arm1176_initfn }, 1534 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, 1535 { .name = "cortex-m3", .initfn = cortex_m3_initfn, 1536 .class_init = arm_v7m_class_init }, 1537 { .name = "cortex-m4", .initfn = cortex_m4_initfn, 1538 .class_init = arm_v7m_class_init }, 1539 { .name = "cortex-r5", .initfn = cortex_r5_initfn }, 1540 { .name = "cortex-a7", .initfn = cortex_a7_initfn }, 1541 { .name = "cortex-a8", .initfn = cortex_a8_initfn }, 1542 { .name = "cortex-a9", .initfn = cortex_a9_initfn }, 1543 { .name = "cortex-a15", .initfn = cortex_a15_initfn }, 1544 { .name = "ti925t", .initfn = ti925t_initfn }, 1545 { .name = "sa1100", .initfn = sa1100_initfn }, 1546 { .name = "sa1110", .initfn = sa1110_initfn }, 1547 { .name = "pxa250", .initfn = pxa250_initfn }, 1548 { .name = "pxa255", .initfn = pxa255_initfn }, 1549 { .name = "pxa260", .initfn = pxa260_initfn }, 1550 { .name = "pxa261", .initfn = pxa261_initfn }, 1551 { .name = "pxa262", .initfn = pxa262_initfn }, 1552 /* "pxa270" is an alias for "pxa270-a0" */ 1553 { .name = "pxa270", .initfn = pxa270a0_initfn }, 1554 { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, 1555 { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, 1556 { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, 1557 { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, 1558 { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, 1559 { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, 1560 #ifdef CONFIG_USER_ONLY 1561 { .name = "any", .initfn = arm_any_initfn }, 1562 #endif 1563 #endif 1564 { .name = NULL } 1565 }; 1566 1567 static Property arm_cpu_properties[] = { 1568 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), 1569 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), 1570 DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), 1571 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 1572 mp_affinity, ARM64_AFFINITY_INVALID), 1573 DEFINE_PROP_END_OF_LIST() 1574 }; 1575 1576 #ifdef CONFIG_USER_ONLY 1577 static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, 1578 int mmu_idx) 1579 { 1580 ARMCPU *cpu = ARM_CPU(cs); 1581 CPUARMState *env = &cpu->env; 1582 1583 env->exception.vaddress = address; 1584 if (rw == 2) { 1585 cs->exception_index = EXCP_PREFETCH_ABORT; 1586 } else { 1587 cs->exception_index = EXCP_DATA_ABORT; 1588 } 1589 return 1; 1590 } 1591 #endif 1592 1593 static gchar *arm_gdb_arch_name(CPUState *cs) 1594 { 1595 ARMCPU *cpu = ARM_CPU(cs); 1596 CPUARMState *env = &cpu->env; 1597 1598 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 1599 return g_strdup("iwmmxt"); 1600 } 1601 return g_strdup("arm"); 1602 } 1603 1604 static void arm_cpu_class_init(ObjectClass *oc, void *data) 1605 { 1606 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 1607 CPUClass *cc = CPU_CLASS(acc); 1608 DeviceClass *dc = DEVICE_CLASS(oc); 1609 1610 acc->parent_realize = dc->realize; 1611 dc->realize = arm_cpu_realizefn; 1612 dc->props = arm_cpu_properties; 1613 1614 acc->parent_reset = cc->reset; 1615 cc->reset = arm_cpu_reset; 1616 1617 cc->class_by_name = arm_cpu_class_by_name; 1618 cc->has_work = arm_cpu_has_work; 1619 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; 1620 cc->dump_state = arm_cpu_dump_state; 1621 cc->set_pc = arm_cpu_set_pc; 1622 cc->gdb_read_register = arm_cpu_gdb_read_register; 1623 cc->gdb_write_register = arm_cpu_gdb_write_register; 1624 #ifdef CONFIG_USER_ONLY 1625 cc->handle_mmu_fault = arm_cpu_handle_mmu_fault; 1626 #else 1627 cc->do_interrupt = arm_cpu_do_interrupt; 1628 cc->do_unaligned_access = arm_cpu_do_unaligned_access; 1629 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; 1630 cc->asidx_from_attrs = arm_asidx_from_attrs; 1631 cc->vmsd = &vmstate_arm_cpu; 1632 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian; 1633 cc->write_elf64_note = arm_cpu_write_elf64_note; 1634 cc->write_elf32_note = arm_cpu_write_elf32_note; 1635 #endif 1636 cc->gdb_num_core_regs = 26; 1637 cc->gdb_core_xml_file = "arm-core.xml"; 1638 cc->gdb_arch_name = arm_gdb_arch_name; 1639 cc->gdb_stop_before_watchpoint = true; 1640 cc->debug_excp_handler = arm_debug_excp_handler; 1641 cc->debug_check_watchpoint = arm_debug_check_watchpoint; 1642 1643 cc->disas_set_info = arm_disas_set_info; 1644 } 1645 1646 static void cpu_register(const ARMCPUInfo *info) 1647 { 1648 TypeInfo type_info = { 1649 .parent = TYPE_ARM_CPU, 1650 .instance_size = sizeof(ARMCPU), 1651 .instance_init = info->initfn, 1652 .class_size = sizeof(ARMCPUClass), 1653 .class_init = info->class_init, 1654 }; 1655 1656 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 1657 type_register(&type_info); 1658 g_free((void *)type_info.name); 1659 } 1660 1661 static const TypeInfo arm_cpu_type_info = { 1662 .name = TYPE_ARM_CPU, 1663 .parent = TYPE_CPU, 1664 .instance_size = sizeof(ARMCPU), 1665 .instance_init = arm_cpu_initfn, 1666 .instance_post_init = arm_cpu_post_init, 1667 .instance_finalize = arm_cpu_finalizefn, 1668 .abstract = true, 1669 .class_size = sizeof(ARMCPUClass), 1670 .class_init = arm_cpu_class_init, 1671 }; 1672 1673 static void arm_cpu_register_types(void) 1674 { 1675 const ARMCPUInfo *info = arm_cpus; 1676 1677 type_register_static(&arm_cpu_type_info); 1678 1679 while (info->name) { 1680 cpu_register(info); 1681 info++; 1682 } 1683 } 1684 1685 type_init(arm_cpu_register_types) 1686