1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/qemu-print.h" 23 #include "qemu-common.h" 24 #include "target/arm/idau.h" 25 #include "qemu/module.h" 26 #include "qapi/error.h" 27 #include "qapi/visitor.h" 28 #include "cpu.h" 29 #ifdef CONFIG_TCG 30 #include "hw/core/tcg-cpu-ops.h" 31 #endif /* CONFIG_TCG */ 32 #include "internals.h" 33 #include "exec/exec-all.h" 34 #include "hw/qdev-properties.h" 35 #if !defined(CONFIG_USER_ONLY) 36 #include "hw/loader.h" 37 #include "hw/boards.h" 38 #endif 39 #include "sysemu/tcg.h" 40 #include "sysemu/hw_accel.h" 41 #include "kvm_arm.h" 42 #include "disas/capstone.h" 43 #include "fpu/softfloat.h" 44 45 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 46 { 47 ARMCPU *cpu = ARM_CPU(cs); 48 CPUARMState *env = &cpu->env; 49 50 if (is_a64(env)) { 51 env->pc = value; 52 env->thumb = 0; 53 } else { 54 env->regs[15] = value & ~1; 55 env->thumb = value & 1; 56 } 57 } 58 59 #ifdef CONFIG_TCG 60 void arm_cpu_synchronize_from_tb(CPUState *cs, 61 const TranslationBlock *tb) 62 { 63 ARMCPU *cpu = ARM_CPU(cs); 64 CPUARMState *env = &cpu->env; 65 66 /* 67 * It's OK to look at env for the current mode here, because it's 68 * never possible for an AArch64 TB to chain to an AArch32 TB. 69 */ 70 if (is_a64(env)) { 71 env->pc = tb->pc; 72 } else { 73 env->regs[15] = tb->pc; 74 } 75 } 76 #endif /* CONFIG_TCG */ 77 78 static bool arm_cpu_has_work(CPUState *cs) 79 { 80 ARMCPU *cpu = ARM_CPU(cs); 81 82 return (cpu->power_state != PSCI_OFF) 83 && cs->interrupt_request & 84 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 85 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ 86 | CPU_INTERRUPT_EXITTB); 87 } 88 89 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 90 void *opaque) 91 { 92 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 93 94 entry->hook = hook; 95 entry->opaque = opaque; 96 97 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 98 } 99 100 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 101 void *opaque) 102 { 103 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 104 105 entry->hook = hook; 106 entry->opaque = opaque; 107 108 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 109 } 110 111 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 112 { 113 /* Reset a single ARMCPRegInfo register */ 114 ARMCPRegInfo *ri = value; 115 ARMCPU *cpu = opaque; 116 117 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { 118 return; 119 } 120 121 if (ri->resetfn) { 122 ri->resetfn(&cpu->env, ri); 123 return; 124 } 125 126 /* A zero offset is never possible as it would be regs[0] 127 * so we use it to indicate that reset is being handled elsewhere. 128 * This is basically only used for fields in non-core coprocessors 129 * (like the pxa2xx ones). 130 */ 131 if (!ri->fieldoffset) { 132 return; 133 } 134 135 if (cpreg_field_is_64bit(ri)) { 136 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 137 } else { 138 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 139 } 140 } 141 142 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 143 { 144 /* Purely an assertion check: we've already done reset once, 145 * so now check that running the reset for the cpreg doesn't 146 * change its value. This traps bugs where two different cpregs 147 * both try to reset the same state field but to different values. 148 */ 149 ARMCPRegInfo *ri = value; 150 ARMCPU *cpu = opaque; 151 uint64_t oldvalue, newvalue; 152 153 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 154 return; 155 } 156 157 oldvalue = read_raw_cp_reg(&cpu->env, ri); 158 cp_reg_reset(key, value, opaque); 159 newvalue = read_raw_cp_reg(&cpu->env, ri); 160 assert(oldvalue == newvalue); 161 } 162 163 static void arm_cpu_reset(DeviceState *dev) 164 { 165 CPUState *s = CPU(dev); 166 ARMCPU *cpu = ARM_CPU(s); 167 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 168 CPUARMState *env = &cpu->env; 169 170 acc->parent_reset(dev); 171 172 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 173 174 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 175 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 176 177 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 178 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 179 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 180 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 181 182 cpu->power_state = s->start_powered_off ? PSCI_OFF : PSCI_ON; 183 184 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 185 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 186 } 187 188 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 189 /* 64 bit CPUs always start in 64 bit mode */ 190 env->aarch64 = 1; 191 #if defined(CONFIG_USER_ONLY) 192 env->pstate = PSTATE_MODE_EL0t; 193 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 194 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 195 /* Enable all PAC keys. */ 196 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | 197 SCTLR_EnDA | SCTLR_EnDB); 198 /* and to the FP/Neon instructions */ 199 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); 200 /* and to the SVE instructions */ 201 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); 202 /* with reasonable vector length */ 203 if (cpu_isar_feature(aa64_sve, cpu)) { 204 env->vfp.zcr_el[1] = 205 aarch64_sve_zcr_get_valid_len(cpu, cpu->sve_default_vq - 1); 206 } 207 /* 208 * Enable TBI0 but not TBI1. 209 * Note that this must match useronly_clean_ptr. 210 */ 211 env->cp15.tcr_el[1].raw_tcr = (1ULL << 37); 212 213 /* Enable MTE */ 214 if (cpu_isar_feature(aa64_mte, cpu)) { 215 /* Enable tag access, but leave TCF0 as No Effect (0). */ 216 env->cp15.sctlr_el[1] |= SCTLR_ATA0; 217 /* 218 * Exclude all tags, so that tag 0 is always used. 219 * This corresponds to Linux current->thread.gcr_incl = 0. 220 * 221 * Set RRND, so that helper_irg() will generate a seed later. 222 * Here in cpu_reset(), the crypto subsystem has not yet been 223 * initialized. 224 */ 225 env->cp15.gcr_el1 = 0x1ffff; 226 } 227 #else 228 /* Reset into the highest available EL */ 229 if (arm_feature(env, ARM_FEATURE_EL3)) { 230 env->pstate = PSTATE_MODE_EL3h; 231 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 232 env->pstate = PSTATE_MODE_EL2h; 233 } else { 234 env->pstate = PSTATE_MODE_EL1h; 235 } 236 env->pc = cpu->rvbar; 237 #endif 238 } else { 239 #if defined(CONFIG_USER_ONLY) 240 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 241 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); 242 #endif 243 } 244 245 #if defined(CONFIG_USER_ONLY) 246 env->uncached_cpsr = ARM_CPU_MODE_USR; 247 /* For user mode we must enable access to coprocessors */ 248 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 249 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 250 env->cp15.c15_cpar = 3; 251 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 252 env->cp15.c15_cpar = 1; 253 } 254 #else 255 256 /* 257 * If the highest available EL is EL2, AArch32 will start in Hyp 258 * mode; otherwise it starts in SVC. Note that if we start in 259 * AArch64 then these values in the uncached_cpsr will be ignored. 260 */ 261 if (arm_feature(env, ARM_FEATURE_EL2) && 262 !arm_feature(env, ARM_FEATURE_EL3)) { 263 env->uncached_cpsr = ARM_CPU_MODE_HYP; 264 } else { 265 env->uncached_cpsr = ARM_CPU_MODE_SVC; 266 } 267 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 268 269 if (arm_feature(env, ARM_FEATURE_M)) { 270 uint32_t initial_msp; /* Loaded from 0x0 */ 271 uint32_t initial_pc; /* Loaded from 0x4 */ 272 uint8_t *rom; 273 uint32_t vecbase; 274 275 if (cpu_isar_feature(aa32_lob, cpu)) { 276 /* 277 * LTPSIZE is constant 4 if MVE not implemented, and resets 278 * to an UNKNOWN value if MVE is implemented. We choose to 279 * always reset to 4. 280 */ 281 env->v7m.ltpsize = 4; 282 /* The LTPSIZE field in FPDSCR is constant and reads as 4. */ 283 env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT; 284 env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT; 285 } 286 287 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 288 env->v7m.secure = true; 289 } else { 290 /* This bit resets to 0 if security is supported, but 1 if 291 * it is not. The bit is not present in v7M, but we set it 292 * here so we can avoid having to make checks on it conditional 293 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 294 */ 295 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 296 /* 297 * Set NSACR to indicate "NS access permitted to everything"; 298 * this avoids having to have all the tests of it being 299 * conditional on ARM_FEATURE_M_SECURITY. Note also that from 300 * v8.1M the guest-visible value of NSACR in a CPU without the 301 * Security Extension is 0xcff. 302 */ 303 env->v7m.nsacr = 0xcff; 304 } 305 306 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 307 * that it resets to 1, so QEMU always does that rather than making 308 * it dependent on CPU model. In v8M it is RES1. 309 */ 310 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 311 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 312 if (arm_feature(env, ARM_FEATURE_V8)) { 313 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 314 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 315 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 316 } 317 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 318 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 319 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 320 } 321 322 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 323 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; 324 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | 325 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; 326 } 327 /* Unlike A/R profile, M profile defines the reset LR value */ 328 env->regs[14] = 0xffffffff; 329 330 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 331 env->v7m.vecbase[M_REG_NS] = cpu->init_nsvtor & 0xffffff80; 332 333 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 334 vecbase = env->v7m.vecbase[env->v7m.secure]; 335 rom = rom_ptr_for_as(s->as, vecbase, 8); 336 if (rom) { 337 /* Address zero is covered by ROM which hasn't yet been 338 * copied into physical memory. 339 */ 340 initial_msp = ldl_p(rom); 341 initial_pc = ldl_p(rom + 4); 342 } else { 343 /* Address zero not covered by a ROM blob, or the ROM blob 344 * is in non-modifiable memory and this is a second reset after 345 * it got copied into memory. In the latter case, rom_ptr 346 * will return a NULL pointer and we should use ldl_phys instead. 347 */ 348 initial_msp = ldl_phys(s->as, vecbase); 349 initial_pc = ldl_phys(s->as, vecbase + 4); 350 } 351 352 env->regs[13] = initial_msp & 0xFFFFFFFC; 353 env->regs[15] = initial_pc & ~1; 354 env->thumb = initial_pc & 1; 355 } 356 357 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 358 * executing as AArch32 then check if highvecs are enabled and 359 * adjust the PC accordingly. 360 */ 361 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 362 env->regs[15] = 0xFFFF0000; 363 } 364 365 /* M profile requires that reset clears the exclusive monitor; 366 * A profile does not, but clearing it makes more sense than having it 367 * set with an exclusive access on address zero. 368 */ 369 arm_clear_exclusive(env); 370 371 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 372 #endif 373 374 if (arm_feature(env, ARM_FEATURE_PMSA)) { 375 if (cpu->pmsav7_dregion > 0) { 376 if (arm_feature(env, ARM_FEATURE_V8)) { 377 memset(env->pmsav8.rbar[M_REG_NS], 0, 378 sizeof(*env->pmsav8.rbar[M_REG_NS]) 379 * cpu->pmsav7_dregion); 380 memset(env->pmsav8.rlar[M_REG_NS], 0, 381 sizeof(*env->pmsav8.rlar[M_REG_NS]) 382 * cpu->pmsav7_dregion); 383 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 384 memset(env->pmsav8.rbar[M_REG_S], 0, 385 sizeof(*env->pmsav8.rbar[M_REG_S]) 386 * cpu->pmsav7_dregion); 387 memset(env->pmsav8.rlar[M_REG_S], 0, 388 sizeof(*env->pmsav8.rlar[M_REG_S]) 389 * cpu->pmsav7_dregion); 390 } 391 } else if (arm_feature(env, ARM_FEATURE_V7)) { 392 memset(env->pmsav7.drbar, 0, 393 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 394 memset(env->pmsav7.drsr, 0, 395 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 396 memset(env->pmsav7.dracr, 0, 397 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 398 } 399 } 400 env->pmsav7.rnr[M_REG_NS] = 0; 401 env->pmsav7.rnr[M_REG_S] = 0; 402 env->pmsav8.mair0[M_REG_NS] = 0; 403 env->pmsav8.mair0[M_REG_S] = 0; 404 env->pmsav8.mair1[M_REG_NS] = 0; 405 env->pmsav8.mair1[M_REG_S] = 0; 406 } 407 408 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 409 if (cpu->sau_sregion > 0) { 410 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 411 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 412 } 413 env->sau.rnr = 0; 414 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 415 * the Cortex-M33 does. 416 */ 417 env->sau.ctrl = 0; 418 } 419 420 set_flush_to_zero(1, &env->vfp.standard_fp_status); 421 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 422 set_default_nan_mode(1, &env->vfp.standard_fp_status); 423 set_default_nan_mode(1, &env->vfp.standard_fp_status_f16); 424 set_float_detect_tininess(float_tininess_before_rounding, 425 &env->vfp.fp_status); 426 set_float_detect_tininess(float_tininess_before_rounding, 427 &env->vfp.standard_fp_status); 428 set_float_detect_tininess(float_tininess_before_rounding, 429 &env->vfp.fp_status_f16); 430 set_float_detect_tininess(float_tininess_before_rounding, 431 &env->vfp.standard_fp_status_f16); 432 #ifndef CONFIG_USER_ONLY 433 if (kvm_enabled()) { 434 kvm_arm_reset_vcpu(cpu); 435 } 436 #endif 437 438 hw_breakpoint_update_all(cpu); 439 hw_watchpoint_update_all(cpu); 440 arm_rebuild_hflags(env); 441 } 442 443 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 444 unsigned int target_el, 445 unsigned int cur_el, bool secure, 446 uint64_t hcr_el2) 447 { 448 CPUARMState *env = cs->env_ptr; 449 bool pstate_unmasked; 450 bool unmasked = false; 451 452 /* 453 * Don't take exceptions if they target a lower EL. 454 * This check should catch any exceptions that would not be taken 455 * but left pending. 456 */ 457 if (cur_el > target_el) { 458 return false; 459 } 460 461 switch (excp_idx) { 462 case EXCP_FIQ: 463 pstate_unmasked = !(env->daif & PSTATE_F); 464 break; 465 466 case EXCP_IRQ: 467 pstate_unmasked = !(env->daif & PSTATE_I); 468 break; 469 470 case EXCP_VFIQ: 471 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 472 /* VFIQs are only taken when hypervized. */ 473 return false; 474 } 475 return !(env->daif & PSTATE_F); 476 case EXCP_VIRQ: 477 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 478 /* VIRQs are only taken when hypervized. */ 479 return false; 480 } 481 return !(env->daif & PSTATE_I); 482 default: 483 g_assert_not_reached(); 484 } 485 486 /* 487 * Use the target EL, current execution state and SCR/HCR settings to 488 * determine whether the corresponding CPSR bit is used to mask the 489 * interrupt. 490 */ 491 if ((target_el > cur_el) && (target_el != 1)) { 492 /* Exceptions targeting a higher EL may not be maskable */ 493 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 494 /* 495 * 64-bit masking rules are simple: exceptions to EL3 496 * can't be masked, and exceptions to EL2 can only be 497 * masked from Secure state. The HCR and SCR settings 498 * don't affect the masking logic, only the interrupt routing. 499 */ 500 if (target_el == 3 || !secure || (env->cp15.scr_el3 & SCR_EEL2)) { 501 unmasked = true; 502 } 503 } else { 504 /* 505 * The old 32-bit-only environment has a more complicated 506 * masking setup. HCR and SCR bits not only affect interrupt 507 * routing but also change the behaviour of masking. 508 */ 509 bool hcr, scr; 510 511 switch (excp_idx) { 512 case EXCP_FIQ: 513 /* 514 * If FIQs are routed to EL3 or EL2 then there are cases where 515 * we override the CPSR.F in determining if the exception is 516 * masked or not. If neither of these are set then we fall back 517 * to the CPSR.F setting otherwise we further assess the state 518 * below. 519 */ 520 hcr = hcr_el2 & HCR_FMO; 521 scr = (env->cp15.scr_el3 & SCR_FIQ); 522 523 /* 524 * When EL3 is 32-bit, the SCR.FW bit controls whether the 525 * CPSR.F bit masks FIQ interrupts when taken in non-secure 526 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 527 * when non-secure but only when FIQs are only routed to EL3. 528 */ 529 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 530 break; 531 case EXCP_IRQ: 532 /* 533 * When EL3 execution state is 32-bit, if HCR.IMO is set then 534 * we may override the CPSR.I masking when in non-secure state. 535 * The SCR.IRQ setting has already been taken into consideration 536 * when setting the target EL, so it does not have a further 537 * affect here. 538 */ 539 hcr = hcr_el2 & HCR_IMO; 540 scr = false; 541 break; 542 default: 543 g_assert_not_reached(); 544 } 545 546 if ((scr || hcr) && !secure) { 547 unmasked = true; 548 } 549 } 550 } 551 552 /* 553 * The PSTATE bits only mask the interrupt if we have not overriden the 554 * ability above. 555 */ 556 return unmasked || pstate_unmasked; 557 } 558 559 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 560 { 561 CPUClass *cc = CPU_GET_CLASS(cs); 562 CPUARMState *env = cs->env_ptr; 563 uint32_t cur_el = arm_current_el(env); 564 bool secure = arm_is_secure(env); 565 uint64_t hcr_el2 = arm_hcr_el2_eff(env); 566 uint32_t target_el; 567 uint32_t excp_idx; 568 569 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ 570 571 if (interrupt_request & CPU_INTERRUPT_FIQ) { 572 excp_idx = EXCP_FIQ; 573 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 574 if (arm_excp_unmasked(cs, excp_idx, target_el, 575 cur_el, secure, hcr_el2)) { 576 goto found; 577 } 578 } 579 if (interrupt_request & CPU_INTERRUPT_HARD) { 580 excp_idx = EXCP_IRQ; 581 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 582 if (arm_excp_unmasked(cs, excp_idx, target_el, 583 cur_el, secure, hcr_el2)) { 584 goto found; 585 } 586 } 587 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 588 excp_idx = EXCP_VIRQ; 589 target_el = 1; 590 if (arm_excp_unmasked(cs, excp_idx, target_el, 591 cur_el, secure, hcr_el2)) { 592 goto found; 593 } 594 } 595 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 596 excp_idx = EXCP_VFIQ; 597 target_el = 1; 598 if (arm_excp_unmasked(cs, excp_idx, target_el, 599 cur_el, secure, hcr_el2)) { 600 goto found; 601 } 602 } 603 return false; 604 605 found: 606 cs->exception_index = excp_idx; 607 env->exception.target_el = target_el; 608 cc->tcg_ops->do_interrupt(cs); 609 return true; 610 } 611 612 void arm_cpu_update_virq(ARMCPU *cpu) 613 { 614 /* 615 * Update the interrupt level for VIRQ, which is the logical OR of 616 * the HCR_EL2.VI bit and the input line level from the GIC. 617 */ 618 CPUARMState *env = &cpu->env; 619 CPUState *cs = CPU(cpu); 620 621 bool new_state = (env->cp15.hcr_el2 & HCR_VI) || 622 (env->irq_line_state & CPU_INTERRUPT_VIRQ); 623 624 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { 625 if (new_state) { 626 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); 627 } else { 628 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); 629 } 630 } 631 } 632 633 void arm_cpu_update_vfiq(ARMCPU *cpu) 634 { 635 /* 636 * Update the interrupt level for VFIQ, which is the logical OR of 637 * the HCR_EL2.VF bit and the input line level from the GIC. 638 */ 639 CPUARMState *env = &cpu->env; 640 CPUState *cs = CPU(cpu); 641 642 bool new_state = (env->cp15.hcr_el2 & HCR_VF) || 643 (env->irq_line_state & CPU_INTERRUPT_VFIQ); 644 645 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { 646 if (new_state) { 647 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); 648 } else { 649 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); 650 } 651 } 652 } 653 654 #ifndef CONFIG_USER_ONLY 655 static void arm_cpu_set_irq(void *opaque, int irq, int level) 656 { 657 ARMCPU *cpu = opaque; 658 CPUARMState *env = &cpu->env; 659 CPUState *cs = CPU(cpu); 660 static const int mask[] = { 661 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 662 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 663 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 664 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 665 }; 666 667 if (level) { 668 env->irq_line_state |= mask[irq]; 669 } else { 670 env->irq_line_state &= ~mask[irq]; 671 } 672 673 switch (irq) { 674 case ARM_CPU_VIRQ: 675 assert(arm_feature(env, ARM_FEATURE_EL2)); 676 arm_cpu_update_virq(cpu); 677 break; 678 case ARM_CPU_VFIQ: 679 assert(arm_feature(env, ARM_FEATURE_EL2)); 680 arm_cpu_update_vfiq(cpu); 681 break; 682 case ARM_CPU_IRQ: 683 case ARM_CPU_FIQ: 684 if (level) { 685 cpu_interrupt(cs, mask[irq]); 686 } else { 687 cpu_reset_interrupt(cs, mask[irq]); 688 } 689 break; 690 default: 691 g_assert_not_reached(); 692 } 693 } 694 695 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 696 { 697 #ifdef CONFIG_KVM 698 ARMCPU *cpu = opaque; 699 CPUARMState *env = &cpu->env; 700 CPUState *cs = CPU(cpu); 701 uint32_t linestate_bit; 702 int irq_id; 703 704 switch (irq) { 705 case ARM_CPU_IRQ: 706 irq_id = KVM_ARM_IRQ_CPU_IRQ; 707 linestate_bit = CPU_INTERRUPT_HARD; 708 break; 709 case ARM_CPU_FIQ: 710 irq_id = KVM_ARM_IRQ_CPU_FIQ; 711 linestate_bit = CPU_INTERRUPT_FIQ; 712 break; 713 default: 714 g_assert_not_reached(); 715 } 716 717 if (level) { 718 env->irq_line_state |= linestate_bit; 719 } else { 720 env->irq_line_state &= ~linestate_bit; 721 } 722 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); 723 #endif 724 } 725 726 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 727 { 728 ARMCPU *cpu = ARM_CPU(cs); 729 CPUARMState *env = &cpu->env; 730 731 cpu_synchronize_state(cs); 732 return arm_cpu_data_is_big_endian(env); 733 } 734 735 #endif 736 737 static int 738 print_insn_thumb1(bfd_vma pc, disassemble_info *info) 739 { 740 return print_insn_arm(pc | 1, info); 741 } 742 743 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 744 { 745 ARMCPU *ac = ARM_CPU(cpu); 746 CPUARMState *env = &ac->env; 747 bool sctlr_b; 748 749 if (is_a64(env)) { 750 /* We might not be compiled with the A64 disassembler 751 * because it needs a C++ compiler. Leave print_insn 752 * unset in this case to use the caller default behaviour. 753 */ 754 #if defined(CONFIG_ARM_A64_DIS) 755 info->print_insn = print_insn_arm_a64; 756 #endif 757 info->cap_arch = CS_ARCH_ARM64; 758 info->cap_insn_unit = 4; 759 info->cap_insn_split = 4; 760 } else { 761 int cap_mode; 762 if (env->thumb) { 763 info->print_insn = print_insn_thumb1; 764 info->cap_insn_unit = 2; 765 info->cap_insn_split = 4; 766 cap_mode = CS_MODE_THUMB; 767 } else { 768 info->print_insn = print_insn_arm; 769 info->cap_insn_unit = 4; 770 info->cap_insn_split = 4; 771 cap_mode = CS_MODE_ARM; 772 } 773 if (arm_feature(env, ARM_FEATURE_V8)) { 774 cap_mode |= CS_MODE_V8; 775 } 776 if (arm_feature(env, ARM_FEATURE_M)) { 777 cap_mode |= CS_MODE_MCLASS; 778 } 779 info->cap_arch = CS_ARCH_ARM; 780 info->cap_mode = cap_mode; 781 } 782 783 sctlr_b = arm_sctlr_b(env); 784 if (bswap_code(sctlr_b)) { 785 #ifdef TARGET_WORDS_BIGENDIAN 786 info->endian = BFD_ENDIAN_LITTLE; 787 #else 788 info->endian = BFD_ENDIAN_BIG; 789 #endif 790 } 791 info->flags &= ~INSN_ARM_BE32; 792 #ifndef CONFIG_USER_ONLY 793 if (sctlr_b) { 794 info->flags |= INSN_ARM_BE32; 795 } 796 #endif 797 } 798 799 #ifdef TARGET_AARCH64 800 801 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 802 { 803 ARMCPU *cpu = ARM_CPU(cs); 804 CPUARMState *env = &cpu->env; 805 uint32_t psr = pstate_read(env); 806 int i; 807 int el = arm_current_el(env); 808 const char *ns_status; 809 810 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 811 for (i = 0; i < 32; i++) { 812 if (i == 31) { 813 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); 814 } else { 815 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], 816 (i + 2) % 3 ? " " : "\n"); 817 } 818 } 819 820 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { 821 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 822 } else { 823 ns_status = ""; 824 } 825 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c", 826 psr, 827 psr & PSTATE_N ? 'N' : '-', 828 psr & PSTATE_Z ? 'Z' : '-', 829 psr & PSTATE_C ? 'C' : '-', 830 psr & PSTATE_V ? 'V' : '-', 831 ns_status, 832 el, 833 psr & PSTATE_SP ? 'h' : 't'); 834 835 if (cpu_isar_feature(aa64_bti, cpu)) { 836 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); 837 } 838 if (!(flags & CPU_DUMP_FPU)) { 839 qemu_fprintf(f, "\n"); 840 return; 841 } 842 if (fp_exception_el(env, el) != 0) { 843 qemu_fprintf(f, " FPU disabled\n"); 844 return; 845 } 846 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", 847 vfp_get_fpcr(env), vfp_get_fpsr(env)); 848 849 if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) { 850 int j, zcr_len = sve_zcr_len_for_el(env, el); 851 852 for (i = 0; i <= FFR_PRED_NUM; i++) { 853 bool eol; 854 if (i == FFR_PRED_NUM) { 855 qemu_fprintf(f, "FFR="); 856 /* It's last, so end the line. */ 857 eol = true; 858 } else { 859 qemu_fprintf(f, "P%02d=", i); 860 switch (zcr_len) { 861 case 0: 862 eol = i % 8 == 7; 863 break; 864 case 1: 865 eol = i % 6 == 5; 866 break; 867 case 2: 868 case 3: 869 eol = i % 3 == 2; 870 break; 871 default: 872 /* More than one quadword per predicate. */ 873 eol = true; 874 break; 875 } 876 } 877 for (j = zcr_len / 4; j >= 0; j--) { 878 int digits; 879 if (j * 4 + 4 <= zcr_len + 1) { 880 digits = 16; 881 } else { 882 digits = (zcr_len % 4 + 1) * 4; 883 } 884 qemu_fprintf(f, "%0*" PRIx64 "%s", digits, 885 env->vfp.pregs[i].p[j], 886 j ? ":" : eol ? "\n" : " "); 887 } 888 } 889 890 for (i = 0; i < 32; i++) { 891 if (zcr_len == 0) { 892 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", 893 i, env->vfp.zregs[i].d[1], 894 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); 895 } else if (zcr_len == 1) { 896 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 897 ":%016" PRIx64 ":%016" PRIx64 "\n", 898 i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2], 899 env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]); 900 } else { 901 for (j = zcr_len; j >= 0; j--) { 902 bool odd = (zcr_len - j) % 2 != 0; 903 if (j == zcr_len) { 904 qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1); 905 } else if (!odd) { 906 if (j > 0) { 907 qemu_fprintf(f, " [%x-%x]=", j, j - 1); 908 } else { 909 qemu_fprintf(f, " [%x]=", j); 910 } 911 } 912 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", 913 env->vfp.zregs[i].d[j * 2 + 1], 914 env->vfp.zregs[i].d[j * 2], 915 odd || j == 0 ? "\n" : ":"); 916 } 917 } 918 } 919 } else { 920 for (i = 0; i < 32; i++) { 921 uint64_t *q = aa64_vfp_qreg(env, i); 922 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", 923 i, q[1], q[0], (i & 1 ? "\n" : " ")); 924 } 925 } 926 } 927 928 #else 929 930 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 931 { 932 g_assert_not_reached(); 933 } 934 935 #endif 936 937 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) 938 { 939 ARMCPU *cpu = ARM_CPU(cs); 940 CPUARMState *env = &cpu->env; 941 int i; 942 943 if (is_a64(env)) { 944 aarch64_cpu_dump_state(cs, f, flags); 945 return; 946 } 947 948 for (i = 0; i < 16; i++) { 949 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]); 950 if ((i % 4) == 3) { 951 qemu_fprintf(f, "\n"); 952 } else { 953 qemu_fprintf(f, " "); 954 } 955 } 956 957 if (arm_feature(env, ARM_FEATURE_M)) { 958 uint32_t xpsr = xpsr_read(env); 959 const char *mode; 960 const char *ns_status = ""; 961 962 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 963 ns_status = env->v7m.secure ? "S " : "NS "; 964 } 965 966 if (xpsr & XPSR_EXCP) { 967 mode = "handler"; 968 } else { 969 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { 970 mode = "unpriv-thread"; 971 } else { 972 mode = "priv-thread"; 973 } 974 } 975 976 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", 977 xpsr, 978 xpsr & XPSR_N ? 'N' : '-', 979 xpsr & XPSR_Z ? 'Z' : '-', 980 xpsr & XPSR_C ? 'C' : '-', 981 xpsr & XPSR_V ? 'V' : '-', 982 xpsr & XPSR_T ? 'T' : 'A', 983 ns_status, 984 mode); 985 } else { 986 uint32_t psr = cpsr_read(env); 987 const char *ns_status = ""; 988 989 if (arm_feature(env, ARM_FEATURE_EL3) && 990 (psr & CPSR_M) != ARM_CPU_MODE_MON) { 991 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 992 } 993 994 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", 995 psr, 996 psr & CPSR_N ? 'N' : '-', 997 psr & CPSR_Z ? 'Z' : '-', 998 psr & CPSR_C ? 'C' : '-', 999 psr & CPSR_V ? 'V' : '-', 1000 psr & CPSR_T ? 'T' : 'A', 1001 ns_status, 1002 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); 1003 } 1004 1005 if (flags & CPU_DUMP_FPU) { 1006 int numvfpregs = 0; 1007 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1008 numvfpregs = 32; 1009 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 1010 numvfpregs = 16; 1011 } 1012 for (i = 0; i < numvfpregs; i++) { 1013 uint64_t v = *aa32_vfp_dreg(env, i); 1014 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", 1015 i * 2, (uint32_t)v, 1016 i * 2 + 1, (uint32_t)(v >> 32), 1017 i, v); 1018 } 1019 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); 1020 if (cpu_isar_feature(aa32_mve, cpu)) { 1021 qemu_fprintf(f, "VPR: %08x\n", env->v7m.vpr); 1022 } 1023 } 1024 } 1025 1026 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 1027 { 1028 uint32_t Aff1 = idx / clustersz; 1029 uint32_t Aff0 = idx % clustersz; 1030 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 1031 } 1032 1033 static void cpreg_hashtable_data_destroy(gpointer data) 1034 { 1035 /* 1036 * Destroy function for cpu->cp_regs hashtable data entries. 1037 * We must free the name string because it was g_strdup()ed in 1038 * add_cpreg_to_hashtable(). It's OK to cast away the 'const' 1039 * from r->name because we know we definitely allocated it. 1040 */ 1041 ARMCPRegInfo *r = data; 1042 1043 g_free((void *)r->name); 1044 g_free(r); 1045 } 1046 1047 static void arm_cpu_initfn(Object *obj) 1048 { 1049 ARMCPU *cpu = ARM_CPU(obj); 1050 1051 cpu_set_cpustate_pointers(cpu); 1052 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, 1053 g_free, cpreg_hashtable_data_destroy); 1054 1055 QLIST_INIT(&cpu->pre_el_change_hooks); 1056 QLIST_INIT(&cpu->el_change_hooks); 1057 1058 #ifdef CONFIG_USER_ONLY 1059 # ifdef TARGET_AARCH64 1060 /* 1061 * The linux kernel defaults to 512-bit vectors, when sve is supported. 1062 * See documentation for /proc/sys/abi/sve_default_vector_length, and 1063 * our corresponding sve-default-vector-length cpu property. 1064 */ 1065 cpu->sve_default_vq = 4; 1066 # endif 1067 #else 1068 /* Our inbound IRQ and FIQ lines */ 1069 if (kvm_enabled()) { 1070 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 1071 * the same interface as non-KVM CPUs. 1072 */ 1073 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 1074 } else { 1075 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 1076 } 1077 1078 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 1079 ARRAY_SIZE(cpu->gt_timer_outputs)); 1080 1081 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 1082 "gicv3-maintenance-interrupt", 1); 1083 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 1084 "pmu-interrupt", 1); 1085 #endif 1086 1087 /* DTB consumers generally don't in fact care what the 'compatible' 1088 * string is, so always provide some string and trust that a hypothetical 1089 * picky DTB consumer will also provide a helpful error message. 1090 */ 1091 cpu->dtb_compatible = "qemu,unknown"; 1092 cpu->psci_version = 1; /* By default assume PSCI v0.1 */ 1093 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 1094 1095 if (tcg_enabled()) { 1096 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ 1097 } 1098 } 1099 1100 static Property arm_cpu_gt_cntfrq_property = 1101 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 1102 NANOSECONDS_PER_SECOND / GTIMER_SCALE); 1103 1104 static Property arm_cpu_reset_cbar_property = 1105 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 1106 1107 static Property arm_cpu_reset_hivecs_property = 1108 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 1109 1110 static Property arm_cpu_rvbar_property = 1111 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); 1112 1113 #ifndef CONFIG_USER_ONLY 1114 static Property arm_cpu_has_el2_property = 1115 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 1116 1117 static Property arm_cpu_has_el3_property = 1118 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 1119 #endif 1120 1121 static Property arm_cpu_cfgend_property = 1122 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 1123 1124 static Property arm_cpu_has_vfp_property = 1125 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); 1126 1127 static Property arm_cpu_has_neon_property = 1128 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); 1129 1130 static Property arm_cpu_has_dsp_property = 1131 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); 1132 1133 static Property arm_cpu_has_mpu_property = 1134 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 1135 1136 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 1137 * because the CPU initfn will have already set cpu->pmsav7_dregion to 1138 * the right value for that particular CPU type, and we don't want 1139 * to override that with an incorrect constant value. 1140 */ 1141 static Property arm_cpu_pmsav7_dregion_property = 1142 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 1143 pmsav7_dregion, 1144 qdev_prop_uint32, uint32_t); 1145 1146 static bool arm_get_pmu(Object *obj, Error **errp) 1147 { 1148 ARMCPU *cpu = ARM_CPU(obj); 1149 1150 return cpu->has_pmu; 1151 } 1152 1153 static void arm_set_pmu(Object *obj, bool value, Error **errp) 1154 { 1155 ARMCPU *cpu = ARM_CPU(obj); 1156 1157 if (value) { 1158 if (kvm_enabled() && !kvm_arm_pmu_supported()) { 1159 error_setg(errp, "'pmu' feature not supported by KVM on this host"); 1160 return; 1161 } 1162 set_feature(&cpu->env, ARM_FEATURE_PMU); 1163 } else { 1164 unset_feature(&cpu->env, ARM_FEATURE_PMU); 1165 } 1166 cpu->has_pmu = value; 1167 } 1168 1169 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) 1170 { 1171 /* 1172 * The exact approach to calculating guest ticks is: 1173 * 1174 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz, 1175 * NANOSECONDS_PER_SECOND); 1176 * 1177 * We don't do that. Rather we intentionally use integer division 1178 * truncation below and in the caller for the conversion of host monotonic 1179 * time to guest ticks to provide the exact inverse for the semantics of 1180 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so 1181 * it loses precision when representing frequencies where 1182 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to 1183 * provide an exact inverse leads to scheduling timers with negative 1184 * periods, which in turn leads to sticky behaviour in the guest. 1185 * 1186 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor 1187 * cannot become zero. 1188 */ 1189 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ? 1190 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; 1191 } 1192 1193 void arm_cpu_post_init(Object *obj) 1194 { 1195 ARMCPU *cpu = ARM_CPU(obj); 1196 1197 /* M profile implies PMSA. We have to do this here rather than 1198 * in realize with the other feature-implication checks because 1199 * we look at the PMSA bit to see if we should add some properties. 1200 */ 1201 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1202 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1203 } 1204 1205 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 1206 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 1207 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); 1208 } 1209 1210 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 1211 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); 1212 } 1213 1214 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1215 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property); 1216 } 1217 1218 #ifndef CONFIG_USER_ONLY 1219 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1220 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 1221 * prevent "has_el3" from existing on CPUs which cannot support EL3. 1222 */ 1223 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); 1224 1225 object_property_add_link(obj, "secure-memory", 1226 TYPE_MEMORY_REGION, 1227 (Object **)&cpu->secure_memory, 1228 qdev_prop_allow_set_link_before_realize, 1229 OBJ_PROP_LINK_STRONG); 1230 } 1231 1232 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 1233 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); 1234 } 1235 #endif 1236 1237 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 1238 cpu->has_pmu = true; 1239 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu); 1240 } 1241 1242 /* 1243 * Allow user to turn off VFP and Neon support, but only for TCG -- 1244 * KVM does not currently allow us to lie to the guest about its 1245 * ID/feature registers, so the guest always sees what the host has. 1246 */ 1247 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) 1248 ? cpu_isar_feature(aa64_fp_simd, cpu) 1249 : cpu_isar_feature(aa32_vfp, cpu)) { 1250 cpu->has_vfp = true; 1251 if (!kvm_enabled()) { 1252 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property); 1253 } 1254 } 1255 1256 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { 1257 cpu->has_neon = true; 1258 if (!kvm_enabled()) { 1259 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property); 1260 } 1261 } 1262 1263 if (arm_feature(&cpu->env, ARM_FEATURE_M) && 1264 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { 1265 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property); 1266 } 1267 1268 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 1269 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); 1270 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1271 qdev_property_add_static(DEVICE(obj), 1272 &arm_cpu_pmsav7_dregion_property); 1273 } 1274 } 1275 1276 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 1277 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 1278 qdev_prop_allow_set_link_before_realize, 1279 OBJ_PROP_LINK_STRONG); 1280 /* 1281 * M profile: initial value of the Secure VTOR. We can't just use 1282 * a simple DEFINE_PROP_UINT32 for this because we want to permit 1283 * the property to be set after realize. 1284 */ 1285 object_property_add_uint32_ptr(obj, "init-svtor", 1286 &cpu->init_svtor, 1287 OBJ_PROP_FLAG_READWRITE); 1288 } 1289 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1290 /* 1291 * Initial value of the NS VTOR (for cores without the Security 1292 * extension, this is the only VTOR) 1293 */ 1294 object_property_add_uint32_ptr(obj, "init-nsvtor", 1295 &cpu->init_nsvtor, 1296 OBJ_PROP_FLAG_READWRITE); 1297 } 1298 1299 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); 1300 1301 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { 1302 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); 1303 } 1304 1305 if (kvm_enabled()) { 1306 kvm_arm_add_vcpu_properties(obj); 1307 } 1308 1309 #ifndef CONFIG_USER_ONLY 1310 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && 1311 cpu_isar_feature(aa64_mte, cpu)) { 1312 object_property_add_link(obj, "tag-memory", 1313 TYPE_MEMORY_REGION, 1314 (Object **)&cpu->tag_memory, 1315 qdev_prop_allow_set_link_before_realize, 1316 OBJ_PROP_LINK_STRONG); 1317 1318 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1319 object_property_add_link(obj, "secure-tag-memory", 1320 TYPE_MEMORY_REGION, 1321 (Object **)&cpu->secure_tag_memory, 1322 qdev_prop_allow_set_link_before_realize, 1323 OBJ_PROP_LINK_STRONG); 1324 } 1325 } 1326 #endif 1327 } 1328 1329 static void arm_cpu_finalizefn(Object *obj) 1330 { 1331 ARMCPU *cpu = ARM_CPU(obj); 1332 ARMELChangeHook *hook, *next; 1333 1334 g_hash_table_destroy(cpu->cp_regs); 1335 1336 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 1337 QLIST_REMOVE(hook, node); 1338 g_free(hook); 1339 } 1340 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 1341 QLIST_REMOVE(hook, node); 1342 g_free(hook); 1343 } 1344 #ifndef CONFIG_USER_ONLY 1345 if (cpu->pmu_timer) { 1346 timer_free(cpu->pmu_timer); 1347 } 1348 #endif 1349 } 1350 1351 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) 1352 { 1353 Error *local_err = NULL; 1354 1355 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1356 arm_cpu_sve_finalize(cpu, &local_err); 1357 if (local_err != NULL) { 1358 error_propagate(errp, local_err); 1359 return; 1360 } 1361 1362 /* 1363 * KVM does not support modifications to this feature. 1364 * We have not registered the cpu properties when KVM 1365 * is in use, so the user will not be able to set them. 1366 */ 1367 if (!kvm_enabled()) { 1368 arm_cpu_pauth_finalize(cpu, &local_err); 1369 if (local_err != NULL) { 1370 error_propagate(errp, local_err); 1371 return; 1372 } 1373 } 1374 } 1375 1376 if (kvm_enabled()) { 1377 kvm_arm_steal_time_finalize(cpu, &local_err); 1378 if (local_err != NULL) { 1379 error_propagate(errp, local_err); 1380 return; 1381 } 1382 } 1383 } 1384 1385 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 1386 { 1387 CPUState *cs = CPU(dev); 1388 ARMCPU *cpu = ARM_CPU(dev); 1389 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 1390 CPUARMState *env = &cpu->env; 1391 int pagebits; 1392 Error *local_err = NULL; 1393 bool no_aa32 = false; 1394 1395 /* If we needed to query the host kernel for the CPU features 1396 * then it's possible that might have failed in the initfn, but 1397 * this is the first point where we can report it. 1398 */ 1399 if (cpu->host_cpu_probe_failed) { 1400 if (!kvm_enabled()) { 1401 error_setg(errp, "The 'host' CPU type can only be used with KVM"); 1402 } else { 1403 error_setg(errp, "Failed to retrieve host CPU features"); 1404 } 1405 return; 1406 } 1407 1408 #ifndef CONFIG_USER_ONLY 1409 /* The NVIC and M-profile CPU are two halves of a single piece of 1410 * hardware; trying to use one without the other is a command line 1411 * error and will result in segfaults if not caught here. 1412 */ 1413 if (arm_feature(env, ARM_FEATURE_M)) { 1414 if (!env->nvic) { 1415 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 1416 return; 1417 } 1418 } else { 1419 if (env->nvic) { 1420 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 1421 return; 1422 } 1423 } 1424 1425 { 1426 uint64_t scale; 1427 1428 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { 1429 if (!cpu->gt_cntfrq_hz) { 1430 error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", 1431 cpu->gt_cntfrq_hz); 1432 return; 1433 } 1434 scale = gt_cntfrq_period_ns(cpu); 1435 } else { 1436 scale = GTIMER_SCALE; 1437 } 1438 1439 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1440 arm_gt_ptimer_cb, cpu); 1441 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1442 arm_gt_vtimer_cb, cpu); 1443 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1444 arm_gt_htimer_cb, cpu); 1445 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1446 arm_gt_stimer_cb, cpu); 1447 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1448 arm_gt_hvtimer_cb, cpu); 1449 } 1450 #endif 1451 1452 cpu_exec_realizefn(cs, &local_err); 1453 if (local_err != NULL) { 1454 error_propagate(errp, local_err); 1455 return; 1456 } 1457 1458 arm_cpu_finalize_features(cpu, &local_err); 1459 if (local_err != NULL) { 1460 error_propagate(errp, local_err); 1461 return; 1462 } 1463 1464 if (arm_feature(env, ARM_FEATURE_AARCH64) && 1465 cpu->has_vfp != cpu->has_neon) { 1466 /* 1467 * This is an architectural requirement for AArch64; AArch32 is 1468 * more flexible and permits VFP-no-Neon and Neon-no-VFP. 1469 */ 1470 error_setg(errp, 1471 "AArch64 CPUs must have both VFP and Neon or neither"); 1472 return; 1473 } 1474 1475 if (!cpu->has_vfp) { 1476 uint64_t t; 1477 uint32_t u; 1478 1479 t = cpu->isar.id_aa64isar1; 1480 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); 1481 cpu->isar.id_aa64isar1 = t; 1482 1483 t = cpu->isar.id_aa64pfr0; 1484 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); 1485 cpu->isar.id_aa64pfr0 = t; 1486 1487 u = cpu->isar.id_isar6; 1488 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); 1489 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 1490 cpu->isar.id_isar6 = u; 1491 1492 u = cpu->isar.mvfr0; 1493 u = FIELD_DP32(u, MVFR0, FPSP, 0); 1494 u = FIELD_DP32(u, MVFR0, FPDP, 0); 1495 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); 1496 u = FIELD_DP32(u, MVFR0, FPSQRT, 0); 1497 u = FIELD_DP32(u, MVFR0, FPROUND, 0); 1498 if (!arm_feature(env, ARM_FEATURE_M)) { 1499 u = FIELD_DP32(u, MVFR0, FPTRAP, 0); 1500 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); 1501 } 1502 cpu->isar.mvfr0 = u; 1503 1504 u = cpu->isar.mvfr1; 1505 u = FIELD_DP32(u, MVFR1, FPFTZ, 0); 1506 u = FIELD_DP32(u, MVFR1, FPDNAN, 0); 1507 u = FIELD_DP32(u, MVFR1, FPHP, 0); 1508 if (arm_feature(env, ARM_FEATURE_M)) { 1509 u = FIELD_DP32(u, MVFR1, FP16, 0); 1510 } 1511 cpu->isar.mvfr1 = u; 1512 1513 u = cpu->isar.mvfr2; 1514 u = FIELD_DP32(u, MVFR2, FPMISC, 0); 1515 cpu->isar.mvfr2 = u; 1516 } 1517 1518 if (!cpu->has_neon) { 1519 uint64_t t; 1520 uint32_t u; 1521 1522 unset_feature(env, ARM_FEATURE_NEON); 1523 1524 t = cpu->isar.id_aa64isar0; 1525 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); 1526 cpu->isar.id_aa64isar0 = t; 1527 1528 t = cpu->isar.id_aa64isar1; 1529 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); 1530 t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 0); 1531 t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0); 1532 cpu->isar.id_aa64isar1 = t; 1533 1534 t = cpu->isar.id_aa64pfr0; 1535 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); 1536 cpu->isar.id_aa64pfr0 = t; 1537 1538 u = cpu->isar.id_isar5; 1539 u = FIELD_DP32(u, ID_ISAR5, RDM, 0); 1540 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); 1541 cpu->isar.id_isar5 = u; 1542 1543 u = cpu->isar.id_isar6; 1544 u = FIELD_DP32(u, ID_ISAR6, DP, 0); 1545 u = FIELD_DP32(u, ID_ISAR6, FHM, 0); 1546 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 1547 u = FIELD_DP32(u, ID_ISAR6, I8MM, 0); 1548 cpu->isar.id_isar6 = u; 1549 1550 if (!arm_feature(env, ARM_FEATURE_M)) { 1551 u = cpu->isar.mvfr1; 1552 u = FIELD_DP32(u, MVFR1, SIMDLS, 0); 1553 u = FIELD_DP32(u, MVFR1, SIMDINT, 0); 1554 u = FIELD_DP32(u, MVFR1, SIMDSP, 0); 1555 u = FIELD_DP32(u, MVFR1, SIMDHP, 0); 1556 cpu->isar.mvfr1 = u; 1557 1558 u = cpu->isar.mvfr2; 1559 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0); 1560 cpu->isar.mvfr2 = u; 1561 } 1562 } 1563 1564 if (!cpu->has_neon && !cpu->has_vfp) { 1565 uint64_t t; 1566 uint32_t u; 1567 1568 t = cpu->isar.id_aa64isar0; 1569 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); 1570 cpu->isar.id_aa64isar0 = t; 1571 1572 t = cpu->isar.id_aa64isar1; 1573 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); 1574 cpu->isar.id_aa64isar1 = t; 1575 1576 u = cpu->isar.mvfr0; 1577 u = FIELD_DP32(u, MVFR0, SIMDREG, 0); 1578 cpu->isar.mvfr0 = u; 1579 1580 /* Despite the name, this field covers both VFP and Neon */ 1581 u = cpu->isar.mvfr1; 1582 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); 1583 cpu->isar.mvfr1 = u; 1584 } 1585 1586 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { 1587 uint32_t u; 1588 1589 unset_feature(env, ARM_FEATURE_THUMB_DSP); 1590 1591 u = cpu->isar.id_isar1; 1592 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1); 1593 cpu->isar.id_isar1 = u; 1594 1595 u = cpu->isar.id_isar2; 1596 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); 1597 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); 1598 cpu->isar.id_isar2 = u; 1599 1600 u = cpu->isar.id_isar3; 1601 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); 1602 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); 1603 cpu->isar.id_isar3 = u; 1604 } 1605 1606 /* Some features automatically imply others: */ 1607 if (arm_feature(env, ARM_FEATURE_V8)) { 1608 if (arm_feature(env, ARM_FEATURE_M)) { 1609 set_feature(env, ARM_FEATURE_V7); 1610 } else { 1611 set_feature(env, ARM_FEATURE_V7VE); 1612 } 1613 } 1614 1615 /* 1616 * There exist AArch64 cpus without AArch32 support. When KVM 1617 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 1618 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 1619 * As a general principle, we also do not make ID register 1620 * consistency checks anywhere unless using TCG, because only 1621 * for TCG would a consistency-check failure be a QEMU bug. 1622 */ 1623 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1624 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 1625 } 1626 1627 if (arm_feature(env, ARM_FEATURE_V7VE)) { 1628 /* v7 Virtualization Extensions. In real hardware this implies 1629 * EL2 and also the presence of the Security Extensions. 1630 * For QEMU, for backwards-compatibility we implement some 1631 * CPUs or CPU configs which have no actual EL2 or EL3 but do 1632 * include the various other features that V7VE implies. 1633 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 1634 * Security Extensions is ARM_FEATURE_EL3. 1635 */ 1636 assert(!tcg_enabled() || no_aa32 || 1637 cpu_isar_feature(aa32_arm_div, cpu)); 1638 set_feature(env, ARM_FEATURE_LPAE); 1639 set_feature(env, ARM_FEATURE_V7); 1640 } 1641 if (arm_feature(env, ARM_FEATURE_V7)) { 1642 set_feature(env, ARM_FEATURE_VAPA); 1643 set_feature(env, ARM_FEATURE_THUMB2); 1644 set_feature(env, ARM_FEATURE_MPIDR); 1645 if (!arm_feature(env, ARM_FEATURE_M)) { 1646 set_feature(env, ARM_FEATURE_V6K); 1647 } else { 1648 set_feature(env, ARM_FEATURE_V6); 1649 } 1650 1651 /* Always define VBAR for V7 CPUs even if it doesn't exist in 1652 * non-EL3 configs. This is needed by some legacy boards. 1653 */ 1654 set_feature(env, ARM_FEATURE_VBAR); 1655 } 1656 if (arm_feature(env, ARM_FEATURE_V6K)) { 1657 set_feature(env, ARM_FEATURE_V6); 1658 set_feature(env, ARM_FEATURE_MVFR); 1659 } 1660 if (arm_feature(env, ARM_FEATURE_V6)) { 1661 set_feature(env, ARM_FEATURE_V5); 1662 if (!arm_feature(env, ARM_FEATURE_M)) { 1663 assert(!tcg_enabled() || no_aa32 || 1664 cpu_isar_feature(aa32_jazelle, cpu)); 1665 set_feature(env, ARM_FEATURE_AUXCR); 1666 } 1667 } 1668 if (arm_feature(env, ARM_FEATURE_V5)) { 1669 set_feature(env, ARM_FEATURE_V4T); 1670 } 1671 if (arm_feature(env, ARM_FEATURE_LPAE)) { 1672 set_feature(env, ARM_FEATURE_V7MP); 1673 } 1674 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 1675 set_feature(env, ARM_FEATURE_CBAR); 1676 } 1677 if (arm_feature(env, ARM_FEATURE_THUMB2) && 1678 !arm_feature(env, ARM_FEATURE_M)) { 1679 set_feature(env, ARM_FEATURE_THUMB_DSP); 1680 } 1681 1682 /* 1683 * We rely on no XScale CPU having VFP so we can use the same bits in the 1684 * TB flags field for VECSTRIDE and XSCALE_CPAR. 1685 */ 1686 assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) || 1687 !cpu_isar_feature(aa32_vfp_simd, cpu) || 1688 !arm_feature(env, ARM_FEATURE_XSCALE)); 1689 1690 if (arm_feature(env, ARM_FEATURE_V7) && 1691 !arm_feature(env, ARM_FEATURE_M) && 1692 !arm_feature(env, ARM_FEATURE_PMSA)) { 1693 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 1694 * can use 4K pages. 1695 */ 1696 pagebits = 12; 1697 } else { 1698 /* For CPUs which might have tiny 1K pages, or which have an 1699 * MPU and might have small region sizes, stick with 1K pages. 1700 */ 1701 pagebits = 10; 1702 } 1703 if (!set_preferred_target_page_bits(pagebits)) { 1704 /* This can only ever happen for hotplugging a CPU, or if 1705 * the board code incorrectly creates a CPU which it has 1706 * promised via minimum_page_size that it will not. 1707 */ 1708 error_setg(errp, "This CPU requires a smaller page size than the " 1709 "system is using"); 1710 return; 1711 } 1712 1713 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 1714 * We don't support setting cluster ID ([16..23]) (known as Aff2 1715 * in later ARM ARM versions), or any of the higher affinity level fields, 1716 * so these bits always RAZ. 1717 */ 1718 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 1719 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 1720 ARM_DEFAULT_CPUS_PER_CLUSTER); 1721 } 1722 1723 if (cpu->reset_hivecs) { 1724 cpu->reset_sctlr |= (1 << 13); 1725 } 1726 1727 if (cpu->cfgend) { 1728 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1729 cpu->reset_sctlr |= SCTLR_EE; 1730 } else { 1731 cpu->reset_sctlr |= SCTLR_B; 1732 } 1733 } 1734 1735 if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) { 1736 /* If the has_el3 CPU property is disabled then we need to disable the 1737 * feature. 1738 */ 1739 unset_feature(env, ARM_FEATURE_EL3); 1740 1741 /* Disable the security extension feature bits in the processor feature 1742 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. 1743 */ 1744 cpu->isar.id_pfr1 &= ~0xf0; 1745 cpu->isar.id_aa64pfr0 &= ~0xf000; 1746 } 1747 1748 if (!cpu->has_el2) { 1749 unset_feature(env, ARM_FEATURE_EL2); 1750 } 1751 1752 if (!cpu->has_pmu) { 1753 unset_feature(env, ARM_FEATURE_PMU); 1754 } 1755 if (arm_feature(env, ARM_FEATURE_PMU)) { 1756 pmu_init(cpu); 1757 1758 if (!kvm_enabled()) { 1759 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); 1760 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); 1761 } 1762 1763 #ifndef CONFIG_USER_ONLY 1764 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, 1765 cpu); 1766 #endif 1767 } else { 1768 cpu->isar.id_aa64dfr0 = 1769 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); 1770 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0); 1771 cpu->pmceid0 = 0; 1772 cpu->pmceid1 = 0; 1773 } 1774 1775 if (!arm_feature(env, ARM_FEATURE_EL2)) { 1776 /* Disable the hypervisor feature bits in the processor feature 1777 * registers if we don't have EL2. These are id_pfr1[15:12] and 1778 * id_aa64pfr0_el1[11:8]. 1779 */ 1780 cpu->isar.id_aa64pfr0 &= ~0xf00; 1781 cpu->isar.id_pfr1 &= ~0xf000; 1782 } 1783 1784 #ifndef CONFIG_USER_ONLY 1785 if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) { 1786 /* 1787 * Disable the MTE feature bits if we do not have tag-memory 1788 * provided by the machine. 1789 */ 1790 cpu->isar.id_aa64pfr1 = 1791 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); 1792 } 1793 #endif 1794 1795 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 1796 * to false or by setting pmsav7-dregion to 0. 1797 */ 1798 if (!cpu->has_mpu) { 1799 cpu->pmsav7_dregion = 0; 1800 } 1801 if (cpu->pmsav7_dregion == 0) { 1802 cpu->has_mpu = false; 1803 } 1804 1805 if (arm_feature(env, ARM_FEATURE_PMSA) && 1806 arm_feature(env, ARM_FEATURE_V7)) { 1807 uint32_t nr = cpu->pmsav7_dregion; 1808 1809 if (nr > 0xff) { 1810 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 1811 return; 1812 } 1813 1814 if (nr) { 1815 if (arm_feature(env, ARM_FEATURE_V8)) { 1816 /* PMSAv8 */ 1817 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 1818 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 1819 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1820 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 1821 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 1822 } 1823 } else { 1824 env->pmsav7.drbar = g_new0(uint32_t, nr); 1825 env->pmsav7.drsr = g_new0(uint32_t, nr); 1826 env->pmsav7.dracr = g_new0(uint32_t, nr); 1827 } 1828 } 1829 } 1830 1831 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1832 uint32_t nr = cpu->sau_sregion; 1833 1834 if (nr > 0xff) { 1835 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 1836 return; 1837 } 1838 1839 if (nr) { 1840 env->sau.rbar = g_new0(uint32_t, nr); 1841 env->sau.rlar = g_new0(uint32_t, nr); 1842 } 1843 } 1844 1845 if (arm_feature(env, ARM_FEATURE_EL3)) { 1846 set_feature(env, ARM_FEATURE_VBAR); 1847 } 1848 1849 register_cp_regs_for_features(cpu); 1850 arm_cpu_register_gdb_regs_for_features(cpu); 1851 1852 init_cpreg_list(cpu); 1853 1854 #ifndef CONFIG_USER_ONLY 1855 MachineState *ms = MACHINE(qdev_get_machine()); 1856 unsigned int smp_cpus = ms->smp.cpus; 1857 bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY); 1858 1859 /* 1860 * We must set cs->num_ases to the final value before 1861 * the first call to cpu_address_space_init. 1862 */ 1863 if (cpu->tag_memory != NULL) { 1864 cs->num_ases = 3 + has_secure; 1865 } else { 1866 cs->num_ases = 1 + has_secure; 1867 } 1868 1869 if (has_secure) { 1870 if (!cpu->secure_memory) { 1871 cpu->secure_memory = cs->memory; 1872 } 1873 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 1874 cpu->secure_memory); 1875 } 1876 1877 if (cpu->tag_memory != NULL) { 1878 cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory", 1879 cpu->tag_memory); 1880 if (has_secure) { 1881 cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory", 1882 cpu->secure_tag_memory); 1883 } 1884 } 1885 1886 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 1887 1888 /* No core_count specified, default to smp_cpus. */ 1889 if (cpu->core_count == -1) { 1890 cpu->core_count = smp_cpus; 1891 } 1892 #endif 1893 1894 if (tcg_enabled()) { 1895 int dcz_blocklen = 4 << cpu->dcz_blocksize; 1896 1897 /* 1898 * We only support DCZ blocklen that fits on one page. 1899 * 1900 * Architectually this is always true. However TARGET_PAGE_SIZE 1901 * is variable and, for compatibility with -machine virt-2.7, 1902 * is only 1KiB, as an artifact of legacy ARMv5 subpage support. 1903 * But even then, while the largest architectural DCZ blocklen 1904 * is 2KiB, no cpu actually uses such a large blocklen. 1905 */ 1906 assert(dcz_blocklen <= TARGET_PAGE_SIZE); 1907 1908 /* 1909 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say 1910 * both nibbles of each byte storing tag data may be written at once. 1911 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32. 1912 */ 1913 if (cpu_isar_feature(aa64_mte, cpu)) { 1914 assert(dcz_blocklen >= 2 * TAG_GRANULE); 1915 } 1916 } 1917 1918 qemu_init_vcpu(cs); 1919 cpu_reset(cs); 1920 1921 acc->parent_realize(dev, errp); 1922 } 1923 1924 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 1925 { 1926 ObjectClass *oc; 1927 char *typename; 1928 char **cpuname; 1929 const char *cpunamestr; 1930 1931 cpuname = g_strsplit(cpu_model, ",", 1); 1932 cpunamestr = cpuname[0]; 1933 #ifdef CONFIG_USER_ONLY 1934 /* For backwards compatibility usermode emulation allows "-cpu any", 1935 * which has the same semantics as "-cpu max". 1936 */ 1937 if (!strcmp(cpunamestr, "any")) { 1938 cpunamestr = "max"; 1939 } 1940 #endif 1941 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 1942 oc = object_class_by_name(typename); 1943 g_strfreev(cpuname); 1944 g_free(typename); 1945 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 1946 object_class_is_abstract(oc)) { 1947 return NULL; 1948 } 1949 return oc; 1950 } 1951 1952 static Property arm_cpu_properties[] = { 1953 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), 1954 DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), 1955 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 1956 mp_affinity, ARM64_AFFINITY_INVALID), 1957 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 1958 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 1959 DEFINE_PROP_END_OF_LIST() 1960 }; 1961 1962 static gchar *arm_gdb_arch_name(CPUState *cs) 1963 { 1964 ARMCPU *cpu = ARM_CPU(cs); 1965 CPUARMState *env = &cpu->env; 1966 1967 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 1968 return g_strdup("iwmmxt"); 1969 } 1970 return g_strdup("arm"); 1971 } 1972 1973 #ifndef CONFIG_USER_ONLY 1974 #include "hw/core/sysemu-cpu-ops.h" 1975 1976 static const struct SysemuCPUOps arm_sysemu_ops = { 1977 .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug, 1978 .asidx_from_attrs = arm_asidx_from_attrs, 1979 .write_elf32_note = arm_cpu_write_elf32_note, 1980 .write_elf64_note = arm_cpu_write_elf64_note, 1981 .virtio_is_big_endian = arm_cpu_virtio_is_big_endian, 1982 .legacy_vmsd = &vmstate_arm_cpu, 1983 }; 1984 #endif 1985 1986 #ifdef CONFIG_TCG 1987 static const struct TCGCPUOps arm_tcg_ops = { 1988 .initialize = arm_translate_init, 1989 .synchronize_from_tb = arm_cpu_synchronize_from_tb, 1990 .cpu_exec_interrupt = arm_cpu_exec_interrupt, 1991 .tlb_fill = arm_cpu_tlb_fill, 1992 .debug_excp_handler = arm_debug_excp_handler, 1993 1994 #if !defined(CONFIG_USER_ONLY) 1995 .do_interrupt = arm_cpu_do_interrupt, 1996 .do_transaction_failed = arm_cpu_do_transaction_failed, 1997 .do_unaligned_access = arm_cpu_do_unaligned_access, 1998 .adjust_watchpoint_address = arm_adjust_watchpoint_address, 1999 .debug_check_watchpoint = arm_debug_check_watchpoint, 2000 .debug_check_breakpoint = arm_debug_check_breakpoint, 2001 #endif /* !CONFIG_USER_ONLY */ 2002 }; 2003 #endif /* CONFIG_TCG */ 2004 2005 static void arm_cpu_class_init(ObjectClass *oc, void *data) 2006 { 2007 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2008 CPUClass *cc = CPU_CLASS(acc); 2009 DeviceClass *dc = DEVICE_CLASS(oc); 2010 2011 device_class_set_parent_realize(dc, arm_cpu_realizefn, 2012 &acc->parent_realize); 2013 2014 device_class_set_props(dc, arm_cpu_properties); 2015 device_class_set_parent_reset(dc, arm_cpu_reset, &acc->parent_reset); 2016 2017 cc->class_by_name = arm_cpu_class_by_name; 2018 cc->has_work = arm_cpu_has_work; 2019 cc->dump_state = arm_cpu_dump_state; 2020 cc->set_pc = arm_cpu_set_pc; 2021 cc->gdb_read_register = arm_cpu_gdb_read_register; 2022 cc->gdb_write_register = arm_cpu_gdb_write_register; 2023 #ifndef CONFIG_USER_ONLY 2024 cc->sysemu_ops = &arm_sysemu_ops; 2025 #endif 2026 cc->gdb_num_core_regs = 26; 2027 cc->gdb_core_xml_file = "arm-core.xml"; 2028 cc->gdb_arch_name = arm_gdb_arch_name; 2029 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; 2030 cc->gdb_stop_before_watchpoint = true; 2031 cc->disas_set_info = arm_disas_set_info; 2032 2033 #ifdef CONFIG_TCG 2034 cc->tcg_ops = &arm_tcg_ops; 2035 #endif /* CONFIG_TCG */ 2036 } 2037 2038 #ifdef CONFIG_KVM 2039 static void arm_host_initfn(Object *obj) 2040 { 2041 ARMCPU *cpu = ARM_CPU(obj); 2042 2043 kvm_arm_set_cpu_features_from_host(cpu); 2044 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 2045 aarch64_add_sve_properties(obj); 2046 } 2047 arm_cpu_post_init(obj); 2048 } 2049 2050 static const TypeInfo host_arm_cpu_type_info = { 2051 .name = TYPE_ARM_HOST_CPU, 2052 .parent = TYPE_AARCH64_CPU, 2053 .instance_init = arm_host_initfn, 2054 }; 2055 2056 #endif 2057 2058 static void arm_cpu_instance_init(Object *obj) 2059 { 2060 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 2061 2062 acc->info->initfn(obj); 2063 arm_cpu_post_init(obj); 2064 } 2065 2066 static void cpu_register_class_init(ObjectClass *oc, void *data) 2067 { 2068 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2069 2070 acc->info = data; 2071 } 2072 2073 void arm_cpu_register(const ARMCPUInfo *info) 2074 { 2075 TypeInfo type_info = { 2076 .parent = TYPE_ARM_CPU, 2077 .instance_size = sizeof(ARMCPU), 2078 .instance_align = __alignof__(ARMCPU), 2079 .instance_init = arm_cpu_instance_init, 2080 .class_size = sizeof(ARMCPUClass), 2081 .class_init = info->class_init ?: cpu_register_class_init, 2082 .class_data = (void *)info, 2083 }; 2084 2085 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2086 type_register(&type_info); 2087 g_free((void *)type_info.name); 2088 } 2089 2090 static const TypeInfo arm_cpu_type_info = { 2091 .name = TYPE_ARM_CPU, 2092 .parent = TYPE_CPU, 2093 .instance_size = sizeof(ARMCPU), 2094 .instance_align = __alignof__(ARMCPU), 2095 .instance_init = arm_cpu_initfn, 2096 .instance_finalize = arm_cpu_finalizefn, 2097 .abstract = true, 2098 .class_size = sizeof(ARMCPUClass), 2099 .class_init = arm_cpu_class_init, 2100 }; 2101 2102 static void arm_cpu_register_types(void) 2103 { 2104 type_register_static(&arm_cpu_type_info); 2105 2106 #ifdef CONFIG_KVM 2107 type_register_static(&host_arm_cpu_type_info); 2108 #endif 2109 } 2110 2111 type_init(arm_cpu_register_types) 2112