1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "qemu/cpu-float.h" 25 #include "hw/registerfields.h" 26 #include "cpu-qom.h" 27 #include "exec/cpu-defs.h" 28 #include "qapi/qapi-types-common.h" 29 30 /* ARM processors have a weak memory model */ 31 #define TCG_GUEST_DEFAULT_MO (0) 32 33 #ifdef TARGET_AARCH64 34 #define KVM_HAVE_MCE_INJECTION 1 35 #endif 36 37 #define EXCP_UDEF 1 /* undefined instruction */ 38 #define EXCP_SWI 2 /* software interrupt */ 39 #define EXCP_PREFETCH_ABORT 3 40 #define EXCP_DATA_ABORT 4 41 #define EXCP_IRQ 5 42 #define EXCP_FIQ 6 43 #define EXCP_BKPT 7 44 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 45 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 46 #define EXCP_HVC 11 /* HyperVisor Call */ 47 #define EXCP_HYP_TRAP 12 48 #define EXCP_SMC 13 /* Secure Monitor Call */ 49 #define EXCP_VIRQ 14 50 #define EXCP_VFIQ 15 51 #define EXCP_SEMIHOST 16 /* semihosting call */ 52 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 53 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 54 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 55 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ 56 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ 57 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ 58 #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ 59 #define EXCP_VSERR 24 60 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 61 62 #define ARMV7M_EXCP_RESET 1 63 #define ARMV7M_EXCP_NMI 2 64 #define ARMV7M_EXCP_HARD 3 65 #define ARMV7M_EXCP_MEM 4 66 #define ARMV7M_EXCP_BUS 5 67 #define ARMV7M_EXCP_USAGE 6 68 #define ARMV7M_EXCP_SECURE 7 69 #define ARMV7M_EXCP_SVC 11 70 #define ARMV7M_EXCP_DEBUG 12 71 #define ARMV7M_EXCP_PENDSV 14 72 #define ARMV7M_EXCP_SYSTICK 15 73 74 /* For M profile, some registers are banked secure vs non-secure; 75 * these are represented as a 2-element array where the first element 76 * is the non-secure copy and the second is the secure copy. 77 * When the CPU does not have implement the security extension then 78 * only the first element is used. 79 * This means that the copy for the current security state can be 80 * accessed via env->registerfield[env->v7m.secure] (whether the security 81 * extension is implemented or not). 82 */ 83 enum { 84 M_REG_NS = 0, 85 M_REG_S = 1, 86 M_REG_NUM_BANKS = 2, 87 }; 88 89 /* ARM-specific interrupt pending bits. */ 90 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 91 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 92 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 93 #define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0 94 95 /* The usual mapping for an AArch64 system register to its AArch32 96 * counterpart is for the 32 bit world to have access to the lower 97 * half only (with writes leaving the upper half untouched). It's 98 * therefore useful to be able to pass TCG the offset of the least 99 * significant half of a uint64_t struct member. 100 */ 101 #if HOST_BIG_ENDIAN 102 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 103 #define offsetofhigh32(S, M) offsetof(S, M) 104 #else 105 #define offsetoflow32(S, M) offsetof(S, M) 106 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 107 #endif 108 109 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 110 #define ARM_CPU_IRQ 0 111 #define ARM_CPU_FIQ 1 112 #define ARM_CPU_VIRQ 2 113 #define ARM_CPU_VFIQ 3 114 115 /* ARM-specific extra insn start words: 116 * 1: Conditional execution bits 117 * 2: Partial exception syndrome for data aborts 118 */ 119 #define TARGET_INSN_START_EXTRA_WORDS 2 120 121 /* The 2nd extra word holding syndrome info for data aborts does not use 122 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 123 * help the sleb128 encoder do a better job. 124 * When restoring the CPU state, we shift it back up. 125 */ 126 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 127 #define ARM_INSN_START_WORD2_SHIFT 14 128 129 /* We currently assume float and double are IEEE single and double 130 precision respectively. 131 Doing runtime conversions is tricky because VFP registers may contain 132 integer values (eg. as the result of a FTOSI instruction). 133 s<2n> maps to the least significant half of d<n> 134 s<2n+1> maps to the most significant half of d<n> 135 */ 136 137 /** 138 * DynamicGDBXMLInfo: 139 * @desc: Contains the XML descriptions. 140 * @num: Number of the registers in this XML seen by GDB. 141 * @data: A union with data specific to the set of registers 142 * @cpregs_keys: Array that contains the corresponding Key of 143 * a given cpreg with the same order of the cpreg 144 * in the XML description. 145 */ 146 typedef struct DynamicGDBXMLInfo { 147 char *desc; 148 int num; 149 union { 150 struct { 151 uint32_t *keys; 152 } cpregs; 153 } data; 154 } DynamicGDBXMLInfo; 155 156 /* CPU state for each instance of a generic timer (in cp15 c14) */ 157 typedef struct ARMGenericTimer { 158 uint64_t cval; /* Timer CompareValue register */ 159 uint64_t ctl; /* Timer Control register */ 160 } ARMGenericTimer; 161 162 #define GTIMER_PHYS 0 163 #define GTIMER_VIRT 1 164 #define GTIMER_HYP 2 165 #define GTIMER_SEC 3 166 #define GTIMER_HYPVIRT 4 167 #define NUM_GTIMERS 5 168 169 typedef struct { 170 uint64_t raw_tcr; 171 uint32_t mask; 172 uint32_t base_mask; 173 } TCR; 174 175 #define VTCR_NSW (1u << 29) 176 #define VTCR_NSA (1u << 30) 177 #define VSTCR_SW VTCR_NSW 178 #define VSTCR_SA VTCR_NSA 179 180 /* Define a maximum sized vector register. 181 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 182 * For 64-bit, this is a 2048-bit SVE register. 183 * 184 * Note that the mapping between S, D, and Q views of the register bank 185 * differs between AArch64 and AArch32. 186 * In AArch32: 187 * Qn = regs[n].d[1]:regs[n].d[0] 188 * Dn = regs[n / 2].d[n & 1] 189 * Sn = regs[n / 4].d[n % 4 / 2], 190 * bits 31..0 for even n, and bits 63..32 for odd n 191 * (and regs[16] to regs[31] are inaccessible) 192 * In AArch64: 193 * Zn = regs[n].d[*] 194 * Qn = regs[n].d[1]:regs[n].d[0] 195 * Dn = regs[n].d[0] 196 * Sn = regs[n].d[0] bits 31..0 197 * Hn = regs[n].d[0] bits 15..0 198 * 199 * This corresponds to the architecturally defined mapping between 200 * the two execution states, and means we do not need to explicitly 201 * map these registers when changing states. 202 * 203 * Align the data for use with TCG host vector operations. 204 */ 205 206 #ifdef TARGET_AARCH64 207 # define ARM_MAX_VQ 16 208 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); 209 void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); 210 void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp); 211 #else 212 # define ARM_MAX_VQ 1 213 static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { } 214 static inline void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { } 215 static inline void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) { } 216 #endif 217 218 typedef struct ARMVectorReg { 219 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 220 } ARMVectorReg; 221 222 #ifdef TARGET_AARCH64 223 /* In AArch32 mode, predicate registers do not exist at all. */ 224 typedef struct ARMPredicateReg { 225 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); 226 } ARMPredicateReg; 227 228 /* In AArch32 mode, PAC keys do not exist at all. */ 229 typedef struct ARMPACKey { 230 uint64_t lo, hi; 231 } ARMPACKey; 232 #endif 233 234 /* See the commentary above the TBFLAG field definitions. */ 235 typedef struct CPUARMTBFlags { 236 uint32_t flags; 237 target_ulong flags2; 238 } CPUARMTBFlags; 239 240 typedef struct CPUArchState { 241 /* Regs for current mode. */ 242 uint32_t regs[16]; 243 244 /* 32/64 switch only happens when taking and returning from 245 * exceptions so the overlap semantics are taken care of then 246 * instead of having a complicated union. 247 */ 248 /* Regs for A64 mode. */ 249 uint64_t xregs[32]; 250 uint64_t pc; 251 /* PSTATE isn't an architectural register for ARMv8. However, it is 252 * convenient for us to assemble the underlying state into a 32 bit format 253 * identical to the architectural format used for the SPSR. (This is also 254 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 255 * 'pstate' register are.) Of the PSTATE bits: 256 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 257 * semantics as for AArch32, as described in the comments on each field) 258 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 259 * DAIF (exception masks) are kept in env->daif 260 * BTYPE is kept in env->btype 261 * all other bits are stored in their correct places in env->pstate 262 */ 263 uint32_t pstate; 264 bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nRW */ 265 bool thumb; /* True if CPU is in thumb mode; cpsr[5] */ 266 267 /* Cached TBFLAGS state. See below for which bits are included. */ 268 CPUARMTBFlags hflags; 269 270 /* Frequently accessed CPSR bits are stored separately for efficiency. 271 This contains all the other bits. Use cpsr_{read,write} to access 272 the whole CPSR. */ 273 uint32_t uncached_cpsr; 274 uint32_t spsr; 275 276 /* Banked registers. */ 277 uint64_t banked_spsr[8]; 278 uint32_t banked_r13[8]; 279 uint32_t banked_r14[8]; 280 281 /* These hold r8-r12. */ 282 uint32_t usr_regs[5]; 283 uint32_t fiq_regs[5]; 284 285 /* cpsr flag cache for faster execution */ 286 uint32_t CF; /* 0 or 1 */ 287 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 288 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 289 uint32_t ZF; /* Z set if zero. */ 290 uint32_t QF; /* 0 or 1 */ 291 uint32_t GE; /* cpsr[19:16] */ 292 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 293 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 294 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 295 296 uint64_t elr_el[4]; /* AArch64 exception link regs */ 297 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 298 299 /* System control coprocessor (cp15) */ 300 struct { 301 uint32_t c0_cpuid; 302 union { /* Cache size selection */ 303 struct { 304 uint64_t _unused_csselr0; 305 uint64_t csselr_ns; 306 uint64_t _unused_csselr1; 307 uint64_t csselr_s; 308 }; 309 uint64_t csselr_el[4]; 310 }; 311 union { /* System control register. */ 312 struct { 313 uint64_t _unused_sctlr; 314 uint64_t sctlr_ns; 315 uint64_t hsctlr; 316 uint64_t sctlr_s; 317 }; 318 uint64_t sctlr_el[4]; 319 }; 320 uint64_t cpacr_el1; /* Architectural feature access control register */ 321 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 322 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 323 uint64_t sder; /* Secure debug enable register. */ 324 uint32_t nsacr; /* Non-secure access control register. */ 325 union { /* MMU translation table base 0. */ 326 struct { 327 uint64_t _unused_ttbr0_0; 328 uint64_t ttbr0_ns; 329 uint64_t _unused_ttbr0_1; 330 uint64_t ttbr0_s; 331 }; 332 uint64_t ttbr0_el[4]; 333 }; 334 union { /* MMU translation table base 1. */ 335 struct { 336 uint64_t _unused_ttbr1_0; 337 uint64_t ttbr1_ns; 338 uint64_t _unused_ttbr1_1; 339 uint64_t ttbr1_s; 340 }; 341 uint64_t ttbr1_el[4]; 342 }; 343 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 344 uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ 345 /* MMU translation table base control. */ 346 TCR tcr_el[4]; 347 TCR vtcr_el2; /* Virtualization Translation Control. */ 348 TCR vstcr_el2; /* Secure Virtualization Translation Control. */ 349 uint32_t c2_data; /* MPU data cacheable bits. */ 350 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 351 union { /* MMU domain access control register 352 * MPU write buffer control. 353 */ 354 struct { 355 uint64_t dacr_ns; 356 uint64_t dacr_s; 357 }; 358 struct { 359 uint64_t dacr32_el2; 360 }; 361 }; 362 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 363 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 364 uint64_t hcr_el2; /* Hypervisor configuration register */ 365 uint64_t hcrx_el2; /* Extended Hypervisor configuration register */ 366 uint64_t scr_el3; /* Secure configuration register. */ 367 union { /* Fault status registers. */ 368 struct { 369 uint64_t ifsr_ns; 370 uint64_t ifsr_s; 371 }; 372 struct { 373 uint64_t ifsr32_el2; 374 }; 375 }; 376 union { 377 struct { 378 uint64_t _unused_dfsr; 379 uint64_t dfsr_ns; 380 uint64_t hsr; 381 uint64_t dfsr_s; 382 }; 383 uint64_t esr_el[4]; 384 }; 385 uint32_t c6_region[8]; /* MPU base/size registers. */ 386 union { /* Fault address registers. */ 387 struct { 388 uint64_t _unused_far0; 389 #if HOST_BIG_ENDIAN 390 uint32_t ifar_ns; 391 uint32_t dfar_ns; 392 uint32_t ifar_s; 393 uint32_t dfar_s; 394 #else 395 uint32_t dfar_ns; 396 uint32_t ifar_ns; 397 uint32_t dfar_s; 398 uint32_t ifar_s; 399 #endif 400 uint64_t _unused_far3; 401 }; 402 uint64_t far_el[4]; 403 }; 404 uint64_t hpfar_el2; 405 uint64_t hstr_el2; 406 union { /* Translation result. */ 407 struct { 408 uint64_t _unused_par_0; 409 uint64_t par_ns; 410 uint64_t _unused_par_1; 411 uint64_t par_s; 412 }; 413 uint64_t par_el[4]; 414 }; 415 416 uint32_t c9_insn; /* Cache lockdown registers. */ 417 uint32_t c9_data; 418 uint64_t c9_pmcr; /* performance monitor control register */ 419 uint64_t c9_pmcnten; /* perf monitor counter enables */ 420 uint64_t c9_pmovsr; /* perf monitor overflow status */ 421 uint64_t c9_pmuserenr; /* perf monitor user enable */ 422 uint64_t c9_pmselr; /* perf monitor counter selection register */ 423 uint64_t c9_pminten; /* perf monitor interrupt enables */ 424 union { /* Memory attribute redirection */ 425 struct { 426 #if HOST_BIG_ENDIAN 427 uint64_t _unused_mair_0; 428 uint32_t mair1_ns; 429 uint32_t mair0_ns; 430 uint64_t _unused_mair_1; 431 uint32_t mair1_s; 432 uint32_t mair0_s; 433 #else 434 uint64_t _unused_mair_0; 435 uint32_t mair0_ns; 436 uint32_t mair1_ns; 437 uint64_t _unused_mair_1; 438 uint32_t mair0_s; 439 uint32_t mair1_s; 440 #endif 441 }; 442 uint64_t mair_el[4]; 443 }; 444 union { /* vector base address register */ 445 struct { 446 uint64_t _unused_vbar; 447 uint64_t vbar_ns; 448 uint64_t hvbar; 449 uint64_t vbar_s; 450 }; 451 uint64_t vbar_el[4]; 452 }; 453 uint32_t mvbar; /* (monitor) vector base address register */ 454 uint64_t rvbar; /* rvbar sampled from rvbar property at reset */ 455 struct { /* FCSE PID. */ 456 uint32_t fcseidr_ns; 457 uint32_t fcseidr_s; 458 }; 459 union { /* Context ID. */ 460 struct { 461 uint64_t _unused_contextidr_0; 462 uint64_t contextidr_ns; 463 uint64_t _unused_contextidr_1; 464 uint64_t contextidr_s; 465 }; 466 uint64_t contextidr_el[4]; 467 }; 468 union { /* User RW Thread register. */ 469 struct { 470 uint64_t tpidrurw_ns; 471 uint64_t tpidrprw_ns; 472 uint64_t htpidr; 473 uint64_t _tpidr_el3; 474 }; 475 uint64_t tpidr_el[4]; 476 }; 477 /* The secure banks of these registers don't map anywhere */ 478 uint64_t tpidrurw_s; 479 uint64_t tpidrprw_s; 480 uint64_t tpidruro_s; 481 482 union { /* User RO Thread register. */ 483 uint64_t tpidruro_ns; 484 uint64_t tpidrro_el[1]; 485 }; 486 uint64_t c14_cntfrq; /* Counter Frequency register */ 487 uint64_t c14_cntkctl; /* Timer Control register */ 488 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 489 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 490 ARMGenericTimer c14_timer[NUM_GTIMERS]; 491 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 492 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 493 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 494 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 495 uint32_t c15_threadid; /* TI debugger thread-ID. */ 496 uint32_t c15_config_base_address; /* SCU base address. */ 497 uint32_t c15_diagnostic; /* diagnostic register */ 498 uint32_t c15_power_diagnostic; 499 uint32_t c15_power_control; /* power control */ 500 uint64_t dbgbvr[16]; /* breakpoint value registers */ 501 uint64_t dbgbcr[16]; /* breakpoint control registers */ 502 uint64_t dbgwvr[16]; /* watchpoint value registers */ 503 uint64_t dbgwcr[16]; /* watchpoint control registers */ 504 uint64_t mdscr_el1; 505 uint64_t oslsr_el1; /* OS Lock Status */ 506 uint64_t mdcr_el2; 507 uint64_t mdcr_el3; 508 /* Stores the architectural value of the counter *the last time it was 509 * updated* by pmccntr_op_start. Accesses should always be surrounded 510 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 511 * architecturally-correct value is being read/set. 512 */ 513 uint64_t c15_ccnt; 514 /* Stores the delta between the architectural value and the underlying 515 * cycle count during normal operation. It is used to update c15_ccnt 516 * to be the correct architectural value before accesses. During 517 * accesses, c15_ccnt_delta contains the underlying count being used 518 * for the access, after which it reverts to the delta value in 519 * pmccntr_op_finish. 520 */ 521 uint64_t c15_ccnt_delta; 522 uint64_t c14_pmevcntr[31]; 523 uint64_t c14_pmevcntr_delta[31]; 524 uint64_t c14_pmevtyper[31]; 525 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 526 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 527 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 528 uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ 529 uint64_t gcr_el1; 530 uint64_t rgsr_el1; 531 532 /* Minimal RAS registers */ 533 uint64_t disr_el1; 534 uint64_t vdisr_el2; 535 uint64_t vsesr_el2; 536 } cp15; 537 538 struct { 539 /* M profile has up to 4 stack pointers: 540 * a Main Stack Pointer and a Process Stack Pointer for each 541 * of the Secure and Non-Secure states. (If the CPU doesn't support 542 * the security extension then it has only two SPs.) 543 * In QEMU we always store the currently active SP in regs[13], 544 * and the non-active SP for the current security state in 545 * v7m.other_sp. The stack pointers for the inactive security state 546 * are stored in other_ss_msp and other_ss_psp. 547 * switch_v7m_security_state() is responsible for rearranging them 548 * when we change security state. 549 */ 550 uint32_t other_sp; 551 uint32_t other_ss_msp; 552 uint32_t other_ss_psp; 553 uint32_t vecbase[M_REG_NUM_BANKS]; 554 uint32_t basepri[M_REG_NUM_BANKS]; 555 uint32_t control[M_REG_NUM_BANKS]; 556 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 557 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 558 uint32_t hfsr; /* HardFault Status */ 559 uint32_t dfsr; /* Debug Fault Status Register */ 560 uint32_t sfsr; /* Secure Fault Status Register */ 561 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 562 uint32_t bfar; /* BusFault Address */ 563 uint32_t sfar; /* Secure Fault Address Register */ 564 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 565 int exception; 566 uint32_t primask[M_REG_NUM_BANKS]; 567 uint32_t faultmask[M_REG_NUM_BANKS]; 568 uint32_t aircr; /* only holds r/w state if security extn implemented */ 569 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 570 uint32_t csselr[M_REG_NUM_BANKS]; 571 uint32_t scr[M_REG_NUM_BANKS]; 572 uint32_t msplim[M_REG_NUM_BANKS]; 573 uint32_t psplim[M_REG_NUM_BANKS]; 574 uint32_t fpcar[M_REG_NUM_BANKS]; 575 uint32_t fpccr[M_REG_NUM_BANKS]; 576 uint32_t fpdscr[M_REG_NUM_BANKS]; 577 uint32_t cpacr[M_REG_NUM_BANKS]; 578 uint32_t nsacr; 579 uint32_t ltpsize; 580 uint32_t vpr; 581 } v7m; 582 583 /* Information associated with an exception about to be taken: 584 * code which raises an exception must set cs->exception_index and 585 * the relevant parts of this structure; the cpu_do_interrupt function 586 * will then set the guest-visible registers as part of the exception 587 * entry process. 588 */ 589 struct { 590 uint32_t syndrome; /* AArch64 format syndrome register */ 591 uint32_t fsr; /* AArch32 format fault status register info */ 592 uint64_t vaddress; /* virtual addr associated with exception, if any */ 593 uint32_t target_el; /* EL the exception should be targeted for */ 594 /* If we implement EL2 we will also need to store information 595 * about the intermediate physical address for stage 2 faults. 596 */ 597 } exception; 598 599 /* Information associated with an SError */ 600 struct { 601 uint8_t pending; 602 uint8_t has_esr; 603 uint64_t esr; 604 } serror; 605 606 uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */ 607 608 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 609 uint32_t irq_line_state; 610 611 /* Thumb-2 EE state. */ 612 uint32_t teecr; 613 uint32_t teehbr; 614 615 /* VFP coprocessor state. */ 616 struct { 617 ARMVectorReg zregs[32]; 618 619 #ifdef TARGET_AARCH64 620 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 621 #define FFR_PRED_NUM 16 622 ARMPredicateReg pregs[17]; 623 /* Scratch space for aa64 sve predicate temporary. */ 624 ARMPredicateReg preg_tmp; 625 #endif 626 627 /* We store these fpcsr fields separately for convenience. */ 628 uint32_t qc[4] QEMU_ALIGNED(16); 629 int vec_len; 630 int vec_stride; 631 632 uint32_t xregs[16]; 633 634 /* Scratch space for aa32 neon expansion. */ 635 uint32_t scratch[8]; 636 637 /* There are a number of distinct float control structures: 638 * 639 * fp_status: is the "normal" fp status. 640 * fp_status_fp16: used for half-precision calculations 641 * standard_fp_status : the ARM "Standard FPSCR Value" 642 * standard_fp_status_fp16 : used for half-precision 643 * calculations with the ARM "Standard FPSCR Value" 644 * 645 * Half-precision operations are governed by a separate 646 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 647 * status structure to control this. 648 * 649 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 650 * round-to-nearest and is used by any operations (generally 651 * Neon) which the architecture defines as controlled by the 652 * standard FPSCR value rather than the FPSCR. 653 * 654 * The "standard FPSCR but for fp16 ops" is needed because 655 * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than 656 * using a fixed value for it. 657 * 658 * To avoid having to transfer exception bits around, we simply 659 * say that the FPSCR cumulative exception flags are the logical 660 * OR of the flags in the four fp statuses. This relies on the 661 * only thing which needs to read the exception flags being 662 * an explicit FPSCR read. 663 */ 664 float_status fp_status; 665 float_status fp_status_f16; 666 float_status standard_fp_status; 667 float_status standard_fp_status_f16; 668 669 /* ZCR_EL[1-3] */ 670 uint64_t zcr_el[4]; 671 } vfp; 672 uint64_t exclusive_addr; 673 uint64_t exclusive_val; 674 uint64_t exclusive_high; 675 676 /* iwMMXt coprocessor state. */ 677 struct { 678 uint64_t regs[16]; 679 uint64_t val; 680 681 uint32_t cregs[16]; 682 } iwmmxt; 683 684 #ifdef TARGET_AARCH64 685 struct { 686 ARMPACKey apia; 687 ARMPACKey apib; 688 ARMPACKey apda; 689 ARMPACKey apdb; 690 ARMPACKey apga; 691 } keys; 692 693 uint64_t scxtnum_el[4]; 694 #endif 695 696 #if defined(CONFIG_USER_ONLY) 697 /* For usermode syscall translation. */ 698 int eabi; 699 #endif 700 701 struct CPUBreakpoint *cpu_breakpoint[16]; 702 struct CPUWatchpoint *cpu_watchpoint[16]; 703 704 /* Fields up to this point are cleared by a CPU reset */ 705 struct {} end_reset_fields; 706 707 /* Fields after this point are preserved across CPU reset. */ 708 709 /* Internal CPU feature flags. */ 710 uint64_t features; 711 712 /* PMSAv7 MPU */ 713 struct { 714 uint32_t *drbar; 715 uint32_t *drsr; 716 uint32_t *dracr; 717 uint32_t rnr[M_REG_NUM_BANKS]; 718 } pmsav7; 719 720 /* PMSAv8 MPU */ 721 struct { 722 /* The PMSAv8 implementation also shares some PMSAv7 config 723 * and state: 724 * pmsav7.rnr (region number register) 725 * pmsav7_dregion (number of configured regions) 726 */ 727 uint32_t *rbar[M_REG_NUM_BANKS]; 728 uint32_t *rlar[M_REG_NUM_BANKS]; 729 uint32_t mair0[M_REG_NUM_BANKS]; 730 uint32_t mair1[M_REG_NUM_BANKS]; 731 } pmsav8; 732 733 /* v8M SAU */ 734 struct { 735 uint32_t *rbar; 736 uint32_t *rlar; 737 uint32_t rnr; 738 uint32_t ctrl; 739 } sau; 740 741 void *nvic; 742 const struct arm_boot_info *boot_info; 743 /* Store GICv3CPUState to access from this struct */ 744 void *gicv3state; 745 746 #ifdef TARGET_TAGGED_ADDRESSES 747 /* Linux syscall tagged address support */ 748 bool tagged_addr_enable; 749 #endif 750 } CPUARMState; 751 752 static inline void set_feature(CPUARMState *env, int feature) 753 { 754 env->features |= 1ULL << feature; 755 } 756 757 static inline void unset_feature(CPUARMState *env, int feature) 758 { 759 env->features &= ~(1ULL << feature); 760 } 761 762 /** 763 * ARMELChangeHookFn: 764 * type of a function which can be registered via arm_register_el_change_hook() 765 * to get callbacks when the CPU changes its exception level or mode. 766 */ 767 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 768 typedef struct ARMELChangeHook ARMELChangeHook; 769 struct ARMELChangeHook { 770 ARMELChangeHookFn *hook; 771 void *opaque; 772 QLIST_ENTRY(ARMELChangeHook) node; 773 }; 774 775 /* These values map onto the return values for 776 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 777 typedef enum ARMPSCIState { 778 PSCI_ON = 0, 779 PSCI_OFF = 1, 780 PSCI_ON_PENDING = 2 781 } ARMPSCIState; 782 783 typedef struct ARMISARegisters ARMISARegisters; 784 785 /** 786 * ARMCPU: 787 * @env: #CPUARMState 788 * 789 * An ARM CPU core. 790 */ 791 struct ArchCPU { 792 /*< private >*/ 793 CPUState parent_obj; 794 /*< public >*/ 795 796 CPUNegativeOffsetState neg; 797 CPUARMState env; 798 799 /* Coprocessor information */ 800 GHashTable *cp_regs; 801 /* For marshalling (mostly coprocessor) register state between the 802 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 803 * we use these arrays. 804 */ 805 /* List of register indexes managed via these arrays; (full KVM style 806 * 64 bit indexes, not CPRegInfo 32 bit indexes) 807 */ 808 uint64_t *cpreg_indexes; 809 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 810 uint64_t *cpreg_values; 811 /* Length of the indexes, values, reset_values arrays */ 812 int32_t cpreg_array_len; 813 /* These are used only for migration: incoming data arrives in 814 * these fields and is sanity checked in post_load before copying 815 * to the working data structures above. 816 */ 817 uint64_t *cpreg_vmstate_indexes; 818 uint64_t *cpreg_vmstate_values; 819 int32_t cpreg_vmstate_array_len; 820 821 DynamicGDBXMLInfo dyn_sysreg_xml; 822 DynamicGDBXMLInfo dyn_svereg_xml; 823 824 /* Timers used by the generic (architected) timer */ 825 QEMUTimer *gt_timer[NUM_GTIMERS]; 826 /* 827 * Timer used by the PMU. Its state is restored after migration by 828 * pmu_op_finish() - it does not need other handling during migration 829 */ 830 QEMUTimer *pmu_timer; 831 /* GPIO outputs for generic timer */ 832 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 833 /* GPIO output for GICv3 maintenance interrupt signal */ 834 qemu_irq gicv3_maintenance_interrupt; 835 /* GPIO output for the PMU interrupt */ 836 qemu_irq pmu_interrupt; 837 838 /* MemoryRegion to use for secure physical accesses */ 839 MemoryRegion *secure_memory; 840 841 /* MemoryRegion to use for allocation tag accesses */ 842 MemoryRegion *tag_memory; 843 MemoryRegion *secure_tag_memory; 844 845 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 846 Object *idau; 847 848 /* 'compatible' string for this CPU for Linux device trees */ 849 const char *dtb_compatible; 850 851 /* PSCI version for this CPU 852 * Bits[31:16] = Major Version 853 * Bits[15:0] = Minor Version 854 */ 855 uint32_t psci_version; 856 857 /* Current power state, access guarded by BQL */ 858 ARMPSCIState power_state; 859 860 /* CPU has virtualization extension */ 861 bool has_el2; 862 /* CPU has security extension */ 863 bool has_el3; 864 /* CPU has PMU (Performance Monitor Unit) */ 865 bool has_pmu; 866 /* CPU has VFP */ 867 bool has_vfp; 868 /* CPU has Neon */ 869 bool has_neon; 870 /* CPU has M-profile DSP extension */ 871 bool has_dsp; 872 873 /* CPU has memory protection unit */ 874 bool has_mpu; 875 /* PMSAv7 MPU number of supported regions */ 876 uint32_t pmsav7_dregion; 877 /* v8M SAU number of supported regions */ 878 uint32_t sau_sregion; 879 880 /* PSCI conduit used to invoke PSCI methods 881 * 0 - disabled, 1 - smc, 2 - hvc 882 */ 883 uint32_t psci_conduit; 884 885 /* For v8M, initial value of the Secure VTOR */ 886 uint32_t init_svtor; 887 /* For v8M, initial value of the Non-secure VTOR */ 888 uint32_t init_nsvtor; 889 890 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 891 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 892 */ 893 uint32_t kvm_target; 894 895 /* KVM init features for this CPU */ 896 uint32_t kvm_init_features[7]; 897 898 /* KVM CPU state */ 899 900 /* KVM virtual time adjustment */ 901 bool kvm_adjvtime; 902 bool kvm_vtime_dirty; 903 uint64_t kvm_vtime; 904 905 /* KVM steal time */ 906 OnOffAuto kvm_steal_time; 907 908 /* Uniprocessor system with MP extensions */ 909 bool mp_is_up; 910 911 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 912 * and the probe failed (so we need to report the error in realize) 913 */ 914 bool host_cpu_probe_failed; 915 916 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 917 * register. 918 */ 919 int32_t core_count; 920 921 /* The instance init functions for implementation-specific subclasses 922 * set these fields to specify the implementation-dependent values of 923 * various constant registers and reset values of non-constant 924 * registers. 925 * Some of these might become QOM properties eventually. 926 * Field names match the official register names as defined in the 927 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 928 * is used for reset values of non-constant registers; no reset_ 929 * prefix means a constant register. 930 * Some of these registers are split out into a substructure that 931 * is shared with the translators to control the ISA. 932 * 933 * Note that if you add an ID register to the ARMISARegisters struct 934 * you need to also update the 32-bit and 64-bit versions of the 935 * kvm_arm_get_host_cpu_features() function to correctly populate the 936 * field by reading the value from the KVM vCPU. 937 */ 938 struct ARMISARegisters { 939 uint32_t id_isar0; 940 uint32_t id_isar1; 941 uint32_t id_isar2; 942 uint32_t id_isar3; 943 uint32_t id_isar4; 944 uint32_t id_isar5; 945 uint32_t id_isar6; 946 uint32_t id_mmfr0; 947 uint32_t id_mmfr1; 948 uint32_t id_mmfr2; 949 uint32_t id_mmfr3; 950 uint32_t id_mmfr4; 951 uint32_t id_pfr0; 952 uint32_t id_pfr1; 953 uint32_t id_pfr2; 954 uint32_t mvfr0; 955 uint32_t mvfr1; 956 uint32_t mvfr2; 957 uint32_t id_dfr0; 958 uint32_t dbgdidr; 959 uint64_t id_aa64isar0; 960 uint64_t id_aa64isar1; 961 uint64_t id_aa64pfr0; 962 uint64_t id_aa64pfr1; 963 uint64_t id_aa64mmfr0; 964 uint64_t id_aa64mmfr1; 965 uint64_t id_aa64mmfr2; 966 uint64_t id_aa64dfr0; 967 uint64_t id_aa64dfr1; 968 uint64_t id_aa64zfr0; 969 uint64_t reset_pmcr_el0; 970 } isar; 971 uint64_t midr; 972 uint32_t revidr; 973 uint32_t reset_fpsid; 974 uint64_t ctr; 975 uint32_t reset_sctlr; 976 uint64_t pmceid0; 977 uint64_t pmceid1; 978 uint32_t id_afr0; 979 uint64_t id_aa64afr0; 980 uint64_t id_aa64afr1; 981 uint64_t clidr; 982 uint64_t mp_affinity; /* MP ID without feature bits */ 983 /* The elements of this array are the CCSIDR values for each cache, 984 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 985 */ 986 uint64_t ccsidr[16]; 987 uint64_t reset_cbar; 988 uint32_t reset_auxcr; 989 bool reset_hivecs; 990 991 /* 992 * Intermediate values used during property parsing. 993 * Once finalized, the values should be read from ID_AA64*. 994 */ 995 bool prop_pauth; 996 bool prop_pauth_impdef; 997 bool prop_lpa2; 998 999 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 1000 uint32_t dcz_blocksize; 1001 uint64_t rvbar_prop; /* Property/input signals. */ 1002 1003 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 1004 int gic_num_lrs; /* number of list registers */ 1005 int gic_vpribits; /* number of virtual priority bits */ 1006 int gic_vprebits; /* number of virtual preemption bits */ 1007 int gic_pribits; /* number of physical priority bits */ 1008 1009 /* Whether the cfgend input is high (i.e. this CPU should reset into 1010 * big-endian mode). This setting isn't used directly: instead it modifies 1011 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 1012 * architecture version. 1013 */ 1014 bool cfgend; 1015 1016 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 1017 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 1018 1019 int32_t node_id; /* NUMA node this CPU belongs to */ 1020 1021 /* Used to synchronize KVM and QEMU in-kernel device levels */ 1022 uint8_t device_irq_level; 1023 1024 /* Used to set the maximum vector length the cpu will support. */ 1025 uint32_t sve_max_vq; 1026 1027 #ifdef CONFIG_USER_ONLY 1028 /* Used to set the default vector length at process start. */ 1029 uint32_t sve_default_vq; 1030 #endif 1031 1032 /* 1033 * In sve_vq_map each set bit is a supported vector length of 1034 * (bit-number + 1) * 16 bytes, i.e. each bit number + 1 is the vector 1035 * length in quadwords. 1036 * 1037 * While processing properties during initialization, corresponding 1038 * sve_vq_init bits are set for bits in sve_vq_map that have been 1039 * set by properties. 1040 * 1041 * Bits set in sve_vq_supported represent valid vector lengths for 1042 * the CPU type. 1043 */ 1044 DECLARE_BITMAP(sve_vq_map, ARM_MAX_VQ); 1045 DECLARE_BITMAP(sve_vq_init, ARM_MAX_VQ); 1046 DECLARE_BITMAP(sve_vq_supported, ARM_MAX_VQ); 1047 1048 /* Generic timer counter frequency, in Hz */ 1049 uint64_t gt_cntfrq_hz; 1050 }; 1051 1052 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); 1053 1054 void arm_cpu_post_init(Object *obj); 1055 1056 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); 1057 1058 #ifndef CONFIG_USER_ONLY 1059 extern const VMStateDescription vmstate_arm_cpu; 1060 1061 void arm_cpu_do_interrupt(CPUState *cpu); 1062 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 1063 #endif /* !CONFIG_USER_ONLY */ 1064 1065 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 1066 MemTxAttrs *attrs); 1067 1068 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1069 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1070 1071 /* 1072 * Helpers to dynamically generates XML descriptions of the sysregs 1073 * and SVE registers. Returns the number of registers in each set. 1074 */ 1075 int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg); 1076 int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg); 1077 1078 /* Returns the dynamically generated XML for the gdb stub. 1079 * Returns a pointer to the XML contents for the specified XML file or NULL 1080 * if the XML name doesn't match the predefined one. 1081 */ 1082 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname); 1083 1084 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 1085 int cpuid, void *opaque); 1086 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 1087 int cpuid, void *opaque); 1088 1089 #ifdef TARGET_AARCH64 1090 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1091 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1092 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 1093 void aarch64_sve_change_el(CPUARMState *env, int old_el, 1094 int new_el, bool el0_a64); 1095 void aarch64_add_sve_properties(Object *obj); 1096 void aarch64_add_pauth_properties(Object *obj); 1097 1098 /* 1099 * SVE registers are encoded in KVM's memory in an endianness-invariant format. 1100 * The byte at offset i from the start of the in-memory representation contains 1101 * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the 1102 * lowest offsets are stored in the lowest memory addresses, then that nearly 1103 * matches QEMU's representation, which is to use an array of host-endian 1104 * uint64_t's, where the lower offsets are at the lower indices. To complete 1105 * the translation we just need to byte swap the uint64_t's on big-endian hosts. 1106 */ 1107 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr) 1108 { 1109 #if HOST_BIG_ENDIAN 1110 int i; 1111 1112 for (i = 0; i < nr; ++i) { 1113 dst[i] = bswap64(src[i]); 1114 } 1115 1116 return dst; 1117 #else 1118 return src; 1119 #endif 1120 } 1121 1122 #else 1123 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } 1124 static inline void aarch64_sve_change_el(CPUARMState *env, int o, 1125 int n, bool a) 1126 { } 1127 static inline void aarch64_add_sve_properties(Object *obj) { } 1128 #endif 1129 1130 void aarch64_sync_32_to_64(CPUARMState *env); 1131 void aarch64_sync_64_to_32(CPUARMState *env); 1132 1133 int fp_exception_el(CPUARMState *env, int cur_el); 1134 int sve_exception_el(CPUARMState *env, int cur_el); 1135 uint32_t sve_zcr_len_for_el(CPUARMState *env, int el); 1136 1137 static inline bool is_a64(CPUARMState *env) 1138 { 1139 return env->aarch64; 1140 } 1141 1142 /** 1143 * pmu_op_start/finish 1144 * @env: CPUARMState 1145 * 1146 * Convert all PMU counters between their delta form (the typical mode when 1147 * they are enabled) and the guest-visible values. These two calls must 1148 * surround any action which might affect the counters. 1149 */ 1150 void pmu_op_start(CPUARMState *env); 1151 void pmu_op_finish(CPUARMState *env); 1152 1153 /* 1154 * Called when a PMU counter is due to overflow 1155 */ 1156 void arm_pmu_timer_cb(void *opaque); 1157 1158 /** 1159 * Functions to register as EL change hooks for PMU mode filtering 1160 */ 1161 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1162 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1163 1164 /* 1165 * pmu_init 1166 * @cpu: ARMCPU 1167 * 1168 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1169 * for the current configuration 1170 */ 1171 void pmu_init(ARMCPU *cpu); 1172 1173 /* SCTLR bit meanings. Several bits have been reused in newer 1174 * versions of the architecture; in that case we define constants 1175 * for both old and new bit meanings. Code which tests against those 1176 * bits should probably check or otherwise arrange that the CPU 1177 * is the architectural version it expects. 1178 */ 1179 #define SCTLR_M (1U << 0) 1180 #define SCTLR_A (1U << 1) 1181 #define SCTLR_C (1U << 2) 1182 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1183 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1184 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1185 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1186 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1187 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1188 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1189 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1190 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1191 #define SCTLR_nAA (1U << 6) /* when v8.4-LSE is implemented */ 1192 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1193 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1194 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1195 #define SCTLR_SED (1U << 8) /* v8 onward */ 1196 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1197 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1198 #define SCTLR_F (1U << 10) /* up to v6 */ 1199 #define SCTLR_SW (1U << 10) /* v7 */ 1200 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ 1201 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1202 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1203 #define SCTLR_I (1U << 12) 1204 #define SCTLR_V (1U << 13) /* AArch32 only */ 1205 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1206 #define SCTLR_RR (1U << 14) /* up to v7 */ 1207 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1208 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1209 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1210 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1211 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1212 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1213 #define SCTLR_BR (1U << 17) /* PMSA only */ 1214 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1215 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1216 #define SCTLR_WXN (1U << 19) 1217 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1218 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1219 #define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */ 1220 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1221 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1222 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1223 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1224 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1225 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1226 #define SCTLR_VE (1U << 24) /* up to v7 */ 1227 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1228 #define SCTLR_EE (1U << 25) 1229 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1230 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1231 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1232 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1233 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1234 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1235 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1236 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1237 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1238 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1239 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1240 #define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */ 1241 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1242 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1243 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1244 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1245 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1246 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1247 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1248 #define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */ 1249 #define SCTLR_TWEDEn (1ULL << 45) /* FEAT_TWED */ 1250 #define SCTLR_TWEDEL MAKE_64_MASK(46, 4) /* FEAT_TWED */ 1251 #define SCTLR_TMT0 (1ULL << 50) /* FEAT_TME */ 1252 #define SCTLR_TMT (1ULL << 51) /* FEAT_TME */ 1253 #define SCTLR_TME0 (1ULL << 52) /* FEAT_TME */ 1254 #define SCTLR_TME (1ULL << 53) /* FEAT_TME */ 1255 #define SCTLR_EnASR (1ULL << 54) /* FEAT_LS64_V */ 1256 #define SCTLR_EnAS0 (1ULL << 55) /* FEAT_LS64_ACCDATA */ 1257 #define SCTLR_EnALS (1ULL << 56) /* FEAT_LS64 */ 1258 #define SCTLR_EPAN (1ULL << 57) /* FEAT_PAN3 */ 1259 #define SCTLR_EnTP2 (1ULL << 60) /* FEAT_SME */ 1260 #define SCTLR_NMI (1ULL << 61) /* FEAT_NMI */ 1261 #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */ 1262 #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */ 1263 1264 /* Bit definitions for CPACR (AArch32 only) */ 1265 FIELD(CPACR, CP10, 20, 2) 1266 FIELD(CPACR, CP11, 22, 2) 1267 FIELD(CPACR, TRCDIS, 28, 1) /* matches CPACR_EL1.TTA */ 1268 FIELD(CPACR, D32DIS, 30, 1) /* up to v7; RAZ in v8 */ 1269 FIELD(CPACR, ASEDIS, 31, 1) 1270 1271 /* Bit definitions for CPACR_EL1 (AArch64 only) */ 1272 FIELD(CPACR_EL1, ZEN, 16, 2) 1273 FIELD(CPACR_EL1, FPEN, 20, 2) 1274 FIELD(CPACR_EL1, SMEN, 24, 2) 1275 FIELD(CPACR_EL1, TTA, 28, 1) /* matches CPACR.TRCDIS */ 1276 1277 /* Bit definitions for HCPTR (AArch32 only) */ 1278 FIELD(HCPTR, TCP10, 10, 1) 1279 FIELD(HCPTR, TCP11, 11, 1) 1280 FIELD(HCPTR, TASE, 15, 1) 1281 FIELD(HCPTR, TTA, 20, 1) 1282 FIELD(HCPTR, TAM, 30, 1) /* matches CPTR_EL2.TAM */ 1283 FIELD(HCPTR, TCPAC, 31, 1) /* matches CPTR_EL2.TCPAC */ 1284 1285 /* Bit definitions for CPTR_EL2 (AArch64 only) */ 1286 FIELD(CPTR_EL2, TZ, 8, 1) /* !E2H */ 1287 FIELD(CPTR_EL2, TFP, 10, 1) /* !E2H, matches HCPTR.TCP10 */ 1288 FIELD(CPTR_EL2, TSM, 12, 1) /* !E2H */ 1289 FIELD(CPTR_EL2, ZEN, 16, 2) /* E2H */ 1290 FIELD(CPTR_EL2, FPEN, 20, 2) /* E2H */ 1291 FIELD(CPTR_EL2, SMEN, 24, 2) /* E2H */ 1292 FIELD(CPTR_EL2, TTA, 28, 1) 1293 FIELD(CPTR_EL2, TAM, 30, 1) /* matches HCPTR.TAM */ 1294 FIELD(CPTR_EL2, TCPAC, 31, 1) /* matches HCPTR.TCPAC */ 1295 1296 /* Bit definitions for CPTR_EL3 (AArch64 only) */ 1297 FIELD(CPTR_EL3, EZ, 8, 1) 1298 FIELD(CPTR_EL3, TFP, 10, 1) 1299 FIELD(CPTR_EL3, ESM, 12, 1) 1300 FIELD(CPTR_EL3, TTA, 20, 1) 1301 FIELD(CPTR_EL3, TAM, 30, 1) 1302 FIELD(CPTR_EL3, TCPAC, 31, 1) 1303 1304 #define MDCR_EPMAD (1U << 21) 1305 #define MDCR_EDAD (1U << 20) 1306 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ 1307 #define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ 1308 #define MDCR_SDD (1U << 16) 1309 #define MDCR_SPD (3U << 14) 1310 #define MDCR_TDRA (1U << 11) 1311 #define MDCR_TDOSA (1U << 10) 1312 #define MDCR_TDA (1U << 9) 1313 #define MDCR_TDE (1U << 8) 1314 #define MDCR_HPME (1U << 7) 1315 #define MDCR_TPM (1U << 6) 1316 #define MDCR_TPMCR (1U << 5) 1317 #define MDCR_HPMN (0x1fU) 1318 1319 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 1320 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) 1321 1322 #define CPSR_M (0x1fU) 1323 #define CPSR_T (1U << 5) 1324 #define CPSR_F (1U << 6) 1325 #define CPSR_I (1U << 7) 1326 #define CPSR_A (1U << 8) 1327 #define CPSR_E (1U << 9) 1328 #define CPSR_IT_2_7 (0xfc00U) 1329 #define CPSR_GE (0xfU << 16) 1330 #define CPSR_IL (1U << 20) 1331 #define CPSR_DIT (1U << 21) 1332 #define CPSR_PAN (1U << 22) 1333 #define CPSR_SSBS (1U << 23) 1334 #define CPSR_J (1U << 24) 1335 #define CPSR_IT_0_1 (3U << 25) 1336 #define CPSR_Q (1U << 27) 1337 #define CPSR_V (1U << 28) 1338 #define CPSR_C (1U << 29) 1339 #define CPSR_Z (1U << 30) 1340 #define CPSR_N (1U << 31) 1341 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1342 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1343 1344 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1345 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1346 | CPSR_NZCV) 1347 /* Bits writable in user mode. */ 1348 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E) 1349 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1350 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1351 1352 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1353 #define XPSR_EXCP 0x1ffU 1354 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1355 #define XPSR_IT_2_7 CPSR_IT_2_7 1356 #define XPSR_GE CPSR_GE 1357 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1358 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1359 #define XPSR_IT_0_1 CPSR_IT_0_1 1360 #define XPSR_Q CPSR_Q 1361 #define XPSR_V CPSR_V 1362 #define XPSR_C CPSR_C 1363 #define XPSR_Z CPSR_Z 1364 #define XPSR_N CPSR_N 1365 #define XPSR_NZCV CPSR_NZCV 1366 #define XPSR_IT CPSR_IT 1367 1368 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 1369 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 1370 #define TTBCR_PD0 (1U << 4) 1371 #define TTBCR_PD1 (1U << 5) 1372 #define TTBCR_EPD0 (1U << 7) 1373 #define TTBCR_IRGN0 (3U << 8) 1374 #define TTBCR_ORGN0 (3U << 10) 1375 #define TTBCR_SH0 (3U << 12) 1376 #define TTBCR_T1SZ (3U << 16) 1377 #define TTBCR_A1 (1U << 22) 1378 #define TTBCR_EPD1 (1U << 23) 1379 #define TTBCR_IRGN1 (3U << 24) 1380 #define TTBCR_ORGN1 (3U << 26) 1381 #define TTBCR_SH1 (1U << 28) 1382 #define TTBCR_EAE (1U << 31) 1383 1384 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1385 * Only these are valid when in AArch64 mode; in 1386 * AArch32 mode SPSRs are basically CPSR-format. 1387 */ 1388 #define PSTATE_SP (1U) 1389 #define PSTATE_M (0xFU) 1390 #define PSTATE_nRW (1U << 4) 1391 #define PSTATE_F (1U << 6) 1392 #define PSTATE_I (1U << 7) 1393 #define PSTATE_A (1U << 8) 1394 #define PSTATE_D (1U << 9) 1395 #define PSTATE_BTYPE (3U << 10) 1396 #define PSTATE_SSBS (1U << 12) 1397 #define PSTATE_IL (1U << 20) 1398 #define PSTATE_SS (1U << 21) 1399 #define PSTATE_PAN (1U << 22) 1400 #define PSTATE_UAO (1U << 23) 1401 #define PSTATE_DIT (1U << 24) 1402 #define PSTATE_TCO (1U << 25) 1403 #define PSTATE_V (1U << 28) 1404 #define PSTATE_C (1U << 29) 1405 #define PSTATE_Z (1U << 30) 1406 #define PSTATE_N (1U << 31) 1407 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1408 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1409 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1410 /* Mode values for AArch64 */ 1411 #define PSTATE_MODE_EL3h 13 1412 #define PSTATE_MODE_EL3t 12 1413 #define PSTATE_MODE_EL2h 9 1414 #define PSTATE_MODE_EL2t 8 1415 #define PSTATE_MODE_EL1h 5 1416 #define PSTATE_MODE_EL1t 4 1417 #define PSTATE_MODE_EL0t 0 1418 1419 /* Write a new value to v7m.exception, thus transitioning into or out 1420 * of Handler mode; this may result in a change of active stack pointer. 1421 */ 1422 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1423 1424 /* Map EL and handler into a PSTATE_MODE. */ 1425 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1426 { 1427 return (el << 2) | handler; 1428 } 1429 1430 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1431 * interprocessing, so we don't attempt to sync with the cpsr state used by 1432 * the 32 bit decoder. 1433 */ 1434 static inline uint32_t pstate_read(CPUARMState *env) 1435 { 1436 int ZF; 1437 1438 ZF = (env->ZF == 0); 1439 return (env->NF & 0x80000000) | (ZF << 30) 1440 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1441 | env->pstate | env->daif | (env->btype << 10); 1442 } 1443 1444 static inline void pstate_write(CPUARMState *env, uint32_t val) 1445 { 1446 env->ZF = (~val) & PSTATE_Z; 1447 env->NF = val; 1448 env->CF = (val >> 29) & 1; 1449 env->VF = (val << 3) & 0x80000000; 1450 env->daif = val & PSTATE_DAIF; 1451 env->btype = (val >> 10) & 3; 1452 env->pstate = val & ~CACHED_PSTATE_BITS; 1453 } 1454 1455 /* Return the current CPSR value. */ 1456 uint32_t cpsr_read(CPUARMState *env); 1457 1458 typedef enum CPSRWriteType { 1459 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1460 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1461 CPSRWriteRaw = 2, 1462 /* trust values, no reg bank switch, no hflags rebuild */ 1463 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1464 } CPSRWriteType; 1465 1466 /* 1467 * Set the CPSR. Note that some bits of mask must be all-set or all-clear. 1468 * This will do an arm_rebuild_hflags() if any of the bits in @mask 1469 * correspond to TB flags bits cached in the hflags, unless @write_type 1470 * is CPSRWriteRaw. 1471 */ 1472 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1473 CPSRWriteType write_type); 1474 1475 /* Return the current xPSR value. */ 1476 static inline uint32_t xpsr_read(CPUARMState *env) 1477 { 1478 int ZF; 1479 ZF = (env->ZF == 0); 1480 return (env->NF & 0x80000000) | (ZF << 30) 1481 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1482 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1483 | ((env->condexec_bits & 0xfc) << 8) 1484 | (env->GE << 16) 1485 | env->v7m.exception; 1486 } 1487 1488 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1489 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1490 { 1491 if (mask & XPSR_NZCV) { 1492 env->ZF = (~val) & XPSR_Z; 1493 env->NF = val; 1494 env->CF = (val >> 29) & 1; 1495 env->VF = (val << 3) & 0x80000000; 1496 } 1497 if (mask & XPSR_Q) { 1498 env->QF = ((val & XPSR_Q) != 0); 1499 } 1500 if (mask & XPSR_GE) { 1501 env->GE = (val & XPSR_GE) >> 16; 1502 } 1503 #ifndef CONFIG_USER_ONLY 1504 if (mask & XPSR_T) { 1505 env->thumb = ((val & XPSR_T) != 0); 1506 } 1507 if (mask & XPSR_IT_0_1) { 1508 env->condexec_bits &= ~3; 1509 env->condexec_bits |= (val >> 25) & 3; 1510 } 1511 if (mask & XPSR_IT_2_7) { 1512 env->condexec_bits &= 3; 1513 env->condexec_bits |= (val >> 8) & 0xfc; 1514 } 1515 if (mask & XPSR_EXCP) { 1516 /* Note that this only happens on exception exit */ 1517 write_v7m_exception(env, val & XPSR_EXCP); 1518 } 1519 #endif 1520 } 1521 1522 #define HCR_VM (1ULL << 0) 1523 #define HCR_SWIO (1ULL << 1) 1524 #define HCR_PTW (1ULL << 2) 1525 #define HCR_FMO (1ULL << 3) 1526 #define HCR_IMO (1ULL << 4) 1527 #define HCR_AMO (1ULL << 5) 1528 #define HCR_VF (1ULL << 6) 1529 #define HCR_VI (1ULL << 7) 1530 #define HCR_VSE (1ULL << 8) 1531 #define HCR_FB (1ULL << 9) 1532 #define HCR_BSU_MASK (3ULL << 10) 1533 #define HCR_DC (1ULL << 12) 1534 #define HCR_TWI (1ULL << 13) 1535 #define HCR_TWE (1ULL << 14) 1536 #define HCR_TID0 (1ULL << 15) 1537 #define HCR_TID1 (1ULL << 16) 1538 #define HCR_TID2 (1ULL << 17) 1539 #define HCR_TID3 (1ULL << 18) 1540 #define HCR_TSC (1ULL << 19) 1541 #define HCR_TIDCP (1ULL << 20) 1542 #define HCR_TACR (1ULL << 21) 1543 #define HCR_TSW (1ULL << 22) 1544 #define HCR_TPCP (1ULL << 23) 1545 #define HCR_TPU (1ULL << 24) 1546 #define HCR_TTLB (1ULL << 25) 1547 #define HCR_TVM (1ULL << 26) 1548 #define HCR_TGE (1ULL << 27) 1549 #define HCR_TDZ (1ULL << 28) 1550 #define HCR_HCD (1ULL << 29) 1551 #define HCR_TRVM (1ULL << 30) 1552 #define HCR_RW (1ULL << 31) 1553 #define HCR_CD (1ULL << 32) 1554 #define HCR_ID (1ULL << 33) 1555 #define HCR_E2H (1ULL << 34) 1556 #define HCR_TLOR (1ULL << 35) 1557 #define HCR_TERR (1ULL << 36) 1558 #define HCR_TEA (1ULL << 37) 1559 #define HCR_MIOCNCE (1ULL << 38) 1560 /* RES0 bit 39 */ 1561 #define HCR_APK (1ULL << 40) 1562 #define HCR_API (1ULL << 41) 1563 #define HCR_NV (1ULL << 42) 1564 #define HCR_NV1 (1ULL << 43) 1565 #define HCR_AT (1ULL << 44) 1566 #define HCR_NV2 (1ULL << 45) 1567 #define HCR_FWB (1ULL << 46) 1568 #define HCR_FIEN (1ULL << 47) 1569 /* RES0 bit 48 */ 1570 #define HCR_TID4 (1ULL << 49) 1571 #define HCR_TICAB (1ULL << 50) 1572 #define HCR_AMVOFFEN (1ULL << 51) 1573 #define HCR_TOCU (1ULL << 52) 1574 #define HCR_ENSCXT (1ULL << 53) 1575 #define HCR_TTLBIS (1ULL << 54) 1576 #define HCR_TTLBOS (1ULL << 55) 1577 #define HCR_ATA (1ULL << 56) 1578 #define HCR_DCT (1ULL << 57) 1579 #define HCR_TID5 (1ULL << 58) 1580 #define HCR_TWEDEN (1ULL << 59) 1581 #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) 1582 1583 #define HCRX_ENAS0 (1ULL << 0) 1584 #define HCRX_ENALS (1ULL << 1) 1585 #define HCRX_ENASR (1ULL << 2) 1586 #define HCRX_FNXS (1ULL << 3) 1587 #define HCRX_FGTNXS (1ULL << 4) 1588 #define HCRX_SMPME (1ULL << 5) 1589 #define HCRX_TALLINT (1ULL << 6) 1590 #define HCRX_VINMI (1ULL << 7) 1591 #define HCRX_VFNMI (1ULL << 8) 1592 #define HCRX_CMOW (1ULL << 9) 1593 #define HCRX_MCE2 (1ULL << 10) 1594 #define HCRX_MSCEN (1ULL << 11) 1595 1596 #define HPFAR_NS (1ULL << 63) 1597 1598 #define SCR_NS (1U << 0) 1599 #define SCR_IRQ (1U << 1) 1600 #define SCR_FIQ (1U << 2) 1601 #define SCR_EA (1U << 3) 1602 #define SCR_FW (1U << 4) 1603 #define SCR_AW (1U << 5) 1604 #define SCR_NET (1U << 6) 1605 #define SCR_SMD (1U << 7) 1606 #define SCR_HCE (1U << 8) 1607 #define SCR_SIF (1U << 9) 1608 #define SCR_RW (1U << 10) 1609 #define SCR_ST (1U << 11) 1610 #define SCR_TWI (1U << 12) 1611 #define SCR_TWE (1U << 13) 1612 #define SCR_TLOR (1U << 14) 1613 #define SCR_TERR (1U << 15) 1614 #define SCR_APK (1U << 16) 1615 #define SCR_API (1U << 17) 1616 #define SCR_EEL2 (1U << 18) 1617 #define SCR_EASE (1U << 19) 1618 #define SCR_NMEA (1U << 20) 1619 #define SCR_FIEN (1U << 21) 1620 #define SCR_ENSCXT (1U << 25) 1621 #define SCR_ATA (1U << 26) 1622 #define SCR_FGTEN (1U << 27) 1623 #define SCR_ECVEN (1U << 28) 1624 #define SCR_TWEDEN (1U << 29) 1625 #define SCR_TWEDEL MAKE_64BIT_MASK(30, 4) 1626 #define SCR_TME (1ULL << 34) 1627 #define SCR_AMVOFFEN (1ULL << 35) 1628 #define SCR_ENAS0 (1ULL << 36) 1629 #define SCR_ADEN (1ULL << 37) 1630 #define SCR_HXEN (1ULL << 38) 1631 #define SCR_TRNDR (1ULL << 40) 1632 #define SCR_ENTP2 (1ULL << 41) 1633 #define SCR_GPF (1ULL << 48) 1634 1635 #define HSTR_TTEE (1 << 16) 1636 #define HSTR_TJDBX (1 << 17) 1637 1638 /* Return the current FPSCR value. */ 1639 uint32_t vfp_get_fpscr(CPUARMState *env); 1640 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1641 1642 /* FPCR, Floating Point Control Register 1643 * FPSR, Floating Poiht Status Register 1644 * 1645 * For A64 the FPSCR is split into two logically distinct registers, 1646 * FPCR and FPSR. However since they still use non-overlapping bits 1647 * we store the underlying state in fpscr and just mask on read/write. 1648 */ 1649 #define FPSR_MASK 0xf800009f 1650 #define FPCR_MASK 0x07ff9f00 1651 1652 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1653 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1654 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1655 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1656 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1657 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1658 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1659 #define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */ 1660 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1661 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1662 #define FPCR_AHP (1 << 26) /* Alternative half-precision */ 1663 #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ 1664 #define FPCR_V (1 << 28) /* FP overflow flag */ 1665 #define FPCR_C (1 << 29) /* FP carry flag */ 1666 #define FPCR_Z (1 << 30) /* FP zero flag */ 1667 #define FPCR_N (1 << 31) /* FP negative flag */ 1668 1669 #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */ 1670 #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT) 1671 #define FPCR_LTPSIZE_LENGTH 3 1672 1673 #define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V) 1674 #define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC) 1675 1676 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1677 { 1678 return vfp_get_fpscr(env) & FPSR_MASK; 1679 } 1680 1681 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1682 { 1683 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1684 vfp_set_fpscr(env, new_fpscr); 1685 } 1686 1687 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1688 { 1689 return vfp_get_fpscr(env) & FPCR_MASK; 1690 } 1691 1692 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1693 { 1694 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1695 vfp_set_fpscr(env, new_fpscr); 1696 } 1697 1698 enum arm_cpu_mode { 1699 ARM_CPU_MODE_USR = 0x10, 1700 ARM_CPU_MODE_FIQ = 0x11, 1701 ARM_CPU_MODE_IRQ = 0x12, 1702 ARM_CPU_MODE_SVC = 0x13, 1703 ARM_CPU_MODE_MON = 0x16, 1704 ARM_CPU_MODE_ABT = 0x17, 1705 ARM_CPU_MODE_HYP = 0x1a, 1706 ARM_CPU_MODE_UND = 0x1b, 1707 ARM_CPU_MODE_SYS = 0x1f 1708 }; 1709 1710 /* VFP system registers. */ 1711 #define ARM_VFP_FPSID 0 1712 #define ARM_VFP_FPSCR 1 1713 #define ARM_VFP_MVFR2 5 1714 #define ARM_VFP_MVFR1 6 1715 #define ARM_VFP_MVFR0 7 1716 #define ARM_VFP_FPEXC 8 1717 #define ARM_VFP_FPINST 9 1718 #define ARM_VFP_FPINST2 10 1719 /* These ones are M-profile only */ 1720 #define ARM_VFP_FPSCR_NZCVQC 2 1721 #define ARM_VFP_VPR 12 1722 #define ARM_VFP_P0 13 1723 #define ARM_VFP_FPCXT_NS 14 1724 #define ARM_VFP_FPCXT_S 15 1725 1726 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */ 1727 #define QEMU_VFP_FPSCR_NZCV 0xffff 1728 1729 /* iwMMXt coprocessor control registers. */ 1730 #define ARM_IWMMXT_wCID 0 1731 #define ARM_IWMMXT_wCon 1 1732 #define ARM_IWMMXT_wCSSF 2 1733 #define ARM_IWMMXT_wCASF 3 1734 #define ARM_IWMMXT_wCGR0 8 1735 #define ARM_IWMMXT_wCGR1 9 1736 #define ARM_IWMMXT_wCGR2 10 1737 #define ARM_IWMMXT_wCGR3 11 1738 1739 /* V7M CCR bits */ 1740 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1741 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1742 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1743 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1744 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1745 FIELD(V7M_CCR, STKALIGN, 9, 1) 1746 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1747 FIELD(V7M_CCR, DC, 16, 1) 1748 FIELD(V7M_CCR, IC, 17, 1) 1749 FIELD(V7M_CCR, BP, 18, 1) 1750 FIELD(V7M_CCR, LOB, 19, 1) 1751 FIELD(V7M_CCR, TRD, 20, 1) 1752 1753 /* V7M SCR bits */ 1754 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1755 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1756 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1757 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1758 1759 /* V7M AIRCR bits */ 1760 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1761 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1762 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1763 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1764 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1765 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1766 FIELD(V7M_AIRCR, PRIS, 14, 1) 1767 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1768 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1769 1770 /* V7M CFSR bits for MMFSR */ 1771 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1772 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1773 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1774 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1775 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1776 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1777 1778 /* V7M CFSR bits for BFSR */ 1779 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1780 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1781 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1782 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1783 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1784 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1785 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1786 1787 /* V7M CFSR bits for UFSR */ 1788 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1789 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1790 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1791 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1792 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1793 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1794 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1795 1796 /* V7M CFSR bit masks covering all of the subregister bits */ 1797 FIELD(V7M_CFSR, MMFSR, 0, 8) 1798 FIELD(V7M_CFSR, BFSR, 8, 8) 1799 FIELD(V7M_CFSR, UFSR, 16, 16) 1800 1801 /* V7M HFSR bits */ 1802 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1803 FIELD(V7M_HFSR, FORCED, 30, 1) 1804 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1805 1806 /* V7M DFSR bits */ 1807 FIELD(V7M_DFSR, HALTED, 0, 1) 1808 FIELD(V7M_DFSR, BKPT, 1, 1) 1809 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1810 FIELD(V7M_DFSR, VCATCH, 3, 1) 1811 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1812 1813 /* V7M SFSR bits */ 1814 FIELD(V7M_SFSR, INVEP, 0, 1) 1815 FIELD(V7M_SFSR, INVIS, 1, 1) 1816 FIELD(V7M_SFSR, INVER, 2, 1) 1817 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1818 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1819 FIELD(V7M_SFSR, LSPERR, 5, 1) 1820 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1821 FIELD(V7M_SFSR, LSERR, 7, 1) 1822 1823 /* v7M MPU_CTRL bits */ 1824 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1825 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1826 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1827 1828 /* v7M CLIDR bits */ 1829 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1830 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1831 FIELD(V7M_CLIDR, LOC, 24, 3) 1832 FIELD(V7M_CLIDR, LOUU, 27, 3) 1833 FIELD(V7M_CLIDR, ICB, 30, 2) 1834 1835 FIELD(V7M_CSSELR, IND, 0, 1) 1836 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1837 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1838 * define a mask for this and check that it doesn't permit running off 1839 * the end of the array. 1840 */ 1841 FIELD(V7M_CSSELR, INDEX, 0, 4) 1842 1843 /* v7M FPCCR bits */ 1844 FIELD(V7M_FPCCR, LSPACT, 0, 1) 1845 FIELD(V7M_FPCCR, USER, 1, 1) 1846 FIELD(V7M_FPCCR, S, 2, 1) 1847 FIELD(V7M_FPCCR, THREAD, 3, 1) 1848 FIELD(V7M_FPCCR, HFRDY, 4, 1) 1849 FIELD(V7M_FPCCR, MMRDY, 5, 1) 1850 FIELD(V7M_FPCCR, BFRDY, 6, 1) 1851 FIELD(V7M_FPCCR, SFRDY, 7, 1) 1852 FIELD(V7M_FPCCR, MONRDY, 8, 1) 1853 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) 1854 FIELD(V7M_FPCCR, UFRDY, 10, 1) 1855 FIELD(V7M_FPCCR, RES0, 11, 15) 1856 FIELD(V7M_FPCCR, TS, 26, 1) 1857 FIELD(V7M_FPCCR, CLRONRETS, 27, 1) 1858 FIELD(V7M_FPCCR, CLRONRET, 28, 1) 1859 FIELD(V7M_FPCCR, LSPENS, 29, 1) 1860 FIELD(V7M_FPCCR, LSPEN, 30, 1) 1861 FIELD(V7M_FPCCR, ASPEN, 31, 1) 1862 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */ 1863 #define R_V7M_FPCCR_BANKED_MASK \ 1864 (R_V7M_FPCCR_LSPACT_MASK | \ 1865 R_V7M_FPCCR_USER_MASK | \ 1866 R_V7M_FPCCR_THREAD_MASK | \ 1867 R_V7M_FPCCR_MMRDY_MASK | \ 1868 R_V7M_FPCCR_SPLIMVIOL_MASK | \ 1869 R_V7M_FPCCR_UFRDY_MASK | \ 1870 R_V7M_FPCCR_ASPEN_MASK) 1871 1872 /* v7M VPR bits */ 1873 FIELD(V7M_VPR, P0, 0, 16) 1874 FIELD(V7M_VPR, MASK01, 16, 4) 1875 FIELD(V7M_VPR, MASK23, 20, 4) 1876 1877 /* 1878 * System register ID fields. 1879 */ 1880 FIELD(CLIDR_EL1, CTYPE1, 0, 3) 1881 FIELD(CLIDR_EL1, CTYPE2, 3, 3) 1882 FIELD(CLIDR_EL1, CTYPE3, 6, 3) 1883 FIELD(CLIDR_EL1, CTYPE4, 9, 3) 1884 FIELD(CLIDR_EL1, CTYPE5, 12, 3) 1885 FIELD(CLIDR_EL1, CTYPE6, 15, 3) 1886 FIELD(CLIDR_EL1, CTYPE7, 18, 3) 1887 FIELD(CLIDR_EL1, LOUIS, 21, 3) 1888 FIELD(CLIDR_EL1, LOC, 24, 3) 1889 FIELD(CLIDR_EL1, LOUU, 27, 3) 1890 FIELD(CLIDR_EL1, ICB, 30, 3) 1891 1892 /* When FEAT_CCIDX is implemented */ 1893 FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3) 1894 FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21) 1895 FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24) 1896 1897 /* When FEAT_CCIDX is not implemented */ 1898 FIELD(CCSIDR_EL1, LINESIZE, 0, 3) 1899 FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10) 1900 FIELD(CCSIDR_EL1, NUMSETS, 13, 15) 1901 1902 FIELD(CTR_EL0, IMINLINE, 0, 4) 1903 FIELD(CTR_EL0, L1IP, 14, 2) 1904 FIELD(CTR_EL0, DMINLINE, 16, 4) 1905 FIELD(CTR_EL0, ERG, 20, 4) 1906 FIELD(CTR_EL0, CWG, 24, 4) 1907 FIELD(CTR_EL0, IDC, 28, 1) 1908 FIELD(CTR_EL0, DIC, 29, 1) 1909 FIELD(CTR_EL0, TMINLINE, 32, 6) 1910 1911 FIELD(MIDR_EL1, REVISION, 0, 4) 1912 FIELD(MIDR_EL1, PARTNUM, 4, 12) 1913 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) 1914 FIELD(MIDR_EL1, VARIANT, 20, 4) 1915 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) 1916 1917 FIELD(ID_ISAR0, SWAP, 0, 4) 1918 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 1919 FIELD(ID_ISAR0, BITFIELD, 8, 4) 1920 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 1921 FIELD(ID_ISAR0, COPROC, 16, 4) 1922 FIELD(ID_ISAR0, DEBUG, 20, 4) 1923 FIELD(ID_ISAR0, DIVIDE, 24, 4) 1924 1925 FIELD(ID_ISAR1, ENDIAN, 0, 4) 1926 FIELD(ID_ISAR1, EXCEPT, 4, 4) 1927 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 1928 FIELD(ID_ISAR1, EXTEND, 12, 4) 1929 FIELD(ID_ISAR1, IFTHEN, 16, 4) 1930 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 1931 FIELD(ID_ISAR1, INTERWORK, 24, 4) 1932 FIELD(ID_ISAR1, JAZELLE, 28, 4) 1933 1934 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 1935 FIELD(ID_ISAR2, MEMHINT, 4, 4) 1936 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 1937 FIELD(ID_ISAR2, MULT, 12, 4) 1938 FIELD(ID_ISAR2, MULTS, 16, 4) 1939 FIELD(ID_ISAR2, MULTU, 20, 4) 1940 FIELD(ID_ISAR2, PSR_AR, 24, 4) 1941 FIELD(ID_ISAR2, REVERSAL, 28, 4) 1942 1943 FIELD(ID_ISAR3, SATURATE, 0, 4) 1944 FIELD(ID_ISAR3, SIMD, 4, 4) 1945 FIELD(ID_ISAR3, SVC, 8, 4) 1946 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 1947 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 1948 FIELD(ID_ISAR3, T32COPY, 20, 4) 1949 FIELD(ID_ISAR3, TRUENOP, 24, 4) 1950 FIELD(ID_ISAR3, T32EE, 28, 4) 1951 1952 FIELD(ID_ISAR4, UNPRIV, 0, 4) 1953 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 1954 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 1955 FIELD(ID_ISAR4, SMC, 12, 4) 1956 FIELD(ID_ISAR4, BARRIER, 16, 4) 1957 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 1958 FIELD(ID_ISAR4, PSR_M, 24, 4) 1959 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 1960 1961 FIELD(ID_ISAR5, SEVL, 0, 4) 1962 FIELD(ID_ISAR5, AES, 4, 4) 1963 FIELD(ID_ISAR5, SHA1, 8, 4) 1964 FIELD(ID_ISAR5, SHA2, 12, 4) 1965 FIELD(ID_ISAR5, CRC32, 16, 4) 1966 FIELD(ID_ISAR5, RDM, 24, 4) 1967 FIELD(ID_ISAR5, VCMA, 28, 4) 1968 1969 FIELD(ID_ISAR6, JSCVT, 0, 4) 1970 FIELD(ID_ISAR6, DP, 4, 4) 1971 FIELD(ID_ISAR6, FHM, 8, 4) 1972 FIELD(ID_ISAR6, SB, 12, 4) 1973 FIELD(ID_ISAR6, SPECRES, 16, 4) 1974 FIELD(ID_ISAR6, BF16, 20, 4) 1975 FIELD(ID_ISAR6, I8MM, 24, 4) 1976 1977 FIELD(ID_MMFR0, VMSA, 0, 4) 1978 FIELD(ID_MMFR0, PMSA, 4, 4) 1979 FIELD(ID_MMFR0, OUTERSHR, 8, 4) 1980 FIELD(ID_MMFR0, SHARELVL, 12, 4) 1981 FIELD(ID_MMFR0, TCM, 16, 4) 1982 FIELD(ID_MMFR0, AUXREG, 20, 4) 1983 FIELD(ID_MMFR0, FCSE, 24, 4) 1984 FIELD(ID_MMFR0, INNERSHR, 28, 4) 1985 1986 FIELD(ID_MMFR1, L1HVDVA, 0, 4) 1987 FIELD(ID_MMFR1, L1UNIVA, 4, 4) 1988 FIELD(ID_MMFR1, L1HVDSW, 8, 4) 1989 FIELD(ID_MMFR1, L1UNISW, 12, 4) 1990 FIELD(ID_MMFR1, L1HVD, 16, 4) 1991 FIELD(ID_MMFR1, L1UNI, 20, 4) 1992 FIELD(ID_MMFR1, L1TSTCLN, 24, 4) 1993 FIELD(ID_MMFR1, BPRED, 28, 4) 1994 1995 FIELD(ID_MMFR2, L1HVDFG, 0, 4) 1996 FIELD(ID_MMFR2, L1HVDBG, 4, 4) 1997 FIELD(ID_MMFR2, L1HVDRNG, 8, 4) 1998 FIELD(ID_MMFR2, HVDTLB, 12, 4) 1999 FIELD(ID_MMFR2, UNITLB, 16, 4) 2000 FIELD(ID_MMFR2, MEMBARR, 20, 4) 2001 FIELD(ID_MMFR2, WFISTALL, 24, 4) 2002 FIELD(ID_MMFR2, HWACCFLG, 28, 4) 2003 2004 FIELD(ID_MMFR3, CMAINTVA, 0, 4) 2005 FIELD(ID_MMFR3, CMAINTSW, 4, 4) 2006 FIELD(ID_MMFR3, BPMAINT, 8, 4) 2007 FIELD(ID_MMFR3, MAINTBCST, 12, 4) 2008 FIELD(ID_MMFR3, PAN, 16, 4) 2009 FIELD(ID_MMFR3, COHWALK, 20, 4) 2010 FIELD(ID_MMFR3, CMEMSZ, 24, 4) 2011 FIELD(ID_MMFR3, SUPERSEC, 28, 4) 2012 2013 FIELD(ID_MMFR4, SPECSEI, 0, 4) 2014 FIELD(ID_MMFR4, AC2, 4, 4) 2015 FIELD(ID_MMFR4, XNX, 8, 4) 2016 FIELD(ID_MMFR4, CNP, 12, 4) 2017 FIELD(ID_MMFR4, HPDS, 16, 4) 2018 FIELD(ID_MMFR4, LSM, 20, 4) 2019 FIELD(ID_MMFR4, CCIDX, 24, 4) 2020 FIELD(ID_MMFR4, EVT, 28, 4) 2021 2022 FIELD(ID_MMFR5, ETS, 0, 4) 2023 FIELD(ID_MMFR5, NTLBPA, 4, 4) 2024 2025 FIELD(ID_PFR0, STATE0, 0, 4) 2026 FIELD(ID_PFR0, STATE1, 4, 4) 2027 FIELD(ID_PFR0, STATE2, 8, 4) 2028 FIELD(ID_PFR0, STATE3, 12, 4) 2029 FIELD(ID_PFR0, CSV2, 16, 4) 2030 FIELD(ID_PFR0, AMU, 20, 4) 2031 FIELD(ID_PFR0, DIT, 24, 4) 2032 FIELD(ID_PFR0, RAS, 28, 4) 2033 2034 FIELD(ID_PFR1, PROGMOD, 0, 4) 2035 FIELD(ID_PFR1, SECURITY, 4, 4) 2036 FIELD(ID_PFR1, MPROGMOD, 8, 4) 2037 FIELD(ID_PFR1, VIRTUALIZATION, 12, 4) 2038 FIELD(ID_PFR1, GENTIMER, 16, 4) 2039 FIELD(ID_PFR1, SEC_FRAC, 20, 4) 2040 FIELD(ID_PFR1, VIRT_FRAC, 24, 4) 2041 FIELD(ID_PFR1, GIC, 28, 4) 2042 2043 FIELD(ID_PFR2, CSV3, 0, 4) 2044 FIELD(ID_PFR2, SSBS, 4, 4) 2045 FIELD(ID_PFR2, RAS_FRAC, 8, 4) 2046 2047 FIELD(ID_AA64ISAR0, AES, 4, 4) 2048 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 2049 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 2050 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 2051 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 2052 FIELD(ID_AA64ISAR0, RDM, 28, 4) 2053 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 2054 FIELD(ID_AA64ISAR0, SM3, 36, 4) 2055 FIELD(ID_AA64ISAR0, SM4, 40, 4) 2056 FIELD(ID_AA64ISAR0, DP, 44, 4) 2057 FIELD(ID_AA64ISAR0, FHM, 48, 4) 2058 FIELD(ID_AA64ISAR0, TS, 52, 4) 2059 FIELD(ID_AA64ISAR0, TLB, 56, 4) 2060 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 2061 2062 FIELD(ID_AA64ISAR1, DPB, 0, 4) 2063 FIELD(ID_AA64ISAR1, APA, 4, 4) 2064 FIELD(ID_AA64ISAR1, API, 8, 4) 2065 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 2066 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 2067 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 2068 FIELD(ID_AA64ISAR1, GPA, 24, 4) 2069 FIELD(ID_AA64ISAR1, GPI, 28, 4) 2070 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 2071 FIELD(ID_AA64ISAR1, SB, 36, 4) 2072 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 2073 FIELD(ID_AA64ISAR1, BF16, 44, 4) 2074 FIELD(ID_AA64ISAR1, DGH, 48, 4) 2075 FIELD(ID_AA64ISAR1, I8MM, 52, 4) 2076 FIELD(ID_AA64ISAR1, XS, 56, 4) 2077 FIELD(ID_AA64ISAR1, LS64, 60, 4) 2078 2079 FIELD(ID_AA64ISAR2, WFXT, 0, 4) 2080 FIELD(ID_AA64ISAR2, RPRES, 4, 4) 2081 FIELD(ID_AA64ISAR2, GPA3, 8, 4) 2082 FIELD(ID_AA64ISAR2, APA3, 12, 4) 2083 FIELD(ID_AA64ISAR2, MOPS, 16, 4) 2084 FIELD(ID_AA64ISAR2, BC, 20, 4) 2085 FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4) 2086 2087 FIELD(ID_AA64PFR0, EL0, 0, 4) 2088 FIELD(ID_AA64PFR0, EL1, 4, 4) 2089 FIELD(ID_AA64PFR0, EL2, 8, 4) 2090 FIELD(ID_AA64PFR0, EL3, 12, 4) 2091 FIELD(ID_AA64PFR0, FP, 16, 4) 2092 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 2093 FIELD(ID_AA64PFR0, GIC, 24, 4) 2094 FIELD(ID_AA64PFR0, RAS, 28, 4) 2095 FIELD(ID_AA64PFR0, SVE, 32, 4) 2096 FIELD(ID_AA64PFR0, SEL2, 36, 4) 2097 FIELD(ID_AA64PFR0, MPAM, 40, 4) 2098 FIELD(ID_AA64PFR0, AMU, 44, 4) 2099 FIELD(ID_AA64PFR0, DIT, 48, 4) 2100 FIELD(ID_AA64PFR0, CSV2, 56, 4) 2101 FIELD(ID_AA64PFR0, CSV3, 60, 4) 2102 2103 FIELD(ID_AA64PFR1, BT, 0, 4) 2104 FIELD(ID_AA64PFR1, SSBS, 4, 4) 2105 FIELD(ID_AA64PFR1, MTE, 8, 4) 2106 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 2107 FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) 2108 FIELD(ID_AA64PFR1, SME, 24, 4) 2109 FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4) 2110 FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4) 2111 FIELD(ID_AA64PFR1, NMI, 36, 4) 2112 2113 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 2114 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 2115 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 2116 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 2117 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 2118 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 2119 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 2120 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 2121 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 2122 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 2123 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 2124 FIELD(ID_AA64MMFR0, EXS, 44, 4) 2125 FIELD(ID_AA64MMFR0, FGT, 56, 4) 2126 FIELD(ID_AA64MMFR0, ECV, 60, 4) 2127 2128 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 2129 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 2130 FIELD(ID_AA64MMFR1, VH, 8, 4) 2131 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 2132 FIELD(ID_AA64MMFR1, LO, 16, 4) 2133 FIELD(ID_AA64MMFR1, PAN, 20, 4) 2134 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 2135 FIELD(ID_AA64MMFR1, XNX, 28, 4) 2136 FIELD(ID_AA64MMFR1, TWED, 32, 4) 2137 FIELD(ID_AA64MMFR1, ETS, 36, 4) 2138 FIELD(ID_AA64MMFR1, HCX, 40, 4) 2139 FIELD(ID_AA64MMFR1, AFP, 44, 4) 2140 FIELD(ID_AA64MMFR1, NTLBPA, 48, 4) 2141 FIELD(ID_AA64MMFR1, TIDCP1, 52, 4) 2142 FIELD(ID_AA64MMFR1, CMOW, 56, 4) 2143 2144 FIELD(ID_AA64MMFR2, CNP, 0, 4) 2145 FIELD(ID_AA64MMFR2, UAO, 4, 4) 2146 FIELD(ID_AA64MMFR2, LSM, 8, 4) 2147 FIELD(ID_AA64MMFR2, IESB, 12, 4) 2148 FIELD(ID_AA64MMFR2, VARANGE, 16, 4) 2149 FIELD(ID_AA64MMFR2, CCIDX, 20, 4) 2150 FIELD(ID_AA64MMFR2, NV, 24, 4) 2151 FIELD(ID_AA64MMFR2, ST, 28, 4) 2152 FIELD(ID_AA64MMFR2, AT, 32, 4) 2153 FIELD(ID_AA64MMFR2, IDS, 36, 4) 2154 FIELD(ID_AA64MMFR2, FWB, 40, 4) 2155 FIELD(ID_AA64MMFR2, TTL, 48, 4) 2156 FIELD(ID_AA64MMFR2, BBM, 52, 4) 2157 FIELD(ID_AA64MMFR2, EVT, 56, 4) 2158 FIELD(ID_AA64MMFR2, E0PD, 60, 4) 2159 2160 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) 2161 FIELD(ID_AA64DFR0, TRACEVER, 4, 4) 2162 FIELD(ID_AA64DFR0, PMUVER, 8, 4) 2163 FIELD(ID_AA64DFR0, BRPS, 12, 4) 2164 FIELD(ID_AA64DFR0, WRPS, 20, 4) 2165 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) 2166 FIELD(ID_AA64DFR0, PMSVER, 32, 4) 2167 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) 2168 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) 2169 FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4) 2170 FIELD(ID_AA64DFR0, MTPMU, 48, 4) 2171 FIELD(ID_AA64DFR0, BRBE, 52, 4) 2172 FIELD(ID_AA64DFR0, HPMN0, 60, 4) 2173 2174 FIELD(ID_AA64ZFR0, SVEVER, 0, 4) 2175 FIELD(ID_AA64ZFR0, AES, 4, 4) 2176 FIELD(ID_AA64ZFR0, BITPERM, 16, 4) 2177 FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4) 2178 FIELD(ID_AA64ZFR0, SHA3, 32, 4) 2179 FIELD(ID_AA64ZFR0, SM4, 40, 4) 2180 FIELD(ID_AA64ZFR0, I8MM, 44, 4) 2181 FIELD(ID_AA64ZFR0, F32MM, 52, 4) 2182 FIELD(ID_AA64ZFR0, F64MM, 56, 4) 2183 2184 FIELD(ID_DFR0, COPDBG, 0, 4) 2185 FIELD(ID_DFR0, COPSDBG, 4, 4) 2186 FIELD(ID_DFR0, MMAPDBG, 8, 4) 2187 FIELD(ID_DFR0, COPTRC, 12, 4) 2188 FIELD(ID_DFR0, MMAPTRC, 16, 4) 2189 FIELD(ID_DFR0, MPROFDBG, 20, 4) 2190 FIELD(ID_DFR0, PERFMON, 24, 4) 2191 FIELD(ID_DFR0, TRACEFILT, 28, 4) 2192 2193 FIELD(ID_DFR1, MTPMU, 0, 4) 2194 FIELD(ID_DFR1, HPMN0, 4, 4) 2195 2196 FIELD(DBGDIDR, SE_IMP, 12, 1) 2197 FIELD(DBGDIDR, NSUHD_IMP, 14, 1) 2198 FIELD(DBGDIDR, VERSION, 16, 4) 2199 FIELD(DBGDIDR, CTX_CMPS, 20, 4) 2200 FIELD(DBGDIDR, BRPS, 24, 4) 2201 FIELD(DBGDIDR, WRPS, 28, 4) 2202 2203 FIELD(MVFR0, SIMDREG, 0, 4) 2204 FIELD(MVFR0, FPSP, 4, 4) 2205 FIELD(MVFR0, FPDP, 8, 4) 2206 FIELD(MVFR0, FPTRAP, 12, 4) 2207 FIELD(MVFR0, FPDIVIDE, 16, 4) 2208 FIELD(MVFR0, FPSQRT, 20, 4) 2209 FIELD(MVFR0, FPSHVEC, 24, 4) 2210 FIELD(MVFR0, FPROUND, 28, 4) 2211 2212 FIELD(MVFR1, FPFTZ, 0, 4) 2213 FIELD(MVFR1, FPDNAN, 4, 4) 2214 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */ 2215 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */ 2216 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */ 2217 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */ 2218 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */ 2219 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */ 2220 FIELD(MVFR1, FPHP, 24, 4) 2221 FIELD(MVFR1, SIMDFMAC, 28, 4) 2222 2223 FIELD(MVFR2, SIMDMISC, 0, 4) 2224 FIELD(MVFR2, FPMISC, 4, 4) 2225 2226 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 2227 2228 /* If adding a feature bit which corresponds to a Linux ELF 2229 * HWCAP bit, remember to update the feature-bit-to-hwcap 2230 * mapping in linux-user/elfload.c:get_elf_hwcap(). 2231 */ 2232 enum arm_features { 2233 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 2234 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 2235 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 2236 ARM_FEATURE_V6, 2237 ARM_FEATURE_V6K, 2238 ARM_FEATURE_V7, 2239 ARM_FEATURE_THUMB2, 2240 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 2241 ARM_FEATURE_NEON, 2242 ARM_FEATURE_M, /* Microcontroller profile. */ 2243 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 2244 ARM_FEATURE_THUMB2EE, 2245 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 2246 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 2247 ARM_FEATURE_V4T, 2248 ARM_FEATURE_V5, 2249 ARM_FEATURE_STRONGARM, 2250 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 2251 ARM_FEATURE_GENERIC_TIMER, 2252 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 2253 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 2254 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 2255 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 2256 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 2257 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 2258 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 2259 ARM_FEATURE_V8, 2260 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 2261 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 2262 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 2263 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 2264 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 2265 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 2266 ARM_FEATURE_PMU, /* has PMU support */ 2267 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 2268 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 2269 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 2270 ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ 2271 }; 2272 2273 static inline int arm_feature(CPUARMState *env, int feature) 2274 { 2275 return (env->features & (1ULL << feature)) != 0; 2276 } 2277 2278 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); 2279 2280 #if !defined(CONFIG_USER_ONLY) 2281 /* Return true if exception levels below EL3 are in secure state, 2282 * or would be following an exception return to that level. 2283 * Unlike arm_is_secure() (which is always a question about the 2284 * _current_ state of the CPU) this doesn't care about the current 2285 * EL or mode. 2286 */ 2287 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2288 { 2289 if (arm_feature(env, ARM_FEATURE_EL3)) { 2290 return !(env->cp15.scr_el3 & SCR_NS); 2291 } else { 2292 /* If EL3 is not supported then the secure state is implementation 2293 * defined, in which case QEMU defaults to non-secure. 2294 */ 2295 return false; 2296 } 2297 } 2298 2299 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 2300 static inline bool arm_is_el3_or_mon(CPUARMState *env) 2301 { 2302 if (arm_feature(env, ARM_FEATURE_EL3)) { 2303 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 2304 /* CPU currently in AArch64 state and EL3 */ 2305 return true; 2306 } else if (!is_a64(env) && 2307 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 2308 /* CPU currently in AArch32 state and monitor mode */ 2309 return true; 2310 } 2311 } 2312 return false; 2313 } 2314 2315 /* Return true if the processor is in secure state */ 2316 static inline bool arm_is_secure(CPUARMState *env) 2317 { 2318 if (arm_is_el3_or_mon(env)) { 2319 return true; 2320 } 2321 return arm_is_secure_below_el3(env); 2322 } 2323 2324 /* 2325 * Return true if the current security state has AArch64 EL2 or AArch32 Hyp. 2326 * This corresponds to the pseudocode EL2Enabled() 2327 */ 2328 static inline bool arm_is_el2_enabled(CPUARMState *env) 2329 { 2330 if (arm_feature(env, ARM_FEATURE_EL2)) { 2331 if (arm_is_secure_below_el3(env)) { 2332 return (env->cp15.scr_el3 & SCR_EEL2) != 0; 2333 } 2334 return true; 2335 } 2336 return false; 2337 } 2338 2339 #else 2340 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2341 { 2342 return false; 2343 } 2344 2345 static inline bool arm_is_secure(CPUARMState *env) 2346 { 2347 return false; 2348 } 2349 2350 static inline bool arm_is_el2_enabled(CPUARMState *env) 2351 { 2352 return false; 2353 } 2354 #endif 2355 2356 /** 2357 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 2358 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 2359 * "for all purposes other than a direct read or write access of HCR_EL2." 2360 * Not included here is HCR_RW. 2361 */ 2362 uint64_t arm_hcr_el2_eff(CPUARMState *env); 2363 uint64_t arm_hcrx_el2_eff(CPUARMState *env); 2364 2365 /* Return true if the specified exception level is running in AArch64 state. */ 2366 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 2367 { 2368 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 2369 * and if we're not in EL0 then the state of EL0 isn't well defined.) 2370 */ 2371 assert(el >= 1 && el <= 3); 2372 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 2373 2374 /* The highest exception level is always at the maximum supported 2375 * register width, and then lower levels have a register width controlled 2376 * by bits in the SCR or HCR registers. 2377 */ 2378 if (el == 3) { 2379 return aa64; 2380 } 2381 2382 if (arm_feature(env, ARM_FEATURE_EL3) && 2383 ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) { 2384 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 2385 } 2386 2387 if (el == 2) { 2388 return aa64; 2389 } 2390 2391 if (arm_is_el2_enabled(env)) { 2392 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 2393 } 2394 2395 return aa64; 2396 } 2397 2398 /* Function for determing whether guest cp register reads and writes should 2399 * access the secure or non-secure bank of a cp register. When EL3 is 2400 * operating in AArch32 state, the NS-bit determines whether the secure 2401 * instance of a cp register should be used. When EL3 is AArch64 (or if 2402 * it doesn't exist at all) then there is no register banking, and all 2403 * accesses are to the non-secure version. 2404 */ 2405 static inline bool access_secure_reg(CPUARMState *env) 2406 { 2407 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 2408 !arm_el_is_aa64(env, 3) && 2409 !(env->cp15.scr_el3 & SCR_NS)); 2410 2411 return ret; 2412 } 2413 2414 /* Macros for accessing a specified CP register bank */ 2415 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 2416 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 2417 2418 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 2419 do { \ 2420 if (_secure) { \ 2421 (_env)->cp15._regname##_s = (_val); \ 2422 } else { \ 2423 (_env)->cp15._regname##_ns = (_val); \ 2424 } \ 2425 } while (0) 2426 2427 /* Macros for automatically accessing a specific CP register bank depending on 2428 * the current secure state of the system. These macros are not intended for 2429 * supporting instruction translation reads/writes as these are dependent 2430 * solely on the SCR.NS bit and not the mode. 2431 */ 2432 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 2433 A32_BANKED_REG_GET((_env), _regname, \ 2434 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 2435 2436 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 2437 A32_BANKED_REG_SET((_env), _regname, \ 2438 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 2439 (_val)) 2440 2441 void arm_cpu_list(void); 2442 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 2443 uint32_t cur_el, bool secure); 2444 2445 /* Interface between CPU and Interrupt controller. */ 2446 #ifndef CONFIG_USER_ONLY 2447 bool armv7m_nvic_can_take_pending_exception(void *opaque); 2448 #else 2449 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) 2450 { 2451 return true; 2452 } 2453 #endif 2454 /** 2455 * armv7m_nvic_set_pending: mark the specified exception as pending 2456 * @opaque: the NVIC 2457 * @irq: the exception number to mark pending 2458 * @secure: false for non-banked exceptions or for the nonsecure 2459 * version of a banked exception, true for the secure version of a banked 2460 * exception. 2461 * 2462 * Marks the specified exception as pending. Note that we will assert() 2463 * if @secure is true and @irq does not specify one of the fixed set 2464 * of architecturally banked exceptions. 2465 */ 2466 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); 2467 /** 2468 * armv7m_nvic_set_pending_derived: mark this derived exception as pending 2469 * @opaque: the NVIC 2470 * @irq: the exception number to mark pending 2471 * @secure: false for non-banked exceptions or for the nonsecure 2472 * version of a banked exception, true for the secure version of a banked 2473 * exception. 2474 * 2475 * Similar to armv7m_nvic_set_pending(), but specifically for derived 2476 * exceptions (exceptions generated in the course of trying to take 2477 * a different exception). 2478 */ 2479 void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); 2480 /** 2481 * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending 2482 * @opaque: the NVIC 2483 * @irq: the exception number to mark pending 2484 * @secure: false for non-banked exceptions or for the nonsecure 2485 * version of a banked exception, true for the secure version of a banked 2486 * exception. 2487 * 2488 * Similar to armv7m_nvic_set_pending(), but specifically for exceptions 2489 * generated in the course of lazy stacking of FP registers. 2490 */ 2491 void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure); 2492 /** 2493 * armv7m_nvic_get_pending_irq_info: return highest priority pending 2494 * exception, and whether it targets Secure state 2495 * @opaque: the NVIC 2496 * @pirq: set to pending exception number 2497 * @ptargets_secure: set to whether pending exception targets Secure 2498 * 2499 * This function writes the number of the highest priority pending 2500 * exception (the one which would be made active by 2501 * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure 2502 * to true if the current highest priority pending exception should 2503 * be taken to Secure state, false for NS. 2504 */ 2505 void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq, 2506 bool *ptargets_secure); 2507 /** 2508 * armv7m_nvic_acknowledge_irq: make highest priority pending exception active 2509 * @opaque: the NVIC 2510 * 2511 * Move the current highest priority pending exception from the pending 2512 * state to the active state, and update v7m.exception to indicate that 2513 * it is the exception currently being handled. 2514 */ 2515 void armv7m_nvic_acknowledge_irq(void *opaque); 2516 /** 2517 * armv7m_nvic_complete_irq: complete specified interrupt or exception 2518 * @opaque: the NVIC 2519 * @irq: the exception number to complete 2520 * @secure: true if this exception was secure 2521 * 2522 * Returns: -1 if the irq was not active 2523 * 1 if completing this irq brought us back to base (no active irqs) 2524 * 0 if there is still an irq active after this one was completed 2525 * (Ignoring -1, this is the same as the RETTOBASE value before completion.) 2526 */ 2527 int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); 2528 /** 2529 * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) 2530 * @opaque: the NVIC 2531 * @irq: the exception number to mark pending 2532 * @secure: false for non-banked exceptions or for the nonsecure 2533 * version of a banked exception, true for the secure version of a banked 2534 * exception. 2535 * 2536 * Return whether an exception is "ready", i.e. whether the exception is 2537 * enabled and is configured at a priority which would allow it to 2538 * interrupt the current execution priority. This controls whether the 2539 * RDY bit for it in the FPCCR is set. 2540 */ 2541 bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure); 2542 /** 2543 * armv7m_nvic_raw_execution_priority: return the raw execution priority 2544 * @opaque: the NVIC 2545 * 2546 * Returns: the raw execution priority as defined by the v8M architecture. 2547 * This is the execution priority minus the effects of AIRCR.PRIS, 2548 * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. 2549 * (v8M ARM ARM I_PKLD.) 2550 */ 2551 int armv7m_nvic_raw_execution_priority(void *opaque); 2552 /** 2553 * armv7m_nvic_neg_prio_requested: return true if the requested execution 2554 * priority is negative for the specified security state. 2555 * @opaque: the NVIC 2556 * @secure: the security state to test 2557 * This corresponds to the pseudocode IsReqExecPriNeg(). 2558 */ 2559 #ifndef CONFIG_USER_ONLY 2560 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); 2561 #else 2562 static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) 2563 { 2564 return false; 2565 } 2566 #endif 2567 2568 /* Interface for defining coprocessor registers. 2569 * Registers are defined in tables of arm_cp_reginfo structs 2570 * which are passed to define_arm_cp_regs(). 2571 */ 2572 2573 /* When looking up a coprocessor register we look for it 2574 * via an integer which encodes all of: 2575 * coprocessor number 2576 * Crn, Crm, opc1, opc2 fields 2577 * 32 or 64 bit register (ie is it accessed via MRC/MCR 2578 * or via MRRC/MCRR?) 2579 * non-secure/secure bank (AArch32 only) 2580 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 2581 * (In this case crn and opc2 should be zero.) 2582 * For AArch64, there is no 32/64 bit size distinction; 2583 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 2584 * and 4 bit CRn and CRm. The encoding patterns are chosen 2585 * to be easy to convert to and from the KVM encodings, and also 2586 * so that the hashtable can contain both AArch32 and AArch64 2587 * registers (to allow for interprocessing where we might run 2588 * 32 bit code on a 64 bit core). 2589 */ 2590 /* This bit is private to our hashtable cpreg; in KVM register 2591 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 2592 * in the upper bits of the 64 bit ID. 2593 */ 2594 #define CP_REG_AA64_SHIFT 28 2595 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 2596 2597 /* To enable banking of coprocessor registers depending on ns-bit we 2598 * add a bit to distinguish between secure and non-secure cpregs in the 2599 * hashtable. 2600 */ 2601 #define CP_REG_NS_SHIFT 29 2602 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 2603 2604 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 2605 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 2606 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 2607 2608 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 2609 (CP_REG_AA64_MASK | \ 2610 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 2611 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 2612 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 2613 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 2614 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 2615 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 2616 2617 /* Convert a full 64 bit KVM register ID to the truncated 32 bit 2618 * version used as a key for the coprocessor register hashtable 2619 */ 2620 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 2621 { 2622 uint32_t cpregid = kvmid; 2623 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 2624 cpregid |= CP_REG_AA64_MASK; 2625 } else { 2626 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 2627 cpregid |= (1 << 15); 2628 } 2629 2630 /* KVM is always non-secure so add the NS flag on AArch32 register 2631 * entries. 2632 */ 2633 cpregid |= 1 << CP_REG_NS_SHIFT; 2634 } 2635 return cpregid; 2636 } 2637 2638 /* Convert a truncated 32 bit hashtable key into the full 2639 * 64 bit KVM register ID. 2640 */ 2641 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 2642 { 2643 uint64_t kvmid; 2644 2645 if (cpregid & CP_REG_AA64_MASK) { 2646 kvmid = cpregid & ~CP_REG_AA64_MASK; 2647 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 2648 } else { 2649 kvmid = cpregid & ~(1 << 15); 2650 if (cpregid & (1 << 15)) { 2651 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 2652 } else { 2653 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 2654 } 2655 } 2656 return kvmid; 2657 } 2658 2659 /* Return the highest implemented Exception Level */ 2660 static inline int arm_highest_el(CPUARMState *env) 2661 { 2662 if (arm_feature(env, ARM_FEATURE_EL3)) { 2663 return 3; 2664 } 2665 if (arm_feature(env, ARM_FEATURE_EL2)) { 2666 return 2; 2667 } 2668 return 1; 2669 } 2670 2671 /* Return true if a v7M CPU is in Handler mode */ 2672 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2673 { 2674 return env->v7m.exception != 0; 2675 } 2676 2677 /* Return the current Exception Level (as per ARMv8; note that this differs 2678 * from the ARMv7 Privilege Level). 2679 */ 2680 static inline int arm_current_el(CPUARMState *env) 2681 { 2682 if (arm_feature(env, ARM_FEATURE_M)) { 2683 return arm_v7m_is_handler_mode(env) || 2684 !(env->v7m.control[env->v7m.secure] & 1); 2685 } 2686 2687 if (is_a64(env)) { 2688 return extract32(env->pstate, 2, 2); 2689 } 2690 2691 switch (env->uncached_cpsr & 0x1f) { 2692 case ARM_CPU_MODE_USR: 2693 return 0; 2694 case ARM_CPU_MODE_HYP: 2695 return 2; 2696 case ARM_CPU_MODE_MON: 2697 return 3; 2698 default: 2699 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2700 /* If EL3 is 32-bit then all secure privileged modes run in 2701 * EL3 2702 */ 2703 return 3; 2704 } 2705 2706 return 1; 2707 } 2708 } 2709 2710 /** 2711 * write_list_to_cpustate 2712 * @cpu: ARMCPU 2713 * 2714 * For each register listed in the ARMCPU cpreg_indexes list, write 2715 * its value from the cpreg_values list into the ARMCPUState structure. 2716 * This updates TCG's working data structures from KVM data or 2717 * from incoming migration state. 2718 * 2719 * Returns: true if all register values were updated correctly, 2720 * false if some register was unknown or could not be written. 2721 * Note that we do not stop early on failure -- we will attempt 2722 * writing all registers in the list. 2723 */ 2724 bool write_list_to_cpustate(ARMCPU *cpu); 2725 2726 /** 2727 * write_cpustate_to_list: 2728 * @cpu: ARMCPU 2729 * @kvm_sync: true if this is for syncing back to KVM 2730 * 2731 * For each register listed in the ARMCPU cpreg_indexes list, write 2732 * its value from the ARMCPUState structure into the cpreg_values list. 2733 * This is used to copy info from TCG's working data structures into 2734 * KVM or for outbound migration. 2735 * 2736 * @kvm_sync is true if we are doing this in order to sync the 2737 * register state back to KVM. In this case we will only update 2738 * values in the list if the previous list->cpustate sync actually 2739 * successfully wrote the CPU state. Otherwise we will keep the value 2740 * that is in the list. 2741 * 2742 * Returns: true if all register values were read correctly, 2743 * false if some register was unknown or could not be read. 2744 * Note that we do not stop early on failure -- we will attempt 2745 * reading all registers in the list. 2746 */ 2747 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); 2748 2749 #define ARM_CPUID_TI915T 0x54029152 2750 #define ARM_CPUID_TI925T 0x54029252 2751 2752 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU 2753 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) 2754 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2755 2756 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU 2757 2758 #define cpu_list arm_cpu_list 2759 2760 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2761 * 2762 * If EL3 is 64-bit: 2763 * + NonSecure EL1 & 0 stage 1 2764 * + NonSecure EL1 & 0 stage 2 2765 * + NonSecure EL2 2766 * + NonSecure EL2 & 0 (ARMv8.1-VHE) 2767 * + Secure EL1 & 0 2768 * + Secure EL3 2769 * If EL3 is 32-bit: 2770 * + NonSecure PL1 & 0 stage 1 2771 * + NonSecure PL1 & 0 stage 2 2772 * + NonSecure PL2 2773 * + Secure PL0 2774 * + Secure PL1 2775 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2776 * 2777 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2778 * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes, 2779 * because they may differ in access permissions even if the VA->PA map is 2780 * the same 2781 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2782 * translation, which means that we have one mmu_idx that deals with two 2783 * concatenated translation regimes [this sort of combined s1+2 TLB is 2784 * architecturally permitted] 2785 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2786 * handling via the TLB. The only way to do a stage 1 translation without 2787 * the immediate stage 2 translation is via the ATS or AT system insns, 2788 * which can be slow-pathed and always do a page table walk. 2789 * The only use of stage 2 translations is either as part of an s1+2 2790 * lookup or when loading the descriptors during a stage 1 page table walk, 2791 * and in both those cases we don't use the TLB. 2792 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2793 * translation regimes, because they map reasonably well to each other 2794 * and they can't both be active at the same time. 2795 * 5. we want to be able to use the TLB for accesses done as part of a 2796 * stage1 page table walk, rather than having to walk the stage2 page 2797 * table over and over. 2798 * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access 2799 * Never (PAN) bit within PSTATE. 2800 * 2801 * This gives us the following list of cases: 2802 * 2803 * NS EL0 EL1&0 stage 1+2 (aka NS PL0) 2804 * NS EL1 EL1&0 stage 1+2 (aka NS PL1) 2805 * NS EL1 EL1&0 stage 1+2 +PAN 2806 * NS EL0 EL2&0 2807 * NS EL2 EL2&0 2808 * NS EL2 EL2&0 +PAN 2809 * NS EL2 (aka NS PL2) 2810 * S EL0 EL1&0 (aka S PL0) 2811 * S EL1 EL1&0 (not used if EL3 is 32 bit) 2812 * S EL1 EL1&0 +PAN 2813 * S EL3 (aka S PL1) 2814 * 2815 * for a total of 11 different mmu_idx. 2816 * 2817 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2818 * as A profile. They only need to distinguish NS EL0 and NS EL1 (and 2819 * NS EL2 if we ever model a Cortex-R52). 2820 * 2821 * M profile CPUs are rather different as they do not have a true MMU. 2822 * They have the following different MMU indexes: 2823 * User 2824 * Privileged 2825 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2826 * Privileged, execution priority negative (ditto) 2827 * If the CPU supports the v8M Security Extension then there are also: 2828 * Secure User 2829 * Secure Privileged 2830 * Secure User, execution priority negative 2831 * Secure Privileged, execution priority negative 2832 * 2833 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2834 * are not quite the same -- different CPU types (most notably M profile 2835 * vs A/R profile) would like to use MMU indexes with different semantics, 2836 * but since we don't ever need to use all of those in a single CPU we 2837 * can avoid having to set NB_MMU_MODES to "total number of A profile MMU 2838 * modes + total number of M profile MMU modes". The lower bits of 2839 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2840 * the same for any particular CPU. 2841 * Variables of type ARMMUIdx are always full values, and the core 2842 * index values are in variables of type 'int'. 2843 * 2844 * Our enumeration includes at the end some entries which are not "true" 2845 * mmu_idx values in that they don't have corresponding TLBs and are only 2846 * valid for doing slow path page table walks. 2847 * 2848 * The constant names here are patterned after the general style of the names 2849 * of the AT/ATS operations. 2850 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2851 * For M profile we arrange them to have a bit for priv, a bit for negpri 2852 * and a bit for secure. 2853 */ 2854 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2855 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2856 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2857 2858 /* Meanings of the bits for A profile mmu idx values */ 2859 #define ARM_MMU_IDX_A_NS 0x8 2860 2861 /* Meanings of the bits for M profile mmu idx values */ 2862 #define ARM_MMU_IDX_M_PRIV 0x1 2863 #define ARM_MMU_IDX_M_NEGPRI 0x2 2864 #define ARM_MMU_IDX_M_S 0x4 /* Secure */ 2865 2866 #define ARM_MMU_IDX_TYPE_MASK \ 2867 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB) 2868 #define ARM_MMU_IDX_COREIDX_MASK 0xf 2869 2870 typedef enum ARMMMUIdx { 2871 /* 2872 * A-profile. 2873 */ 2874 ARMMMUIdx_SE10_0 = 0 | ARM_MMU_IDX_A, 2875 ARMMMUIdx_SE20_0 = 1 | ARM_MMU_IDX_A, 2876 ARMMMUIdx_SE10_1 = 2 | ARM_MMU_IDX_A, 2877 ARMMMUIdx_SE20_2 = 3 | ARM_MMU_IDX_A, 2878 ARMMMUIdx_SE10_1_PAN = 4 | ARM_MMU_IDX_A, 2879 ARMMMUIdx_SE20_2_PAN = 5 | ARM_MMU_IDX_A, 2880 ARMMMUIdx_SE2 = 6 | ARM_MMU_IDX_A, 2881 ARMMMUIdx_SE3 = 7 | ARM_MMU_IDX_A, 2882 2883 ARMMMUIdx_E10_0 = ARMMMUIdx_SE10_0 | ARM_MMU_IDX_A_NS, 2884 ARMMMUIdx_E20_0 = ARMMMUIdx_SE20_0 | ARM_MMU_IDX_A_NS, 2885 ARMMMUIdx_E10_1 = ARMMMUIdx_SE10_1 | ARM_MMU_IDX_A_NS, 2886 ARMMMUIdx_E20_2 = ARMMMUIdx_SE20_2 | ARM_MMU_IDX_A_NS, 2887 ARMMMUIdx_E10_1_PAN = ARMMMUIdx_SE10_1_PAN | ARM_MMU_IDX_A_NS, 2888 ARMMMUIdx_E20_2_PAN = ARMMMUIdx_SE20_2_PAN | ARM_MMU_IDX_A_NS, 2889 ARMMMUIdx_E2 = ARMMMUIdx_SE2 | ARM_MMU_IDX_A_NS, 2890 2891 /* 2892 * These are not allocated TLBs and are used only for AT system 2893 * instructions or for the first stage of an S12 page table walk. 2894 */ 2895 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, 2896 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, 2897 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB, 2898 ARMMMUIdx_Stage1_SE0 = 3 | ARM_MMU_IDX_NOTLB, 2899 ARMMMUIdx_Stage1_SE1 = 4 | ARM_MMU_IDX_NOTLB, 2900 ARMMMUIdx_Stage1_SE1_PAN = 5 | ARM_MMU_IDX_NOTLB, 2901 /* 2902 * Not allocated a TLB: used only for second stage of an S12 page 2903 * table walk, or for descriptor loads during first stage of an S1 2904 * page table walk. Note that if we ever want to have a TLB for this 2905 * then various TLB flush insns which currently are no-ops or flush 2906 * only stage 1 MMU indexes will need to change to flush stage 2. 2907 */ 2908 ARMMMUIdx_Stage2 = 6 | ARM_MMU_IDX_NOTLB, 2909 ARMMMUIdx_Stage2_S = 7 | ARM_MMU_IDX_NOTLB, 2910 2911 /* 2912 * M-profile. 2913 */ 2914 ARMMMUIdx_MUser = ARM_MMU_IDX_M, 2915 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV, 2916 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI, 2917 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI, 2918 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S, 2919 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S, 2920 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S, 2921 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S, 2922 } ARMMMUIdx; 2923 2924 /* 2925 * Bit macros for the core-mmu-index values for each index, 2926 * for use when calling tlb_flush_by_mmuidx() and friends. 2927 */ 2928 #define TO_CORE_BIT(NAME) \ 2929 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK) 2930 2931 typedef enum ARMMMUIdxBit { 2932 TO_CORE_BIT(E10_0), 2933 TO_CORE_BIT(E20_0), 2934 TO_CORE_BIT(E10_1), 2935 TO_CORE_BIT(E10_1_PAN), 2936 TO_CORE_BIT(E2), 2937 TO_CORE_BIT(E20_2), 2938 TO_CORE_BIT(E20_2_PAN), 2939 TO_CORE_BIT(SE10_0), 2940 TO_CORE_BIT(SE20_0), 2941 TO_CORE_BIT(SE10_1), 2942 TO_CORE_BIT(SE20_2), 2943 TO_CORE_BIT(SE10_1_PAN), 2944 TO_CORE_BIT(SE20_2_PAN), 2945 TO_CORE_BIT(SE2), 2946 TO_CORE_BIT(SE3), 2947 2948 TO_CORE_BIT(MUser), 2949 TO_CORE_BIT(MPriv), 2950 TO_CORE_BIT(MUserNegPri), 2951 TO_CORE_BIT(MPrivNegPri), 2952 TO_CORE_BIT(MSUser), 2953 TO_CORE_BIT(MSPriv), 2954 TO_CORE_BIT(MSUserNegPri), 2955 TO_CORE_BIT(MSPrivNegPri), 2956 } ARMMMUIdxBit; 2957 2958 #undef TO_CORE_BIT 2959 2960 #define MMU_USER_IDX 0 2961 2962 /* Indexes used when registering address spaces with cpu_address_space_init */ 2963 typedef enum ARMASIdx { 2964 ARMASIdx_NS = 0, 2965 ARMASIdx_S = 1, 2966 ARMASIdx_TagNS = 2, 2967 ARMASIdx_TagS = 3, 2968 } ARMASIdx; 2969 2970 /* Return the Exception Level targeted by debug exceptions. */ 2971 static inline int arm_debug_target_el(CPUARMState *env) 2972 { 2973 bool secure = arm_is_secure(env); 2974 bool route_to_el2 = false; 2975 2976 if (arm_is_el2_enabled(env)) { 2977 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || 2978 env->cp15.mdcr_el2 & MDCR_TDE; 2979 } 2980 2981 if (route_to_el2) { 2982 return 2; 2983 } else if (arm_feature(env, ARM_FEATURE_EL3) && 2984 !arm_el_is_aa64(env, 3) && secure) { 2985 return 3; 2986 } else { 2987 return 1; 2988 } 2989 } 2990 2991 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 2992 { 2993 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 2994 * CSSELR is RAZ/WI. 2995 */ 2996 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 2997 } 2998 2999 /* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */ 3000 static inline bool aa64_generate_debug_exceptions(CPUARMState *env) 3001 { 3002 int cur_el = arm_current_el(env); 3003 int debug_el; 3004 3005 if (cur_el == 3) { 3006 return false; 3007 } 3008 3009 /* MDCR_EL3.SDD disables debug events from Secure state */ 3010 if (arm_is_secure_below_el3(env) 3011 && extract32(env->cp15.mdcr_el3, 16, 1)) { 3012 return false; 3013 } 3014 3015 /* 3016 * Same EL to same EL debug exceptions need MDSCR_KDE enabled 3017 * while not masking the (D)ebug bit in DAIF. 3018 */ 3019 debug_el = arm_debug_target_el(env); 3020 3021 if (cur_el == debug_el) { 3022 return extract32(env->cp15.mdscr_el1, 13, 1) 3023 && !(env->daif & PSTATE_D); 3024 } 3025 3026 /* Otherwise the debug target needs to be a higher EL */ 3027 return debug_el > cur_el; 3028 } 3029 3030 static inline bool aa32_generate_debug_exceptions(CPUARMState *env) 3031 { 3032 int el = arm_current_el(env); 3033 3034 if (el == 0 && arm_el_is_aa64(env, 1)) { 3035 return aa64_generate_debug_exceptions(env); 3036 } 3037 3038 if (arm_is_secure(env)) { 3039 int spd; 3040 3041 if (el == 0 && (env->cp15.sder & 1)) { 3042 /* SDER.SUIDEN means debug exceptions from Secure EL0 3043 * are always enabled. Otherwise they are controlled by 3044 * SDCR.SPD like those from other Secure ELs. 3045 */ 3046 return true; 3047 } 3048 3049 spd = extract32(env->cp15.mdcr_el3, 14, 2); 3050 switch (spd) { 3051 case 1: 3052 /* SPD == 0b01 is reserved, but behaves as 0b00. */ 3053 case 0: 3054 /* For 0b00 we return true if external secure invasive debug 3055 * is enabled. On real hardware this is controlled by external 3056 * signals to the core. QEMU always permits debug, and behaves 3057 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. 3058 */ 3059 return true; 3060 case 2: 3061 return false; 3062 case 3: 3063 return true; 3064 } 3065 } 3066 3067 return el != 2; 3068 } 3069 3070 /* Return true if debugging exceptions are currently enabled. 3071 * This corresponds to what in ARM ARM pseudocode would be 3072 * if UsingAArch32() then 3073 * return AArch32.GenerateDebugExceptions() 3074 * else 3075 * return AArch64.GenerateDebugExceptions() 3076 * We choose to push the if() down into this function for clarity, 3077 * since the pseudocode has it at all callsites except for the one in 3078 * CheckSoftwareStep(), where it is elided because both branches would 3079 * always return the same value. 3080 */ 3081 static inline bool arm_generate_debug_exceptions(CPUARMState *env) 3082 { 3083 if (env->aarch64) { 3084 return aa64_generate_debug_exceptions(env); 3085 } else { 3086 return aa32_generate_debug_exceptions(env); 3087 } 3088 } 3089 3090 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check 3091 * implicitly means this always returns false in pre-v8 CPUs.) 3092 */ 3093 static inline bool arm_singlestep_active(CPUARMState *env) 3094 { 3095 return extract32(env->cp15.mdscr_el1, 0, 1) 3096 && arm_el_is_aa64(env, arm_debug_target_el(env)) 3097 && arm_generate_debug_exceptions(env); 3098 } 3099 3100 static inline bool arm_sctlr_b(CPUARMState *env) 3101 { 3102 return 3103 /* We need not implement SCTLR.ITD in user-mode emulation, so 3104 * let linux-user ignore the fact that it conflicts with SCTLR_B. 3105 * This lets people run BE32 binaries with "-cpu any". 3106 */ 3107 #ifndef CONFIG_USER_ONLY 3108 !arm_feature(env, ARM_FEATURE_V7) && 3109 #endif 3110 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 3111 } 3112 3113 uint64_t arm_sctlr(CPUARMState *env, int el); 3114 3115 static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, 3116 bool sctlr_b) 3117 { 3118 #ifdef CONFIG_USER_ONLY 3119 /* 3120 * In system mode, BE32 is modelled in line with the 3121 * architecture (as word-invariant big-endianness), where loads 3122 * and stores are done little endian but from addresses which 3123 * are adjusted by XORing with the appropriate constant. So the 3124 * endianness to use for the raw data access is not affected by 3125 * SCTLR.B. 3126 * In user mode, however, we model BE32 as byte-invariant 3127 * big-endianness (because user-only code cannot tell the 3128 * difference), and so we need to use a data access endianness 3129 * that depends on SCTLR.B. 3130 */ 3131 if (sctlr_b) { 3132 return true; 3133 } 3134 #endif 3135 /* In 32bit endianness is determined by looking at CPSR's E bit */ 3136 return env->uncached_cpsr & CPSR_E; 3137 } 3138 3139 static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr) 3140 { 3141 return sctlr & (el ? SCTLR_EE : SCTLR_E0E); 3142 } 3143 3144 /* Return true if the processor is in big-endian mode. */ 3145 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 3146 { 3147 if (!is_a64(env)) { 3148 return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); 3149 } else { 3150 int cur_el = arm_current_el(env); 3151 uint64_t sctlr = arm_sctlr(env, cur_el); 3152 return arm_cpu_data_is_big_endian_a64(cur_el, sctlr); 3153 } 3154 } 3155 3156 #include "exec/cpu-all.h" 3157 3158 /* 3159 * We have more than 32-bits worth of state per TB, so we split the data 3160 * between tb->flags and tb->cs_base, which is otherwise unused for ARM. 3161 * We collect these two parts in CPUARMTBFlags where they are named 3162 * flags and flags2 respectively. 3163 * 3164 * The flags that are shared between all execution modes, TBFLAG_ANY, 3165 * are stored in flags. The flags that are specific to a given mode 3166 * are stores in flags2. Since cs_base is sized on the configured 3167 * address size, flags2 always has 64-bits for A64, and a minimum of 3168 * 32-bits for A32 and M32. 3169 * 3170 * The bits for 32-bit A-profile and M-profile partially overlap: 3171 * 3172 * 31 23 11 10 0 3173 * +-------------+----------+----------------+ 3174 * | | | TBFLAG_A32 | 3175 * | TBFLAG_AM32 | +-----+----------+ 3176 * | | |TBFLAG_M32| 3177 * +-------------+----------------+----------+ 3178 * 31 23 6 5 0 3179 * 3180 * Unless otherwise noted, these bits are cached in env->hflags. 3181 */ 3182 FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1) 3183 FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1) 3184 FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1) /* Not cached. */ 3185 FIELD(TBFLAG_ANY, BE_DATA, 3, 1) 3186 FIELD(TBFLAG_ANY, MMUIDX, 4, 4) 3187 /* Target EL if we take a floating-point-disabled exception */ 3188 FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) 3189 /* For A-profile only, target EL for debug exceptions. */ 3190 FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 10, 2) 3191 /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ 3192 FIELD(TBFLAG_ANY, ALIGN_MEM, 12, 1) 3193 FIELD(TBFLAG_ANY, PSTATE__IL, 13, 1) 3194 3195 /* 3196 * Bit usage when in AArch32 state, both A- and M-profile. 3197 */ 3198 FIELD(TBFLAG_AM32, CONDEXEC, 24, 8) /* Not cached. */ 3199 FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cached. */ 3200 3201 /* 3202 * Bit usage when in AArch32 state, for A-profile only. 3203 */ 3204 FIELD(TBFLAG_A32, VECLEN, 0, 3) /* Not cached. */ 3205 FIELD(TBFLAG_A32, VECSTRIDE, 3, 2) /* Not cached. */ 3206 /* 3207 * We store the bottom two bits of the CPAR as TB flags and handle 3208 * checks on the other bits at runtime. This shares the same bits as 3209 * VECSTRIDE, which is OK as no XScale CPU has VFP. 3210 * Not cached, because VECLEN+VECSTRIDE are not cached. 3211 */ 3212 FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2) 3213 FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ 3214 FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */ 3215 FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1) 3216 /* 3217 * Indicates whether cp register reads and writes by guest code should access 3218 * the secure or nonsecure bank of banked registers; note that this is not 3219 * the same thing as the current security state of the processor! 3220 */ 3221 FIELD(TBFLAG_A32, NS, 10, 1) 3222 3223 /* 3224 * Bit usage when in AArch32 state, for M-profile only. 3225 */ 3226 /* Handler (ie not Thread) mode */ 3227 FIELD(TBFLAG_M32, HANDLER, 0, 1) 3228 /* Whether we should generate stack-limit checks */ 3229 FIELD(TBFLAG_M32, STACKCHECK, 1, 1) 3230 /* Set if FPCCR.LSPACT is set */ 3231 FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */ 3232 /* Set if we must create a new FP context */ 3233 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */ 3234 /* Set if FPCCR.S does not match current security state */ 3235 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */ 3236 /* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */ 3237 FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */ 3238 3239 /* 3240 * Bit usage when in AArch64 state 3241 */ 3242 FIELD(TBFLAG_A64, TBII, 0, 2) 3243 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3244 FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) 3245 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3246 FIELD(TBFLAG_A64, BT, 9, 1) 3247 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ 3248 FIELD(TBFLAG_A64, TBID, 12, 2) 3249 FIELD(TBFLAG_A64, UNPRIV, 14, 1) 3250 FIELD(TBFLAG_A64, ATA, 15, 1) 3251 FIELD(TBFLAG_A64, TCMA, 16, 2) 3252 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) 3253 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) 3254 3255 /* 3256 * Helpers for using the above. 3257 */ 3258 #define DP_TBFLAG_ANY(DST, WHICH, VAL) \ 3259 (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL)) 3260 #define DP_TBFLAG_A64(DST, WHICH, VAL) \ 3261 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A64, WHICH, VAL)) 3262 #define DP_TBFLAG_A32(DST, WHICH, VAL) \ 3263 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL)) 3264 #define DP_TBFLAG_M32(DST, WHICH, VAL) \ 3265 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL)) 3266 #define DP_TBFLAG_AM32(DST, WHICH, VAL) \ 3267 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL)) 3268 3269 #define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH) 3270 #define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A64, WHICH) 3271 #define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH) 3272 #define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH) 3273 #define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH) 3274 3275 /** 3276 * cpu_mmu_index: 3277 * @env: The cpu environment 3278 * @ifetch: True for code access, false for data access. 3279 * 3280 * Return the core mmu index for the current translation regime. 3281 * This function is used by generic TCG code paths. 3282 */ 3283 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) 3284 { 3285 return EX_TBFLAG_ANY(env->hflags, MMUIDX); 3286 } 3287 3288 static inline bool bswap_code(bool sctlr_b) 3289 { 3290 #ifdef CONFIG_USER_ONLY 3291 /* BE8 (SCTLR.B = 0, TARGET_BIG_ENDIAN = 1) is mixed endian. 3292 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_BIG_ENDIAN=0 3293 * would also end up as a mixed-endian mode with BE code, LE data. 3294 */ 3295 return 3296 #if TARGET_BIG_ENDIAN 3297 1 ^ 3298 #endif 3299 sctlr_b; 3300 #else 3301 /* All code access in ARM is little endian, and there are no loaders 3302 * doing swaps that need to be reversed 3303 */ 3304 return 0; 3305 #endif 3306 } 3307 3308 #ifdef CONFIG_USER_ONLY 3309 static inline bool arm_cpu_bswap_data(CPUARMState *env) 3310 { 3311 return 3312 #if TARGET_BIG_ENDIAN 3313 1 ^ 3314 #endif 3315 arm_cpu_data_is_big_endian(env); 3316 } 3317 #endif 3318 3319 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 3320 target_ulong *cs_base, uint32_t *flags); 3321 3322 enum { 3323 QEMU_PSCI_CONDUIT_DISABLED = 0, 3324 QEMU_PSCI_CONDUIT_SMC = 1, 3325 QEMU_PSCI_CONDUIT_HVC = 2, 3326 }; 3327 3328 #ifndef CONFIG_USER_ONLY 3329 /* Return the address space index to use for a memory access */ 3330 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3331 { 3332 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3333 } 3334 3335 /* Return the AddressSpace to use for a memory access 3336 * (which depends on whether the access is S or NS, and whether 3337 * the board gave us a separate AddressSpace for S accesses). 3338 */ 3339 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3340 { 3341 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3342 } 3343 #endif 3344 3345 /** 3346 * arm_register_pre_el_change_hook: 3347 * Register a hook function which will be called immediately before this 3348 * CPU changes exception level or mode. The hook function will be 3349 * passed a pointer to the ARMCPU and the opaque data pointer passed 3350 * to this function when the hook was registered. 3351 * 3352 * Note that if a pre-change hook is called, any registered post-change hooks 3353 * are guaranteed to subsequently be called. 3354 */ 3355 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3356 void *opaque); 3357 /** 3358 * arm_register_el_change_hook: 3359 * Register a hook function which will be called immediately after this 3360 * CPU changes exception level or mode. The hook function will be 3361 * passed a pointer to the ARMCPU and the opaque data pointer passed 3362 * to this function when the hook was registered. 3363 * 3364 * Note that any registered hooks registered here are guaranteed to be called 3365 * if pre-change hooks have been. 3366 */ 3367 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3368 *opaque); 3369 3370 /** 3371 * arm_rebuild_hflags: 3372 * Rebuild the cached TBFLAGS for arbitrary changed processor state. 3373 */ 3374 void arm_rebuild_hflags(CPUARMState *env); 3375 3376 /** 3377 * aa32_vfp_dreg: 3378 * Return a pointer to the Dn register within env in 32-bit mode. 3379 */ 3380 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3381 { 3382 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3383 } 3384 3385 /** 3386 * aa32_vfp_qreg: 3387 * Return a pointer to the Qn register within env in 32-bit mode. 3388 */ 3389 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3390 { 3391 return &env->vfp.zregs[regno].d[0]; 3392 } 3393 3394 /** 3395 * aa64_vfp_qreg: 3396 * Return a pointer to the Qn register within env in 64-bit mode. 3397 */ 3398 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3399 { 3400 return &env->vfp.zregs[regno].d[0]; 3401 } 3402 3403 /* Shared between translate-sve.c and sve_helper.c. */ 3404 extern const uint64_t pred_esz_masks[4]; 3405 3406 /* Helper for the macros below, validating the argument type. */ 3407 static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x) 3408 { 3409 return x; 3410 } 3411 3412 /* 3413 * Lvalue macros for ARM TLB bits that we must cache in the TCG TLB. 3414 * Using these should be a bit more self-documenting than using the 3415 * generic target bits directly. 3416 */ 3417 #define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0) 3418 #define arm_tlb_mte_tagged(x) (typecheck_memtxattrs(x)->target_tlb_bit1) 3419 3420 /* 3421 * AArch64 usage of the PAGE_TARGET_* bits for linux-user. 3422 */ 3423 #define PAGE_BTI PAGE_TARGET_1 3424 #define PAGE_MTE PAGE_TARGET_2 3425 3426 #ifdef TARGET_TAGGED_ADDRESSES 3427 /** 3428 * cpu_untagged_addr: 3429 * @cs: CPU context 3430 * @x: tagged address 3431 * 3432 * Remove any address tag from @x. This is explicitly related to the 3433 * linux syscall TIF_TAGGED_ADDR setting, not TBI in general. 3434 * 3435 * There should be a better place to put this, but we need this in 3436 * include/exec/cpu_ldst.h, and not some place linux-user specific. 3437 */ 3438 static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x) 3439 { 3440 ARMCPU *cpu = ARM_CPU(cs); 3441 if (cpu->env.tagged_addr_enable) { 3442 /* 3443 * TBI is enabled for userspace but not kernelspace addresses. 3444 * Only clear the tag if bit 55 is clear. 3445 */ 3446 x &= sextract64(x, 0, 56); 3447 } 3448 return x; 3449 } 3450 #endif 3451 3452 /* 3453 * Naming convention for isar_feature functions: 3454 * Functions which test 32-bit ID registers should have _aa32_ in 3455 * their name. Functions which test 64-bit ID registers should have 3456 * _aa64_ in their name. These must only be used in code where we 3457 * know for certain that the CPU has AArch32 or AArch64 respectively 3458 * or where the correct answer for a CPU which doesn't implement that 3459 * CPU state is "false" (eg when generating A32 or A64 code, if adding 3460 * system registers that are specific to that CPU state, for "should 3461 * we let this system register bit be set" tests where the 32-bit 3462 * flavour of the register doesn't have the bit, and so on). 3463 * Functions which simply ask "does this feature exist at all" have 3464 * _any_ in their name, and always return the logical OR of the _aa64_ 3465 * and the _aa32_ function. 3466 */ 3467 3468 /* 3469 * 32-bit feature tests via id registers. 3470 */ 3471 static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id) 3472 { 3473 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; 3474 } 3475 3476 static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id) 3477 { 3478 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; 3479 } 3480 3481 static inline bool isar_feature_aa32_lob(const ARMISARegisters *id) 3482 { 3483 /* (M-profile) low-overhead loops and branch future */ 3484 return FIELD_EX32(id->id_isar0, ID_ISAR0, CMPBRANCH) >= 3; 3485 } 3486 3487 static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id) 3488 { 3489 return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0; 3490 } 3491 3492 static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) 3493 { 3494 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0; 3495 } 3496 3497 static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id) 3498 { 3499 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1; 3500 } 3501 3502 static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id) 3503 { 3504 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0; 3505 } 3506 3507 static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id) 3508 { 3509 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0; 3510 } 3511 3512 static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id) 3513 { 3514 return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0; 3515 } 3516 3517 static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id) 3518 { 3519 return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0; 3520 } 3521 3522 static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id) 3523 { 3524 return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0; 3525 } 3526 3527 static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id) 3528 { 3529 return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0; 3530 } 3531 3532 static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) 3533 { 3534 return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0; 3535 } 3536 3537 static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id) 3538 { 3539 return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0; 3540 } 3541 3542 static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) 3543 { 3544 return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0; 3545 } 3546 3547 static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id) 3548 { 3549 return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0; 3550 } 3551 3552 static inline bool isar_feature_aa32_bf16(const ARMISARegisters *id) 3553 { 3554 return FIELD_EX32(id->id_isar6, ID_ISAR6, BF16) != 0; 3555 } 3556 3557 static inline bool isar_feature_aa32_i8mm(const ARMISARegisters *id) 3558 { 3559 return FIELD_EX32(id->id_isar6, ID_ISAR6, I8MM) != 0; 3560 } 3561 3562 static inline bool isar_feature_aa32_ras(const ARMISARegisters *id) 3563 { 3564 return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) != 0; 3565 } 3566 3567 static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id) 3568 { 3569 return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0; 3570 } 3571 3572 static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id) 3573 { 3574 /* 3575 * Return true if M-profile state handling insns 3576 * (VSCCLRM, CLRM, FPCTX access insns) are implemented 3577 */ 3578 return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >= 3; 3579 } 3580 3581 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) 3582 { 3583 /* Sadly this is encoded differently for A-profile and M-profile */ 3584 if (isar_feature_aa32_mprofile(id)) { 3585 return FIELD_EX32(id->mvfr1, MVFR1, FP16) > 0; 3586 } else { 3587 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3; 3588 } 3589 } 3590 3591 static inline bool isar_feature_aa32_mve(const ARMISARegisters *id) 3592 { 3593 /* 3594 * Return true if MVE is supported (either integer or floating point). 3595 * We must check for M-profile as the MVFR1 field means something 3596 * else for A-profile. 3597 */ 3598 return isar_feature_aa32_mprofile(id) && 3599 FIELD_EX32(id->mvfr1, MVFR1, MVE) > 0; 3600 } 3601 3602 static inline bool isar_feature_aa32_mve_fp(const ARMISARegisters *id) 3603 { 3604 /* 3605 * Return true if MVE is supported (either integer or floating point). 3606 * We must check for M-profile as the MVFR1 field means something 3607 * else for A-profile. 3608 */ 3609 return isar_feature_aa32_mprofile(id) && 3610 FIELD_EX32(id->mvfr1, MVFR1, MVE) >= 2; 3611 } 3612 3613 static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id) 3614 { 3615 /* 3616 * Return true if either VFP or SIMD is implemented. 3617 * In this case, a minimum of VFP w/ D0-D15. 3618 */ 3619 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0; 3620 } 3621 3622 static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id) 3623 { 3624 /* Return true if D16-D31 are implemented */ 3625 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2; 3626 } 3627 3628 static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id) 3629 { 3630 return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0; 3631 } 3632 3633 static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id) 3634 { 3635 /* Return true if CPU supports single precision floating point, VFPv2 */ 3636 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0; 3637 } 3638 3639 static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id) 3640 { 3641 /* Return true if CPU supports single precision floating point, VFPv3 */ 3642 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2; 3643 } 3644 3645 static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id) 3646 { 3647 /* Return true if CPU supports double precision floating point, VFPv2 */ 3648 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0; 3649 } 3650 3651 static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id) 3652 { 3653 /* Return true if CPU supports double precision floating point, VFPv3 */ 3654 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2; 3655 } 3656 3657 static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id) 3658 { 3659 return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id); 3660 } 3661 3662 /* 3663 * We always set the FP and SIMD FP16 fields to indicate identical 3664 * levels of support (assuming SIMD is implemented at all), so 3665 * we only need one set of accessors. 3666 */ 3667 static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id) 3668 { 3669 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0; 3670 } 3671 3672 static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id) 3673 { 3674 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1; 3675 } 3676 3677 /* 3678 * Note that this ID register field covers both VFP and Neon FMAC, 3679 * so should usually be tested in combination with some other 3680 * check that confirms the presence of whichever of VFP or Neon is 3681 * relevant, to avoid accidentally enabling a Neon feature on 3682 * a VFP-no-Neon core or vice-versa. 3683 */ 3684 static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id) 3685 { 3686 return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0; 3687 } 3688 3689 static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id) 3690 { 3691 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1; 3692 } 3693 3694 static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id) 3695 { 3696 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2; 3697 } 3698 3699 static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id) 3700 { 3701 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3; 3702 } 3703 3704 static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id) 3705 { 3706 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4; 3707 } 3708 3709 static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id) 3710 { 3711 return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >= 4; 3712 } 3713 3714 static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) 3715 { 3716 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0; 3717 } 3718 3719 static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id) 3720 { 3721 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2; 3722 } 3723 3724 static inline bool isar_feature_aa32_pmu_8_1(const ARMISARegisters *id) 3725 { 3726 /* 0xf means "non-standard IMPDEF PMU" */ 3727 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 && 3728 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3729 } 3730 3731 static inline bool isar_feature_aa32_pmu_8_4(const ARMISARegisters *id) 3732 { 3733 /* 0xf means "non-standard IMPDEF PMU" */ 3734 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 5 && 3735 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3736 } 3737 3738 static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id) 3739 { 3740 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0; 3741 } 3742 3743 static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id) 3744 { 3745 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0; 3746 } 3747 3748 static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id) 3749 { 3750 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0; 3751 } 3752 3753 static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id) 3754 { 3755 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0; 3756 } 3757 3758 static inline bool isar_feature_aa32_dit(const ARMISARegisters *id) 3759 { 3760 return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0; 3761 } 3762 3763 static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id) 3764 { 3765 return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0; 3766 } 3767 3768 static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id) 3769 { 3770 return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 8; 3771 } 3772 3773 /* 3774 * 64-bit feature tests via id registers. 3775 */ 3776 static inline bool isar_feature_aa64_aes(const ARMISARegisters *id) 3777 { 3778 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0; 3779 } 3780 3781 static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id) 3782 { 3783 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1; 3784 } 3785 3786 static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id) 3787 { 3788 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0; 3789 } 3790 3791 static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id) 3792 { 3793 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0; 3794 } 3795 3796 static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id) 3797 { 3798 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1; 3799 } 3800 3801 static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id) 3802 { 3803 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0; 3804 } 3805 3806 static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id) 3807 { 3808 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0; 3809 } 3810 3811 static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) 3812 { 3813 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0; 3814 } 3815 3816 static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id) 3817 { 3818 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0; 3819 } 3820 3821 static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id) 3822 { 3823 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0; 3824 } 3825 3826 static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id) 3827 { 3828 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0; 3829 } 3830 3831 static inline bool isar_feature_aa64_dp(const ARMISARegisters *id) 3832 { 3833 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0; 3834 } 3835 3836 static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id) 3837 { 3838 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0; 3839 } 3840 3841 static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id) 3842 { 3843 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0; 3844 } 3845 3846 static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id) 3847 { 3848 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2; 3849 } 3850 3851 static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id) 3852 { 3853 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0; 3854 } 3855 3856 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) 3857 { 3858 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0; 3859 } 3860 3861 static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) 3862 { 3863 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0; 3864 } 3865 3866 static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) 3867 { 3868 /* 3869 * Return true if any form of pauth is enabled, as this 3870 * predicate controls migration of the 128-bit keys. 3871 */ 3872 return (id->id_aa64isar1 & 3873 (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) | 3874 FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) | 3875 FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) | 3876 FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0; 3877 } 3878 3879 static inline bool isar_feature_aa64_pauth_arch(const ARMISARegisters *id) 3880 { 3881 /* 3882 * Return true if pauth is enabled with the architected QARMA algorithm. 3883 * QEMU will always set APA+GPA to the same value. 3884 */ 3885 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0; 3886 } 3887 3888 static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id) 3889 { 3890 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2; 3891 } 3892 3893 static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id) 3894 { 3895 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) != 0; 3896 } 3897 3898 static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) 3899 { 3900 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0; 3901 } 3902 3903 static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id) 3904 { 3905 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0; 3906 } 3907 3908 static inline bool isar_feature_aa64_frint(const ARMISARegisters *id) 3909 { 3910 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0; 3911 } 3912 3913 static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id) 3914 { 3915 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) != 0; 3916 } 3917 3918 static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id) 3919 { 3920 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2; 3921 } 3922 3923 static inline bool isar_feature_aa64_bf16(const ARMISARegisters *id) 3924 { 3925 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) != 0; 3926 } 3927 3928 static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id) 3929 { 3930 /* We always set the AdvSIMD and FP fields identically. */ 3931 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf; 3932 } 3933 3934 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) 3935 { 3936 /* We always set the AdvSIMD and FP fields identically wrt FP16. */ 3937 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 3938 } 3939 3940 static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id) 3941 { 3942 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2; 3943 } 3944 3945 static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id) 3946 { 3947 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2; 3948 } 3949 3950 static inline bool isar_feature_aa64_ras(const ARMISARegisters *id) 3951 { 3952 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) != 0; 3953 } 3954 3955 static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) 3956 { 3957 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; 3958 } 3959 3960 static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id) 3961 { 3962 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) != 0; 3963 } 3964 3965 static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) 3966 { 3967 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0; 3968 } 3969 3970 static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) 3971 { 3972 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; 3973 } 3974 3975 static inline bool isar_feature_aa64_pan(const ARMISARegisters *id) 3976 { 3977 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0; 3978 } 3979 3980 static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id) 3981 { 3982 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2; 3983 } 3984 3985 static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id) 3986 { 3987 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HCX) != 0; 3988 } 3989 3990 static inline bool isar_feature_aa64_uao(const ARMISARegisters *id) 3991 { 3992 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0; 3993 } 3994 3995 static inline bool isar_feature_aa64_st(const ARMISARegisters *id) 3996 { 3997 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0; 3998 } 3999 4000 static inline bool isar_feature_aa64_fwb(const ARMISARegisters *id) 4001 { 4002 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, FWB) != 0; 4003 } 4004 4005 static inline bool isar_feature_aa64_ids(const ARMISARegisters *id) 4006 { 4007 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, IDS) != 0; 4008 } 4009 4010 static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) 4011 { 4012 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; 4013 } 4014 4015 static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id) 4016 { 4017 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0; 4018 } 4019 4020 static inline bool isar_feature_aa64_mte(const ARMISARegisters *id) 4021 { 4022 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2; 4023 } 4024 4025 static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id) 4026 { 4027 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 && 4028 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 4029 } 4030 4031 static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id) 4032 { 4033 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 && 4034 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 4035 } 4036 4037 static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id) 4038 { 4039 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0; 4040 } 4041 4042 static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id) 4043 { 4044 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2; 4045 } 4046 4047 static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id) 4048 { 4049 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0; 4050 } 4051 4052 static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id) 4053 { 4054 return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1; 4055 } 4056 4057 static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *id) 4058 { 4059 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2); 4060 return t >= 3 || (t == 0 && isar_feature_aa64_tgran4_lpa2(id)); 4061 } 4062 4063 static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *id) 4064 { 4065 return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 2; 4066 } 4067 4068 static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id) 4069 { 4070 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2); 4071 return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id)); 4072 } 4073 4074 static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) 4075 { 4076 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0; 4077 } 4078 4079 static inline bool isar_feature_aa64_lva(const ARMISARegisters *id) 4080 { 4081 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) != 0; 4082 } 4083 4084 static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id) 4085 { 4086 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0; 4087 } 4088 4089 static inline bool isar_feature_aa64_dit(const ARMISARegisters *id) 4090 { 4091 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0; 4092 } 4093 4094 static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id) 4095 { 4096 int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2); 4097 if (key >= 2) { 4098 return true; /* FEAT_CSV2_2 */ 4099 } 4100 if (key == 1) { 4101 key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC); 4102 return key >= 2; /* FEAT_CSV2_1p2 */ 4103 } 4104 return false; 4105 } 4106 4107 static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id) 4108 { 4109 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0; 4110 } 4111 4112 static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id) 4113 { 4114 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >= 8; 4115 } 4116 4117 static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id) 4118 { 4119 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0; 4120 } 4121 4122 static inline bool isar_feature_aa64_sve2_aes(const ARMISARegisters *id) 4123 { 4124 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) != 0; 4125 } 4126 4127 static inline bool isar_feature_aa64_sve2_pmull128(const ARMISARegisters *id) 4128 { 4129 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) >= 2; 4130 } 4131 4132 static inline bool isar_feature_aa64_sve2_bitperm(const ARMISARegisters *id) 4133 { 4134 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BITPERM) != 0; 4135 } 4136 4137 static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id) 4138 { 4139 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BFLOAT16) != 0; 4140 } 4141 4142 static inline bool isar_feature_aa64_sve2_sha3(const ARMISARegisters *id) 4143 { 4144 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SHA3) != 0; 4145 } 4146 4147 static inline bool isar_feature_aa64_sve2_sm4(const ARMISARegisters *id) 4148 { 4149 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SM4) != 0; 4150 } 4151 4152 static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id) 4153 { 4154 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, I8MM) != 0; 4155 } 4156 4157 static inline bool isar_feature_aa64_sve_f32mm(const ARMISARegisters *id) 4158 { 4159 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F32MM) != 0; 4160 } 4161 4162 static inline bool isar_feature_aa64_sve_f64mm(const ARMISARegisters *id) 4163 { 4164 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F64MM) != 0; 4165 } 4166 4167 /* 4168 * Feature tests for "does this exist in either 32-bit or 64-bit?" 4169 */ 4170 static inline bool isar_feature_any_fp16(const ARMISARegisters *id) 4171 { 4172 return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id); 4173 } 4174 4175 static inline bool isar_feature_any_predinv(const ARMISARegisters *id) 4176 { 4177 return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id); 4178 } 4179 4180 static inline bool isar_feature_any_pmu_8_1(const ARMISARegisters *id) 4181 { 4182 return isar_feature_aa64_pmu_8_1(id) || isar_feature_aa32_pmu_8_1(id); 4183 } 4184 4185 static inline bool isar_feature_any_pmu_8_4(const ARMISARegisters *id) 4186 { 4187 return isar_feature_aa64_pmu_8_4(id) || isar_feature_aa32_pmu_8_4(id); 4188 } 4189 4190 static inline bool isar_feature_any_ccidx(const ARMISARegisters *id) 4191 { 4192 return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id); 4193 } 4194 4195 static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id) 4196 { 4197 return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id); 4198 } 4199 4200 static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id) 4201 { 4202 return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(id); 4203 } 4204 4205 static inline bool isar_feature_any_ras(const ARMISARegisters *id) 4206 { 4207 return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id); 4208 } 4209 4210 /* 4211 * Forward to the above feature tests given an ARMCPU pointer. 4212 */ 4213 #define cpu_isar_feature(name, cpu) \ 4214 ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); }) 4215 4216 #endif 4217