1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 25 #if defined(TARGET_AARCH64) 26 /* AArch64 definitions */ 27 # define TARGET_LONG_BITS 64 28 #else 29 # define TARGET_LONG_BITS 32 30 #endif 31 32 #define CPUArchState struct CPUARMState 33 34 #include "qemu-common.h" 35 #include "cpu-qom.h" 36 #include "exec/cpu-defs.h" 37 38 #include "fpu/softfloat.h" 39 40 #define EXCP_UDEF 1 /* undefined instruction */ 41 #define EXCP_SWI 2 /* software interrupt */ 42 #define EXCP_PREFETCH_ABORT 3 43 #define EXCP_DATA_ABORT 4 44 #define EXCP_IRQ 5 45 #define EXCP_FIQ 6 46 #define EXCP_BKPT 7 47 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 48 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 49 #define EXCP_HVC 11 /* HyperVisor Call */ 50 #define EXCP_HYP_TRAP 12 51 #define EXCP_SMC 13 /* Secure Monitor Call */ 52 #define EXCP_VIRQ 14 53 #define EXCP_VFIQ 15 54 #define EXCP_SEMIHOST 16 /* semihosting call */ 55 56 #define ARMV7M_EXCP_RESET 1 57 #define ARMV7M_EXCP_NMI 2 58 #define ARMV7M_EXCP_HARD 3 59 #define ARMV7M_EXCP_MEM 4 60 #define ARMV7M_EXCP_BUS 5 61 #define ARMV7M_EXCP_USAGE 6 62 #define ARMV7M_EXCP_SVC 11 63 #define ARMV7M_EXCP_DEBUG 12 64 #define ARMV7M_EXCP_PENDSV 14 65 #define ARMV7M_EXCP_SYSTICK 15 66 67 /* ARM-specific interrupt pending bits. */ 68 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 69 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 70 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 71 72 /* The usual mapping for an AArch64 system register to its AArch32 73 * counterpart is for the 32 bit world to have access to the lower 74 * half only (with writes leaving the upper half untouched). It's 75 * therefore useful to be able to pass TCG the offset of the least 76 * significant half of a uint64_t struct member. 77 */ 78 #ifdef HOST_WORDS_BIGENDIAN 79 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 80 #define offsetofhigh32(S, M) offsetof(S, M) 81 #else 82 #define offsetoflow32(S, M) offsetof(S, M) 83 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 84 #endif 85 86 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 87 #define ARM_CPU_IRQ 0 88 #define ARM_CPU_FIQ 1 89 #define ARM_CPU_VIRQ 2 90 #define ARM_CPU_VFIQ 3 91 92 #define NB_MMU_MODES 7 93 /* ARM-specific extra insn start words: 94 * 1: Conditional execution bits 95 * 2: Partial exception syndrome for data aborts 96 */ 97 #define TARGET_INSN_START_EXTRA_WORDS 2 98 99 /* The 2nd extra word holding syndrome info for data aborts does not use 100 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 101 * help the sleb128 encoder do a better job. 102 * When restoring the CPU state, we shift it back up. 103 */ 104 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 105 #define ARM_INSN_START_WORD2_SHIFT 14 106 107 /* We currently assume float and double are IEEE single and double 108 precision respectively. 109 Doing runtime conversions is tricky because VFP registers may contain 110 integer values (eg. as the result of a FTOSI instruction). 111 s<2n> maps to the least significant half of d<n> 112 s<2n+1> maps to the most significant half of d<n> 113 */ 114 115 /* CPU state for each instance of a generic timer (in cp15 c14) */ 116 typedef struct ARMGenericTimer { 117 uint64_t cval; /* Timer CompareValue register */ 118 uint64_t ctl; /* Timer Control register */ 119 } ARMGenericTimer; 120 121 #define GTIMER_PHYS 0 122 #define GTIMER_VIRT 1 123 #define GTIMER_HYP 2 124 #define GTIMER_SEC 3 125 #define NUM_GTIMERS 4 126 127 typedef struct { 128 uint64_t raw_tcr; 129 uint32_t mask; 130 uint32_t base_mask; 131 } TCR; 132 133 typedef struct CPUARMState { 134 /* Regs for current mode. */ 135 uint32_t regs[16]; 136 137 /* 32/64 switch only happens when taking and returning from 138 * exceptions so the overlap semantics are taken care of then 139 * instead of having a complicated union. 140 */ 141 /* Regs for A64 mode. */ 142 uint64_t xregs[32]; 143 uint64_t pc; 144 /* PSTATE isn't an architectural register for ARMv8. However, it is 145 * convenient for us to assemble the underlying state into a 32 bit format 146 * identical to the architectural format used for the SPSR. (This is also 147 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 148 * 'pstate' register are.) Of the PSTATE bits: 149 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 150 * semantics as for AArch32, as described in the comments on each field) 151 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 152 * DAIF (exception masks) are kept in env->daif 153 * all other bits are stored in their correct places in env->pstate 154 */ 155 uint32_t pstate; 156 uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ 157 158 /* Frequently accessed CPSR bits are stored separately for efficiency. 159 This contains all the other bits. Use cpsr_{read,write} to access 160 the whole CPSR. */ 161 uint32_t uncached_cpsr; 162 uint32_t spsr; 163 164 /* Banked registers. */ 165 uint64_t banked_spsr[8]; 166 uint32_t banked_r13[8]; 167 uint32_t banked_r14[8]; 168 169 /* These hold r8-r12. */ 170 uint32_t usr_regs[5]; 171 uint32_t fiq_regs[5]; 172 173 /* cpsr flag cache for faster execution */ 174 uint32_t CF; /* 0 or 1 */ 175 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 176 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 177 uint32_t ZF; /* Z set if zero. */ 178 uint32_t QF; /* 0 or 1 */ 179 uint32_t GE; /* cpsr[19:16] */ 180 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ 181 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 182 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 183 184 uint64_t elr_el[4]; /* AArch64 exception link regs */ 185 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 186 187 /* System control coprocessor (cp15) */ 188 struct { 189 uint32_t c0_cpuid; 190 union { /* Cache size selection */ 191 struct { 192 uint64_t _unused_csselr0; 193 uint64_t csselr_ns; 194 uint64_t _unused_csselr1; 195 uint64_t csselr_s; 196 }; 197 uint64_t csselr_el[4]; 198 }; 199 union { /* System control register. */ 200 struct { 201 uint64_t _unused_sctlr; 202 uint64_t sctlr_ns; 203 uint64_t hsctlr; 204 uint64_t sctlr_s; 205 }; 206 uint64_t sctlr_el[4]; 207 }; 208 uint64_t cpacr_el1; /* Architectural feature access control register */ 209 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 210 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 211 uint64_t sder; /* Secure debug enable register. */ 212 uint32_t nsacr; /* Non-secure access control register. */ 213 union { /* MMU translation table base 0. */ 214 struct { 215 uint64_t _unused_ttbr0_0; 216 uint64_t ttbr0_ns; 217 uint64_t _unused_ttbr0_1; 218 uint64_t ttbr0_s; 219 }; 220 uint64_t ttbr0_el[4]; 221 }; 222 union { /* MMU translation table base 1. */ 223 struct { 224 uint64_t _unused_ttbr1_0; 225 uint64_t ttbr1_ns; 226 uint64_t _unused_ttbr1_1; 227 uint64_t ttbr1_s; 228 }; 229 uint64_t ttbr1_el[4]; 230 }; 231 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 232 /* MMU translation table base control. */ 233 TCR tcr_el[4]; 234 TCR vtcr_el2; /* Virtualization Translation Control. */ 235 uint32_t c2_data; /* MPU data cacheable bits. */ 236 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 237 union { /* MMU domain access control register 238 * MPU write buffer control. 239 */ 240 struct { 241 uint64_t dacr_ns; 242 uint64_t dacr_s; 243 }; 244 struct { 245 uint64_t dacr32_el2; 246 }; 247 }; 248 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 249 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 250 uint64_t hcr_el2; /* Hypervisor configuration register */ 251 uint64_t scr_el3; /* Secure configuration register. */ 252 union { /* Fault status registers. */ 253 struct { 254 uint64_t ifsr_ns; 255 uint64_t ifsr_s; 256 }; 257 struct { 258 uint64_t ifsr32_el2; 259 }; 260 }; 261 union { 262 struct { 263 uint64_t _unused_dfsr; 264 uint64_t dfsr_ns; 265 uint64_t hsr; 266 uint64_t dfsr_s; 267 }; 268 uint64_t esr_el[4]; 269 }; 270 uint32_t c6_region[8]; /* MPU base/size registers. */ 271 union { /* Fault address registers. */ 272 struct { 273 uint64_t _unused_far0; 274 #ifdef HOST_WORDS_BIGENDIAN 275 uint32_t ifar_ns; 276 uint32_t dfar_ns; 277 uint32_t ifar_s; 278 uint32_t dfar_s; 279 #else 280 uint32_t dfar_ns; 281 uint32_t ifar_ns; 282 uint32_t dfar_s; 283 uint32_t ifar_s; 284 #endif 285 uint64_t _unused_far3; 286 }; 287 uint64_t far_el[4]; 288 }; 289 uint64_t hpfar_el2; 290 uint64_t hstr_el2; 291 union { /* Translation result. */ 292 struct { 293 uint64_t _unused_par_0; 294 uint64_t par_ns; 295 uint64_t _unused_par_1; 296 uint64_t par_s; 297 }; 298 uint64_t par_el[4]; 299 }; 300 301 uint32_t c6_rgnr; 302 303 uint32_t c9_insn; /* Cache lockdown registers. */ 304 uint32_t c9_data; 305 uint64_t c9_pmcr; /* performance monitor control register */ 306 uint64_t c9_pmcnten; /* perf monitor counter enables */ 307 uint32_t c9_pmovsr; /* perf monitor overflow status */ 308 uint32_t c9_pmxevtyper; /* perf monitor event type */ 309 uint32_t c9_pmuserenr; /* perf monitor user enable */ 310 uint32_t c9_pminten; /* perf monitor interrupt enables */ 311 union { /* Memory attribute redirection */ 312 struct { 313 #ifdef HOST_WORDS_BIGENDIAN 314 uint64_t _unused_mair_0; 315 uint32_t mair1_ns; 316 uint32_t mair0_ns; 317 uint64_t _unused_mair_1; 318 uint32_t mair1_s; 319 uint32_t mair0_s; 320 #else 321 uint64_t _unused_mair_0; 322 uint32_t mair0_ns; 323 uint32_t mair1_ns; 324 uint64_t _unused_mair_1; 325 uint32_t mair0_s; 326 uint32_t mair1_s; 327 #endif 328 }; 329 uint64_t mair_el[4]; 330 }; 331 union { /* vector base address register */ 332 struct { 333 uint64_t _unused_vbar; 334 uint64_t vbar_ns; 335 uint64_t hvbar; 336 uint64_t vbar_s; 337 }; 338 uint64_t vbar_el[4]; 339 }; 340 uint32_t mvbar; /* (monitor) vector base address register */ 341 struct { /* FCSE PID. */ 342 uint32_t fcseidr_ns; 343 uint32_t fcseidr_s; 344 }; 345 union { /* Context ID. */ 346 struct { 347 uint64_t _unused_contextidr_0; 348 uint64_t contextidr_ns; 349 uint64_t _unused_contextidr_1; 350 uint64_t contextidr_s; 351 }; 352 uint64_t contextidr_el[4]; 353 }; 354 union { /* User RW Thread register. */ 355 struct { 356 uint64_t tpidrurw_ns; 357 uint64_t tpidrprw_ns; 358 uint64_t htpidr; 359 uint64_t _tpidr_el3; 360 }; 361 uint64_t tpidr_el[4]; 362 }; 363 /* The secure banks of these registers don't map anywhere */ 364 uint64_t tpidrurw_s; 365 uint64_t tpidrprw_s; 366 uint64_t tpidruro_s; 367 368 union { /* User RO Thread register. */ 369 uint64_t tpidruro_ns; 370 uint64_t tpidrro_el[1]; 371 }; 372 uint64_t c14_cntfrq; /* Counter Frequency register */ 373 uint64_t c14_cntkctl; /* Timer Control register */ 374 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 375 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 376 ARMGenericTimer c14_timer[NUM_GTIMERS]; 377 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 378 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 379 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 380 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 381 uint32_t c15_threadid; /* TI debugger thread-ID. */ 382 uint32_t c15_config_base_address; /* SCU base address. */ 383 uint32_t c15_diagnostic; /* diagnostic register */ 384 uint32_t c15_power_diagnostic; 385 uint32_t c15_power_control; /* power control */ 386 uint64_t dbgbvr[16]; /* breakpoint value registers */ 387 uint64_t dbgbcr[16]; /* breakpoint control registers */ 388 uint64_t dbgwvr[16]; /* watchpoint value registers */ 389 uint64_t dbgwcr[16]; /* watchpoint control registers */ 390 uint64_t mdscr_el1; 391 uint64_t oslsr_el1; /* OS Lock Status */ 392 uint64_t mdcr_el2; 393 uint64_t mdcr_el3; 394 /* If the counter is enabled, this stores the last time the counter 395 * was reset. Otherwise it stores the counter value 396 */ 397 uint64_t c15_ccnt; 398 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 399 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 400 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 401 } cp15; 402 403 struct { 404 uint32_t other_sp; 405 uint32_t vecbase; 406 uint32_t basepri; 407 uint32_t control; 408 int current_sp; 409 int exception; 410 } v7m; 411 412 /* Information associated with an exception about to be taken: 413 * code which raises an exception must set cs->exception_index and 414 * the relevant parts of this structure; the cpu_do_interrupt function 415 * will then set the guest-visible registers as part of the exception 416 * entry process. 417 */ 418 struct { 419 uint32_t syndrome; /* AArch64 format syndrome register */ 420 uint32_t fsr; /* AArch32 format fault status register info */ 421 uint64_t vaddress; /* virtual addr associated with exception, if any */ 422 uint32_t target_el; /* EL the exception should be targeted for */ 423 /* If we implement EL2 we will also need to store information 424 * about the intermediate physical address for stage 2 faults. 425 */ 426 } exception; 427 428 /* Thumb-2 EE state. */ 429 uint32_t teecr; 430 uint32_t teehbr; 431 432 /* VFP coprocessor state. */ 433 struct { 434 /* VFP/Neon register state. Note that the mapping between S, D and Q 435 * views of the register bank differs between AArch64 and AArch32: 436 * In AArch32: 437 * Qn = regs[2n+1]:regs[2n] 438 * Dn = regs[n] 439 * Sn = regs[n/2] bits 31..0 for even n, and bits 63..32 for odd n 440 * (and regs[32] to regs[63] are inaccessible) 441 * In AArch64: 442 * Qn = regs[2n+1]:regs[2n] 443 * Dn = regs[2n] 444 * Sn = regs[2n] bits 31..0 445 * This corresponds to the architecturally defined mapping between 446 * the two execution states, and means we do not need to explicitly 447 * map these registers when changing states. 448 */ 449 float64 regs[64]; 450 451 uint32_t xregs[16]; 452 /* We store these fpcsr fields separately for convenience. */ 453 int vec_len; 454 int vec_stride; 455 456 /* scratch space when Tn are not sufficient. */ 457 uint32_t scratch[8]; 458 459 /* fp_status is the "normal" fp status. standard_fp_status retains 460 * values corresponding to the ARM "Standard FPSCR Value", ie 461 * default-NaN, flush-to-zero, round-to-nearest and is used by 462 * any operations (generally Neon) which the architecture defines 463 * as controlled by the standard FPSCR value rather than the FPSCR. 464 * 465 * To avoid having to transfer exception bits around, we simply 466 * say that the FPSCR cumulative exception flags are the logical 467 * OR of the flags in the two fp statuses. This relies on the 468 * only thing which needs to read the exception flags being 469 * an explicit FPSCR read. 470 */ 471 float_status fp_status; 472 float_status standard_fp_status; 473 } vfp; 474 uint64_t exclusive_addr; 475 uint64_t exclusive_val; 476 uint64_t exclusive_high; 477 478 /* iwMMXt coprocessor state. */ 479 struct { 480 uint64_t regs[16]; 481 uint64_t val; 482 483 uint32_t cregs[16]; 484 } iwmmxt; 485 486 #if defined(CONFIG_USER_ONLY) 487 /* For usermode syscall translation. */ 488 int eabi; 489 #endif 490 491 struct CPUBreakpoint *cpu_breakpoint[16]; 492 struct CPUWatchpoint *cpu_watchpoint[16]; 493 494 CPU_COMMON 495 496 /* These fields after the common ones so they are preserved on reset. */ 497 498 /* Internal CPU feature flags. */ 499 uint64_t features; 500 501 /* PMSAv7 MPU */ 502 struct { 503 uint32_t *drbar; 504 uint32_t *drsr; 505 uint32_t *dracr; 506 } pmsav7; 507 508 void *nvic; 509 const struct arm_boot_info *boot_info; 510 } CPUARMState; 511 512 /** 513 * ARMELChangeHook: 514 * type of a function which can be registered via arm_register_el_change_hook() 515 * to get callbacks when the CPU changes its exception level or mode. 516 */ 517 typedef void ARMELChangeHook(ARMCPU *cpu, void *opaque); 518 519 /** 520 * ARMCPU: 521 * @env: #CPUARMState 522 * 523 * An ARM CPU core. 524 */ 525 struct ARMCPU { 526 /*< private >*/ 527 CPUState parent_obj; 528 /*< public >*/ 529 530 CPUARMState env; 531 532 /* Coprocessor information */ 533 GHashTable *cp_regs; 534 /* For marshalling (mostly coprocessor) register state between the 535 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 536 * we use these arrays. 537 */ 538 /* List of register indexes managed via these arrays; (full KVM style 539 * 64 bit indexes, not CPRegInfo 32 bit indexes) 540 */ 541 uint64_t *cpreg_indexes; 542 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 543 uint64_t *cpreg_values; 544 /* Length of the indexes, values, reset_values arrays */ 545 int32_t cpreg_array_len; 546 /* These are used only for migration: incoming data arrives in 547 * these fields and is sanity checked in post_load before copying 548 * to the working data structures above. 549 */ 550 uint64_t *cpreg_vmstate_indexes; 551 uint64_t *cpreg_vmstate_values; 552 int32_t cpreg_vmstate_array_len; 553 554 /* Timers used by the generic (architected) timer */ 555 QEMUTimer *gt_timer[NUM_GTIMERS]; 556 /* GPIO outputs for generic timer */ 557 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 558 559 /* MemoryRegion to use for secure physical accesses */ 560 MemoryRegion *secure_memory; 561 562 /* 'compatible' string for this CPU for Linux device trees */ 563 const char *dtb_compatible; 564 565 /* PSCI version for this CPU 566 * Bits[31:16] = Major Version 567 * Bits[15:0] = Minor Version 568 */ 569 uint32_t psci_version; 570 571 /* Should CPU start in PSCI powered-off state? */ 572 bool start_powered_off; 573 /* CPU currently in PSCI powered-off state */ 574 bool powered_off; 575 /* CPU has security extension */ 576 bool has_el3; 577 /* CPU has PMU (Performance Monitor Unit) */ 578 bool has_pmu; 579 580 /* CPU has memory protection unit */ 581 bool has_mpu; 582 /* PMSAv7 MPU number of supported regions */ 583 uint32_t pmsav7_dregion; 584 585 /* PSCI conduit used to invoke PSCI methods 586 * 0 - disabled, 1 - smc, 2 - hvc 587 */ 588 uint32_t psci_conduit; 589 590 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 591 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 592 */ 593 uint32_t kvm_target; 594 595 /* KVM init features for this CPU */ 596 uint32_t kvm_init_features[7]; 597 598 /* Uniprocessor system with MP extensions */ 599 bool mp_is_up; 600 601 /* The instance init functions for implementation-specific subclasses 602 * set these fields to specify the implementation-dependent values of 603 * various constant registers and reset values of non-constant 604 * registers. 605 * Some of these might become QOM properties eventually. 606 * Field names match the official register names as defined in the 607 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 608 * is used for reset values of non-constant registers; no reset_ 609 * prefix means a constant register. 610 */ 611 uint32_t midr; 612 uint32_t revidr; 613 uint32_t reset_fpsid; 614 uint32_t mvfr0; 615 uint32_t mvfr1; 616 uint32_t mvfr2; 617 uint32_t ctr; 618 uint32_t reset_sctlr; 619 uint32_t id_pfr0; 620 uint32_t id_pfr1; 621 uint32_t id_dfr0; 622 uint32_t pmceid0; 623 uint32_t pmceid1; 624 uint32_t id_afr0; 625 uint32_t id_mmfr0; 626 uint32_t id_mmfr1; 627 uint32_t id_mmfr2; 628 uint32_t id_mmfr3; 629 uint32_t id_mmfr4; 630 uint32_t id_isar0; 631 uint32_t id_isar1; 632 uint32_t id_isar2; 633 uint32_t id_isar3; 634 uint32_t id_isar4; 635 uint32_t id_isar5; 636 uint64_t id_aa64pfr0; 637 uint64_t id_aa64pfr1; 638 uint64_t id_aa64dfr0; 639 uint64_t id_aa64dfr1; 640 uint64_t id_aa64afr0; 641 uint64_t id_aa64afr1; 642 uint64_t id_aa64isar0; 643 uint64_t id_aa64isar1; 644 uint64_t id_aa64mmfr0; 645 uint64_t id_aa64mmfr1; 646 uint32_t dbgdidr; 647 uint32_t clidr; 648 uint64_t mp_affinity; /* MP ID without feature bits */ 649 /* The elements of this array are the CCSIDR values for each cache, 650 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 651 */ 652 uint32_t ccsidr[16]; 653 uint64_t reset_cbar; 654 uint32_t reset_auxcr; 655 bool reset_hivecs; 656 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 657 uint32_t dcz_blocksize; 658 uint64_t rvbar; 659 660 ARMELChangeHook *el_change_hook; 661 void *el_change_hook_opaque; 662 }; 663 664 static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) 665 { 666 return container_of(env, ARMCPU, env); 667 } 668 669 #define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e)) 670 671 #define ENV_OFFSET offsetof(ARMCPU, env) 672 673 #ifndef CONFIG_USER_ONLY 674 extern const struct VMStateDescription vmstate_arm_cpu; 675 #endif 676 677 void arm_cpu_do_interrupt(CPUState *cpu); 678 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 679 bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req); 680 681 void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 682 int flags); 683 684 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 685 MemTxAttrs *attrs); 686 687 int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 688 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 689 690 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 691 int cpuid, void *opaque); 692 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 693 int cpuid, void *opaque); 694 695 #ifdef TARGET_AARCH64 696 int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 697 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 698 #endif 699 700 ARMCPU *cpu_arm_init(const char *cpu_model); 701 target_ulong do_arm_semihosting(CPUARMState *env); 702 void aarch64_sync_32_to_64(CPUARMState *env); 703 void aarch64_sync_64_to_32(CPUARMState *env); 704 705 static inline bool is_a64(CPUARMState *env) 706 { 707 return env->aarch64; 708 } 709 710 /* you can call this signal handler from your SIGBUS and SIGSEGV 711 signal handlers to inform the virtual CPU of exceptions. non zero 712 is returned if the signal was handled by the virtual CPU. */ 713 int cpu_arm_signal_handler(int host_signum, void *pinfo, 714 void *puc); 715 716 /** 717 * pmccntr_sync 718 * @env: CPUARMState 719 * 720 * Synchronises the counter in the PMCCNTR. This must always be called twice, 721 * once before any action that might affect the timer and again afterwards. 722 * The function is used to swap the state of the register if required. 723 * This only happens when not in user mode (!CONFIG_USER_ONLY) 724 */ 725 void pmccntr_sync(CPUARMState *env); 726 727 /* SCTLR bit meanings. Several bits have been reused in newer 728 * versions of the architecture; in that case we define constants 729 * for both old and new bit meanings. Code which tests against those 730 * bits should probably check or otherwise arrange that the CPU 731 * is the architectural version it expects. 732 */ 733 #define SCTLR_M (1U << 0) 734 #define SCTLR_A (1U << 1) 735 #define SCTLR_C (1U << 2) 736 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 737 #define SCTLR_SA (1U << 3) 738 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 739 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 740 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 741 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 742 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 743 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 744 #define SCTLR_ITD (1U << 7) /* v8 onward */ 745 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 746 #define SCTLR_SED (1U << 8) /* v8 onward */ 747 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 748 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 749 #define SCTLR_F (1U << 10) /* up to v6 */ 750 #define SCTLR_SW (1U << 10) /* v7 onward */ 751 #define SCTLR_Z (1U << 11) 752 #define SCTLR_I (1U << 12) 753 #define SCTLR_V (1U << 13) 754 #define SCTLR_RR (1U << 14) /* up to v7 */ 755 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 756 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 757 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 758 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 759 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 760 #define SCTLR_HA (1U << 17) 761 #define SCTLR_BR (1U << 17) /* PMSA only */ 762 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 763 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 764 #define SCTLR_WXN (1U << 19) 765 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 766 #define SCTLR_UWXN (1U << 20) /* v7 onward */ 767 #define SCTLR_FI (1U << 21) 768 #define SCTLR_U (1U << 22) 769 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 770 #define SCTLR_VE (1U << 24) /* up to v7 */ 771 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 772 #define SCTLR_EE (1U << 25) 773 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 774 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 775 #define SCTLR_NMFI (1U << 27) 776 #define SCTLR_TRE (1U << 28) 777 #define SCTLR_AFE (1U << 29) 778 #define SCTLR_TE (1U << 30) 779 780 #define CPTR_TCPAC (1U << 31) 781 #define CPTR_TTA (1U << 20) 782 #define CPTR_TFP (1U << 10) 783 784 #define MDCR_EPMAD (1U << 21) 785 #define MDCR_EDAD (1U << 20) 786 #define MDCR_SPME (1U << 17) 787 #define MDCR_SDD (1U << 16) 788 #define MDCR_SPD (3U << 14) 789 #define MDCR_TDRA (1U << 11) 790 #define MDCR_TDOSA (1U << 10) 791 #define MDCR_TDA (1U << 9) 792 #define MDCR_TDE (1U << 8) 793 #define MDCR_HPME (1U << 7) 794 #define MDCR_TPM (1U << 6) 795 #define MDCR_TPMCR (1U << 5) 796 797 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 798 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) 799 800 #define CPSR_M (0x1fU) 801 #define CPSR_T (1U << 5) 802 #define CPSR_F (1U << 6) 803 #define CPSR_I (1U << 7) 804 #define CPSR_A (1U << 8) 805 #define CPSR_E (1U << 9) 806 #define CPSR_IT_2_7 (0xfc00U) 807 #define CPSR_GE (0xfU << 16) 808 #define CPSR_IL (1U << 20) 809 /* Note that the RESERVED bits include bit 21, which is PSTATE_SS in 810 * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use 811 * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32, 812 * where it is live state but not accessible to the AArch32 code. 813 */ 814 #define CPSR_RESERVED (0x7U << 21) 815 #define CPSR_J (1U << 24) 816 #define CPSR_IT_0_1 (3U << 25) 817 #define CPSR_Q (1U << 27) 818 #define CPSR_V (1U << 28) 819 #define CPSR_C (1U << 29) 820 #define CPSR_Z (1U << 30) 821 #define CPSR_N (1U << 31) 822 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 823 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 824 825 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 826 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 827 | CPSR_NZCV) 828 /* Bits writable in user mode. */ 829 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) 830 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 831 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 832 /* Mask of bits which may be set by exception return copying them from SPSR */ 833 #define CPSR_ERET_MASK (~CPSR_RESERVED) 834 835 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 836 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 837 #define TTBCR_PD0 (1U << 4) 838 #define TTBCR_PD1 (1U << 5) 839 #define TTBCR_EPD0 (1U << 7) 840 #define TTBCR_IRGN0 (3U << 8) 841 #define TTBCR_ORGN0 (3U << 10) 842 #define TTBCR_SH0 (3U << 12) 843 #define TTBCR_T1SZ (3U << 16) 844 #define TTBCR_A1 (1U << 22) 845 #define TTBCR_EPD1 (1U << 23) 846 #define TTBCR_IRGN1 (3U << 24) 847 #define TTBCR_ORGN1 (3U << 26) 848 #define TTBCR_SH1 (1U << 28) 849 #define TTBCR_EAE (1U << 31) 850 851 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 852 * Only these are valid when in AArch64 mode; in 853 * AArch32 mode SPSRs are basically CPSR-format. 854 */ 855 #define PSTATE_SP (1U) 856 #define PSTATE_M (0xFU) 857 #define PSTATE_nRW (1U << 4) 858 #define PSTATE_F (1U << 6) 859 #define PSTATE_I (1U << 7) 860 #define PSTATE_A (1U << 8) 861 #define PSTATE_D (1U << 9) 862 #define PSTATE_IL (1U << 20) 863 #define PSTATE_SS (1U << 21) 864 #define PSTATE_V (1U << 28) 865 #define PSTATE_C (1U << 29) 866 #define PSTATE_Z (1U << 30) 867 #define PSTATE_N (1U << 31) 868 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 869 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 870 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF) 871 /* Mode values for AArch64 */ 872 #define PSTATE_MODE_EL3h 13 873 #define PSTATE_MODE_EL3t 12 874 #define PSTATE_MODE_EL2h 9 875 #define PSTATE_MODE_EL2t 8 876 #define PSTATE_MODE_EL1h 5 877 #define PSTATE_MODE_EL1t 4 878 #define PSTATE_MODE_EL0t 0 879 880 /* Map EL and handler into a PSTATE_MODE. */ 881 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 882 { 883 return (el << 2) | handler; 884 } 885 886 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 887 * interprocessing, so we don't attempt to sync with the cpsr state used by 888 * the 32 bit decoder. 889 */ 890 static inline uint32_t pstate_read(CPUARMState *env) 891 { 892 int ZF; 893 894 ZF = (env->ZF == 0); 895 return (env->NF & 0x80000000) | (ZF << 30) 896 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 897 | env->pstate | env->daif; 898 } 899 900 static inline void pstate_write(CPUARMState *env, uint32_t val) 901 { 902 env->ZF = (~val) & PSTATE_Z; 903 env->NF = val; 904 env->CF = (val >> 29) & 1; 905 env->VF = (val << 3) & 0x80000000; 906 env->daif = val & PSTATE_DAIF; 907 env->pstate = val & ~CACHED_PSTATE_BITS; 908 } 909 910 /* Return the current CPSR value. */ 911 uint32_t cpsr_read(CPUARMState *env); 912 913 typedef enum CPSRWriteType { 914 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 915 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 916 CPSRWriteRaw = 2, /* trust values, do not switch reg banks */ 917 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 918 } CPSRWriteType; 919 920 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/ 921 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 922 CPSRWriteType write_type); 923 924 /* Return the current xPSR value. */ 925 static inline uint32_t xpsr_read(CPUARMState *env) 926 { 927 int ZF; 928 ZF = (env->ZF == 0); 929 return (env->NF & 0x80000000) | (ZF << 30) 930 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 931 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 932 | ((env->condexec_bits & 0xfc) << 8) 933 | env->v7m.exception; 934 } 935 936 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 937 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 938 { 939 if (mask & CPSR_NZCV) { 940 env->ZF = (~val) & CPSR_Z; 941 env->NF = val; 942 env->CF = (val >> 29) & 1; 943 env->VF = (val << 3) & 0x80000000; 944 } 945 if (mask & CPSR_Q) 946 env->QF = ((val & CPSR_Q) != 0); 947 if (mask & (1 << 24)) 948 env->thumb = ((val & (1 << 24)) != 0); 949 if (mask & CPSR_IT_0_1) { 950 env->condexec_bits &= ~3; 951 env->condexec_bits |= (val >> 25) & 3; 952 } 953 if (mask & CPSR_IT_2_7) { 954 env->condexec_bits &= 3; 955 env->condexec_bits |= (val >> 8) & 0xfc; 956 } 957 if (mask & 0x1ff) { 958 env->v7m.exception = val & 0x1ff; 959 } 960 } 961 962 #define HCR_VM (1ULL << 0) 963 #define HCR_SWIO (1ULL << 1) 964 #define HCR_PTW (1ULL << 2) 965 #define HCR_FMO (1ULL << 3) 966 #define HCR_IMO (1ULL << 4) 967 #define HCR_AMO (1ULL << 5) 968 #define HCR_VF (1ULL << 6) 969 #define HCR_VI (1ULL << 7) 970 #define HCR_VSE (1ULL << 8) 971 #define HCR_FB (1ULL << 9) 972 #define HCR_BSU_MASK (3ULL << 10) 973 #define HCR_DC (1ULL << 12) 974 #define HCR_TWI (1ULL << 13) 975 #define HCR_TWE (1ULL << 14) 976 #define HCR_TID0 (1ULL << 15) 977 #define HCR_TID1 (1ULL << 16) 978 #define HCR_TID2 (1ULL << 17) 979 #define HCR_TID3 (1ULL << 18) 980 #define HCR_TSC (1ULL << 19) 981 #define HCR_TIDCP (1ULL << 20) 982 #define HCR_TACR (1ULL << 21) 983 #define HCR_TSW (1ULL << 22) 984 #define HCR_TPC (1ULL << 23) 985 #define HCR_TPU (1ULL << 24) 986 #define HCR_TTLB (1ULL << 25) 987 #define HCR_TVM (1ULL << 26) 988 #define HCR_TGE (1ULL << 27) 989 #define HCR_TDZ (1ULL << 28) 990 #define HCR_HCD (1ULL << 29) 991 #define HCR_TRVM (1ULL << 30) 992 #define HCR_RW (1ULL << 31) 993 #define HCR_CD (1ULL << 32) 994 #define HCR_ID (1ULL << 33) 995 #define HCR_MASK ((1ULL << 34) - 1) 996 997 #define SCR_NS (1U << 0) 998 #define SCR_IRQ (1U << 1) 999 #define SCR_FIQ (1U << 2) 1000 #define SCR_EA (1U << 3) 1001 #define SCR_FW (1U << 4) 1002 #define SCR_AW (1U << 5) 1003 #define SCR_NET (1U << 6) 1004 #define SCR_SMD (1U << 7) 1005 #define SCR_HCE (1U << 8) 1006 #define SCR_SIF (1U << 9) 1007 #define SCR_RW (1U << 10) 1008 #define SCR_ST (1U << 11) 1009 #define SCR_TWI (1U << 12) 1010 #define SCR_TWE (1U << 13) 1011 #define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST)) 1012 #define SCR_AARCH64_MASK (0x3fff & ~SCR_NET) 1013 1014 /* Return the current FPSCR value. */ 1015 uint32_t vfp_get_fpscr(CPUARMState *env); 1016 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1017 1018 /* For A64 the FPSCR is split into two logically distinct registers, 1019 * FPCR and FPSR. However since they still use non-overlapping bits 1020 * we store the underlying state in fpscr and just mask on read/write. 1021 */ 1022 #define FPSR_MASK 0xf800009f 1023 #define FPCR_MASK 0x07f79f00 1024 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1025 { 1026 return vfp_get_fpscr(env) & FPSR_MASK; 1027 } 1028 1029 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1030 { 1031 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1032 vfp_set_fpscr(env, new_fpscr); 1033 } 1034 1035 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1036 { 1037 return vfp_get_fpscr(env) & FPCR_MASK; 1038 } 1039 1040 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1041 { 1042 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1043 vfp_set_fpscr(env, new_fpscr); 1044 } 1045 1046 enum arm_cpu_mode { 1047 ARM_CPU_MODE_USR = 0x10, 1048 ARM_CPU_MODE_FIQ = 0x11, 1049 ARM_CPU_MODE_IRQ = 0x12, 1050 ARM_CPU_MODE_SVC = 0x13, 1051 ARM_CPU_MODE_MON = 0x16, 1052 ARM_CPU_MODE_ABT = 0x17, 1053 ARM_CPU_MODE_HYP = 0x1a, 1054 ARM_CPU_MODE_UND = 0x1b, 1055 ARM_CPU_MODE_SYS = 0x1f 1056 }; 1057 1058 /* VFP system registers. */ 1059 #define ARM_VFP_FPSID 0 1060 #define ARM_VFP_FPSCR 1 1061 #define ARM_VFP_MVFR2 5 1062 #define ARM_VFP_MVFR1 6 1063 #define ARM_VFP_MVFR0 7 1064 #define ARM_VFP_FPEXC 8 1065 #define ARM_VFP_FPINST 9 1066 #define ARM_VFP_FPINST2 10 1067 1068 /* iwMMXt coprocessor control registers. */ 1069 #define ARM_IWMMXT_wCID 0 1070 #define ARM_IWMMXT_wCon 1 1071 #define ARM_IWMMXT_wCSSF 2 1072 #define ARM_IWMMXT_wCASF 3 1073 #define ARM_IWMMXT_wCGR0 8 1074 #define ARM_IWMMXT_wCGR1 9 1075 #define ARM_IWMMXT_wCGR2 10 1076 #define ARM_IWMMXT_wCGR3 11 1077 1078 /* If adding a feature bit which corresponds to a Linux ELF 1079 * HWCAP bit, remember to update the feature-bit-to-hwcap 1080 * mapping in linux-user/elfload.c:get_elf_hwcap(). 1081 */ 1082 enum arm_features { 1083 ARM_FEATURE_VFP, 1084 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 1085 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 1086 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 1087 ARM_FEATURE_V6, 1088 ARM_FEATURE_V6K, 1089 ARM_FEATURE_V7, 1090 ARM_FEATURE_THUMB2, 1091 ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full MMU. */ 1092 ARM_FEATURE_VFP3, 1093 ARM_FEATURE_VFP_FP16, 1094 ARM_FEATURE_NEON, 1095 ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */ 1096 ARM_FEATURE_M, /* Microcontroller profile. */ 1097 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 1098 ARM_FEATURE_THUMB2EE, 1099 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 1100 ARM_FEATURE_V4T, 1101 ARM_FEATURE_V5, 1102 ARM_FEATURE_STRONGARM, 1103 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 1104 ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */ 1105 ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */ 1106 ARM_FEATURE_GENERIC_TIMER, 1107 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 1108 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 1109 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 1110 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 1111 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 1112 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 1113 ARM_FEATURE_PXN, /* has Privileged Execute Never bit */ 1114 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 1115 ARM_FEATURE_V8, 1116 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 1117 ARM_FEATURE_V8_AES, /* implements AES part of v8 Crypto Extensions */ 1118 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 1119 ARM_FEATURE_CRC, /* ARMv8 CRC instructions */ 1120 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 1121 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 1122 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 1123 ARM_FEATURE_V8_SHA1, /* implements SHA1 part of v8 Crypto Extensions */ 1124 ARM_FEATURE_V8_SHA256, /* implements SHA256 part of v8 Crypto Extensions */ 1125 ARM_FEATURE_V8_PMULL, /* implements PMULL part of v8 Crypto Extensions */ 1126 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 1127 ARM_FEATURE_PMU, /* has PMU support */ 1128 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 1129 }; 1130 1131 static inline int arm_feature(CPUARMState *env, int feature) 1132 { 1133 return (env->features & (1ULL << feature)) != 0; 1134 } 1135 1136 #if !defined(CONFIG_USER_ONLY) 1137 /* Return true if exception levels below EL3 are in secure state, 1138 * or would be following an exception return to that level. 1139 * Unlike arm_is_secure() (which is always a question about the 1140 * _current_ state of the CPU) this doesn't care about the current 1141 * EL or mode. 1142 */ 1143 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1144 { 1145 if (arm_feature(env, ARM_FEATURE_EL3)) { 1146 return !(env->cp15.scr_el3 & SCR_NS); 1147 } else { 1148 /* If EL3 is not supported then the secure state is implementation 1149 * defined, in which case QEMU defaults to non-secure. 1150 */ 1151 return false; 1152 } 1153 } 1154 1155 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 1156 static inline bool arm_is_el3_or_mon(CPUARMState *env) 1157 { 1158 if (arm_feature(env, ARM_FEATURE_EL3)) { 1159 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 1160 /* CPU currently in AArch64 state and EL3 */ 1161 return true; 1162 } else if (!is_a64(env) && 1163 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 1164 /* CPU currently in AArch32 state and monitor mode */ 1165 return true; 1166 } 1167 } 1168 return false; 1169 } 1170 1171 /* Return true if the processor is in secure state */ 1172 static inline bool arm_is_secure(CPUARMState *env) 1173 { 1174 if (arm_is_el3_or_mon(env)) { 1175 return true; 1176 } 1177 return arm_is_secure_below_el3(env); 1178 } 1179 1180 #else 1181 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1182 { 1183 return false; 1184 } 1185 1186 static inline bool arm_is_secure(CPUARMState *env) 1187 { 1188 return false; 1189 } 1190 #endif 1191 1192 /* Return true if the specified exception level is running in AArch64 state. */ 1193 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 1194 { 1195 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 1196 * and if we're not in EL0 then the state of EL0 isn't well defined.) 1197 */ 1198 assert(el >= 1 && el <= 3); 1199 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 1200 1201 /* The highest exception level is always at the maximum supported 1202 * register width, and then lower levels have a register width controlled 1203 * by bits in the SCR or HCR registers. 1204 */ 1205 if (el == 3) { 1206 return aa64; 1207 } 1208 1209 if (arm_feature(env, ARM_FEATURE_EL3)) { 1210 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 1211 } 1212 1213 if (el == 2) { 1214 return aa64; 1215 } 1216 1217 if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) { 1218 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 1219 } 1220 1221 return aa64; 1222 } 1223 1224 /* Function for determing whether guest cp register reads and writes should 1225 * access the secure or non-secure bank of a cp register. When EL3 is 1226 * operating in AArch32 state, the NS-bit determines whether the secure 1227 * instance of a cp register should be used. When EL3 is AArch64 (or if 1228 * it doesn't exist at all) then there is no register banking, and all 1229 * accesses are to the non-secure version. 1230 */ 1231 static inline bool access_secure_reg(CPUARMState *env) 1232 { 1233 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 1234 !arm_el_is_aa64(env, 3) && 1235 !(env->cp15.scr_el3 & SCR_NS)); 1236 1237 return ret; 1238 } 1239 1240 /* Macros for accessing a specified CP register bank */ 1241 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 1242 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 1243 1244 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 1245 do { \ 1246 if (_secure) { \ 1247 (_env)->cp15._regname##_s = (_val); \ 1248 } else { \ 1249 (_env)->cp15._regname##_ns = (_val); \ 1250 } \ 1251 } while (0) 1252 1253 /* Macros for automatically accessing a specific CP register bank depending on 1254 * the current secure state of the system. These macros are not intended for 1255 * supporting instruction translation reads/writes as these are dependent 1256 * solely on the SCR.NS bit and not the mode. 1257 */ 1258 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 1259 A32_BANKED_REG_GET((_env), _regname, \ 1260 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 1261 1262 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 1263 A32_BANKED_REG_SET((_env), _regname, \ 1264 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 1265 (_val)) 1266 1267 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf); 1268 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 1269 uint32_t cur_el, bool secure); 1270 1271 /* Interface between CPU and Interrupt controller. */ 1272 void armv7m_nvic_set_pending(void *opaque, int irq); 1273 int armv7m_nvic_acknowledge_irq(void *opaque); 1274 void armv7m_nvic_complete_irq(void *opaque, int irq); 1275 1276 /* Interface for defining coprocessor registers. 1277 * Registers are defined in tables of arm_cp_reginfo structs 1278 * which are passed to define_arm_cp_regs(). 1279 */ 1280 1281 /* When looking up a coprocessor register we look for it 1282 * via an integer which encodes all of: 1283 * coprocessor number 1284 * Crn, Crm, opc1, opc2 fields 1285 * 32 or 64 bit register (ie is it accessed via MRC/MCR 1286 * or via MRRC/MCRR?) 1287 * non-secure/secure bank (AArch32 only) 1288 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 1289 * (In this case crn and opc2 should be zero.) 1290 * For AArch64, there is no 32/64 bit size distinction; 1291 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 1292 * and 4 bit CRn and CRm. The encoding patterns are chosen 1293 * to be easy to convert to and from the KVM encodings, and also 1294 * so that the hashtable can contain both AArch32 and AArch64 1295 * registers (to allow for interprocessing where we might run 1296 * 32 bit code on a 64 bit core). 1297 */ 1298 /* This bit is private to our hashtable cpreg; in KVM register 1299 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 1300 * in the upper bits of the 64 bit ID. 1301 */ 1302 #define CP_REG_AA64_SHIFT 28 1303 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 1304 1305 /* To enable banking of coprocessor registers depending on ns-bit we 1306 * add a bit to distinguish between secure and non-secure cpregs in the 1307 * hashtable. 1308 */ 1309 #define CP_REG_NS_SHIFT 29 1310 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 1311 1312 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 1313 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 1314 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 1315 1316 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 1317 (CP_REG_AA64_MASK | \ 1318 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 1319 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 1320 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 1321 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 1322 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 1323 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 1324 1325 /* Convert a full 64 bit KVM register ID to the truncated 32 bit 1326 * version used as a key for the coprocessor register hashtable 1327 */ 1328 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 1329 { 1330 uint32_t cpregid = kvmid; 1331 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 1332 cpregid |= CP_REG_AA64_MASK; 1333 } else { 1334 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 1335 cpregid |= (1 << 15); 1336 } 1337 1338 /* KVM is always non-secure so add the NS flag on AArch32 register 1339 * entries. 1340 */ 1341 cpregid |= 1 << CP_REG_NS_SHIFT; 1342 } 1343 return cpregid; 1344 } 1345 1346 /* Convert a truncated 32 bit hashtable key into the full 1347 * 64 bit KVM register ID. 1348 */ 1349 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 1350 { 1351 uint64_t kvmid; 1352 1353 if (cpregid & CP_REG_AA64_MASK) { 1354 kvmid = cpregid & ~CP_REG_AA64_MASK; 1355 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 1356 } else { 1357 kvmid = cpregid & ~(1 << 15); 1358 if (cpregid & (1 << 15)) { 1359 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 1360 } else { 1361 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 1362 } 1363 } 1364 return kvmid; 1365 } 1366 1367 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a 1368 * special-behaviour cp reg and bits [15..8] indicate what behaviour 1369 * it has. Otherwise it is a simple cp reg, where CONST indicates that 1370 * TCG can assume the value to be constant (ie load at translate time) 1371 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END 1372 * indicates that the TB should not be ended after a write to this register 1373 * (the default is that the TB ends after cp writes). OVERRIDE permits 1374 * a register definition to override a previous definition for the 1375 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the 1376 * old must have the OVERRIDE bit set. 1377 * ALIAS indicates that this register is an alias view of some underlying 1378 * state which is also visible via another register, and that the other 1379 * register is handling migration and reset; registers marked ALIAS will not be 1380 * migrated but may have their state set by syncing of register state from KVM. 1381 * NO_RAW indicates that this register has no underlying state and does not 1382 * support raw access for state saving/loading; it will not be used for either 1383 * migration or KVM state synchronization. (Typically this is for "registers" 1384 * which are actually used as instructions for cache maintenance and so on.) 1385 * IO indicates that this register does I/O and therefore its accesses 1386 * need to be surrounded by gen_io_start()/gen_io_end(). In particular, 1387 * registers which implement clocks or timers require this. 1388 */ 1389 #define ARM_CP_SPECIAL 1 1390 #define ARM_CP_CONST 2 1391 #define ARM_CP_64BIT 4 1392 #define ARM_CP_SUPPRESS_TB_END 8 1393 #define ARM_CP_OVERRIDE 16 1394 #define ARM_CP_ALIAS 32 1395 #define ARM_CP_IO 64 1396 #define ARM_CP_NO_RAW 128 1397 #define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8)) 1398 #define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8)) 1399 #define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8)) 1400 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8)) 1401 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | (5 << 8)) 1402 #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA 1403 /* Used only as a terminator for ARMCPRegInfo lists */ 1404 #define ARM_CP_SENTINEL 0xffff 1405 /* Mask of only the flag bits in a type field */ 1406 #define ARM_CP_FLAG_MASK 0xff 1407 1408 /* Valid values for ARMCPRegInfo state field, indicating which of 1409 * the AArch32 and AArch64 execution states this register is visible in. 1410 * If the reginfo doesn't explicitly specify then it is AArch32 only. 1411 * If the reginfo is declared to be visible in both states then a second 1412 * reginfo is synthesised for the AArch32 view of the AArch64 register, 1413 * such that the AArch32 view is the lower 32 bits of the AArch64 one. 1414 * Note that we rely on the values of these enums as we iterate through 1415 * the various states in some places. 1416 */ 1417 enum { 1418 ARM_CP_STATE_AA32 = 0, 1419 ARM_CP_STATE_AA64 = 1, 1420 ARM_CP_STATE_BOTH = 2, 1421 }; 1422 1423 /* ARM CP register secure state flags. These flags identify security state 1424 * attributes for a given CP register entry. 1425 * The existence of both or neither secure and non-secure flags indicates that 1426 * the register has both a secure and non-secure hash entry. A single one of 1427 * these flags causes the register to only be hashed for the specified 1428 * security state. 1429 * Although definitions may have any combination of the S/NS bits, each 1430 * registered entry will only have one to identify whether the entry is secure 1431 * or non-secure. 1432 */ 1433 enum { 1434 ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ 1435 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ 1436 }; 1437 1438 /* Return true if cptype is a valid type field. This is used to try to 1439 * catch errors where the sentinel has been accidentally left off the end 1440 * of a list of registers. 1441 */ 1442 static inline bool cptype_valid(int cptype) 1443 { 1444 return ((cptype & ~ARM_CP_FLAG_MASK) == 0) 1445 || ((cptype & ARM_CP_SPECIAL) && 1446 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); 1447 } 1448 1449 /* Access rights: 1450 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM 1451 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and 1452 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 1453 * (ie any of the privileged modes in Secure state, or Monitor mode). 1454 * If a register is accessible in one privilege level it's always accessible 1455 * in higher privilege levels too. Since "Secure PL1" also follows this rule 1456 * (ie anything visible in PL2 is visible in S-PL1, some things are only 1457 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the 1458 * terminology a little and call this PL3. 1459 * In AArch64 things are somewhat simpler as the PLx bits line up exactly 1460 * with the ELx exception levels. 1461 * 1462 * If access permissions for a register are more complex than can be 1463 * described with these bits, then use a laxer set of restrictions, and 1464 * do the more restrictive/complex check inside a helper function. 1465 */ 1466 #define PL3_R 0x80 1467 #define PL3_W 0x40 1468 #define PL2_R (0x20 | PL3_R) 1469 #define PL2_W (0x10 | PL3_W) 1470 #define PL1_R (0x08 | PL2_R) 1471 #define PL1_W (0x04 | PL2_W) 1472 #define PL0_R (0x02 | PL1_R) 1473 #define PL0_W (0x01 | PL1_W) 1474 1475 #define PL3_RW (PL3_R | PL3_W) 1476 #define PL2_RW (PL2_R | PL2_W) 1477 #define PL1_RW (PL1_R | PL1_W) 1478 #define PL0_RW (PL0_R | PL0_W) 1479 1480 /* Return the highest implemented Exception Level */ 1481 static inline int arm_highest_el(CPUARMState *env) 1482 { 1483 if (arm_feature(env, ARM_FEATURE_EL3)) { 1484 return 3; 1485 } 1486 if (arm_feature(env, ARM_FEATURE_EL2)) { 1487 return 2; 1488 } 1489 return 1; 1490 } 1491 1492 /* Return the current Exception Level (as per ARMv8; note that this differs 1493 * from the ARMv7 Privilege Level). 1494 */ 1495 static inline int arm_current_el(CPUARMState *env) 1496 { 1497 if (arm_feature(env, ARM_FEATURE_M)) { 1498 return !((env->v7m.exception == 0) && (env->v7m.control & 1)); 1499 } 1500 1501 if (is_a64(env)) { 1502 return extract32(env->pstate, 2, 2); 1503 } 1504 1505 switch (env->uncached_cpsr & 0x1f) { 1506 case ARM_CPU_MODE_USR: 1507 return 0; 1508 case ARM_CPU_MODE_HYP: 1509 return 2; 1510 case ARM_CPU_MODE_MON: 1511 return 3; 1512 default: 1513 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 1514 /* If EL3 is 32-bit then all secure privileged modes run in 1515 * EL3 1516 */ 1517 return 3; 1518 } 1519 1520 return 1; 1521 } 1522 } 1523 1524 typedef struct ARMCPRegInfo ARMCPRegInfo; 1525 1526 typedef enum CPAccessResult { 1527 /* Access is permitted */ 1528 CP_ACCESS_OK = 0, 1529 /* Access fails due to a configurable trap or enable which would 1530 * result in a categorized exception syndrome giving information about 1531 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, 1532 * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or 1533 * PL1 if in EL0, otherwise to the current EL). 1534 */ 1535 CP_ACCESS_TRAP = 1, 1536 /* Access fails and results in an exception syndrome 0x0 ("uncategorized"). 1537 * Note that this is not a catch-all case -- the set of cases which may 1538 * result in this failure is specifically defined by the architecture. 1539 */ 1540 CP_ACCESS_TRAP_UNCATEGORIZED = 2, 1541 /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ 1542 CP_ACCESS_TRAP_EL2 = 3, 1543 CP_ACCESS_TRAP_EL3 = 4, 1544 /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ 1545 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5, 1546 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6, 1547 /* Access fails and results in an exception syndrome for an FP access, 1548 * trapped directly to EL2 or EL3 1549 */ 1550 CP_ACCESS_TRAP_FP_EL2 = 7, 1551 CP_ACCESS_TRAP_FP_EL3 = 8, 1552 } CPAccessResult; 1553 1554 /* Access functions for coprocessor registers. These cannot fail and 1555 * may not raise exceptions. 1556 */ 1557 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); 1558 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, 1559 uint64_t value); 1560 /* Access permission check functions for coprocessor registers. */ 1561 typedef CPAccessResult CPAccessFn(CPUARMState *env, 1562 const ARMCPRegInfo *opaque, 1563 bool isread); 1564 /* Hook function for register reset */ 1565 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); 1566 1567 #define CP_ANY 0xff 1568 1569 /* Definition of an ARM coprocessor register */ 1570 struct ARMCPRegInfo { 1571 /* Name of register (useful mainly for debugging, need not be unique) */ 1572 const char *name; 1573 /* Location of register: coprocessor number and (crn,crm,opc1,opc2) 1574 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a 1575 * 'wildcard' field -- any value of that field in the MRC/MCR insn 1576 * will be decoded to this register. The register read and write 1577 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 1578 * used by the program, so it is possible to register a wildcard and 1579 * then behave differently on read/write if necessary. 1580 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 1581 * must both be zero. 1582 * For AArch64-visible registers, opc0 is also used. 1583 * Since there are no "coprocessors" in AArch64, cp is purely used as a 1584 * way to distinguish (for KVM's benefit) guest-visible system registers 1585 * from demuxed ones provided to preserve the "no side effects on 1586 * KVM register read/write from QEMU" semantics. cp==0x13 is guest 1587 * visible (to match KVM's encoding); cp==0 will be converted to 1588 * cp==0x13 when the ARMCPRegInfo is registered, for convenience. 1589 */ 1590 uint8_t cp; 1591 uint8_t crn; 1592 uint8_t crm; 1593 uint8_t opc0; 1594 uint8_t opc1; 1595 uint8_t opc2; 1596 /* Execution state in which this register is visible: ARM_CP_STATE_* */ 1597 int state; 1598 /* Register type: ARM_CP_* bits/values */ 1599 int type; 1600 /* Access rights: PL*_[RW] */ 1601 int access; 1602 /* Security state: ARM_CP_SECSTATE_* bits/values */ 1603 int secure; 1604 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when 1605 * this register was defined: can be used to hand data through to the 1606 * register read/write functions, since they are passed the ARMCPRegInfo*. 1607 */ 1608 void *opaque; 1609 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if 1610 * fieldoffset is non-zero, the reset value of the register. 1611 */ 1612 uint64_t resetvalue; 1613 /* Offset of the field in CPUARMState for this register. 1614 * 1615 * This is not needed if either: 1616 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs 1617 * 2. both readfn and writefn are specified 1618 */ 1619 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ 1620 1621 /* Offsets of the secure and non-secure fields in CPUARMState for the 1622 * register if it is banked. These fields are only used during the static 1623 * registration of a register. During hashing the bank associated 1624 * with a given security state is copied to fieldoffset which is used from 1625 * there on out. 1626 * 1627 * It is expected that register definitions use either fieldoffset or 1628 * bank_fieldoffsets in the definition but not both. It is also expected 1629 * that both bank offsets are set when defining a banked register. This 1630 * use indicates that a register is banked. 1631 */ 1632 ptrdiff_t bank_fieldoffsets[2]; 1633 1634 /* Function for making any access checks for this register in addition to 1635 * those specified by the 'access' permissions bits. If NULL, no extra 1636 * checks required. The access check is performed at runtime, not at 1637 * translate time. 1638 */ 1639 CPAccessFn *accessfn; 1640 /* Function for handling reads of this register. If NULL, then reads 1641 * will be done by loading from the offset into CPUARMState specified 1642 * by fieldoffset. 1643 */ 1644 CPReadFn *readfn; 1645 /* Function for handling writes of this register. If NULL, then writes 1646 * will be done by writing to the offset into CPUARMState specified 1647 * by fieldoffset. 1648 */ 1649 CPWriteFn *writefn; 1650 /* Function for doing a "raw" read; used when we need to copy 1651 * coprocessor state to the kernel for KVM or out for 1652 * migration. This only needs to be provided if there is also a 1653 * readfn and it has side effects (for instance clear-on-read bits). 1654 */ 1655 CPReadFn *raw_readfn; 1656 /* Function for doing a "raw" write; used when we need to copy KVM 1657 * kernel coprocessor state into userspace, or for inbound 1658 * migration. This only needs to be provided if there is also a 1659 * writefn and it masks out "unwritable" bits or has write-one-to-clear 1660 * or similar behaviour. 1661 */ 1662 CPWriteFn *raw_writefn; 1663 /* Function for resetting the register. If NULL, then reset will be done 1664 * by writing resetvalue to the field specified in fieldoffset. If 1665 * fieldoffset is 0 then no reset will be done. 1666 */ 1667 CPResetFn *resetfn; 1668 }; 1669 1670 /* Macros which are lvalues for the field in CPUARMState for the 1671 * ARMCPRegInfo *ri. 1672 */ 1673 #define CPREG_FIELD32(env, ri) \ 1674 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) 1675 #define CPREG_FIELD64(env, ri) \ 1676 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) 1677 1678 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } 1679 1680 void define_arm_cp_regs_with_opaque(ARMCPU *cpu, 1681 const ARMCPRegInfo *regs, void *opaque); 1682 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, 1683 const ARMCPRegInfo *regs, void *opaque); 1684 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) 1685 { 1686 define_arm_cp_regs_with_opaque(cpu, regs, 0); 1687 } 1688 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) 1689 { 1690 define_one_arm_cp_reg_with_opaque(cpu, regs, 0); 1691 } 1692 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); 1693 1694 /* CPWriteFn that can be used to implement writes-ignored behaviour */ 1695 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, 1696 uint64_t value); 1697 /* CPReadFn that can be used for read-as-zero behaviour */ 1698 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); 1699 1700 /* CPResetFn that does nothing, for use if no reset is required even 1701 * if fieldoffset is non zero. 1702 */ 1703 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); 1704 1705 /* Return true if this reginfo struct's field in the cpu state struct 1706 * is 64 bits wide. 1707 */ 1708 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) 1709 { 1710 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT); 1711 } 1712 1713 static inline bool cp_access_ok(int current_el, 1714 const ARMCPRegInfo *ri, int isread) 1715 { 1716 return (ri->access >> ((current_el * 2) + isread)) & 1; 1717 } 1718 1719 /* Raw read of a coprocessor register (as needed for migration, etc) */ 1720 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); 1721 1722 /** 1723 * write_list_to_cpustate 1724 * @cpu: ARMCPU 1725 * 1726 * For each register listed in the ARMCPU cpreg_indexes list, write 1727 * its value from the cpreg_values list into the ARMCPUState structure. 1728 * This updates TCG's working data structures from KVM data or 1729 * from incoming migration state. 1730 * 1731 * Returns: true if all register values were updated correctly, 1732 * false if some register was unknown or could not be written. 1733 * Note that we do not stop early on failure -- we will attempt 1734 * writing all registers in the list. 1735 */ 1736 bool write_list_to_cpustate(ARMCPU *cpu); 1737 1738 /** 1739 * write_cpustate_to_list: 1740 * @cpu: ARMCPU 1741 * 1742 * For each register listed in the ARMCPU cpreg_indexes list, write 1743 * its value from the ARMCPUState structure into the cpreg_values list. 1744 * This is used to copy info from TCG's working data structures into 1745 * KVM or for outbound migration. 1746 * 1747 * Returns: true if all register values were read correctly, 1748 * false if some register was unknown or could not be read. 1749 * Note that we do not stop early on failure -- we will attempt 1750 * reading all registers in the list. 1751 */ 1752 bool write_cpustate_to_list(ARMCPU *cpu); 1753 1754 /* Does the core conform to the "MicroController" profile. e.g. Cortex-M3. 1755 Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are 1756 conventional cores (ie. Application or Realtime profile). */ 1757 1758 #define IS_M(env) arm_feature(env, ARM_FEATURE_M) 1759 1760 #define ARM_CPUID_TI915T 0x54029152 1761 #define ARM_CPUID_TI925T 0x54029252 1762 1763 #if defined(CONFIG_USER_ONLY) 1764 #define TARGET_PAGE_BITS 12 1765 #else 1766 /* ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6 1767 * have to support 1K tiny pages. 1768 */ 1769 #define TARGET_PAGE_BITS_VARY 1770 #define TARGET_PAGE_BITS_MIN 10 1771 #endif 1772 1773 #if defined(TARGET_AARCH64) 1774 # define TARGET_PHYS_ADDR_SPACE_BITS 48 1775 # define TARGET_VIRT_ADDR_SPACE_BITS 64 1776 #else 1777 # define TARGET_PHYS_ADDR_SPACE_BITS 40 1778 # define TARGET_VIRT_ADDR_SPACE_BITS 32 1779 #endif 1780 1781 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 1782 unsigned int target_el) 1783 { 1784 CPUARMState *env = cs->env_ptr; 1785 unsigned int cur_el = arm_current_el(env); 1786 bool secure = arm_is_secure(env); 1787 bool pstate_unmasked; 1788 int8_t unmasked = 0; 1789 1790 /* Don't take exceptions if they target a lower EL. 1791 * This check should catch any exceptions that would not be taken but left 1792 * pending. 1793 */ 1794 if (cur_el > target_el) { 1795 return false; 1796 } 1797 1798 switch (excp_idx) { 1799 case EXCP_FIQ: 1800 pstate_unmasked = !(env->daif & PSTATE_F); 1801 break; 1802 1803 case EXCP_IRQ: 1804 pstate_unmasked = !(env->daif & PSTATE_I); 1805 break; 1806 1807 case EXCP_VFIQ: 1808 if (secure || !(env->cp15.hcr_el2 & HCR_FMO)) { 1809 /* VFIQs are only taken when hypervized and non-secure. */ 1810 return false; 1811 } 1812 return !(env->daif & PSTATE_F); 1813 case EXCP_VIRQ: 1814 if (secure || !(env->cp15.hcr_el2 & HCR_IMO)) { 1815 /* VIRQs are only taken when hypervized and non-secure. */ 1816 return false; 1817 } 1818 return !(env->daif & PSTATE_I); 1819 default: 1820 g_assert_not_reached(); 1821 } 1822 1823 /* Use the target EL, current execution state and SCR/HCR settings to 1824 * determine whether the corresponding CPSR bit is used to mask the 1825 * interrupt. 1826 */ 1827 if ((target_el > cur_el) && (target_el != 1)) { 1828 /* Exceptions targeting a higher EL may not be maskable */ 1829 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 1830 /* 64-bit masking rules are simple: exceptions to EL3 1831 * can't be masked, and exceptions to EL2 can only be 1832 * masked from Secure state. The HCR and SCR settings 1833 * don't affect the masking logic, only the interrupt routing. 1834 */ 1835 if (target_el == 3 || !secure) { 1836 unmasked = 1; 1837 } 1838 } else { 1839 /* The old 32-bit-only environment has a more complicated 1840 * masking setup. HCR and SCR bits not only affect interrupt 1841 * routing but also change the behaviour of masking. 1842 */ 1843 bool hcr, scr; 1844 1845 switch (excp_idx) { 1846 case EXCP_FIQ: 1847 /* If FIQs are routed to EL3 or EL2 then there are cases where 1848 * we override the CPSR.F in determining if the exception is 1849 * masked or not. If neither of these are set then we fall back 1850 * to the CPSR.F setting otherwise we further assess the state 1851 * below. 1852 */ 1853 hcr = (env->cp15.hcr_el2 & HCR_FMO); 1854 scr = (env->cp15.scr_el3 & SCR_FIQ); 1855 1856 /* When EL3 is 32-bit, the SCR.FW bit controls whether the 1857 * CPSR.F bit masks FIQ interrupts when taken in non-secure 1858 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 1859 * when non-secure but only when FIQs are only routed to EL3. 1860 */ 1861 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 1862 break; 1863 case EXCP_IRQ: 1864 /* When EL3 execution state is 32-bit, if HCR.IMO is set then 1865 * we may override the CPSR.I masking when in non-secure state. 1866 * The SCR.IRQ setting has already been taken into consideration 1867 * when setting the target EL, so it does not have a further 1868 * affect here. 1869 */ 1870 hcr = (env->cp15.hcr_el2 & HCR_IMO); 1871 scr = false; 1872 break; 1873 default: 1874 g_assert_not_reached(); 1875 } 1876 1877 if ((scr || hcr) && !secure) { 1878 unmasked = 1; 1879 } 1880 } 1881 } 1882 1883 /* The PSTATE bits only mask the interrupt if we have not overriden the 1884 * ability above. 1885 */ 1886 return unmasked || pstate_unmasked; 1887 } 1888 1889 #define cpu_init(cpu_model) CPU(cpu_arm_init(cpu_model)) 1890 1891 #define cpu_signal_handler cpu_arm_signal_handler 1892 #define cpu_list arm_cpu_list 1893 1894 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 1895 * 1896 * If EL3 is 64-bit: 1897 * + NonSecure EL1 & 0 stage 1 1898 * + NonSecure EL1 & 0 stage 2 1899 * + NonSecure EL2 1900 * + Secure EL1 & EL0 1901 * + Secure EL3 1902 * If EL3 is 32-bit: 1903 * + NonSecure PL1 & 0 stage 1 1904 * + NonSecure PL1 & 0 stage 2 1905 * + NonSecure PL2 1906 * + Secure PL0 & PL1 1907 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 1908 * 1909 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 1910 * 1. we need to split the "EL1 & 0" regimes into two mmu_idxes, because they 1911 * may differ in access permissions even if the VA->PA map is the same 1912 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 1913 * translation, which means that we have one mmu_idx that deals with two 1914 * concatenated translation regimes [this sort of combined s1+2 TLB is 1915 * architecturally permitted] 1916 * 3. we don't need to allocate an mmu_idx to translations that we won't be 1917 * handling via the TLB. The only way to do a stage 1 translation without 1918 * the immediate stage 2 translation is via the ATS or AT system insns, 1919 * which can be slow-pathed and always do a page table walk. 1920 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 1921 * translation regimes, because they map reasonably well to each other 1922 * and they can't both be active at the same time. 1923 * This gives us the following list of mmu_idx values: 1924 * 1925 * NS EL0 (aka NS PL0) stage 1+2 1926 * NS EL1 (aka NS PL1) stage 1+2 1927 * NS EL2 (aka NS PL2) 1928 * S EL3 (aka S PL1) 1929 * S EL0 (aka S PL0) 1930 * S EL1 (not used if EL3 is 32 bit) 1931 * NS EL0+1 stage 2 1932 * 1933 * (The last of these is an mmu_idx because we want to be able to use the TLB 1934 * for the accesses done as part of a stage 1 page table walk, rather than 1935 * having to walk the stage 2 page table over and over.) 1936 * 1937 * Our enumeration includes at the end some entries which are not "true" 1938 * mmu_idx values in that they don't have corresponding TLBs and are only 1939 * valid for doing slow path page table walks. 1940 * 1941 * The constant names here are patterned after the general style of the names 1942 * of the AT/ATS operations. 1943 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 1944 */ 1945 typedef enum ARMMMUIdx { 1946 ARMMMUIdx_S12NSE0 = 0, 1947 ARMMMUIdx_S12NSE1 = 1, 1948 ARMMMUIdx_S1E2 = 2, 1949 ARMMMUIdx_S1E3 = 3, 1950 ARMMMUIdx_S1SE0 = 4, 1951 ARMMMUIdx_S1SE1 = 5, 1952 ARMMMUIdx_S2NS = 6, 1953 /* Indexes below here don't have TLBs and are used only for AT system 1954 * instructions or for the first stage of an S12 page table walk. 1955 */ 1956 ARMMMUIdx_S1NSE0 = 7, 1957 ARMMMUIdx_S1NSE1 = 8, 1958 } ARMMMUIdx; 1959 1960 #define MMU_USER_IDX 0 1961 1962 /* Return the exception level we're running at if this is our mmu_idx */ 1963 static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) 1964 { 1965 assert(mmu_idx < ARMMMUIdx_S2NS); 1966 return mmu_idx & 3; 1967 } 1968 1969 /* Determine the current mmu_idx to use for normal loads/stores */ 1970 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) 1971 { 1972 int el = arm_current_el(env); 1973 1974 if (el < 2 && arm_is_secure_below_el3(env)) { 1975 return ARMMMUIdx_S1SE0 + el; 1976 } 1977 return el; 1978 } 1979 1980 /* Indexes used when registering address spaces with cpu_address_space_init */ 1981 typedef enum ARMASIdx { 1982 ARMASIdx_NS = 0, 1983 ARMASIdx_S = 1, 1984 } ARMASIdx; 1985 1986 /* Return the Exception Level targeted by debug exceptions. */ 1987 static inline int arm_debug_target_el(CPUARMState *env) 1988 { 1989 bool secure = arm_is_secure(env); 1990 bool route_to_el2 = false; 1991 1992 if (arm_feature(env, ARM_FEATURE_EL2) && !secure) { 1993 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || 1994 env->cp15.mdcr_el2 & (1 << 8); 1995 } 1996 1997 if (route_to_el2) { 1998 return 2; 1999 } else if (arm_feature(env, ARM_FEATURE_EL3) && 2000 !arm_el_is_aa64(env, 3) && secure) { 2001 return 3; 2002 } else { 2003 return 1; 2004 } 2005 } 2006 2007 static inline bool aa64_generate_debug_exceptions(CPUARMState *env) 2008 { 2009 if (arm_is_secure(env)) { 2010 /* MDCR_EL3.SDD disables debug events from Secure state */ 2011 if (extract32(env->cp15.mdcr_el3, 16, 1) != 0 2012 || arm_current_el(env) == 3) { 2013 return false; 2014 } 2015 } 2016 2017 if (arm_current_el(env) == arm_debug_target_el(env)) { 2018 if ((extract32(env->cp15.mdscr_el1, 13, 1) == 0) 2019 || (env->daif & PSTATE_D)) { 2020 return false; 2021 } 2022 } 2023 return true; 2024 } 2025 2026 static inline bool aa32_generate_debug_exceptions(CPUARMState *env) 2027 { 2028 int el = arm_current_el(env); 2029 2030 if (el == 0 && arm_el_is_aa64(env, 1)) { 2031 return aa64_generate_debug_exceptions(env); 2032 } 2033 2034 if (arm_is_secure(env)) { 2035 int spd; 2036 2037 if (el == 0 && (env->cp15.sder & 1)) { 2038 /* SDER.SUIDEN means debug exceptions from Secure EL0 2039 * are always enabled. Otherwise they are controlled by 2040 * SDCR.SPD like those from other Secure ELs. 2041 */ 2042 return true; 2043 } 2044 2045 spd = extract32(env->cp15.mdcr_el3, 14, 2); 2046 switch (spd) { 2047 case 1: 2048 /* SPD == 0b01 is reserved, but behaves as 0b00. */ 2049 case 0: 2050 /* For 0b00 we return true if external secure invasive debug 2051 * is enabled. On real hardware this is controlled by external 2052 * signals to the core. QEMU always permits debug, and behaves 2053 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. 2054 */ 2055 return true; 2056 case 2: 2057 return false; 2058 case 3: 2059 return true; 2060 } 2061 } 2062 2063 return el != 2; 2064 } 2065 2066 /* Return true if debugging exceptions are currently enabled. 2067 * This corresponds to what in ARM ARM pseudocode would be 2068 * if UsingAArch32() then 2069 * return AArch32.GenerateDebugExceptions() 2070 * else 2071 * return AArch64.GenerateDebugExceptions() 2072 * We choose to push the if() down into this function for clarity, 2073 * since the pseudocode has it at all callsites except for the one in 2074 * CheckSoftwareStep(), where it is elided because both branches would 2075 * always return the same value. 2076 * 2077 * Parts of the pseudocode relating to EL2 and EL3 are omitted because we 2078 * don't yet implement those exception levels or their associated trap bits. 2079 */ 2080 static inline bool arm_generate_debug_exceptions(CPUARMState *env) 2081 { 2082 if (env->aarch64) { 2083 return aa64_generate_debug_exceptions(env); 2084 } else { 2085 return aa32_generate_debug_exceptions(env); 2086 } 2087 } 2088 2089 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check 2090 * implicitly means this always returns false in pre-v8 CPUs.) 2091 */ 2092 static inline bool arm_singlestep_active(CPUARMState *env) 2093 { 2094 return extract32(env->cp15.mdscr_el1, 0, 1) 2095 && arm_el_is_aa64(env, arm_debug_target_el(env)) 2096 && arm_generate_debug_exceptions(env); 2097 } 2098 2099 static inline bool arm_sctlr_b(CPUARMState *env) 2100 { 2101 return 2102 /* We need not implement SCTLR.ITD in user-mode emulation, so 2103 * let linux-user ignore the fact that it conflicts with SCTLR_B. 2104 * This lets people run BE32 binaries with "-cpu any". 2105 */ 2106 #ifndef CONFIG_USER_ONLY 2107 !arm_feature(env, ARM_FEATURE_V7) && 2108 #endif 2109 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 2110 } 2111 2112 /* Return true if the processor is in big-endian mode. */ 2113 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 2114 { 2115 int cur_el; 2116 2117 /* In 32bit endianness is determined by looking at CPSR's E bit */ 2118 if (!is_a64(env)) { 2119 return 2120 #ifdef CONFIG_USER_ONLY 2121 /* In system mode, BE32 is modelled in line with the 2122 * architecture (as word-invariant big-endianness), where loads 2123 * and stores are done little endian but from addresses which 2124 * are adjusted by XORing with the appropriate constant. So the 2125 * endianness to use for the raw data access is not affected by 2126 * SCTLR.B. 2127 * In user mode, however, we model BE32 as byte-invariant 2128 * big-endianness (because user-only code cannot tell the 2129 * difference), and so we need to use a data access endianness 2130 * that depends on SCTLR.B. 2131 */ 2132 arm_sctlr_b(env) || 2133 #endif 2134 ((env->uncached_cpsr & CPSR_E) ? 1 : 0); 2135 } 2136 2137 cur_el = arm_current_el(env); 2138 2139 if (cur_el == 0) { 2140 return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0; 2141 } 2142 2143 return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0; 2144 } 2145 2146 #include "exec/cpu-all.h" 2147 2148 /* Bit usage in the TB flags field: bit 31 indicates whether we are 2149 * in 32 or 64 bit mode. The meaning of the other bits depends on that. 2150 * We put flags which are shared between 32 and 64 bit mode at the top 2151 * of the word, and flags which apply to only one mode at the bottom. 2152 */ 2153 #define ARM_TBFLAG_AARCH64_STATE_SHIFT 31 2154 #define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT) 2155 #define ARM_TBFLAG_MMUIDX_SHIFT 28 2156 #define ARM_TBFLAG_MMUIDX_MASK (0x7 << ARM_TBFLAG_MMUIDX_SHIFT) 2157 #define ARM_TBFLAG_SS_ACTIVE_SHIFT 27 2158 #define ARM_TBFLAG_SS_ACTIVE_MASK (1 << ARM_TBFLAG_SS_ACTIVE_SHIFT) 2159 #define ARM_TBFLAG_PSTATE_SS_SHIFT 26 2160 #define ARM_TBFLAG_PSTATE_SS_MASK (1 << ARM_TBFLAG_PSTATE_SS_SHIFT) 2161 /* Target EL if we take a floating-point-disabled exception */ 2162 #define ARM_TBFLAG_FPEXC_EL_SHIFT 24 2163 #define ARM_TBFLAG_FPEXC_EL_MASK (0x3 << ARM_TBFLAG_FPEXC_EL_SHIFT) 2164 2165 /* Bit usage when in AArch32 state: */ 2166 #define ARM_TBFLAG_THUMB_SHIFT 0 2167 #define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT) 2168 #define ARM_TBFLAG_VECLEN_SHIFT 1 2169 #define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT) 2170 #define ARM_TBFLAG_VECSTRIDE_SHIFT 4 2171 #define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT) 2172 #define ARM_TBFLAG_VFPEN_SHIFT 7 2173 #define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT) 2174 #define ARM_TBFLAG_CONDEXEC_SHIFT 8 2175 #define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT) 2176 #define ARM_TBFLAG_SCTLR_B_SHIFT 16 2177 #define ARM_TBFLAG_SCTLR_B_MASK (1 << ARM_TBFLAG_SCTLR_B_SHIFT) 2178 /* We store the bottom two bits of the CPAR as TB flags and handle 2179 * checks on the other bits at runtime 2180 */ 2181 #define ARM_TBFLAG_XSCALE_CPAR_SHIFT 17 2182 #define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT) 2183 /* Indicates whether cp register reads and writes by guest code should access 2184 * the secure or nonsecure bank of banked registers; note that this is not 2185 * the same thing as the current security state of the processor! 2186 */ 2187 #define ARM_TBFLAG_NS_SHIFT 19 2188 #define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT) 2189 #define ARM_TBFLAG_BE_DATA_SHIFT 20 2190 #define ARM_TBFLAG_BE_DATA_MASK (1 << ARM_TBFLAG_BE_DATA_SHIFT) 2191 2192 /* Bit usage when in AArch64 state */ 2193 #define ARM_TBFLAG_TBI0_SHIFT 0 /* TBI0 for EL0/1 or TBI for EL2/3 */ 2194 #define ARM_TBFLAG_TBI0_MASK (0x1ull << ARM_TBFLAG_TBI0_SHIFT) 2195 #define ARM_TBFLAG_TBI1_SHIFT 1 /* TBI1 for EL0/1 */ 2196 #define ARM_TBFLAG_TBI1_MASK (0x1ull << ARM_TBFLAG_TBI1_SHIFT) 2197 2198 /* some convenience accessor macros */ 2199 #define ARM_TBFLAG_AARCH64_STATE(F) \ 2200 (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT) 2201 #define ARM_TBFLAG_MMUIDX(F) \ 2202 (((F) & ARM_TBFLAG_MMUIDX_MASK) >> ARM_TBFLAG_MMUIDX_SHIFT) 2203 #define ARM_TBFLAG_SS_ACTIVE(F) \ 2204 (((F) & ARM_TBFLAG_SS_ACTIVE_MASK) >> ARM_TBFLAG_SS_ACTIVE_SHIFT) 2205 #define ARM_TBFLAG_PSTATE_SS(F) \ 2206 (((F) & ARM_TBFLAG_PSTATE_SS_MASK) >> ARM_TBFLAG_PSTATE_SS_SHIFT) 2207 #define ARM_TBFLAG_FPEXC_EL(F) \ 2208 (((F) & ARM_TBFLAG_FPEXC_EL_MASK) >> ARM_TBFLAG_FPEXC_EL_SHIFT) 2209 #define ARM_TBFLAG_THUMB(F) \ 2210 (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT) 2211 #define ARM_TBFLAG_VECLEN(F) \ 2212 (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT) 2213 #define ARM_TBFLAG_VECSTRIDE(F) \ 2214 (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT) 2215 #define ARM_TBFLAG_VFPEN(F) \ 2216 (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT) 2217 #define ARM_TBFLAG_CONDEXEC(F) \ 2218 (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT) 2219 #define ARM_TBFLAG_SCTLR_B(F) \ 2220 (((F) & ARM_TBFLAG_SCTLR_B_MASK) >> ARM_TBFLAG_SCTLR_B_SHIFT) 2221 #define ARM_TBFLAG_XSCALE_CPAR(F) \ 2222 (((F) & ARM_TBFLAG_XSCALE_CPAR_MASK) >> ARM_TBFLAG_XSCALE_CPAR_SHIFT) 2223 #define ARM_TBFLAG_NS(F) \ 2224 (((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT) 2225 #define ARM_TBFLAG_BE_DATA(F) \ 2226 (((F) & ARM_TBFLAG_BE_DATA_MASK) >> ARM_TBFLAG_BE_DATA_SHIFT) 2227 #define ARM_TBFLAG_TBI0(F) \ 2228 (((F) & ARM_TBFLAG_TBI0_MASK) >> ARM_TBFLAG_TBI0_SHIFT) 2229 #define ARM_TBFLAG_TBI1(F) \ 2230 (((F) & ARM_TBFLAG_TBI1_MASK) >> ARM_TBFLAG_TBI1_SHIFT) 2231 2232 static inline bool bswap_code(bool sctlr_b) 2233 { 2234 #ifdef CONFIG_USER_ONLY 2235 /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian. 2236 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0 2237 * would also end up as a mixed-endian mode with BE code, LE data. 2238 */ 2239 return 2240 #ifdef TARGET_WORDS_BIGENDIAN 2241 1 ^ 2242 #endif 2243 sctlr_b; 2244 #else 2245 /* All code access in ARM is little endian, and there are no loaders 2246 * doing swaps that need to be reversed 2247 */ 2248 return 0; 2249 #endif 2250 } 2251 2252 /* Return the exception level to which FP-disabled exceptions should 2253 * be taken, or 0 if FP is enabled. 2254 */ 2255 static inline int fp_exception_el(CPUARMState *env) 2256 { 2257 int fpen; 2258 int cur_el = arm_current_el(env); 2259 2260 /* CPACR and the CPTR registers don't exist before v6, so FP is 2261 * always accessible 2262 */ 2263 if (!arm_feature(env, ARM_FEATURE_V6)) { 2264 return 0; 2265 } 2266 2267 /* The CPACR controls traps to EL1, or PL1 if we're 32 bit: 2268 * 0, 2 : trap EL0 and EL1/PL1 accesses 2269 * 1 : trap only EL0 accesses 2270 * 3 : trap no accesses 2271 */ 2272 fpen = extract32(env->cp15.cpacr_el1, 20, 2); 2273 switch (fpen) { 2274 case 0: 2275 case 2: 2276 if (cur_el == 0 || cur_el == 1) { 2277 /* Trap to PL1, which might be EL1 or EL3 */ 2278 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2279 return 3; 2280 } 2281 return 1; 2282 } 2283 if (cur_el == 3 && !is_a64(env)) { 2284 /* Secure PL1 running at EL3 */ 2285 return 3; 2286 } 2287 break; 2288 case 1: 2289 if (cur_el == 0) { 2290 return 1; 2291 } 2292 break; 2293 case 3: 2294 break; 2295 } 2296 2297 /* For the CPTR registers we don't need to guard with an ARM_FEATURE 2298 * check because zero bits in the registers mean "don't trap". 2299 */ 2300 2301 /* CPTR_EL2 : present in v7VE or v8 */ 2302 if (cur_el <= 2 && extract32(env->cp15.cptr_el[2], 10, 1) 2303 && !arm_is_secure_below_el3(env)) { 2304 /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */ 2305 return 2; 2306 } 2307 2308 /* CPTR_EL3 : present in v8 */ 2309 if (extract32(env->cp15.cptr_el[3], 10, 1)) { 2310 /* Trap all FP ops to EL3 */ 2311 return 3; 2312 } 2313 2314 return 0; 2315 } 2316 2317 #ifdef CONFIG_USER_ONLY 2318 static inline bool arm_cpu_bswap_data(CPUARMState *env) 2319 { 2320 return 2321 #ifdef TARGET_WORDS_BIGENDIAN 2322 1 ^ 2323 #endif 2324 arm_cpu_data_is_big_endian(env); 2325 } 2326 #endif 2327 2328 #ifndef CONFIG_USER_ONLY 2329 /** 2330 * arm_regime_tbi0: 2331 * @env: CPUARMState 2332 * @mmu_idx: MMU index indicating required translation regime 2333 * 2334 * Extracts the TBI0 value from the appropriate TCR for the current EL 2335 * 2336 * Returns: the TBI0 value. 2337 */ 2338 uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx); 2339 2340 /** 2341 * arm_regime_tbi1: 2342 * @env: CPUARMState 2343 * @mmu_idx: MMU index indicating required translation regime 2344 * 2345 * Extracts the TBI1 value from the appropriate TCR for the current EL 2346 * 2347 * Returns: the TBI1 value. 2348 */ 2349 uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx); 2350 #else 2351 /* We can't handle tagged addresses properly in user-only mode */ 2352 static inline uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx) 2353 { 2354 return 0; 2355 } 2356 2357 static inline uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx) 2358 { 2359 return 0; 2360 } 2361 #endif 2362 2363 static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 2364 target_ulong *cs_base, uint32_t *flags) 2365 { 2366 ARMMMUIdx mmu_idx = cpu_mmu_index(env, false); 2367 if (is_a64(env)) { 2368 *pc = env->pc; 2369 *flags = ARM_TBFLAG_AARCH64_STATE_MASK; 2370 /* Get control bits for tagged addresses */ 2371 *flags |= (arm_regime_tbi0(env, mmu_idx) << ARM_TBFLAG_TBI0_SHIFT); 2372 *flags |= (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIFT); 2373 } else { 2374 *pc = env->regs[15]; 2375 *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT) 2376 | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT) 2377 | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT) 2378 | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT) 2379 | (arm_sctlr_b(env) << ARM_TBFLAG_SCTLR_B_SHIFT); 2380 if (!(access_secure_reg(env))) { 2381 *flags |= ARM_TBFLAG_NS_MASK; 2382 } 2383 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) 2384 || arm_el_is_aa64(env, 1)) { 2385 *flags |= ARM_TBFLAG_VFPEN_MASK; 2386 } 2387 *flags |= (extract32(env->cp15.c15_cpar, 0, 2) 2388 << ARM_TBFLAG_XSCALE_CPAR_SHIFT); 2389 } 2390 2391 *flags |= (mmu_idx << ARM_TBFLAG_MMUIDX_SHIFT); 2392 2393 /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine 2394 * states defined in the ARM ARM for software singlestep: 2395 * SS_ACTIVE PSTATE.SS State 2396 * 0 x Inactive (the TB flag for SS is always 0) 2397 * 1 0 Active-pending 2398 * 1 1 Active-not-pending 2399 */ 2400 if (arm_singlestep_active(env)) { 2401 *flags |= ARM_TBFLAG_SS_ACTIVE_MASK; 2402 if (is_a64(env)) { 2403 if (env->pstate & PSTATE_SS) { 2404 *flags |= ARM_TBFLAG_PSTATE_SS_MASK; 2405 } 2406 } else { 2407 if (env->uncached_cpsr & PSTATE_SS) { 2408 *flags |= ARM_TBFLAG_PSTATE_SS_MASK; 2409 } 2410 } 2411 } 2412 if (arm_cpu_data_is_big_endian(env)) { 2413 *flags |= ARM_TBFLAG_BE_DATA_MASK; 2414 } 2415 *flags |= fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT; 2416 2417 *cs_base = 0; 2418 } 2419 2420 enum { 2421 QEMU_PSCI_CONDUIT_DISABLED = 0, 2422 QEMU_PSCI_CONDUIT_SMC = 1, 2423 QEMU_PSCI_CONDUIT_HVC = 2, 2424 }; 2425 2426 #ifndef CONFIG_USER_ONLY 2427 /* Return the address space index to use for a memory access */ 2428 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 2429 { 2430 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 2431 } 2432 2433 /* Return the AddressSpace to use for a memory access 2434 * (which depends on whether the access is S or NS, and whether 2435 * the board gave us a separate AddressSpace for S accesses). 2436 */ 2437 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 2438 { 2439 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 2440 } 2441 #endif 2442 2443 /** 2444 * arm_register_el_change_hook: 2445 * Register a hook function which will be called back whenever this 2446 * CPU changes exception level or mode. The hook function will be 2447 * passed a pointer to the ARMCPU and the opaque data pointer passed 2448 * to this function when the hook was registered. 2449 * 2450 * Note that we currently only support registering a single hook function, 2451 * and will assert if this function is called twice. 2452 * This facility is intended for the use of the GICv3 emulation. 2453 */ 2454 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook, 2455 void *opaque); 2456 2457 /** 2458 * arm_get_el_change_hook_opaque: 2459 * Return the opaque data that will be used by the el_change_hook 2460 * for this CPU. 2461 */ 2462 static inline void *arm_get_el_change_hook_opaque(ARMCPU *cpu) 2463 { 2464 return cpu->el_change_hook_opaque; 2465 } 2466 2467 #endif 2468