1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "hw/registerfields.h" 25 #include "cpu-qom.h" 26 #include "exec/cpu-defs.h" 27 #include "qapi/qapi-types-common.h" 28 29 /* ARM processors have a weak memory model */ 30 #define TCG_GUEST_DEFAULT_MO (0) 31 32 #ifdef TARGET_AARCH64 33 #define KVM_HAVE_MCE_INJECTION 1 34 #endif 35 36 #define EXCP_UDEF 1 /* undefined instruction */ 37 #define EXCP_SWI 2 /* software interrupt */ 38 #define EXCP_PREFETCH_ABORT 3 39 #define EXCP_DATA_ABORT 4 40 #define EXCP_IRQ 5 41 #define EXCP_FIQ 6 42 #define EXCP_BKPT 7 43 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 44 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 45 #define EXCP_HVC 11 /* HyperVisor Call */ 46 #define EXCP_HYP_TRAP 12 47 #define EXCP_SMC 13 /* Secure Monitor Call */ 48 #define EXCP_VIRQ 14 49 #define EXCP_VFIQ 15 50 #define EXCP_SEMIHOST 16 /* semihosting call */ 51 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 52 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 53 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 54 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ 55 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ 56 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ 57 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 58 59 #define ARMV7M_EXCP_RESET 1 60 #define ARMV7M_EXCP_NMI 2 61 #define ARMV7M_EXCP_HARD 3 62 #define ARMV7M_EXCP_MEM 4 63 #define ARMV7M_EXCP_BUS 5 64 #define ARMV7M_EXCP_USAGE 6 65 #define ARMV7M_EXCP_SECURE 7 66 #define ARMV7M_EXCP_SVC 11 67 #define ARMV7M_EXCP_DEBUG 12 68 #define ARMV7M_EXCP_PENDSV 14 69 #define ARMV7M_EXCP_SYSTICK 15 70 71 /* For M profile, some registers are banked secure vs non-secure; 72 * these are represented as a 2-element array where the first element 73 * is the non-secure copy and the second is the secure copy. 74 * When the CPU does not have implement the security extension then 75 * only the first element is used. 76 * This means that the copy for the current security state can be 77 * accessed via env->registerfield[env->v7m.secure] (whether the security 78 * extension is implemented or not). 79 */ 80 enum { 81 M_REG_NS = 0, 82 M_REG_S = 1, 83 M_REG_NUM_BANKS = 2, 84 }; 85 86 /* ARM-specific interrupt pending bits. */ 87 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 88 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 89 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 90 91 /* The usual mapping for an AArch64 system register to its AArch32 92 * counterpart is for the 32 bit world to have access to the lower 93 * half only (with writes leaving the upper half untouched). It's 94 * therefore useful to be able to pass TCG the offset of the least 95 * significant half of a uint64_t struct member. 96 */ 97 #ifdef HOST_WORDS_BIGENDIAN 98 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 99 #define offsetofhigh32(S, M) offsetof(S, M) 100 #else 101 #define offsetoflow32(S, M) offsetof(S, M) 102 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 103 #endif 104 105 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 106 #define ARM_CPU_IRQ 0 107 #define ARM_CPU_FIQ 1 108 #define ARM_CPU_VIRQ 2 109 #define ARM_CPU_VFIQ 3 110 111 /* ARM-specific extra insn start words: 112 * 1: Conditional execution bits 113 * 2: Partial exception syndrome for data aborts 114 */ 115 #define TARGET_INSN_START_EXTRA_WORDS 2 116 117 /* The 2nd extra word holding syndrome info for data aborts does not use 118 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 119 * help the sleb128 encoder do a better job. 120 * When restoring the CPU state, we shift it back up. 121 */ 122 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 123 #define ARM_INSN_START_WORD2_SHIFT 14 124 125 /* We currently assume float and double are IEEE single and double 126 precision respectively. 127 Doing runtime conversions is tricky because VFP registers may contain 128 integer values (eg. as the result of a FTOSI instruction). 129 s<2n> maps to the least significant half of d<n> 130 s<2n+1> maps to the most significant half of d<n> 131 */ 132 133 /** 134 * DynamicGDBXMLInfo: 135 * @desc: Contains the XML descriptions. 136 * @num: Number of the registers in this XML seen by GDB. 137 * @data: A union with data specific to the set of registers 138 * @cpregs_keys: Array that contains the corresponding Key of 139 * a given cpreg with the same order of the cpreg 140 * in the XML description. 141 */ 142 typedef struct DynamicGDBXMLInfo { 143 char *desc; 144 int num; 145 union { 146 struct { 147 uint32_t *keys; 148 } cpregs; 149 } data; 150 } DynamicGDBXMLInfo; 151 152 /* CPU state for each instance of a generic timer (in cp15 c14) */ 153 typedef struct ARMGenericTimer { 154 uint64_t cval; /* Timer CompareValue register */ 155 uint64_t ctl; /* Timer Control register */ 156 } ARMGenericTimer; 157 158 #define GTIMER_PHYS 0 159 #define GTIMER_VIRT 1 160 #define GTIMER_HYP 2 161 #define GTIMER_SEC 3 162 #define GTIMER_HYPVIRT 4 163 #define NUM_GTIMERS 5 164 165 typedef struct { 166 uint64_t raw_tcr; 167 uint32_t mask; 168 uint32_t base_mask; 169 } TCR; 170 171 #define VTCR_NSW (1u << 29) 172 #define VTCR_NSA (1u << 30) 173 #define VSTCR_SW VTCR_NSW 174 #define VSTCR_SA VTCR_NSA 175 176 /* Define a maximum sized vector register. 177 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 178 * For 64-bit, this is a 2048-bit SVE register. 179 * 180 * Note that the mapping between S, D, and Q views of the register bank 181 * differs between AArch64 and AArch32. 182 * In AArch32: 183 * Qn = regs[n].d[1]:regs[n].d[0] 184 * Dn = regs[n / 2].d[n & 1] 185 * Sn = regs[n / 4].d[n % 4 / 2], 186 * bits 31..0 for even n, and bits 63..32 for odd n 187 * (and regs[16] to regs[31] are inaccessible) 188 * In AArch64: 189 * Zn = regs[n].d[*] 190 * Qn = regs[n].d[1]:regs[n].d[0] 191 * Dn = regs[n].d[0] 192 * Sn = regs[n].d[0] bits 31..0 193 * Hn = regs[n].d[0] bits 15..0 194 * 195 * This corresponds to the architecturally defined mapping between 196 * the two execution states, and means we do not need to explicitly 197 * map these registers when changing states. 198 * 199 * Align the data for use with TCG host vector operations. 200 */ 201 202 #ifdef TARGET_AARCH64 203 # define ARM_MAX_VQ 16 204 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); 205 void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); 206 #else 207 # define ARM_MAX_VQ 1 208 static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { } 209 static inline void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { } 210 #endif 211 212 typedef struct ARMVectorReg { 213 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 214 } ARMVectorReg; 215 216 #ifdef TARGET_AARCH64 217 /* In AArch32 mode, predicate registers do not exist at all. */ 218 typedef struct ARMPredicateReg { 219 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); 220 } ARMPredicateReg; 221 222 /* In AArch32 mode, PAC keys do not exist at all. */ 223 typedef struct ARMPACKey { 224 uint64_t lo, hi; 225 } ARMPACKey; 226 #endif 227 228 /* See the commentary above the TBFLAG field definitions. */ 229 typedef struct CPUARMTBFlags { 230 uint32_t flags; 231 target_ulong flags2; 232 } CPUARMTBFlags; 233 234 typedef struct CPUARMState { 235 /* Regs for current mode. */ 236 uint32_t regs[16]; 237 238 /* 32/64 switch only happens when taking and returning from 239 * exceptions so the overlap semantics are taken care of then 240 * instead of having a complicated union. 241 */ 242 /* Regs for A64 mode. */ 243 uint64_t xregs[32]; 244 uint64_t pc; 245 /* PSTATE isn't an architectural register for ARMv8. However, it is 246 * convenient for us to assemble the underlying state into a 32 bit format 247 * identical to the architectural format used for the SPSR. (This is also 248 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 249 * 'pstate' register are.) Of the PSTATE bits: 250 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 251 * semantics as for AArch32, as described in the comments on each field) 252 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 253 * DAIF (exception masks) are kept in env->daif 254 * BTYPE is kept in env->btype 255 * all other bits are stored in their correct places in env->pstate 256 */ 257 uint32_t pstate; 258 uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ 259 260 /* Cached TBFLAGS state. See below for which bits are included. */ 261 CPUARMTBFlags hflags; 262 263 /* Frequently accessed CPSR bits are stored separately for efficiency. 264 This contains all the other bits. Use cpsr_{read,write} to access 265 the whole CPSR. */ 266 uint32_t uncached_cpsr; 267 uint32_t spsr; 268 269 /* Banked registers. */ 270 uint64_t banked_spsr[8]; 271 uint32_t banked_r13[8]; 272 uint32_t banked_r14[8]; 273 274 /* These hold r8-r12. */ 275 uint32_t usr_regs[5]; 276 uint32_t fiq_regs[5]; 277 278 /* cpsr flag cache for faster execution */ 279 uint32_t CF; /* 0 or 1 */ 280 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 281 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 282 uint32_t ZF; /* Z set if zero. */ 283 uint32_t QF; /* 0 or 1 */ 284 uint32_t GE; /* cpsr[19:16] */ 285 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ 286 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 287 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 288 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 289 290 uint64_t elr_el[4]; /* AArch64 exception link regs */ 291 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 292 293 /* System control coprocessor (cp15) */ 294 struct { 295 uint32_t c0_cpuid; 296 union { /* Cache size selection */ 297 struct { 298 uint64_t _unused_csselr0; 299 uint64_t csselr_ns; 300 uint64_t _unused_csselr1; 301 uint64_t csselr_s; 302 }; 303 uint64_t csselr_el[4]; 304 }; 305 union { /* System control register. */ 306 struct { 307 uint64_t _unused_sctlr; 308 uint64_t sctlr_ns; 309 uint64_t hsctlr; 310 uint64_t sctlr_s; 311 }; 312 uint64_t sctlr_el[4]; 313 }; 314 uint64_t cpacr_el1; /* Architectural feature access control register */ 315 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 316 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 317 uint64_t sder; /* Secure debug enable register. */ 318 uint32_t nsacr; /* Non-secure access control register. */ 319 union { /* MMU translation table base 0. */ 320 struct { 321 uint64_t _unused_ttbr0_0; 322 uint64_t ttbr0_ns; 323 uint64_t _unused_ttbr0_1; 324 uint64_t ttbr0_s; 325 }; 326 uint64_t ttbr0_el[4]; 327 }; 328 union { /* MMU translation table base 1. */ 329 struct { 330 uint64_t _unused_ttbr1_0; 331 uint64_t ttbr1_ns; 332 uint64_t _unused_ttbr1_1; 333 uint64_t ttbr1_s; 334 }; 335 uint64_t ttbr1_el[4]; 336 }; 337 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 338 uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ 339 /* MMU translation table base control. */ 340 TCR tcr_el[4]; 341 TCR vtcr_el2; /* Virtualization Translation Control. */ 342 TCR vstcr_el2; /* Secure Virtualization Translation Control. */ 343 uint32_t c2_data; /* MPU data cacheable bits. */ 344 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 345 union { /* MMU domain access control register 346 * MPU write buffer control. 347 */ 348 struct { 349 uint64_t dacr_ns; 350 uint64_t dacr_s; 351 }; 352 struct { 353 uint64_t dacr32_el2; 354 }; 355 }; 356 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 357 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 358 uint64_t hcr_el2; /* Hypervisor configuration register */ 359 uint64_t scr_el3; /* Secure configuration register. */ 360 union { /* Fault status registers. */ 361 struct { 362 uint64_t ifsr_ns; 363 uint64_t ifsr_s; 364 }; 365 struct { 366 uint64_t ifsr32_el2; 367 }; 368 }; 369 union { 370 struct { 371 uint64_t _unused_dfsr; 372 uint64_t dfsr_ns; 373 uint64_t hsr; 374 uint64_t dfsr_s; 375 }; 376 uint64_t esr_el[4]; 377 }; 378 uint32_t c6_region[8]; /* MPU base/size registers. */ 379 union { /* Fault address registers. */ 380 struct { 381 uint64_t _unused_far0; 382 #ifdef HOST_WORDS_BIGENDIAN 383 uint32_t ifar_ns; 384 uint32_t dfar_ns; 385 uint32_t ifar_s; 386 uint32_t dfar_s; 387 #else 388 uint32_t dfar_ns; 389 uint32_t ifar_ns; 390 uint32_t dfar_s; 391 uint32_t ifar_s; 392 #endif 393 uint64_t _unused_far3; 394 }; 395 uint64_t far_el[4]; 396 }; 397 uint64_t hpfar_el2; 398 uint64_t hstr_el2; 399 union { /* Translation result. */ 400 struct { 401 uint64_t _unused_par_0; 402 uint64_t par_ns; 403 uint64_t _unused_par_1; 404 uint64_t par_s; 405 }; 406 uint64_t par_el[4]; 407 }; 408 409 uint32_t c9_insn; /* Cache lockdown registers. */ 410 uint32_t c9_data; 411 uint64_t c9_pmcr; /* performance monitor control register */ 412 uint64_t c9_pmcnten; /* perf monitor counter enables */ 413 uint64_t c9_pmovsr; /* perf monitor overflow status */ 414 uint64_t c9_pmuserenr; /* perf monitor user enable */ 415 uint64_t c9_pmselr; /* perf monitor counter selection register */ 416 uint64_t c9_pminten; /* perf monitor interrupt enables */ 417 union { /* Memory attribute redirection */ 418 struct { 419 #ifdef HOST_WORDS_BIGENDIAN 420 uint64_t _unused_mair_0; 421 uint32_t mair1_ns; 422 uint32_t mair0_ns; 423 uint64_t _unused_mair_1; 424 uint32_t mair1_s; 425 uint32_t mair0_s; 426 #else 427 uint64_t _unused_mair_0; 428 uint32_t mair0_ns; 429 uint32_t mair1_ns; 430 uint64_t _unused_mair_1; 431 uint32_t mair0_s; 432 uint32_t mair1_s; 433 #endif 434 }; 435 uint64_t mair_el[4]; 436 }; 437 union { /* vector base address register */ 438 struct { 439 uint64_t _unused_vbar; 440 uint64_t vbar_ns; 441 uint64_t hvbar; 442 uint64_t vbar_s; 443 }; 444 uint64_t vbar_el[4]; 445 }; 446 uint32_t mvbar; /* (monitor) vector base address register */ 447 struct { /* FCSE PID. */ 448 uint32_t fcseidr_ns; 449 uint32_t fcseidr_s; 450 }; 451 union { /* Context ID. */ 452 struct { 453 uint64_t _unused_contextidr_0; 454 uint64_t contextidr_ns; 455 uint64_t _unused_contextidr_1; 456 uint64_t contextidr_s; 457 }; 458 uint64_t contextidr_el[4]; 459 }; 460 union { /* User RW Thread register. */ 461 struct { 462 uint64_t tpidrurw_ns; 463 uint64_t tpidrprw_ns; 464 uint64_t htpidr; 465 uint64_t _tpidr_el3; 466 }; 467 uint64_t tpidr_el[4]; 468 }; 469 /* The secure banks of these registers don't map anywhere */ 470 uint64_t tpidrurw_s; 471 uint64_t tpidrprw_s; 472 uint64_t tpidruro_s; 473 474 union { /* User RO Thread register. */ 475 uint64_t tpidruro_ns; 476 uint64_t tpidrro_el[1]; 477 }; 478 uint64_t c14_cntfrq; /* Counter Frequency register */ 479 uint64_t c14_cntkctl; /* Timer Control register */ 480 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 481 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 482 ARMGenericTimer c14_timer[NUM_GTIMERS]; 483 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 484 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 485 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 486 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 487 uint32_t c15_threadid; /* TI debugger thread-ID. */ 488 uint32_t c15_config_base_address; /* SCU base address. */ 489 uint32_t c15_diagnostic; /* diagnostic register */ 490 uint32_t c15_power_diagnostic; 491 uint32_t c15_power_control; /* power control */ 492 uint64_t dbgbvr[16]; /* breakpoint value registers */ 493 uint64_t dbgbcr[16]; /* breakpoint control registers */ 494 uint64_t dbgwvr[16]; /* watchpoint value registers */ 495 uint64_t dbgwcr[16]; /* watchpoint control registers */ 496 uint64_t mdscr_el1; 497 uint64_t oslsr_el1; /* OS Lock Status */ 498 uint64_t mdcr_el2; 499 uint64_t mdcr_el3; 500 /* Stores the architectural value of the counter *the last time it was 501 * updated* by pmccntr_op_start. Accesses should always be surrounded 502 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 503 * architecturally-correct value is being read/set. 504 */ 505 uint64_t c15_ccnt; 506 /* Stores the delta between the architectural value and the underlying 507 * cycle count during normal operation. It is used to update c15_ccnt 508 * to be the correct architectural value before accesses. During 509 * accesses, c15_ccnt_delta contains the underlying count being used 510 * for the access, after which it reverts to the delta value in 511 * pmccntr_op_finish. 512 */ 513 uint64_t c15_ccnt_delta; 514 uint64_t c14_pmevcntr[31]; 515 uint64_t c14_pmevcntr_delta[31]; 516 uint64_t c14_pmevtyper[31]; 517 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 518 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 519 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 520 uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ 521 uint64_t gcr_el1; 522 uint64_t rgsr_el1; 523 } cp15; 524 525 struct { 526 /* M profile has up to 4 stack pointers: 527 * a Main Stack Pointer and a Process Stack Pointer for each 528 * of the Secure and Non-Secure states. (If the CPU doesn't support 529 * the security extension then it has only two SPs.) 530 * In QEMU we always store the currently active SP in regs[13], 531 * and the non-active SP for the current security state in 532 * v7m.other_sp. The stack pointers for the inactive security state 533 * are stored in other_ss_msp and other_ss_psp. 534 * switch_v7m_security_state() is responsible for rearranging them 535 * when we change security state. 536 */ 537 uint32_t other_sp; 538 uint32_t other_ss_msp; 539 uint32_t other_ss_psp; 540 uint32_t vecbase[M_REG_NUM_BANKS]; 541 uint32_t basepri[M_REG_NUM_BANKS]; 542 uint32_t control[M_REG_NUM_BANKS]; 543 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 544 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 545 uint32_t hfsr; /* HardFault Status */ 546 uint32_t dfsr; /* Debug Fault Status Register */ 547 uint32_t sfsr; /* Secure Fault Status Register */ 548 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 549 uint32_t bfar; /* BusFault Address */ 550 uint32_t sfar; /* Secure Fault Address Register */ 551 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 552 int exception; 553 uint32_t primask[M_REG_NUM_BANKS]; 554 uint32_t faultmask[M_REG_NUM_BANKS]; 555 uint32_t aircr; /* only holds r/w state if security extn implemented */ 556 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 557 uint32_t csselr[M_REG_NUM_BANKS]; 558 uint32_t scr[M_REG_NUM_BANKS]; 559 uint32_t msplim[M_REG_NUM_BANKS]; 560 uint32_t psplim[M_REG_NUM_BANKS]; 561 uint32_t fpcar[M_REG_NUM_BANKS]; 562 uint32_t fpccr[M_REG_NUM_BANKS]; 563 uint32_t fpdscr[M_REG_NUM_BANKS]; 564 uint32_t cpacr[M_REG_NUM_BANKS]; 565 uint32_t nsacr; 566 int ltpsize; 567 } v7m; 568 569 /* Information associated with an exception about to be taken: 570 * code which raises an exception must set cs->exception_index and 571 * the relevant parts of this structure; the cpu_do_interrupt function 572 * will then set the guest-visible registers as part of the exception 573 * entry process. 574 */ 575 struct { 576 uint32_t syndrome; /* AArch64 format syndrome register */ 577 uint32_t fsr; /* AArch32 format fault status register info */ 578 uint64_t vaddress; /* virtual addr associated with exception, if any */ 579 uint32_t target_el; /* EL the exception should be targeted for */ 580 /* If we implement EL2 we will also need to store information 581 * about the intermediate physical address for stage 2 faults. 582 */ 583 } exception; 584 585 /* Information associated with an SError */ 586 struct { 587 uint8_t pending; 588 uint8_t has_esr; 589 uint64_t esr; 590 } serror; 591 592 uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */ 593 594 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 595 uint32_t irq_line_state; 596 597 /* Thumb-2 EE state. */ 598 uint32_t teecr; 599 uint32_t teehbr; 600 601 /* VFP coprocessor state. */ 602 struct { 603 ARMVectorReg zregs[32]; 604 605 #ifdef TARGET_AARCH64 606 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 607 #define FFR_PRED_NUM 16 608 ARMPredicateReg pregs[17]; 609 /* Scratch space for aa64 sve predicate temporary. */ 610 ARMPredicateReg preg_tmp; 611 #endif 612 613 /* We store these fpcsr fields separately for convenience. */ 614 uint32_t qc[4] QEMU_ALIGNED(16); 615 int vec_len; 616 int vec_stride; 617 618 uint32_t xregs[16]; 619 620 /* Scratch space for aa32 neon expansion. */ 621 uint32_t scratch[8]; 622 623 /* There are a number of distinct float control structures: 624 * 625 * fp_status: is the "normal" fp status. 626 * fp_status_fp16: used for half-precision calculations 627 * standard_fp_status : the ARM "Standard FPSCR Value" 628 * standard_fp_status_fp16 : used for half-precision 629 * calculations with the ARM "Standard FPSCR Value" 630 * 631 * Half-precision operations are governed by a separate 632 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 633 * status structure to control this. 634 * 635 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 636 * round-to-nearest and is used by any operations (generally 637 * Neon) which the architecture defines as controlled by the 638 * standard FPSCR value rather than the FPSCR. 639 * 640 * The "standard FPSCR but for fp16 ops" is needed because 641 * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than 642 * using a fixed value for it. 643 * 644 * To avoid having to transfer exception bits around, we simply 645 * say that the FPSCR cumulative exception flags are the logical 646 * OR of the flags in the four fp statuses. This relies on the 647 * only thing which needs to read the exception flags being 648 * an explicit FPSCR read. 649 */ 650 float_status fp_status; 651 float_status fp_status_f16; 652 float_status standard_fp_status; 653 float_status standard_fp_status_f16; 654 655 /* ZCR_EL[1-3] */ 656 uint64_t zcr_el[4]; 657 } vfp; 658 uint64_t exclusive_addr; 659 uint64_t exclusive_val; 660 uint64_t exclusive_high; 661 662 /* iwMMXt coprocessor state. */ 663 struct { 664 uint64_t regs[16]; 665 uint64_t val; 666 667 uint32_t cregs[16]; 668 } iwmmxt; 669 670 #ifdef TARGET_AARCH64 671 struct { 672 ARMPACKey apia; 673 ARMPACKey apib; 674 ARMPACKey apda; 675 ARMPACKey apdb; 676 ARMPACKey apga; 677 } keys; 678 #endif 679 680 #if defined(CONFIG_USER_ONLY) 681 /* For usermode syscall translation. */ 682 int eabi; 683 #endif 684 685 struct CPUBreakpoint *cpu_breakpoint[16]; 686 struct CPUWatchpoint *cpu_watchpoint[16]; 687 688 /* Fields up to this point are cleared by a CPU reset */ 689 struct {} end_reset_fields; 690 691 /* Fields after this point are preserved across CPU reset. */ 692 693 /* Internal CPU feature flags. */ 694 uint64_t features; 695 696 /* PMSAv7 MPU */ 697 struct { 698 uint32_t *drbar; 699 uint32_t *drsr; 700 uint32_t *dracr; 701 uint32_t rnr[M_REG_NUM_BANKS]; 702 } pmsav7; 703 704 /* PMSAv8 MPU */ 705 struct { 706 /* The PMSAv8 implementation also shares some PMSAv7 config 707 * and state: 708 * pmsav7.rnr (region number register) 709 * pmsav7_dregion (number of configured regions) 710 */ 711 uint32_t *rbar[M_REG_NUM_BANKS]; 712 uint32_t *rlar[M_REG_NUM_BANKS]; 713 uint32_t mair0[M_REG_NUM_BANKS]; 714 uint32_t mair1[M_REG_NUM_BANKS]; 715 } pmsav8; 716 717 /* v8M SAU */ 718 struct { 719 uint32_t *rbar; 720 uint32_t *rlar; 721 uint32_t rnr; 722 uint32_t ctrl; 723 } sau; 724 725 void *nvic; 726 const struct arm_boot_info *boot_info; 727 /* Store GICv3CPUState to access from this struct */ 728 void *gicv3state; 729 730 #ifdef TARGET_TAGGED_ADDRESSES 731 /* Linux syscall tagged address support */ 732 bool tagged_addr_enable; 733 #endif 734 } CPUARMState; 735 736 static inline void set_feature(CPUARMState *env, int feature) 737 { 738 env->features |= 1ULL << feature; 739 } 740 741 static inline void unset_feature(CPUARMState *env, int feature) 742 { 743 env->features &= ~(1ULL << feature); 744 } 745 746 /** 747 * ARMELChangeHookFn: 748 * type of a function which can be registered via arm_register_el_change_hook() 749 * to get callbacks when the CPU changes its exception level or mode. 750 */ 751 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 752 typedef struct ARMELChangeHook ARMELChangeHook; 753 struct ARMELChangeHook { 754 ARMELChangeHookFn *hook; 755 void *opaque; 756 QLIST_ENTRY(ARMELChangeHook) node; 757 }; 758 759 /* These values map onto the return values for 760 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 761 typedef enum ARMPSCIState { 762 PSCI_ON = 0, 763 PSCI_OFF = 1, 764 PSCI_ON_PENDING = 2 765 } ARMPSCIState; 766 767 typedef struct ARMISARegisters ARMISARegisters; 768 769 /** 770 * ARMCPU: 771 * @env: #CPUARMState 772 * 773 * An ARM CPU core. 774 */ 775 struct ARMCPU { 776 /*< private >*/ 777 CPUState parent_obj; 778 /*< public >*/ 779 780 CPUNegativeOffsetState neg; 781 CPUARMState env; 782 783 /* Coprocessor information */ 784 GHashTable *cp_regs; 785 /* For marshalling (mostly coprocessor) register state between the 786 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 787 * we use these arrays. 788 */ 789 /* List of register indexes managed via these arrays; (full KVM style 790 * 64 bit indexes, not CPRegInfo 32 bit indexes) 791 */ 792 uint64_t *cpreg_indexes; 793 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 794 uint64_t *cpreg_values; 795 /* Length of the indexes, values, reset_values arrays */ 796 int32_t cpreg_array_len; 797 /* These are used only for migration: incoming data arrives in 798 * these fields and is sanity checked in post_load before copying 799 * to the working data structures above. 800 */ 801 uint64_t *cpreg_vmstate_indexes; 802 uint64_t *cpreg_vmstate_values; 803 int32_t cpreg_vmstate_array_len; 804 805 DynamicGDBXMLInfo dyn_sysreg_xml; 806 DynamicGDBXMLInfo dyn_svereg_xml; 807 808 /* Timers used by the generic (architected) timer */ 809 QEMUTimer *gt_timer[NUM_GTIMERS]; 810 /* 811 * Timer used by the PMU. Its state is restored after migration by 812 * pmu_op_finish() - it does not need other handling during migration 813 */ 814 QEMUTimer *pmu_timer; 815 /* GPIO outputs for generic timer */ 816 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 817 /* GPIO output for GICv3 maintenance interrupt signal */ 818 qemu_irq gicv3_maintenance_interrupt; 819 /* GPIO output for the PMU interrupt */ 820 qemu_irq pmu_interrupt; 821 822 /* MemoryRegion to use for secure physical accesses */ 823 MemoryRegion *secure_memory; 824 825 /* MemoryRegion to use for allocation tag accesses */ 826 MemoryRegion *tag_memory; 827 MemoryRegion *secure_tag_memory; 828 829 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 830 Object *idau; 831 832 /* 'compatible' string for this CPU for Linux device trees */ 833 const char *dtb_compatible; 834 835 /* PSCI version for this CPU 836 * Bits[31:16] = Major Version 837 * Bits[15:0] = Minor Version 838 */ 839 uint32_t psci_version; 840 841 /* Current power state, access guarded by BQL */ 842 ARMPSCIState power_state; 843 844 /* CPU has virtualization extension */ 845 bool has_el2; 846 /* CPU has security extension */ 847 bool has_el3; 848 /* CPU has PMU (Performance Monitor Unit) */ 849 bool has_pmu; 850 /* CPU has VFP */ 851 bool has_vfp; 852 /* CPU has Neon */ 853 bool has_neon; 854 /* CPU has M-profile DSP extension */ 855 bool has_dsp; 856 857 /* CPU has memory protection unit */ 858 bool has_mpu; 859 /* PMSAv7 MPU number of supported regions */ 860 uint32_t pmsav7_dregion; 861 /* v8M SAU number of supported regions */ 862 uint32_t sau_sregion; 863 864 /* PSCI conduit used to invoke PSCI methods 865 * 0 - disabled, 1 - smc, 2 - hvc 866 */ 867 uint32_t psci_conduit; 868 869 /* For v8M, initial value of the Secure VTOR */ 870 uint32_t init_svtor; 871 872 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 873 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 874 */ 875 uint32_t kvm_target; 876 877 /* KVM init features for this CPU */ 878 uint32_t kvm_init_features[7]; 879 880 /* KVM CPU state */ 881 882 /* KVM virtual time adjustment */ 883 bool kvm_adjvtime; 884 bool kvm_vtime_dirty; 885 uint64_t kvm_vtime; 886 887 /* KVM steal time */ 888 OnOffAuto kvm_steal_time; 889 890 /* Uniprocessor system with MP extensions */ 891 bool mp_is_up; 892 893 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 894 * and the probe failed (so we need to report the error in realize) 895 */ 896 bool host_cpu_probe_failed; 897 898 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 899 * register. 900 */ 901 int32_t core_count; 902 903 /* The instance init functions for implementation-specific subclasses 904 * set these fields to specify the implementation-dependent values of 905 * various constant registers and reset values of non-constant 906 * registers. 907 * Some of these might become QOM properties eventually. 908 * Field names match the official register names as defined in the 909 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 910 * is used for reset values of non-constant registers; no reset_ 911 * prefix means a constant register. 912 * Some of these registers are split out into a substructure that 913 * is shared with the translators to control the ISA. 914 * 915 * Note that if you add an ID register to the ARMISARegisters struct 916 * you need to also update the 32-bit and 64-bit versions of the 917 * kvm_arm_get_host_cpu_features() function to correctly populate the 918 * field by reading the value from the KVM vCPU. 919 */ 920 struct ARMISARegisters { 921 uint32_t id_isar0; 922 uint32_t id_isar1; 923 uint32_t id_isar2; 924 uint32_t id_isar3; 925 uint32_t id_isar4; 926 uint32_t id_isar5; 927 uint32_t id_isar6; 928 uint32_t id_mmfr0; 929 uint32_t id_mmfr1; 930 uint32_t id_mmfr2; 931 uint32_t id_mmfr3; 932 uint32_t id_mmfr4; 933 uint32_t id_pfr0; 934 uint32_t id_pfr1; 935 uint32_t id_pfr2; 936 uint32_t mvfr0; 937 uint32_t mvfr1; 938 uint32_t mvfr2; 939 uint32_t id_dfr0; 940 uint32_t dbgdidr; 941 uint64_t id_aa64isar0; 942 uint64_t id_aa64isar1; 943 uint64_t id_aa64pfr0; 944 uint64_t id_aa64pfr1; 945 uint64_t id_aa64mmfr0; 946 uint64_t id_aa64mmfr1; 947 uint64_t id_aa64mmfr2; 948 uint64_t id_aa64dfr0; 949 uint64_t id_aa64dfr1; 950 } isar; 951 uint64_t midr; 952 uint32_t revidr; 953 uint32_t reset_fpsid; 954 uint64_t ctr; 955 uint32_t reset_sctlr; 956 uint64_t pmceid0; 957 uint64_t pmceid1; 958 uint32_t id_afr0; 959 uint64_t id_aa64afr0; 960 uint64_t id_aa64afr1; 961 uint64_t clidr; 962 uint64_t mp_affinity; /* MP ID without feature bits */ 963 /* The elements of this array are the CCSIDR values for each cache, 964 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 965 */ 966 uint64_t ccsidr[16]; 967 uint64_t reset_cbar; 968 uint32_t reset_auxcr; 969 bool reset_hivecs; 970 971 /* 972 * Intermediate values used during property parsing. 973 * Once finalized, the values should be read from ID_AA64ISAR1. 974 */ 975 bool prop_pauth; 976 bool prop_pauth_impdef; 977 978 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 979 uint32_t dcz_blocksize; 980 uint64_t rvbar; 981 982 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 983 int gic_num_lrs; /* number of list registers */ 984 int gic_vpribits; /* number of virtual priority bits */ 985 int gic_vprebits; /* number of virtual preemption bits */ 986 987 /* Whether the cfgend input is high (i.e. this CPU should reset into 988 * big-endian mode). This setting isn't used directly: instead it modifies 989 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 990 * architecture version. 991 */ 992 bool cfgend; 993 994 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 995 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 996 997 int32_t node_id; /* NUMA node this CPU belongs to */ 998 999 /* Used to synchronize KVM and QEMU in-kernel device levels */ 1000 uint8_t device_irq_level; 1001 1002 /* Used to set the maximum vector length the cpu will support. */ 1003 uint32_t sve_max_vq; 1004 1005 /* 1006 * In sve_vq_map each set bit is a supported vector length of 1007 * (bit-number + 1) * 16 bytes, i.e. each bit number + 1 is the vector 1008 * length in quadwords. 1009 * 1010 * While processing properties during initialization, corresponding 1011 * sve_vq_init bits are set for bits in sve_vq_map that have been 1012 * set by properties. 1013 */ 1014 DECLARE_BITMAP(sve_vq_map, ARM_MAX_VQ); 1015 DECLARE_BITMAP(sve_vq_init, ARM_MAX_VQ); 1016 1017 /* Generic timer counter frequency, in Hz */ 1018 uint64_t gt_cntfrq_hz; 1019 }; 1020 1021 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); 1022 1023 void arm_cpu_post_init(Object *obj); 1024 1025 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); 1026 1027 #ifndef CONFIG_USER_ONLY 1028 extern const VMStateDescription vmstate_arm_cpu; 1029 #endif 1030 1031 void arm_cpu_do_interrupt(CPUState *cpu); 1032 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 1033 bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req); 1034 1035 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 1036 MemTxAttrs *attrs); 1037 1038 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1039 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1040 1041 /* 1042 * Helpers to dynamically generates XML descriptions of the sysregs 1043 * and SVE registers. Returns the number of registers in each set. 1044 */ 1045 int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg); 1046 int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg); 1047 1048 /* Returns the dynamically generated XML for the gdb stub. 1049 * Returns a pointer to the XML contents for the specified XML file or NULL 1050 * if the XML name doesn't match the predefined one. 1051 */ 1052 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname); 1053 1054 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 1055 int cpuid, void *opaque); 1056 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 1057 int cpuid, void *opaque); 1058 1059 #ifdef TARGET_AARCH64 1060 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1061 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1062 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 1063 void aarch64_sve_change_el(CPUARMState *env, int old_el, 1064 int new_el, bool el0_a64); 1065 void aarch64_add_sve_properties(Object *obj); 1066 1067 /* 1068 * SVE registers are encoded in KVM's memory in an endianness-invariant format. 1069 * The byte at offset i from the start of the in-memory representation contains 1070 * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the 1071 * lowest offsets are stored in the lowest memory addresses, then that nearly 1072 * matches QEMU's representation, which is to use an array of host-endian 1073 * uint64_t's, where the lower offsets are at the lower indices. To complete 1074 * the translation we just need to byte swap the uint64_t's on big-endian hosts. 1075 */ 1076 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr) 1077 { 1078 #ifdef HOST_WORDS_BIGENDIAN 1079 int i; 1080 1081 for (i = 0; i < nr; ++i) { 1082 dst[i] = bswap64(src[i]); 1083 } 1084 1085 return dst; 1086 #else 1087 return src; 1088 #endif 1089 } 1090 1091 #else 1092 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } 1093 static inline void aarch64_sve_change_el(CPUARMState *env, int o, 1094 int n, bool a) 1095 { } 1096 static inline void aarch64_add_sve_properties(Object *obj) { } 1097 #endif 1098 1099 void aarch64_sync_32_to_64(CPUARMState *env); 1100 void aarch64_sync_64_to_32(CPUARMState *env); 1101 1102 int fp_exception_el(CPUARMState *env, int cur_el); 1103 int sve_exception_el(CPUARMState *env, int cur_el); 1104 uint32_t sve_zcr_len_for_el(CPUARMState *env, int el); 1105 1106 static inline bool is_a64(CPUARMState *env) 1107 { 1108 return env->aarch64; 1109 } 1110 1111 /* you can call this signal handler from your SIGBUS and SIGSEGV 1112 signal handlers to inform the virtual CPU of exceptions. non zero 1113 is returned if the signal was handled by the virtual CPU. */ 1114 int cpu_arm_signal_handler(int host_signum, void *pinfo, 1115 void *puc); 1116 1117 /** 1118 * pmu_op_start/finish 1119 * @env: CPUARMState 1120 * 1121 * Convert all PMU counters between their delta form (the typical mode when 1122 * they are enabled) and the guest-visible values. These two calls must 1123 * surround any action which might affect the counters. 1124 */ 1125 void pmu_op_start(CPUARMState *env); 1126 void pmu_op_finish(CPUARMState *env); 1127 1128 /* 1129 * Called when a PMU counter is due to overflow 1130 */ 1131 void arm_pmu_timer_cb(void *opaque); 1132 1133 /** 1134 * Functions to register as EL change hooks for PMU mode filtering 1135 */ 1136 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1137 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1138 1139 /* 1140 * pmu_init 1141 * @cpu: ARMCPU 1142 * 1143 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1144 * for the current configuration 1145 */ 1146 void pmu_init(ARMCPU *cpu); 1147 1148 /* SCTLR bit meanings. Several bits have been reused in newer 1149 * versions of the architecture; in that case we define constants 1150 * for both old and new bit meanings. Code which tests against those 1151 * bits should probably check or otherwise arrange that the CPU 1152 * is the architectural version it expects. 1153 */ 1154 #define SCTLR_M (1U << 0) 1155 #define SCTLR_A (1U << 1) 1156 #define SCTLR_C (1U << 2) 1157 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1158 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1159 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1160 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1161 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1162 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1163 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1164 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1165 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1166 #define SCTLR_nAA (1U << 6) /* when v8.4-LSE is implemented */ 1167 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1168 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1169 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1170 #define SCTLR_SED (1U << 8) /* v8 onward */ 1171 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1172 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1173 #define SCTLR_F (1U << 10) /* up to v6 */ 1174 #define SCTLR_SW (1U << 10) /* v7 */ 1175 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ 1176 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1177 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1178 #define SCTLR_I (1U << 12) 1179 #define SCTLR_V (1U << 13) /* AArch32 only */ 1180 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1181 #define SCTLR_RR (1U << 14) /* up to v7 */ 1182 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1183 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1184 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1185 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1186 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1187 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1188 #define SCTLR_BR (1U << 17) /* PMSA only */ 1189 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1190 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1191 #define SCTLR_WXN (1U << 19) 1192 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1193 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1194 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1195 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1196 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1197 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1198 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1199 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1200 #define SCTLR_VE (1U << 24) /* up to v7 */ 1201 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1202 #define SCTLR_EE (1U << 25) 1203 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1204 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1205 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1206 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1207 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1208 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1209 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1210 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1211 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1212 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1213 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1214 #define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */ 1215 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1216 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1217 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1218 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1219 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1220 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1221 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1222 #define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */ 1223 1224 #define CPTR_TCPAC (1U << 31) 1225 #define CPTR_TTA (1U << 20) 1226 #define CPTR_TFP (1U << 10) 1227 #define CPTR_TZ (1U << 8) /* CPTR_EL2 */ 1228 #define CPTR_EZ (1U << 8) /* CPTR_EL3 */ 1229 1230 #define MDCR_EPMAD (1U << 21) 1231 #define MDCR_EDAD (1U << 20) 1232 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ 1233 #define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ 1234 #define MDCR_SDD (1U << 16) 1235 #define MDCR_SPD (3U << 14) 1236 #define MDCR_TDRA (1U << 11) 1237 #define MDCR_TDOSA (1U << 10) 1238 #define MDCR_TDA (1U << 9) 1239 #define MDCR_TDE (1U << 8) 1240 #define MDCR_HPME (1U << 7) 1241 #define MDCR_TPM (1U << 6) 1242 #define MDCR_TPMCR (1U << 5) 1243 #define MDCR_HPMN (0x1fU) 1244 1245 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 1246 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) 1247 1248 #define CPSR_M (0x1fU) 1249 #define CPSR_T (1U << 5) 1250 #define CPSR_F (1U << 6) 1251 #define CPSR_I (1U << 7) 1252 #define CPSR_A (1U << 8) 1253 #define CPSR_E (1U << 9) 1254 #define CPSR_IT_2_7 (0xfc00U) 1255 #define CPSR_GE (0xfU << 16) 1256 #define CPSR_IL (1U << 20) 1257 #define CPSR_DIT (1U << 21) 1258 #define CPSR_PAN (1U << 22) 1259 #define CPSR_SSBS (1U << 23) 1260 #define CPSR_J (1U << 24) 1261 #define CPSR_IT_0_1 (3U << 25) 1262 #define CPSR_Q (1U << 27) 1263 #define CPSR_V (1U << 28) 1264 #define CPSR_C (1U << 29) 1265 #define CPSR_Z (1U << 30) 1266 #define CPSR_N (1U << 31) 1267 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1268 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1269 1270 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1271 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1272 | CPSR_NZCV) 1273 /* Bits writable in user mode. */ 1274 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E) 1275 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1276 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1277 1278 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1279 #define XPSR_EXCP 0x1ffU 1280 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1281 #define XPSR_IT_2_7 CPSR_IT_2_7 1282 #define XPSR_GE CPSR_GE 1283 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1284 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1285 #define XPSR_IT_0_1 CPSR_IT_0_1 1286 #define XPSR_Q CPSR_Q 1287 #define XPSR_V CPSR_V 1288 #define XPSR_C CPSR_C 1289 #define XPSR_Z CPSR_Z 1290 #define XPSR_N CPSR_N 1291 #define XPSR_NZCV CPSR_NZCV 1292 #define XPSR_IT CPSR_IT 1293 1294 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 1295 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 1296 #define TTBCR_PD0 (1U << 4) 1297 #define TTBCR_PD1 (1U << 5) 1298 #define TTBCR_EPD0 (1U << 7) 1299 #define TTBCR_IRGN0 (3U << 8) 1300 #define TTBCR_ORGN0 (3U << 10) 1301 #define TTBCR_SH0 (3U << 12) 1302 #define TTBCR_T1SZ (3U << 16) 1303 #define TTBCR_A1 (1U << 22) 1304 #define TTBCR_EPD1 (1U << 23) 1305 #define TTBCR_IRGN1 (3U << 24) 1306 #define TTBCR_ORGN1 (3U << 26) 1307 #define TTBCR_SH1 (1U << 28) 1308 #define TTBCR_EAE (1U << 31) 1309 1310 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1311 * Only these are valid when in AArch64 mode; in 1312 * AArch32 mode SPSRs are basically CPSR-format. 1313 */ 1314 #define PSTATE_SP (1U) 1315 #define PSTATE_M (0xFU) 1316 #define PSTATE_nRW (1U << 4) 1317 #define PSTATE_F (1U << 6) 1318 #define PSTATE_I (1U << 7) 1319 #define PSTATE_A (1U << 8) 1320 #define PSTATE_D (1U << 9) 1321 #define PSTATE_BTYPE (3U << 10) 1322 #define PSTATE_SSBS (1U << 12) 1323 #define PSTATE_IL (1U << 20) 1324 #define PSTATE_SS (1U << 21) 1325 #define PSTATE_PAN (1U << 22) 1326 #define PSTATE_UAO (1U << 23) 1327 #define PSTATE_DIT (1U << 24) 1328 #define PSTATE_TCO (1U << 25) 1329 #define PSTATE_V (1U << 28) 1330 #define PSTATE_C (1U << 29) 1331 #define PSTATE_Z (1U << 30) 1332 #define PSTATE_N (1U << 31) 1333 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1334 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1335 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1336 /* Mode values for AArch64 */ 1337 #define PSTATE_MODE_EL3h 13 1338 #define PSTATE_MODE_EL3t 12 1339 #define PSTATE_MODE_EL2h 9 1340 #define PSTATE_MODE_EL2t 8 1341 #define PSTATE_MODE_EL1h 5 1342 #define PSTATE_MODE_EL1t 4 1343 #define PSTATE_MODE_EL0t 0 1344 1345 /* Write a new value to v7m.exception, thus transitioning into or out 1346 * of Handler mode; this may result in a change of active stack pointer. 1347 */ 1348 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1349 1350 /* Map EL and handler into a PSTATE_MODE. */ 1351 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1352 { 1353 return (el << 2) | handler; 1354 } 1355 1356 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1357 * interprocessing, so we don't attempt to sync with the cpsr state used by 1358 * the 32 bit decoder. 1359 */ 1360 static inline uint32_t pstate_read(CPUARMState *env) 1361 { 1362 int ZF; 1363 1364 ZF = (env->ZF == 0); 1365 return (env->NF & 0x80000000) | (ZF << 30) 1366 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1367 | env->pstate | env->daif | (env->btype << 10); 1368 } 1369 1370 static inline void pstate_write(CPUARMState *env, uint32_t val) 1371 { 1372 env->ZF = (~val) & PSTATE_Z; 1373 env->NF = val; 1374 env->CF = (val >> 29) & 1; 1375 env->VF = (val << 3) & 0x80000000; 1376 env->daif = val & PSTATE_DAIF; 1377 env->btype = (val >> 10) & 3; 1378 env->pstate = val & ~CACHED_PSTATE_BITS; 1379 } 1380 1381 /* Return the current CPSR value. */ 1382 uint32_t cpsr_read(CPUARMState *env); 1383 1384 typedef enum CPSRWriteType { 1385 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1386 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1387 CPSRWriteRaw = 2, /* trust values, do not switch reg banks */ 1388 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1389 } CPSRWriteType; 1390 1391 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/ 1392 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1393 CPSRWriteType write_type); 1394 1395 /* Return the current xPSR value. */ 1396 static inline uint32_t xpsr_read(CPUARMState *env) 1397 { 1398 int ZF; 1399 ZF = (env->ZF == 0); 1400 return (env->NF & 0x80000000) | (ZF << 30) 1401 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1402 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1403 | ((env->condexec_bits & 0xfc) << 8) 1404 | (env->GE << 16) 1405 | env->v7m.exception; 1406 } 1407 1408 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1409 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1410 { 1411 if (mask & XPSR_NZCV) { 1412 env->ZF = (~val) & XPSR_Z; 1413 env->NF = val; 1414 env->CF = (val >> 29) & 1; 1415 env->VF = (val << 3) & 0x80000000; 1416 } 1417 if (mask & XPSR_Q) { 1418 env->QF = ((val & XPSR_Q) != 0); 1419 } 1420 if (mask & XPSR_GE) { 1421 env->GE = (val & XPSR_GE) >> 16; 1422 } 1423 #ifndef CONFIG_USER_ONLY 1424 if (mask & XPSR_T) { 1425 env->thumb = ((val & XPSR_T) != 0); 1426 } 1427 if (mask & XPSR_IT_0_1) { 1428 env->condexec_bits &= ~3; 1429 env->condexec_bits |= (val >> 25) & 3; 1430 } 1431 if (mask & XPSR_IT_2_7) { 1432 env->condexec_bits &= 3; 1433 env->condexec_bits |= (val >> 8) & 0xfc; 1434 } 1435 if (mask & XPSR_EXCP) { 1436 /* Note that this only happens on exception exit */ 1437 write_v7m_exception(env, val & XPSR_EXCP); 1438 } 1439 #endif 1440 } 1441 1442 #define HCR_VM (1ULL << 0) 1443 #define HCR_SWIO (1ULL << 1) 1444 #define HCR_PTW (1ULL << 2) 1445 #define HCR_FMO (1ULL << 3) 1446 #define HCR_IMO (1ULL << 4) 1447 #define HCR_AMO (1ULL << 5) 1448 #define HCR_VF (1ULL << 6) 1449 #define HCR_VI (1ULL << 7) 1450 #define HCR_VSE (1ULL << 8) 1451 #define HCR_FB (1ULL << 9) 1452 #define HCR_BSU_MASK (3ULL << 10) 1453 #define HCR_DC (1ULL << 12) 1454 #define HCR_TWI (1ULL << 13) 1455 #define HCR_TWE (1ULL << 14) 1456 #define HCR_TID0 (1ULL << 15) 1457 #define HCR_TID1 (1ULL << 16) 1458 #define HCR_TID2 (1ULL << 17) 1459 #define HCR_TID3 (1ULL << 18) 1460 #define HCR_TSC (1ULL << 19) 1461 #define HCR_TIDCP (1ULL << 20) 1462 #define HCR_TACR (1ULL << 21) 1463 #define HCR_TSW (1ULL << 22) 1464 #define HCR_TPCP (1ULL << 23) 1465 #define HCR_TPU (1ULL << 24) 1466 #define HCR_TTLB (1ULL << 25) 1467 #define HCR_TVM (1ULL << 26) 1468 #define HCR_TGE (1ULL << 27) 1469 #define HCR_TDZ (1ULL << 28) 1470 #define HCR_HCD (1ULL << 29) 1471 #define HCR_TRVM (1ULL << 30) 1472 #define HCR_RW (1ULL << 31) 1473 #define HCR_CD (1ULL << 32) 1474 #define HCR_ID (1ULL << 33) 1475 #define HCR_E2H (1ULL << 34) 1476 #define HCR_TLOR (1ULL << 35) 1477 #define HCR_TERR (1ULL << 36) 1478 #define HCR_TEA (1ULL << 37) 1479 #define HCR_MIOCNCE (1ULL << 38) 1480 /* RES0 bit 39 */ 1481 #define HCR_APK (1ULL << 40) 1482 #define HCR_API (1ULL << 41) 1483 #define HCR_NV (1ULL << 42) 1484 #define HCR_NV1 (1ULL << 43) 1485 #define HCR_AT (1ULL << 44) 1486 #define HCR_NV2 (1ULL << 45) 1487 #define HCR_FWB (1ULL << 46) 1488 #define HCR_FIEN (1ULL << 47) 1489 /* RES0 bit 48 */ 1490 #define HCR_TID4 (1ULL << 49) 1491 #define HCR_TICAB (1ULL << 50) 1492 #define HCR_AMVOFFEN (1ULL << 51) 1493 #define HCR_TOCU (1ULL << 52) 1494 #define HCR_ENSCXT (1ULL << 53) 1495 #define HCR_TTLBIS (1ULL << 54) 1496 #define HCR_TTLBOS (1ULL << 55) 1497 #define HCR_ATA (1ULL << 56) 1498 #define HCR_DCT (1ULL << 57) 1499 #define HCR_TID5 (1ULL << 58) 1500 #define HCR_TWEDEN (1ULL << 59) 1501 #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) 1502 1503 #define HPFAR_NS (1ULL << 63) 1504 1505 #define SCR_NS (1U << 0) 1506 #define SCR_IRQ (1U << 1) 1507 #define SCR_FIQ (1U << 2) 1508 #define SCR_EA (1U << 3) 1509 #define SCR_FW (1U << 4) 1510 #define SCR_AW (1U << 5) 1511 #define SCR_NET (1U << 6) 1512 #define SCR_SMD (1U << 7) 1513 #define SCR_HCE (1U << 8) 1514 #define SCR_SIF (1U << 9) 1515 #define SCR_RW (1U << 10) 1516 #define SCR_ST (1U << 11) 1517 #define SCR_TWI (1U << 12) 1518 #define SCR_TWE (1U << 13) 1519 #define SCR_TLOR (1U << 14) 1520 #define SCR_TERR (1U << 15) 1521 #define SCR_APK (1U << 16) 1522 #define SCR_API (1U << 17) 1523 #define SCR_EEL2 (1U << 18) 1524 #define SCR_EASE (1U << 19) 1525 #define SCR_NMEA (1U << 20) 1526 #define SCR_FIEN (1U << 21) 1527 #define SCR_ENSCXT (1U << 25) 1528 #define SCR_ATA (1U << 26) 1529 1530 /* Return the current FPSCR value. */ 1531 uint32_t vfp_get_fpscr(CPUARMState *env); 1532 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1533 1534 /* FPCR, Floating Point Control Register 1535 * FPSR, Floating Poiht Status Register 1536 * 1537 * For A64 the FPSCR is split into two logically distinct registers, 1538 * FPCR and FPSR. However since they still use non-overlapping bits 1539 * we store the underlying state in fpscr and just mask on read/write. 1540 */ 1541 #define FPSR_MASK 0xf800009f 1542 #define FPCR_MASK 0x07ff9f00 1543 1544 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1545 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1546 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1547 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1548 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1549 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1550 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1551 #define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */ 1552 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1553 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1554 #define FPCR_AHP (1 << 26) /* Alternative half-precision */ 1555 #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ 1556 #define FPCR_V (1 << 28) /* FP overflow flag */ 1557 #define FPCR_C (1 << 29) /* FP carry flag */ 1558 #define FPCR_Z (1 << 30) /* FP zero flag */ 1559 #define FPCR_N (1 << 31) /* FP negative flag */ 1560 1561 #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */ 1562 #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT) 1563 1564 #define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V) 1565 #define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC) 1566 1567 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1568 { 1569 return vfp_get_fpscr(env) & FPSR_MASK; 1570 } 1571 1572 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1573 { 1574 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1575 vfp_set_fpscr(env, new_fpscr); 1576 } 1577 1578 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1579 { 1580 return vfp_get_fpscr(env) & FPCR_MASK; 1581 } 1582 1583 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1584 { 1585 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1586 vfp_set_fpscr(env, new_fpscr); 1587 } 1588 1589 enum arm_cpu_mode { 1590 ARM_CPU_MODE_USR = 0x10, 1591 ARM_CPU_MODE_FIQ = 0x11, 1592 ARM_CPU_MODE_IRQ = 0x12, 1593 ARM_CPU_MODE_SVC = 0x13, 1594 ARM_CPU_MODE_MON = 0x16, 1595 ARM_CPU_MODE_ABT = 0x17, 1596 ARM_CPU_MODE_HYP = 0x1a, 1597 ARM_CPU_MODE_UND = 0x1b, 1598 ARM_CPU_MODE_SYS = 0x1f 1599 }; 1600 1601 /* VFP system registers. */ 1602 #define ARM_VFP_FPSID 0 1603 #define ARM_VFP_FPSCR 1 1604 #define ARM_VFP_MVFR2 5 1605 #define ARM_VFP_MVFR1 6 1606 #define ARM_VFP_MVFR0 7 1607 #define ARM_VFP_FPEXC 8 1608 #define ARM_VFP_FPINST 9 1609 #define ARM_VFP_FPINST2 10 1610 /* These ones are M-profile only */ 1611 #define ARM_VFP_FPSCR_NZCVQC 2 1612 #define ARM_VFP_VPR 12 1613 #define ARM_VFP_P0 13 1614 #define ARM_VFP_FPCXT_NS 14 1615 #define ARM_VFP_FPCXT_S 15 1616 1617 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */ 1618 #define QEMU_VFP_FPSCR_NZCV 0xffff 1619 1620 /* iwMMXt coprocessor control registers. */ 1621 #define ARM_IWMMXT_wCID 0 1622 #define ARM_IWMMXT_wCon 1 1623 #define ARM_IWMMXT_wCSSF 2 1624 #define ARM_IWMMXT_wCASF 3 1625 #define ARM_IWMMXT_wCGR0 8 1626 #define ARM_IWMMXT_wCGR1 9 1627 #define ARM_IWMMXT_wCGR2 10 1628 #define ARM_IWMMXT_wCGR3 11 1629 1630 /* V7M CCR bits */ 1631 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1632 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1633 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1634 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1635 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1636 FIELD(V7M_CCR, STKALIGN, 9, 1) 1637 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1638 FIELD(V7M_CCR, DC, 16, 1) 1639 FIELD(V7M_CCR, IC, 17, 1) 1640 FIELD(V7M_CCR, BP, 18, 1) 1641 FIELD(V7M_CCR, LOB, 19, 1) 1642 FIELD(V7M_CCR, TRD, 20, 1) 1643 1644 /* V7M SCR bits */ 1645 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1646 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1647 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1648 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1649 1650 /* V7M AIRCR bits */ 1651 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1652 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1653 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1654 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1655 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1656 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1657 FIELD(V7M_AIRCR, PRIS, 14, 1) 1658 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1659 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1660 1661 /* V7M CFSR bits for MMFSR */ 1662 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1663 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1664 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1665 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1666 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1667 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1668 1669 /* V7M CFSR bits for BFSR */ 1670 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1671 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1672 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1673 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1674 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1675 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1676 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1677 1678 /* V7M CFSR bits for UFSR */ 1679 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1680 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1681 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1682 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1683 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1684 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1685 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1686 1687 /* V7M CFSR bit masks covering all of the subregister bits */ 1688 FIELD(V7M_CFSR, MMFSR, 0, 8) 1689 FIELD(V7M_CFSR, BFSR, 8, 8) 1690 FIELD(V7M_CFSR, UFSR, 16, 16) 1691 1692 /* V7M HFSR bits */ 1693 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1694 FIELD(V7M_HFSR, FORCED, 30, 1) 1695 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1696 1697 /* V7M DFSR bits */ 1698 FIELD(V7M_DFSR, HALTED, 0, 1) 1699 FIELD(V7M_DFSR, BKPT, 1, 1) 1700 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1701 FIELD(V7M_DFSR, VCATCH, 3, 1) 1702 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1703 1704 /* V7M SFSR bits */ 1705 FIELD(V7M_SFSR, INVEP, 0, 1) 1706 FIELD(V7M_SFSR, INVIS, 1, 1) 1707 FIELD(V7M_SFSR, INVER, 2, 1) 1708 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1709 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1710 FIELD(V7M_SFSR, LSPERR, 5, 1) 1711 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1712 FIELD(V7M_SFSR, LSERR, 7, 1) 1713 1714 /* v7M MPU_CTRL bits */ 1715 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1716 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1717 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1718 1719 /* v7M CLIDR bits */ 1720 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1721 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1722 FIELD(V7M_CLIDR, LOC, 24, 3) 1723 FIELD(V7M_CLIDR, LOUU, 27, 3) 1724 FIELD(V7M_CLIDR, ICB, 30, 2) 1725 1726 FIELD(V7M_CSSELR, IND, 0, 1) 1727 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1728 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1729 * define a mask for this and check that it doesn't permit running off 1730 * the end of the array. 1731 */ 1732 FIELD(V7M_CSSELR, INDEX, 0, 4) 1733 1734 /* v7M FPCCR bits */ 1735 FIELD(V7M_FPCCR, LSPACT, 0, 1) 1736 FIELD(V7M_FPCCR, USER, 1, 1) 1737 FIELD(V7M_FPCCR, S, 2, 1) 1738 FIELD(V7M_FPCCR, THREAD, 3, 1) 1739 FIELD(V7M_FPCCR, HFRDY, 4, 1) 1740 FIELD(V7M_FPCCR, MMRDY, 5, 1) 1741 FIELD(V7M_FPCCR, BFRDY, 6, 1) 1742 FIELD(V7M_FPCCR, SFRDY, 7, 1) 1743 FIELD(V7M_FPCCR, MONRDY, 8, 1) 1744 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) 1745 FIELD(V7M_FPCCR, UFRDY, 10, 1) 1746 FIELD(V7M_FPCCR, RES0, 11, 15) 1747 FIELD(V7M_FPCCR, TS, 26, 1) 1748 FIELD(V7M_FPCCR, CLRONRETS, 27, 1) 1749 FIELD(V7M_FPCCR, CLRONRET, 28, 1) 1750 FIELD(V7M_FPCCR, LSPENS, 29, 1) 1751 FIELD(V7M_FPCCR, LSPEN, 30, 1) 1752 FIELD(V7M_FPCCR, ASPEN, 31, 1) 1753 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */ 1754 #define R_V7M_FPCCR_BANKED_MASK \ 1755 (R_V7M_FPCCR_LSPACT_MASK | \ 1756 R_V7M_FPCCR_USER_MASK | \ 1757 R_V7M_FPCCR_THREAD_MASK | \ 1758 R_V7M_FPCCR_MMRDY_MASK | \ 1759 R_V7M_FPCCR_SPLIMVIOL_MASK | \ 1760 R_V7M_FPCCR_UFRDY_MASK | \ 1761 R_V7M_FPCCR_ASPEN_MASK) 1762 1763 /* 1764 * System register ID fields. 1765 */ 1766 FIELD(CLIDR_EL1, CTYPE1, 0, 3) 1767 FIELD(CLIDR_EL1, CTYPE2, 3, 3) 1768 FIELD(CLIDR_EL1, CTYPE3, 6, 3) 1769 FIELD(CLIDR_EL1, CTYPE4, 9, 3) 1770 FIELD(CLIDR_EL1, CTYPE5, 12, 3) 1771 FIELD(CLIDR_EL1, CTYPE6, 15, 3) 1772 FIELD(CLIDR_EL1, CTYPE7, 18, 3) 1773 FIELD(CLIDR_EL1, LOUIS, 21, 3) 1774 FIELD(CLIDR_EL1, LOC, 24, 3) 1775 FIELD(CLIDR_EL1, LOUU, 27, 3) 1776 FIELD(CLIDR_EL1, ICB, 30, 3) 1777 1778 /* When FEAT_CCIDX is implemented */ 1779 FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3) 1780 FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21) 1781 FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24) 1782 1783 /* When FEAT_CCIDX is not implemented */ 1784 FIELD(CCSIDR_EL1, LINESIZE, 0, 3) 1785 FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10) 1786 FIELD(CCSIDR_EL1, NUMSETS, 13, 15) 1787 1788 FIELD(CTR_EL0, IMINLINE, 0, 4) 1789 FIELD(CTR_EL0, L1IP, 14, 2) 1790 FIELD(CTR_EL0, DMINLINE, 16, 4) 1791 FIELD(CTR_EL0, ERG, 20, 4) 1792 FIELD(CTR_EL0, CWG, 24, 4) 1793 FIELD(CTR_EL0, IDC, 28, 1) 1794 FIELD(CTR_EL0, DIC, 29, 1) 1795 FIELD(CTR_EL0, TMINLINE, 32, 6) 1796 1797 FIELD(MIDR_EL1, REVISION, 0, 4) 1798 FIELD(MIDR_EL1, PARTNUM, 4, 12) 1799 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) 1800 FIELD(MIDR_EL1, VARIANT, 20, 4) 1801 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) 1802 1803 FIELD(ID_ISAR0, SWAP, 0, 4) 1804 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 1805 FIELD(ID_ISAR0, BITFIELD, 8, 4) 1806 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 1807 FIELD(ID_ISAR0, COPROC, 16, 4) 1808 FIELD(ID_ISAR0, DEBUG, 20, 4) 1809 FIELD(ID_ISAR0, DIVIDE, 24, 4) 1810 1811 FIELD(ID_ISAR1, ENDIAN, 0, 4) 1812 FIELD(ID_ISAR1, EXCEPT, 4, 4) 1813 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 1814 FIELD(ID_ISAR1, EXTEND, 12, 4) 1815 FIELD(ID_ISAR1, IFTHEN, 16, 4) 1816 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 1817 FIELD(ID_ISAR1, INTERWORK, 24, 4) 1818 FIELD(ID_ISAR1, JAZELLE, 28, 4) 1819 1820 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 1821 FIELD(ID_ISAR2, MEMHINT, 4, 4) 1822 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 1823 FIELD(ID_ISAR2, MULT, 12, 4) 1824 FIELD(ID_ISAR2, MULTS, 16, 4) 1825 FIELD(ID_ISAR2, MULTU, 20, 4) 1826 FIELD(ID_ISAR2, PSR_AR, 24, 4) 1827 FIELD(ID_ISAR2, REVERSAL, 28, 4) 1828 1829 FIELD(ID_ISAR3, SATURATE, 0, 4) 1830 FIELD(ID_ISAR3, SIMD, 4, 4) 1831 FIELD(ID_ISAR3, SVC, 8, 4) 1832 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 1833 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 1834 FIELD(ID_ISAR3, T32COPY, 20, 4) 1835 FIELD(ID_ISAR3, TRUENOP, 24, 4) 1836 FIELD(ID_ISAR3, T32EE, 28, 4) 1837 1838 FIELD(ID_ISAR4, UNPRIV, 0, 4) 1839 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 1840 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 1841 FIELD(ID_ISAR4, SMC, 12, 4) 1842 FIELD(ID_ISAR4, BARRIER, 16, 4) 1843 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 1844 FIELD(ID_ISAR4, PSR_M, 24, 4) 1845 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 1846 1847 FIELD(ID_ISAR5, SEVL, 0, 4) 1848 FIELD(ID_ISAR5, AES, 4, 4) 1849 FIELD(ID_ISAR5, SHA1, 8, 4) 1850 FIELD(ID_ISAR5, SHA2, 12, 4) 1851 FIELD(ID_ISAR5, CRC32, 16, 4) 1852 FIELD(ID_ISAR5, RDM, 24, 4) 1853 FIELD(ID_ISAR5, VCMA, 28, 4) 1854 1855 FIELD(ID_ISAR6, JSCVT, 0, 4) 1856 FIELD(ID_ISAR6, DP, 4, 4) 1857 FIELD(ID_ISAR6, FHM, 8, 4) 1858 FIELD(ID_ISAR6, SB, 12, 4) 1859 FIELD(ID_ISAR6, SPECRES, 16, 4) 1860 FIELD(ID_ISAR6, BF16, 20, 4) 1861 FIELD(ID_ISAR6, I8MM, 24, 4) 1862 1863 FIELD(ID_MMFR0, VMSA, 0, 4) 1864 FIELD(ID_MMFR0, PMSA, 4, 4) 1865 FIELD(ID_MMFR0, OUTERSHR, 8, 4) 1866 FIELD(ID_MMFR0, SHARELVL, 12, 4) 1867 FIELD(ID_MMFR0, TCM, 16, 4) 1868 FIELD(ID_MMFR0, AUXREG, 20, 4) 1869 FIELD(ID_MMFR0, FCSE, 24, 4) 1870 FIELD(ID_MMFR0, INNERSHR, 28, 4) 1871 1872 FIELD(ID_MMFR1, L1HVDVA, 0, 4) 1873 FIELD(ID_MMFR1, L1UNIVA, 4, 4) 1874 FIELD(ID_MMFR1, L1HVDSW, 8, 4) 1875 FIELD(ID_MMFR1, L1UNISW, 12, 4) 1876 FIELD(ID_MMFR1, L1HVD, 16, 4) 1877 FIELD(ID_MMFR1, L1UNI, 20, 4) 1878 FIELD(ID_MMFR1, L1TSTCLN, 24, 4) 1879 FIELD(ID_MMFR1, BPRED, 28, 4) 1880 1881 FIELD(ID_MMFR2, L1HVDFG, 0, 4) 1882 FIELD(ID_MMFR2, L1HVDBG, 4, 4) 1883 FIELD(ID_MMFR2, L1HVDRNG, 8, 4) 1884 FIELD(ID_MMFR2, HVDTLB, 12, 4) 1885 FIELD(ID_MMFR2, UNITLB, 16, 4) 1886 FIELD(ID_MMFR2, MEMBARR, 20, 4) 1887 FIELD(ID_MMFR2, WFISTALL, 24, 4) 1888 FIELD(ID_MMFR2, HWACCFLG, 28, 4) 1889 1890 FIELD(ID_MMFR3, CMAINTVA, 0, 4) 1891 FIELD(ID_MMFR3, CMAINTSW, 4, 4) 1892 FIELD(ID_MMFR3, BPMAINT, 8, 4) 1893 FIELD(ID_MMFR3, MAINTBCST, 12, 4) 1894 FIELD(ID_MMFR3, PAN, 16, 4) 1895 FIELD(ID_MMFR3, COHWALK, 20, 4) 1896 FIELD(ID_MMFR3, CMEMSZ, 24, 4) 1897 FIELD(ID_MMFR3, SUPERSEC, 28, 4) 1898 1899 FIELD(ID_MMFR4, SPECSEI, 0, 4) 1900 FIELD(ID_MMFR4, AC2, 4, 4) 1901 FIELD(ID_MMFR4, XNX, 8, 4) 1902 FIELD(ID_MMFR4, CNP, 12, 4) 1903 FIELD(ID_MMFR4, HPDS, 16, 4) 1904 FIELD(ID_MMFR4, LSM, 20, 4) 1905 FIELD(ID_MMFR4, CCIDX, 24, 4) 1906 FIELD(ID_MMFR4, EVT, 28, 4) 1907 1908 FIELD(ID_MMFR5, ETS, 0, 4) 1909 1910 FIELD(ID_PFR0, STATE0, 0, 4) 1911 FIELD(ID_PFR0, STATE1, 4, 4) 1912 FIELD(ID_PFR0, STATE2, 8, 4) 1913 FIELD(ID_PFR0, STATE3, 12, 4) 1914 FIELD(ID_PFR0, CSV2, 16, 4) 1915 FIELD(ID_PFR0, AMU, 20, 4) 1916 FIELD(ID_PFR0, DIT, 24, 4) 1917 FIELD(ID_PFR0, RAS, 28, 4) 1918 1919 FIELD(ID_PFR1, PROGMOD, 0, 4) 1920 FIELD(ID_PFR1, SECURITY, 4, 4) 1921 FIELD(ID_PFR1, MPROGMOD, 8, 4) 1922 FIELD(ID_PFR1, VIRTUALIZATION, 12, 4) 1923 FIELD(ID_PFR1, GENTIMER, 16, 4) 1924 FIELD(ID_PFR1, SEC_FRAC, 20, 4) 1925 FIELD(ID_PFR1, VIRT_FRAC, 24, 4) 1926 FIELD(ID_PFR1, GIC, 28, 4) 1927 1928 FIELD(ID_PFR2, CSV3, 0, 4) 1929 FIELD(ID_PFR2, SSBS, 4, 4) 1930 FIELD(ID_PFR2, RAS_FRAC, 8, 4) 1931 1932 FIELD(ID_AA64ISAR0, AES, 4, 4) 1933 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 1934 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 1935 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 1936 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 1937 FIELD(ID_AA64ISAR0, RDM, 28, 4) 1938 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 1939 FIELD(ID_AA64ISAR0, SM3, 36, 4) 1940 FIELD(ID_AA64ISAR0, SM4, 40, 4) 1941 FIELD(ID_AA64ISAR0, DP, 44, 4) 1942 FIELD(ID_AA64ISAR0, FHM, 48, 4) 1943 FIELD(ID_AA64ISAR0, TS, 52, 4) 1944 FIELD(ID_AA64ISAR0, TLB, 56, 4) 1945 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 1946 1947 FIELD(ID_AA64ISAR1, DPB, 0, 4) 1948 FIELD(ID_AA64ISAR1, APA, 4, 4) 1949 FIELD(ID_AA64ISAR1, API, 8, 4) 1950 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 1951 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 1952 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 1953 FIELD(ID_AA64ISAR1, GPA, 24, 4) 1954 FIELD(ID_AA64ISAR1, GPI, 28, 4) 1955 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 1956 FIELD(ID_AA64ISAR1, SB, 36, 4) 1957 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 1958 FIELD(ID_AA64ISAR1, BF16, 44, 4) 1959 FIELD(ID_AA64ISAR1, DGH, 48, 4) 1960 FIELD(ID_AA64ISAR1, I8MM, 52, 4) 1961 1962 FIELD(ID_AA64PFR0, EL0, 0, 4) 1963 FIELD(ID_AA64PFR0, EL1, 4, 4) 1964 FIELD(ID_AA64PFR0, EL2, 8, 4) 1965 FIELD(ID_AA64PFR0, EL3, 12, 4) 1966 FIELD(ID_AA64PFR0, FP, 16, 4) 1967 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 1968 FIELD(ID_AA64PFR0, GIC, 24, 4) 1969 FIELD(ID_AA64PFR0, RAS, 28, 4) 1970 FIELD(ID_AA64PFR0, SVE, 32, 4) 1971 FIELD(ID_AA64PFR0, SEL2, 36, 4) 1972 FIELD(ID_AA64PFR0, MPAM, 40, 4) 1973 FIELD(ID_AA64PFR0, AMU, 44, 4) 1974 FIELD(ID_AA64PFR0, DIT, 48, 4) 1975 FIELD(ID_AA64PFR0, CSV2, 56, 4) 1976 FIELD(ID_AA64PFR0, CSV3, 60, 4) 1977 1978 FIELD(ID_AA64PFR1, BT, 0, 4) 1979 FIELD(ID_AA64PFR1, SSBS, 4, 4) 1980 FIELD(ID_AA64PFR1, MTE, 8, 4) 1981 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 1982 FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) 1983 1984 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 1985 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 1986 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 1987 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 1988 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 1989 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 1990 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 1991 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 1992 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 1993 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 1994 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 1995 FIELD(ID_AA64MMFR0, EXS, 44, 4) 1996 FIELD(ID_AA64MMFR0, FGT, 56, 4) 1997 FIELD(ID_AA64MMFR0, ECV, 60, 4) 1998 1999 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 2000 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 2001 FIELD(ID_AA64MMFR1, VH, 8, 4) 2002 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 2003 FIELD(ID_AA64MMFR1, LO, 16, 4) 2004 FIELD(ID_AA64MMFR1, PAN, 20, 4) 2005 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 2006 FIELD(ID_AA64MMFR1, XNX, 28, 4) 2007 FIELD(ID_AA64MMFR1, TWED, 32, 4) 2008 FIELD(ID_AA64MMFR1, ETS, 36, 4) 2009 2010 FIELD(ID_AA64MMFR2, CNP, 0, 4) 2011 FIELD(ID_AA64MMFR2, UAO, 4, 4) 2012 FIELD(ID_AA64MMFR2, LSM, 8, 4) 2013 FIELD(ID_AA64MMFR2, IESB, 12, 4) 2014 FIELD(ID_AA64MMFR2, VARANGE, 16, 4) 2015 FIELD(ID_AA64MMFR2, CCIDX, 20, 4) 2016 FIELD(ID_AA64MMFR2, NV, 24, 4) 2017 FIELD(ID_AA64MMFR2, ST, 28, 4) 2018 FIELD(ID_AA64MMFR2, AT, 32, 4) 2019 FIELD(ID_AA64MMFR2, IDS, 36, 4) 2020 FIELD(ID_AA64MMFR2, FWB, 40, 4) 2021 FIELD(ID_AA64MMFR2, TTL, 48, 4) 2022 FIELD(ID_AA64MMFR2, BBM, 52, 4) 2023 FIELD(ID_AA64MMFR2, EVT, 56, 4) 2024 FIELD(ID_AA64MMFR2, E0PD, 60, 4) 2025 2026 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) 2027 FIELD(ID_AA64DFR0, TRACEVER, 4, 4) 2028 FIELD(ID_AA64DFR0, PMUVER, 8, 4) 2029 FIELD(ID_AA64DFR0, BRPS, 12, 4) 2030 FIELD(ID_AA64DFR0, WRPS, 20, 4) 2031 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) 2032 FIELD(ID_AA64DFR0, PMSVER, 32, 4) 2033 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) 2034 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) 2035 FIELD(ID_AA64DFR0, MTPMU, 48, 4) 2036 2037 FIELD(ID_DFR0, COPDBG, 0, 4) 2038 FIELD(ID_DFR0, COPSDBG, 4, 4) 2039 FIELD(ID_DFR0, MMAPDBG, 8, 4) 2040 FIELD(ID_DFR0, COPTRC, 12, 4) 2041 FIELD(ID_DFR0, MMAPTRC, 16, 4) 2042 FIELD(ID_DFR0, MPROFDBG, 20, 4) 2043 FIELD(ID_DFR0, PERFMON, 24, 4) 2044 FIELD(ID_DFR0, TRACEFILT, 28, 4) 2045 2046 FIELD(ID_DFR1, MTPMU, 0, 4) 2047 2048 FIELD(DBGDIDR, SE_IMP, 12, 1) 2049 FIELD(DBGDIDR, NSUHD_IMP, 14, 1) 2050 FIELD(DBGDIDR, VERSION, 16, 4) 2051 FIELD(DBGDIDR, CTX_CMPS, 20, 4) 2052 FIELD(DBGDIDR, BRPS, 24, 4) 2053 FIELD(DBGDIDR, WRPS, 28, 4) 2054 2055 FIELD(MVFR0, SIMDREG, 0, 4) 2056 FIELD(MVFR0, FPSP, 4, 4) 2057 FIELD(MVFR0, FPDP, 8, 4) 2058 FIELD(MVFR0, FPTRAP, 12, 4) 2059 FIELD(MVFR0, FPDIVIDE, 16, 4) 2060 FIELD(MVFR0, FPSQRT, 20, 4) 2061 FIELD(MVFR0, FPSHVEC, 24, 4) 2062 FIELD(MVFR0, FPROUND, 28, 4) 2063 2064 FIELD(MVFR1, FPFTZ, 0, 4) 2065 FIELD(MVFR1, FPDNAN, 4, 4) 2066 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */ 2067 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */ 2068 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */ 2069 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */ 2070 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */ 2071 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */ 2072 FIELD(MVFR1, FPHP, 24, 4) 2073 FIELD(MVFR1, SIMDFMAC, 28, 4) 2074 2075 FIELD(MVFR2, SIMDMISC, 0, 4) 2076 FIELD(MVFR2, FPMISC, 4, 4) 2077 2078 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 2079 2080 /* If adding a feature bit which corresponds to a Linux ELF 2081 * HWCAP bit, remember to update the feature-bit-to-hwcap 2082 * mapping in linux-user/elfload.c:get_elf_hwcap(). 2083 */ 2084 enum arm_features { 2085 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 2086 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 2087 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 2088 ARM_FEATURE_V6, 2089 ARM_FEATURE_V6K, 2090 ARM_FEATURE_V7, 2091 ARM_FEATURE_THUMB2, 2092 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 2093 ARM_FEATURE_NEON, 2094 ARM_FEATURE_M, /* Microcontroller profile. */ 2095 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 2096 ARM_FEATURE_THUMB2EE, 2097 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 2098 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 2099 ARM_FEATURE_V4T, 2100 ARM_FEATURE_V5, 2101 ARM_FEATURE_STRONGARM, 2102 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 2103 ARM_FEATURE_GENERIC_TIMER, 2104 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 2105 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 2106 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 2107 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 2108 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 2109 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 2110 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 2111 ARM_FEATURE_V8, 2112 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 2113 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 2114 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 2115 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 2116 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 2117 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 2118 ARM_FEATURE_PMU, /* has PMU support */ 2119 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 2120 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 2121 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 2122 ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ 2123 }; 2124 2125 static inline int arm_feature(CPUARMState *env, int feature) 2126 { 2127 return (env->features & (1ULL << feature)) != 0; 2128 } 2129 2130 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); 2131 2132 #if !defined(CONFIG_USER_ONLY) 2133 /* Return true if exception levels below EL3 are in secure state, 2134 * or would be following an exception return to that level. 2135 * Unlike arm_is_secure() (which is always a question about the 2136 * _current_ state of the CPU) this doesn't care about the current 2137 * EL or mode. 2138 */ 2139 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2140 { 2141 if (arm_feature(env, ARM_FEATURE_EL3)) { 2142 return !(env->cp15.scr_el3 & SCR_NS); 2143 } else { 2144 /* If EL3 is not supported then the secure state is implementation 2145 * defined, in which case QEMU defaults to non-secure. 2146 */ 2147 return false; 2148 } 2149 } 2150 2151 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 2152 static inline bool arm_is_el3_or_mon(CPUARMState *env) 2153 { 2154 if (arm_feature(env, ARM_FEATURE_EL3)) { 2155 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 2156 /* CPU currently in AArch64 state and EL3 */ 2157 return true; 2158 } else if (!is_a64(env) && 2159 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 2160 /* CPU currently in AArch32 state and monitor mode */ 2161 return true; 2162 } 2163 } 2164 return false; 2165 } 2166 2167 /* Return true if the processor is in secure state */ 2168 static inline bool arm_is_secure(CPUARMState *env) 2169 { 2170 if (arm_is_el3_or_mon(env)) { 2171 return true; 2172 } 2173 return arm_is_secure_below_el3(env); 2174 } 2175 2176 /* 2177 * Return true if the current security state has AArch64 EL2 or AArch32 Hyp. 2178 * This corresponds to the pseudocode EL2Enabled() 2179 */ 2180 static inline bool arm_is_el2_enabled(CPUARMState *env) 2181 { 2182 if (arm_feature(env, ARM_FEATURE_EL2)) { 2183 if (arm_is_secure_below_el3(env)) { 2184 return (env->cp15.scr_el3 & SCR_EEL2) != 0; 2185 } 2186 return true; 2187 } 2188 return false; 2189 } 2190 2191 #else 2192 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2193 { 2194 return false; 2195 } 2196 2197 static inline bool arm_is_secure(CPUARMState *env) 2198 { 2199 return false; 2200 } 2201 2202 static inline bool arm_is_el2_enabled(CPUARMState *env) 2203 { 2204 return false; 2205 } 2206 #endif 2207 2208 /** 2209 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 2210 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 2211 * "for all purposes other than a direct read or write access of HCR_EL2." 2212 * Not included here is HCR_RW. 2213 */ 2214 uint64_t arm_hcr_el2_eff(CPUARMState *env); 2215 2216 /* Return true if the specified exception level is running in AArch64 state. */ 2217 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 2218 { 2219 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 2220 * and if we're not in EL0 then the state of EL0 isn't well defined.) 2221 */ 2222 assert(el >= 1 && el <= 3); 2223 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 2224 2225 /* The highest exception level is always at the maximum supported 2226 * register width, and then lower levels have a register width controlled 2227 * by bits in the SCR or HCR registers. 2228 */ 2229 if (el == 3) { 2230 return aa64; 2231 } 2232 2233 if (arm_feature(env, ARM_FEATURE_EL3) && 2234 ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) { 2235 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 2236 } 2237 2238 if (el == 2) { 2239 return aa64; 2240 } 2241 2242 if (arm_is_el2_enabled(env)) { 2243 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 2244 } 2245 2246 return aa64; 2247 } 2248 2249 /* Function for determing whether guest cp register reads and writes should 2250 * access the secure or non-secure bank of a cp register. When EL3 is 2251 * operating in AArch32 state, the NS-bit determines whether the secure 2252 * instance of a cp register should be used. When EL3 is AArch64 (or if 2253 * it doesn't exist at all) then there is no register banking, and all 2254 * accesses are to the non-secure version. 2255 */ 2256 static inline bool access_secure_reg(CPUARMState *env) 2257 { 2258 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 2259 !arm_el_is_aa64(env, 3) && 2260 !(env->cp15.scr_el3 & SCR_NS)); 2261 2262 return ret; 2263 } 2264 2265 /* Macros for accessing a specified CP register bank */ 2266 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 2267 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 2268 2269 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 2270 do { \ 2271 if (_secure) { \ 2272 (_env)->cp15._regname##_s = (_val); \ 2273 } else { \ 2274 (_env)->cp15._regname##_ns = (_val); \ 2275 } \ 2276 } while (0) 2277 2278 /* Macros for automatically accessing a specific CP register bank depending on 2279 * the current secure state of the system. These macros are not intended for 2280 * supporting instruction translation reads/writes as these are dependent 2281 * solely on the SCR.NS bit and not the mode. 2282 */ 2283 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 2284 A32_BANKED_REG_GET((_env), _regname, \ 2285 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 2286 2287 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 2288 A32_BANKED_REG_SET((_env), _regname, \ 2289 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 2290 (_val)) 2291 2292 void arm_cpu_list(void); 2293 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 2294 uint32_t cur_el, bool secure); 2295 2296 /* Interface between CPU and Interrupt controller. */ 2297 #ifndef CONFIG_USER_ONLY 2298 bool armv7m_nvic_can_take_pending_exception(void *opaque); 2299 #else 2300 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) 2301 { 2302 return true; 2303 } 2304 #endif 2305 /** 2306 * armv7m_nvic_set_pending: mark the specified exception as pending 2307 * @opaque: the NVIC 2308 * @irq: the exception number to mark pending 2309 * @secure: false for non-banked exceptions or for the nonsecure 2310 * version of a banked exception, true for the secure version of a banked 2311 * exception. 2312 * 2313 * Marks the specified exception as pending. Note that we will assert() 2314 * if @secure is true and @irq does not specify one of the fixed set 2315 * of architecturally banked exceptions. 2316 */ 2317 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); 2318 /** 2319 * armv7m_nvic_set_pending_derived: mark this derived exception as pending 2320 * @opaque: the NVIC 2321 * @irq: the exception number to mark pending 2322 * @secure: false for non-banked exceptions or for the nonsecure 2323 * version of a banked exception, true for the secure version of a banked 2324 * exception. 2325 * 2326 * Similar to armv7m_nvic_set_pending(), but specifically for derived 2327 * exceptions (exceptions generated in the course of trying to take 2328 * a different exception). 2329 */ 2330 void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); 2331 /** 2332 * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending 2333 * @opaque: the NVIC 2334 * @irq: the exception number to mark pending 2335 * @secure: false for non-banked exceptions or for the nonsecure 2336 * version of a banked exception, true for the secure version of a banked 2337 * exception. 2338 * 2339 * Similar to armv7m_nvic_set_pending(), but specifically for exceptions 2340 * generated in the course of lazy stacking of FP registers. 2341 */ 2342 void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure); 2343 /** 2344 * armv7m_nvic_get_pending_irq_info: return highest priority pending 2345 * exception, and whether it targets Secure state 2346 * @opaque: the NVIC 2347 * @pirq: set to pending exception number 2348 * @ptargets_secure: set to whether pending exception targets Secure 2349 * 2350 * This function writes the number of the highest priority pending 2351 * exception (the one which would be made active by 2352 * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure 2353 * to true if the current highest priority pending exception should 2354 * be taken to Secure state, false for NS. 2355 */ 2356 void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq, 2357 bool *ptargets_secure); 2358 /** 2359 * armv7m_nvic_acknowledge_irq: make highest priority pending exception active 2360 * @opaque: the NVIC 2361 * 2362 * Move the current highest priority pending exception from the pending 2363 * state to the active state, and update v7m.exception to indicate that 2364 * it is the exception currently being handled. 2365 */ 2366 void armv7m_nvic_acknowledge_irq(void *opaque); 2367 /** 2368 * armv7m_nvic_complete_irq: complete specified interrupt or exception 2369 * @opaque: the NVIC 2370 * @irq: the exception number to complete 2371 * @secure: true if this exception was secure 2372 * 2373 * Returns: -1 if the irq was not active 2374 * 1 if completing this irq brought us back to base (no active irqs) 2375 * 0 if there is still an irq active after this one was completed 2376 * (Ignoring -1, this is the same as the RETTOBASE value before completion.) 2377 */ 2378 int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); 2379 /** 2380 * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) 2381 * @opaque: the NVIC 2382 * @irq: the exception number to mark pending 2383 * @secure: false for non-banked exceptions or for the nonsecure 2384 * version of a banked exception, true for the secure version of a banked 2385 * exception. 2386 * 2387 * Return whether an exception is "ready", i.e. whether the exception is 2388 * enabled and is configured at a priority which would allow it to 2389 * interrupt the current execution priority. This controls whether the 2390 * RDY bit for it in the FPCCR is set. 2391 */ 2392 bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure); 2393 /** 2394 * armv7m_nvic_raw_execution_priority: return the raw execution priority 2395 * @opaque: the NVIC 2396 * 2397 * Returns: the raw execution priority as defined by the v8M architecture. 2398 * This is the execution priority minus the effects of AIRCR.PRIS, 2399 * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. 2400 * (v8M ARM ARM I_PKLD.) 2401 */ 2402 int armv7m_nvic_raw_execution_priority(void *opaque); 2403 /** 2404 * armv7m_nvic_neg_prio_requested: return true if the requested execution 2405 * priority is negative for the specified security state. 2406 * @opaque: the NVIC 2407 * @secure: the security state to test 2408 * This corresponds to the pseudocode IsReqExecPriNeg(). 2409 */ 2410 #ifndef CONFIG_USER_ONLY 2411 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); 2412 #else 2413 static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) 2414 { 2415 return false; 2416 } 2417 #endif 2418 2419 /* Interface for defining coprocessor registers. 2420 * Registers are defined in tables of arm_cp_reginfo structs 2421 * which are passed to define_arm_cp_regs(). 2422 */ 2423 2424 /* When looking up a coprocessor register we look for it 2425 * via an integer which encodes all of: 2426 * coprocessor number 2427 * Crn, Crm, opc1, opc2 fields 2428 * 32 or 64 bit register (ie is it accessed via MRC/MCR 2429 * or via MRRC/MCRR?) 2430 * non-secure/secure bank (AArch32 only) 2431 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 2432 * (In this case crn and opc2 should be zero.) 2433 * For AArch64, there is no 32/64 bit size distinction; 2434 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 2435 * and 4 bit CRn and CRm. The encoding patterns are chosen 2436 * to be easy to convert to and from the KVM encodings, and also 2437 * so that the hashtable can contain both AArch32 and AArch64 2438 * registers (to allow for interprocessing where we might run 2439 * 32 bit code on a 64 bit core). 2440 */ 2441 /* This bit is private to our hashtable cpreg; in KVM register 2442 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 2443 * in the upper bits of the 64 bit ID. 2444 */ 2445 #define CP_REG_AA64_SHIFT 28 2446 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 2447 2448 /* To enable banking of coprocessor registers depending on ns-bit we 2449 * add a bit to distinguish between secure and non-secure cpregs in the 2450 * hashtable. 2451 */ 2452 #define CP_REG_NS_SHIFT 29 2453 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 2454 2455 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 2456 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 2457 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 2458 2459 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 2460 (CP_REG_AA64_MASK | \ 2461 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 2462 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 2463 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 2464 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 2465 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 2466 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 2467 2468 /* Convert a full 64 bit KVM register ID to the truncated 32 bit 2469 * version used as a key for the coprocessor register hashtable 2470 */ 2471 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 2472 { 2473 uint32_t cpregid = kvmid; 2474 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 2475 cpregid |= CP_REG_AA64_MASK; 2476 } else { 2477 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 2478 cpregid |= (1 << 15); 2479 } 2480 2481 /* KVM is always non-secure so add the NS flag on AArch32 register 2482 * entries. 2483 */ 2484 cpregid |= 1 << CP_REG_NS_SHIFT; 2485 } 2486 return cpregid; 2487 } 2488 2489 /* Convert a truncated 32 bit hashtable key into the full 2490 * 64 bit KVM register ID. 2491 */ 2492 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 2493 { 2494 uint64_t kvmid; 2495 2496 if (cpregid & CP_REG_AA64_MASK) { 2497 kvmid = cpregid & ~CP_REG_AA64_MASK; 2498 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 2499 } else { 2500 kvmid = cpregid & ~(1 << 15); 2501 if (cpregid & (1 << 15)) { 2502 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 2503 } else { 2504 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 2505 } 2506 } 2507 return kvmid; 2508 } 2509 2510 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a 2511 * special-behaviour cp reg and bits [11..8] indicate what behaviour 2512 * it has. Otherwise it is a simple cp reg, where CONST indicates that 2513 * TCG can assume the value to be constant (ie load at translate time) 2514 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END 2515 * indicates that the TB should not be ended after a write to this register 2516 * (the default is that the TB ends after cp writes). OVERRIDE permits 2517 * a register definition to override a previous definition for the 2518 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the 2519 * old must have the OVERRIDE bit set. 2520 * ALIAS indicates that this register is an alias view of some underlying 2521 * state which is also visible via another register, and that the other 2522 * register is handling migration and reset; registers marked ALIAS will not be 2523 * migrated but may have their state set by syncing of register state from KVM. 2524 * NO_RAW indicates that this register has no underlying state and does not 2525 * support raw access for state saving/loading; it will not be used for either 2526 * migration or KVM state synchronization. (Typically this is for "registers" 2527 * which are actually used as instructions for cache maintenance and so on.) 2528 * IO indicates that this register does I/O and therefore its accesses 2529 * need to be marked with gen_io_start() and also end the TB. In particular, 2530 * registers which implement clocks or timers require this. 2531 * RAISES_EXC is for when the read or write hook might raise an exception; 2532 * the generated code will synchronize the CPU state before calling the hook 2533 * so that it is safe for the hook to call raise_exception(). 2534 * NEWEL is for writes to registers that might change the exception 2535 * level - typically on older ARM chips. For those cases we need to 2536 * re-read the new el when recomputing the translation flags. 2537 */ 2538 #define ARM_CP_SPECIAL 0x0001 2539 #define ARM_CP_CONST 0x0002 2540 #define ARM_CP_64BIT 0x0004 2541 #define ARM_CP_SUPPRESS_TB_END 0x0008 2542 #define ARM_CP_OVERRIDE 0x0010 2543 #define ARM_CP_ALIAS 0x0020 2544 #define ARM_CP_IO 0x0040 2545 #define ARM_CP_NO_RAW 0x0080 2546 #define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100) 2547 #define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200) 2548 #define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) 2549 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) 2550 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) 2551 #define ARM_CP_DC_GVA (ARM_CP_SPECIAL | 0x0600) 2552 #define ARM_CP_DC_GZVA (ARM_CP_SPECIAL | 0x0700) 2553 #define ARM_LAST_SPECIAL ARM_CP_DC_GZVA 2554 #define ARM_CP_FPU 0x1000 2555 #define ARM_CP_SVE 0x2000 2556 #define ARM_CP_NO_GDB 0x4000 2557 #define ARM_CP_RAISES_EXC 0x8000 2558 #define ARM_CP_NEWEL 0x10000 2559 /* Used only as a terminator for ARMCPRegInfo lists */ 2560 #define ARM_CP_SENTINEL 0xfffff 2561 /* Mask of only the flag bits in a type field */ 2562 #define ARM_CP_FLAG_MASK 0x1f0ff 2563 2564 /* Valid values for ARMCPRegInfo state field, indicating which of 2565 * the AArch32 and AArch64 execution states this register is visible in. 2566 * If the reginfo doesn't explicitly specify then it is AArch32 only. 2567 * If the reginfo is declared to be visible in both states then a second 2568 * reginfo is synthesised for the AArch32 view of the AArch64 register, 2569 * such that the AArch32 view is the lower 32 bits of the AArch64 one. 2570 * Note that we rely on the values of these enums as we iterate through 2571 * the various states in some places. 2572 */ 2573 enum { 2574 ARM_CP_STATE_AA32 = 0, 2575 ARM_CP_STATE_AA64 = 1, 2576 ARM_CP_STATE_BOTH = 2, 2577 }; 2578 2579 /* ARM CP register secure state flags. These flags identify security state 2580 * attributes for a given CP register entry. 2581 * The existence of both or neither secure and non-secure flags indicates that 2582 * the register has both a secure and non-secure hash entry. A single one of 2583 * these flags causes the register to only be hashed for the specified 2584 * security state. 2585 * Although definitions may have any combination of the S/NS bits, each 2586 * registered entry will only have one to identify whether the entry is secure 2587 * or non-secure. 2588 */ 2589 enum { 2590 ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ 2591 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ 2592 }; 2593 2594 /* Return true if cptype is a valid type field. This is used to try to 2595 * catch errors where the sentinel has been accidentally left off the end 2596 * of a list of registers. 2597 */ 2598 static inline bool cptype_valid(int cptype) 2599 { 2600 return ((cptype & ~ARM_CP_FLAG_MASK) == 0) 2601 || ((cptype & ARM_CP_SPECIAL) && 2602 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); 2603 } 2604 2605 /* Access rights: 2606 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM 2607 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and 2608 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 2609 * (ie any of the privileged modes in Secure state, or Monitor mode). 2610 * If a register is accessible in one privilege level it's always accessible 2611 * in higher privilege levels too. Since "Secure PL1" also follows this rule 2612 * (ie anything visible in PL2 is visible in S-PL1, some things are only 2613 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the 2614 * terminology a little and call this PL3. 2615 * In AArch64 things are somewhat simpler as the PLx bits line up exactly 2616 * with the ELx exception levels. 2617 * 2618 * If access permissions for a register are more complex than can be 2619 * described with these bits, then use a laxer set of restrictions, and 2620 * do the more restrictive/complex check inside a helper function. 2621 */ 2622 #define PL3_R 0x80 2623 #define PL3_W 0x40 2624 #define PL2_R (0x20 | PL3_R) 2625 #define PL2_W (0x10 | PL3_W) 2626 #define PL1_R (0x08 | PL2_R) 2627 #define PL1_W (0x04 | PL2_W) 2628 #define PL0_R (0x02 | PL1_R) 2629 #define PL0_W (0x01 | PL1_W) 2630 2631 /* 2632 * For user-mode some registers are accessible to EL0 via a kernel 2633 * trap-and-emulate ABI. In this case we define the read permissions 2634 * as actually being PL0_R. However some bits of any given register 2635 * may still be masked. 2636 */ 2637 #ifdef CONFIG_USER_ONLY 2638 #define PL0U_R PL0_R 2639 #else 2640 #define PL0U_R PL1_R 2641 #endif 2642 2643 #define PL3_RW (PL3_R | PL3_W) 2644 #define PL2_RW (PL2_R | PL2_W) 2645 #define PL1_RW (PL1_R | PL1_W) 2646 #define PL0_RW (PL0_R | PL0_W) 2647 2648 /* Return the highest implemented Exception Level */ 2649 static inline int arm_highest_el(CPUARMState *env) 2650 { 2651 if (arm_feature(env, ARM_FEATURE_EL3)) { 2652 return 3; 2653 } 2654 if (arm_feature(env, ARM_FEATURE_EL2)) { 2655 return 2; 2656 } 2657 return 1; 2658 } 2659 2660 /* Return true if a v7M CPU is in Handler mode */ 2661 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2662 { 2663 return env->v7m.exception != 0; 2664 } 2665 2666 /* Return the current Exception Level (as per ARMv8; note that this differs 2667 * from the ARMv7 Privilege Level). 2668 */ 2669 static inline int arm_current_el(CPUARMState *env) 2670 { 2671 if (arm_feature(env, ARM_FEATURE_M)) { 2672 return arm_v7m_is_handler_mode(env) || 2673 !(env->v7m.control[env->v7m.secure] & 1); 2674 } 2675 2676 if (is_a64(env)) { 2677 return extract32(env->pstate, 2, 2); 2678 } 2679 2680 switch (env->uncached_cpsr & 0x1f) { 2681 case ARM_CPU_MODE_USR: 2682 return 0; 2683 case ARM_CPU_MODE_HYP: 2684 return 2; 2685 case ARM_CPU_MODE_MON: 2686 return 3; 2687 default: 2688 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2689 /* If EL3 is 32-bit then all secure privileged modes run in 2690 * EL3 2691 */ 2692 return 3; 2693 } 2694 2695 return 1; 2696 } 2697 } 2698 2699 typedef struct ARMCPRegInfo ARMCPRegInfo; 2700 2701 typedef enum CPAccessResult { 2702 /* Access is permitted */ 2703 CP_ACCESS_OK = 0, 2704 /* Access fails due to a configurable trap or enable which would 2705 * result in a categorized exception syndrome giving information about 2706 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, 2707 * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or 2708 * PL1 if in EL0, otherwise to the current EL). 2709 */ 2710 CP_ACCESS_TRAP = 1, 2711 /* Access fails and results in an exception syndrome 0x0 ("uncategorized"). 2712 * Note that this is not a catch-all case -- the set of cases which may 2713 * result in this failure is specifically defined by the architecture. 2714 */ 2715 CP_ACCESS_TRAP_UNCATEGORIZED = 2, 2716 /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ 2717 CP_ACCESS_TRAP_EL2 = 3, 2718 CP_ACCESS_TRAP_EL3 = 4, 2719 /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ 2720 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5, 2721 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6, 2722 /* Access fails and results in an exception syndrome for an FP access, 2723 * trapped directly to EL2 or EL3 2724 */ 2725 CP_ACCESS_TRAP_FP_EL2 = 7, 2726 CP_ACCESS_TRAP_FP_EL3 = 8, 2727 } CPAccessResult; 2728 2729 /* Access functions for coprocessor registers. These cannot fail and 2730 * may not raise exceptions. 2731 */ 2732 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); 2733 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, 2734 uint64_t value); 2735 /* Access permission check functions for coprocessor registers. */ 2736 typedef CPAccessResult CPAccessFn(CPUARMState *env, 2737 const ARMCPRegInfo *opaque, 2738 bool isread); 2739 /* Hook function for register reset */ 2740 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); 2741 2742 #define CP_ANY 0xff 2743 2744 /* Definition of an ARM coprocessor register */ 2745 struct ARMCPRegInfo { 2746 /* Name of register (useful mainly for debugging, need not be unique) */ 2747 const char *name; 2748 /* Location of register: coprocessor number and (crn,crm,opc1,opc2) 2749 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a 2750 * 'wildcard' field -- any value of that field in the MRC/MCR insn 2751 * will be decoded to this register. The register read and write 2752 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 2753 * used by the program, so it is possible to register a wildcard and 2754 * then behave differently on read/write if necessary. 2755 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 2756 * must both be zero. 2757 * For AArch64-visible registers, opc0 is also used. 2758 * Since there are no "coprocessors" in AArch64, cp is purely used as a 2759 * way to distinguish (for KVM's benefit) guest-visible system registers 2760 * from demuxed ones provided to preserve the "no side effects on 2761 * KVM register read/write from QEMU" semantics. cp==0x13 is guest 2762 * visible (to match KVM's encoding); cp==0 will be converted to 2763 * cp==0x13 when the ARMCPRegInfo is registered, for convenience. 2764 */ 2765 uint8_t cp; 2766 uint8_t crn; 2767 uint8_t crm; 2768 uint8_t opc0; 2769 uint8_t opc1; 2770 uint8_t opc2; 2771 /* Execution state in which this register is visible: ARM_CP_STATE_* */ 2772 int state; 2773 /* Register type: ARM_CP_* bits/values */ 2774 int type; 2775 /* Access rights: PL*_[RW] */ 2776 int access; 2777 /* Security state: ARM_CP_SECSTATE_* bits/values */ 2778 int secure; 2779 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when 2780 * this register was defined: can be used to hand data through to the 2781 * register read/write functions, since they are passed the ARMCPRegInfo*. 2782 */ 2783 void *opaque; 2784 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if 2785 * fieldoffset is non-zero, the reset value of the register. 2786 */ 2787 uint64_t resetvalue; 2788 /* Offset of the field in CPUARMState for this register. 2789 * 2790 * This is not needed if either: 2791 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs 2792 * 2. both readfn and writefn are specified 2793 */ 2794 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ 2795 2796 /* Offsets of the secure and non-secure fields in CPUARMState for the 2797 * register if it is banked. These fields are only used during the static 2798 * registration of a register. During hashing the bank associated 2799 * with a given security state is copied to fieldoffset which is used from 2800 * there on out. 2801 * 2802 * It is expected that register definitions use either fieldoffset or 2803 * bank_fieldoffsets in the definition but not both. It is also expected 2804 * that both bank offsets are set when defining a banked register. This 2805 * use indicates that a register is banked. 2806 */ 2807 ptrdiff_t bank_fieldoffsets[2]; 2808 2809 /* Function for making any access checks for this register in addition to 2810 * those specified by the 'access' permissions bits. If NULL, no extra 2811 * checks required. The access check is performed at runtime, not at 2812 * translate time. 2813 */ 2814 CPAccessFn *accessfn; 2815 /* Function for handling reads of this register. If NULL, then reads 2816 * will be done by loading from the offset into CPUARMState specified 2817 * by fieldoffset. 2818 */ 2819 CPReadFn *readfn; 2820 /* Function for handling writes of this register. If NULL, then writes 2821 * will be done by writing to the offset into CPUARMState specified 2822 * by fieldoffset. 2823 */ 2824 CPWriteFn *writefn; 2825 /* Function for doing a "raw" read; used when we need to copy 2826 * coprocessor state to the kernel for KVM or out for 2827 * migration. This only needs to be provided if there is also a 2828 * readfn and it has side effects (for instance clear-on-read bits). 2829 */ 2830 CPReadFn *raw_readfn; 2831 /* Function for doing a "raw" write; used when we need to copy KVM 2832 * kernel coprocessor state into userspace, or for inbound 2833 * migration. This only needs to be provided if there is also a 2834 * writefn and it masks out "unwritable" bits or has write-one-to-clear 2835 * or similar behaviour. 2836 */ 2837 CPWriteFn *raw_writefn; 2838 /* Function for resetting the register. If NULL, then reset will be done 2839 * by writing resetvalue to the field specified in fieldoffset. If 2840 * fieldoffset is 0 then no reset will be done. 2841 */ 2842 CPResetFn *resetfn; 2843 2844 /* 2845 * "Original" writefn and readfn. 2846 * For ARMv8.1-VHE register aliases, we overwrite the read/write 2847 * accessor functions of various EL1/EL0 to perform the runtime 2848 * check for which sysreg should actually be modified, and then 2849 * forwards the operation. Before overwriting the accessors, 2850 * the original function is copied here, so that accesses that 2851 * really do go to the EL1/EL0 version proceed normally. 2852 * (The corresponding EL2 register is linked via opaque.) 2853 */ 2854 CPReadFn *orig_readfn; 2855 CPWriteFn *orig_writefn; 2856 }; 2857 2858 /* Macros which are lvalues for the field in CPUARMState for the 2859 * ARMCPRegInfo *ri. 2860 */ 2861 #define CPREG_FIELD32(env, ri) \ 2862 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) 2863 #define CPREG_FIELD64(env, ri) \ 2864 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) 2865 2866 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } 2867 2868 void define_arm_cp_regs_with_opaque(ARMCPU *cpu, 2869 const ARMCPRegInfo *regs, void *opaque); 2870 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, 2871 const ARMCPRegInfo *regs, void *opaque); 2872 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) 2873 { 2874 define_arm_cp_regs_with_opaque(cpu, regs, 0); 2875 } 2876 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) 2877 { 2878 define_one_arm_cp_reg_with_opaque(cpu, regs, 0); 2879 } 2880 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); 2881 2882 /* 2883 * Definition of an ARM co-processor register as viewed from 2884 * userspace. This is used for presenting sanitised versions of 2885 * registers to userspace when emulating the Linux AArch64 CPU 2886 * ID/feature ABI (advertised as HWCAP_CPUID). 2887 */ 2888 typedef struct ARMCPRegUserSpaceInfo { 2889 /* Name of register */ 2890 const char *name; 2891 2892 /* Is the name actually a glob pattern */ 2893 bool is_glob; 2894 2895 /* Only some bits are exported to user space */ 2896 uint64_t exported_bits; 2897 2898 /* Fixed bits are applied after the mask */ 2899 uint64_t fixed_bits; 2900 } ARMCPRegUserSpaceInfo; 2901 2902 #define REGUSERINFO_SENTINEL { .name = NULL } 2903 2904 void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods); 2905 2906 /* CPWriteFn that can be used to implement writes-ignored behaviour */ 2907 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, 2908 uint64_t value); 2909 /* CPReadFn that can be used for read-as-zero behaviour */ 2910 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); 2911 2912 /* CPResetFn that does nothing, for use if no reset is required even 2913 * if fieldoffset is non zero. 2914 */ 2915 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); 2916 2917 /* Return true if this reginfo struct's field in the cpu state struct 2918 * is 64 bits wide. 2919 */ 2920 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) 2921 { 2922 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT); 2923 } 2924 2925 static inline bool cp_access_ok(int current_el, 2926 const ARMCPRegInfo *ri, int isread) 2927 { 2928 return (ri->access >> ((current_el * 2) + isread)) & 1; 2929 } 2930 2931 /* Raw read of a coprocessor register (as needed for migration, etc) */ 2932 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); 2933 2934 /** 2935 * write_list_to_cpustate 2936 * @cpu: ARMCPU 2937 * 2938 * For each register listed in the ARMCPU cpreg_indexes list, write 2939 * its value from the cpreg_values list into the ARMCPUState structure. 2940 * This updates TCG's working data structures from KVM data or 2941 * from incoming migration state. 2942 * 2943 * Returns: true if all register values were updated correctly, 2944 * false if some register was unknown or could not be written. 2945 * Note that we do not stop early on failure -- we will attempt 2946 * writing all registers in the list. 2947 */ 2948 bool write_list_to_cpustate(ARMCPU *cpu); 2949 2950 /** 2951 * write_cpustate_to_list: 2952 * @cpu: ARMCPU 2953 * @kvm_sync: true if this is for syncing back to KVM 2954 * 2955 * For each register listed in the ARMCPU cpreg_indexes list, write 2956 * its value from the ARMCPUState structure into the cpreg_values list. 2957 * This is used to copy info from TCG's working data structures into 2958 * KVM or for outbound migration. 2959 * 2960 * @kvm_sync is true if we are doing this in order to sync the 2961 * register state back to KVM. In this case we will only update 2962 * values in the list if the previous list->cpustate sync actually 2963 * successfully wrote the CPU state. Otherwise we will keep the value 2964 * that is in the list. 2965 * 2966 * Returns: true if all register values were read correctly, 2967 * false if some register was unknown or could not be read. 2968 * Note that we do not stop early on failure -- we will attempt 2969 * reading all registers in the list. 2970 */ 2971 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); 2972 2973 #define ARM_CPUID_TI915T 0x54029152 2974 #define ARM_CPUID_TI925T 0x54029252 2975 2976 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU 2977 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) 2978 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2979 2980 #define cpu_signal_handler cpu_arm_signal_handler 2981 #define cpu_list arm_cpu_list 2982 2983 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2984 * 2985 * If EL3 is 64-bit: 2986 * + NonSecure EL1 & 0 stage 1 2987 * + NonSecure EL1 & 0 stage 2 2988 * + NonSecure EL2 2989 * + NonSecure EL2 & 0 (ARMv8.1-VHE) 2990 * + Secure EL1 & 0 2991 * + Secure EL3 2992 * If EL3 is 32-bit: 2993 * + NonSecure PL1 & 0 stage 1 2994 * + NonSecure PL1 & 0 stage 2 2995 * + NonSecure PL2 2996 * + Secure PL0 2997 * + Secure PL1 2998 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2999 * 3000 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 3001 * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes, 3002 * because they may differ in access permissions even if the VA->PA map is 3003 * the same 3004 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 3005 * translation, which means that we have one mmu_idx that deals with two 3006 * concatenated translation regimes [this sort of combined s1+2 TLB is 3007 * architecturally permitted] 3008 * 3. we don't need to allocate an mmu_idx to translations that we won't be 3009 * handling via the TLB. The only way to do a stage 1 translation without 3010 * the immediate stage 2 translation is via the ATS or AT system insns, 3011 * which can be slow-pathed and always do a page table walk. 3012 * The only use of stage 2 translations is either as part of an s1+2 3013 * lookup or when loading the descriptors during a stage 1 page table walk, 3014 * and in both those cases we don't use the TLB. 3015 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 3016 * translation regimes, because they map reasonably well to each other 3017 * and they can't both be active at the same time. 3018 * 5. we want to be able to use the TLB for accesses done as part of a 3019 * stage1 page table walk, rather than having to walk the stage2 page 3020 * table over and over. 3021 * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access 3022 * Never (PAN) bit within PSTATE. 3023 * 3024 * This gives us the following list of cases: 3025 * 3026 * NS EL0 EL1&0 stage 1+2 (aka NS PL0) 3027 * NS EL1 EL1&0 stage 1+2 (aka NS PL1) 3028 * NS EL1 EL1&0 stage 1+2 +PAN 3029 * NS EL0 EL2&0 3030 * NS EL2 EL2&0 3031 * NS EL2 EL2&0 +PAN 3032 * NS EL2 (aka NS PL2) 3033 * S EL0 EL1&0 (aka S PL0) 3034 * S EL1 EL1&0 (not used if EL3 is 32 bit) 3035 * S EL1 EL1&0 +PAN 3036 * S EL3 (aka S PL1) 3037 * 3038 * for a total of 11 different mmu_idx. 3039 * 3040 * R profile CPUs have an MPU, but can use the same set of MMU indexes 3041 * as A profile. They only need to distinguish NS EL0 and NS EL1 (and 3042 * NS EL2 if we ever model a Cortex-R52). 3043 * 3044 * M profile CPUs are rather different as they do not have a true MMU. 3045 * They have the following different MMU indexes: 3046 * User 3047 * Privileged 3048 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 3049 * Privileged, execution priority negative (ditto) 3050 * If the CPU supports the v8M Security Extension then there are also: 3051 * Secure User 3052 * Secure Privileged 3053 * Secure User, execution priority negative 3054 * Secure Privileged, execution priority negative 3055 * 3056 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 3057 * are not quite the same -- different CPU types (most notably M profile 3058 * vs A/R profile) would like to use MMU indexes with different semantics, 3059 * but since we don't ever need to use all of those in a single CPU we 3060 * can avoid having to set NB_MMU_MODES to "total number of A profile MMU 3061 * modes + total number of M profile MMU modes". The lower bits of 3062 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 3063 * the same for any particular CPU. 3064 * Variables of type ARMMUIdx are always full values, and the core 3065 * index values are in variables of type 'int'. 3066 * 3067 * Our enumeration includes at the end some entries which are not "true" 3068 * mmu_idx values in that they don't have corresponding TLBs and are only 3069 * valid for doing slow path page table walks. 3070 * 3071 * The constant names here are patterned after the general style of the names 3072 * of the AT/ATS operations. 3073 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 3074 * For M profile we arrange them to have a bit for priv, a bit for negpri 3075 * and a bit for secure. 3076 */ 3077 #define ARM_MMU_IDX_A 0x10 /* A profile */ 3078 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 3079 #define ARM_MMU_IDX_M 0x40 /* M profile */ 3080 3081 /* Meanings of the bits for A profile mmu idx values */ 3082 #define ARM_MMU_IDX_A_NS 0x8 3083 3084 /* Meanings of the bits for M profile mmu idx values */ 3085 #define ARM_MMU_IDX_M_PRIV 0x1 3086 #define ARM_MMU_IDX_M_NEGPRI 0x2 3087 #define ARM_MMU_IDX_M_S 0x4 /* Secure */ 3088 3089 #define ARM_MMU_IDX_TYPE_MASK \ 3090 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB) 3091 #define ARM_MMU_IDX_COREIDX_MASK 0xf 3092 3093 typedef enum ARMMMUIdx { 3094 /* 3095 * A-profile. 3096 */ 3097 ARMMMUIdx_SE10_0 = 0 | ARM_MMU_IDX_A, 3098 ARMMMUIdx_SE20_0 = 1 | ARM_MMU_IDX_A, 3099 ARMMMUIdx_SE10_1 = 2 | ARM_MMU_IDX_A, 3100 ARMMMUIdx_SE20_2 = 3 | ARM_MMU_IDX_A, 3101 ARMMMUIdx_SE10_1_PAN = 4 | ARM_MMU_IDX_A, 3102 ARMMMUIdx_SE20_2_PAN = 5 | ARM_MMU_IDX_A, 3103 ARMMMUIdx_SE2 = 6 | ARM_MMU_IDX_A, 3104 ARMMMUIdx_SE3 = 7 | ARM_MMU_IDX_A, 3105 3106 ARMMMUIdx_E10_0 = ARMMMUIdx_SE10_0 | ARM_MMU_IDX_A_NS, 3107 ARMMMUIdx_E20_0 = ARMMMUIdx_SE20_0 | ARM_MMU_IDX_A_NS, 3108 ARMMMUIdx_E10_1 = ARMMMUIdx_SE10_1 | ARM_MMU_IDX_A_NS, 3109 ARMMMUIdx_E20_2 = ARMMMUIdx_SE20_2 | ARM_MMU_IDX_A_NS, 3110 ARMMMUIdx_E10_1_PAN = ARMMMUIdx_SE10_1_PAN | ARM_MMU_IDX_A_NS, 3111 ARMMMUIdx_E20_2_PAN = ARMMMUIdx_SE20_2_PAN | ARM_MMU_IDX_A_NS, 3112 ARMMMUIdx_E2 = ARMMMUIdx_SE2 | ARM_MMU_IDX_A_NS, 3113 3114 /* 3115 * These are not allocated TLBs and are used only for AT system 3116 * instructions or for the first stage of an S12 page table walk. 3117 */ 3118 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, 3119 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, 3120 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB, 3121 ARMMMUIdx_Stage1_SE0 = 3 | ARM_MMU_IDX_NOTLB, 3122 ARMMMUIdx_Stage1_SE1 = 4 | ARM_MMU_IDX_NOTLB, 3123 ARMMMUIdx_Stage1_SE1_PAN = 5 | ARM_MMU_IDX_NOTLB, 3124 /* 3125 * Not allocated a TLB: used only for second stage of an S12 page 3126 * table walk, or for descriptor loads during first stage of an S1 3127 * page table walk. Note that if we ever want to have a TLB for this 3128 * then various TLB flush insns which currently are no-ops or flush 3129 * only stage 1 MMU indexes will need to change to flush stage 2. 3130 */ 3131 ARMMMUIdx_Stage2 = 6 | ARM_MMU_IDX_NOTLB, 3132 ARMMMUIdx_Stage2_S = 7 | ARM_MMU_IDX_NOTLB, 3133 3134 /* 3135 * M-profile. 3136 */ 3137 ARMMMUIdx_MUser = ARM_MMU_IDX_M, 3138 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV, 3139 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI, 3140 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI, 3141 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S, 3142 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S, 3143 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S, 3144 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S, 3145 } ARMMMUIdx; 3146 3147 /* 3148 * Bit macros for the core-mmu-index values for each index, 3149 * for use when calling tlb_flush_by_mmuidx() and friends. 3150 */ 3151 #define TO_CORE_BIT(NAME) \ 3152 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK) 3153 3154 typedef enum ARMMMUIdxBit { 3155 TO_CORE_BIT(E10_0), 3156 TO_CORE_BIT(E20_0), 3157 TO_CORE_BIT(E10_1), 3158 TO_CORE_BIT(E10_1_PAN), 3159 TO_CORE_BIT(E2), 3160 TO_CORE_BIT(E20_2), 3161 TO_CORE_BIT(E20_2_PAN), 3162 TO_CORE_BIT(SE10_0), 3163 TO_CORE_BIT(SE20_0), 3164 TO_CORE_BIT(SE10_1), 3165 TO_CORE_BIT(SE20_2), 3166 TO_CORE_BIT(SE10_1_PAN), 3167 TO_CORE_BIT(SE20_2_PAN), 3168 TO_CORE_BIT(SE2), 3169 TO_CORE_BIT(SE3), 3170 3171 TO_CORE_BIT(MUser), 3172 TO_CORE_BIT(MPriv), 3173 TO_CORE_BIT(MUserNegPri), 3174 TO_CORE_BIT(MPrivNegPri), 3175 TO_CORE_BIT(MSUser), 3176 TO_CORE_BIT(MSPriv), 3177 TO_CORE_BIT(MSUserNegPri), 3178 TO_CORE_BIT(MSPrivNegPri), 3179 } ARMMMUIdxBit; 3180 3181 #undef TO_CORE_BIT 3182 3183 #define MMU_USER_IDX 0 3184 3185 /* Indexes used when registering address spaces with cpu_address_space_init */ 3186 typedef enum ARMASIdx { 3187 ARMASIdx_NS = 0, 3188 ARMASIdx_S = 1, 3189 ARMASIdx_TagNS = 2, 3190 ARMASIdx_TagS = 3, 3191 } ARMASIdx; 3192 3193 /* Return the Exception Level targeted by debug exceptions. */ 3194 static inline int arm_debug_target_el(CPUARMState *env) 3195 { 3196 bool secure = arm_is_secure(env); 3197 bool route_to_el2 = false; 3198 3199 if (arm_is_el2_enabled(env)) { 3200 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || 3201 env->cp15.mdcr_el2 & MDCR_TDE; 3202 } 3203 3204 if (route_to_el2) { 3205 return 2; 3206 } else if (arm_feature(env, ARM_FEATURE_EL3) && 3207 !arm_el_is_aa64(env, 3) && secure) { 3208 return 3; 3209 } else { 3210 return 1; 3211 } 3212 } 3213 3214 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 3215 { 3216 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 3217 * CSSELR is RAZ/WI. 3218 */ 3219 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 3220 } 3221 3222 /* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */ 3223 static inline bool aa64_generate_debug_exceptions(CPUARMState *env) 3224 { 3225 int cur_el = arm_current_el(env); 3226 int debug_el; 3227 3228 if (cur_el == 3) { 3229 return false; 3230 } 3231 3232 /* MDCR_EL3.SDD disables debug events from Secure state */ 3233 if (arm_is_secure_below_el3(env) 3234 && extract32(env->cp15.mdcr_el3, 16, 1)) { 3235 return false; 3236 } 3237 3238 /* 3239 * Same EL to same EL debug exceptions need MDSCR_KDE enabled 3240 * while not masking the (D)ebug bit in DAIF. 3241 */ 3242 debug_el = arm_debug_target_el(env); 3243 3244 if (cur_el == debug_el) { 3245 return extract32(env->cp15.mdscr_el1, 13, 1) 3246 && !(env->daif & PSTATE_D); 3247 } 3248 3249 /* Otherwise the debug target needs to be a higher EL */ 3250 return debug_el > cur_el; 3251 } 3252 3253 static inline bool aa32_generate_debug_exceptions(CPUARMState *env) 3254 { 3255 int el = arm_current_el(env); 3256 3257 if (el == 0 && arm_el_is_aa64(env, 1)) { 3258 return aa64_generate_debug_exceptions(env); 3259 } 3260 3261 if (arm_is_secure(env)) { 3262 int spd; 3263 3264 if (el == 0 && (env->cp15.sder & 1)) { 3265 /* SDER.SUIDEN means debug exceptions from Secure EL0 3266 * are always enabled. Otherwise they are controlled by 3267 * SDCR.SPD like those from other Secure ELs. 3268 */ 3269 return true; 3270 } 3271 3272 spd = extract32(env->cp15.mdcr_el3, 14, 2); 3273 switch (spd) { 3274 case 1: 3275 /* SPD == 0b01 is reserved, but behaves as 0b00. */ 3276 case 0: 3277 /* For 0b00 we return true if external secure invasive debug 3278 * is enabled. On real hardware this is controlled by external 3279 * signals to the core. QEMU always permits debug, and behaves 3280 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. 3281 */ 3282 return true; 3283 case 2: 3284 return false; 3285 case 3: 3286 return true; 3287 } 3288 } 3289 3290 return el != 2; 3291 } 3292 3293 /* Return true if debugging exceptions are currently enabled. 3294 * This corresponds to what in ARM ARM pseudocode would be 3295 * if UsingAArch32() then 3296 * return AArch32.GenerateDebugExceptions() 3297 * else 3298 * return AArch64.GenerateDebugExceptions() 3299 * We choose to push the if() down into this function for clarity, 3300 * since the pseudocode has it at all callsites except for the one in 3301 * CheckSoftwareStep(), where it is elided because both branches would 3302 * always return the same value. 3303 */ 3304 static inline bool arm_generate_debug_exceptions(CPUARMState *env) 3305 { 3306 if (env->aarch64) { 3307 return aa64_generate_debug_exceptions(env); 3308 } else { 3309 return aa32_generate_debug_exceptions(env); 3310 } 3311 } 3312 3313 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check 3314 * implicitly means this always returns false in pre-v8 CPUs.) 3315 */ 3316 static inline bool arm_singlestep_active(CPUARMState *env) 3317 { 3318 return extract32(env->cp15.mdscr_el1, 0, 1) 3319 && arm_el_is_aa64(env, arm_debug_target_el(env)) 3320 && arm_generate_debug_exceptions(env); 3321 } 3322 3323 static inline bool arm_sctlr_b(CPUARMState *env) 3324 { 3325 return 3326 /* We need not implement SCTLR.ITD in user-mode emulation, so 3327 * let linux-user ignore the fact that it conflicts with SCTLR_B. 3328 * This lets people run BE32 binaries with "-cpu any". 3329 */ 3330 #ifndef CONFIG_USER_ONLY 3331 !arm_feature(env, ARM_FEATURE_V7) && 3332 #endif 3333 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 3334 } 3335 3336 uint64_t arm_sctlr(CPUARMState *env, int el); 3337 3338 static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, 3339 bool sctlr_b) 3340 { 3341 #ifdef CONFIG_USER_ONLY 3342 /* 3343 * In system mode, BE32 is modelled in line with the 3344 * architecture (as word-invariant big-endianness), where loads 3345 * and stores are done little endian but from addresses which 3346 * are adjusted by XORing with the appropriate constant. So the 3347 * endianness to use for the raw data access is not affected by 3348 * SCTLR.B. 3349 * In user mode, however, we model BE32 as byte-invariant 3350 * big-endianness (because user-only code cannot tell the 3351 * difference), and so we need to use a data access endianness 3352 * that depends on SCTLR.B. 3353 */ 3354 if (sctlr_b) { 3355 return true; 3356 } 3357 #endif 3358 /* In 32bit endianness is determined by looking at CPSR's E bit */ 3359 return env->uncached_cpsr & CPSR_E; 3360 } 3361 3362 static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr) 3363 { 3364 return sctlr & (el ? SCTLR_EE : SCTLR_E0E); 3365 } 3366 3367 /* Return true if the processor is in big-endian mode. */ 3368 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 3369 { 3370 if (!is_a64(env)) { 3371 return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); 3372 } else { 3373 int cur_el = arm_current_el(env); 3374 uint64_t sctlr = arm_sctlr(env, cur_el); 3375 return arm_cpu_data_is_big_endian_a64(cur_el, sctlr); 3376 } 3377 } 3378 3379 typedef CPUARMState CPUArchState; 3380 typedef ARMCPU ArchCPU; 3381 3382 #include "exec/cpu-all.h" 3383 3384 /* 3385 * We have more than 32-bits worth of state per TB, so we split the data 3386 * between tb->flags and tb->cs_base, which is otherwise unused for ARM. 3387 * We collect these two parts in CPUARMTBFlags where they are named 3388 * flags and flags2 respectively. 3389 * 3390 * The flags that are shared between all execution modes, TBFLAG_ANY, 3391 * are stored in flags. The flags that are specific to a given mode 3392 * are stores in flags2. Since cs_base is sized on the configured 3393 * address size, flags2 always has 64-bits for A64, and a minimum of 3394 * 32-bits for A32 and M32. 3395 * 3396 * The bits for 32-bit A-profile and M-profile partially overlap: 3397 * 3398 * 31 23 11 10 0 3399 * +-------------+----------+----------------+ 3400 * | | | TBFLAG_A32 | 3401 * | TBFLAG_AM32 | +-----+----------+ 3402 * | | |TBFLAG_M32| 3403 * +-------------+----------------+----------+ 3404 * 31 23 5 4 0 3405 * 3406 * Unless otherwise noted, these bits are cached in env->hflags. 3407 */ 3408 FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1) 3409 FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1) 3410 FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1) /* Not cached. */ 3411 FIELD(TBFLAG_ANY, BE_DATA, 3, 1) 3412 FIELD(TBFLAG_ANY, MMUIDX, 4, 4) 3413 /* Target EL if we take a floating-point-disabled exception */ 3414 FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) 3415 /* For A-profile only, target EL for debug exceptions. */ 3416 FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 10, 2) 3417 /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ 3418 FIELD(TBFLAG_ANY, ALIGN_MEM, 12, 1) 3419 3420 /* 3421 * Bit usage when in AArch32 state, both A- and M-profile. 3422 */ 3423 FIELD(TBFLAG_AM32, CONDEXEC, 24, 8) /* Not cached. */ 3424 FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cached. */ 3425 3426 /* 3427 * Bit usage when in AArch32 state, for A-profile only. 3428 */ 3429 FIELD(TBFLAG_A32, VECLEN, 0, 3) /* Not cached. */ 3430 FIELD(TBFLAG_A32, VECSTRIDE, 3, 2) /* Not cached. */ 3431 /* 3432 * We store the bottom two bits of the CPAR as TB flags and handle 3433 * checks on the other bits at runtime. This shares the same bits as 3434 * VECSTRIDE, which is OK as no XScale CPU has VFP. 3435 * Not cached, because VECLEN+VECSTRIDE are not cached. 3436 */ 3437 FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2) 3438 FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ 3439 FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */ 3440 FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1) 3441 /* 3442 * Indicates whether cp register reads and writes by guest code should access 3443 * the secure or nonsecure bank of banked registers; note that this is not 3444 * the same thing as the current security state of the processor! 3445 */ 3446 FIELD(TBFLAG_A32, NS, 10, 1) 3447 3448 /* 3449 * Bit usage when in AArch32 state, for M-profile only. 3450 */ 3451 /* Handler (ie not Thread) mode */ 3452 FIELD(TBFLAG_M32, HANDLER, 0, 1) 3453 /* Whether we should generate stack-limit checks */ 3454 FIELD(TBFLAG_M32, STACKCHECK, 1, 1) 3455 /* Set if FPCCR.LSPACT is set */ 3456 FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */ 3457 /* Set if we must create a new FP context */ 3458 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */ 3459 /* Set if FPCCR.S does not match current security state */ 3460 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */ 3461 3462 /* 3463 * Bit usage when in AArch64 state 3464 */ 3465 FIELD(TBFLAG_A64, TBII, 0, 2) 3466 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3467 FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) 3468 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3469 FIELD(TBFLAG_A64, BT, 9, 1) 3470 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ 3471 FIELD(TBFLAG_A64, TBID, 12, 2) 3472 FIELD(TBFLAG_A64, UNPRIV, 14, 1) 3473 FIELD(TBFLAG_A64, ATA, 15, 1) 3474 FIELD(TBFLAG_A64, TCMA, 16, 2) 3475 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) 3476 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) 3477 3478 /* 3479 * Helpers for using the above. 3480 */ 3481 #define DP_TBFLAG_ANY(DST, WHICH, VAL) \ 3482 (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL)) 3483 #define DP_TBFLAG_A64(DST, WHICH, VAL) \ 3484 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A64, WHICH, VAL)) 3485 #define DP_TBFLAG_A32(DST, WHICH, VAL) \ 3486 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL)) 3487 #define DP_TBFLAG_M32(DST, WHICH, VAL) \ 3488 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL)) 3489 #define DP_TBFLAG_AM32(DST, WHICH, VAL) \ 3490 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL)) 3491 3492 #define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH) 3493 #define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A64, WHICH) 3494 #define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH) 3495 #define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH) 3496 #define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH) 3497 3498 /** 3499 * cpu_mmu_index: 3500 * @env: The cpu environment 3501 * @ifetch: True for code access, false for data access. 3502 * 3503 * Return the core mmu index for the current translation regime. 3504 * This function is used by generic TCG code paths. 3505 */ 3506 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) 3507 { 3508 return EX_TBFLAG_ANY(env->hflags, MMUIDX); 3509 } 3510 3511 static inline bool bswap_code(bool sctlr_b) 3512 { 3513 #ifdef CONFIG_USER_ONLY 3514 /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian. 3515 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0 3516 * would also end up as a mixed-endian mode with BE code, LE data. 3517 */ 3518 return 3519 #ifdef TARGET_WORDS_BIGENDIAN 3520 1 ^ 3521 #endif 3522 sctlr_b; 3523 #else 3524 /* All code access in ARM is little endian, and there are no loaders 3525 * doing swaps that need to be reversed 3526 */ 3527 return 0; 3528 #endif 3529 } 3530 3531 #ifdef CONFIG_USER_ONLY 3532 static inline bool arm_cpu_bswap_data(CPUARMState *env) 3533 { 3534 return 3535 #ifdef TARGET_WORDS_BIGENDIAN 3536 1 ^ 3537 #endif 3538 arm_cpu_data_is_big_endian(env); 3539 } 3540 #endif 3541 3542 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 3543 target_ulong *cs_base, uint32_t *flags); 3544 3545 enum { 3546 QEMU_PSCI_CONDUIT_DISABLED = 0, 3547 QEMU_PSCI_CONDUIT_SMC = 1, 3548 QEMU_PSCI_CONDUIT_HVC = 2, 3549 }; 3550 3551 #ifndef CONFIG_USER_ONLY 3552 /* Return the address space index to use for a memory access */ 3553 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3554 { 3555 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3556 } 3557 3558 /* Return the AddressSpace to use for a memory access 3559 * (which depends on whether the access is S or NS, and whether 3560 * the board gave us a separate AddressSpace for S accesses). 3561 */ 3562 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3563 { 3564 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3565 } 3566 #endif 3567 3568 /** 3569 * arm_register_pre_el_change_hook: 3570 * Register a hook function which will be called immediately before this 3571 * CPU changes exception level or mode. The hook function will be 3572 * passed a pointer to the ARMCPU and the opaque data pointer passed 3573 * to this function when the hook was registered. 3574 * 3575 * Note that if a pre-change hook is called, any registered post-change hooks 3576 * are guaranteed to subsequently be called. 3577 */ 3578 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3579 void *opaque); 3580 /** 3581 * arm_register_el_change_hook: 3582 * Register a hook function which will be called immediately after this 3583 * CPU changes exception level or mode. The hook function will be 3584 * passed a pointer to the ARMCPU and the opaque data pointer passed 3585 * to this function when the hook was registered. 3586 * 3587 * Note that any registered hooks registered here are guaranteed to be called 3588 * if pre-change hooks have been. 3589 */ 3590 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3591 *opaque); 3592 3593 /** 3594 * arm_rebuild_hflags: 3595 * Rebuild the cached TBFLAGS for arbitrary changed processor state. 3596 */ 3597 void arm_rebuild_hflags(CPUARMState *env); 3598 3599 /** 3600 * aa32_vfp_dreg: 3601 * Return a pointer to the Dn register within env in 32-bit mode. 3602 */ 3603 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3604 { 3605 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3606 } 3607 3608 /** 3609 * aa32_vfp_qreg: 3610 * Return a pointer to the Qn register within env in 32-bit mode. 3611 */ 3612 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3613 { 3614 return &env->vfp.zregs[regno].d[0]; 3615 } 3616 3617 /** 3618 * aa64_vfp_qreg: 3619 * Return a pointer to the Qn register within env in 64-bit mode. 3620 */ 3621 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3622 { 3623 return &env->vfp.zregs[regno].d[0]; 3624 } 3625 3626 /* Shared between translate-sve.c and sve_helper.c. */ 3627 extern const uint64_t pred_esz_masks[4]; 3628 3629 /* Helper for the macros below, validating the argument type. */ 3630 static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x) 3631 { 3632 return x; 3633 } 3634 3635 /* 3636 * Lvalue macros for ARM TLB bits that we must cache in the TCG TLB. 3637 * Using these should be a bit more self-documenting than using the 3638 * generic target bits directly. 3639 */ 3640 #define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0) 3641 #define arm_tlb_mte_tagged(x) (typecheck_memtxattrs(x)->target_tlb_bit1) 3642 3643 /* 3644 * AArch64 usage of the PAGE_TARGET_* bits for linux-user. 3645 */ 3646 #define PAGE_BTI PAGE_TARGET_1 3647 #define PAGE_MTE PAGE_TARGET_2 3648 3649 #ifdef TARGET_TAGGED_ADDRESSES 3650 /** 3651 * cpu_untagged_addr: 3652 * @cs: CPU context 3653 * @x: tagged address 3654 * 3655 * Remove any address tag from @x. This is explicitly related to the 3656 * linux syscall TIF_TAGGED_ADDR setting, not TBI in general. 3657 * 3658 * There should be a better place to put this, but we need this in 3659 * include/exec/cpu_ldst.h, and not some place linux-user specific. 3660 */ 3661 static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x) 3662 { 3663 ARMCPU *cpu = ARM_CPU(cs); 3664 if (cpu->env.tagged_addr_enable) { 3665 /* 3666 * TBI is enabled for userspace but not kernelspace addresses. 3667 * Only clear the tag if bit 55 is clear. 3668 */ 3669 x &= sextract64(x, 0, 56); 3670 } 3671 return x; 3672 } 3673 #endif 3674 3675 /* 3676 * Naming convention for isar_feature functions: 3677 * Functions which test 32-bit ID registers should have _aa32_ in 3678 * their name. Functions which test 64-bit ID registers should have 3679 * _aa64_ in their name. These must only be used in code where we 3680 * know for certain that the CPU has AArch32 or AArch64 respectively 3681 * or where the correct answer for a CPU which doesn't implement that 3682 * CPU state is "false" (eg when generating A32 or A64 code, if adding 3683 * system registers that are specific to that CPU state, for "should 3684 * we let this system register bit be set" tests where the 32-bit 3685 * flavour of the register doesn't have the bit, and so on). 3686 * Functions which simply ask "does this feature exist at all" have 3687 * _any_ in their name, and always return the logical OR of the _aa64_ 3688 * and the _aa32_ function. 3689 */ 3690 3691 /* 3692 * 32-bit feature tests via id registers. 3693 */ 3694 static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id) 3695 { 3696 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; 3697 } 3698 3699 static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id) 3700 { 3701 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; 3702 } 3703 3704 static inline bool isar_feature_aa32_lob(const ARMISARegisters *id) 3705 { 3706 /* (M-profile) low-overhead loops and branch future */ 3707 return FIELD_EX32(id->id_isar0, ID_ISAR0, CMPBRANCH) >= 3; 3708 } 3709 3710 static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id) 3711 { 3712 return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0; 3713 } 3714 3715 static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) 3716 { 3717 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0; 3718 } 3719 3720 static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id) 3721 { 3722 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1; 3723 } 3724 3725 static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id) 3726 { 3727 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0; 3728 } 3729 3730 static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id) 3731 { 3732 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0; 3733 } 3734 3735 static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id) 3736 { 3737 return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0; 3738 } 3739 3740 static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id) 3741 { 3742 return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0; 3743 } 3744 3745 static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id) 3746 { 3747 return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0; 3748 } 3749 3750 static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id) 3751 { 3752 return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0; 3753 } 3754 3755 static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) 3756 { 3757 return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0; 3758 } 3759 3760 static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id) 3761 { 3762 return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0; 3763 } 3764 3765 static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) 3766 { 3767 return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0; 3768 } 3769 3770 static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id) 3771 { 3772 return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0; 3773 } 3774 3775 static inline bool isar_feature_aa32_ras(const ARMISARegisters *id) 3776 { 3777 return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) != 0; 3778 } 3779 3780 static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id) 3781 { 3782 return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0; 3783 } 3784 3785 static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id) 3786 { 3787 /* 3788 * Return true if M-profile state handling insns 3789 * (VSCCLRM, CLRM, FPCTX access insns) are implemented 3790 */ 3791 return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >= 3; 3792 } 3793 3794 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) 3795 { 3796 /* Sadly this is encoded differently for A-profile and M-profile */ 3797 if (isar_feature_aa32_mprofile(id)) { 3798 return FIELD_EX32(id->mvfr1, MVFR1, FP16) > 0; 3799 } else { 3800 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3; 3801 } 3802 } 3803 3804 static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id) 3805 { 3806 /* 3807 * Return true if either VFP or SIMD is implemented. 3808 * In this case, a minimum of VFP w/ D0-D15. 3809 */ 3810 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0; 3811 } 3812 3813 static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id) 3814 { 3815 /* Return true if D16-D31 are implemented */ 3816 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2; 3817 } 3818 3819 static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id) 3820 { 3821 return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0; 3822 } 3823 3824 static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id) 3825 { 3826 /* Return true if CPU supports single precision floating point, VFPv2 */ 3827 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0; 3828 } 3829 3830 static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id) 3831 { 3832 /* Return true if CPU supports single precision floating point, VFPv3 */ 3833 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2; 3834 } 3835 3836 static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id) 3837 { 3838 /* Return true if CPU supports double precision floating point, VFPv2 */ 3839 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0; 3840 } 3841 3842 static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id) 3843 { 3844 /* Return true if CPU supports double precision floating point, VFPv3 */ 3845 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2; 3846 } 3847 3848 static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id) 3849 { 3850 return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id); 3851 } 3852 3853 /* 3854 * We always set the FP and SIMD FP16 fields to indicate identical 3855 * levels of support (assuming SIMD is implemented at all), so 3856 * we only need one set of accessors. 3857 */ 3858 static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id) 3859 { 3860 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0; 3861 } 3862 3863 static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id) 3864 { 3865 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1; 3866 } 3867 3868 /* 3869 * Note that this ID register field covers both VFP and Neon FMAC, 3870 * so should usually be tested in combination with some other 3871 * check that confirms the presence of whichever of VFP or Neon is 3872 * relevant, to avoid accidentally enabling a Neon feature on 3873 * a VFP-no-Neon core or vice-versa. 3874 */ 3875 static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id) 3876 { 3877 return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0; 3878 } 3879 3880 static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id) 3881 { 3882 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1; 3883 } 3884 3885 static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id) 3886 { 3887 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2; 3888 } 3889 3890 static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id) 3891 { 3892 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3; 3893 } 3894 3895 static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id) 3896 { 3897 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4; 3898 } 3899 3900 static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id) 3901 { 3902 return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >= 4; 3903 } 3904 3905 static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) 3906 { 3907 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0; 3908 } 3909 3910 static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id) 3911 { 3912 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2; 3913 } 3914 3915 static inline bool isar_feature_aa32_pmu_8_1(const ARMISARegisters *id) 3916 { 3917 /* 0xf means "non-standard IMPDEF PMU" */ 3918 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 && 3919 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3920 } 3921 3922 static inline bool isar_feature_aa32_pmu_8_4(const ARMISARegisters *id) 3923 { 3924 /* 0xf means "non-standard IMPDEF PMU" */ 3925 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 5 && 3926 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3927 } 3928 3929 static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id) 3930 { 3931 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0; 3932 } 3933 3934 static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id) 3935 { 3936 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0; 3937 } 3938 3939 static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id) 3940 { 3941 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0; 3942 } 3943 3944 static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id) 3945 { 3946 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0; 3947 } 3948 3949 static inline bool isar_feature_aa32_dit(const ARMISARegisters *id) 3950 { 3951 return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0; 3952 } 3953 3954 static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id) 3955 { 3956 return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0; 3957 } 3958 3959 /* 3960 * 64-bit feature tests via id registers. 3961 */ 3962 static inline bool isar_feature_aa64_aes(const ARMISARegisters *id) 3963 { 3964 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0; 3965 } 3966 3967 static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id) 3968 { 3969 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1; 3970 } 3971 3972 static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id) 3973 { 3974 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0; 3975 } 3976 3977 static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id) 3978 { 3979 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0; 3980 } 3981 3982 static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id) 3983 { 3984 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1; 3985 } 3986 3987 static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id) 3988 { 3989 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0; 3990 } 3991 3992 static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id) 3993 { 3994 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0; 3995 } 3996 3997 static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) 3998 { 3999 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0; 4000 } 4001 4002 static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id) 4003 { 4004 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0; 4005 } 4006 4007 static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id) 4008 { 4009 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0; 4010 } 4011 4012 static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id) 4013 { 4014 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0; 4015 } 4016 4017 static inline bool isar_feature_aa64_dp(const ARMISARegisters *id) 4018 { 4019 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0; 4020 } 4021 4022 static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id) 4023 { 4024 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0; 4025 } 4026 4027 static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id) 4028 { 4029 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0; 4030 } 4031 4032 static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id) 4033 { 4034 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2; 4035 } 4036 4037 static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id) 4038 { 4039 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0; 4040 } 4041 4042 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) 4043 { 4044 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0; 4045 } 4046 4047 static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) 4048 { 4049 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0; 4050 } 4051 4052 static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) 4053 { 4054 /* 4055 * Return true if any form of pauth is enabled, as this 4056 * predicate controls migration of the 128-bit keys. 4057 */ 4058 return (id->id_aa64isar1 & 4059 (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) | 4060 FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) | 4061 FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) | 4062 FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0; 4063 } 4064 4065 static inline bool isar_feature_aa64_pauth_arch(const ARMISARegisters *id) 4066 { 4067 /* 4068 * Return true if pauth is enabled with the architected QARMA algorithm. 4069 * QEMU will always set APA+GPA to the same value. 4070 */ 4071 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0; 4072 } 4073 4074 static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) 4075 { 4076 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0; 4077 } 4078 4079 static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id) 4080 { 4081 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0; 4082 } 4083 4084 static inline bool isar_feature_aa64_frint(const ARMISARegisters *id) 4085 { 4086 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0; 4087 } 4088 4089 static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id) 4090 { 4091 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) != 0; 4092 } 4093 4094 static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id) 4095 { 4096 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2; 4097 } 4098 4099 static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id) 4100 { 4101 /* We always set the AdvSIMD and FP fields identically. */ 4102 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf; 4103 } 4104 4105 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) 4106 { 4107 /* We always set the AdvSIMD and FP fields identically wrt FP16. */ 4108 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 4109 } 4110 4111 static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id) 4112 { 4113 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2; 4114 } 4115 4116 static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id) 4117 { 4118 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2; 4119 } 4120 4121 static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) 4122 { 4123 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; 4124 } 4125 4126 static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id) 4127 { 4128 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) != 0; 4129 } 4130 4131 static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) 4132 { 4133 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0; 4134 } 4135 4136 static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) 4137 { 4138 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; 4139 } 4140 4141 static inline bool isar_feature_aa64_pan(const ARMISARegisters *id) 4142 { 4143 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0; 4144 } 4145 4146 static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id) 4147 { 4148 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2; 4149 } 4150 4151 static inline bool isar_feature_aa64_uao(const ARMISARegisters *id) 4152 { 4153 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0; 4154 } 4155 4156 static inline bool isar_feature_aa64_st(const ARMISARegisters *id) 4157 { 4158 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0; 4159 } 4160 4161 static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) 4162 { 4163 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; 4164 } 4165 4166 static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id) 4167 { 4168 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0; 4169 } 4170 4171 static inline bool isar_feature_aa64_mte(const ARMISARegisters *id) 4172 { 4173 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2; 4174 } 4175 4176 static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id) 4177 { 4178 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 && 4179 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 4180 } 4181 4182 static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id) 4183 { 4184 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 && 4185 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 4186 } 4187 4188 static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id) 4189 { 4190 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0; 4191 } 4192 4193 static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id) 4194 { 4195 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2; 4196 } 4197 4198 static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) 4199 { 4200 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0; 4201 } 4202 4203 static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id) 4204 { 4205 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0; 4206 } 4207 4208 static inline bool isar_feature_aa64_dit(const ARMISARegisters *id) 4209 { 4210 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0; 4211 } 4212 4213 static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id) 4214 { 4215 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0; 4216 } 4217 4218 /* 4219 * Feature tests for "does this exist in either 32-bit or 64-bit?" 4220 */ 4221 static inline bool isar_feature_any_fp16(const ARMISARegisters *id) 4222 { 4223 return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id); 4224 } 4225 4226 static inline bool isar_feature_any_predinv(const ARMISARegisters *id) 4227 { 4228 return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id); 4229 } 4230 4231 static inline bool isar_feature_any_pmu_8_1(const ARMISARegisters *id) 4232 { 4233 return isar_feature_aa64_pmu_8_1(id) || isar_feature_aa32_pmu_8_1(id); 4234 } 4235 4236 static inline bool isar_feature_any_pmu_8_4(const ARMISARegisters *id) 4237 { 4238 return isar_feature_aa64_pmu_8_4(id) || isar_feature_aa32_pmu_8_4(id); 4239 } 4240 4241 static inline bool isar_feature_any_ccidx(const ARMISARegisters *id) 4242 { 4243 return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id); 4244 } 4245 4246 static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id) 4247 { 4248 return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id); 4249 } 4250 4251 /* 4252 * Forward to the above feature tests given an ARMCPU pointer. 4253 */ 4254 #define cpu_isar_feature(name, cpu) \ 4255 ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); }) 4256 4257 #endif 4258