1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "qemu/cpu-float.h" 25 #include "hw/registerfields.h" 26 #include "cpu-qom.h" 27 #include "exec/cpu-defs.h" 28 #include "qapi/qapi-types-common.h" 29 30 /* ARM processors have a weak memory model */ 31 #define TCG_GUEST_DEFAULT_MO (0) 32 33 #ifdef TARGET_AARCH64 34 #define KVM_HAVE_MCE_INJECTION 1 35 #endif 36 37 #define EXCP_UDEF 1 /* undefined instruction */ 38 #define EXCP_SWI 2 /* software interrupt */ 39 #define EXCP_PREFETCH_ABORT 3 40 #define EXCP_DATA_ABORT 4 41 #define EXCP_IRQ 5 42 #define EXCP_FIQ 6 43 #define EXCP_BKPT 7 44 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 45 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 46 #define EXCP_HVC 11 /* HyperVisor Call */ 47 #define EXCP_HYP_TRAP 12 48 #define EXCP_SMC 13 /* Secure Monitor Call */ 49 #define EXCP_VIRQ 14 50 #define EXCP_VFIQ 15 51 #define EXCP_SEMIHOST 16 /* semihosting call */ 52 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 53 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 54 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 55 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ 56 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ 57 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ 58 #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ 59 #define EXCP_VSERR 24 60 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 61 62 #define ARMV7M_EXCP_RESET 1 63 #define ARMV7M_EXCP_NMI 2 64 #define ARMV7M_EXCP_HARD 3 65 #define ARMV7M_EXCP_MEM 4 66 #define ARMV7M_EXCP_BUS 5 67 #define ARMV7M_EXCP_USAGE 6 68 #define ARMV7M_EXCP_SECURE 7 69 #define ARMV7M_EXCP_SVC 11 70 #define ARMV7M_EXCP_DEBUG 12 71 #define ARMV7M_EXCP_PENDSV 14 72 #define ARMV7M_EXCP_SYSTICK 15 73 74 /* For M profile, some registers are banked secure vs non-secure; 75 * these are represented as a 2-element array where the first element 76 * is the non-secure copy and the second is the secure copy. 77 * When the CPU does not have implement the security extension then 78 * only the first element is used. 79 * This means that the copy for the current security state can be 80 * accessed via env->registerfield[env->v7m.secure] (whether the security 81 * extension is implemented or not). 82 */ 83 enum { 84 M_REG_NS = 0, 85 M_REG_S = 1, 86 M_REG_NUM_BANKS = 2, 87 }; 88 89 /* ARM-specific interrupt pending bits. */ 90 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 91 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 92 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 93 #define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0 94 95 /* The usual mapping for an AArch64 system register to its AArch32 96 * counterpart is for the 32 bit world to have access to the lower 97 * half only (with writes leaving the upper half untouched). It's 98 * therefore useful to be able to pass TCG the offset of the least 99 * significant half of a uint64_t struct member. 100 */ 101 #if HOST_BIG_ENDIAN 102 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 103 #define offsetofhigh32(S, M) offsetof(S, M) 104 #else 105 #define offsetoflow32(S, M) offsetof(S, M) 106 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 107 #endif 108 109 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 110 #define ARM_CPU_IRQ 0 111 #define ARM_CPU_FIQ 1 112 #define ARM_CPU_VIRQ 2 113 #define ARM_CPU_VFIQ 3 114 115 /* ARM-specific extra insn start words: 116 * 1: Conditional execution bits 117 * 2: Partial exception syndrome for data aborts 118 */ 119 #define TARGET_INSN_START_EXTRA_WORDS 2 120 121 /* The 2nd extra word holding syndrome info for data aborts does not use 122 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 123 * help the sleb128 encoder do a better job. 124 * When restoring the CPU state, we shift it back up. 125 */ 126 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 127 #define ARM_INSN_START_WORD2_SHIFT 14 128 129 /* We currently assume float and double are IEEE single and double 130 precision respectively. 131 Doing runtime conversions is tricky because VFP registers may contain 132 integer values (eg. as the result of a FTOSI instruction). 133 s<2n> maps to the least significant half of d<n> 134 s<2n+1> maps to the most significant half of d<n> 135 */ 136 137 /** 138 * DynamicGDBXMLInfo: 139 * @desc: Contains the XML descriptions. 140 * @num: Number of the registers in this XML seen by GDB. 141 * @data: A union with data specific to the set of registers 142 * @cpregs_keys: Array that contains the corresponding Key of 143 * a given cpreg with the same order of the cpreg 144 * in the XML description. 145 */ 146 typedef struct DynamicGDBXMLInfo { 147 char *desc; 148 int num; 149 union { 150 struct { 151 uint32_t *keys; 152 } cpregs; 153 } data; 154 } DynamicGDBXMLInfo; 155 156 /* CPU state for each instance of a generic timer (in cp15 c14) */ 157 typedef struct ARMGenericTimer { 158 uint64_t cval; /* Timer CompareValue register */ 159 uint64_t ctl; /* Timer Control register */ 160 } ARMGenericTimer; 161 162 #define GTIMER_PHYS 0 163 #define GTIMER_VIRT 1 164 #define GTIMER_HYP 2 165 #define GTIMER_SEC 3 166 #define GTIMER_HYPVIRT 4 167 #define NUM_GTIMERS 5 168 169 typedef struct { 170 uint64_t raw_tcr; 171 uint32_t mask; 172 uint32_t base_mask; 173 } TCR; 174 175 #define VTCR_NSW (1u << 29) 176 #define VTCR_NSA (1u << 30) 177 #define VSTCR_SW VTCR_NSW 178 #define VSTCR_SA VTCR_NSA 179 180 /* Define a maximum sized vector register. 181 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 182 * For 64-bit, this is a 2048-bit SVE register. 183 * 184 * Note that the mapping between S, D, and Q views of the register bank 185 * differs between AArch64 and AArch32. 186 * In AArch32: 187 * Qn = regs[n].d[1]:regs[n].d[0] 188 * Dn = regs[n / 2].d[n & 1] 189 * Sn = regs[n / 4].d[n % 4 / 2], 190 * bits 31..0 for even n, and bits 63..32 for odd n 191 * (and regs[16] to regs[31] are inaccessible) 192 * In AArch64: 193 * Zn = regs[n].d[*] 194 * Qn = regs[n].d[1]:regs[n].d[0] 195 * Dn = regs[n].d[0] 196 * Sn = regs[n].d[0] bits 31..0 197 * Hn = regs[n].d[0] bits 15..0 198 * 199 * This corresponds to the architecturally defined mapping between 200 * the two execution states, and means we do not need to explicitly 201 * map these registers when changing states. 202 * 203 * Align the data for use with TCG host vector operations. 204 */ 205 206 #ifdef TARGET_AARCH64 207 # define ARM_MAX_VQ 16 208 #else 209 # define ARM_MAX_VQ 1 210 #endif 211 212 typedef struct ARMVectorReg { 213 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 214 } ARMVectorReg; 215 216 #ifdef TARGET_AARCH64 217 /* In AArch32 mode, predicate registers do not exist at all. */ 218 typedef struct ARMPredicateReg { 219 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); 220 } ARMPredicateReg; 221 222 /* In AArch32 mode, PAC keys do not exist at all. */ 223 typedef struct ARMPACKey { 224 uint64_t lo, hi; 225 } ARMPACKey; 226 #endif 227 228 /* See the commentary above the TBFLAG field definitions. */ 229 typedef struct CPUARMTBFlags { 230 uint32_t flags; 231 target_ulong flags2; 232 } CPUARMTBFlags; 233 234 typedef struct CPUArchState { 235 /* Regs for current mode. */ 236 uint32_t regs[16]; 237 238 /* 32/64 switch only happens when taking and returning from 239 * exceptions so the overlap semantics are taken care of then 240 * instead of having a complicated union. 241 */ 242 /* Regs for A64 mode. */ 243 uint64_t xregs[32]; 244 uint64_t pc; 245 /* PSTATE isn't an architectural register for ARMv8. However, it is 246 * convenient for us to assemble the underlying state into a 32 bit format 247 * identical to the architectural format used for the SPSR. (This is also 248 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 249 * 'pstate' register are.) Of the PSTATE bits: 250 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 251 * semantics as for AArch32, as described in the comments on each field) 252 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 253 * DAIF (exception masks) are kept in env->daif 254 * BTYPE is kept in env->btype 255 * SM and ZA are kept in env->svcr 256 * all other bits are stored in their correct places in env->pstate 257 */ 258 uint32_t pstate; 259 bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nRW */ 260 bool thumb; /* True if CPU is in thumb mode; cpsr[5] */ 261 262 /* Cached TBFLAGS state. See below for which bits are included. */ 263 CPUARMTBFlags hflags; 264 265 /* Frequently accessed CPSR bits are stored separately for efficiency. 266 This contains all the other bits. Use cpsr_{read,write} to access 267 the whole CPSR. */ 268 uint32_t uncached_cpsr; 269 uint32_t spsr; 270 271 /* Banked registers. */ 272 uint64_t banked_spsr[8]; 273 uint32_t banked_r13[8]; 274 uint32_t banked_r14[8]; 275 276 /* These hold r8-r12. */ 277 uint32_t usr_regs[5]; 278 uint32_t fiq_regs[5]; 279 280 /* cpsr flag cache for faster execution */ 281 uint32_t CF; /* 0 or 1 */ 282 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 283 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 284 uint32_t ZF; /* Z set if zero. */ 285 uint32_t QF; /* 0 or 1 */ 286 uint32_t GE; /* cpsr[19:16] */ 287 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 288 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 289 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 290 uint64_t svcr; /* PSTATE.{SM,ZA} in the bits they are in SVCR */ 291 292 uint64_t elr_el[4]; /* AArch64 exception link regs */ 293 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 294 295 /* System control coprocessor (cp15) */ 296 struct { 297 uint32_t c0_cpuid; 298 union { /* Cache size selection */ 299 struct { 300 uint64_t _unused_csselr0; 301 uint64_t csselr_ns; 302 uint64_t _unused_csselr1; 303 uint64_t csselr_s; 304 }; 305 uint64_t csselr_el[4]; 306 }; 307 union { /* System control register. */ 308 struct { 309 uint64_t _unused_sctlr; 310 uint64_t sctlr_ns; 311 uint64_t hsctlr; 312 uint64_t sctlr_s; 313 }; 314 uint64_t sctlr_el[4]; 315 }; 316 uint64_t cpacr_el1; /* Architectural feature access control register */ 317 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 318 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 319 uint64_t sder; /* Secure debug enable register. */ 320 uint32_t nsacr; /* Non-secure access control register. */ 321 union { /* MMU translation table base 0. */ 322 struct { 323 uint64_t _unused_ttbr0_0; 324 uint64_t ttbr0_ns; 325 uint64_t _unused_ttbr0_1; 326 uint64_t ttbr0_s; 327 }; 328 uint64_t ttbr0_el[4]; 329 }; 330 union { /* MMU translation table base 1. */ 331 struct { 332 uint64_t _unused_ttbr1_0; 333 uint64_t ttbr1_ns; 334 uint64_t _unused_ttbr1_1; 335 uint64_t ttbr1_s; 336 }; 337 uint64_t ttbr1_el[4]; 338 }; 339 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 340 uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ 341 /* MMU translation table base control. */ 342 TCR tcr_el[4]; 343 TCR vtcr_el2; /* Virtualization Translation Control. */ 344 TCR vstcr_el2; /* Secure Virtualization Translation Control. */ 345 uint32_t c2_data; /* MPU data cacheable bits. */ 346 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 347 union { /* MMU domain access control register 348 * MPU write buffer control. 349 */ 350 struct { 351 uint64_t dacr_ns; 352 uint64_t dacr_s; 353 }; 354 struct { 355 uint64_t dacr32_el2; 356 }; 357 }; 358 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 359 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 360 uint64_t hcr_el2; /* Hypervisor configuration register */ 361 uint64_t hcrx_el2; /* Extended Hypervisor configuration register */ 362 uint64_t scr_el3; /* Secure configuration register. */ 363 union { /* Fault status registers. */ 364 struct { 365 uint64_t ifsr_ns; 366 uint64_t ifsr_s; 367 }; 368 struct { 369 uint64_t ifsr32_el2; 370 }; 371 }; 372 union { 373 struct { 374 uint64_t _unused_dfsr; 375 uint64_t dfsr_ns; 376 uint64_t hsr; 377 uint64_t dfsr_s; 378 }; 379 uint64_t esr_el[4]; 380 }; 381 uint32_t c6_region[8]; /* MPU base/size registers. */ 382 union { /* Fault address registers. */ 383 struct { 384 uint64_t _unused_far0; 385 #if HOST_BIG_ENDIAN 386 uint32_t ifar_ns; 387 uint32_t dfar_ns; 388 uint32_t ifar_s; 389 uint32_t dfar_s; 390 #else 391 uint32_t dfar_ns; 392 uint32_t ifar_ns; 393 uint32_t dfar_s; 394 uint32_t ifar_s; 395 #endif 396 uint64_t _unused_far3; 397 }; 398 uint64_t far_el[4]; 399 }; 400 uint64_t hpfar_el2; 401 uint64_t hstr_el2; 402 union { /* Translation result. */ 403 struct { 404 uint64_t _unused_par_0; 405 uint64_t par_ns; 406 uint64_t _unused_par_1; 407 uint64_t par_s; 408 }; 409 uint64_t par_el[4]; 410 }; 411 412 uint32_t c9_insn; /* Cache lockdown registers. */ 413 uint32_t c9_data; 414 uint64_t c9_pmcr; /* performance monitor control register */ 415 uint64_t c9_pmcnten; /* perf monitor counter enables */ 416 uint64_t c9_pmovsr; /* perf monitor overflow status */ 417 uint64_t c9_pmuserenr; /* perf monitor user enable */ 418 uint64_t c9_pmselr; /* perf monitor counter selection register */ 419 uint64_t c9_pminten; /* perf monitor interrupt enables */ 420 union { /* Memory attribute redirection */ 421 struct { 422 #if HOST_BIG_ENDIAN 423 uint64_t _unused_mair_0; 424 uint32_t mair1_ns; 425 uint32_t mair0_ns; 426 uint64_t _unused_mair_1; 427 uint32_t mair1_s; 428 uint32_t mair0_s; 429 #else 430 uint64_t _unused_mair_0; 431 uint32_t mair0_ns; 432 uint32_t mair1_ns; 433 uint64_t _unused_mair_1; 434 uint32_t mair0_s; 435 uint32_t mair1_s; 436 #endif 437 }; 438 uint64_t mair_el[4]; 439 }; 440 union { /* vector base address register */ 441 struct { 442 uint64_t _unused_vbar; 443 uint64_t vbar_ns; 444 uint64_t hvbar; 445 uint64_t vbar_s; 446 }; 447 uint64_t vbar_el[4]; 448 }; 449 uint32_t mvbar; /* (monitor) vector base address register */ 450 uint64_t rvbar; /* rvbar sampled from rvbar property at reset */ 451 struct { /* FCSE PID. */ 452 uint32_t fcseidr_ns; 453 uint32_t fcseidr_s; 454 }; 455 union { /* Context ID. */ 456 struct { 457 uint64_t _unused_contextidr_0; 458 uint64_t contextidr_ns; 459 uint64_t _unused_contextidr_1; 460 uint64_t contextidr_s; 461 }; 462 uint64_t contextidr_el[4]; 463 }; 464 union { /* User RW Thread register. */ 465 struct { 466 uint64_t tpidrurw_ns; 467 uint64_t tpidrprw_ns; 468 uint64_t htpidr; 469 uint64_t _tpidr_el3; 470 }; 471 uint64_t tpidr_el[4]; 472 }; 473 uint64_t tpidr2_el0; 474 /* The secure banks of these registers don't map anywhere */ 475 uint64_t tpidrurw_s; 476 uint64_t tpidrprw_s; 477 uint64_t tpidruro_s; 478 479 union { /* User RO Thread register. */ 480 uint64_t tpidruro_ns; 481 uint64_t tpidrro_el[1]; 482 }; 483 uint64_t c14_cntfrq; /* Counter Frequency register */ 484 uint64_t c14_cntkctl; /* Timer Control register */ 485 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 486 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 487 ARMGenericTimer c14_timer[NUM_GTIMERS]; 488 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 489 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 490 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 491 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 492 uint32_t c15_threadid; /* TI debugger thread-ID. */ 493 uint32_t c15_config_base_address; /* SCU base address. */ 494 uint32_t c15_diagnostic; /* diagnostic register */ 495 uint32_t c15_power_diagnostic; 496 uint32_t c15_power_control; /* power control */ 497 uint64_t dbgbvr[16]; /* breakpoint value registers */ 498 uint64_t dbgbcr[16]; /* breakpoint control registers */ 499 uint64_t dbgwvr[16]; /* watchpoint value registers */ 500 uint64_t dbgwcr[16]; /* watchpoint control registers */ 501 uint64_t mdscr_el1; 502 uint64_t oslsr_el1; /* OS Lock Status */ 503 uint64_t osdlr_el1; /* OS DoubleLock status */ 504 uint64_t mdcr_el2; 505 uint64_t mdcr_el3; 506 /* Stores the architectural value of the counter *the last time it was 507 * updated* by pmccntr_op_start. Accesses should always be surrounded 508 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 509 * architecturally-correct value is being read/set. 510 */ 511 uint64_t c15_ccnt; 512 /* Stores the delta between the architectural value and the underlying 513 * cycle count during normal operation. It is used to update c15_ccnt 514 * to be the correct architectural value before accesses. During 515 * accesses, c15_ccnt_delta contains the underlying count being used 516 * for the access, after which it reverts to the delta value in 517 * pmccntr_op_finish. 518 */ 519 uint64_t c15_ccnt_delta; 520 uint64_t c14_pmevcntr[31]; 521 uint64_t c14_pmevcntr_delta[31]; 522 uint64_t c14_pmevtyper[31]; 523 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 524 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 525 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 526 uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ 527 uint64_t gcr_el1; 528 uint64_t rgsr_el1; 529 530 /* Minimal RAS registers */ 531 uint64_t disr_el1; 532 uint64_t vdisr_el2; 533 uint64_t vsesr_el2; 534 } cp15; 535 536 struct { 537 /* M profile has up to 4 stack pointers: 538 * a Main Stack Pointer and a Process Stack Pointer for each 539 * of the Secure and Non-Secure states. (If the CPU doesn't support 540 * the security extension then it has only two SPs.) 541 * In QEMU we always store the currently active SP in regs[13], 542 * and the non-active SP for the current security state in 543 * v7m.other_sp. The stack pointers for the inactive security state 544 * are stored in other_ss_msp and other_ss_psp. 545 * switch_v7m_security_state() is responsible for rearranging them 546 * when we change security state. 547 */ 548 uint32_t other_sp; 549 uint32_t other_ss_msp; 550 uint32_t other_ss_psp; 551 uint32_t vecbase[M_REG_NUM_BANKS]; 552 uint32_t basepri[M_REG_NUM_BANKS]; 553 uint32_t control[M_REG_NUM_BANKS]; 554 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 555 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 556 uint32_t hfsr; /* HardFault Status */ 557 uint32_t dfsr; /* Debug Fault Status Register */ 558 uint32_t sfsr; /* Secure Fault Status Register */ 559 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 560 uint32_t bfar; /* BusFault Address */ 561 uint32_t sfar; /* Secure Fault Address Register */ 562 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 563 int exception; 564 uint32_t primask[M_REG_NUM_BANKS]; 565 uint32_t faultmask[M_REG_NUM_BANKS]; 566 uint32_t aircr; /* only holds r/w state if security extn implemented */ 567 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 568 uint32_t csselr[M_REG_NUM_BANKS]; 569 uint32_t scr[M_REG_NUM_BANKS]; 570 uint32_t msplim[M_REG_NUM_BANKS]; 571 uint32_t psplim[M_REG_NUM_BANKS]; 572 uint32_t fpcar[M_REG_NUM_BANKS]; 573 uint32_t fpccr[M_REG_NUM_BANKS]; 574 uint32_t fpdscr[M_REG_NUM_BANKS]; 575 uint32_t cpacr[M_REG_NUM_BANKS]; 576 uint32_t nsacr; 577 uint32_t ltpsize; 578 uint32_t vpr; 579 } v7m; 580 581 /* Information associated with an exception about to be taken: 582 * code which raises an exception must set cs->exception_index and 583 * the relevant parts of this structure; the cpu_do_interrupt function 584 * will then set the guest-visible registers as part of the exception 585 * entry process. 586 */ 587 struct { 588 uint32_t syndrome; /* AArch64 format syndrome register */ 589 uint32_t fsr; /* AArch32 format fault status register info */ 590 uint64_t vaddress; /* virtual addr associated with exception, if any */ 591 uint32_t target_el; /* EL the exception should be targeted for */ 592 /* If we implement EL2 we will also need to store information 593 * about the intermediate physical address for stage 2 faults. 594 */ 595 } exception; 596 597 /* Information associated with an SError */ 598 struct { 599 uint8_t pending; 600 uint8_t has_esr; 601 uint64_t esr; 602 } serror; 603 604 uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */ 605 606 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 607 uint32_t irq_line_state; 608 609 /* Thumb-2 EE state. */ 610 uint32_t teecr; 611 uint32_t teehbr; 612 613 /* VFP coprocessor state. */ 614 struct { 615 ARMVectorReg zregs[32]; 616 617 #ifdef TARGET_AARCH64 618 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 619 #define FFR_PRED_NUM 16 620 ARMPredicateReg pregs[17]; 621 /* Scratch space for aa64 sve predicate temporary. */ 622 ARMPredicateReg preg_tmp; 623 #endif 624 625 /* We store these fpcsr fields separately for convenience. */ 626 uint32_t qc[4] QEMU_ALIGNED(16); 627 int vec_len; 628 int vec_stride; 629 630 uint32_t xregs[16]; 631 632 /* Scratch space for aa32 neon expansion. */ 633 uint32_t scratch[8]; 634 635 /* There are a number of distinct float control structures: 636 * 637 * fp_status: is the "normal" fp status. 638 * fp_status_fp16: used for half-precision calculations 639 * standard_fp_status : the ARM "Standard FPSCR Value" 640 * standard_fp_status_fp16 : used for half-precision 641 * calculations with the ARM "Standard FPSCR Value" 642 * 643 * Half-precision operations are governed by a separate 644 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 645 * status structure to control this. 646 * 647 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 648 * round-to-nearest and is used by any operations (generally 649 * Neon) which the architecture defines as controlled by the 650 * standard FPSCR value rather than the FPSCR. 651 * 652 * The "standard FPSCR but for fp16 ops" is needed because 653 * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than 654 * using a fixed value for it. 655 * 656 * To avoid having to transfer exception bits around, we simply 657 * say that the FPSCR cumulative exception flags are the logical 658 * OR of the flags in the four fp statuses. This relies on the 659 * only thing which needs to read the exception flags being 660 * an explicit FPSCR read. 661 */ 662 float_status fp_status; 663 float_status fp_status_f16; 664 float_status standard_fp_status; 665 float_status standard_fp_status_f16; 666 667 uint64_t zcr_el[4]; /* ZCR_EL[1-3] */ 668 uint64_t smcr_el[4]; /* SMCR_EL[1-3] */ 669 } vfp; 670 uint64_t exclusive_addr; 671 uint64_t exclusive_val; 672 uint64_t exclusive_high; 673 674 /* iwMMXt coprocessor state. */ 675 struct { 676 uint64_t regs[16]; 677 uint64_t val; 678 679 uint32_t cregs[16]; 680 } iwmmxt; 681 682 #ifdef TARGET_AARCH64 683 struct { 684 ARMPACKey apia; 685 ARMPACKey apib; 686 ARMPACKey apda; 687 ARMPACKey apdb; 688 ARMPACKey apga; 689 } keys; 690 691 uint64_t scxtnum_el[4]; 692 693 /* 694 * SME ZA storage -- 256 x 256 byte array, with bytes in host word order, 695 * as we do with vfp.zregs[]. This corresponds to the architectural ZA 696 * array, where ZA[N] is in the least-significant bytes of env->zarray[N]. 697 * When SVL is less than the architectural maximum, the accessible 698 * storage is restricted, such that if the SVL is X bytes the guest can 699 * see only the bottom X elements of zarray[], and only the least 700 * significant X bytes of each element of the array. (In other words, 701 * the observable part is always square.) 702 * 703 * The ZA storage can also be considered as a set of square tiles of 704 * elements of different sizes. The mapping from tiles to the ZA array 705 * is architecturally defined, such that for tiles of elements of esz 706 * bytes, the Nth row (or "horizontal slice") of tile T is in 707 * ZA[T + N * esz]. Note that this means that each tile is not contiguous 708 * in the ZA storage, because its rows are striped through the ZA array. 709 * 710 * Because this is so large, keep this toward the end of the reset area, 711 * to keep the offsets into the rest of the structure smaller. 712 */ 713 ARMVectorReg zarray[ARM_MAX_VQ * 16]; 714 #endif 715 716 #if defined(CONFIG_USER_ONLY) 717 /* For usermode syscall translation. */ 718 int eabi; 719 #endif 720 721 struct CPUBreakpoint *cpu_breakpoint[16]; 722 struct CPUWatchpoint *cpu_watchpoint[16]; 723 724 /* Fields up to this point are cleared by a CPU reset */ 725 struct {} end_reset_fields; 726 727 /* Fields after this point are preserved across CPU reset. */ 728 729 /* Internal CPU feature flags. */ 730 uint64_t features; 731 732 /* PMSAv7 MPU */ 733 struct { 734 uint32_t *drbar; 735 uint32_t *drsr; 736 uint32_t *dracr; 737 uint32_t rnr[M_REG_NUM_BANKS]; 738 } pmsav7; 739 740 /* PMSAv8 MPU */ 741 struct { 742 /* The PMSAv8 implementation also shares some PMSAv7 config 743 * and state: 744 * pmsav7.rnr (region number register) 745 * pmsav7_dregion (number of configured regions) 746 */ 747 uint32_t *rbar[M_REG_NUM_BANKS]; 748 uint32_t *rlar[M_REG_NUM_BANKS]; 749 uint32_t mair0[M_REG_NUM_BANKS]; 750 uint32_t mair1[M_REG_NUM_BANKS]; 751 } pmsav8; 752 753 /* v8M SAU */ 754 struct { 755 uint32_t *rbar; 756 uint32_t *rlar; 757 uint32_t rnr; 758 uint32_t ctrl; 759 } sau; 760 761 void *nvic; 762 const struct arm_boot_info *boot_info; 763 /* Store GICv3CPUState to access from this struct */ 764 void *gicv3state; 765 766 #ifdef TARGET_TAGGED_ADDRESSES 767 /* Linux syscall tagged address support */ 768 bool tagged_addr_enable; 769 #endif 770 } CPUARMState; 771 772 static inline void set_feature(CPUARMState *env, int feature) 773 { 774 env->features |= 1ULL << feature; 775 } 776 777 static inline void unset_feature(CPUARMState *env, int feature) 778 { 779 env->features &= ~(1ULL << feature); 780 } 781 782 /** 783 * ARMELChangeHookFn: 784 * type of a function which can be registered via arm_register_el_change_hook() 785 * to get callbacks when the CPU changes its exception level or mode. 786 */ 787 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 788 typedef struct ARMELChangeHook ARMELChangeHook; 789 struct ARMELChangeHook { 790 ARMELChangeHookFn *hook; 791 void *opaque; 792 QLIST_ENTRY(ARMELChangeHook) node; 793 }; 794 795 /* These values map onto the return values for 796 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 797 typedef enum ARMPSCIState { 798 PSCI_ON = 0, 799 PSCI_OFF = 1, 800 PSCI_ON_PENDING = 2 801 } ARMPSCIState; 802 803 typedef struct ARMISARegisters ARMISARegisters; 804 805 /* 806 * In map, each set bit is a supported vector length of (bit-number + 1) * 16 807 * bytes, i.e. each bit number + 1 is the vector length in quadwords. 808 * 809 * While processing properties during initialization, corresponding init bits 810 * are set for bits in sve_vq_map that have been set by properties. 811 * 812 * Bits set in supported represent valid vector lengths for the CPU type. 813 */ 814 typedef struct { 815 uint32_t map, init, supported; 816 } ARMVQMap; 817 818 /** 819 * ARMCPU: 820 * @env: #CPUARMState 821 * 822 * An ARM CPU core. 823 */ 824 struct ArchCPU { 825 /*< private >*/ 826 CPUState parent_obj; 827 /*< public >*/ 828 829 CPUNegativeOffsetState neg; 830 CPUARMState env; 831 832 /* Coprocessor information */ 833 GHashTable *cp_regs; 834 /* For marshalling (mostly coprocessor) register state between the 835 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 836 * we use these arrays. 837 */ 838 /* List of register indexes managed via these arrays; (full KVM style 839 * 64 bit indexes, not CPRegInfo 32 bit indexes) 840 */ 841 uint64_t *cpreg_indexes; 842 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 843 uint64_t *cpreg_values; 844 /* Length of the indexes, values, reset_values arrays */ 845 int32_t cpreg_array_len; 846 /* These are used only for migration: incoming data arrives in 847 * these fields and is sanity checked in post_load before copying 848 * to the working data structures above. 849 */ 850 uint64_t *cpreg_vmstate_indexes; 851 uint64_t *cpreg_vmstate_values; 852 int32_t cpreg_vmstate_array_len; 853 854 DynamicGDBXMLInfo dyn_sysreg_xml; 855 DynamicGDBXMLInfo dyn_svereg_xml; 856 857 /* Timers used by the generic (architected) timer */ 858 QEMUTimer *gt_timer[NUM_GTIMERS]; 859 /* 860 * Timer used by the PMU. Its state is restored after migration by 861 * pmu_op_finish() - it does not need other handling during migration 862 */ 863 QEMUTimer *pmu_timer; 864 /* GPIO outputs for generic timer */ 865 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 866 /* GPIO output for GICv3 maintenance interrupt signal */ 867 qemu_irq gicv3_maintenance_interrupt; 868 /* GPIO output for the PMU interrupt */ 869 qemu_irq pmu_interrupt; 870 871 /* MemoryRegion to use for secure physical accesses */ 872 MemoryRegion *secure_memory; 873 874 /* MemoryRegion to use for allocation tag accesses */ 875 MemoryRegion *tag_memory; 876 MemoryRegion *secure_tag_memory; 877 878 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 879 Object *idau; 880 881 /* 'compatible' string for this CPU for Linux device trees */ 882 const char *dtb_compatible; 883 884 /* PSCI version for this CPU 885 * Bits[31:16] = Major Version 886 * Bits[15:0] = Minor Version 887 */ 888 uint32_t psci_version; 889 890 /* Current power state, access guarded by BQL */ 891 ARMPSCIState power_state; 892 893 /* CPU has virtualization extension */ 894 bool has_el2; 895 /* CPU has security extension */ 896 bool has_el3; 897 /* CPU has PMU (Performance Monitor Unit) */ 898 bool has_pmu; 899 /* CPU has VFP */ 900 bool has_vfp; 901 /* CPU has Neon */ 902 bool has_neon; 903 /* CPU has M-profile DSP extension */ 904 bool has_dsp; 905 906 /* CPU has memory protection unit */ 907 bool has_mpu; 908 /* PMSAv7 MPU number of supported regions */ 909 uint32_t pmsav7_dregion; 910 /* v8M SAU number of supported regions */ 911 uint32_t sau_sregion; 912 913 /* PSCI conduit used to invoke PSCI methods 914 * 0 - disabled, 1 - smc, 2 - hvc 915 */ 916 uint32_t psci_conduit; 917 918 /* For v8M, initial value of the Secure VTOR */ 919 uint32_t init_svtor; 920 /* For v8M, initial value of the Non-secure VTOR */ 921 uint32_t init_nsvtor; 922 923 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 924 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 925 */ 926 uint32_t kvm_target; 927 928 /* KVM init features for this CPU */ 929 uint32_t kvm_init_features[7]; 930 931 /* KVM CPU state */ 932 933 /* KVM virtual time adjustment */ 934 bool kvm_adjvtime; 935 bool kvm_vtime_dirty; 936 uint64_t kvm_vtime; 937 938 /* KVM steal time */ 939 OnOffAuto kvm_steal_time; 940 941 /* Uniprocessor system with MP extensions */ 942 bool mp_is_up; 943 944 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 945 * and the probe failed (so we need to report the error in realize) 946 */ 947 bool host_cpu_probe_failed; 948 949 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 950 * register. 951 */ 952 int32_t core_count; 953 954 /* The instance init functions for implementation-specific subclasses 955 * set these fields to specify the implementation-dependent values of 956 * various constant registers and reset values of non-constant 957 * registers. 958 * Some of these might become QOM properties eventually. 959 * Field names match the official register names as defined in the 960 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 961 * is used for reset values of non-constant registers; no reset_ 962 * prefix means a constant register. 963 * Some of these registers are split out into a substructure that 964 * is shared with the translators to control the ISA. 965 * 966 * Note that if you add an ID register to the ARMISARegisters struct 967 * you need to also update the 32-bit and 64-bit versions of the 968 * kvm_arm_get_host_cpu_features() function to correctly populate the 969 * field by reading the value from the KVM vCPU. 970 */ 971 struct ARMISARegisters { 972 uint32_t id_isar0; 973 uint32_t id_isar1; 974 uint32_t id_isar2; 975 uint32_t id_isar3; 976 uint32_t id_isar4; 977 uint32_t id_isar5; 978 uint32_t id_isar6; 979 uint32_t id_mmfr0; 980 uint32_t id_mmfr1; 981 uint32_t id_mmfr2; 982 uint32_t id_mmfr3; 983 uint32_t id_mmfr4; 984 uint32_t id_pfr0; 985 uint32_t id_pfr1; 986 uint32_t id_pfr2; 987 uint32_t mvfr0; 988 uint32_t mvfr1; 989 uint32_t mvfr2; 990 uint32_t id_dfr0; 991 uint32_t dbgdidr; 992 uint32_t dbgdevid; 993 uint32_t dbgdevid1; 994 uint64_t id_aa64isar0; 995 uint64_t id_aa64isar1; 996 uint64_t id_aa64pfr0; 997 uint64_t id_aa64pfr1; 998 uint64_t id_aa64mmfr0; 999 uint64_t id_aa64mmfr1; 1000 uint64_t id_aa64mmfr2; 1001 uint64_t id_aa64dfr0; 1002 uint64_t id_aa64dfr1; 1003 uint64_t id_aa64zfr0; 1004 uint64_t id_aa64smfr0; 1005 uint64_t reset_pmcr_el0; 1006 } isar; 1007 uint64_t midr; 1008 uint32_t revidr; 1009 uint32_t reset_fpsid; 1010 uint64_t ctr; 1011 uint32_t reset_sctlr; 1012 uint64_t pmceid0; 1013 uint64_t pmceid1; 1014 uint32_t id_afr0; 1015 uint64_t id_aa64afr0; 1016 uint64_t id_aa64afr1; 1017 uint64_t clidr; 1018 uint64_t mp_affinity; /* MP ID without feature bits */ 1019 /* The elements of this array are the CCSIDR values for each cache, 1020 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 1021 */ 1022 uint64_t ccsidr[16]; 1023 uint64_t reset_cbar; 1024 uint32_t reset_auxcr; 1025 bool reset_hivecs; 1026 1027 /* 1028 * Intermediate values used during property parsing. 1029 * Once finalized, the values should be read from ID_AA64*. 1030 */ 1031 bool prop_pauth; 1032 bool prop_pauth_impdef; 1033 bool prop_lpa2; 1034 1035 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 1036 uint32_t dcz_blocksize; 1037 uint64_t rvbar_prop; /* Property/input signals. */ 1038 1039 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 1040 int gic_num_lrs; /* number of list registers */ 1041 int gic_vpribits; /* number of virtual priority bits */ 1042 int gic_vprebits; /* number of virtual preemption bits */ 1043 int gic_pribits; /* number of physical priority bits */ 1044 1045 /* Whether the cfgend input is high (i.e. this CPU should reset into 1046 * big-endian mode). This setting isn't used directly: instead it modifies 1047 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 1048 * architecture version. 1049 */ 1050 bool cfgend; 1051 1052 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 1053 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 1054 1055 int32_t node_id; /* NUMA node this CPU belongs to */ 1056 1057 /* Used to synchronize KVM and QEMU in-kernel device levels */ 1058 uint8_t device_irq_level; 1059 1060 /* Used to set the maximum vector length the cpu will support. */ 1061 uint32_t sve_max_vq; 1062 1063 #ifdef CONFIG_USER_ONLY 1064 /* Used to set the default vector length at process start. */ 1065 uint32_t sve_default_vq; 1066 uint32_t sme_default_vq; 1067 #endif 1068 1069 ARMVQMap sve_vq; 1070 ARMVQMap sme_vq; 1071 1072 /* Generic timer counter frequency, in Hz */ 1073 uint64_t gt_cntfrq_hz; 1074 }; 1075 1076 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); 1077 1078 void arm_cpu_post_init(Object *obj); 1079 1080 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); 1081 1082 #ifndef CONFIG_USER_ONLY 1083 extern const VMStateDescription vmstate_arm_cpu; 1084 1085 void arm_cpu_do_interrupt(CPUState *cpu); 1086 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 1087 #endif /* !CONFIG_USER_ONLY */ 1088 1089 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 1090 MemTxAttrs *attrs); 1091 1092 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1093 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1094 1095 /* 1096 * Helpers to dynamically generates XML descriptions of the sysregs 1097 * and SVE registers. Returns the number of registers in each set. 1098 */ 1099 int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg); 1100 int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg); 1101 1102 /* Returns the dynamically generated XML for the gdb stub. 1103 * Returns a pointer to the XML contents for the specified XML file or NULL 1104 * if the XML name doesn't match the predefined one. 1105 */ 1106 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname); 1107 1108 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 1109 int cpuid, void *opaque); 1110 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 1111 int cpuid, void *opaque); 1112 1113 #ifdef TARGET_AARCH64 1114 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1115 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1116 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 1117 void aarch64_sve_change_el(CPUARMState *env, int old_el, 1118 int new_el, bool el0_a64); 1119 void arm_reset_sve_state(CPUARMState *env); 1120 1121 /* 1122 * SVE registers are encoded in KVM's memory in an endianness-invariant format. 1123 * The byte at offset i from the start of the in-memory representation contains 1124 * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the 1125 * lowest offsets are stored in the lowest memory addresses, then that nearly 1126 * matches QEMU's representation, which is to use an array of host-endian 1127 * uint64_t's, where the lower offsets are at the lower indices. To complete 1128 * the translation we just need to byte swap the uint64_t's on big-endian hosts. 1129 */ 1130 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr) 1131 { 1132 #if HOST_BIG_ENDIAN 1133 int i; 1134 1135 for (i = 0; i < nr; ++i) { 1136 dst[i] = bswap64(src[i]); 1137 } 1138 1139 return dst; 1140 #else 1141 return src; 1142 #endif 1143 } 1144 1145 #else 1146 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } 1147 static inline void aarch64_sve_change_el(CPUARMState *env, int o, 1148 int n, bool a) 1149 { } 1150 #endif 1151 1152 void aarch64_sync_32_to_64(CPUARMState *env); 1153 void aarch64_sync_64_to_32(CPUARMState *env); 1154 1155 int fp_exception_el(CPUARMState *env, int cur_el); 1156 int sve_exception_el(CPUARMState *env, int cur_el); 1157 int sme_exception_el(CPUARMState *env, int cur_el); 1158 1159 /** 1160 * sve_vqm1_for_el_sm: 1161 * @env: CPUARMState 1162 * @el: exception level 1163 * @sm: streaming mode 1164 * 1165 * Compute the current vector length for @el & @sm, in units of 1166 * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN. 1167 * If @sm, compute for SVL, otherwise NVL. 1168 */ 1169 uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm); 1170 1171 /* Likewise, but using @sm = PSTATE.SM. */ 1172 uint32_t sve_vqm1_for_el(CPUARMState *env, int el); 1173 1174 static inline bool is_a64(CPUARMState *env) 1175 { 1176 return env->aarch64; 1177 } 1178 1179 /** 1180 * pmu_op_start/finish 1181 * @env: CPUARMState 1182 * 1183 * Convert all PMU counters between their delta form (the typical mode when 1184 * they are enabled) and the guest-visible values. These two calls must 1185 * surround any action which might affect the counters. 1186 */ 1187 void pmu_op_start(CPUARMState *env); 1188 void pmu_op_finish(CPUARMState *env); 1189 1190 /* 1191 * Called when a PMU counter is due to overflow 1192 */ 1193 void arm_pmu_timer_cb(void *opaque); 1194 1195 /** 1196 * Functions to register as EL change hooks for PMU mode filtering 1197 */ 1198 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1199 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1200 1201 /* 1202 * pmu_init 1203 * @cpu: ARMCPU 1204 * 1205 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1206 * for the current configuration 1207 */ 1208 void pmu_init(ARMCPU *cpu); 1209 1210 /* SCTLR bit meanings. Several bits have been reused in newer 1211 * versions of the architecture; in that case we define constants 1212 * for both old and new bit meanings. Code which tests against those 1213 * bits should probably check or otherwise arrange that the CPU 1214 * is the architectural version it expects. 1215 */ 1216 #define SCTLR_M (1U << 0) 1217 #define SCTLR_A (1U << 1) 1218 #define SCTLR_C (1U << 2) 1219 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1220 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1221 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1222 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1223 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1224 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1225 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1226 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1227 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1228 #define SCTLR_nAA (1U << 6) /* when v8.4-LSE is implemented */ 1229 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1230 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1231 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1232 #define SCTLR_SED (1U << 8) /* v8 onward */ 1233 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1234 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1235 #define SCTLR_F (1U << 10) /* up to v6 */ 1236 #define SCTLR_SW (1U << 10) /* v7 */ 1237 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ 1238 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1239 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1240 #define SCTLR_I (1U << 12) 1241 #define SCTLR_V (1U << 13) /* AArch32 only */ 1242 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1243 #define SCTLR_RR (1U << 14) /* up to v7 */ 1244 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1245 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1246 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1247 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1248 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1249 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1250 #define SCTLR_BR (1U << 17) /* PMSA only */ 1251 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1252 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1253 #define SCTLR_WXN (1U << 19) 1254 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1255 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1256 #define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */ 1257 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1258 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1259 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1260 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1261 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1262 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1263 #define SCTLR_VE (1U << 24) /* up to v7 */ 1264 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1265 #define SCTLR_EE (1U << 25) 1266 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1267 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1268 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1269 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1270 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1271 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1272 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1273 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1274 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1275 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1276 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1277 #define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */ 1278 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1279 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1280 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1281 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1282 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1283 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1284 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1285 #define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */ 1286 #define SCTLR_TWEDEn (1ULL << 45) /* FEAT_TWED */ 1287 #define SCTLR_TWEDEL MAKE_64_MASK(46, 4) /* FEAT_TWED */ 1288 #define SCTLR_TMT0 (1ULL << 50) /* FEAT_TME */ 1289 #define SCTLR_TMT (1ULL << 51) /* FEAT_TME */ 1290 #define SCTLR_TME0 (1ULL << 52) /* FEAT_TME */ 1291 #define SCTLR_TME (1ULL << 53) /* FEAT_TME */ 1292 #define SCTLR_EnASR (1ULL << 54) /* FEAT_LS64_V */ 1293 #define SCTLR_EnAS0 (1ULL << 55) /* FEAT_LS64_ACCDATA */ 1294 #define SCTLR_EnALS (1ULL << 56) /* FEAT_LS64 */ 1295 #define SCTLR_EPAN (1ULL << 57) /* FEAT_PAN3 */ 1296 #define SCTLR_EnTP2 (1ULL << 60) /* FEAT_SME */ 1297 #define SCTLR_NMI (1ULL << 61) /* FEAT_NMI */ 1298 #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */ 1299 #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */ 1300 1301 /* Bit definitions for CPACR (AArch32 only) */ 1302 FIELD(CPACR, CP10, 20, 2) 1303 FIELD(CPACR, CP11, 22, 2) 1304 FIELD(CPACR, TRCDIS, 28, 1) /* matches CPACR_EL1.TTA */ 1305 FIELD(CPACR, D32DIS, 30, 1) /* up to v7; RAZ in v8 */ 1306 FIELD(CPACR, ASEDIS, 31, 1) 1307 1308 /* Bit definitions for CPACR_EL1 (AArch64 only) */ 1309 FIELD(CPACR_EL1, ZEN, 16, 2) 1310 FIELD(CPACR_EL1, FPEN, 20, 2) 1311 FIELD(CPACR_EL1, SMEN, 24, 2) 1312 FIELD(CPACR_EL1, TTA, 28, 1) /* matches CPACR.TRCDIS */ 1313 1314 /* Bit definitions for HCPTR (AArch32 only) */ 1315 FIELD(HCPTR, TCP10, 10, 1) 1316 FIELD(HCPTR, TCP11, 11, 1) 1317 FIELD(HCPTR, TASE, 15, 1) 1318 FIELD(HCPTR, TTA, 20, 1) 1319 FIELD(HCPTR, TAM, 30, 1) /* matches CPTR_EL2.TAM */ 1320 FIELD(HCPTR, TCPAC, 31, 1) /* matches CPTR_EL2.TCPAC */ 1321 1322 /* Bit definitions for CPTR_EL2 (AArch64 only) */ 1323 FIELD(CPTR_EL2, TZ, 8, 1) /* !E2H */ 1324 FIELD(CPTR_EL2, TFP, 10, 1) /* !E2H, matches HCPTR.TCP10 */ 1325 FIELD(CPTR_EL2, TSM, 12, 1) /* !E2H */ 1326 FIELD(CPTR_EL2, ZEN, 16, 2) /* E2H */ 1327 FIELD(CPTR_EL2, FPEN, 20, 2) /* E2H */ 1328 FIELD(CPTR_EL2, SMEN, 24, 2) /* E2H */ 1329 FIELD(CPTR_EL2, TTA, 28, 1) 1330 FIELD(CPTR_EL2, TAM, 30, 1) /* matches HCPTR.TAM */ 1331 FIELD(CPTR_EL2, TCPAC, 31, 1) /* matches HCPTR.TCPAC */ 1332 1333 /* Bit definitions for CPTR_EL3 (AArch64 only) */ 1334 FIELD(CPTR_EL3, EZ, 8, 1) 1335 FIELD(CPTR_EL3, TFP, 10, 1) 1336 FIELD(CPTR_EL3, ESM, 12, 1) 1337 FIELD(CPTR_EL3, TTA, 20, 1) 1338 FIELD(CPTR_EL3, TAM, 30, 1) 1339 FIELD(CPTR_EL3, TCPAC, 31, 1) 1340 1341 #define MDCR_EPMAD (1U << 21) 1342 #define MDCR_EDAD (1U << 20) 1343 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ 1344 #define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ 1345 #define MDCR_SDD (1U << 16) 1346 #define MDCR_SPD (3U << 14) 1347 #define MDCR_TDRA (1U << 11) 1348 #define MDCR_TDOSA (1U << 10) 1349 #define MDCR_TDA (1U << 9) 1350 #define MDCR_TDE (1U << 8) 1351 #define MDCR_HPME (1U << 7) 1352 #define MDCR_TPM (1U << 6) 1353 #define MDCR_TPMCR (1U << 5) 1354 #define MDCR_HPMN (0x1fU) 1355 1356 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 1357 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) 1358 1359 #define CPSR_M (0x1fU) 1360 #define CPSR_T (1U << 5) 1361 #define CPSR_F (1U << 6) 1362 #define CPSR_I (1U << 7) 1363 #define CPSR_A (1U << 8) 1364 #define CPSR_E (1U << 9) 1365 #define CPSR_IT_2_7 (0xfc00U) 1366 #define CPSR_GE (0xfU << 16) 1367 #define CPSR_IL (1U << 20) 1368 #define CPSR_DIT (1U << 21) 1369 #define CPSR_PAN (1U << 22) 1370 #define CPSR_SSBS (1U << 23) 1371 #define CPSR_J (1U << 24) 1372 #define CPSR_IT_0_1 (3U << 25) 1373 #define CPSR_Q (1U << 27) 1374 #define CPSR_V (1U << 28) 1375 #define CPSR_C (1U << 29) 1376 #define CPSR_Z (1U << 30) 1377 #define CPSR_N (1U << 31) 1378 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1379 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1380 1381 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1382 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1383 | CPSR_NZCV) 1384 /* Bits writable in user mode. */ 1385 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E) 1386 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1387 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1388 1389 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1390 #define XPSR_EXCP 0x1ffU 1391 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1392 #define XPSR_IT_2_7 CPSR_IT_2_7 1393 #define XPSR_GE CPSR_GE 1394 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1395 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1396 #define XPSR_IT_0_1 CPSR_IT_0_1 1397 #define XPSR_Q CPSR_Q 1398 #define XPSR_V CPSR_V 1399 #define XPSR_C CPSR_C 1400 #define XPSR_Z CPSR_Z 1401 #define XPSR_N CPSR_N 1402 #define XPSR_NZCV CPSR_NZCV 1403 #define XPSR_IT CPSR_IT 1404 1405 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 1406 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 1407 #define TTBCR_PD0 (1U << 4) 1408 #define TTBCR_PD1 (1U << 5) 1409 #define TTBCR_EPD0 (1U << 7) 1410 #define TTBCR_IRGN0 (3U << 8) 1411 #define TTBCR_ORGN0 (3U << 10) 1412 #define TTBCR_SH0 (3U << 12) 1413 #define TTBCR_T1SZ (3U << 16) 1414 #define TTBCR_A1 (1U << 22) 1415 #define TTBCR_EPD1 (1U << 23) 1416 #define TTBCR_IRGN1 (3U << 24) 1417 #define TTBCR_ORGN1 (3U << 26) 1418 #define TTBCR_SH1 (1U << 28) 1419 #define TTBCR_EAE (1U << 31) 1420 1421 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1422 * Only these are valid when in AArch64 mode; in 1423 * AArch32 mode SPSRs are basically CPSR-format. 1424 */ 1425 #define PSTATE_SP (1U) 1426 #define PSTATE_M (0xFU) 1427 #define PSTATE_nRW (1U << 4) 1428 #define PSTATE_F (1U << 6) 1429 #define PSTATE_I (1U << 7) 1430 #define PSTATE_A (1U << 8) 1431 #define PSTATE_D (1U << 9) 1432 #define PSTATE_BTYPE (3U << 10) 1433 #define PSTATE_SSBS (1U << 12) 1434 #define PSTATE_IL (1U << 20) 1435 #define PSTATE_SS (1U << 21) 1436 #define PSTATE_PAN (1U << 22) 1437 #define PSTATE_UAO (1U << 23) 1438 #define PSTATE_DIT (1U << 24) 1439 #define PSTATE_TCO (1U << 25) 1440 #define PSTATE_V (1U << 28) 1441 #define PSTATE_C (1U << 29) 1442 #define PSTATE_Z (1U << 30) 1443 #define PSTATE_N (1U << 31) 1444 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1445 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1446 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1447 /* Mode values for AArch64 */ 1448 #define PSTATE_MODE_EL3h 13 1449 #define PSTATE_MODE_EL3t 12 1450 #define PSTATE_MODE_EL2h 9 1451 #define PSTATE_MODE_EL2t 8 1452 #define PSTATE_MODE_EL1h 5 1453 #define PSTATE_MODE_EL1t 4 1454 #define PSTATE_MODE_EL0t 0 1455 1456 /* PSTATE bits that are accessed via SVCR and not stored in SPSR_ELx. */ 1457 FIELD(SVCR, SM, 0, 1) 1458 FIELD(SVCR, ZA, 1, 1) 1459 1460 /* Fields for SMCR_ELx. */ 1461 FIELD(SMCR, LEN, 0, 4) 1462 FIELD(SMCR, FA64, 31, 1) 1463 1464 /* Write a new value to v7m.exception, thus transitioning into or out 1465 * of Handler mode; this may result in a change of active stack pointer. 1466 */ 1467 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1468 1469 /* Map EL and handler into a PSTATE_MODE. */ 1470 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1471 { 1472 return (el << 2) | handler; 1473 } 1474 1475 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1476 * interprocessing, so we don't attempt to sync with the cpsr state used by 1477 * the 32 bit decoder. 1478 */ 1479 static inline uint32_t pstate_read(CPUARMState *env) 1480 { 1481 int ZF; 1482 1483 ZF = (env->ZF == 0); 1484 return (env->NF & 0x80000000) | (ZF << 30) 1485 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1486 | env->pstate | env->daif | (env->btype << 10); 1487 } 1488 1489 static inline void pstate_write(CPUARMState *env, uint32_t val) 1490 { 1491 env->ZF = (~val) & PSTATE_Z; 1492 env->NF = val; 1493 env->CF = (val >> 29) & 1; 1494 env->VF = (val << 3) & 0x80000000; 1495 env->daif = val & PSTATE_DAIF; 1496 env->btype = (val >> 10) & 3; 1497 env->pstate = val & ~CACHED_PSTATE_BITS; 1498 } 1499 1500 /* Return the current CPSR value. */ 1501 uint32_t cpsr_read(CPUARMState *env); 1502 1503 typedef enum CPSRWriteType { 1504 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1505 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1506 CPSRWriteRaw = 2, 1507 /* trust values, no reg bank switch, no hflags rebuild */ 1508 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1509 } CPSRWriteType; 1510 1511 /* 1512 * Set the CPSR. Note that some bits of mask must be all-set or all-clear. 1513 * This will do an arm_rebuild_hflags() if any of the bits in @mask 1514 * correspond to TB flags bits cached in the hflags, unless @write_type 1515 * is CPSRWriteRaw. 1516 */ 1517 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1518 CPSRWriteType write_type); 1519 1520 /* Return the current xPSR value. */ 1521 static inline uint32_t xpsr_read(CPUARMState *env) 1522 { 1523 int ZF; 1524 ZF = (env->ZF == 0); 1525 return (env->NF & 0x80000000) | (ZF << 30) 1526 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1527 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1528 | ((env->condexec_bits & 0xfc) << 8) 1529 | (env->GE << 16) 1530 | env->v7m.exception; 1531 } 1532 1533 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1534 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1535 { 1536 if (mask & XPSR_NZCV) { 1537 env->ZF = (~val) & XPSR_Z; 1538 env->NF = val; 1539 env->CF = (val >> 29) & 1; 1540 env->VF = (val << 3) & 0x80000000; 1541 } 1542 if (mask & XPSR_Q) { 1543 env->QF = ((val & XPSR_Q) != 0); 1544 } 1545 if (mask & XPSR_GE) { 1546 env->GE = (val & XPSR_GE) >> 16; 1547 } 1548 #ifndef CONFIG_USER_ONLY 1549 if (mask & XPSR_T) { 1550 env->thumb = ((val & XPSR_T) != 0); 1551 } 1552 if (mask & XPSR_IT_0_1) { 1553 env->condexec_bits &= ~3; 1554 env->condexec_bits |= (val >> 25) & 3; 1555 } 1556 if (mask & XPSR_IT_2_7) { 1557 env->condexec_bits &= 3; 1558 env->condexec_bits |= (val >> 8) & 0xfc; 1559 } 1560 if (mask & XPSR_EXCP) { 1561 /* Note that this only happens on exception exit */ 1562 write_v7m_exception(env, val & XPSR_EXCP); 1563 } 1564 #endif 1565 } 1566 1567 #define HCR_VM (1ULL << 0) 1568 #define HCR_SWIO (1ULL << 1) 1569 #define HCR_PTW (1ULL << 2) 1570 #define HCR_FMO (1ULL << 3) 1571 #define HCR_IMO (1ULL << 4) 1572 #define HCR_AMO (1ULL << 5) 1573 #define HCR_VF (1ULL << 6) 1574 #define HCR_VI (1ULL << 7) 1575 #define HCR_VSE (1ULL << 8) 1576 #define HCR_FB (1ULL << 9) 1577 #define HCR_BSU_MASK (3ULL << 10) 1578 #define HCR_DC (1ULL << 12) 1579 #define HCR_TWI (1ULL << 13) 1580 #define HCR_TWE (1ULL << 14) 1581 #define HCR_TID0 (1ULL << 15) 1582 #define HCR_TID1 (1ULL << 16) 1583 #define HCR_TID2 (1ULL << 17) 1584 #define HCR_TID3 (1ULL << 18) 1585 #define HCR_TSC (1ULL << 19) 1586 #define HCR_TIDCP (1ULL << 20) 1587 #define HCR_TACR (1ULL << 21) 1588 #define HCR_TSW (1ULL << 22) 1589 #define HCR_TPCP (1ULL << 23) 1590 #define HCR_TPU (1ULL << 24) 1591 #define HCR_TTLB (1ULL << 25) 1592 #define HCR_TVM (1ULL << 26) 1593 #define HCR_TGE (1ULL << 27) 1594 #define HCR_TDZ (1ULL << 28) 1595 #define HCR_HCD (1ULL << 29) 1596 #define HCR_TRVM (1ULL << 30) 1597 #define HCR_RW (1ULL << 31) 1598 #define HCR_CD (1ULL << 32) 1599 #define HCR_ID (1ULL << 33) 1600 #define HCR_E2H (1ULL << 34) 1601 #define HCR_TLOR (1ULL << 35) 1602 #define HCR_TERR (1ULL << 36) 1603 #define HCR_TEA (1ULL << 37) 1604 #define HCR_MIOCNCE (1ULL << 38) 1605 /* RES0 bit 39 */ 1606 #define HCR_APK (1ULL << 40) 1607 #define HCR_API (1ULL << 41) 1608 #define HCR_NV (1ULL << 42) 1609 #define HCR_NV1 (1ULL << 43) 1610 #define HCR_AT (1ULL << 44) 1611 #define HCR_NV2 (1ULL << 45) 1612 #define HCR_FWB (1ULL << 46) 1613 #define HCR_FIEN (1ULL << 47) 1614 /* RES0 bit 48 */ 1615 #define HCR_TID4 (1ULL << 49) 1616 #define HCR_TICAB (1ULL << 50) 1617 #define HCR_AMVOFFEN (1ULL << 51) 1618 #define HCR_TOCU (1ULL << 52) 1619 #define HCR_ENSCXT (1ULL << 53) 1620 #define HCR_TTLBIS (1ULL << 54) 1621 #define HCR_TTLBOS (1ULL << 55) 1622 #define HCR_ATA (1ULL << 56) 1623 #define HCR_DCT (1ULL << 57) 1624 #define HCR_TID5 (1ULL << 58) 1625 #define HCR_TWEDEN (1ULL << 59) 1626 #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) 1627 1628 #define HCRX_ENAS0 (1ULL << 0) 1629 #define HCRX_ENALS (1ULL << 1) 1630 #define HCRX_ENASR (1ULL << 2) 1631 #define HCRX_FNXS (1ULL << 3) 1632 #define HCRX_FGTNXS (1ULL << 4) 1633 #define HCRX_SMPME (1ULL << 5) 1634 #define HCRX_TALLINT (1ULL << 6) 1635 #define HCRX_VINMI (1ULL << 7) 1636 #define HCRX_VFNMI (1ULL << 8) 1637 #define HCRX_CMOW (1ULL << 9) 1638 #define HCRX_MCE2 (1ULL << 10) 1639 #define HCRX_MSCEN (1ULL << 11) 1640 1641 #define HPFAR_NS (1ULL << 63) 1642 1643 #define SCR_NS (1U << 0) 1644 #define SCR_IRQ (1U << 1) 1645 #define SCR_FIQ (1U << 2) 1646 #define SCR_EA (1U << 3) 1647 #define SCR_FW (1U << 4) 1648 #define SCR_AW (1U << 5) 1649 #define SCR_NET (1U << 6) 1650 #define SCR_SMD (1U << 7) 1651 #define SCR_HCE (1U << 8) 1652 #define SCR_SIF (1U << 9) 1653 #define SCR_RW (1U << 10) 1654 #define SCR_ST (1U << 11) 1655 #define SCR_TWI (1U << 12) 1656 #define SCR_TWE (1U << 13) 1657 #define SCR_TLOR (1U << 14) 1658 #define SCR_TERR (1U << 15) 1659 #define SCR_APK (1U << 16) 1660 #define SCR_API (1U << 17) 1661 #define SCR_EEL2 (1U << 18) 1662 #define SCR_EASE (1U << 19) 1663 #define SCR_NMEA (1U << 20) 1664 #define SCR_FIEN (1U << 21) 1665 #define SCR_ENSCXT (1U << 25) 1666 #define SCR_ATA (1U << 26) 1667 #define SCR_FGTEN (1U << 27) 1668 #define SCR_ECVEN (1U << 28) 1669 #define SCR_TWEDEN (1U << 29) 1670 #define SCR_TWEDEL MAKE_64BIT_MASK(30, 4) 1671 #define SCR_TME (1ULL << 34) 1672 #define SCR_AMVOFFEN (1ULL << 35) 1673 #define SCR_ENAS0 (1ULL << 36) 1674 #define SCR_ADEN (1ULL << 37) 1675 #define SCR_HXEN (1ULL << 38) 1676 #define SCR_TRNDR (1ULL << 40) 1677 #define SCR_ENTP2 (1ULL << 41) 1678 #define SCR_GPF (1ULL << 48) 1679 1680 #define HSTR_TTEE (1 << 16) 1681 #define HSTR_TJDBX (1 << 17) 1682 1683 /* Return the current FPSCR value. */ 1684 uint32_t vfp_get_fpscr(CPUARMState *env); 1685 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1686 1687 /* FPCR, Floating Point Control Register 1688 * FPSR, Floating Poiht Status Register 1689 * 1690 * For A64 the FPSCR is split into two logically distinct registers, 1691 * FPCR and FPSR. However since they still use non-overlapping bits 1692 * we store the underlying state in fpscr and just mask on read/write. 1693 */ 1694 #define FPSR_MASK 0xf800009f 1695 #define FPCR_MASK 0x07ff9f00 1696 1697 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1698 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1699 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1700 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1701 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1702 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1703 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1704 #define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */ 1705 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1706 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1707 #define FPCR_AHP (1 << 26) /* Alternative half-precision */ 1708 #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ 1709 #define FPCR_V (1 << 28) /* FP overflow flag */ 1710 #define FPCR_C (1 << 29) /* FP carry flag */ 1711 #define FPCR_Z (1 << 30) /* FP zero flag */ 1712 #define FPCR_N (1 << 31) /* FP negative flag */ 1713 1714 #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */ 1715 #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT) 1716 #define FPCR_LTPSIZE_LENGTH 3 1717 1718 #define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V) 1719 #define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC) 1720 1721 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1722 { 1723 return vfp_get_fpscr(env) & FPSR_MASK; 1724 } 1725 1726 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1727 { 1728 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1729 vfp_set_fpscr(env, new_fpscr); 1730 } 1731 1732 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1733 { 1734 return vfp_get_fpscr(env) & FPCR_MASK; 1735 } 1736 1737 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1738 { 1739 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1740 vfp_set_fpscr(env, new_fpscr); 1741 } 1742 1743 enum arm_cpu_mode { 1744 ARM_CPU_MODE_USR = 0x10, 1745 ARM_CPU_MODE_FIQ = 0x11, 1746 ARM_CPU_MODE_IRQ = 0x12, 1747 ARM_CPU_MODE_SVC = 0x13, 1748 ARM_CPU_MODE_MON = 0x16, 1749 ARM_CPU_MODE_ABT = 0x17, 1750 ARM_CPU_MODE_HYP = 0x1a, 1751 ARM_CPU_MODE_UND = 0x1b, 1752 ARM_CPU_MODE_SYS = 0x1f 1753 }; 1754 1755 /* VFP system registers. */ 1756 #define ARM_VFP_FPSID 0 1757 #define ARM_VFP_FPSCR 1 1758 #define ARM_VFP_MVFR2 5 1759 #define ARM_VFP_MVFR1 6 1760 #define ARM_VFP_MVFR0 7 1761 #define ARM_VFP_FPEXC 8 1762 #define ARM_VFP_FPINST 9 1763 #define ARM_VFP_FPINST2 10 1764 /* These ones are M-profile only */ 1765 #define ARM_VFP_FPSCR_NZCVQC 2 1766 #define ARM_VFP_VPR 12 1767 #define ARM_VFP_P0 13 1768 #define ARM_VFP_FPCXT_NS 14 1769 #define ARM_VFP_FPCXT_S 15 1770 1771 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */ 1772 #define QEMU_VFP_FPSCR_NZCV 0xffff 1773 1774 /* iwMMXt coprocessor control registers. */ 1775 #define ARM_IWMMXT_wCID 0 1776 #define ARM_IWMMXT_wCon 1 1777 #define ARM_IWMMXT_wCSSF 2 1778 #define ARM_IWMMXT_wCASF 3 1779 #define ARM_IWMMXT_wCGR0 8 1780 #define ARM_IWMMXT_wCGR1 9 1781 #define ARM_IWMMXT_wCGR2 10 1782 #define ARM_IWMMXT_wCGR3 11 1783 1784 /* V7M CCR bits */ 1785 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1786 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1787 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1788 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1789 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1790 FIELD(V7M_CCR, STKALIGN, 9, 1) 1791 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1792 FIELD(V7M_CCR, DC, 16, 1) 1793 FIELD(V7M_CCR, IC, 17, 1) 1794 FIELD(V7M_CCR, BP, 18, 1) 1795 FIELD(V7M_CCR, LOB, 19, 1) 1796 FIELD(V7M_CCR, TRD, 20, 1) 1797 1798 /* V7M SCR bits */ 1799 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1800 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1801 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1802 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1803 1804 /* V7M AIRCR bits */ 1805 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1806 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1807 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1808 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1809 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1810 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1811 FIELD(V7M_AIRCR, PRIS, 14, 1) 1812 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1813 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1814 1815 /* V7M CFSR bits for MMFSR */ 1816 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1817 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1818 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1819 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1820 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1821 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1822 1823 /* V7M CFSR bits for BFSR */ 1824 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1825 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1826 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1827 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1828 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1829 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1830 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1831 1832 /* V7M CFSR bits for UFSR */ 1833 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1834 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1835 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1836 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1837 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1838 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1839 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1840 1841 /* V7M CFSR bit masks covering all of the subregister bits */ 1842 FIELD(V7M_CFSR, MMFSR, 0, 8) 1843 FIELD(V7M_CFSR, BFSR, 8, 8) 1844 FIELD(V7M_CFSR, UFSR, 16, 16) 1845 1846 /* V7M HFSR bits */ 1847 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1848 FIELD(V7M_HFSR, FORCED, 30, 1) 1849 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1850 1851 /* V7M DFSR bits */ 1852 FIELD(V7M_DFSR, HALTED, 0, 1) 1853 FIELD(V7M_DFSR, BKPT, 1, 1) 1854 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1855 FIELD(V7M_DFSR, VCATCH, 3, 1) 1856 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1857 1858 /* V7M SFSR bits */ 1859 FIELD(V7M_SFSR, INVEP, 0, 1) 1860 FIELD(V7M_SFSR, INVIS, 1, 1) 1861 FIELD(V7M_SFSR, INVER, 2, 1) 1862 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1863 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1864 FIELD(V7M_SFSR, LSPERR, 5, 1) 1865 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1866 FIELD(V7M_SFSR, LSERR, 7, 1) 1867 1868 /* v7M MPU_CTRL bits */ 1869 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1870 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1871 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1872 1873 /* v7M CLIDR bits */ 1874 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1875 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1876 FIELD(V7M_CLIDR, LOC, 24, 3) 1877 FIELD(V7M_CLIDR, LOUU, 27, 3) 1878 FIELD(V7M_CLIDR, ICB, 30, 2) 1879 1880 FIELD(V7M_CSSELR, IND, 0, 1) 1881 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1882 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1883 * define a mask for this and check that it doesn't permit running off 1884 * the end of the array. 1885 */ 1886 FIELD(V7M_CSSELR, INDEX, 0, 4) 1887 1888 /* v7M FPCCR bits */ 1889 FIELD(V7M_FPCCR, LSPACT, 0, 1) 1890 FIELD(V7M_FPCCR, USER, 1, 1) 1891 FIELD(V7M_FPCCR, S, 2, 1) 1892 FIELD(V7M_FPCCR, THREAD, 3, 1) 1893 FIELD(V7M_FPCCR, HFRDY, 4, 1) 1894 FIELD(V7M_FPCCR, MMRDY, 5, 1) 1895 FIELD(V7M_FPCCR, BFRDY, 6, 1) 1896 FIELD(V7M_FPCCR, SFRDY, 7, 1) 1897 FIELD(V7M_FPCCR, MONRDY, 8, 1) 1898 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) 1899 FIELD(V7M_FPCCR, UFRDY, 10, 1) 1900 FIELD(V7M_FPCCR, RES0, 11, 15) 1901 FIELD(V7M_FPCCR, TS, 26, 1) 1902 FIELD(V7M_FPCCR, CLRONRETS, 27, 1) 1903 FIELD(V7M_FPCCR, CLRONRET, 28, 1) 1904 FIELD(V7M_FPCCR, LSPENS, 29, 1) 1905 FIELD(V7M_FPCCR, LSPEN, 30, 1) 1906 FIELD(V7M_FPCCR, ASPEN, 31, 1) 1907 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */ 1908 #define R_V7M_FPCCR_BANKED_MASK \ 1909 (R_V7M_FPCCR_LSPACT_MASK | \ 1910 R_V7M_FPCCR_USER_MASK | \ 1911 R_V7M_FPCCR_THREAD_MASK | \ 1912 R_V7M_FPCCR_MMRDY_MASK | \ 1913 R_V7M_FPCCR_SPLIMVIOL_MASK | \ 1914 R_V7M_FPCCR_UFRDY_MASK | \ 1915 R_V7M_FPCCR_ASPEN_MASK) 1916 1917 /* v7M VPR bits */ 1918 FIELD(V7M_VPR, P0, 0, 16) 1919 FIELD(V7M_VPR, MASK01, 16, 4) 1920 FIELD(V7M_VPR, MASK23, 20, 4) 1921 1922 /* 1923 * System register ID fields. 1924 */ 1925 FIELD(CLIDR_EL1, CTYPE1, 0, 3) 1926 FIELD(CLIDR_EL1, CTYPE2, 3, 3) 1927 FIELD(CLIDR_EL1, CTYPE3, 6, 3) 1928 FIELD(CLIDR_EL1, CTYPE4, 9, 3) 1929 FIELD(CLIDR_EL1, CTYPE5, 12, 3) 1930 FIELD(CLIDR_EL1, CTYPE6, 15, 3) 1931 FIELD(CLIDR_EL1, CTYPE7, 18, 3) 1932 FIELD(CLIDR_EL1, LOUIS, 21, 3) 1933 FIELD(CLIDR_EL1, LOC, 24, 3) 1934 FIELD(CLIDR_EL1, LOUU, 27, 3) 1935 FIELD(CLIDR_EL1, ICB, 30, 3) 1936 1937 /* When FEAT_CCIDX is implemented */ 1938 FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3) 1939 FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21) 1940 FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24) 1941 1942 /* When FEAT_CCIDX is not implemented */ 1943 FIELD(CCSIDR_EL1, LINESIZE, 0, 3) 1944 FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10) 1945 FIELD(CCSIDR_EL1, NUMSETS, 13, 15) 1946 1947 FIELD(CTR_EL0, IMINLINE, 0, 4) 1948 FIELD(CTR_EL0, L1IP, 14, 2) 1949 FIELD(CTR_EL0, DMINLINE, 16, 4) 1950 FIELD(CTR_EL0, ERG, 20, 4) 1951 FIELD(CTR_EL0, CWG, 24, 4) 1952 FIELD(CTR_EL0, IDC, 28, 1) 1953 FIELD(CTR_EL0, DIC, 29, 1) 1954 FIELD(CTR_EL0, TMINLINE, 32, 6) 1955 1956 FIELD(MIDR_EL1, REVISION, 0, 4) 1957 FIELD(MIDR_EL1, PARTNUM, 4, 12) 1958 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) 1959 FIELD(MIDR_EL1, VARIANT, 20, 4) 1960 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) 1961 1962 FIELD(ID_ISAR0, SWAP, 0, 4) 1963 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 1964 FIELD(ID_ISAR0, BITFIELD, 8, 4) 1965 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 1966 FIELD(ID_ISAR0, COPROC, 16, 4) 1967 FIELD(ID_ISAR0, DEBUG, 20, 4) 1968 FIELD(ID_ISAR0, DIVIDE, 24, 4) 1969 1970 FIELD(ID_ISAR1, ENDIAN, 0, 4) 1971 FIELD(ID_ISAR1, EXCEPT, 4, 4) 1972 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 1973 FIELD(ID_ISAR1, EXTEND, 12, 4) 1974 FIELD(ID_ISAR1, IFTHEN, 16, 4) 1975 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 1976 FIELD(ID_ISAR1, INTERWORK, 24, 4) 1977 FIELD(ID_ISAR1, JAZELLE, 28, 4) 1978 1979 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 1980 FIELD(ID_ISAR2, MEMHINT, 4, 4) 1981 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 1982 FIELD(ID_ISAR2, MULT, 12, 4) 1983 FIELD(ID_ISAR2, MULTS, 16, 4) 1984 FIELD(ID_ISAR2, MULTU, 20, 4) 1985 FIELD(ID_ISAR2, PSR_AR, 24, 4) 1986 FIELD(ID_ISAR2, REVERSAL, 28, 4) 1987 1988 FIELD(ID_ISAR3, SATURATE, 0, 4) 1989 FIELD(ID_ISAR3, SIMD, 4, 4) 1990 FIELD(ID_ISAR3, SVC, 8, 4) 1991 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 1992 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 1993 FIELD(ID_ISAR3, T32COPY, 20, 4) 1994 FIELD(ID_ISAR3, TRUENOP, 24, 4) 1995 FIELD(ID_ISAR3, T32EE, 28, 4) 1996 1997 FIELD(ID_ISAR4, UNPRIV, 0, 4) 1998 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 1999 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 2000 FIELD(ID_ISAR4, SMC, 12, 4) 2001 FIELD(ID_ISAR4, BARRIER, 16, 4) 2002 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 2003 FIELD(ID_ISAR4, PSR_M, 24, 4) 2004 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 2005 2006 FIELD(ID_ISAR5, SEVL, 0, 4) 2007 FIELD(ID_ISAR5, AES, 4, 4) 2008 FIELD(ID_ISAR5, SHA1, 8, 4) 2009 FIELD(ID_ISAR5, SHA2, 12, 4) 2010 FIELD(ID_ISAR5, CRC32, 16, 4) 2011 FIELD(ID_ISAR5, RDM, 24, 4) 2012 FIELD(ID_ISAR5, VCMA, 28, 4) 2013 2014 FIELD(ID_ISAR6, JSCVT, 0, 4) 2015 FIELD(ID_ISAR6, DP, 4, 4) 2016 FIELD(ID_ISAR6, FHM, 8, 4) 2017 FIELD(ID_ISAR6, SB, 12, 4) 2018 FIELD(ID_ISAR6, SPECRES, 16, 4) 2019 FIELD(ID_ISAR6, BF16, 20, 4) 2020 FIELD(ID_ISAR6, I8MM, 24, 4) 2021 2022 FIELD(ID_MMFR0, VMSA, 0, 4) 2023 FIELD(ID_MMFR0, PMSA, 4, 4) 2024 FIELD(ID_MMFR0, OUTERSHR, 8, 4) 2025 FIELD(ID_MMFR0, SHARELVL, 12, 4) 2026 FIELD(ID_MMFR0, TCM, 16, 4) 2027 FIELD(ID_MMFR0, AUXREG, 20, 4) 2028 FIELD(ID_MMFR0, FCSE, 24, 4) 2029 FIELD(ID_MMFR0, INNERSHR, 28, 4) 2030 2031 FIELD(ID_MMFR1, L1HVDVA, 0, 4) 2032 FIELD(ID_MMFR1, L1UNIVA, 4, 4) 2033 FIELD(ID_MMFR1, L1HVDSW, 8, 4) 2034 FIELD(ID_MMFR1, L1UNISW, 12, 4) 2035 FIELD(ID_MMFR1, L1HVD, 16, 4) 2036 FIELD(ID_MMFR1, L1UNI, 20, 4) 2037 FIELD(ID_MMFR1, L1TSTCLN, 24, 4) 2038 FIELD(ID_MMFR1, BPRED, 28, 4) 2039 2040 FIELD(ID_MMFR2, L1HVDFG, 0, 4) 2041 FIELD(ID_MMFR2, L1HVDBG, 4, 4) 2042 FIELD(ID_MMFR2, L1HVDRNG, 8, 4) 2043 FIELD(ID_MMFR2, HVDTLB, 12, 4) 2044 FIELD(ID_MMFR2, UNITLB, 16, 4) 2045 FIELD(ID_MMFR2, MEMBARR, 20, 4) 2046 FIELD(ID_MMFR2, WFISTALL, 24, 4) 2047 FIELD(ID_MMFR2, HWACCFLG, 28, 4) 2048 2049 FIELD(ID_MMFR3, CMAINTVA, 0, 4) 2050 FIELD(ID_MMFR3, CMAINTSW, 4, 4) 2051 FIELD(ID_MMFR3, BPMAINT, 8, 4) 2052 FIELD(ID_MMFR3, MAINTBCST, 12, 4) 2053 FIELD(ID_MMFR3, PAN, 16, 4) 2054 FIELD(ID_MMFR3, COHWALK, 20, 4) 2055 FIELD(ID_MMFR3, CMEMSZ, 24, 4) 2056 FIELD(ID_MMFR3, SUPERSEC, 28, 4) 2057 2058 FIELD(ID_MMFR4, SPECSEI, 0, 4) 2059 FIELD(ID_MMFR4, AC2, 4, 4) 2060 FIELD(ID_MMFR4, XNX, 8, 4) 2061 FIELD(ID_MMFR4, CNP, 12, 4) 2062 FIELD(ID_MMFR4, HPDS, 16, 4) 2063 FIELD(ID_MMFR4, LSM, 20, 4) 2064 FIELD(ID_MMFR4, CCIDX, 24, 4) 2065 FIELD(ID_MMFR4, EVT, 28, 4) 2066 2067 FIELD(ID_MMFR5, ETS, 0, 4) 2068 FIELD(ID_MMFR5, NTLBPA, 4, 4) 2069 2070 FIELD(ID_PFR0, STATE0, 0, 4) 2071 FIELD(ID_PFR0, STATE1, 4, 4) 2072 FIELD(ID_PFR0, STATE2, 8, 4) 2073 FIELD(ID_PFR0, STATE3, 12, 4) 2074 FIELD(ID_PFR0, CSV2, 16, 4) 2075 FIELD(ID_PFR0, AMU, 20, 4) 2076 FIELD(ID_PFR0, DIT, 24, 4) 2077 FIELD(ID_PFR0, RAS, 28, 4) 2078 2079 FIELD(ID_PFR1, PROGMOD, 0, 4) 2080 FIELD(ID_PFR1, SECURITY, 4, 4) 2081 FIELD(ID_PFR1, MPROGMOD, 8, 4) 2082 FIELD(ID_PFR1, VIRTUALIZATION, 12, 4) 2083 FIELD(ID_PFR1, GENTIMER, 16, 4) 2084 FIELD(ID_PFR1, SEC_FRAC, 20, 4) 2085 FIELD(ID_PFR1, VIRT_FRAC, 24, 4) 2086 FIELD(ID_PFR1, GIC, 28, 4) 2087 2088 FIELD(ID_PFR2, CSV3, 0, 4) 2089 FIELD(ID_PFR2, SSBS, 4, 4) 2090 FIELD(ID_PFR2, RAS_FRAC, 8, 4) 2091 2092 FIELD(ID_AA64ISAR0, AES, 4, 4) 2093 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 2094 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 2095 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 2096 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 2097 FIELD(ID_AA64ISAR0, RDM, 28, 4) 2098 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 2099 FIELD(ID_AA64ISAR0, SM3, 36, 4) 2100 FIELD(ID_AA64ISAR0, SM4, 40, 4) 2101 FIELD(ID_AA64ISAR0, DP, 44, 4) 2102 FIELD(ID_AA64ISAR0, FHM, 48, 4) 2103 FIELD(ID_AA64ISAR0, TS, 52, 4) 2104 FIELD(ID_AA64ISAR0, TLB, 56, 4) 2105 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 2106 2107 FIELD(ID_AA64ISAR1, DPB, 0, 4) 2108 FIELD(ID_AA64ISAR1, APA, 4, 4) 2109 FIELD(ID_AA64ISAR1, API, 8, 4) 2110 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 2111 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 2112 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 2113 FIELD(ID_AA64ISAR1, GPA, 24, 4) 2114 FIELD(ID_AA64ISAR1, GPI, 28, 4) 2115 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 2116 FIELD(ID_AA64ISAR1, SB, 36, 4) 2117 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 2118 FIELD(ID_AA64ISAR1, BF16, 44, 4) 2119 FIELD(ID_AA64ISAR1, DGH, 48, 4) 2120 FIELD(ID_AA64ISAR1, I8MM, 52, 4) 2121 FIELD(ID_AA64ISAR1, XS, 56, 4) 2122 FIELD(ID_AA64ISAR1, LS64, 60, 4) 2123 2124 FIELD(ID_AA64ISAR2, WFXT, 0, 4) 2125 FIELD(ID_AA64ISAR2, RPRES, 4, 4) 2126 FIELD(ID_AA64ISAR2, GPA3, 8, 4) 2127 FIELD(ID_AA64ISAR2, APA3, 12, 4) 2128 FIELD(ID_AA64ISAR2, MOPS, 16, 4) 2129 FIELD(ID_AA64ISAR2, BC, 20, 4) 2130 FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4) 2131 2132 FIELD(ID_AA64PFR0, EL0, 0, 4) 2133 FIELD(ID_AA64PFR0, EL1, 4, 4) 2134 FIELD(ID_AA64PFR0, EL2, 8, 4) 2135 FIELD(ID_AA64PFR0, EL3, 12, 4) 2136 FIELD(ID_AA64PFR0, FP, 16, 4) 2137 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 2138 FIELD(ID_AA64PFR0, GIC, 24, 4) 2139 FIELD(ID_AA64PFR0, RAS, 28, 4) 2140 FIELD(ID_AA64PFR0, SVE, 32, 4) 2141 FIELD(ID_AA64PFR0, SEL2, 36, 4) 2142 FIELD(ID_AA64PFR0, MPAM, 40, 4) 2143 FIELD(ID_AA64PFR0, AMU, 44, 4) 2144 FIELD(ID_AA64PFR0, DIT, 48, 4) 2145 FIELD(ID_AA64PFR0, CSV2, 56, 4) 2146 FIELD(ID_AA64PFR0, CSV3, 60, 4) 2147 2148 FIELD(ID_AA64PFR1, BT, 0, 4) 2149 FIELD(ID_AA64PFR1, SSBS, 4, 4) 2150 FIELD(ID_AA64PFR1, MTE, 8, 4) 2151 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 2152 FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) 2153 FIELD(ID_AA64PFR1, SME, 24, 4) 2154 FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4) 2155 FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4) 2156 FIELD(ID_AA64PFR1, NMI, 36, 4) 2157 2158 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 2159 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 2160 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 2161 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 2162 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 2163 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 2164 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 2165 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 2166 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 2167 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 2168 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 2169 FIELD(ID_AA64MMFR0, EXS, 44, 4) 2170 FIELD(ID_AA64MMFR0, FGT, 56, 4) 2171 FIELD(ID_AA64MMFR0, ECV, 60, 4) 2172 2173 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 2174 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 2175 FIELD(ID_AA64MMFR1, VH, 8, 4) 2176 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 2177 FIELD(ID_AA64MMFR1, LO, 16, 4) 2178 FIELD(ID_AA64MMFR1, PAN, 20, 4) 2179 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 2180 FIELD(ID_AA64MMFR1, XNX, 28, 4) 2181 FIELD(ID_AA64MMFR1, TWED, 32, 4) 2182 FIELD(ID_AA64MMFR1, ETS, 36, 4) 2183 FIELD(ID_AA64MMFR1, HCX, 40, 4) 2184 FIELD(ID_AA64MMFR1, AFP, 44, 4) 2185 FIELD(ID_AA64MMFR1, NTLBPA, 48, 4) 2186 FIELD(ID_AA64MMFR1, TIDCP1, 52, 4) 2187 FIELD(ID_AA64MMFR1, CMOW, 56, 4) 2188 2189 FIELD(ID_AA64MMFR2, CNP, 0, 4) 2190 FIELD(ID_AA64MMFR2, UAO, 4, 4) 2191 FIELD(ID_AA64MMFR2, LSM, 8, 4) 2192 FIELD(ID_AA64MMFR2, IESB, 12, 4) 2193 FIELD(ID_AA64MMFR2, VARANGE, 16, 4) 2194 FIELD(ID_AA64MMFR2, CCIDX, 20, 4) 2195 FIELD(ID_AA64MMFR2, NV, 24, 4) 2196 FIELD(ID_AA64MMFR2, ST, 28, 4) 2197 FIELD(ID_AA64MMFR2, AT, 32, 4) 2198 FIELD(ID_AA64MMFR2, IDS, 36, 4) 2199 FIELD(ID_AA64MMFR2, FWB, 40, 4) 2200 FIELD(ID_AA64MMFR2, TTL, 48, 4) 2201 FIELD(ID_AA64MMFR2, BBM, 52, 4) 2202 FIELD(ID_AA64MMFR2, EVT, 56, 4) 2203 FIELD(ID_AA64MMFR2, E0PD, 60, 4) 2204 2205 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) 2206 FIELD(ID_AA64DFR0, TRACEVER, 4, 4) 2207 FIELD(ID_AA64DFR0, PMUVER, 8, 4) 2208 FIELD(ID_AA64DFR0, BRPS, 12, 4) 2209 FIELD(ID_AA64DFR0, WRPS, 20, 4) 2210 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) 2211 FIELD(ID_AA64DFR0, PMSVER, 32, 4) 2212 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) 2213 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) 2214 FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4) 2215 FIELD(ID_AA64DFR0, MTPMU, 48, 4) 2216 FIELD(ID_AA64DFR0, BRBE, 52, 4) 2217 FIELD(ID_AA64DFR0, HPMN0, 60, 4) 2218 2219 FIELD(ID_AA64ZFR0, SVEVER, 0, 4) 2220 FIELD(ID_AA64ZFR0, AES, 4, 4) 2221 FIELD(ID_AA64ZFR0, BITPERM, 16, 4) 2222 FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4) 2223 FIELD(ID_AA64ZFR0, SHA3, 32, 4) 2224 FIELD(ID_AA64ZFR0, SM4, 40, 4) 2225 FIELD(ID_AA64ZFR0, I8MM, 44, 4) 2226 FIELD(ID_AA64ZFR0, F32MM, 52, 4) 2227 FIELD(ID_AA64ZFR0, F64MM, 56, 4) 2228 2229 FIELD(ID_AA64SMFR0, F32F32, 32, 1) 2230 FIELD(ID_AA64SMFR0, B16F32, 34, 1) 2231 FIELD(ID_AA64SMFR0, F16F32, 35, 1) 2232 FIELD(ID_AA64SMFR0, I8I32, 36, 4) 2233 FIELD(ID_AA64SMFR0, F64F64, 48, 1) 2234 FIELD(ID_AA64SMFR0, I16I64, 52, 4) 2235 FIELD(ID_AA64SMFR0, SMEVER, 56, 4) 2236 FIELD(ID_AA64SMFR0, FA64, 63, 1) 2237 2238 FIELD(ID_DFR0, COPDBG, 0, 4) 2239 FIELD(ID_DFR0, COPSDBG, 4, 4) 2240 FIELD(ID_DFR0, MMAPDBG, 8, 4) 2241 FIELD(ID_DFR0, COPTRC, 12, 4) 2242 FIELD(ID_DFR0, MMAPTRC, 16, 4) 2243 FIELD(ID_DFR0, MPROFDBG, 20, 4) 2244 FIELD(ID_DFR0, PERFMON, 24, 4) 2245 FIELD(ID_DFR0, TRACEFILT, 28, 4) 2246 2247 FIELD(ID_DFR1, MTPMU, 0, 4) 2248 FIELD(ID_DFR1, HPMN0, 4, 4) 2249 2250 FIELD(DBGDIDR, SE_IMP, 12, 1) 2251 FIELD(DBGDIDR, NSUHD_IMP, 14, 1) 2252 FIELD(DBGDIDR, VERSION, 16, 4) 2253 FIELD(DBGDIDR, CTX_CMPS, 20, 4) 2254 FIELD(DBGDIDR, BRPS, 24, 4) 2255 FIELD(DBGDIDR, WRPS, 28, 4) 2256 2257 FIELD(DBGDEVID, PCSAMPLE, 0, 4) 2258 FIELD(DBGDEVID, WPADDRMASK, 4, 4) 2259 FIELD(DBGDEVID, BPADDRMASK, 8, 4) 2260 FIELD(DBGDEVID, VECTORCATCH, 12, 4) 2261 FIELD(DBGDEVID, VIRTEXTNS, 16, 4) 2262 FIELD(DBGDEVID, DOUBLELOCK, 20, 4) 2263 FIELD(DBGDEVID, AUXREGS, 24, 4) 2264 FIELD(DBGDEVID, CIDMASK, 28, 4) 2265 2266 FIELD(MVFR0, SIMDREG, 0, 4) 2267 FIELD(MVFR0, FPSP, 4, 4) 2268 FIELD(MVFR0, FPDP, 8, 4) 2269 FIELD(MVFR0, FPTRAP, 12, 4) 2270 FIELD(MVFR0, FPDIVIDE, 16, 4) 2271 FIELD(MVFR0, FPSQRT, 20, 4) 2272 FIELD(MVFR0, FPSHVEC, 24, 4) 2273 FIELD(MVFR0, FPROUND, 28, 4) 2274 2275 FIELD(MVFR1, FPFTZ, 0, 4) 2276 FIELD(MVFR1, FPDNAN, 4, 4) 2277 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */ 2278 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */ 2279 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */ 2280 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */ 2281 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */ 2282 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */ 2283 FIELD(MVFR1, FPHP, 24, 4) 2284 FIELD(MVFR1, SIMDFMAC, 28, 4) 2285 2286 FIELD(MVFR2, SIMDMISC, 0, 4) 2287 FIELD(MVFR2, FPMISC, 4, 4) 2288 2289 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 2290 2291 /* If adding a feature bit which corresponds to a Linux ELF 2292 * HWCAP bit, remember to update the feature-bit-to-hwcap 2293 * mapping in linux-user/elfload.c:get_elf_hwcap(). 2294 */ 2295 enum arm_features { 2296 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 2297 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 2298 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 2299 ARM_FEATURE_V6, 2300 ARM_FEATURE_V6K, 2301 ARM_FEATURE_V7, 2302 ARM_FEATURE_THUMB2, 2303 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 2304 ARM_FEATURE_NEON, 2305 ARM_FEATURE_M, /* Microcontroller profile. */ 2306 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 2307 ARM_FEATURE_THUMB2EE, 2308 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 2309 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 2310 ARM_FEATURE_V4T, 2311 ARM_FEATURE_V5, 2312 ARM_FEATURE_STRONGARM, 2313 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 2314 ARM_FEATURE_GENERIC_TIMER, 2315 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 2316 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 2317 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 2318 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 2319 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 2320 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 2321 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 2322 ARM_FEATURE_V8, 2323 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 2324 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 2325 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 2326 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 2327 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 2328 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 2329 ARM_FEATURE_PMU, /* has PMU support */ 2330 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 2331 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 2332 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 2333 ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ 2334 }; 2335 2336 static inline int arm_feature(CPUARMState *env, int feature) 2337 { 2338 return (env->features & (1ULL << feature)) != 0; 2339 } 2340 2341 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); 2342 2343 #if !defined(CONFIG_USER_ONLY) 2344 /* Return true if exception levels below EL3 are in secure state, 2345 * or would be following an exception return to that level. 2346 * Unlike arm_is_secure() (which is always a question about the 2347 * _current_ state of the CPU) this doesn't care about the current 2348 * EL or mode. 2349 */ 2350 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2351 { 2352 if (arm_feature(env, ARM_FEATURE_EL3)) { 2353 return !(env->cp15.scr_el3 & SCR_NS); 2354 } else { 2355 /* If EL3 is not supported then the secure state is implementation 2356 * defined, in which case QEMU defaults to non-secure. 2357 */ 2358 return false; 2359 } 2360 } 2361 2362 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 2363 static inline bool arm_is_el3_or_mon(CPUARMState *env) 2364 { 2365 if (arm_feature(env, ARM_FEATURE_EL3)) { 2366 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 2367 /* CPU currently in AArch64 state and EL3 */ 2368 return true; 2369 } else if (!is_a64(env) && 2370 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 2371 /* CPU currently in AArch32 state and monitor mode */ 2372 return true; 2373 } 2374 } 2375 return false; 2376 } 2377 2378 /* Return true if the processor is in secure state */ 2379 static inline bool arm_is_secure(CPUARMState *env) 2380 { 2381 if (arm_is_el3_or_mon(env)) { 2382 return true; 2383 } 2384 return arm_is_secure_below_el3(env); 2385 } 2386 2387 /* 2388 * Return true if the current security state has AArch64 EL2 or AArch32 Hyp. 2389 * This corresponds to the pseudocode EL2Enabled() 2390 */ 2391 static inline bool arm_is_el2_enabled(CPUARMState *env) 2392 { 2393 if (arm_feature(env, ARM_FEATURE_EL2)) { 2394 if (arm_is_secure_below_el3(env)) { 2395 return (env->cp15.scr_el3 & SCR_EEL2) != 0; 2396 } 2397 return true; 2398 } 2399 return false; 2400 } 2401 2402 #else 2403 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2404 { 2405 return false; 2406 } 2407 2408 static inline bool arm_is_secure(CPUARMState *env) 2409 { 2410 return false; 2411 } 2412 2413 static inline bool arm_is_el2_enabled(CPUARMState *env) 2414 { 2415 return false; 2416 } 2417 #endif 2418 2419 /** 2420 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 2421 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 2422 * "for all purposes other than a direct read or write access of HCR_EL2." 2423 * Not included here is HCR_RW. 2424 */ 2425 uint64_t arm_hcr_el2_eff(CPUARMState *env); 2426 uint64_t arm_hcrx_el2_eff(CPUARMState *env); 2427 2428 /* Return true if the specified exception level is running in AArch64 state. */ 2429 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 2430 { 2431 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 2432 * and if we're not in EL0 then the state of EL0 isn't well defined.) 2433 */ 2434 assert(el >= 1 && el <= 3); 2435 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 2436 2437 /* The highest exception level is always at the maximum supported 2438 * register width, and then lower levels have a register width controlled 2439 * by bits in the SCR or HCR registers. 2440 */ 2441 if (el == 3) { 2442 return aa64; 2443 } 2444 2445 if (arm_feature(env, ARM_FEATURE_EL3) && 2446 ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) { 2447 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 2448 } 2449 2450 if (el == 2) { 2451 return aa64; 2452 } 2453 2454 if (arm_is_el2_enabled(env)) { 2455 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 2456 } 2457 2458 return aa64; 2459 } 2460 2461 /* Function for determing whether guest cp register reads and writes should 2462 * access the secure or non-secure bank of a cp register. When EL3 is 2463 * operating in AArch32 state, the NS-bit determines whether the secure 2464 * instance of a cp register should be used. When EL3 is AArch64 (or if 2465 * it doesn't exist at all) then there is no register banking, and all 2466 * accesses are to the non-secure version. 2467 */ 2468 static inline bool access_secure_reg(CPUARMState *env) 2469 { 2470 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 2471 !arm_el_is_aa64(env, 3) && 2472 !(env->cp15.scr_el3 & SCR_NS)); 2473 2474 return ret; 2475 } 2476 2477 /* Macros for accessing a specified CP register bank */ 2478 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 2479 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 2480 2481 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 2482 do { \ 2483 if (_secure) { \ 2484 (_env)->cp15._regname##_s = (_val); \ 2485 } else { \ 2486 (_env)->cp15._regname##_ns = (_val); \ 2487 } \ 2488 } while (0) 2489 2490 /* Macros for automatically accessing a specific CP register bank depending on 2491 * the current secure state of the system. These macros are not intended for 2492 * supporting instruction translation reads/writes as these are dependent 2493 * solely on the SCR.NS bit and not the mode. 2494 */ 2495 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 2496 A32_BANKED_REG_GET((_env), _regname, \ 2497 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 2498 2499 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 2500 A32_BANKED_REG_SET((_env), _regname, \ 2501 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 2502 (_val)) 2503 2504 void arm_cpu_list(void); 2505 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 2506 uint32_t cur_el, bool secure); 2507 2508 /* Interface between CPU and Interrupt controller. */ 2509 #ifndef CONFIG_USER_ONLY 2510 bool armv7m_nvic_can_take_pending_exception(void *opaque); 2511 #else 2512 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) 2513 { 2514 return true; 2515 } 2516 #endif 2517 /** 2518 * armv7m_nvic_set_pending: mark the specified exception as pending 2519 * @opaque: the NVIC 2520 * @irq: the exception number to mark pending 2521 * @secure: false for non-banked exceptions or for the nonsecure 2522 * version of a banked exception, true for the secure version of a banked 2523 * exception. 2524 * 2525 * Marks the specified exception as pending. Note that we will assert() 2526 * if @secure is true and @irq does not specify one of the fixed set 2527 * of architecturally banked exceptions. 2528 */ 2529 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); 2530 /** 2531 * armv7m_nvic_set_pending_derived: mark this derived exception as pending 2532 * @opaque: the NVIC 2533 * @irq: the exception number to mark pending 2534 * @secure: false for non-banked exceptions or for the nonsecure 2535 * version of a banked exception, true for the secure version of a banked 2536 * exception. 2537 * 2538 * Similar to armv7m_nvic_set_pending(), but specifically for derived 2539 * exceptions (exceptions generated in the course of trying to take 2540 * a different exception). 2541 */ 2542 void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); 2543 /** 2544 * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending 2545 * @opaque: the NVIC 2546 * @irq: the exception number to mark pending 2547 * @secure: false for non-banked exceptions or for the nonsecure 2548 * version of a banked exception, true for the secure version of a banked 2549 * exception. 2550 * 2551 * Similar to armv7m_nvic_set_pending(), but specifically for exceptions 2552 * generated in the course of lazy stacking of FP registers. 2553 */ 2554 void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure); 2555 /** 2556 * armv7m_nvic_get_pending_irq_info: return highest priority pending 2557 * exception, and whether it targets Secure state 2558 * @opaque: the NVIC 2559 * @pirq: set to pending exception number 2560 * @ptargets_secure: set to whether pending exception targets Secure 2561 * 2562 * This function writes the number of the highest priority pending 2563 * exception (the one which would be made active by 2564 * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure 2565 * to true if the current highest priority pending exception should 2566 * be taken to Secure state, false for NS. 2567 */ 2568 void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq, 2569 bool *ptargets_secure); 2570 /** 2571 * armv7m_nvic_acknowledge_irq: make highest priority pending exception active 2572 * @opaque: the NVIC 2573 * 2574 * Move the current highest priority pending exception from the pending 2575 * state to the active state, and update v7m.exception to indicate that 2576 * it is the exception currently being handled. 2577 */ 2578 void armv7m_nvic_acknowledge_irq(void *opaque); 2579 /** 2580 * armv7m_nvic_complete_irq: complete specified interrupt or exception 2581 * @opaque: the NVIC 2582 * @irq: the exception number to complete 2583 * @secure: true if this exception was secure 2584 * 2585 * Returns: -1 if the irq was not active 2586 * 1 if completing this irq brought us back to base (no active irqs) 2587 * 0 if there is still an irq active after this one was completed 2588 * (Ignoring -1, this is the same as the RETTOBASE value before completion.) 2589 */ 2590 int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); 2591 /** 2592 * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) 2593 * @opaque: the NVIC 2594 * @irq: the exception number to mark pending 2595 * @secure: false for non-banked exceptions or for the nonsecure 2596 * version of a banked exception, true for the secure version of a banked 2597 * exception. 2598 * 2599 * Return whether an exception is "ready", i.e. whether the exception is 2600 * enabled and is configured at a priority which would allow it to 2601 * interrupt the current execution priority. This controls whether the 2602 * RDY bit for it in the FPCCR is set. 2603 */ 2604 bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure); 2605 /** 2606 * armv7m_nvic_raw_execution_priority: return the raw execution priority 2607 * @opaque: the NVIC 2608 * 2609 * Returns: the raw execution priority as defined by the v8M architecture. 2610 * This is the execution priority minus the effects of AIRCR.PRIS, 2611 * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. 2612 * (v8M ARM ARM I_PKLD.) 2613 */ 2614 int armv7m_nvic_raw_execution_priority(void *opaque); 2615 /** 2616 * armv7m_nvic_neg_prio_requested: return true if the requested execution 2617 * priority is negative for the specified security state. 2618 * @opaque: the NVIC 2619 * @secure: the security state to test 2620 * This corresponds to the pseudocode IsReqExecPriNeg(). 2621 */ 2622 #ifndef CONFIG_USER_ONLY 2623 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); 2624 #else 2625 static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) 2626 { 2627 return false; 2628 } 2629 #endif 2630 2631 /* Interface for defining coprocessor registers. 2632 * Registers are defined in tables of arm_cp_reginfo structs 2633 * which are passed to define_arm_cp_regs(). 2634 */ 2635 2636 /* When looking up a coprocessor register we look for it 2637 * via an integer which encodes all of: 2638 * coprocessor number 2639 * Crn, Crm, opc1, opc2 fields 2640 * 32 or 64 bit register (ie is it accessed via MRC/MCR 2641 * or via MRRC/MCRR?) 2642 * non-secure/secure bank (AArch32 only) 2643 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 2644 * (In this case crn and opc2 should be zero.) 2645 * For AArch64, there is no 32/64 bit size distinction; 2646 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 2647 * and 4 bit CRn and CRm. The encoding patterns are chosen 2648 * to be easy to convert to and from the KVM encodings, and also 2649 * so that the hashtable can contain both AArch32 and AArch64 2650 * registers (to allow for interprocessing where we might run 2651 * 32 bit code on a 64 bit core). 2652 */ 2653 /* This bit is private to our hashtable cpreg; in KVM register 2654 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 2655 * in the upper bits of the 64 bit ID. 2656 */ 2657 #define CP_REG_AA64_SHIFT 28 2658 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 2659 2660 /* To enable banking of coprocessor registers depending on ns-bit we 2661 * add a bit to distinguish between secure and non-secure cpregs in the 2662 * hashtable. 2663 */ 2664 #define CP_REG_NS_SHIFT 29 2665 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 2666 2667 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 2668 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 2669 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 2670 2671 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 2672 (CP_REG_AA64_MASK | \ 2673 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 2674 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 2675 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 2676 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 2677 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 2678 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 2679 2680 /* Convert a full 64 bit KVM register ID to the truncated 32 bit 2681 * version used as a key for the coprocessor register hashtable 2682 */ 2683 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 2684 { 2685 uint32_t cpregid = kvmid; 2686 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 2687 cpregid |= CP_REG_AA64_MASK; 2688 } else { 2689 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 2690 cpregid |= (1 << 15); 2691 } 2692 2693 /* KVM is always non-secure so add the NS flag on AArch32 register 2694 * entries. 2695 */ 2696 cpregid |= 1 << CP_REG_NS_SHIFT; 2697 } 2698 return cpregid; 2699 } 2700 2701 /* Convert a truncated 32 bit hashtable key into the full 2702 * 64 bit KVM register ID. 2703 */ 2704 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 2705 { 2706 uint64_t kvmid; 2707 2708 if (cpregid & CP_REG_AA64_MASK) { 2709 kvmid = cpregid & ~CP_REG_AA64_MASK; 2710 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 2711 } else { 2712 kvmid = cpregid & ~(1 << 15); 2713 if (cpregid & (1 << 15)) { 2714 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 2715 } else { 2716 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 2717 } 2718 } 2719 return kvmid; 2720 } 2721 2722 /* Return the highest implemented Exception Level */ 2723 static inline int arm_highest_el(CPUARMState *env) 2724 { 2725 if (arm_feature(env, ARM_FEATURE_EL3)) { 2726 return 3; 2727 } 2728 if (arm_feature(env, ARM_FEATURE_EL2)) { 2729 return 2; 2730 } 2731 return 1; 2732 } 2733 2734 /* Return true if a v7M CPU is in Handler mode */ 2735 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2736 { 2737 return env->v7m.exception != 0; 2738 } 2739 2740 /* Return the current Exception Level (as per ARMv8; note that this differs 2741 * from the ARMv7 Privilege Level). 2742 */ 2743 static inline int arm_current_el(CPUARMState *env) 2744 { 2745 if (arm_feature(env, ARM_FEATURE_M)) { 2746 return arm_v7m_is_handler_mode(env) || 2747 !(env->v7m.control[env->v7m.secure] & 1); 2748 } 2749 2750 if (is_a64(env)) { 2751 return extract32(env->pstate, 2, 2); 2752 } 2753 2754 switch (env->uncached_cpsr & 0x1f) { 2755 case ARM_CPU_MODE_USR: 2756 return 0; 2757 case ARM_CPU_MODE_HYP: 2758 return 2; 2759 case ARM_CPU_MODE_MON: 2760 return 3; 2761 default: 2762 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2763 /* If EL3 is 32-bit then all secure privileged modes run in 2764 * EL3 2765 */ 2766 return 3; 2767 } 2768 2769 return 1; 2770 } 2771 } 2772 2773 /** 2774 * write_list_to_cpustate 2775 * @cpu: ARMCPU 2776 * 2777 * For each register listed in the ARMCPU cpreg_indexes list, write 2778 * its value from the cpreg_values list into the ARMCPUState structure. 2779 * This updates TCG's working data structures from KVM data or 2780 * from incoming migration state. 2781 * 2782 * Returns: true if all register values were updated correctly, 2783 * false if some register was unknown or could not be written. 2784 * Note that we do not stop early on failure -- we will attempt 2785 * writing all registers in the list. 2786 */ 2787 bool write_list_to_cpustate(ARMCPU *cpu); 2788 2789 /** 2790 * write_cpustate_to_list: 2791 * @cpu: ARMCPU 2792 * @kvm_sync: true if this is for syncing back to KVM 2793 * 2794 * For each register listed in the ARMCPU cpreg_indexes list, write 2795 * its value from the ARMCPUState structure into the cpreg_values list. 2796 * This is used to copy info from TCG's working data structures into 2797 * KVM or for outbound migration. 2798 * 2799 * @kvm_sync is true if we are doing this in order to sync the 2800 * register state back to KVM. In this case we will only update 2801 * values in the list if the previous list->cpustate sync actually 2802 * successfully wrote the CPU state. Otherwise we will keep the value 2803 * that is in the list. 2804 * 2805 * Returns: true if all register values were read correctly, 2806 * false if some register was unknown or could not be read. 2807 * Note that we do not stop early on failure -- we will attempt 2808 * reading all registers in the list. 2809 */ 2810 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); 2811 2812 #define ARM_CPUID_TI915T 0x54029152 2813 #define ARM_CPUID_TI925T 0x54029252 2814 2815 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU 2816 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) 2817 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2818 2819 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU 2820 2821 #define cpu_list arm_cpu_list 2822 2823 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2824 * 2825 * If EL3 is 64-bit: 2826 * + NonSecure EL1 & 0 stage 1 2827 * + NonSecure EL1 & 0 stage 2 2828 * + NonSecure EL2 2829 * + NonSecure EL2 & 0 (ARMv8.1-VHE) 2830 * + Secure EL1 & 0 2831 * + Secure EL3 2832 * If EL3 is 32-bit: 2833 * + NonSecure PL1 & 0 stage 1 2834 * + NonSecure PL1 & 0 stage 2 2835 * + NonSecure PL2 2836 * + Secure PL0 2837 * + Secure PL1 2838 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2839 * 2840 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2841 * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes, 2842 * because they may differ in access permissions even if the VA->PA map is 2843 * the same 2844 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2845 * translation, which means that we have one mmu_idx that deals with two 2846 * concatenated translation regimes [this sort of combined s1+2 TLB is 2847 * architecturally permitted] 2848 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2849 * handling via the TLB. The only way to do a stage 1 translation without 2850 * the immediate stage 2 translation is via the ATS or AT system insns, 2851 * which can be slow-pathed and always do a page table walk. 2852 * The only use of stage 2 translations is either as part of an s1+2 2853 * lookup or when loading the descriptors during a stage 1 page table walk, 2854 * and in both those cases we don't use the TLB. 2855 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2856 * translation regimes, because they map reasonably well to each other 2857 * and they can't both be active at the same time. 2858 * 5. we want to be able to use the TLB for accesses done as part of a 2859 * stage1 page table walk, rather than having to walk the stage2 page 2860 * table over and over. 2861 * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access 2862 * Never (PAN) bit within PSTATE. 2863 * 2864 * This gives us the following list of cases: 2865 * 2866 * NS EL0 EL1&0 stage 1+2 (aka NS PL0) 2867 * NS EL1 EL1&0 stage 1+2 (aka NS PL1) 2868 * NS EL1 EL1&0 stage 1+2 +PAN 2869 * NS EL0 EL2&0 2870 * NS EL2 EL2&0 2871 * NS EL2 EL2&0 +PAN 2872 * NS EL2 (aka NS PL2) 2873 * S EL0 EL1&0 (aka S PL0) 2874 * S EL1 EL1&0 (not used if EL3 is 32 bit) 2875 * S EL1 EL1&0 +PAN 2876 * S EL3 (aka S PL1) 2877 * 2878 * for a total of 11 different mmu_idx. 2879 * 2880 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2881 * as A profile. They only need to distinguish NS EL0 and NS EL1 (and 2882 * NS EL2 if we ever model a Cortex-R52). 2883 * 2884 * M profile CPUs are rather different as they do not have a true MMU. 2885 * They have the following different MMU indexes: 2886 * User 2887 * Privileged 2888 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2889 * Privileged, execution priority negative (ditto) 2890 * If the CPU supports the v8M Security Extension then there are also: 2891 * Secure User 2892 * Secure Privileged 2893 * Secure User, execution priority negative 2894 * Secure Privileged, execution priority negative 2895 * 2896 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2897 * are not quite the same -- different CPU types (most notably M profile 2898 * vs A/R profile) would like to use MMU indexes with different semantics, 2899 * but since we don't ever need to use all of those in a single CPU we 2900 * can avoid having to set NB_MMU_MODES to "total number of A profile MMU 2901 * modes + total number of M profile MMU modes". The lower bits of 2902 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2903 * the same for any particular CPU. 2904 * Variables of type ARMMUIdx are always full values, and the core 2905 * index values are in variables of type 'int'. 2906 * 2907 * Our enumeration includes at the end some entries which are not "true" 2908 * mmu_idx values in that they don't have corresponding TLBs and are only 2909 * valid for doing slow path page table walks. 2910 * 2911 * The constant names here are patterned after the general style of the names 2912 * of the AT/ATS operations. 2913 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2914 * For M profile we arrange them to have a bit for priv, a bit for negpri 2915 * and a bit for secure. 2916 */ 2917 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2918 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2919 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2920 2921 /* Meanings of the bits for A profile mmu idx values */ 2922 #define ARM_MMU_IDX_A_NS 0x8 2923 2924 /* Meanings of the bits for M profile mmu idx values */ 2925 #define ARM_MMU_IDX_M_PRIV 0x1 2926 #define ARM_MMU_IDX_M_NEGPRI 0x2 2927 #define ARM_MMU_IDX_M_S 0x4 /* Secure */ 2928 2929 #define ARM_MMU_IDX_TYPE_MASK \ 2930 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB) 2931 #define ARM_MMU_IDX_COREIDX_MASK 0xf 2932 2933 typedef enum ARMMMUIdx { 2934 /* 2935 * A-profile. 2936 */ 2937 ARMMMUIdx_SE10_0 = 0 | ARM_MMU_IDX_A, 2938 ARMMMUIdx_SE20_0 = 1 | ARM_MMU_IDX_A, 2939 ARMMMUIdx_SE10_1 = 2 | ARM_MMU_IDX_A, 2940 ARMMMUIdx_SE20_2 = 3 | ARM_MMU_IDX_A, 2941 ARMMMUIdx_SE10_1_PAN = 4 | ARM_MMU_IDX_A, 2942 ARMMMUIdx_SE20_2_PAN = 5 | ARM_MMU_IDX_A, 2943 ARMMMUIdx_SE2 = 6 | ARM_MMU_IDX_A, 2944 ARMMMUIdx_SE3 = 7 | ARM_MMU_IDX_A, 2945 2946 ARMMMUIdx_E10_0 = ARMMMUIdx_SE10_0 | ARM_MMU_IDX_A_NS, 2947 ARMMMUIdx_E20_0 = ARMMMUIdx_SE20_0 | ARM_MMU_IDX_A_NS, 2948 ARMMMUIdx_E10_1 = ARMMMUIdx_SE10_1 | ARM_MMU_IDX_A_NS, 2949 ARMMMUIdx_E20_2 = ARMMMUIdx_SE20_2 | ARM_MMU_IDX_A_NS, 2950 ARMMMUIdx_E10_1_PAN = ARMMMUIdx_SE10_1_PAN | ARM_MMU_IDX_A_NS, 2951 ARMMMUIdx_E20_2_PAN = ARMMMUIdx_SE20_2_PAN | ARM_MMU_IDX_A_NS, 2952 ARMMMUIdx_E2 = ARMMMUIdx_SE2 | ARM_MMU_IDX_A_NS, 2953 2954 /* 2955 * These are not allocated TLBs and are used only for AT system 2956 * instructions or for the first stage of an S12 page table walk. 2957 */ 2958 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, 2959 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, 2960 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB, 2961 ARMMMUIdx_Stage1_SE0 = 3 | ARM_MMU_IDX_NOTLB, 2962 ARMMMUIdx_Stage1_SE1 = 4 | ARM_MMU_IDX_NOTLB, 2963 ARMMMUIdx_Stage1_SE1_PAN = 5 | ARM_MMU_IDX_NOTLB, 2964 /* 2965 * Not allocated a TLB: used only for second stage of an S12 page 2966 * table walk, or for descriptor loads during first stage of an S1 2967 * page table walk. Note that if we ever want to have a TLB for this 2968 * then various TLB flush insns which currently are no-ops or flush 2969 * only stage 1 MMU indexes will need to change to flush stage 2. 2970 */ 2971 ARMMMUIdx_Stage2 = 6 | ARM_MMU_IDX_NOTLB, 2972 ARMMMUIdx_Stage2_S = 7 | ARM_MMU_IDX_NOTLB, 2973 2974 /* 2975 * M-profile. 2976 */ 2977 ARMMMUIdx_MUser = ARM_MMU_IDX_M, 2978 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV, 2979 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI, 2980 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI, 2981 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S, 2982 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S, 2983 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S, 2984 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S, 2985 } ARMMMUIdx; 2986 2987 /* 2988 * Bit macros for the core-mmu-index values for each index, 2989 * for use when calling tlb_flush_by_mmuidx() and friends. 2990 */ 2991 #define TO_CORE_BIT(NAME) \ 2992 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK) 2993 2994 typedef enum ARMMMUIdxBit { 2995 TO_CORE_BIT(E10_0), 2996 TO_CORE_BIT(E20_0), 2997 TO_CORE_BIT(E10_1), 2998 TO_CORE_BIT(E10_1_PAN), 2999 TO_CORE_BIT(E2), 3000 TO_CORE_BIT(E20_2), 3001 TO_CORE_BIT(E20_2_PAN), 3002 TO_CORE_BIT(SE10_0), 3003 TO_CORE_BIT(SE20_0), 3004 TO_CORE_BIT(SE10_1), 3005 TO_CORE_BIT(SE20_2), 3006 TO_CORE_BIT(SE10_1_PAN), 3007 TO_CORE_BIT(SE20_2_PAN), 3008 TO_CORE_BIT(SE2), 3009 TO_CORE_BIT(SE3), 3010 3011 TO_CORE_BIT(MUser), 3012 TO_CORE_BIT(MPriv), 3013 TO_CORE_BIT(MUserNegPri), 3014 TO_CORE_BIT(MPrivNegPri), 3015 TO_CORE_BIT(MSUser), 3016 TO_CORE_BIT(MSPriv), 3017 TO_CORE_BIT(MSUserNegPri), 3018 TO_CORE_BIT(MSPrivNegPri), 3019 } ARMMMUIdxBit; 3020 3021 #undef TO_CORE_BIT 3022 3023 #define MMU_USER_IDX 0 3024 3025 /* Indexes used when registering address spaces with cpu_address_space_init */ 3026 typedef enum ARMASIdx { 3027 ARMASIdx_NS = 0, 3028 ARMASIdx_S = 1, 3029 ARMASIdx_TagNS = 2, 3030 ARMASIdx_TagS = 3, 3031 } ARMASIdx; 3032 3033 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 3034 { 3035 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 3036 * CSSELR is RAZ/WI. 3037 */ 3038 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 3039 } 3040 3041 static inline bool arm_sctlr_b(CPUARMState *env) 3042 { 3043 return 3044 /* We need not implement SCTLR.ITD in user-mode emulation, so 3045 * let linux-user ignore the fact that it conflicts with SCTLR_B. 3046 * This lets people run BE32 binaries with "-cpu any". 3047 */ 3048 #ifndef CONFIG_USER_ONLY 3049 !arm_feature(env, ARM_FEATURE_V7) && 3050 #endif 3051 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 3052 } 3053 3054 uint64_t arm_sctlr(CPUARMState *env, int el); 3055 3056 static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, 3057 bool sctlr_b) 3058 { 3059 #ifdef CONFIG_USER_ONLY 3060 /* 3061 * In system mode, BE32 is modelled in line with the 3062 * architecture (as word-invariant big-endianness), where loads 3063 * and stores are done little endian but from addresses which 3064 * are adjusted by XORing with the appropriate constant. So the 3065 * endianness to use for the raw data access is not affected by 3066 * SCTLR.B. 3067 * In user mode, however, we model BE32 as byte-invariant 3068 * big-endianness (because user-only code cannot tell the 3069 * difference), and so we need to use a data access endianness 3070 * that depends on SCTLR.B. 3071 */ 3072 if (sctlr_b) { 3073 return true; 3074 } 3075 #endif 3076 /* In 32bit endianness is determined by looking at CPSR's E bit */ 3077 return env->uncached_cpsr & CPSR_E; 3078 } 3079 3080 static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr) 3081 { 3082 return sctlr & (el ? SCTLR_EE : SCTLR_E0E); 3083 } 3084 3085 /* Return true if the processor is in big-endian mode. */ 3086 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 3087 { 3088 if (!is_a64(env)) { 3089 return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); 3090 } else { 3091 int cur_el = arm_current_el(env); 3092 uint64_t sctlr = arm_sctlr(env, cur_el); 3093 return arm_cpu_data_is_big_endian_a64(cur_el, sctlr); 3094 } 3095 } 3096 3097 #include "exec/cpu-all.h" 3098 3099 /* 3100 * We have more than 32-bits worth of state per TB, so we split the data 3101 * between tb->flags and tb->cs_base, which is otherwise unused for ARM. 3102 * We collect these two parts in CPUARMTBFlags where they are named 3103 * flags and flags2 respectively. 3104 * 3105 * The flags that are shared between all execution modes, TBFLAG_ANY, 3106 * are stored in flags. The flags that are specific to a given mode 3107 * are stores in flags2. Since cs_base is sized on the configured 3108 * address size, flags2 always has 64-bits for A64, and a minimum of 3109 * 32-bits for A32 and M32. 3110 * 3111 * The bits for 32-bit A-profile and M-profile partially overlap: 3112 * 3113 * 31 23 11 10 0 3114 * +-------------+----------+----------------+ 3115 * | | | TBFLAG_A32 | 3116 * | TBFLAG_AM32 | +-----+----------+ 3117 * | | |TBFLAG_M32| 3118 * +-------------+----------------+----------+ 3119 * 31 23 6 5 0 3120 * 3121 * Unless otherwise noted, these bits are cached in env->hflags. 3122 */ 3123 FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1) 3124 FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1) 3125 FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1) /* Not cached. */ 3126 FIELD(TBFLAG_ANY, BE_DATA, 3, 1) 3127 FIELD(TBFLAG_ANY, MMUIDX, 4, 4) 3128 /* Target EL if we take a floating-point-disabled exception */ 3129 FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) 3130 /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ 3131 FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1) 3132 FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1) 3133 3134 /* 3135 * Bit usage when in AArch32 state, both A- and M-profile. 3136 */ 3137 FIELD(TBFLAG_AM32, CONDEXEC, 24, 8) /* Not cached. */ 3138 FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cached. */ 3139 3140 /* 3141 * Bit usage when in AArch32 state, for A-profile only. 3142 */ 3143 FIELD(TBFLAG_A32, VECLEN, 0, 3) /* Not cached. */ 3144 FIELD(TBFLAG_A32, VECSTRIDE, 3, 2) /* Not cached. */ 3145 /* 3146 * We store the bottom two bits of the CPAR as TB flags and handle 3147 * checks on the other bits at runtime. This shares the same bits as 3148 * VECSTRIDE, which is OK as no XScale CPU has VFP. 3149 * Not cached, because VECLEN+VECSTRIDE are not cached. 3150 */ 3151 FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2) 3152 FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ 3153 FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */ 3154 FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1) 3155 /* 3156 * Indicates whether cp register reads and writes by guest code should access 3157 * the secure or nonsecure bank of banked registers; note that this is not 3158 * the same thing as the current security state of the processor! 3159 */ 3160 FIELD(TBFLAG_A32, NS, 10, 1) 3161 /* 3162 * Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. 3163 * This requires an SME trap from AArch32 mode when using NEON. 3164 */ 3165 FIELD(TBFLAG_A32, SME_TRAP_NONSTREAMING, 11, 1) 3166 3167 /* 3168 * Bit usage when in AArch32 state, for M-profile only. 3169 */ 3170 /* Handler (ie not Thread) mode */ 3171 FIELD(TBFLAG_M32, HANDLER, 0, 1) 3172 /* Whether we should generate stack-limit checks */ 3173 FIELD(TBFLAG_M32, STACKCHECK, 1, 1) 3174 /* Set if FPCCR.LSPACT is set */ 3175 FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */ 3176 /* Set if we must create a new FP context */ 3177 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */ 3178 /* Set if FPCCR.S does not match current security state */ 3179 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */ 3180 /* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */ 3181 FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */ 3182 3183 /* 3184 * Bit usage when in AArch64 state 3185 */ 3186 FIELD(TBFLAG_A64, TBII, 0, 2) 3187 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3188 /* The current vector length, either NVL or SVL. */ 3189 FIELD(TBFLAG_A64, VL, 4, 4) 3190 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3191 FIELD(TBFLAG_A64, BT, 9, 1) 3192 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ 3193 FIELD(TBFLAG_A64, TBID, 12, 2) 3194 FIELD(TBFLAG_A64, UNPRIV, 14, 1) 3195 FIELD(TBFLAG_A64, ATA, 15, 1) 3196 FIELD(TBFLAG_A64, TCMA, 16, 2) 3197 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) 3198 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) 3199 FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2) 3200 FIELD(TBFLAG_A64, PSTATE_SM, 22, 1) 3201 FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) 3202 FIELD(TBFLAG_A64, SVL, 24, 4) 3203 /* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. */ 3204 FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1) 3205 3206 /* 3207 * Helpers for using the above. 3208 */ 3209 #define DP_TBFLAG_ANY(DST, WHICH, VAL) \ 3210 (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL)) 3211 #define DP_TBFLAG_A64(DST, WHICH, VAL) \ 3212 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A64, WHICH, VAL)) 3213 #define DP_TBFLAG_A32(DST, WHICH, VAL) \ 3214 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL)) 3215 #define DP_TBFLAG_M32(DST, WHICH, VAL) \ 3216 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL)) 3217 #define DP_TBFLAG_AM32(DST, WHICH, VAL) \ 3218 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL)) 3219 3220 #define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH) 3221 #define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A64, WHICH) 3222 #define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH) 3223 #define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH) 3224 #define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH) 3225 3226 /** 3227 * cpu_mmu_index: 3228 * @env: The cpu environment 3229 * @ifetch: True for code access, false for data access. 3230 * 3231 * Return the core mmu index for the current translation regime. 3232 * This function is used by generic TCG code paths. 3233 */ 3234 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) 3235 { 3236 return EX_TBFLAG_ANY(env->hflags, MMUIDX); 3237 } 3238 3239 /** 3240 * sve_vq 3241 * @env: the cpu context 3242 * 3243 * Return the VL cached within env->hflags, in units of quadwords. 3244 */ 3245 static inline int sve_vq(CPUARMState *env) 3246 { 3247 return EX_TBFLAG_A64(env->hflags, VL) + 1; 3248 } 3249 3250 /** 3251 * sme_vq 3252 * @env: the cpu context 3253 * 3254 * Return the SVL cached within env->hflags, in units of quadwords. 3255 */ 3256 static inline int sme_vq(CPUARMState *env) 3257 { 3258 return EX_TBFLAG_A64(env->hflags, SVL) + 1; 3259 } 3260 3261 static inline bool bswap_code(bool sctlr_b) 3262 { 3263 #ifdef CONFIG_USER_ONLY 3264 /* BE8 (SCTLR.B = 0, TARGET_BIG_ENDIAN = 1) is mixed endian. 3265 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_BIG_ENDIAN=0 3266 * would also end up as a mixed-endian mode with BE code, LE data. 3267 */ 3268 return 3269 #if TARGET_BIG_ENDIAN 3270 1 ^ 3271 #endif 3272 sctlr_b; 3273 #else 3274 /* All code access in ARM is little endian, and there are no loaders 3275 * doing swaps that need to be reversed 3276 */ 3277 return 0; 3278 #endif 3279 } 3280 3281 #ifdef CONFIG_USER_ONLY 3282 static inline bool arm_cpu_bswap_data(CPUARMState *env) 3283 { 3284 return 3285 #if TARGET_BIG_ENDIAN 3286 1 ^ 3287 #endif 3288 arm_cpu_data_is_big_endian(env); 3289 } 3290 #endif 3291 3292 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 3293 target_ulong *cs_base, uint32_t *flags); 3294 3295 enum { 3296 QEMU_PSCI_CONDUIT_DISABLED = 0, 3297 QEMU_PSCI_CONDUIT_SMC = 1, 3298 QEMU_PSCI_CONDUIT_HVC = 2, 3299 }; 3300 3301 #ifndef CONFIG_USER_ONLY 3302 /* Return the address space index to use for a memory access */ 3303 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3304 { 3305 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3306 } 3307 3308 /* Return the AddressSpace to use for a memory access 3309 * (which depends on whether the access is S or NS, and whether 3310 * the board gave us a separate AddressSpace for S accesses). 3311 */ 3312 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3313 { 3314 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3315 } 3316 #endif 3317 3318 /** 3319 * arm_register_pre_el_change_hook: 3320 * Register a hook function which will be called immediately before this 3321 * CPU changes exception level or mode. The hook function will be 3322 * passed a pointer to the ARMCPU and the opaque data pointer passed 3323 * to this function when the hook was registered. 3324 * 3325 * Note that if a pre-change hook is called, any registered post-change hooks 3326 * are guaranteed to subsequently be called. 3327 */ 3328 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3329 void *opaque); 3330 /** 3331 * arm_register_el_change_hook: 3332 * Register a hook function which will be called immediately after this 3333 * CPU changes exception level or mode. The hook function will be 3334 * passed a pointer to the ARMCPU and the opaque data pointer passed 3335 * to this function when the hook was registered. 3336 * 3337 * Note that any registered hooks registered here are guaranteed to be called 3338 * if pre-change hooks have been. 3339 */ 3340 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3341 *opaque); 3342 3343 /** 3344 * arm_rebuild_hflags: 3345 * Rebuild the cached TBFLAGS for arbitrary changed processor state. 3346 */ 3347 void arm_rebuild_hflags(CPUARMState *env); 3348 3349 /** 3350 * aa32_vfp_dreg: 3351 * Return a pointer to the Dn register within env in 32-bit mode. 3352 */ 3353 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3354 { 3355 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3356 } 3357 3358 /** 3359 * aa32_vfp_qreg: 3360 * Return a pointer to the Qn register within env in 32-bit mode. 3361 */ 3362 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3363 { 3364 return &env->vfp.zregs[regno].d[0]; 3365 } 3366 3367 /** 3368 * aa64_vfp_qreg: 3369 * Return a pointer to the Qn register within env in 64-bit mode. 3370 */ 3371 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3372 { 3373 return &env->vfp.zregs[regno].d[0]; 3374 } 3375 3376 /* Shared between translate-sve.c and sve_helper.c. */ 3377 extern const uint64_t pred_esz_masks[4]; 3378 3379 /* Helper for the macros below, validating the argument type. */ 3380 static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x) 3381 { 3382 return x; 3383 } 3384 3385 /* 3386 * Lvalue macros for ARM TLB bits that we must cache in the TCG TLB. 3387 * Using these should be a bit more self-documenting than using the 3388 * generic target bits directly. 3389 */ 3390 #define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0) 3391 #define arm_tlb_mte_tagged(x) (typecheck_memtxattrs(x)->target_tlb_bit1) 3392 3393 /* 3394 * AArch64 usage of the PAGE_TARGET_* bits for linux-user. 3395 */ 3396 #define PAGE_BTI PAGE_TARGET_1 3397 #define PAGE_MTE PAGE_TARGET_2 3398 3399 #ifdef TARGET_TAGGED_ADDRESSES 3400 /** 3401 * cpu_untagged_addr: 3402 * @cs: CPU context 3403 * @x: tagged address 3404 * 3405 * Remove any address tag from @x. This is explicitly related to the 3406 * linux syscall TIF_TAGGED_ADDR setting, not TBI in general. 3407 * 3408 * There should be a better place to put this, but we need this in 3409 * include/exec/cpu_ldst.h, and not some place linux-user specific. 3410 */ 3411 static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x) 3412 { 3413 ARMCPU *cpu = ARM_CPU(cs); 3414 if (cpu->env.tagged_addr_enable) { 3415 /* 3416 * TBI is enabled for userspace but not kernelspace addresses. 3417 * Only clear the tag if bit 55 is clear. 3418 */ 3419 x &= sextract64(x, 0, 56); 3420 } 3421 return x; 3422 } 3423 #endif 3424 3425 /* 3426 * Naming convention for isar_feature functions: 3427 * Functions which test 32-bit ID registers should have _aa32_ in 3428 * their name. Functions which test 64-bit ID registers should have 3429 * _aa64_ in their name. These must only be used in code where we 3430 * know for certain that the CPU has AArch32 or AArch64 respectively 3431 * or where the correct answer for a CPU which doesn't implement that 3432 * CPU state is "false" (eg when generating A32 or A64 code, if adding 3433 * system registers that are specific to that CPU state, for "should 3434 * we let this system register bit be set" tests where the 32-bit 3435 * flavour of the register doesn't have the bit, and so on). 3436 * Functions which simply ask "does this feature exist at all" have 3437 * _any_ in their name, and always return the logical OR of the _aa64_ 3438 * and the _aa32_ function. 3439 */ 3440 3441 /* 3442 * 32-bit feature tests via id registers. 3443 */ 3444 static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id) 3445 { 3446 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; 3447 } 3448 3449 static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id) 3450 { 3451 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; 3452 } 3453 3454 static inline bool isar_feature_aa32_lob(const ARMISARegisters *id) 3455 { 3456 /* (M-profile) low-overhead loops and branch future */ 3457 return FIELD_EX32(id->id_isar0, ID_ISAR0, CMPBRANCH) >= 3; 3458 } 3459 3460 static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id) 3461 { 3462 return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0; 3463 } 3464 3465 static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) 3466 { 3467 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0; 3468 } 3469 3470 static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id) 3471 { 3472 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1; 3473 } 3474 3475 static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id) 3476 { 3477 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0; 3478 } 3479 3480 static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id) 3481 { 3482 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0; 3483 } 3484 3485 static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id) 3486 { 3487 return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0; 3488 } 3489 3490 static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id) 3491 { 3492 return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0; 3493 } 3494 3495 static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id) 3496 { 3497 return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0; 3498 } 3499 3500 static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id) 3501 { 3502 return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0; 3503 } 3504 3505 static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) 3506 { 3507 return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0; 3508 } 3509 3510 static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id) 3511 { 3512 return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0; 3513 } 3514 3515 static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) 3516 { 3517 return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0; 3518 } 3519 3520 static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id) 3521 { 3522 return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0; 3523 } 3524 3525 static inline bool isar_feature_aa32_bf16(const ARMISARegisters *id) 3526 { 3527 return FIELD_EX32(id->id_isar6, ID_ISAR6, BF16) != 0; 3528 } 3529 3530 static inline bool isar_feature_aa32_i8mm(const ARMISARegisters *id) 3531 { 3532 return FIELD_EX32(id->id_isar6, ID_ISAR6, I8MM) != 0; 3533 } 3534 3535 static inline bool isar_feature_aa32_ras(const ARMISARegisters *id) 3536 { 3537 return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) != 0; 3538 } 3539 3540 static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id) 3541 { 3542 return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0; 3543 } 3544 3545 static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id) 3546 { 3547 /* 3548 * Return true if M-profile state handling insns 3549 * (VSCCLRM, CLRM, FPCTX access insns) are implemented 3550 */ 3551 return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >= 3; 3552 } 3553 3554 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) 3555 { 3556 /* Sadly this is encoded differently for A-profile and M-profile */ 3557 if (isar_feature_aa32_mprofile(id)) { 3558 return FIELD_EX32(id->mvfr1, MVFR1, FP16) > 0; 3559 } else { 3560 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3; 3561 } 3562 } 3563 3564 static inline bool isar_feature_aa32_mve(const ARMISARegisters *id) 3565 { 3566 /* 3567 * Return true if MVE is supported (either integer or floating point). 3568 * We must check for M-profile as the MVFR1 field means something 3569 * else for A-profile. 3570 */ 3571 return isar_feature_aa32_mprofile(id) && 3572 FIELD_EX32(id->mvfr1, MVFR1, MVE) > 0; 3573 } 3574 3575 static inline bool isar_feature_aa32_mve_fp(const ARMISARegisters *id) 3576 { 3577 /* 3578 * Return true if MVE is supported (either integer or floating point). 3579 * We must check for M-profile as the MVFR1 field means something 3580 * else for A-profile. 3581 */ 3582 return isar_feature_aa32_mprofile(id) && 3583 FIELD_EX32(id->mvfr1, MVFR1, MVE) >= 2; 3584 } 3585 3586 static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id) 3587 { 3588 /* 3589 * Return true if either VFP or SIMD is implemented. 3590 * In this case, a minimum of VFP w/ D0-D15. 3591 */ 3592 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0; 3593 } 3594 3595 static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id) 3596 { 3597 /* Return true if D16-D31 are implemented */ 3598 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2; 3599 } 3600 3601 static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id) 3602 { 3603 return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0; 3604 } 3605 3606 static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id) 3607 { 3608 /* Return true if CPU supports single precision floating point, VFPv2 */ 3609 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0; 3610 } 3611 3612 static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id) 3613 { 3614 /* Return true if CPU supports single precision floating point, VFPv3 */ 3615 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2; 3616 } 3617 3618 static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id) 3619 { 3620 /* Return true if CPU supports double precision floating point, VFPv2 */ 3621 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0; 3622 } 3623 3624 static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id) 3625 { 3626 /* Return true if CPU supports double precision floating point, VFPv3 */ 3627 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2; 3628 } 3629 3630 static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id) 3631 { 3632 return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id); 3633 } 3634 3635 /* 3636 * We always set the FP and SIMD FP16 fields to indicate identical 3637 * levels of support (assuming SIMD is implemented at all), so 3638 * we only need one set of accessors. 3639 */ 3640 static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id) 3641 { 3642 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0; 3643 } 3644 3645 static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id) 3646 { 3647 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1; 3648 } 3649 3650 /* 3651 * Note that this ID register field covers both VFP and Neon FMAC, 3652 * so should usually be tested in combination with some other 3653 * check that confirms the presence of whichever of VFP or Neon is 3654 * relevant, to avoid accidentally enabling a Neon feature on 3655 * a VFP-no-Neon core or vice-versa. 3656 */ 3657 static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id) 3658 { 3659 return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0; 3660 } 3661 3662 static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id) 3663 { 3664 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1; 3665 } 3666 3667 static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id) 3668 { 3669 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2; 3670 } 3671 3672 static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id) 3673 { 3674 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3; 3675 } 3676 3677 static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id) 3678 { 3679 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4; 3680 } 3681 3682 static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id) 3683 { 3684 return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >= 4; 3685 } 3686 3687 static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) 3688 { 3689 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0; 3690 } 3691 3692 static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id) 3693 { 3694 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2; 3695 } 3696 3697 static inline bool isar_feature_aa32_pmu_8_1(const ARMISARegisters *id) 3698 { 3699 /* 0xf means "non-standard IMPDEF PMU" */ 3700 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 && 3701 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3702 } 3703 3704 static inline bool isar_feature_aa32_pmu_8_4(const ARMISARegisters *id) 3705 { 3706 /* 0xf means "non-standard IMPDEF PMU" */ 3707 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 5 && 3708 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3709 } 3710 3711 static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id) 3712 { 3713 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0; 3714 } 3715 3716 static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id) 3717 { 3718 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0; 3719 } 3720 3721 static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id) 3722 { 3723 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0; 3724 } 3725 3726 static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id) 3727 { 3728 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0; 3729 } 3730 3731 static inline bool isar_feature_aa32_dit(const ARMISARegisters *id) 3732 { 3733 return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0; 3734 } 3735 3736 static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id) 3737 { 3738 return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0; 3739 } 3740 3741 static inline bool isar_feature_aa32_debugv7p1(const ARMISARegisters *id) 3742 { 3743 return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 5; 3744 } 3745 3746 static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id) 3747 { 3748 return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 8; 3749 } 3750 3751 static inline bool isar_feature_aa32_doublelock(const ARMISARegisters *id) 3752 { 3753 return FIELD_EX32(id->dbgdevid, DBGDEVID, DOUBLELOCK) > 0; 3754 } 3755 3756 /* 3757 * 64-bit feature tests via id registers. 3758 */ 3759 static inline bool isar_feature_aa64_aes(const ARMISARegisters *id) 3760 { 3761 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0; 3762 } 3763 3764 static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id) 3765 { 3766 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1; 3767 } 3768 3769 static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id) 3770 { 3771 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0; 3772 } 3773 3774 static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id) 3775 { 3776 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0; 3777 } 3778 3779 static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id) 3780 { 3781 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1; 3782 } 3783 3784 static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id) 3785 { 3786 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0; 3787 } 3788 3789 static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id) 3790 { 3791 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0; 3792 } 3793 3794 static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) 3795 { 3796 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0; 3797 } 3798 3799 static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id) 3800 { 3801 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0; 3802 } 3803 3804 static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id) 3805 { 3806 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0; 3807 } 3808 3809 static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id) 3810 { 3811 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0; 3812 } 3813 3814 static inline bool isar_feature_aa64_dp(const ARMISARegisters *id) 3815 { 3816 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0; 3817 } 3818 3819 static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id) 3820 { 3821 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0; 3822 } 3823 3824 static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id) 3825 { 3826 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0; 3827 } 3828 3829 static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id) 3830 { 3831 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2; 3832 } 3833 3834 static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id) 3835 { 3836 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0; 3837 } 3838 3839 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) 3840 { 3841 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0; 3842 } 3843 3844 static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) 3845 { 3846 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0; 3847 } 3848 3849 static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) 3850 { 3851 /* 3852 * Return true if any form of pauth is enabled, as this 3853 * predicate controls migration of the 128-bit keys. 3854 */ 3855 return (id->id_aa64isar1 & 3856 (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) | 3857 FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) | 3858 FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) | 3859 FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0; 3860 } 3861 3862 static inline bool isar_feature_aa64_pauth_arch(const ARMISARegisters *id) 3863 { 3864 /* 3865 * Return true if pauth is enabled with the architected QARMA algorithm. 3866 * QEMU will always set APA+GPA to the same value. 3867 */ 3868 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0; 3869 } 3870 3871 static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id) 3872 { 3873 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2; 3874 } 3875 3876 static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id) 3877 { 3878 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) != 0; 3879 } 3880 3881 static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) 3882 { 3883 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0; 3884 } 3885 3886 static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id) 3887 { 3888 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0; 3889 } 3890 3891 static inline bool isar_feature_aa64_frint(const ARMISARegisters *id) 3892 { 3893 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0; 3894 } 3895 3896 static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id) 3897 { 3898 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) != 0; 3899 } 3900 3901 static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id) 3902 { 3903 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2; 3904 } 3905 3906 static inline bool isar_feature_aa64_bf16(const ARMISARegisters *id) 3907 { 3908 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) != 0; 3909 } 3910 3911 static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id) 3912 { 3913 /* We always set the AdvSIMD and FP fields identically. */ 3914 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf; 3915 } 3916 3917 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) 3918 { 3919 /* We always set the AdvSIMD and FP fields identically wrt FP16. */ 3920 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 3921 } 3922 3923 static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id) 3924 { 3925 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2; 3926 } 3927 3928 static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id) 3929 { 3930 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2; 3931 } 3932 3933 static inline bool isar_feature_aa64_aa32_el2(const ARMISARegisters *id) 3934 { 3935 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL2) >= 2; 3936 } 3937 3938 static inline bool isar_feature_aa64_ras(const ARMISARegisters *id) 3939 { 3940 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) != 0; 3941 } 3942 3943 static inline bool isar_feature_aa64_doublefault(const ARMISARegisters *id) 3944 { 3945 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) >= 2; 3946 } 3947 3948 static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) 3949 { 3950 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; 3951 } 3952 3953 static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id) 3954 { 3955 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) != 0; 3956 } 3957 3958 static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) 3959 { 3960 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0; 3961 } 3962 3963 static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) 3964 { 3965 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; 3966 } 3967 3968 static inline bool isar_feature_aa64_pan(const ARMISARegisters *id) 3969 { 3970 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0; 3971 } 3972 3973 static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id) 3974 { 3975 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2; 3976 } 3977 3978 static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id) 3979 { 3980 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HCX) != 0; 3981 } 3982 3983 static inline bool isar_feature_aa64_uao(const ARMISARegisters *id) 3984 { 3985 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0; 3986 } 3987 3988 static inline bool isar_feature_aa64_st(const ARMISARegisters *id) 3989 { 3990 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0; 3991 } 3992 3993 static inline bool isar_feature_aa64_fwb(const ARMISARegisters *id) 3994 { 3995 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, FWB) != 0; 3996 } 3997 3998 static inline bool isar_feature_aa64_ids(const ARMISARegisters *id) 3999 { 4000 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, IDS) != 0; 4001 } 4002 4003 static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) 4004 { 4005 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; 4006 } 4007 4008 static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id) 4009 { 4010 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0; 4011 } 4012 4013 static inline bool isar_feature_aa64_mte(const ARMISARegisters *id) 4014 { 4015 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2; 4016 } 4017 4018 static inline bool isar_feature_aa64_sme(const ARMISARegisters *id) 4019 { 4020 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SME) != 0; 4021 } 4022 4023 static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id) 4024 { 4025 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 && 4026 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 4027 } 4028 4029 static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id) 4030 { 4031 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 && 4032 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 4033 } 4034 4035 static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id) 4036 { 4037 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0; 4038 } 4039 4040 static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id) 4041 { 4042 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2; 4043 } 4044 4045 static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id) 4046 { 4047 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0; 4048 } 4049 4050 static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id) 4051 { 4052 return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1; 4053 } 4054 4055 static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *id) 4056 { 4057 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2); 4058 return t >= 3 || (t == 0 && isar_feature_aa64_tgran4_lpa2(id)); 4059 } 4060 4061 static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *id) 4062 { 4063 return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 2; 4064 } 4065 4066 static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id) 4067 { 4068 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2); 4069 return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id)); 4070 } 4071 4072 static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) 4073 { 4074 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0; 4075 } 4076 4077 static inline bool isar_feature_aa64_lva(const ARMISARegisters *id) 4078 { 4079 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) != 0; 4080 } 4081 4082 static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id) 4083 { 4084 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0; 4085 } 4086 4087 static inline bool isar_feature_aa64_dit(const ARMISARegisters *id) 4088 { 4089 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0; 4090 } 4091 4092 static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id) 4093 { 4094 int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2); 4095 if (key >= 2) { 4096 return true; /* FEAT_CSV2_2 */ 4097 } 4098 if (key == 1) { 4099 key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC); 4100 return key >= 2; /* FEAT_CSV2_1p2 */ 4101 } 4102 return false; 4103 } 4104 4105 static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id) 4106 { 4107 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0; 4108 } 4109 4110 static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id) 4111 { 4112 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >= 8; 4113 } 4114 4115 static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id) 4116 { 4117 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0; 4118 } 4119 4120 static inline bool isar_feature_aa64_sve2_aes(const ARMISARegisters *id) 4121 { 4122 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) != 0; 4123 } 4124 4125 static inline bool isar_feature_aa64_sve2_pmull128(const ARMISARegisters *id) 4126 { 4127 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) >= 2; 4128 } 4129 4130 static inline bool isar_feature_aa64_sve2_bitperm(const ARMISARegisters *id) 4131 { 4132 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BITPERM) != 0; 4133 } 4134 4135 static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id) 4136 { 4137 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BFLOAT16) != 0; 4138 } 4139 4140 static inline bool isar_feature_aa64_sve2_sha3(const ARMISARegisters *id) 4141 { 4142 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SHA3) != 0; 4143 } 4144 4145 static inline bool isar_feature_aa64_sve2_sm4(const ARMISARegisters *id) 4146 { 4147 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SM4) != 0; 4148 } 4149 4150 static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id) 4151 { 4152 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, I8MM) != 0; 4153 } 4154 4155 static inline bool isar_feature_aa64_sve_f32mm(const ARMISARegisters *id) 4156 { 4157 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F32MM) != 0; 4158 } 4159 4160 static inline bool isar_feature_aa64_sve_f64mm(const ARMISARegisters *id) 4161 { 4162 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F64MM) != 0; 4163 } 4164 4165 static inline bool isar_feature_aa64_sme_f64f64(const ARMISARegisters *id) 4166 { 4167 return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, F64F64); 4168 } 4169 4170 static inline bool isar_feature_aa64_sme_i16i64(const ARMISARegisters *id) 4171 { 4172 return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, I16I64) == 0xf; 4173 } 4174 4175 static inline bool isar_feature_aa64_sme_fa64(const ARMISARegisters *id) 4176 { 4177 return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, FA64); 4178 } 4179 4180 static inline bool isar_feature_aa64_doublelock(const ARMISARegisters *id) 4181 { 4182 return FIELD_SEX64(id->id_aa64dfr0, ID_AA64DFR0, DOUBLELOCK) >= 0; 4183 } 4184 4185 /* 4186 * Feature tests for "does this exist in either 32-bit or 64-bit?" 4187 */ 4188 static inline bool isar_feature_any_fp16(const ARMISARegisters *id) 4189 { 4190 return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id); 4191 } 4192 4193 static inline bool isar_feature_any_predinv(const ARMISARegisters *id) 4194 { 4195 return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id); 4196 } 4197 4198 static inline bool isar_feature_any_pmu_8_1(const ARMISARegisters *id) 4199 { 4200 return isar_feature_aa64_pmu_8_1(id) || isar_feature_aa32_pmu_8_1(id); 4201 } 4202 4203 static inline bool isar_feature_any_pmu_8_4(const ARMISARegisters *id) 4204 { 4205 return isar_feature_aa64_pmu_8_4(id) || isar_feature_aa32_pmu_8_4(id); 4206 } 4207 4208 static inline bool isar_feature_any_ccidx(const ARMISARegisters *id) 4209 { 4210 return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id); 4211 } 4212 4213 static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id) 4214 { 4215 return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id); 4216 } 4217 4218 static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id) 4219 { 4220 return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(id); 4221 } 4222 4223 static inline bool isar_feature_any_ras(const ARMISARegisters *id) 4224 { 4225 return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id); 4226 } 4227 4228 /* 4229 * Forward to the above feature tests given an ARMCPU pointer. 4230 */ 4231 #define cpu_isar_feature(name, cpu) \ 4232 ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); }) 4233 4234 #endif 4235