1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "qemu/cpu-float.h" 25 #include "hw/registerfields.h" 26 #include "cpu-qom.h" 27 #include "exec/cpu-defs.h" 28 #include "qapi/qapi-types-common.h" 29 30 /* ARM processors have a weak memory model */ 31 #define TCG_GUEST_DEFAULT_MO (0) 32 33 #ifdef TARGET_AARCH64 34 #define KVM_HAVE_MCE_INJECTION 1 35 #endif 36 37 #define EXCP_UDEF 1 /* undefined instruction */ 38 #define EXCP_SWI 2 /* software interrupt */ 39 #define EXCP_PREFETCH_ABORT 3 40 #define EXCP_DATA_ABORT 4 41 #define EXCP_IRQ 5 42 #define EXCP_FIQ 6 43 #define EXCP_BKPT 7 44 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 45 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 46 #define EXCP_HVC 11 /* HyperVisor Call */ 47 #define EXCP_HYP_TRAP 12 48 #define EXCP_SMC 13 /* Secure Monitor Call */ 49 #define EXCP_VIRQ 14 50 #define EXCP_VFIQ 15 51 #define EXCP_SEMIHOST 16 /* semihosting call */ 52 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 53 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 54 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 55 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ 56 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ 57 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ 58 #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ 59 #define EXCP_VSERR 24 60 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 61 62 #define ARMV7M_EXCP_RESET 1 63 #define ARMV7M_EXCP_NMI 2 64 #define ARMV7M_EXCP_HARD 3 65 #define ARMV7M_EXCP_MEM 4 66 #define ARMV7M_EXCP_BUS 5 67 #define ARMV7M_EXCP_USAGE 6 68 #define ARMV7M_EXCP_SECURE 7 69 #define ARMV7M_EXCP_SVC 11 70 #define ARMV7M_EXCP_DEBUG 12 71 #define ARMV7M_EXCP_PENDSV 14 72 #define ARMV7M_EXCP_SYSTICK 15 73 74 /* For M profile, some registers are banked secure vs non-secure; 75 * these are represented as a 2-element array where the first element 76 * is the non-secure copy and the second is the secure copy. 77 * When the CPU does not have implement the security extension then 78 * only the first element is used. 79 * This means that the copy for the current security state can be 80 * accessed via env->registerfield[env->v7m.secure] (whether the security 81 * extension is implemented or not). 82 */ 83 enum { 84 M_REG_NS = 0, 85 M_REG_S = 1, 86 M_REG_NUM_BANKS = 2, 87 }; 88 89 /* ARM-specific interrupt pending bits. */ 90 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 91 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 92 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 93 #define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0 94 95 /* The usual mapping for an AArch64 system register to its AArch32 96 * counterpart is for the 32 bit world to have access to the lower 97 * half only (with writes leaving the upper half untouched). It's 98 * therefore useful to be able to pass TCG the offset of the least 99 * significant half of a uint64_t struct member. 100 */ 101 #if HOST_BIG_ENDIAN 102 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 103 #define offsetofhigh32(S, M) offsetof(S, M) 104 #else 105 #define offsetoflow32(S, M) offsetof(S, M) 106 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 107 #endif 108 109 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 110 #define ARM_CPU_IRQ 0 111 #define ARM_CPU_FIQ 1 112 #define ARM_CPU_VIRQ 2 113 #define ARM_CPU_VFIQ 3 114 115 /* ARM-specific extra insn start words: 116 * 1: Conditional execution bits 117 * 2: Partial exception syndrome for data aborts 118 */ 119 #define TARGET_INSN_START_EXTRA_WORDS 2 120 121 /* The 2nd extra word holding syndrome info for data aborts does not use 122 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 123 * help the sleb128 encoder do a better job. 124 * When restoring the CPU state, we shift it back up. 125 */ 126 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 127 #define ARM_INSN_START_WORD2_SHIFT 14 128 129 /* We currently assume float and double are IEEE single and double 130 precision respectively. 131 Doing runtime conversions is tricky because VFP registers may contain 132 integer values (eg. as the result of a FTOSI instruction). 133 s<2n> maps to the least significant half of d<n> 134 s<2n+1> maps to the most significant half of d<n> 135 */ 136 137 /** 138 * DynamicGDBXMLInfo: 139 * @desc: Contains the XML descriptions. 140 * @num: Number of the registers in this XML seen by GDB. 141 * @data: A union with data specific to the set of registers 142 * @cpregs_keys: Array that contains the corresponding Key of 143 * a given cpreg with the same order of the cpreg 144 * in the XML description. 145 */ 146 typedef struct DynamicGDBXMLInfo { 147 char *desc; 148 int num; 149 union { 150 struct { 151 uint32_t *keys; 152 } cpregs; 153 } data; 154 } DynamicGDBXMLInfo; 155 156 /* CPU state for each instance of a generic timer (in cp15 c14) */ 157 typedef struct ARMGenericTimer { 158 uint64_t cval; /* Timer CompareValue register */ 159 uint64_t ctl; /* Timer Control register */ 160 } ARMGenericTimer; 161 162 #define GTIMER_PHYS 0 163 #define GTIMER_VIRT 1 164 #define GTIMER_HYP 2 165 #define GTIMER_SEC 3 166 #define GTIMER_HYPVIRT 4 167 #define NUM_GTIMERS 5 168 169 typedef struct { 170 uint64_t raw_tcr; 171 uint32_t mask; 172 uint32_t base_mask; 173 } TCR; 174 175 #define VTCR_NSW (1u << 29) 176 #define VTCR_NSA (1u << 30) 177 #define VSTCR_SW VTCR_NSW 178 #define VSTCR_SA VTCR_NSA 179 180 /* Define a maximum sized vector register. 181 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 182 * For 64-bit, this is a 2048-bit SVE register. 183 * 184 * Note that the mapping between S, D, and Q views of the register bank 185 * differs between AArch64 and AArch32. 186 * In AArch32: 187 * Qn = regs[n].d[1]:regs[n].d[0] 188 * Dn = regs[n / 2].d[n & 1] 189 * Sn = regs[n / 4].d[n % 4 / 2], 190 * bits 31..0 for even n, and bits 63..32 for odd n 191 * (and regs[16] to regs[31] are inaccessible) 192 * In AArch64: 193 * Zn = regs[n].d[*] 194 * Qn = regs[n].d[1]:regs[n].d[0] 195 * Dn = regs[n].d[0] 196 * Sn = regs[n].d[0] bits 31..0 197 * Hn = regs[n].d[0] bits 15..0 198 * 199 * This corresponds to the architecturally defined mapping between 200 * the two execution states, and means we do not need to explicitly 201 * map these registers when changing states. 202 * 203 * Align the data for use with TCG host vector operations. 204 */ 205 206 #ifdef TARGET_AARCH64 207 # define ARM_MAX_VQ 16 208 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); 209 void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); 210 void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp); 211 #else 212 # define ARM_MAX_VQ 1 213 static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { } 214 static inline void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { } 215 static inline void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) { } 216 #endif 217 218 typedef struct ARMVectorReg { 219 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 220 } ARMVectorReg; 221 222 #ifdef TARGET_AARCH64 223 /* In AArch32 mode, predicate registers do not exist at all. */ 224 typedef struct ARMPredicateReg { 225 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); 226 } ARMPredicateReg; 227 228 /* In AArch32 mode, PAC keys do not exist at all. */ 229 typedef struct ARMPACKey { 230 uint64_t lo, hi; 231 } ARMPACKey; 232 #endif 233 234 /* See the commentary above the TBFLAG field definitions. */ 235 typedef struct CPUARMTBFlags { 236 uint32_t flags; 237 target_ulong flags2; 238 } CPUARMTBFlags; 239 240 typedef struct CPUArchState { 241 /* Regs for current mode. */ 242 uint32_t regs[16]; 243 244 /* 32/64 switch only happens when taking and returning from 245 * exceptions so the overlap semantics are taken care of then 246 * instead of having a complicated union. 247 */ 248 /* Regs for A64 mode. */ 249 uint64_t xregs[32]; 250 uint64_t pc; 251 /* PSTATE isn't an architectural register for ARMv8. However, it is 252 * convenient for us to assemble the underlying state into a 32 bit format 253 * identical to the architectural format used for the SPSR. (This is also 254 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 255 * 'pstate' register are.) Of the PSTATE bits: 256 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 257 * semantics as for AArch32, as described in the comments on each field) 258 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 259 * DAIF (exception masks) are kept in env->daif 260 * BTYPE is kept in env->btype 261 * all other bits are stored in their correct places in env->pstate 262 */ 263 uint32_t pstate; 264 bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nRW */ 265 bool thumb; /* True if CPU is in thumb mode; cpsr[5] */ 266 267 /* Cached TBFLAGS state. See below for which bits are included. */ 268 CPUARMTBFlags hflags; 269 270 /* Frequently accessed CPSR bits are stored separately for efficiency. 271 This contains all the other bits. Use cpsr_{read,write} to access 272 the whole CPSR. */ 273 uint32_t uncached_cpsr; 274 uint32_t spsr; 275 276 /* Banked registers. */ 277 uint64_t banked_spsr[8]; 278 uint32_t banked_r13[8]; 279 uint32_t banked_r14[8]; 280 281 /* These hold r8-r12. */ 282 uint32_t usr_regs[5]; 283 uint32_t fiq_regs[5]; 284 285 /* cpsr flag cache for faster execution */ 286 uint32_t CF; /* 0 or 1 */ 287 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 288 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 289 uint32_t ZF; /* Z set if zero. */ 290 uint32_t QF; /* 0 or 1 */ 291 uint32_t GE; /* cpsr[19:16] */ 292 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 293 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 294 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 295 296 uint64_t elr_el[4]; /* AArch64 exception link regs */ 297 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 298 299 /* System control coprocessor (cp15) */ 300 struct { 301 uint32_t c0_cpuid; 302 union { /* Cache size selection */ 303 struct { 304 uint64_t _unused_csselr0; 305 uint64_t csselr_ns; 306 uint64_t _unused_csselr1; 307 uint64_t csselr_s; 308 }; 309 uint64_t csselr_el[4]; 310 }; 311 union { /* System control register. */ 312 struct { 313 uint64_t _unused_sctlr; 314 uint64_t sctlr_ns; 315 uint64_t hsctlr; 316 uint64_t sctlr_s; 317 }; 318 uint64_t sctlr_el[4]; 319 }; 320 uint64_t cpacr_el1; /* Architectural feature access control register */ 321 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 322 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 323 uint64_t sder; /* Secure debug enable register. */ 324 uint32_t nsacr; /* Non-secure access control register. */ 325 union { /* MMU translation table base 0. */ 326 struct { 327 uint64_t _unused_ttbr0_0; 328 uint64_t ttbr0_ns; 329 uint64_t _unused_ttbr0_1; 330 uint64_t ttbr0_s; 331 }; 332 uint64_t ttbr0_el[4]; 333 }; 334 union { /* MMU translation table base 1. */ 335 struct { 336 uint64_t _unused_ttbr1_0; 337 uint64_t ttbr1_ns; 338 uint64_t _unused_ttbr1_1; 339 uint64_t ttbr1_s; 340 }; 341 uint64_t ttbr1_el[4]; 342 }; 343 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 344 uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ 345 /* MMU translation table base control. */ 346 TCR tcr_el[4]; 347 TCR vtcr_el2; /* Virtualization Translation Control. */ 348 TCR vstcr_el2; /* Secure Virtualization Translation Control. */ 349 uint32_t c2_data; /* MPU data cacheable bits. */ 350 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 351 union { /* MMU domain access control register 352 * MPU write buffer control. 353 */ 354 struct { 355 uint64_t dacr_ns; 356 uint64_t dacr_s; 357 }; 358 struct { 359 uint64_t dacr32_el2; 360 }; 361 }; 362 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 363 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 364 uint64_t hcr_el2; /* Hypervisor configuration register */ 365 uint64_t scr_el3; /* Secure configuration register. */ 366 union { /* Fault status registers. */ 367 struct { 368 uint64_t ifsr_ns; 369 uint64_t ifsr_s; 370 }; 371 struct { 372 uint64_t ifsr32_el2; 373 }; 374 }; 375 union { 376 struct { 377 uint64_t _unused_dfsr; 378 uint64_t dfsr_ns; 379 uint64_t hsr; 380 uint64_t dfsr_s; 381 }; 382 uint64_t esr_el[4]; 383 }; 384 uint32_t c6_region[8]; /* MPU base/size registers. */ 385 union { /* Fault address registers. */ 386 struct { 387 uint64_t _unused_far0; 388 #if HOST_BIG_ENDIAN 389 uint32_t ifar_ns; 390 uint32_t dfar_ns; 391 uint32_t ifar_s; 392 uint32_t dfar_s; 393 #else 394 uint32_t dfar_ns; 395 uint32_t ifar_ns; 396 uint32_t dfar_s; 397 uint32_t ifar_s; 398 #endif 399 uint64_t _unused_far3; 400 }; 401 uint64_t far_el[4]; 402 }; 403 uint64_t hpfar_el2; 404 uint64_t hstr_el2; 405 union { /* Translation result. */ 406 struct { 407 uint64_t _unused_par_0; 408 uint64_t par_ns; 409 uint64_t _unused_par_1; 410 uint64_t par_s; 411 }; 412 uint64_t par_el[4]; 413 }; 414 415 uint32_t c9_insn; /* Cache lockdown registers. */ 416 uint32_t c9_data; 417 uint64_t c9_pmcr; /* performance monitor control register */ 418 uint64_t c9_pmcnten; /* perf monitor counter enables */ 419 uint64_t c9_pmovsr; /* perf monitor overflow status */ 420 uint64_t c9_pmuserenr; /* perf monitor user enable */ 421 uint64_t c9_pmselr; /* perf monitor counter selection register */ 422 uint64_t c9_pminten; /* perf monitor interrupt enables */ 423 union { /* Memory attribute redirection */ 424 struct { 425 #if HOST_BIG_ENDIAN 426 uint64_t _unused_mair_0; 427 uint32_t mair1_ns; 428 uint32_t mair0_ns; 429 uint64_t _unused_mair_1; 430 uint32_t mair1_s; 431 uint32_t mair0_s; 432 #else 433 uint64_t _unused_mair_0; 434 uint32_t mair0_ns; 435 uint32_t mair1_ns; 436 uint64_t _unused_mair_1; 437 uint32_t mair0_s; 438 uint32_t mair1_s; 439 #endif 440 }; 441 uint64_t mair_el[4]; 442 }; 443 union { /* vector base address register */ 444 struct { 445 uint64_t _unused_vbar; 446 uint64_t vbar_ns; 447 uint64_t hvbar; 448 uint64_t vbar_s; 449 }; 450 uint64_t vbar_el[4]; 451 }; 452 uint32_t mvbar; /* (monitor) vector base address register */ 453 uint64_t rvbar; /* rvbar sampled from rvbar property at reset */ 454 struct { /* FCSE PID. */ 455 uint32_t fcseidr_ns; 456 uint32_t fcseidr_s; 457 }; 458 union { /* Context ID. */ 459 struct { 460 uint64_t _unused_contextidr_0; 461 uint64_t contextidr_ns; 462 uint64_t _unused_contextidr_1; 463 uint64_t contextidr_s; 464 }; 465 uint64_t contextidr_el[4]; 466 }; 467 union { /* User RW Thread register. */ 468 struct { 469 uint64_t tpidrurw_ns; 470 uint64_t tpidrprw_ns; 471 uint64_t htpidr; 472 uint64_t _tpidr_el3; 473 }; 474 uint64_t tpidr_el[4]; 475 }; 476 /* The secure banks of these registers don't map anywhere */ 477 uint64_t tpidrurw_s; 478 uint64_t tpidrprw_s; 479 uint64_t tpidruro_s; 480 481 union { /* User RO Thread register. */ 482 uint64_t tpidruro_ns; 483 uint64_t tpidrro_el[1]; 484 }; 485 uint64_t c14_cntfrq; /* Counter Frequency register */ 486 uint64_t c14_cntkctl; /* Timer Control register */ 487 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 488 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 489 ARMGenericTimer c14_timer[NUM_GTIMERS]; 490 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 491 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 492 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 493 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 494 uint32_t c15_threadid; /* TI debugger thread-ID. */ 495 uint32_t c15_config_base_address; /* SCU base address. */ 496 uint32_t c15_diagnostic; /* diagnostic register */ 497 uint32_t c15_power_diagnostic; 498 uint32_t c15_power_control; /* power control */ 499 uint64_t dbgbvr[16]; /* breakpoint value registers */ 500 uint64_t dbgbcr[16]; /* breakpoint control registers */ 501 uint64_t dbgwvr[16]; /* watchpoint value registers */ 502 uint64_t dbgwcr[16]; /* watchpoint control registers */ 503 uint64_t mdscr_el1; 504 uint64_t oslsr_el1; /* OS Lock Status */ 505 uint64_t mdcr_el2; 506 uint64_t mdcr_el3; 507 /* Stores the architectural value of the counter *the last time it was 508 * updated* by pmccntr_op_start. Accesses should always be surrounded 509 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 510 * architecturally-correct value is being read/set. 511 */ 512 uint64_t c15_ccnt; 513 /* Stores the delta between the architectural value and the underlying 514 * cycle count during normal operation. It is used to update c15_ccnt 515 * to be the correct architectural value before accesses. During 516 * accesses, c15_ccnt_delta contains the underlying count being used 517 * for the access, after which it reverts to the delta value in 518 * pmccntr_op_finish. 519 */ 520 uint64_t c15_ccnt_delta; 521 uint64_t c14_pmevcntr[31]; 522 uint64_t c14_pmevcntr_delta[31]; 523 uint64_t c14_pmevtyper[31]; 524 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 525 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 526 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 527 uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ 528 uint64_t gcr_el1; 529 uint64_t rgsr_el1; 530 531 /* Minimal RAS registers */ 532 uint64_t disr_el1; 533 uint64_t vdisr_el2; 534 uint64_t vsesr_el2; 535 } cp15; 536 537 struct { 538 /* M profile has up to 4 stack pointers: 539 * a Main Stack Pointer and a Process Stack Pointer for each 540 * of the Secure and Non-Secure states. (If the CPU doesn't support 541 * the security extension then it has only two SPs.) 542 * In QEMU we always store the currently active SP in regs[13], 543 * and the non-active SP for the current security state in 544 * v7m.other_sp. The stack pointers for the inactive security state 545 * are stored in other_ss_msp and other_ss_psp. 546 * switch_v7m_security_state() is responsible for rearranging them 547 * when we change security state. 548 */ 549 uint32_t other_sp; 550 uint32_t other_ss_msp; 551 uint32_t other_ss_psp; 552 uint32_t vecbase[M_REG_NUM_BANKS]; 553 uint32_t basepri[M_REG_NUM_BANKS]; 554 uint32_t control[M_REG_NUM_BANKS]; 555 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 556 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 557 uint32_t hfsr; /* HardFault Status */ 558 uint32_t dfsr; /* Debug Fault Status Register */ 559 uint32_t sfsr; /* Secure Fault Status Register */ 560 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 561 uint32_t bfar; /* BusFault Address */ 562 uint32_t sfar; /* Secure Fault Address Register */ 563 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 564 int exception; 565 uint32_t primask[M_REG_NUM_BANKS]; 566 uint32_t faultmask[M_REG_NUM_BANKS]; 567 uint32_t aircr; /* only holds r/w state if security extn implemented */ 568 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 569 uint32_t csselr[M_REG_NUM_BANKS]; 570 uint32_t scr[M_REG_NUM_BANKS]; 571 uint32_t msplim[M_REG_NUM_BANKS]; 572 uint32_t psplim[M_REG_NUM_BANKS]; 573 uint32_t fpcar[M_REG_NUM_BANKS]; 574 uint32_t fpccr[M_REG_NUM_BANKS]; 575 uint32_t fpdscr[M_REG_NUM_BANKS]; 576 uint32_t cpacr[M_REG_NUM_BANKS]; 577 uint32_t nsacr; 578 uint32_t ltpsize; 579 uint32_t vpr; 580 } v7m; 581 582 /* Information associated with an exception about to be taken: 583 * code which raises an exception must set cs->exception_index and 584 * the relevant parts of this structure; the cpu_do_interrupt function 585 * will then set the guest-visible registers as part of the exception 586 * entry process. 587 */ 588 struct { 589 uint32_t syndrome; /* AArch64 format syndrome register */ 590 uint32_t fsr; /* AArch32 format fault status register info */ 591 uint64_t vaddress; /* virtual addr associated with exception, if any */ 592 uint32_t target_el; /* EL the exception should be targeted for */ 593 /* If we implement EL2 we will also need to store information 594 * about the intermediate physical address for stage 2 faults. 595 */ 596 } exception; 597 598 /* Information associated with an SError */ 599 struct { 600 uint8_t pending; 601 uint8_t has_esr; 602 uint64_t esr; 603 } serror; 604 605 uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */ 606 607 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 608 uint32_t irq_line_state; 609 610 /* Thumb-2 EE state. */ 611 uint32_t teecr; 612 uint32_t teehbr; 613 614 /* VFP coprocessor state. */ 615 struct { 616 ARMVectorReg zregs[32]; 617 618 #ifdef TARGET_AARCH64 619 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 620 #define FFR_PRED_NUM 16 621 ARMPredicateReg pregs[17]; 622 /* Scratch space for aa64 sve predicate temporary. */ 623 ARMPredicateReg preg_tmp; 624 #endif 625 626 /* We store these fpcsr fields separately for convenience. */ 627 uint32_t qc[4] QEMU_ALIGNED(16); 628 int vec_len; 629 int vec_stride; 630 631 uint32_t xregs[16]; 632 633 /* Scratch space for aa32 neon expansion. */ 634 uint32_t scratch[8]; 635 636 /* There are a number of distinct float control structures: 637 * 638 * fp_status: is the "normal" fp status. 639 * fp_status_fp16: used for half-precision calculations 640 * standard_fp_status : the ARM "Standard FPSCR Value" 641 * standard_fp_status_fp16 : used for half-precision 642 * calculations with the ARM "Standard FPSCR Value" 643 * 644 * Half-precision operations are governed by a separate 645 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 646 * status structure to control this. 647 * 648 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 649 * round-to-nearest and is used by any operations (generally 650 * Neon) which the architecture defines as controlled by the 651 * standard FPSCR value rather than the FPSCR. 652 * 653 * The "standard FPSCR but for fp16 ops" is needed because 654 * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than 655 * using a fixed value for it. 656 * 657 * To avoid having to transfer exception bits around, we simply 658 * say that the FPSCR cumulative exception flags are the logical 659 * OR of the flags in the four fp statuses. This relies on the 660 * only thing which needs to read the exception flags being 661 * an explicit FPSCR read. 662 */ 663 float_status fp_status; 664 float_status fp_status_f16; 665 float_status standard_fp_status; 666 float_status standard_fp_status_f16; 667 668 /* ZCR_EL[1-3] */ 669 uint64_t zcr_el[4]; 670 } vfp; 671 uint64_t exclusive_addr; 672 uint64_t exclusive_val; 673 uint64_t exclusive_high; 674 675 /* iwMMXt coprocessor state. */ 676 struct { 677 uint64_t regs[16]; 678 uint64_t val; 679 680 uint32_t cregs[16]; 681 } iwmmxt; 682 683 #ifdef TARGET_AARCH64 684 struct { 685 ARMPACKey apia; 686 ARMPACKey apib; 687 ARMPACKey apda; 688 ARMPACKey apdb; 689 ARMPACKey apga; 690 } keys; 691 692 uint64_t scxtnum_el[4]; 693 #endif 694 695 #if defined(CONFIG_USER_ONLY) 696 /* For usermode syscall translation. */ 697 int eabi; 698 #endif 699 700 struct CPUBreakpoint *cpu_breakpoint[16]; 701 struct CPUWatchpoint *cpu_watchpoint[16]; 702 703 /* Fields up to this point are cleared by a CPU reset */ 704 struct {} end_reset_fields; 705 706 /* Fields after this point are preserved across CPU reset. */ 707 708 /* Internal CPU feature flags. */ 709 uint64_t features; 710 711 /* PMSAv7 MPU */ 712 struct { 713 uint32_t *drbar; 714 uint32_t *drsr; 715 uint32_t *dracr; 716 uint32_t rnr[M_REG_NUM_BANKS]; 717 } pmsav7; 718 719 /* PMSAv8 MPU */ 720 struct { 721 /* The PMSAv8 implementation also shares some PMSAv7 config 722 * and state: 723 * pmsav7.rnr (region number register) 724 * pmsav7_dregion (number of configured regions) 725 */ 726 uint32_t *rbar[M_REG_NUM_BANKS]; 727 uint32_t *rlar[M_REG_NUM_BANKS]; 728 uint32_t mair0[M_REG_NUM_BANKS]; 729 uint32_t mair1[M_REG_NUM_BANKS]; 730 } pmsav8; 731 732 /* v8M SAU */ 733 struct { 734 uint32_t *rbar; 735 uint32_t *rlar; 736 uint32_t rnr; 737 uint32_t ctrl; 738 } sau; 739 740 void *nvic; 741 const struct arm_boot_info *boot_info; 742 /* Store GICv3CPUState to access from this struct */ 743 void *gicv3state; 744 745 #ifdef TARGET_TAGGED_ADDRESSES 746 /* Linux syscall tagged address support */ 747 bool tagged_addr_enable; 748 #endif 749 } CPUARMState; 750 751 static inline void set_feature(CPUARMState *env, int feature) 752 { 753 env->features |= 1ULL << feature; 754 } 755 756 static inline void unset_feature(CPUARMState *env, int feature) 757 { 758 env->features &= ~(1ULL << feature); 759 } 760 761 /** 762 * ARMELChangeHookFn: 763 * type of a function which can be registered via arm_register_el_change_hook() 764 * to get callbacks when the CPU changes its exception level or mode. 765 */ 766 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 767 typedef struct ARMELChangeHook ARMELChangeHook; 768 struct ARMELChangeHook { 769 ARMELChangeHookFn *hook; 770 void *opaque; 771 QLIST_ENTRY(ARMELChangeHook) node; 772 }; 773 774 /* These values map onto the return values for 775 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 776 typedef enum ARMPSCIState { 777 PSCI_ON = 0, 778 PSCI_OFF = 1, 779 PSCI_ON_PENDING = 2 780 } ARMPSCIState; 781 782 typedef struct ARMISARegisters ARMISARegisters; 783 784 /** 785 * ARMCPU: 786 * @env: #CPUARMState 787 * 788 * An ARM CPU core. 789 */ 790 struct ArchCPU { 791 /*< private >*/ 792 CPUState parent_obj; 793 /*< public >*/ 794 795 CPUNegativeOffsetState neg; 796 CPUARMState env; 797 798 /* Coprocessor information */ 799 GHashTable *cp_regs; 800 /* For marshalling (mostly coprocessor) register state between the 801 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 802 * we use these arrays. 803 */ 804 /* List of register indexes managed via these arrays; (full KVM style 805 * 64 bit indexes, not CPRegInfo 32 bit indexes) 806 */ 807 uint64_t *cpreg_indexes; 808 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 809 uint64_t *cpreg_values; 810 /* Length of the indexes, values, reset_values arrays */ 811 int32_t cpreg_array_len; 812 /* These are used only for migration: incoming data arrives in 813 * these fields and is sanity checked in post_load before copying 814 * to the working data structures above. 815 */ 816 uint64_t *cpreg_vmstate_indexes; 817 uint64_t *cpreg_vmstate_values; 818 int32_t cpreg_vmstate_array_len; 819 820 DynamicGDBXMLInfo dyn_sysreg_xml; 821 DynamicGDBXMLInfo dyn_svereg_xml; 822 823 /* Timers used by the generic (architected) timer */ 824 QEMUTimer *gt_timer[NUM_GTIMERS]; 825 /* 826 * Timer used by the PMU. Its state is restored after migration by 827 * pmu_op_finish() - it does not need other handling during migration 828 */ 829 QEMUTimer *pmu_timer; 830 /* GPIO outputs for generic timer */ 831 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 832 /* GPIO output for GICv3 maintenance interrupt signal */ 833 qemu_irq gicv3_maintenance_interrupt; 834 /* GPIO output for the PMU interrupt */ 835 qemu_irq pmu_interrupt; 836 837 /* MemoryRegion to use for secure physical accesses */ 838 MemoryRegion *secure_memory; 839 840 /* MemoryRegion to use for allocation tag accesses */ 841 MemoryRegion *tag_memory; 842 MemoryRegion *secure_tag_memory; 843 844 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 845 Object *idau; 846 847 /* 'compatible' string for this CPU for Linux device trees */ 848 const char *dtb_compatible; 849 850 /* PSCI version for this CPU 851 * Bits[31:16] = Major Version 852 * Bits[15:0] = Minor Version 853 */ 854 uint32_t psci_version; 855 856 /* Current power state, access guarded by BQL */ 857 ARMPSCIState power_state; 858 859 /* CPU has virtualization extension */ 860 bool has_el2; 861 /* CPU has security extension */ 862 bool has_el3; 863 /* CPU has PMU (Performance Monitor Unit) */ 864 bool has_pmu; 865 /* CPU has VFP */ 866 bool has_vfp; 867 /* CPU has Neon */ 868 bool has_neon; 869 /* CPU has M-profile DSP extension */ 870 bool has_dsp; 871 872 /* CPU has memory protection unit */ 873 bool has_mpu; 874 /* PMSAv7 MPU number of supported regions */ 875 uint32_t pmsav7_dregion; 876 /* v8M SAU number of supported regions */ 877 uint32_t sau_sregion; 878 879 /* PSCI conduit used to invoke PSCI methods 880 * 0 - disabled, 1 - smc, 2 - hvc 881 */ 882 uint32_t psci_conduit; 883 884 /* For v8M, initial value of the Secure VTOR */ 885 uint32_t init_svtor; 886 /* For v8M, initial value of the Non-secure VTOR */ 887 uint32_t init_nsvtor; 888 889 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 890 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 891 */ 892 uint32_t kvm_target; 893 894 /* KVM init features for this CPU */ 895 uint32_t kvm_init_features[7]; 896 897 /* KVM CPU state */ 898 899 /* KVM virtual time adjustment */ 900 bool kvm_adjvtime; 901 bool kvm_vtime_dirty; 902 uint64_t kvm_vtime; 903 904 /* KVM steal time */ 905 OnOffAuto kvm_steal_time; 906 907 /* Uniprocessor system with MP extensions */ 908 bool mp_is_up; 909 910 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 911 * and the probe failed (so we need to report the error in realize) 912 */ 913 bool host_cpu_probe_failed; 914 915 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 916 * register. 917 */ 918 int32_t core_count; 919 920 /* The instance init functions for implementation-specific subclasses 921 * set these fields to specify the implementation-dependent values of 922 * various constant registers and reset values of non-constant 923 * registers. 924 * Some of these might become QOM properties eventually. 925 * Field names match the official register names as defined in the 926 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 927 * is used for reset values of non-constant registers; no reset_ 928 * prefix means a constant register. 929 * Some of these registers are split out into a substructure that 930 * is shared with the translators to control the ISA. 931 * 932 * Note that if you add an ID register to the ARMISARegisters struct 933 * you need to also update the 32-bit and 64-bit versions of the 934 * kvm_arm_get_host_cpu_features() function to correctly populate the 935 * field by reading the value from the KVM vCPU. 936 */ 937 struct ARMISARegisters { 938 uint32_t id_isar0; 939 uint32_t id_isar1; 940 uint32_t id_isar2; 941 uint32_t id_isar3; 942 uint32_t id_isar4; 943 uint32_t id_isar5; 944 uint32_t id_isar6; 945 uint32_t id_mmfr0; 946 uint32_t id_mmfr1; 947 uint32_t id_mmfr2; 948 uint32_t id_mmfr3; 949 uint32_t id_mmfr4; 950 uint32_t id_pfr0; 951 uint32_t id_pfr1; 952 uint32_t id_pfr2; 953 uint32_t mvfr0; 954 uint32_t mvfr1; 955 uint32_t mvfr2; 956 uint32_t id_dfr0; 957 uint32_t dbgdidr; 958 uint64_t id_aa64isar0; 959 uint64_t id_aa64isar1; 960 uint64_t id_aa64pfr0; 961 uint64_t id_aa64pfr1; 962 uint64_t id_aa64mmfr0; 963 uint64_t id_aa64mmfr1; 964 uint64_t id_aa64mmfr2; 965 uint64_t id_aa64dfr0; 966 uint64_t id_aa64dfr1; 967 uint64_t id_aa64zfr0; 968 } isar; 969 uint64_t midr; 970 uint32_t revidr; 971 uint32_t reset_fpsid; 972 uint64_t ctr; 973 uint32_t reset_sctlr; 974 uint64_t pmceid0; 975 uint64_t pmceid1; 976 uint32_t id_afr0; 977 uint64_t id_aa64afr0; 978 uint64_t id_aa64afr1; 979 uint64_t clidr; 980 uint64_t mp_affinity; /* MP ID without feature bits */ 981 /* The elements of this array are the CCSIDR values for each cache, 982 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 983 */ 984 uint64_t ccsidr[16]; 985 uint64_t reset_cbar; 986 uint32_t reset_auxcr; 987 bool reset_hivecs; 988 989 /* 990 * Intermediate values used during property parsing. 991 * Once finalized, the values should be read from ID_AA64*. 992 */ 993 bool prop_pauth; 994 bool prop_pauth_impdef; 995 bool prop_lpa2; 996 997 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 998 uint32_t dcz_blocksize; 999 uint64_t rvbar_prop; /* Property/input signals. */ 1000 1001 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 1002 int gic_num_lrs; /* number of list registers */ 1003 int gic_vpribits; /* number of virtual priority bits */ 1004 int gic_vprebits; /* number of virtual preemption bits */ 1005 1006 /* Whether the cfgend input is high (i.e. this CPU should reset into 1007 * big-endian mode). This setting isn't used directly: instead it modifies 1008 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 1009 * architecture version. 1010 */ 1011 bool cfgend; 1012 1013 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 1014 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 1015 1016 int32_t node_id; /* NUMA node this CPU belongs to */ 1017 1018 /* Used to synchronize KVM and QEMU in-kernel device levels */ 1019 uint8_t device_irq_level; 1020 1021 /* Used to set the maximum vector length the cpu will support. */ 1022 uint32_t sve_max_vq; 1023 1024 #ifdef CONFIG_USER_ONLY 1025 /* Used to set the default vector length at process start. */ 1026 uint32_t sve_default_vq; 1027 #endif 1028 1029 /* 1030 * In sve_vq_map each set bit is a supported vector length of 1031 * (bit-number + 1) * 16 bytes, i.e. each bit number + 1 is the vector 1032 * length in quadwords. 1033 * 1034 * While processing properties during initialization, corresponding 1035 * sve_vq_init bits are set for bits in sve_vq_map that have been 1036 * set by properties. 1037 * 1038 * Bits set in sve_vq_supported represent valid vector lengths for 1039 * the CPU type. 1040 */ 1041 DECLARE_BITMAP(sve_vq_map, ARM_MAX_VQ); 1042 DECLARE_BITMAP(sve_vq_init, ARM_MAX_VQ); 1043 DECLARE_BITMAP(sve_vq_supported, ARM_MAX_VQ); 1044 1045 /* Generic timer counter frequency, in Hz */ 1046 uint64_t gt_cntfrq_hz; 1047 }; 1048 1049 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); 1050 1051 void arm_cpu_post_init(Object *obj); 1052 1053 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); 1054 1055 #ifndef CONFIG_USER_ONLY 1056 extern const VMStateDescription vmstate_arm_cpu; 1057 1058 void arm_cpu_do_interrupt(CPUState *cpu); 1059 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 1060 #endif /* !CONFIG_USER_ONLY */ 1061 1062 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 1063 MemTxAttrs *attrs); 1064 1065 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1066 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1067 1068 /* 1069 * Helpers to dynamically generates XML descriptions of the sysregs 1070 * and SVE registers. Returns the number of registers in each set. 1071 */ 1072 int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg); 1073 int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg); 1074 1075 /* Returns the dynamically generated XML for the gdb stub. 1076 * Returns a pointer to the XML contents for the specified XML file or NULL 1077 * if the XML name doesn't match the predefined one. 1078 */ 1079 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname); 1080 1081 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 1082 int cpuid, void *opaque); 1083 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 1084 int cpuid, void *opaque); 1085 1086 #ifdef TARGET_AARCH64 1087 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1088 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1089 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 1090 void aarch64_sve_change_el(CPUARMState *env, int old_el, 1091 int new_el, bool el0_a64); 1092 void aarch64_add_sve_properties(Object *obj); 1093 void aarch64_add_pauth_properties(Object *obj); 1094 1095 /* 1096 * SVE registers are encoded in KVM's memory in an endianness-invariant format. 1097 * The byte at offset i from the start of the in-memory representation contains 1098 * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the 1099 * lowest offsets are stored in the lowest memory addresses, then that nearly 1100 * matches QEMU's representation, which is to use an array of host-endian 1101 * uint64_t's, where the lower offsets are at the lower indices. To complete 1102 * the translation we just need to byte swap the uint64_t's on big-endian hosts. 1103 */ 1104 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr) 1105 { 1106 #if HOST_BIG_ENDIAN 1107 int i; 1108 1109 for (i = 0; i < nr; ++i) { 1110 dst[i] = bswap64(src[i]); 1111 } 1112 1113 return dst; 1114 #else 1115 return src; 1116 #endif 1117 } 1118 1119 #else 1120 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } 1121 static inline void aarch64_sve_change_el(CPUARMState *env, int o, 1122 int n, bool a) 1123 { } 1124 static inline void aarch64_add_sve_properties(Object *obj) { } 1125 #endif 1126 1127 void aarch64_sync_32_to_64(CPUARMState *env); 1128 void aarch64_sync_64_to_32(CPUARMState *env); 1129 1130 int fp_exception_el(CPUARMState *env, int cur_el); 1131 int sve_exception_el(CPUARMState *env, int cur_el); 1132 uint32_t sve_zcr_len_for_el(CPUARMState *env, int el); 1133 1134 static inline bool is_a64(CPUARMState *env) 1135 { 1136 return env->aarch64; 1137 } 1138 1139 /** 1140 * pmu_op_start/finish 1141 * @env: CPUARMState 1142 * 1143 * Convert all PMU counters between their delta form (the typical mode when 1144 * they are enabled) and the guest-visible values. These two calls must 1145 * surround any action which might affect the counters. 1146 */ 1147 void pmu_op_start(CPUARMState *env); 1148 void pmu_op_finish(CPUARMState *env); 1149 1150 /* 1151 * Called when a PMU counter is due to overflow 1152 */ 1153 void arm_pmu_timer_cb(void *opaque); 1154 1155 /** 1156 * Functions to register as EL change hooks for PMU mode filtering 1157 */ 1158 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1159 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1160 1161 /* 1162 * pmu_init 1163 * @cpu: ARMCPU 1164 * 1165 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1166 * for the current configuration 1167 */ 1168 void pmu_init(ARMCPU *cpu); 1169 1170 /* SCTLR bit meanings. Several bits have been reused in newer 1171 * versions of the architecture; in that case we define constants 1172 * for both old and new bit meanings. Code which tests against those 1173 * bits should probably check or otherwise arrange that the CPU 1174 * is the architectural version it expects. 1175 */ 1176 #define SCTLR_M (1U << 0) 1177 #define SCTLR_A (1U << 1) 1178 #define SCTLR_C (1U << 2) 1179 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1180 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1181 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1182 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1183 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1184 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1185 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1186 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1187 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1188 #define SCTLR_nAA (1U << 6) /* when v8.4-LSE is implemented */ 1189 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1190 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1191 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1192 #define SCTLR_SED (1U << 8) /* v8 onward */ 1193 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1194 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1195 #define SCTLR_F (1U << 10) /* up to v6 */ 1196 #define SCTLR_SW (1U << 10) /* v7 */ 1197 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ 1198 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1199 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1200 #define SCTLR_I (1U << 12) 1201 #define SCTLR_V (1U << 13) /* AArch32 only */ 1202 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1203 #define SCTLR_RR (1U << 14) /* up to v7 */ 1204 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1205 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1206 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1207 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1208 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1209 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1210 #define SCTLR_BR (1U << 17) /* PMSA only */ 1211 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1212 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1213 #define SCTLR_WXN (1U << 19) 1214 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1215 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1216 #define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */ 1217 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1218 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1219 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1220 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1221 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1222 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1223 #define SCTLR_VE (1U << 24) /* up to v7 */ 1224 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1225 #define SCTLR_EE (1U << 25) 1226 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1227 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1228 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1229 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1230 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1231 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1232 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1233 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1234 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1235 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1236 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1237 #define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */ 1238 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1239 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1240 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1241 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1242 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1243 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1244 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1245 #define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */ 1246 #define SCTLR_TWEDEn (1ULL << 45) /* FEAT_TWED */ 1247 #define SCTLR_TWEDEL MAKE_64_MASK(46, 4) /* FEAT_TWED */ 1248 #define SCTLR_TMT0 (1ULL << 50) /* FEAT_TME */ 1249 #define SCTLR_TMT (1ULL << 51) /* FEAT_TME */ 1250 #define SCTLR_TME0 (1ULL << 52) /* FEAT_TME */ 1251 #define SCTLR_TME (1ULL << 53) /* FEAT_TME */ 1252 #define SCTLR_EnASR (1ULL << 54) /* FEAT_LS64_V */ 1253 #define SCTLR_EnAS0 (1ULL << 55) /* FEAT_LS64_ACCDATA */ 1254 #define SCTLR_EnALS (1ULL << 56) /* FEAT_LS64 */ 1255 #define SCTLR_EPAN (1ULL << 57) /* FEAT_PAN3 */ 1256 #define SCTLR_EnTP2 (1ULL << 60) /* FEAT_SME */ 1257 #define SCTLR_NMI (1ULL << 61) /* FEAT_NMI */ 1258 #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */ 1259 #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */ 1260 1261 #define CPTR_TCPAC (1U << 31) 1262 #define CPTR_TTA (1U << 20) 1263 #define CPTR_TFP (1U << 10) 1264 #define CPTR_TZ (1U << 8) /* CPTR_EL2 */ 1265 #define CPTR_EZ (1U << 8) /* CPTR_EL3 */ 1266 1267 #define MDCR_EPMAD (1U << 21) 1268 #define MDCR_EDAD (1U << 20) 1269 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ 1270 #define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ 1271 #define MDCR_SDD (1U << 16) 1272 #define MDCR_SPD (3U << 14) 1273 #define MDCR_TDRA (1U << 11) 1274 #define MDCR_TDOSA (1U << 10) 1275 #define MDCR_TDA (1U << 9) 1276 #define MDCR_TDE (1U << 8) 1277 #define MDCR_HPME (1U << 7) 1278 #define MDCR_TPM (1U << 6) 1279 #define MDCR_TPMCR (1U << 5) 1280 #define MDCR_HPMN (0x1fU) 1281 1282 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 1283 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) 1284 1285 #define CPSR_M (0x1fU) 1286 #define CPSR_T (1U << 5) 1287 #define CPSR_F (1U << 6) 1288 #define CPSR_I (1U << 7) 1289 #define CPSR_A (1U << 8) 1290 #define CPSR_E (1U << 9) 1291 #define CPSR_IT_2_7 (0xfc00U) 1292 #define CPSR_GE (0xfU << 16) 1293 #define CPSR_IL (1U << 20) 1294 #define CPSR_DIT (1U << 21) 1295 #define CPSR_PAN (1U << 22) 1296 #define CPSR_SSBS (1U << 23) 1297 #define CPSR_J (1U << 24) 1298 #define CPSR_IT_0_1 (3U << 25) 1299 #define CPSR_Q (1U << 27) 1300 #define CPSR_V (1U << 28) 1301 #define CPSR_C (1U << 29) 1302 #define CPSR_Z (1U << 30) 1303 #define CPSR_N (1U << 31) 1304 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1305 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1306 1307 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1308 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1309 | CPSR_NZCV) 1310 /* Bits writable in user mode. */ 1311 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E) 1312 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1313 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1314 1315 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1316 #define XPSR_EXCP 0x1ffU 1317 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1318 #define XPSR_IT_2_7 CPSR_IT_2_7 1319 #define XPSR_GE CPSR_GE 1320 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1321 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1322 #define XPSR_IT_0_1 CPSR_IT_0_1 1323 #define XPSR_Q CPSR_Q 1324 #define XPSR_V CPSR_V 1325 #define XPSR_C CPSR_C 1326 #define XPSR_Z CPSR_Z 1327 #define XPSR_N CPSR_N 1328 #define XPSR_NZCV CPSR_NZCV 1329 #define XPSR_IT CPSR_IT 1330 1331 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 1332 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 1333 #define TTBCR_PD0 (1U << 4) 1334 #define TTBCR_PD1 (1U << 5) 1335 #define TTBCR_EPD0 (1U << 7) 1336 #define TTBCR_IRGN0 (3U << 8) 1337 #define TTBCR_ORGN0 (3U << 10) 1338 #define TTBCR_SH0 (3U << 12) 1339 #define TTBCR_T1SZ (3U << 16) 1340 #define TTBCR_A1 (1U << 22) 1341 #define TTBCR_EPD1 (1U << 23) 1342 #define TTBCR_IRGN1 (3U << 24) 1343 #define TTBCR_ORGN1 (3U << 26) 1344 #define TTBCR_SH1 (1U << 28) 1345 #define TTBCR_EAE (1U << 31) 1346 1347 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1348 * Only these are valid when in AArch64 mode; in 1349 * AArch32 mode SPSRs are basically CPSR-format. 1350 */ 1351 #define PSTATE_SP (1U) 1352 #define PSTATE_M (0xFU) 1353 #define PSTATE_nRW (1U << 4) 1354 #define PSTATE_F (1U << 6) 1355 #define PSTATE_I (1U << 7) 1356 #define PSTATE_A (1U << 8) 1357 #define PSTATE_D (1U << 9) 1358 #define PSTATE_BTYPE (3U << 10) 1359 #define PSTATE_SSBS (1U << 12) 1360 #define PSTATE_IL (1U << 20) 1361 #define PSTATE_SS (1U << 21) 1362 #define PSTATE_PAN (1U << 22) 1363 #define PSTATE_UAO (1U << 23) 1364 #define PSTATE_DIT (1U << 24) 1365 #define PSTATE_TCO (1U << 25) 1366 #define PSTATE_V (1U << 28) 1367 #define PSTATE_C (1U << 29) 1368 #define PSTATE_Z (1U << 30) 1369 #define PSTATE_N (1U << 31) 1370 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1371 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1372 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1373 /* Mode values for AArch64 */ 1374 #define PSTATE_MODE_EL3h 13 1375 #define PSTATE_MODE_EL3t 12 1376 #define PSTATE_MODE_EL2h 9 1377 #define PSTATE_MODE_EL2t 8 1378 #define PSTATE_MODE_EL1h 5 1379 #define PSTATE_MODE_EL1t 4 1380 #define PSTATE_MODE_EL0t 0 1381 1382 /* Write a new value to v7m.exception, thus transitioning into or out 1383 * of Handler mode; this may result in a change of active stack pointer. 1384 */ 1385 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1386 1387 /* Map EL and handler into a PSTATE_MODE. */ 1388 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1389 { 1390 return (el << 2) | handler; 1391 } 1392 1393 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1394 * interprocessing, so we don't attempt to sync with the cpsr state used by 1395 * the 32 bit decoder. 1396 */ 1397 static inline uint32_t pstate_read(CPUARMState *env) 1398 { 1399 int ZF; 1400 1401 ZF = (env->ZF == 0); 1402 return (env->NF & 0x80000000) | (ZF << 30) 1403 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1404 | env->pstate | env->daif | (env->btype << 10); 1405 } 1406 1407 static inline void pstate_write(CPUARMState *env, uint32_t val) 1408 { 1409 env->ZF = (~val) & PSTATE_Z; 1410 env->NF = val; 1411 env->CF = (val >> 29) & 1; 1412 env->VF = (val << 3) & 0x80000000; 1413 env->daif = val & PSTATE_DAIF; 1414 env->btype = (val >> 10) & 3; 1415 env->pstate = val & ~CACHED_PSTATE_BITS; 1416 } 1417 1418 /* Return the current CPSR value. */ 1419 uint32_t cpsr_read(CPUARMState *env); 1420 1421 typedef enum CPSRWriteType { 1422 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1423 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1424 CPSRWriteRaw = 2, 1425 /* trust values, no reg bank switch, no hflags rebuild */ 1426 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1427 } CPSRWriteType; 1428 1429 /* 1430 * Set the CPSR. Note that some bits of mask must be all-set or all-clear. 1431 * This will do an arm_rebuild_hflags() if any of the bits in @mask 1432 * correspond to TB flags bits cached in the hflags, unless @write_type 1433 * is CPSRWriteRaw. 1434 */ 1435 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1436 CPSRWriteType write_type); 1437 1438 /* Return the current xPSR value. */ 1439 static inline uint32_t xpsr_read(CPUARMState *env) 1440 { 1441 int ZF; 1442 ZF = (env->ZF == 0); 1443 return (env->NF & 0x80000000) | (ZF << 30) 1444 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1445 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1446 | ((env->condexec_bits & 0xfc) << 8) 1447 | (env->GE << 16) 1448 | env->v7m.exception; 1449 } 1450 1451 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1452 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1453 { 1454 if (mask & XPSR_NZCV) { 1455 env->ZF = (~val) & XPSR_Z; 1456 env->NF = val; 1457 env->CF = (val >> 29) & 1; 1458 env->VF = (val << 3) & 0x80000000; 1459 } 1460 if (mask & XPSR_Q) { 1461 env->QF = ((val & XPSR_Q) != 0); 1462 } 1463 if (mask & XPSR_GE) { 1464 env->GE = (val & XPSR_GE) >> 16; 1465 } 1466 #ifndef CONFIG_USER_ONLY 1467 if (mask & XPSR_T) { 1468 env->thumb = ((val & XPSR_T) != 0); 1469 } 1470 if (mask & XPSR_IT_0_1) { 1471 env->condexec_bits &= ~3; 1472 env->condexec_bits |= (val >> 25) & 3; 1473 } 1474 if (mask & XPSR_IT_2_7) { 1475 env->condexec_bits &= 3; 1476 env->condexec_bits |= (val >> 8) & 0xfc; 1477 } 1478 if (mask & XPSR_EXCP) { 1479 /* Note that this only happens on exception exit */ 1480 write_v7m_exception(env, val & XPSR_EXCP); 1481 } 1482 #endif 1483 } 1484 1485 #define HCR_VM (1ULL << 0) 1486 #define HCR_SWIO (1ULL << 1) 1487 #define HCR_PTW (1ULL << 2) 1488 #define HCR_FMO (1ULL << 3) 1489 #define HCR_IMO (1ULL << 4) 1490 #define HCR_AMO (1ULL << 5) 1491 #define HCR_VF (1ULL << 6) 1492 #define HCR_VI (1ULL << 7) 1493 #define HCR_VSE (1ULL << 8) 1494 #define HCR_FB (1ULL << 9) 1495 #define HCR_BSU_MASK (3ULL << 10) 1496 #define HCR_DC (1ULL << 12) 1497 #define HCR_TWI (1ULL << 13) 1498 #define HCR_TWE (1ULL << 14) 1499 #define HCR_TID0 (1ULL << 15) 1500 #define HCR_TID1 (1ULL << 16) 1501 #define HCR_TID2 (1ULL << 17) 1502 #define HCR_TID3 (1ULL << 18) 1503 #define HCR_TSC (1ULL << 19) 1504 #define HCR_TIDCP (1ULL << 20) 1505 #define HCR_TACR (1ULL << 21) 1506 #define HCR_TSW (1ULL << 22) 1507 #define HCR_TPCP (1ULL << 23) 1508 #define HCR_TPU (1ULL << 24) 1509 #define HCR_TTLB (1ULL << 25) 1510 #define HCR_TVM (1ULL << 26) 1511 #define HCR_TGE (1ULL << 27) 1512 #define HCR_TDZ (1ULL << 28) 1513 #define HCR_HCD (1ULL << 29) 1514 #define HCR_TRVM (1ULL << 30) 1515 #define HCR_RW (1ULL << 31) 1516 #define HCR_CD (1ULL << 32) 1517 #define HCR_ID (1ULL << 33) 1518 #define HCR_E2H (1ULL << 34) 1519 #define HCR_TLOR (1ULL << 35) 1520 #define HCR_TERR (1ULL << 36) 1521 #define HCR_TEA (1ULL << 37) 1522 #define HCR_MIOCNCE (1ULL << 38) 1523 /* RES0 bit 39 */ 1524 #define HCR_APK (1ULL << 40) 1525 #define HCR_API (1ULL << 41) 1526 #define HCR_NV (1ULL << 42) 1527 #define HCR_NV1 (1ULL << 43) 1528 #define HCR_AT (1ULL << 44) 1529 #define HCR_NV2 (1ULL << 45) 1530 #define HCR_FWB (1ULL << 46) 1531 #define HCR_FIEN (1ULL << 47) 1532 /* RES0 bit 48 */ 1533 #define HCR_TID4 (1ULL << 49) 1534 #define HCR_TICAB (1ULL << 50) 1535 #define HCR_AMVOFFEN (1ULL << 51) 1536 #define HCR_TOCU (1ULL << 52) 1537 #define HCR_ENSCXT (1ULL << 53) 1538 #define HCR_TTLBIS (1ULL << 54) 1539 #define HCR_TTLBOS (1ULL << 55) 1540 #define HCR_ATA (1ULL << 56) 1541 #define HCR_DCT (1ULL << 57) 1542 #define HCR_TID5 (1ULL << 58) 1543 #define HCR_TWEDEN (1ULL << 59) 1544 #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) 1545 1546 #define HPFAR_NS (1ULL << 63) 1547 1548 #define SCR_NS (1U << 0) 1549 #define SCR_IRQ (1U << 1) 1550 #define SCR_FIQ (1U << 2) 1551 #define SCR_EA (1U << 3) 1552 #define SCR_FW (1U << 4) 1553 #define SCR_AW (1U << 5) 1554 #define SCR_NET (1U << 6) 1555 #define SCR_SMD (1U << 7) 1556 #define SCR_HCE (1U << 8) 1557 #define SCR_SIF (1U << 9) 1558 #define SCR_RW (1U << 10) 1559 #define SCR_ST (1U << 11) 1560 #define SCR_TWI (1U << 12) 1561 #define SCR_TWE (1U << 13) 1562 #define SCR_TLOR (1U << 14) 1563 #define SCR_TERR (1U << 15) 1564 #define SCR_APK (1U << 16) 1565 #define SCR_API (1U << 17) 1566 #define SCR_EEL2 (1U << 18) 1567 #define SCR_EASE (1U << 19) 1568 #define SCR_NMEA (1U << 20) 1569 #define SCR_FIEN (1U << 21) 1570 #define SCR_ENSCXT (1U << 25) 1571 #define SCR_ATA (1U << 26) 1572 #define SCR_FGTEN (1U << 27) 1573 #define SCR_ECVEN (1U << 28) 1574 #define SCR_TWEDEN (1U << 29) 1575 #define SCR_TWEDEL MAKE_64BIT_MASK(30, 4) 1576 #define SCR_TME (1ULL << 34) 1577 #define SCR_AMVOFFEN (1ULL << 35) 1578 #define SCR_ENAS0 (1ULL << 36) 1579 #define SCR_ADEN (1ULL << 37) 1580 #define SCR_HXEN (1ULL << 38) 1581 #define SCR_TRNDR (1ULL << 40) 1582 #define SCR_ENTP2 (1ULL << 41) 1583 #define SCR_GPF (1ULL << 48) 1584 1585 #define HSTR_TTEE (1 << 16) 1586 #define HSTR_TJDBX (1 << 17) 1587 1588 /* Return the current FPSCR value. */ 1589 uint32_t vfp_get_fpscr(CPUARMState *env); 1590 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1591 1592 /* FPCR, Floating Point Control Register 1593 * FPSR, Floating Poiht Status Register 1594 * 1595 * For A64 the FPSCR is split into two logically distinct registers, 1596 * FPCR and FPSR. However since they still use non-overlapping bits 1597 * we store the underlying state in fpscr and just mask on read/write. 1598 */ 1599 #define FPSR_MASK 0xf800009f 1600 #define FPCR_MASK 0x07ff9f00 1601 1602 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1603 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1604 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1605 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1606 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1607 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1608 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1609 #define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */ 1610 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1611 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1612 #define FPCR_AHP (1 << 26) /* Alternative half-precision */ 1613 #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ 1614 #define FPCR_V (1 << 28) /* FP overflow flag */ 1615 #define FPCR_C (1 << 29) /* FP carry flag */ 1616 #define FPCR_Z (1 << 30) /* FP zero flag */ 1617 #define FPCR_N (1 << 31) /* FP negative flag */ 1618 1619 #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */ 1620 #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT) 1621 #define FPCR_LTPSIZE_LENGTH 3 1622 1623 #define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V) 1624 #define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC) 1625 1626 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1627 { 1628 return vfp_get_fpscr(env) & FPSR_MASK; 1629 } 1630 1631 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1632 { 1633 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1634 vfp_set_fpscr(env, new_fpscr); 1635 } 1636 1637 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1638 { 1639 return vfp_get_fpscr(env) & FPCR_MASK; 1640 } 1641 1642 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1643 { 1644 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1645 vfp_set_fpscr(env, new_fpscr); 1646 } 1647 1648 enum arm_cpu_mode { 1649 ARM_CPU_MODE_USR = 0x10, 1650 ARM_CPU_MODE_FIQ = 0x11, 1651 ARM_CPU_MODE_IRQ = 0x12, 1652 ARM_CPU_MODE_SVC = 0x13, 1653 ARM_CPU_MODE_MON = 0x16, 1654 ARM_CPU_MODE_ABT = 0x17, 1655 ARM_CPU_MODE_HYP = 0x1a, 1656 ARM_CPU_MODE_UND = 0x1b, 1657 ARM_CPU_MODE_SYS = 0x1f 1658 }; 1659 1660 /* VFP system registers. */ 1661 #define ARM_VFP_FPSID 0 1662 #define ARM_VFP_FPSCR 1 1663 #define ARM_VFP_MVFR2 5 1664 #define ARM_VFP_MVFR1 6 1665 #define ARM_VFP_MVFR0 7 1666 #define ARM_VFP_FPEXC 8 1667 #define ARM_VFP_FPINST 9 1668 #define ARM_VFP_FPINST2 10 1669 /* These ones are M-profile only */ 1670 #define ARM_VFP_FPSCR_NZCVQC 2 1671 #define ARM_VFP_VPR 12 1672 #define ARM_VFP_P0 13 1673 #define ARM_VFP_FPCXT_NS 14 1674 #define ARM_VFP_FPCXT_S 15 1675 1676 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */ 1677 #define QEMU_VFP_FPSCR_NZCV 0xffff 1678 1679 /* iwMMXt coprocessor control registers. */ 1680 #define ARM_IWMMXT_wCID 0 1681 #define ARM_IWMMXT_wCon 1 1682 #define ARM_IWMMXT_wCSSF 2 1683 #define ARM_IWMMXT_wCASF 3 1684 #define ARM_IWMMXT_wCGR0 8 1685 #define ARM_IWMMXT_wCGR1 9 1686 #define ARM_IWMMXT_wCGR2 10 1687 #define ARM_IWMMXT_wCGR3 11 1688 1689 /* V7M CCR bits */ 1690 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1691 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1692 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1693 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1694 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1695 FIELD(V7M_CCR, STKALIGN, 9, 1) 1696 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1697 FIELD(V7M_CCR, DC, 16, 1) 1698 FIELD(V7M_CCR, IC, 17, 1) 1699 FIELD(V7M_CCR, BP, 18, 1) 1700 FIELD(V7M_CCR, LOB, 19, 1) 1701 FIELD(V7M_CCR, TRD, 20, 1) 1702 1703 /* V7M SCR bits */ 1704 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1705 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1706 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1707 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1708 1709 /* V7M AIRCR bits */ 1710 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1711 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1712 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1713 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1714 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1715 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1716 FIELD(V7M_AIRCR, PRIS, 14, 1) 1717 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1718 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1719 1720 /* V7M CFSR bits for MMFSR */ 1721 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1722 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1723 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1724 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1725 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1726 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1727 1728 /* V7M CFSR bits for BFSR */ 1729 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1730 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1731 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1732 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1733 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1734 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1735 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1736 1737 /* V7M CFSR bits for UFSR */ 1738 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1739 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1740 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1741 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1742 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1743 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1744 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1745 1746 /* V7M CFSR bit masks covering all of the subregister bits */ 1747 FIELD(V7M_CFSR, MMFSR, 0, 8) 1748 FIELD(V7M_CFSR, BFSR, 8, 8) 1749 FIELD(V7M_CFSR, UFSR, 16, 16) 1750 1751 /* V7M HFSR bits */ 1752 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1753 FIELD(V7M_HFSR, FORCED, 30, 1) 1754 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1755 1756 /* V7M DFSR bits */ 1757 FIELD(V7M_DFSR, HALTED, 0, 1) 1758 FIELD(V7M_DFSR, BKPT, 1, 1) 1759 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1760 FIELD(V7M_DFSR, VCATCH, 3, 1) 1761 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1762 1763 /* V7M SFSR bits */ 1764 FIELD(V7M_SFSR, INVEP, 0, 1) 1765 FIELD(V7M_SFSR, INVIS, 1, 1) 1766 FIELD(V7M_SFSR, INVER, 2, 1) 1767 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1768 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1769 FIELD(V7M_SFSR, LSPERR, 5, 1) 1770 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1771 FIELD(V7M_SFSR, LSERR, 7, 1) 1772 1773 /* v7M MPU_CTRL bits */ 1774 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1775 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1776 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1777 1778 /* v7M CLIDR bits */ 1779 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1780 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1781 FIELD(V7M_CLIDR, LOC, 24, 3) 1782 FIELD(V7M_CLIDR, LOUU, 27, 3) 1783 FIELD(V7M_CLIDR, ICB, 30, 2) 1784 1785 FIELD(V7M_CSSELR, IND, 0, 1) 1786 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1787 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1788 * define a mask for this and check that it doesn't permit running off 1789 * the end of the array. 1790 */ 1791 FIELD(V7M_CSSELR, INDEX, 0, 4) 1792 1793 /* v7M FPCCR bits */ 1794 FIELD(V7M_FPCCR, LSPACT, 0, 1) 1795 FIELD(V7M_FPCCR, USER, 1, 1) 1796 FIELD(V7M_FPCCR, S, 2, 1) 1797 FIELD(V7M_FPCCR, THREAD, 3, 1) 1798 FIELD(V7M_FPCCR, HFRDY, 4, 1) 1799 FIELD(V7M_FPCCR, MMRDY, 5, 1) 1800 FIELD(V7M_FPCCR, BFRDY, 6, 1) 1801 FIELD(V7M_FPCCR, SFRDY, 7, 1) 1802 FIELD(V7M_FPCCR, MONRDY, 8, 1) 1803 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) 1804 FIELD(V7M_FPCCR, UFRDY, 10, 1) 1805 FIELD(V7M_FPCCR, RES0, 11, 15) 1806 FIELD(V7M_FPCCR, TS, 26, 1) 1807 FIELD(V7M_FPCCR, CLRONRETS, 27, 1) 1808 FIELD(V7M_FPCCR, CLRONRET, 28, 1) 1809 FIELD(V7M_FPCCR, LSPENS, 29, 1) 1810 FIELD(V7M_FPCCR, LSPEN, 30, 1) 1811 FIELD(V7M_FPCCR, ASPEN, 31, 1) 1812 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */ 1813 #define R_V7M_FPCCR_BANKED_MASK \ 1814 (R_V7M_FPCCR_LSPACT_MASK | \ 1815 R_V7M_FPCCR_USER_MASK | \ 1816 R_V7M_FPCCR_THREAD_MASK | \ 1817 R_V7M_FPCCR_MMRDY_MASK | \ 1818 R_V7M_FPCCR_SPLIMVIOL_MASK | \ 1819 R_V7M_FPCCR_UFRDY_MASK | \ 1820 R_V7M_FPCCR_ASPEN_MASK) 1821 1822 /* v7M VPR bits */ 1823 FIELD(V7M_VPR, P0, 0, 16) 1824 FIELD(V7M_VPR, MASK01, 16, 4) 1825 FIELD(V7M_VPR, MASK23, 20, 4) 1826 1827 /* 1828 * System register ID fields. 1829 */ 1830 FIELD(CLIDR_EL1, CTYPE1, 0, 3) 1831 FIELD(CLIDR_EL1, CTYPE2, 3, 3) 1832 FIELD(CLIDR_EL1, CTYPE3, 6, 3) 1833 FIELD(CLIDR_EL1, CTYPE4, 9, 3) 1834 FIELD(CLIDR_EL1, CTYPE5, 12, 3) 1835 FIELD(CLIDR_EL1, CTYPE6, 15, 3) 1836 FIELD(CLIDR_EL1, CTYPE7, 18, 3) 1837 FIELD(CLIDR_EL1, LOUIS, 21, 3) 1838 FIELD(CLIDR_EL1, LOC, 24, 3) 1839 FIELD(CLIDR_EL1, LOUU, 27, 3) 1840 FIELD(CLIDR_EL1, ICB, 30, 3) 1841 1842 /* When FEAT_CCIDX is implemented */ 1843 FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3) 1844 FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21) 1845 FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24) 1846 1847 /* When FEAT_CCIDX is not implemented */ 1848 FIELD(CCSIDR_EL1, LINESIZE, 0, 3) 1849 FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10) 1850 FIELD(CCSIDR_EL1, NUMSETS, 13, 15) 1851 1852 FIELD(CTR_EL0, IMINLINE, 0, 4) 1853 FIELD(CTR_EL0, L1IP, 14, 2) 1854 FIELD(CTR_EL0, DMINLINE, 16, 4) 1855 FIELD(CTR_EL0, ERG, 20, 4) 1856 FIELD(CTR_EL0, CWG, 24, 4) 1857 FIELD(CTR_EL0, IDC, 28, 1) 1858 FIELD(CTR_EL0, DIC, 29, 1) 1859 FIELD(CTR_EL0, TMINLINE, 32, 6) 1860 1861 FIELD(MIDR_EL1, REVISION, 0, 4) 1862 FIELD(MIDR_EL1, PARTNUM, 4, 12) 1863 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) 1864 FIELD(MIDR_EL1, VARIANT, 20, 4) 1865 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) 1866 1867 FIELD(ID_ISAR0, SWAP, 0, 4) 1868 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 1869 FIELD(ID_ISAR0, BITFIELD, 8, 4) 1870 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 1871 FIELD(ID_ISAR0, COPROC, 16, 4) 1872 FIELD(ID_ISAR0, DEBUG, 20, 4) 1873 FIELD(ID_ISAR0, DIVIDE, 24, 4) 1874 1875 FIELD(ID_ISAR1, ENDIAN, 0, 4) 1876 FIELD(ID_ISAR1, EXCEPT, 4, 4) 1877 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 1878 FIELD(ID_ISAR1, EXTEND, 12, 4) 1879 FIELD(ID_ISAR1, IFTHEN, 16, 4) 1880 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 1881 FIELD(ID_ISAR1, INTERWORK, 24, 4) 1882 FIELD(ID_ISAR1, JAZELLE, 28, 4) 1883 1884 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 1885 FIELD(ID_ISAR2, MEMHINT, 4, 4) 1886 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 1887 FIELD(ID_ISAR2, MULT, 12, 4) 1888 FIELD(ID_ISAR2, MULTS, 16, 4) 1889 FIELD(ID_ISAR2, MULTU, 20, 4) 1890 FIELD(ID_ISAR2, PSR_AR, 24, 4) 1891 FIELD(ID_ISAR2, REVERSAL, 28, 4) 1892 1893 FIELD(ID_ISAR3, SATURATE, 0, 4) 1894 FIELD(ID_ISAR3, SIMD, 4, 4) 1895 FIELD(ID_ISAR3, SVC, 8, 4) 1896 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 1897 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 1898 FIELD(ID_ISAR3, T32COPY, 20, 4) 1899 FIELD(ID_ISAR3, TRUENOP, 24, 4) 1900 FIELD(ID_ISAR3, T32EE, 28, 4) 1901 1902 FIELD(ID_ISAR4, UNPRIV, 0, 4) 1903 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 1904 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 1905 FIELD(ID_ISAR4, SMC, 12, 4) 1906 FIELD(ID_ISAR4, BARRIER, 16, 4) 1907 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 1908 FIELD(ID_ISAR4, PSR_M, 24, 4) 1909 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 1910 1911 FIELD(ID_ISAR5, SEVL, 0, 4) 1912 FIELD(ID_ISAR5, AES, 4, 4) 1913 FIELD(ID_ISAR5, SHA1, 8, 4) 1914 FIELD(ID_ISAR5, SHA2, 12, 4) 1915 FIELD(ID_ISAR5, CRC32, 16, 4) 1916 FIELD(ID_ISAR5, RDM, 24, 4) 1917 FIELD(ID_ISAR5, VCMA, 28, 4) 1918 1919 FIELD(ID_ISAR6, JSCVT, 0, 4) 1920 FIELD(ID_ISAR6, DP, 4, 4) 1921 FIELD(ID_ISAR6, FHM, 8, 4) 1922 FIELD(ID_ISAR6, SB, 12, 4) 1923 FIELD(ID_ISAR6, SPECRES, 16, 4) 1924 FIELD(ID_ISAR6, BF16, 20, 4) 1925 FIELD(ID_ISAR6, I8MM, 24, 4) 1926 1927 FIELD(ID_MMFR0, VMSA, 0, 4) 1928 FIELD(ID_MMFR0, PMSA, 4, 4) 1929 FIELD(ID_MMFR0, OUTERSHR, 8, 4) 1930 FIELD(ID_MMFR0, SHARELVL, 12, 4) 1931 FIELD(ID_MMFR0, TCM, 16, 4) 1932 FIELD(ID_MMFR0, AUXREG, 20, 4) 1933 FIELD(ID_MMFR0, FCSE, 24, 4) 1934 FIELD(ID_MMFR0, INNERSHR, 28, 4) 1935 1936 FIELD(ID_MMFR1, L1HVDVA, 0, 4) 1937 FIELD(ID_MMFR1, L1UNIVA, 4, 4) 1938 FIELD(ID_MMFR1, L1HVDSW, 8, 4) 1939 FIELD(ID_MMFR1, L1UNISW, 12, 4) 1940 FIELD(ID_MMFR1, L1HVD, 16, 4) 1941 FIELD(ID_MMFR1, L1UNI, 20, 4) 1942 FIELD(ID_MMFR1, L1TSTCLN, 24, 4) 1943 FIELD(ID_MMFR1, BPRED, 28, 4) 1944 1945 FIELD(ID_MMFR2, L1HVDFG, 0, 4) 1946 FIELD(ID_MMFR2, L1HVDBG, 4, 4) 1947 FIELD(ID_MMFR2, L1HVDRNG, 8, 4) 1948 FIELD(ID_MMFR2, HVDTLB, 12, 4) 1949 FIELD(ID_MMFR2, UNITLB, 16, 4) 1950 FIELD(ID_MMFR2, MEMBARR, 20, 4) 1951 FIELD(ID_MMFR2, WFISTALL, 24, 4) 1952 FIELD(ID_MMFR2, HWACCFLG, 28, 4) 1953 1954 FIELD(ID_MMFR3, CMAINTVA, 0, 4) 1955 FIELD(ID_MMFR3, CMAINTSW, 4, 4) 1956 FIELD(ID_MMFR3, BPMAINT, 8, 4) 1957 FIELD(ID_MMFR3, MAINTBCST, 12, 4) 1958 FIELD(ID_MMFR3, PAN, 16, 4) 1959 FIELD(ID_MMFR3, COHWALK, 20, 4) 1960 FIELD(ID_MMFR3, CMEMSZ, 24, 4) 1961 FIELD(ID_MMFR3, SUPERSEC, 28, 4) 1962 1963 FIELD(ID_MMFR4, SPECSEI, 0, 4) 1964 FIELD(ID_MMFR4, AC2, 4, 4) 1965 FIELD(ID_MMFR4, XNX, 8, 4) 1966 FIELD(ID_MMFR4, CNP, 12, 4) 1967 FIELD(ID_MMFR4, HPDS, 16, 4) 1968 FIELD(ID_MMFR4, LSM, 20, 4) 1969 FIELD(ID_MMFR4, CCIDX, 24, 4) 1970 FIELD(ID_MMFR4, EVT, 28, 4) 1971 1972 FIELD(ID_MMFR5, ETS, 0, 4) 1973 FIELD(ID_MMFR5, NTLBPA, 4, 4) 1974 1975 FIELD(ID_PFR0, STATE0, 0, 4) 1976 FIELD(ID_PFR0, STATE1, 4, 4) 1977 FIELD(ID_PFR0, STATE2, 8, 4) 1978 FIELD(ID_PFR0, STATE3, 12, 4) 1979 FIELD(ID_PFR0, CSV2, 16, 4) 1980 FIELD(ID_PFR0, AMU, 20, 4) 1981 FIELD(ID_PFR0, DIT, 24, 4) 1982 FIELD(ID_PFR0, RAS, 28, 4) 1983 1984 FIELD(ID_PFR1, PROGMOD, 0, 4) 1985 FIELD(ID_PFR1, SECURITY, 4, 4) 1986 FIELD(ID_PFR1, MPROGMOD, 8, 4) 1987 FIELD(ID_PFR1, VIRTUALIZATION, 12, 4) 1988 FIELD(ID_PFR1, GENTIMER, 16, 4) 1989 FIELD(ID_PFR1, SEC_FRAC, 20, 4) 1990 FIELD(ID_PFR1, VIRT_FRAC, 24, 4) 1991 FIELD(ID_PFR1, GIC, 28, 4) 1992 1993 FIELD(ID_PFR2, CSV3, 0, 4) 1994 FIELD(ID_PFR2, SSBS, 4, 4) 1995 FIELD(ID_PFR2, RAS_FRAC, 8, 4) 1996 1997 FIELD(ID_AA64ISAR0, AES, 4, 4) 1998 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 1999 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 2000 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 2001 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 2002 FIELD(ID_AA64ISAR0, RDM, 28, 4) 2003 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 2004 FIELD(ID_AA64ISAR0, SM3, 36, 4) 2005 FIELD(ID_AA64ISAR0, SM4, 40, 4) 2006 FIELD(ID_AA64ISAR0, DP, 44, 4) 2007 FIELD(ID_AA64ISAR0, FHM, 48, 4) 2008 FIELD(ID_AA64ISAR0, TS, 52, 4) 2009 FIELD(ID_AA64ISAR0, TLB, 56, 4) 2010 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 2011 2012 FIELD(ID_AA64ISAR1, DPB, 0, 4) 2013 FIELD(ID_AA64ISAR1, APA, 4, 4) 2014 FIELD(ID_AA64ISAR1, API, 8, 4) 2015 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 2016 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 2017 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 2018 FIELD(ID_AA64ISAR1, GPA, 24, 4) 2019 FIELD(ID_AA64ISAR1, GPI, 28, 4) 2020 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 2021 FIELD(ID_AA64ISAR1, SB, 36, 4) 2022 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 2023 FIELD(ID_AA64ISAR1, BF16, 44, 4) 2024 FIELD(ID_AA64ISAR1, DGH, 48, 4) 2025 FIELD(ID_AA64ISAR1, I8MM, 52, 4) 2026 FIELD(ID_AA64ISAR1, XS, 56, 4) 2027 FIELD(ID_AA64ISAR1, LS64, 60, 4) 2028 2029 FIELD(ID_AA64ISAR2, WFXT, 0, 4) 2030 FIELD(ID_AA64ISAR2, RPRES, 4, 4) 2031 FIELD(ID_AA64ISAR2, GPA3, 8, 4) 2032 FIELD(ID_AA64ISAR2, APA3, 12, 4) 2033 FIELD(ID_AA64ISAR2, MOPS, 16, 4) 2034 FIELD(ID_AA64ISAR2, BC, 20, 4) 2035 FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4) 2036 2037 FIELD(ID_AA64PFR0, EL0, 0, 4) 2038 FIELD(ID_AA64PFR0, EL1, 4, 4) 2039 FIELD(ID_AA64PFR0, EL2, 8, 4) 2040 FIELD(ID_AA64PFR0, EL3, 12, 4) 2041 FIELD(ID_AA64PFR0, FP, 16, 4) 2042 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 2043 FIELD(ID_AA64PFR0, GIC, 24, 4) 2044 FIELD(ID_AA64PFR0, RAS, 28, 4) 2045 FIELD(ID_AA64PFR0, SVE, 32, 4) 2046 FIELD(ID_AA64PFR0, SEL2, 36, 4) 2047 FIELD(ID_AA64PFR0, MPAM, 40, 4) 2048 FIELD(ID_AA64PFR0, AMU, 44, 4) 2049 FIELD(ID_AA64PFR0, DIT, 48, 4) 2050 FIELD(ID_AA64PFR0, CSV2, 56, 4) 2051 FIELD(ID_AA64PFR0, CSV3, 60, 4) 2052 2053 FIELD(ID_AA64PFR1, BT, 0, 4) 2054 FIELD(ID_AA64PFR1, SSBS, 4, 4) 2055 FIELD(ID_AA64PFR1, MTE, 8, 4) 2056 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 2057 FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) 2058 FIELD(ID_AA64PFR1, SME, 24, 4) 2059 FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4) 2060 FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4) 2061 FIELD(ID_AA64PFR1, NMI, 36, 4) 2062 2063 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 2064 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 2065 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 2066 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 2067 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 2068 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 2069 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 2070 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 2071 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 2072 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 2073 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 2074 FIELD(ID_AA64MMFR0, EXS, 44, 4) 2075 FIELD(ID_AA64MMFR0, FGT, 56, 4) 2076 FIELD(ID_AA64MMFR0, ECV, 60, 4) 2077 2078 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 2079 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 2080 FIELD(ID_AA64MMFR1, VH, 8, 4) 2081 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 2082 FIELD(ID_AA64MMFR1, LO, 16, 4) 2083 FIELD(ID_AA64MMFR1, PAN, 20, 4) 2084 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 2085 FIELD(ID_AA64MMFR1, XNX, 28, 4) 2086 FIELD(ID_AA64MMFR1, TWED, 32, 4) 2087 FIELD(ID_AA64MMFR1, ETS, 36, 4) 2088 FIELD(ID_AA64MMFR1, HCX, 40, 4) 2089 FIELD(ID_AA64MMFR1, AFP, 44, 4) 2090 FIELD(ID_AA64MMFR1, NTLBPA, 48, 4) 2091 FIELD(ID_AA64MMFR1, TIDCP1, 52, 4) 2092 FIELD(ID_AA64MMFR1, CMOW, 56, 4) 2093 2094 FIELD(ID_AA64MMFR2, CNP, 0, 4) 2095 FIELD(ID_AA64MMFR2, UAO, 4, 4) 2096 FIELD(ID_AA64MMFR2, LSM, 8, 4) 2097 FIELD(ID_AA64MMFR2, IESB, 12, 4) 2098 FIELD(ID_AA64MMFR2, VARANGE, 16, 4) 2099 FIELD(ID_AA64MMFR2, CCIDX, 20, 4) 2100 FIELD(ID_AA64MMFR2, NV, 24, 4) 2101 FIELD(ID_AA64MMFR2, ST, 28, 4) 2102 FIELD(ID_AA64MMFR2, AT, 32, 4) 2103 FIELD(ID_AA64MMFR2, IDS, 36, 4) 2104 FIELD(ID_AA64MMFR2, FWB, 40, 4) 2105 FIELD(ID_AA64MMFR2, TTL, 48, 4) 2106 FIELD(ID_AA64MMFR2, BBM, 52, 4) 2107 FIELD(ID_AA64MMFR2, EVT, 56, 4) 2108 FIELD(ID_AA64MMFR2, E0PD, 60, 4) 2109 2110 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) 2111 FIELD(ID_AA64DFR0, TRACEVER, 4, 4) 2112 FIELD(ID_AA64DFR0, PMUVER, 8, 4) 2113 FIELD(ID_AA64DFR0, BRPS, 12, 4) 2114 FIELD(ID_AA64DFR0, WRPS, 20, 4) 2115 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) 2116 FIELD(ID_AA64DFR0, PMSVER, 32, 4) 2117 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) 2118 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) 2119 FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4) 2120 FIELD(ID_AA64DFR0, MTPMU, 48, 4) 2121 FIELD(ID_AA64DFR0, BRBE, 52, 4) 2122 FIELD(ID_AA64DFR0, HPMN0, 60, 4) 2123 2124 FIELD(ID_AA64ZFR0, SVEVER, 0, 4) 2125 FIELD(ID_AA64ZFR0, AES, 4, 4) 2126 FIELD(ID_AA64ZFR0, BITPERM, 16, 4) 2127 FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4) 2128 FIELD(ID_AA64ZFR0, SHA3, 32, 4) 2129 FIELD(ID_AA64ZFR0, SM4, 40, 4) 2130 FIELD(ID_AA64ZFR0, I8MM, 44, 4) 2131 FIELD(ID_AA64ZFR0, F32MM, 52, 4) 2132 FIELD(ID_AA64ZFR0, F64MM, 56, 4) 2133 2134 FIELD(ID_DFR0, COPDBG, 0, 4) 2135 FIELD(ID_DFR0, COPSDBG, 4, 4) 2136 FIELD(ID_DFR0, MMAPDBG, 8, 4) 2137 FIELD(ID_DFR0, COPTRC, 12, 4) 2138 FIELD(ID_DFR0, MMAPTRC, 16, 4) 2139 FIELD(ID_DFR0, MPROFDBG, 20, 4) 2140 FIELD(ID_DFR0, PERFMON, 24, 4) 2141 FIELD(ID_DFR0, TRACEFILT, 28, 4) 2142 2143 FIELD(ID_DFR1, MTPMU, 0, 4) 2144 FIELD(ID_DFR1, HPMN0, 4, 4) 2145 2146 FIELD(DBGDIDR, SE_IMP, 12, 1) 2147 FIELD(DBGDIDR, NSUHD_IMP, 14, 1) 2148 FIELD(DBGDIDR, VERSION, 16, 4) 2149 FIELD(DBGDIDR, CTX_CMPS, 20, 4) 2150 FIELD(DBGDIDR, BRPS, 24, 4) 2151 FIELD(DBGDIDR, WRPS, 28, 4) 2152 2153 FIELD(MVFR0, SIMDREG, 0, 4) 2154 FIELD(MVFR0, FPSP, 4, 4) 2155 FIELD(MVFR0, FPDP, 8, 4) 2156 FIELD(MVFR0, FPTRAP, 12, 4) 2157 FIELD(MVFR0, FPDIVIDE, 16, 4) 2158 FIELD(MVFR0, FPSQRT, 20, 4) 2159 FIELD(MVFR0, FPSHVEC, 24, 4) 2160 FIELD(MVFR0, FPROUND, 28, 4) 2161 2162 FIELD(MVFR1, FPFTZ, 0, 4) 2163 FIELD(MVFR1, FPDNAN, 4, 4) 2164 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */ 2165 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */ 2166 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */ 2167 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */ 2168 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */ 2169 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */ 2170 FIELD(MVFR1, FPHP, 24, 4) 2171 FIELD(MVFR1, SIMDFMAC, 28, 4) 2172 2173 FIELD(MVFR2, SIMDMISC, 0, 4) 2174 FIELD(MVFR2, FPMISC, 4, 4) 2175 2176 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 2177 2178 /* If adding a feature bit which corresponds to a Linux ELF 2179 * HWCAP bit, remember to update the feature-bit-to-hwcap 2180 * mapping in linux-user/elfload.c:get_elf_hwcap(). 2181 */ 2182 enum arm_features { 2183 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 2184 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 2185 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 2186 ARM_FEATURE_V6, 2187 ARM_FEATURE_V6K, 2188 ARM_FEATURE_V7, 2189 ARM_FEATURE_THUMB2, 2190 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 2191 ARM_FEATURE_NEON, 2192 ARM_FEATURE_M, /* Microcontroller profile. */ 2193 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 2194 ARM_FEATURE_THUMB2EE, 2195 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 2196 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 2197 ARM_FEATURE_V4T, 2198 ARM_FEATURE_V5, 2199 ARM_FEATURE_STRONGARM, 2200 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 2201 ARM_FEATURE_GENERIC_TIMER, 2202 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 2203 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 2204 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 2205 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 2206 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 2207 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 2208 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 2209 ARM_FEATURE_V8, 2210 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 2211 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 2212 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 2213 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 2214 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 2215 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 2216 ARM_FEATURE_PMU, /* has PMU support */ 2217 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 2218 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 2219 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 2220 ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ 2221 }; 2222 2223 static inline int arm_feature(CPUARMState *env, int feature) 2224 { 2225 return (env->features & (1ULL << feature)) != 0; 2226 } 2227 2228 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); 2229 2230 #if !defined(CONFIG_USER_ONLY) 2231 /* Return true if exception levels below EL3 are in secure state, 2232 * or would be following an exception return to that level. 2233 * Unlike arm_is_secure() (which is always a question about the 2234 * _current_ state of the CPU) this doesn't care about the current 2235 * EL or mode. 2236 */ 2237 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2238 { 2239 if (arm_feature(env, ARM_FEATURE_EL3)) { 2240 return !(env->cp15.scr_el3 & SCR_NS); 2241 } else { 2242 /* If EL3 is not supported then the secure state is implementation 2243 * defined, in which case QEMU defaults to non-secure. 2244 */ 2245 return false; 2246 } 2247 } 2248 2249 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 2250 static inline bool arm_is_el3_or_mon(CPUARMState *env) 2251 { 2252 if (arm_feature(env, ARM_FEATURE_EL3)) { 2253 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 2254 /* CPU currently in AArch64 state and EL3 */ 2255 return true; 2256 } else if (!is_a64(env) && 2257 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 2258 /* CPU currently in AArch32 state and monitor mode */ 2259 return true; 2260 } 2261 } 2262 return false; 2263 } 2264 2265 /* Return true if the processor is in secure state */ 2266 static inline bool arm_is_secure(CPUARMState *env) 2267 { 2268 if (arm_is_el3_or_mon(env)) { 2269 return true; 2270 } 2271 return arm_is_secure_below_el3(env); 2272 } 2273 2274 /* 2275 * Return true if the current security state has AArch64 EL2 or AArch32 Hyp. 2276 * This corresponds to the pseudocode EL2Enabled() 2277 */ 2278 static inline bool arm_is_el2_enabled(CPUARMState *env) 2279 { 2280 if (arm_feature(env, ARM_FEATURE_EL2)) { 2281 if (arm_is_secure_below_el3(env)) { 2282 return (env->cp15.scr_el3 & SCR_EEL2) != 0; 2283 } 2284 return true; 2285 } 2286 return false; 2287 } 2288 2289 #else 2290 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2291 { 2292 return false; 2293 } 2294 2295 static inline bool arm_is_secure(CPUARMState *env) 2296 { 2297 return false; 2298 } 2299 2300 static inline bool arm_is_el2_enabled(CPUARMState *env) 2301 { 2302 return false; 2303 } 2304 #endif 2305 2306 /** 2307 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 2308 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 2309 * "for all purposes other than a direct read or write access of HCR_EL2." 2310 * Not included here is HCR_RW. 2311 */ 2312 uint64_t arm_hcr_el2_eff(CPUARMState *env); 2313 2314 /* Return true if the specified exception level is running in AArch64 state. */ 2315 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 2316 { 2317 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 2318 * and if we're not in EL0 then the state of EL0 isn't well defined.) 2319 */ 2320 assert(el >= 1 && el <= 3); 2321 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 2322 2323 /* The highest exception level is always at the maximum supported 2324 * register width, and then lower levels have a register width controlled 2325 * by bits in the SCR or HCR registers. 2326 */ 2327 if (el == 3) { 2328 return aa64; 2329 } 2330 2331 if (arm_feature(env, ARM_FEATURE_EL3) && 2332 ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) { 2333 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 2334 } 2335 2336 if (el == 2) { 2337 return aa64; 2338 } 2339 2340 if (arm_is_el2_enabled(env)) { 2341 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 2342 } 2343 2344 return aa64; 2345 } 2346 2347 /* Function for determing whether guest cp register reads and writes should 2348 * access the secure or non-secure bank of a cp register. When EL3 is 2349 * operating in AArch32 state, the NS-bit determines whether the secure 2350 * instance of a cp register should be used. When EL3 is AArch64 (or if 2351 * it doesn't exist at all) then there is no register banking, and all 2352 * accesses are to the non-secure version. 2353 */ 2354 static inline bool access_secure_reg(CPUARMState *env) 2355 { 2356 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 2357 !arm_el_is_aa64(env, 3) && 2358 !(env->cp15.scr_el3 & SCR_NS)); 2359 2360 return ret; 2361 } 2362 2363 /* Macros for accessing a specified CP register bank */ 2364 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 2365 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 2366 2367 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 2368 do { \ 2369 if (_secure) { \ 2370 (_env)->cp15._regname##_s = (_val); \ 2371 } else { \ 2372 (_env)->cp15._regname##_ns = (_val); \ 2373 } \ 2374 } while (0) 2375 2376 /* Macros for automatically accessing a specific CP register bank depending on 2377 * the current secure state of the system. These macros are not intended for 2378 * supporting instruction translation reads/writes as these are dependent 2379 * solely on the SCR.NS bit and not the mode. 2380 */ 2381 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 2382 A32_BANKED_REG_GET((_env), _regname, \ 2383 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 2384 2385 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 2386 A32_BANKED_REG_SET((_env), _regname, \ 2387 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 2388 (_val)) 2389 2390 void arm_cpu_list(void); 2391 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 2392 uint32_t cur_el, bool secure); 2393 2394 /* Interface between CPU and Interrupt controller. */ 2395 #ifndef CONFIG_USER_ONLY 2396 bool armv7m_nvic_can_take_pending_exception(void *opaque); 2397 #else 2398 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) 2399 { 2400 return true; 2401 } 2402 #endif 2403 /** 2404 * armv7m_nvic_set_pending: mark the specified exception as pending 2405 * @opaque: the NVIC 2406 * @irq: the exception number to mark pending 2407 * @secure: false for non-banked exceptions or for the nonsecure 2408 * version of a banked exception, true for the secure version of a banked 2409 * exception. 2410 * 2411 * Marks the specified exception as pending. Note that we will assert() 2412 * if @secure is true and @irq does not specify one of the fixed set 2413 * of architecturally banked exceptions. 2414 */ 2415 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); 2416 /** 2417 * armv7m_nvic_set_pending_derived: mark this derived exception as pending 2418 * @opaque: the NVIC 2419 * @irq: the exception number to mark pending 2420 * @secure: false for non-banked exceptions or for the nonsecure 2421 * version of a banked exception, true for the secure version of a banked 2422 * exception. 2423 * 2424 * Similar to armv7m_nvic_set_pending(), but specifically for derived 2425 * exceptions (exceptions generated in the course of trying to take 2426 * a different exception). 2427 */ 2428 void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); 2429 /** 2430 * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending 2431 * @opaque: the NVIC 2432 * @irq: the exception number to mark pending 2433 * @secure: false for non-banked exceptions or for the nonsecure 2434 * version of a banked exception, true for the secure version of a banked 2435 * exception. 2436 * 2437 * Similar to armv7m_nvic_set_pending(), but specifically for exceptions 2438 * generated in the course of lazy stacking of FP registers. 2439 */ 2440 void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure); 2441 /** 2442 * armv7m_nvic_get_pending_irq_info: return highest priority pending 2443 * exception, and whether it targets Secure state 2444 * @opaque: the NVIC 2445 * @pirq: set to pending exception number 2446 * @ptargets_secure: set to whether pending exception targets Secure 2447 * 2448 * This function writes the number of the highest priority pending 2449 * exception (the one which would be made active by 2450 * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure 2451 * to true if the current highest priority pending exception should 2452 * be taken to Secure state, false for NS. 2453 */ 2454 void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq, 2455 bool *ptargets_secure); 2456 /** 2457 * armv7m_nvic_acknowledge_irq: make highest priority pending exception active 2458 * @opaque: the NVIC 2459 * 2460 * Move the current highest priority pending exception from the pending 2461 * state to the active state, and update v7m.exception to indicate that 2462 * it is the exception currently being handled. 2463 */ 2464 void armv7m_nvic_acknowledge_irq(void *opaque); 2465 /** 2466 * armv7m_nvic_complete_irq: complete specified interrupt or exception 2467 * @opaque: the NVIC 2468 * @irq: the exception number to complete 2469 * @secure: true if this exception was secure 2470 * 2471 * Returns: -1 if the irq was not active 2472 * 1 if completing this irq brought us back to base (no active irqs) 2473 * 0 if there is still an irq active after this one was completed 2474 * (Ignoring -1, this is the same as the RETTOBASE value before completion.) 2475 */ 2476 int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); 2477 /** 2478 * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) 2479 * @opaque: the NVIC 2480 * @irq: the exception number to mark pending 2481 * @secure: false for non-banked exceptions or for the nonsecure 2482 * version of a banked exception, true for the secure version of a banked 2483 * exception. 2484 * 2485 * Return whether an exception is "ready", i.e. whether the exception is 2486 * enabled and is configured at a priority which would allow it to 2487 * interrupt the current execution priority. This controls whether the 2488 * RDY bit for it in the FPCCR is set. 2489 */ 2490 bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure); 2491 /** 2492 * armv7m_nvic_raw_execution_priority: return the raw execution priority 2493 * @opaque: the NVIC 2494 * 2495 * Returns: the raw execution priority as defined by the v8M architecture. 2496 * This is the execution priority minus the effects of AIRCR.PRIS, 2497 * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. 2498 * (v8M ARM ARM I_PKLD.) 2499 */ 2500 int armv7m_nvic_raw_execution_priority(void *opaque); 2501 /** 2502 * armv7m_nvic_neg_prio_requested: return true if the requested execution 2503 * priority is negative for the specified security state. 2504 * @opaque: the NVIC 2505 * @secure: the security state to test 2506 * This corresponds to the pseudocode IsReqExecPriNeg(). 2507 */ 2508 #ifndef CONFIG_USER_ONLY 2509 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); 2510 #else 2511 static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) 2512 { 2513 return false; 2514 } 2515 #endif 2516 2517 /* Interface for defining coprocessor registers. 2518 * Registers are defined in tables of arm_cp_reginfo structs 2519 * which are passed to define_arm_cp_regs(). 2520 */ 2521 2522 /* When looking up a coprocessor register we look for it 2523 * via an integer which encodes all of: 2524 * coprocessor number 2525 * Crn, Crm, opc1, opc2 fields 2526 * 32 or 64 bit register (ie is it accessed via MRC/MCR 2527 * or via MRRC/MCRR?) 2528 * non-secure/secure bank (AArch32 only) 2529 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 2530 * (In this case crn and opc2 should be zero.) 2531 * For AArch64, there is no 32/64 bit size distinction; 2532 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 2533 * and 4 bit CRn and CRm. The encoding patterns are chosen 2534 * to be easy to convert to and from the KVM encodings, and also 2535 * so that the hashtable can contain both AArch32 and AArch64 2536 * registers (to allow for interprocessing where we might run 2537 * 32 bit code on a 64 bit core). 2538 */ 2539 /* This bit is private to our hashtable cpreg; in KVM register 2540 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 2541 * in the upper bits of the 64 bit ID. 2542 */ 2543 #define CP_REG_AA64_SHIFT 28 2544 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 2545 2546 /* To enable banking of coprocessor registers depending on ns-bit we 2547 * add a bit to distinguish between secure and non-secure cpregs in the 2548 * hashtable. 2549 */ 2550 #define CP_REG_NS_SHIFT 29 2551 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 2552 2553 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 2554 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 2555 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 2556 2557 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 2558 (CP_REG_AA64_MASK | \ 2559 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 2560 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 2561 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 2562 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 2563 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 2564 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 2565 2566 /* Convert a full 64 bit KVM register ID to the truncated 32 bit 2567 * version used as a key for the coprocessor register hashtable 2568 */ 2569 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 2570 { 2571 uint32_t cpregid = kvmid; 2572 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 2573 cpregid |= CP_REG_AA64_MASK; 2574 } else { 2575 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 2576 cpregid |= (1 << 15); 2577 } 2578 2579 /* KVM is always non-secure so add the NS flag on AArch32 register 2580 * entries. 2581 */ 2582 cpregid |= 1 << CP_REG_NS_SHIFT; 2583 } 2584 return cpregid; 2585 } 2586 2587 /* Convert a truncated 32 bit hashtable key into the full 2588 * 64 bit KVM register ID. 2589 */ 2590 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 2591 { 2592 uint64_t kvmid; 2593 2594 if (cpregid & CP_REG_AA64_MASK) { 2595 kvmid = cpregid & ~CP_REG_AA64_MASK; 2596 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 2597 } else { 2598 kvmid = cpregid & ~(1 << 15); 2599 if (cpregid & (1 << 15)) { 2600 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 2601 } else { 2602 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 2603 } 2604 } 2605 return kvmid; 2606 } 2607 2608 /* Return the highest implemented Exception Level */ 2609 static inline int arm_highest_el(CPUARMState *env) 2610 { 2611 if (arm_feature(env, ARM_FEATURE_EL3)) { 2612 return 3; 2613 } 2614 if (arm_feature(env, ARM_FEATURE_EL2)) { 2615 return 2; 2616 } 2617 return 1; 2618 } 2619 2620 /* Return true if a v7M CPU is in Handler mode */ 2621 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2622 { 2623 return env->v7m.exception != 0; 2624 } 2625 2626 /* Return the current Exception Level (as per ARMv8; note that this differs 2627 * from the ARMv7 Privilege Level). 2628 */ 2629 static inline int arm_current_el(CPUARMState *env) 2630 { 2631 if (arm_feature(env, ARM_FEATURE_M)) { 2632 return arm_v7m_is_handler_mode(env) || 2633 !(env->v7m.control[env->v7m.secure] & 1); 2634 } 2635 2636 if (is_a64(env)) { 2637 return extract32(env->pstate, 2, 2); 2638 } 2639 2640 switch (env->uncached_cpsr & 0x1f) { 2641 case ARM_CPU_MODE_USR: 2642 return 0; 2643 case ARM_CPU_MODE_HYP: 2644 return 2; 2645 case ARM_CPU_MODE_MON: 2646 return 3; 2647 default: 2648 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2649 /* If EL3 is 32-bit then all secure privileged modes run in 2650 * EL3 2651 */ 2652 return 3; 2653 } 2654 2655 return 1; 2656 } 2657 } 2658 2659 /** 2660 * write_list_to_cpustate 2661 * @cpu: ARMCPU 2662 * 2663 * For each register listed in the ARMCPU cpreg_indexes list, write 2664 * its value from the cpreg_values list into the ARMCPUState structure. 2665 * This updates TCG's working data structures from KVM data or 2666 * from incoming migration state. 2667 * 2668 * Returns: true if all register values were updated correctly, 2669 * false if some register was unknown or could not be written. 2670 * Note that we do not stop early on failure -- we will attempt 2671 * writing all registers in the list. 2672 */ 2673 bool write_list_to_cpustate(ARMCPU *cpu); 2674 2675 /** 2676 * write_cpustate_to_list: 2677 * @cpu: ARMCPU 2678 * @kvm_sync: true if this is for syncing back to KVM 2679 * 2680 * For each register listed in the ARMCPU cpreg_indexes list, write 2681 * its value from the ARMCPUState structure into the cpreg_values list. 2682 * This is used to copy info from TCG's working data structures into 2683 * KVM or for outbound migration. 2684 * 2685 * @kvm_sync is true if we are doing this in order to sync the 2686 * register state back to KVM. In this case we will only update 2687 * values in the list if the previous list->cpustate sync actually 2688 * successfully wrote the CPU state. Otherwise we will keep the value 2689 * that is in the list. 2690 * 2691 * Returns: true if all register values were read correctly, 2692 * false if some register was unknown or could not be read. 2693 * Note that we do not stop early on failure -- we will attempt 2694 * reading all registers in the list. 2695 */ 2696 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); 2697 2698 #define ARM_CPUID_TI915T 0x54029152 2699 #define ARM_CPUID_TI925T 0x54029252 2700 2701 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU 2702 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) 2703 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2704 2705 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU 2706 2707 #define cpu_list arm_cpu_list 2708 2709 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2710 * 2711 * If EL3 is 64-bit: 2712 * + NonSecure EL1 & 0 stage 1 2713 * + NonSecure EL1 & 0 stage 2 2714 * + NonSecure EL2 2715 * + NonSecure EL2 & 0 (ARMv8.1-VHE) 2716 * + Secure EL1 & 0 2717 * + Secure EL3 2718 * If EL3 is 32-bit: 2719 * + NonSecure PL1 & 0 stage 1 2720 * + NonSecure PL1 & 0 stage 2 2721 * + NonSecure PL2 2722 * + Secure PL0 2723 * + Secure PL1 2724 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2725 * 2726 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2727 * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes, 2728 * because they may differ in access permissions even if the VA->PA map is 2729 * the same 2730 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2731 * translation, which means that we have one mmu_idx that deals with two 2732 * concatenated translation regimes [this sort of combined s1+2 TLB is 2733 * architecturally permitted] 2734 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2735 * handling via the TLB. The only way to do a stage 1 translation without 2736 * the immediate stage 2 translation is via the ATS or AT system insns, 2737 * which can be slow-pathed and always do a page table walk. 2738 * The only use of stage 2 translations is either as part of an s1+2 2739 * lookup or when loading the descriptors during a stage 1 page table walk, 2740 * and in both those cases we don't use the TLB. 2741 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2742 * translation regimes, because they map reasonably well to each other 2743 * and they can't both be active at the same time. 2744 * 5. we want to be able to use the TLB for accesses done as part of a 2745 * stage1 page table walk, rather than having to walk the stage2 page 2746 * table over and over. 2747 * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access 2748 * Never (PAN) bit within PSTATE. 2749 * 2750 * This gives us the following list of cases: 2751 * 2752 * NS EL0 EL1&0 stage 1+2 (aka NS PL0) 2753 * NS EL1 EL1&0 stage 1+2 (aka NS PL1) 2754 * NS EL1 EL1&0 stage 1+2 +PAN 2755 * NS EL0 EL2&0 2756 * NS EL2 EL2&0 2757 * NS EL2 EL2&0 +PAN 2758 * NS EL2 (aka NS PL2) 2759 * S EL0 EL1&0 (aka S PL0) 2760 * S EL1 EL1&0 (not used if EL3 is 32 bit) 2761 * S EL1 EL1&0 +PAN 2762 * S EL3 (aka S PL1) 2763 * 2764 * for a total of 11 different mmu_idx. 2765 * 2766 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2767 * as A profile. They only need to distinguish NS EL0 and NS EL1 (and 2768 * NS EL2 if we ever model a Cortex-R52). 2769 * 2770 * M profile CPUs are rather different as they do not have a true MMU. 2771 * They have the following different MMU indexes: 2772 * User 2773 * Privileged 2774 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2775 * Privileged, execution priority negative (ditto) 2776 * If the CPU supports the v8M Security Extension then there are also: 2777 * Secure User 2778 * Secure Privileged 2779 * Secure User, execution priority negative 2780 * Secure Privileged, execution priority negative 2781 * 2782 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2783 * are not quite the same -- different CPU types (most notably M profile 2784 * vs A/R profile) would like to use MMU indexes with different semantics, 2785 * but since we don't ever need to use all of those in a single CPU we 2786 * can avoid having to set NB_MMU_MODES to "total number of A profile MMU 2787 * modes + total number of M profile MMU modes". The lower bits of 2788 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2789 * the same for any particular CPU. 2790 * Variables of type ARMMUIdx are always full values, and the core 2791 * index values are in variables of type 'int'. 2792 * 2793 * Our enumeration includes at the end some entries which are not "true" 2794 * mmu_idx values in that they don't have corresponding TLBs and are only 2795 * valid for doing slow path page table walks. 2796 * 2797 * The constant names here are patterned after the general style of the names 2798 * of the AT/ATS operations. 2799 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2800 * For M profile we arrange them to have a bit for priv, a bit for negpri 2801 * and a bit for secure. 2802 */ 2803 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2804 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2805 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2806 2807 /* Meanings of the bits for A profile mmu idx values */ 2808 #define ARM_MMU_IDX_A_NS 0x8 2809 2810 /* Meanings of the bits for M profile mmu idx values */ 2811 #define ARM_MMU_IDX_M_PRIV 0x1 2812 #define ARM_MMU_IDX_M_NEGPRI 0x2 2813 #define ARM_MMU_IDX_M_S 0x4 /* Secure */ 2814 2815 #define ARM_MMU_IDX_TYPE_MASK \ 2816 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB) 2817 #define ARM_MMU_IDX_COREIDX_MASK 0xf 2818 2819 typedef enum ARMMMUIdx { 2820 /* 2821 * A-profile. 2822 */ 2823 ARMMMUIdx_SE10_0 = 0 | ARM_MMU_IDX_A, 2824 ARMMMUIdx_SE20_0 = 1 | ARM_MMU_IDX_A, 2825 ARMMMUIdx_SE10_1 = 2 | ARM_MMU_IDX_A, 2826 ARMMMUIdx_SE20_2 = 3 | ARM_MMU_IDX_A, 2827 ARMMMUIdx_SE10_1_PAN = 4 | ARM_MMU_IDX_A, 2828 ARMMMUIdx_SE20_2_PAN = 5 | ARM_MMU_IDX_A, 2829 ARMMMUIdx_SE2 = 6 | ARM_MMU_IDX_A, 2830 ARMMMUIdx_SE3 = 7 | ARM_MMU_IDX_A, 2831 2832 ARMMMUIdx_E10_0 = ARMMMUIdx_SE10_0 | ARM_MMU_IDX_A_NS, 2833 ARMMMUIdx_E20_0 = ARMMMUIdx_SE20_0 | ARM_MMU_IDX_A_NS, 2834 ARMMMUIdx_E10_1 = ARMMMUIdx_SE10_1 | ARM_MMU_IDX_A_NS, 2835 ARMMMUIdx_E20_2 = ARMMMUIdx_SE20_2 | ARM_MMU_IDX_A_NS, 2836 ARMMMUIdx_E10_1_PAN = ARMMMUIdx_SE10_1_PAN | ARM_MMU_IDX_A_NS, 2837 ARMMMUIdx_E20_2_PAN = ARMMMUIdx_SE20_2_PAN | ARM_MMU_IDX_A_NS, 2838 ARMMMUIdx_E2 = ARMMMUIdx_SE2 | ARM_MMU_IDX_A_NS, 2839 2840 /* 2841 * These are not allocated TLBs and are used only for AT system 2842 * instructions or for the first stage of an S12 page table walk. 2843 */ 2844 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, 2845 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, 2846 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB, 2847 ARMMMUIdx_Stage1_SE0 = 3 | ARM_MMU_IDX_NOTLB, 2848 ARMMMUIdx_Stage1_SE1 = 4 | ARM_MMU_IDX_NOTLB, 2849 ARMMMUIdx_Stage1_SE1_PAN = 5 | ARM_MMU_IDX_NOTLB, 2850 /* 2851 * Not allocated a TLB: used only for second stage of an S12 page 2852 * table walk, or for descriptor loads during first stage of an S1 2853 * page table walk. Note that if we ever want to have a TLB for this 2854 * then various TLB flush insns which currently are no-ops or flush 2855 * only stage 1 MMU indexes will need to change to flush stage 2. 2856 */ 2857 ARMMMUIdx_Stage2 = 6 | ARM_MMU_IDX_NOTLB, 2858 ARMMMUIdx_Stage2_S = 7 | ARM_MMU_IDX_NOTLB, 2859 2860 /* 2861 * M-profile. 2862 */ 2863 ARMMMUIdx_MUser = ARM_MMU_IDX_M, 2864 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV, 2865 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI, 2866 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI, 2867 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S, 2868 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S, 2869 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S, 2870 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S, 2871 } ARMMMUIdx; 2872 2873 /* 2874 * Bit macros for the core-mmu-index values for each index, 2875 * for use when calling tlb_flush_by_mmuidx() and friends. 2876 */ 2877 #define TO_CORE_BIT(NAME) \ 2878 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK) 2879 2880 typedef enum ARMMMUIdxBit { 2881 TO_CORE_BIT(E10_0), 2882 TO_CORE_BIT(E20_0), 2883 TO_CORE_BIT(E10_1), 2884 TO_CORE_BIT(E10_1_PAN), 2885 TO_CORE_BIT(E2), 2886 TO_CORE_BIT(E20_2), 2887 TO_CORE_BIT(E20_2_PAN), 2888 TO_CORE_BIT(SE10_0), 2889 TO_CORE_BIT(SE20_0), 2890 TO_CORE_BIT(SE10_1), 2891 TO_CORE_BIT(SE20_2), 2892 TO_CORE_BIT(SE10_1_PAN), 2893 TO_CORE_BIT(SE20_2_PAN), 2894 TO_CORE_BIT(SE2), 2895 TO_CORE_BIT(SE3), 2896 2897 TO_CORE_BIT(MUser), 2898 TO_CORE_BIT(MPriv), 2899 TO_CORE_BIT(MUserNegPri), 2900 TO_CORE_BIT(MPrivNegPri), 2901 TO_CORE_BIT(MSUser), 2902 TO_CORE_BIT(MSPriv), 2903 TO_CORE_BIT(MSUserNegPri), 2904 TO_CORE_BIT(MSPrivNegPri), 2905 } ARMMMUIdxBit; 2906 2907 #undef TO_CORE_BIT 2908 2909 #define MMU_USER_IDX 0 2910 2911 /* Indexes used when registering address spaces with cpu_address_space_init */ 2912 typedef enum ARMASIdx { 2913 ARMASIdx_NS = 0, 2914 ARMASIdx_S = 1, 2915 ARMASIdx_TagNS = 2, 2916 ARMASIdx_TagS = 3, 2917 } ARMASIdx; 2918 2919 /* Return the Exception Level targeted by debug exceptions. */ 2920 static inline int arm_debug_target_el(CPUARMState *env) 2921 { 2922 bool secure = arm_is_secure(env); 2923 bool route_to_el2 = false; 2924 2925 if (arm_is_el2_enabled(env)) { 2926 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || 2927 env->cp15.mdcr_el2 & MDCR_TDE; 2928 } 2929 2930 if (route_to_el2) { 2931 return 2; 2932 } else if (arm_feature(env, ARM_FEATURE_EL3) && 2933 !arm_el_is_aa64(env, 3) && secure) { 2934 return 3; 2935 } else { 2936 return 1; 2937 } 2938 } 2939 2940 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 2941 { 2942 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 2943 * CSSELR is RAZ/WI. 2944 */ 2945 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 2946 } 2947 2948 /* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */ 2949 static inline bool aa64_generate_debug_exceptions(CPUARMState *env) 2950 { 2951 int cur_el = arm_current_el(env); 2952 int debug_el; 2953 2954 if (cur_el == 3) { 2955 return false; 2956 } 2957 2958 /* MDCR_EL3.SDD disables debug events from Secure state */ 2959 if (arm_is_secure_below_el3(env) 2960 && extract32(env->cp15.mdcr_el3, 16, 1)) { 2961 return false; 2962 } 2963 2964 /* 2965 * Same EL to same EL debug exceptions need MDSCR_KDE enabled 2966 * while not masking the (D)ebug bit in DAIF. 2967 */ 2968 debug_el = arm_debug_target_el(env); 2969 2970 if (cur_el == debug_el) { 2971 return extract32(env->cp15.mdscr_el1, 13, 1) 2972 && !(env->daif & PSTATE_D); 2973 } 2974 2975 /* Otherwise the debug target needs to be a higher EL */ 2976 return debug_el > cur_el; 2977 } 2978 2979 static inline bool aa32_generate_debug_exceptions(CPUARMState *env) 2980 { 2981 int el = arm_current_el(env); 2982 2983 if (el == 0 && arm_el_is_aa64(env, 1)) { 2984 return aa64_generate_debug_exceptions(env); 2985 } 2986 2987 if (arm_is_secure(env)) { 2988 int spd; 2989 2990 if (el == 0 && (env->cp15.sder & 1)) { 2991 /* SDER.SUIDEN means debug exceptions from Secure EL0 2992 * are always enabled. Otherwise they are controlled by 2993 * SDCR.SPD like those from other Secure ELs. 2994 */ 2995 return true; 2996 } 2997 2998 spd = extract32(env->cp15.mdcr_el3, 14, 2); 2999 switch (spd) { 3000 case 1: 3001 /* SPD == 0b01 is reserved, but behaves as 0b00. */ 3002 case 0: 3003 /* For 0b00 we return true if external secure invasive debug 3004 * is enabled. On real hardware this is controlled by external 3005 * signals to the core. QEMU always permits debug, and behaves 3006 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. 3007 */ 3008 return true; 3009 case 2: 3010 return false; 3011 case 3: 3012 return true; 3013 } 3014 } 3015 3016 return el != 2; 3017 } 3018 3019 /* Return true if debugging exceptions are currently enabled. 3020 * This corresponds to what in ARM ARM pseudocode would be 3021 * if UsingAArch32() then 3022 * return AArch32.GenerateDebugExceptions() 3023 * else 3024 * return AArch64.GenerateDebugExceptions() 3025 * We choose to push the if() down into this function for clarity, 3026 * since the pseudocode has it at all callsites except for the one in 3027 * CheckSoftwareStep(), where it is elided because both branches would 3028 * always return the same value. 3029 */ 3030 static inline bool arm_generate_debug_exceptions(CPUARMState *env) 3031 { 3032 if (env->aarch64) { 3033 return aa64_generate_debug_exceptions(env); 3034 } else { 3035 return aa32_generate_debug_exceptions(env); 3036 } 3037 } 3038 3039 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check 3040 * implicitly means this always returns false in pre-v8 CPUs.) 3041 */ 3042 static inline bool arm_singlestep_active(CPUARMState *env) 3043 { 3044 return extract32(env->cp15.mdscr_el1, 0, 1) 3045 && arm_el_is_aa64(env, arm_debug_target_el(env)) 3046 && arm_generate_debug_exceptions(env); 3047 } 3048 3049 static inline bool arm_sctlr_b(CPUARMState *env) 3050 { 3051 return 3052 /* We need not implement SCTLR.ITD in user-mode emulation, so 3053 * let linux-user ignore the fact that it conflicts with SCTLR_B. 3054 * This lets people run BE32 binaries with "-cpu any". 3055 */ 3056 #ifndef CONFIG_USER_ONLY 3057 !arm_feature(env, ARM_FEATURE_V7) && 3058 #endif 3059 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 3060 } 3061 3062 uint64_t arm_sctlr(CPUARMState *env, int el); 3063 3064 static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, 3065 bool sctlr_b) 3066 { 3067 #ifdef CONFIG_USER_ONLY 3068 /* 3069 * In system mode, BE32 is modelled in line with the 3070 * architecture (as word-invariant big-endianness), where loads 3071 * and stores are done little endian but from addresses which 3072 * are adjusted by XORing with the appropriate constant. So the 3073 * endianness to use for the raw data access is not affected by 3074 * SCTLR.B. 3075 * In user mode, however, we model BE32 as byte-invariant 3076 * big-endianness (because user-only code cannot tell the 3077 * difference), and so we need to use a data access endianness 3078 * that depends on SCTLR.B. 3079 */ 3080 if (sctlr_b) { 3081 return true; 3082 } 3083 #endif 3084 /* In 32bit endianness is determined by looking at CPSR's E bit */ 3085 return env->uncached_cpsr & CPSR_E; 3086 } 3087 3088 static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr) 3089 { 3090 return sctlr & (el ? SCTLR_EE : SCTLR_E0E); 3091 } 3092 3093 /* Return true if the processor is in big-endian mode. */ 3094 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 3095 { 3096 if (!is_a64(env)) { 3097 return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); 3098 } else { 3099 int cur_el = arm_current_el(env); 3100 uint64_t sctlr = arm_sctlr(env, cur_el); 3101 return arm_cpu_data_is_big_endian_a64(cur_el, sctlr); 3102 } 3103 } 3104 3105 #include "exec/cpu-all.h" 3106 3107 /* 3108 * We have more than 32-bits worth of state per TB, so we split the data 3109 * between tb->flags and tb->cs_base, which is otherwise unused for ARM. 3110 * We collect these two parts in CPUARMTBFlags where they are named 3111 * flags and flags2 respectively. 3112 * 3113 * The flags that are shared between all execution modes, TBFLAG_ANY, 3114 * are stored in flags. The flags that are specific to a given mode 3115 * are stores in flags2. Since cs_base is sized on the configured 3116 * address size, flags2 always has 64-bits for A64, and a minimum of 3117 * 32-bits for A32 and M32. 3118 * 3119 * The bits for 32-bit A-profile and M-profile partially overlap: 3120 * 3121 * 31 23 11 10 0 3122 * +-------------+----------+----------------+ 3123 * | | | TBFLAG_A32 | 3124 * | TBFLAG_AM32 | +-----+----------+ 3125 * | | |TBFLAG_M32| 3126 * +-------------+----------------+----------+ 3127 * 31 23 6 5 0 3128 * 3129 * Unless otherwise noted, these bits are cached in env->hflags. 3130 */ 3131 FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1) 3132 FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1) 3133 FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1) /* Not cached. */ 3134 FIELD(TBFLAG_ANY, BE_DATA, 3, 1) 3135 FIELD(TBFLAG_ANY, MMUIDX, 4, 4) 3136 /* Target EL if we take a floating-point-disabled exception */ 3137 FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) 3138 /* For A-profile only, target EL for debug exceptions. */ 3139 FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 10, 2) 3140 /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ 3141 FIELD(TBFLAG_ANY, ALIGN_MEM, 12, 1) 3142 FIELD(TBFLAG_ANY, PSTATE__IL, 13, 1) 3143 3144 /* 3145 * Bit usage when in AArch32 state, both A- and M-profile. 3146 */ 3147 FIELD(TBFLAG_AM32, CONDEXEC, 24, 8) /* Not cached. */ 3148 FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cached. */ 3149 3150 /* 3151 * Bit usage when in AArch32 state, for A-profile only. 3152 */ 3153 FIELD(TBFLAG_A32, VECLEN, 0, 3) /* Not cached. */ 3154 FIELD(TBFLAG_A32, VECSTRIDE, 3, 2) /* Not cached. */ 3155 /* 3156 * We store the bottom two bits of the CPAR as TB flags and handle 3157 * checks on the other bits at runtime. This shares the same bits as 3158 * VECSTRIDE, which is OK as no XScale CPU has VFP. 3159 * Not cached, because VECLEN+VECSTRIDE are not cached. 3160 */ 3161 FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2) 3162 FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ 3163 FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */ 3164 FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1) 3165 /* 3166 * Indicates whether cp register reads and writes by guest code should access 3167 * the secure or nonsecure bank of banked registers; note that this is not 3168 * the same thing as the current security state of the processor! 3169 */ 3170 FIELD(TBFLAG_A32, NS, 10, 1) 3171 3172 /* 3173 * Bit usage when in AArch32 state, for M-profile only. 3174 */ 3175 /* Handler (ie not Thread) mode */ 3176 FIELD(TBFLAG_M32, HANDLER, 0, 1) 3177 /* Whether we should generate stack-limit checks */ 3178 FIELD(TBFLAG_M32, STACKCHECK, 1, 1) 3179 /* Set if FPCCR.LSPACT is set */ 3180 FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */ 3181 /* Set if we must create a new FP context */ 3182 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */ 3183 /* Set if FPCCR.S does not match current security state */ 3184 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */ 3185 /* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */ 3186 FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */ 3187 3188 /* 3189 * Bit usage when in AArch64 state 3190 */ 3191 FIELD(TBFLAG_A64, TBII, 0, 2) 3192 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3193 FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) 3194 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3195 FIELD(TBFLAG_A64, BT, 9, 1) 3196 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ 3197 FIELD(TBFLAG_A64, TBID, 12, 2) 3198 FIELD(TBFLAG_A64, UNPRIV, 14, 1) 3199 FIELD(TBFLAG_A64, ATA, 15, 1) 3200 FIELD(TBFLAG_A64, TCMA, 16, 2) 3201 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) 3202 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) 3203 3204 /* 3205 * Helpers for using the above. 3206 */ 3207 #define DP_TBFLAG_ANY(DST, WHICH, VAL) \ 3208 (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL)) 3209 #define DP_TBFLAG_A64(DST, WHICH, VAL) \ 3210 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A64, WHICH, VAL)) 3211 #define DP_TBFLAG_A32(DST, WHICH, VAL) \ 3212 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL)) 3213 #define DP_TBFLAG_M32(DST, WHICH, VAL) \ 3214 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL)) 3215 #define DP_TBFLAG_AM32(DST, WHICH, VAL) \ 3216 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL)) 3217 3218 #define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH) 3219 #define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A64, WHICH) 3220 #define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH) 3221 #define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH) 3222 #define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH) 3223 3224 /** 3225 * cpu_mmu_index: 3226 * @env: The cpu environment 3227 * @ifetch: True for code access, false for data access. 3228 * 3229 * Return the core mmu index for the current translation regime. 3230 * This function is used by generic TCG code paths. 3231 */ 3232 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) 3233 { 3234 return EX_TBFLAG_ANY(env->hflags, MMUIDX); 3235 } 3236 3237 static inline bool bswap_code(bool sctlr_b) 3238 { 3239 #ifdef CONFIG_USER_ONLY 3240 /* BE8 (SCTLR.B = 0, TARGET_BIG_ENDIAN = 1) is mixed endian. 3241 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_BIG_ENDIAN=0 3242 * would also end up as a mixed-endian mode with BE code, LE data. 3243 */ 3244 return 3245 #if TARGET_BIG_ENDIAN 3246 1 ^ 3247 #endif 3248 sctlr_b; 3249 #else 3250 /* All code access in ARM is little endian, and there are no loaders 3251 * doing swaps that need to be reversed 3252 */ 3253 return 0; 3254 #endif 3255 } 3256 3257 #ifdef CONFIG_USER_ONLY 3258 static inline bool arm_cpu_bswap_data(CPUARMState *env) 3259 { 3260 return 3261 #if TARGET_BIG_ENDIAN 3262 1 ^ 3263 #endif 3264 arm_cpu_data_is_big_endian(env); 3265 } 3266 #endif 3267 3268 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 3269 target_ulong *cs_base, uint32_t *flags); 3270 3271 enum { 3272 QEMU_PSCI_CONDUIT_DISABLED = 0, 3273 QEMU_PSCI_CONDUIT_SMC = 1, 3274 QEMU_PSCI_CONDUIT_HVC = 2, 3275 }; 3276 3277 #ifndef CONFIG_USER_ONLY 3278 /* Return the address space index to use for a memory access */ 3279 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3280 { 3281 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3282 } 3283 3284 /* Return the AddressSpace to use for a memory access 3285 * (which depends on whether the access is S or NS, and whether 3286 * the board gave us a separate AddressSpace for S accesses). 3287 */ 3288 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3289 { 3290 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3291 } 3292 #endif 3293 3294 /** 3295 * arm_register_pre_el_change_hook: 3296 * Register a hook function which will be called immediately before this 3297 * CPU changes exception level or mode. The hook function will be 3298 * passed a pointer to the ARMCPU and the opaque data pointer passed 3299 * to this function when the hook was registered. 3300 * 3301 * Note that if a pre-change hook is called, any registered post-change hooks 3302 * are guaranteed to subsequently be called. 3303 */ 3304 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3305 void *opaque); 3306 /** 3307 * arm_register_el_change_hook: 3308 * Register a hook function which will be called immediately after this 3309 * CPU changes exception level or mode. The hook function will be 3310 * passed a pointer to the ARMCPU and the opaque data pointer passed 3311 * to this function when the hook was registered. 3312 * 3313 * Note that any registered hooks registered here are guaranteed to be called 3314 * if pre-change hooks have been. 3315 */ 3316 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3317 *opaque); 3318 3319 /** 3320 * arm_rebuild_hflags: 3321 * Rebuild the cached TBFLAGS for arbitrary changed processor state. 3322 */ 3323 void arm_rebuild_hflags(CPUARMState *env); 3324 3325 /** 3326 * aa32_vfp_dreg: 3327 * Return a pointer to the Dn register within env in 32-bit mode. 3328 */ 3329 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3330 { 3331 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3332 } 3333 3334 /** 3335 * aa32_vfp_qreg: 3336 * Return a pointer to the Qn register within env in 32-bit mode. 3337 */ 3338 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3339 { 3340 return &env->vfp.zregs[regno].d[0]; 3341 } 3342 3343 /** 3344 * aa64_vfp_qreg: 3345 * Return a pointer to the Qn register within env in 64-bit mode. 3346 */ 3347 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3348 { 3349 return &env->vfp.zregs[regno].d[0]; 3350 } 3351 3352 /* Shared between translate-sve.c and sve_helper.c. */ 3353 extern const uint64_t pred_esz_masks[4]; 3354 3355 /* Helper for the macros below, validating the argument type. */ 3356 static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x) 3357 { 3358 return x; 3359 } 3360 3361 /* 3362 * Lvalue macros for ARM TLB bits that we must cache in the TCG TLB. 3363 * Using these should be a bit more self-documenting than using the 3364 * generic target bits directly. 3365 */ 3366 #define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0) 3367 #define arm_tlb_mte_tagged(x) (typecheck_memtxattrs(x)->target_tlb_bit1) 3368 3369 /* 3370 * AArch64 usage of the PAGE_TARGET_* bits for linux-user. 3371 */ 3372 #define PAGE_BTI PAGE_TARGET_1 3373 #define PAGE_MTE PAGE_TARGET_2 3374 3375 #ifdef TARGET_TAGGED_ADDRESSES 3376 /** 3377 * cpu_untagged_addr: 3378 * @cs: CPU context 3379 * @x: tagged address 3380 * 3381 * Remove any address tag from @x. This is explicitly related to the 3382 * linux syscall TIF_TAGGED_ADDR setting, not TBI in general. 3383 * 3384 * There should be a better place to put this, but we need this in 3385 * include/exec/cpu_ldst.h, and not some place linux-user specific. 3386 */ 3387 static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x) 3388 { 3389 ARMCPU *cpu = ARM_CPU(cs); 3390 if (cpu->env.tagged_addr_enable) { 3391 /* 3392 * TBI is enabled for userspace but not kernelspace addresses. 3393 * Only clear the tag if bit 55 is clear. 3394 */ 3395 x &= sextract64(x, 0, 56); 3396 } 3397 return x; 3398 } 3399 #endif 3400 3401 /* 3402 * Naming convention for isar_feature functions: 3403 * Functions which test 32-bit ID registers should have _aa32_ in 3404 * their name. Functions which test 64-bit ID registers should have 3405 * _aa64_ in their name. These must only be used in code where we 3406 * know for certain that the CPU has AArch32 or AArch64 respectively 3407 * or where the correct answer for a CPU which doesn't implement that 3408 * CPU state is "false" (eg when generating A32 or A64 code, if adding 3409 * system registers that are specific to that CPU state, for "should 3410 * we let this system register bit be set" tests where the 32-bit 3411 * flavour of the register doesn't have the bit, and so on). 3412 * Functions which simply ask "does this feature exist at all" have 3413 * _any_ in their name, and always return the logical OR of the _aa64_ 3414 * and the _aa32_ function. 3415 */ 3416 3417 /* 3418 * 32-bit feature tests via id registers. 3419 */ 3420 static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id) 3421 { 3422 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; 3423 } 3424 3425 static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id) 3426 { 3427 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; 3428 } 3429 3430 static inline bool isar_feature_aa32_lob(const ARMISARegisters *id) 3431 { 3432 /* (M-profile) low-overhead loops and branch future */ 3433 return FIELD_EX32(id->id_isar0, ID_ISAR0, CMPBRANCH) >= 3; 3434 } 3435 3436 static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id) 3437 { 3438 return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0; 3439 } 3440 3441 static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) 3442 { 3443 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0; 3444 } 3445 3446 static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id) 3447 { 3448 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1; 3449 } 3450 3451 static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id) 3452 { 3453 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0; 3454 } 3455 3456 static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id) 3457 { 3458 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0; 3459 } 3460 3461 static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id) 3462 { 3463 return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0; 3464 } 3465 3466 static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id) 3467 { 3468 return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0; 3469 } 3470 3471 static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id) 3472 { 3473 return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0; 3474 } 3475 3476 static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id) 3477 { 3478 return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0; 3479 } 3480 3481 static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) 3482 { 3483 return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0; 3484 } 3485 3486 static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id) 3487 { 3488 return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0; 3489 } 3490 3491 static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) 3492 { 3493 return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0; 3494 } 3495 3496 static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id) 3497 { 3498 return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0; 3499 } 3500 3501 static inline bool isar_feature_aa32_bf16(const ARMISARegisters *id) 3502 { 3503 return FIELD_EX32(id->id_isar6, ID_ISAR6, BF16) != 0; 3504 } 3505 3506 static inline bool isar_feature_aa32_i8mm(const ARMISARegisters *id) 3507 { 3508 return FIELD_EX32(id->id_isar6, ID_ISAR6, I8MM) != 0; 3509 } 3510 3511 static inline bool isar_feature_aa32_ras(const ARMISARegisters *id) 3512 { 3513 return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) != 0; 3514 } 3515 3516 static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id) 3517 { 3518 return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0; 3519 } 3520 3521 static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id) 3522 { 3523 /* 3524 * Return true if M-profile state handling insns 3525 * (VSCCLRM, CLRM, FPCTX access insns) are implemented 3526 */ 3527 return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >= 3; 3528 } 3529 3530 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) 3531 { 3532 /* Sadly this is encoded differently for A-profile and M-profile */ 3533 if (isar_feature_aa32_mprofile(id)) { 3534 return FIELD_EX32(id->mvfr1, MVFR1, FP16) > 0; 3535 } else { 3536 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3; 3537 } 3538 } 3539 3540 static inline bool isar_feature_aa32_mve(const ARMISARegisters *id) 3541 { 3542 /* 3543 * Return true if MVE is supported (either integer or floating point). 3544 * We must check for M-profile as the MVFR1 field means something 3545 * else for A-profile. 3546 */ 3547 return isar_feature_aa32_mprofile(id) && 3548 FIELD_EX32(id->mvfr1, MVFR1, MVE) > 0; 3549 } 3550 3551 static inline bool isar_feature_aa32_mve_fp(const ARMISARegisters *id) 3552 { 3553 /* 3554 * Return true if MVE is supported (either integer or floating point). 3555 * We must check for M-profile as the MVFR1 field means something 3556 * else for A-profile. 3557 */ 3558 return isar_feature_aa32_mprofile(id) && 3559 FIELD_EX32(id->mvfr1, MVFR1, MVE) >= 2; 3560 } 3561 3562 static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id) 3563 { 3564 /* 3565 * Return true if either VFP or SIMD is implemented. 3566 * In this case, a minimum of VFP w/ D0-D15. 3567 */ 3568 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0; 3569 } 3570 3571 static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id) 3572 { 3573 /* Return true if D16-D31 are implemented */ 3574 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2; 3575 } 3576 3577 static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id) 3578 { 3579 return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0; 3580 } 3581 3582 static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id) 3583 { 3584 /* Return true if CPU supports single precision floating point, VFPv2 */ 3585 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0; 3586 } 3587 3588 static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id) 3589 { 3590 /* Return true if CPU supports single precision floating point, VFPv3 */ 3591 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2; 3592 } 3593 3594 static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id) 3595 { 3596 /* Return true if CPU supports double precision floating point, VFPv2 */ 3597 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0; 3598 } 3599 3600 static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id) 3601 { 3602 /* Return true if CPU supports double precision floating point, VFPv3 */ 3603 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2; 3604 } 3605 3606 static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id) 3607 { 3608 return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id); 3609 } 3610 3611 /* 3612 * We always set the FP and SIMD FP16 fields to indicate identical 3613 * levels of support (assuming SIMD is implemented at all), so 3614 * we only need one set of accessors. 3615 */ 3616 static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id) 3617 { 3618 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0; 3619 } 3620 3621 static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id) 3622 { 3623 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1; 3624 } 3625 3626 /* 3627 * Note that this ID register field covers both VFP and Neon FMAC, 3628 * so should usually be tested in combination with some other 3629 * check that confirms the presence of whichever of VFP or Neon is 3630 * relevant, to avoid accidentally enabling a Neon feature on 3631 * a VFP-no-Neon core or vice-versa. 3632 */ 3633 static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id) 3634 { 3635 return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0; 3636 } 3637 3638 static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id) 3639 { 3640 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1; 3641 } 3642 3643 static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id) 3644 { 3645 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2; 3646 } 3647 3648 static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id) 3649 { 3650 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3; 3651 } 3652 3653 static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id) 3654 { 3655 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4; 3656 } 3657 3658 static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id) 3659 { 3660 return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >= 4; 3661 } 3662 3663 static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) 3664 { 3665 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0; 3666 } 3667 3668 static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id) 3669 { 3670 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2; 3671 } 3672 3673 static inline bool isar_feature_aa32_pmu_8_1(const ARMISARegisters *id) 3674 { 3675 /* 0xf means "non-standard IMPDEF PMU" */ 3676 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 && 3677 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3678 } 3679 3680 static inline bool isar_feature_aa32_pmu_8_4(const ARMISARegisters *id) 3681 { 3682 /* 0xf means "non-standard IMPDEF PMU" */ 3683 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 5 && 3684 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3685 } 3686 3687 static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id) 3688 { 3689 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0; 3690 } 3691 3692 static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id) 3693 { 3694 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0; 3695 } 3696 3697 static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id) 3698 { 3699 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0; 3700 } 3701 3702 static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id) 3703 { 3704 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0; 3705 } 3706 3707 static inline bool isar_feature_aa32_dit(const ARMISARegisters *id) 3708 { 3709 return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0; 3710 } 3711 3712 static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id) 3713 { 3714 return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0; 3715 } 3716 3717 static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id) 3718 { 3719 return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 8; 3720 } 3721 3722 /* 3723 * 64-bit feature tests via id registers. 3724 */ 3725 static inline bool isar_feature_aa64_aes(const ARMISARegisters *id) 3726 { 3727 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0; 3728 } 3729 3730 static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id) 3731 { 3732 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1; 3733 } 3734 3735 static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id) 3736 { 3737 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0; 3738 } 3739 3740 static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id) 3741 { 3742 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0; 3743 } 3744 3745 static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id) 3746 { 3747 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1; 3748 } 3749 3750 static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id) 3751 { 3752 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0; 3753 } 3754 3755 static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id) 3756 { 3757 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0; 3758 } 3759 3760 static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) 3761 { 3762 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0; 3763 } 3764 3765 static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id) 3766 { 3767 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0; 3768 } 3769 3770 static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id) 3771 { 3772 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0; 3773 } 3774 3775 static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id) 3776 { 3777 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0; 3778 } 3779 3780 static inline bool isar_feature_aa64_dp(const ARMISARegisters *id) 3781 { 3782 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0; 3783 } 3784 3785 static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id) 3786 { 3787 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0; 3788 } 3789 3790 static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id) 3791 { 3792 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0; 3793 } 3794 3795 static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id) 3796 { 3797 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2; 3798 } 3799 3800 static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id) 3801 { 3802 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0; 3803 } 3804 3805 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) 3806 { 3807 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0; 3808 } 3809 3810 static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) 3811 { 3812 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0; 3813 } 3814 3815 static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) 3816 { 3817 /* 3818 * Return true if any form of pauth is enabled, as this 3819 * predicate controls migration of the 128-bit keys. 3820 */ 3821 return (id->id_aa64isar1 & 3822 (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) | 3823 FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) | 3824 FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) | 3825 FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0; 3826 } 3827 3828 static inline bool isar_feature_aa64_pauth_arch(const ARMISARegisters *id) 3829 { 3830 /* 3831 * Return true if pauth is enabled with the architected QARMA algorithm. 3832 * QEMU will always set APA+GPA to the same value. 3833 */ 3834 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0; 3835 } 3836 3837 static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id) 3838 { 3839 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2; 3840 } 3841 3842 static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id) 3843 { 3844 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) != 0; 3845 } 3846 3847 static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) 3848 { 3849 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0; 3850 } 3851 3852 static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id) 3853 { 3854 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0; 3855 } 3856 3857 static inline bool isar_feature_aa64_frint(const ARMISARegisters *id) 3858 { 3859 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0; 3860 } 3861 3862 static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id) 3863 { 3864 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) != 0; 3865 } 3866 3867 static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id) 3868 { 3869 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2; 3870 } 3871 3872 static inline bool isar_feature_aa64_bf16(const ARMISARegisters *id) 3873 { 3874 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) != 0; 3875 } 3876 3877 static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id) 3878 { 3879 /* We always set the AdvSIMD and FP fields identically. */ 3880 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf; 3881 } 3882 3883 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) 3884 { 3885 /* We always set the AdvSIMD and FP fields identically wrt FP16. */ 3886 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 3887 } 3888 3889 static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id) 3890 { 3891 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2; 3892 } 3893 3894 static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id) 3895 { 3896 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2; 3897 } 3898 3899 static inline bool isar_feature_aa64_ras(const ARMISARegisters *id) 3900 { 3901 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) != 0; 3902 } 3903 3904 static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) 3905 { 3906 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; 3907 } 3908 3909 static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id) 3910 { 3911 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) != 0; 3912 } 3913 3914 static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) 3915 { 3916 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0; 3917 } 3918 3919 static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) 3920 { 3921 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; 3922 } 3923 3924 static inline bool isar_feature_aa64_pan(const ARMISARegisters *id) 3925 { 3926 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0; 3927 } 3928 3929 static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id) 3930 { 3931 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2; 3932 } 3933 3934 static inline bool isar_feature_aa64_uao(const ARMISARegisters *id) 3935 { 3936 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0; 3937 } 3938 3939 static inline bool isar_feature_aa64_st(const ARMISARegisters *id) 3940 { 3941 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0; 3942 } 3943 3944 static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) 3945 { 3946 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; 3947 } 3948 3949 static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id) 3950 { 3951 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0; 3952 } 3953 3954 static inline bool isar_feature_aa64_mte(const ARMISARegisters *id) 3955 { 3956 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2; 3957 } 3958 3959 static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id) 3960 { 3961 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 && 3962 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 3963 } 3964 3965 static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id) 3966 { 3967 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 && 3968 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 3969 } 3970 3971 static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id) 3972 { 3973 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0; 3974 } 3975 3976 static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id) 3977 { 3978 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2; 3979 } 3980 3981 static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id) 3982 { 3983 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0; 3984 } 3985 3986 static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id) 3987 { 3988 return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1; 3989 } 3990 3991 static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *id) 3992 { 3993 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2); 3994 return t >= 3 || (t == 0 && isar_feature_aa64_tgran4_lpa2(id)); 3995 } 3996 3997 static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *id) 3998 { 3999 return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 2; 4000 } 4001 4002 static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id) 4003 { 4004 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2); 4005 return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id)); 4006 } 4007 4008 static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) 4009 { 4010 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0; 4011 } 4012 4013 static inline bool isar_feature_aa64_lva(const ARMISARegisters *id) 4014 { 4015 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) != 0; 4016 } 4017 4018 static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id) 4019 { 4020 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0; 4021 } 4022 4023 static inline bool isar_feature_aa64_dit(const ARMISARegisters *id) 4024 { 4025 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0; 4026 } 4027 4028 static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id) 4029 { 4030 int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2); 4031 if (key >= 2) { 4032 return true; /* FEAT_CSV2_2 */ 4033 } 4034 if (key == 1) { 4035 key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC); 4036 return key >= 2; /* FEAT_CSV2_1p2 */ 4037 } 4038 return false; 4039 } 4040 4041 static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id) 4042 { 4043 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0; 4044 } 4045 4046 static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id) 4047 { 4048 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >= 8; 4049 } 4050 4051 static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id) 4052 { 4053 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0; 4054 } 4055 4056 static inline bool isar_feature_aa64_sve2_aes(const ARMISARegisters *id) 4057 { 4058 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) != 0; 4059 } 4060 4061 static inline bool isar_feature_aa64_sve2_pmull128(const ARMISARegisters *id) 4062 { 4063 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) >= 2; 4064 } 4065 4066 static inline bool isar_feature_aa64_sve2_bitperm(const ARMISARegisters *id) 4067 { 4068 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BITPERM) != 0; 4069 } 4070 4071 static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id) 4072 { 4073 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BFLOAT16) != 0; 4074 } 4075 4076 static inline bool isar_feature_aa64_sve2_sha3(const ARMISARegisters *id) 4077 { 4078 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SHA3) != 0; 4079 } 4080 4081 static inline bool isar_feature_aa64_sve2_sm4(const ARMISARegisters *id) 4082 { 4083 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SM4) != 0; 4084 } 4085 4086 static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id) 4087 { 4088 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, I8MM) != 0; 4089 } 4090 4091 static inline bool isar_feature_aa64_sve_f32mm(const ARMISARegisters *id) 4092 { 4093 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F32MM) != 0; 4094 } 4095 4096 static inline bool isar_feature_aa64_sve_f64mm(const ARMISARegisters *id) 4097 { 4098 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F64MM) != 0; 4099 } 4100 4101 /* 4102 * Feature tests for "does this exist in either 32-bit or 64-bit?" 4103 */ 4104 static inline bool isar_feature_any_fp16(const ARMISARegisters *id) 4105 { 4106 return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id); 4107 } 4108 4109 static inline bool isar_feature_any_predinv(const ARMISARegisters *id) 4110 { 4111 return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id); 4112 } 4113 4114 static inline bool isar_feature_any_pmu_8_1(const ARMISARegisters *id) 4115 { 4116 return isar_feature_aa64_pmu_8_1(id) || isar_feature_aa32_pmu_8_1(id); 4117 } 4118 4119 static inline bool isar_feature_any_pmu_8_4(const ARMISARegisters *id) 4120 { 4121 return isar_feature_aa64_pmu_8_4(id) || isar_feature_aa32_pmu_8_4(id); 4122 } 4123 4124 static inline bool isar_feature_any_ccidx(const ARMISARegisters *id) 4125 { 4126 return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id); 4127 } 4128 4129 static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id) 4130 { 4131 return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id); 4132 } 4133 4134 static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id) 4135 { 4136 return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(id); 4137 } 4138 4139 static inline bool isar_feature_any_ras(const ARMISARegisters *id) 4140 { 4141 return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id); 4142 } 4143 4144 /* 4145 * Forward to the above feature tests given an ARMCPU pointer. 4146 */ 4147 #define cpu_isar_feature(name, cpu) \ 4148 ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); }) 4149 4150 #endif 4151