1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "qemu/cpu-float.h" 25 #include "hw/registerfields.h" 26 #include "cpu-qom.h" 27 #include "exec/cpu-defs.h" 28 #include "qapi/qapi-types-common.h" 29 30 /* ARM processors have a weak memory model */ 31 #define TCG_GUEST_DEFAULT_MO (0) 32 33 #ifdef TARGET_AARCH64 34 #define KVM_HAVE_MCE_INJECTION 1 35 #endif 36 37 #define EXCP_UDEF 1 /* undefined instruction */ 38 #define EXCP_SWI 2 /* software interrupt */ 39 #define EXCP_PREFETCH_ABORT 3 40 #define EXCP_DATA_ABORT 4 41 #define EXCP_IRQ 5 42 #define EXCP_FIQ 6 43 #define EXCP_BKPT 7 44 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 45 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 46 #define EXCP_HVC 11 /* HyperVisor Call */ 47 #define EXCP_HYP_TRAP 12 48 #define EXCP_SMC 13 /* Secure Monitor Call */ 49 #define EXCP_VIRQ 14 50 #define EXCP_VFIQ 15 51 #define EXCP_SEMIHOST 16 /* semihosting call */ 52 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 53 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 54 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 55 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ 56 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ 57 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ 58 #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ 59 #define EXCP_VSERR 24 60 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 61 62 #define ARMV7M_EXCP_RESET 1 63 #define ARMV7M_EXCP_NMI 2 64 #define ARMV7M_EXCP_HARD 3 65 #define ARMV7M_EXCP_MEM 4 66 #define ARMV7M_EXCP_BUS 5 67 #define ARMV7M_EXCP_USAGE 6 68 #define ARMV7M_EXCP_SECURE 7 69 #define ARMV7M_EXCP_SVC 11 70 #define ARMV7M_EXCP_DEBUG 12 71 #define ARMV7M_EXCP_PENDSV 14 72 #define ARMV7M_EXCP_SYSTICK 15 73 74 /* For M profile, some registers are banked secure vs non-secure; 75 * these are represented as a 2-element array where the first element 76 * is the non-secure copy and the second is the secure copy. 77 * When the CPU does not have implement the security extension then 78 * only the first element is used. 79 * This means that the copy for the current security state can be 80 * accessed via env->registerfield[env->v7m.secure] (whether the security 81 * extension is implemented or not). 82 */ 83 enum { 84 M_REG_NS = 0, 85 M_REG_S = 1, 86 M_REG_NUM_BANKS = 2, 87 }; 88 89 /* ARM-specific interrupt pending bits. */ 90 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 91 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 92 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 93 #define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0 94 95 /* The usual mapping for an AArch64 system register to its AArch32 96 * counterpart is for the 32 bit world to have access to the lower 97 * half only (with writes leaving the upper half untouched). It's 98 * therefore useful to be able to pass TCG the offset of the least 99 * significant half of a uint64_t struct member. 100 */ 101 #if HOST_BIG_ENDIAN 102 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 103 #define offsetofhigh32(S, M) offsetof(S, M) 104 #else 105 #define offsetoflow32(S, M) offsetof(S, M) 106 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 107 #endif 108 109 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 110 #define ARM_CPU_IRQ 0 111 #define ARM_CPU_FIQ 1 112 #define ARM_CPU_VIRQ 2 113 #define ARM_CPU_VFIQ 3 114 115 /* ARM-specific extra insn start words: 116 * 1: Conditional execution bits 117 * 2: Partial exception syndrome for data aborts 118 */ 119 #define TARGET_INSN_START_EXTRA_WORDS 2 120 121 /* The 2nd extra word holding syndrome info for data aborts does not use 122 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 123 * help the sleb128 encoder do a better job. 124 * When restoring the CPU state, we shift it back up. 125 */ 126 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 127 #define ARM_INSN_START_WORD2_SHIFT 14 128 129 /* We currently assume float and double are IEEE single and double 130 precision respectively. 131 Doing runtime conversions is tricky because VFP registers may contain 132 integer values (eg. as the result of a FTOSI instruction). 133 s<2n> maps to the least significant half of d<n> 134 s<2n+1> maps to the most significant half of d<n> 135 */ 136 137 /** 138 * DynamicGDBXMLInfo: 139 * @desc: Contains the XML descriptions. 140 * @num: Number of the registers in this XML seen by GDB. 141 * @data: A union with data specific to the set of registers 142 * @cpregs_keys: Array that contains the corresponding Key of 143 * a given cpreg with the same order of the cpreg 144 * in the XML description. 145 */ 146 typedef struct DynamicGDBXMLInfo { 147 char *desc; 148 int num; 149 union { 150 struct { 151 uint32_t *keys; 152 } cpregs; 153 } data; 154 } DynamicGDBXMLInfo; 155 156 /* CPU state for each instance of a generic timer (in cp15 c14) */ 157 typedef struct ARMGenericTimer { 158 uint64_t cval; /* Timer CompareValue register */ 159 uint64_t ctl; /* Timer Control register */ 160 } ARMGenericTimer; 161 162 #define GTIMER_PHYS 0 163 #define GTIMER_VIRT 1 164 #define GTIMER_HYP 2 165 #define GTIMER_SEC 3 166 #define GTIMER_HYPVIRT 4 167 #define NUM_GTIMERS 5 168 169 #define VTCR_NSW (1u << 29) 170 #define VTCR_NSA (1u << 30) 171 #define VSTCR_SW VTCR_NSW 172 #define VSTCR_SA VTCR_NSA 173 174 /* Define a maximum sized vector register. 175 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 176 * For 64-bit, this is a 2048-bit SVE register. 177 * 178 * Note that the mapping between S, D, and Q views of the register bank 179 * differs between AArch64 and AArch32. 180 * In AArch32: 181 * Qn = regs[n].d[1]:regs[n].d[0] 182 * Dn = regs[n / 2].d[n & 1] 183 * Sn = regs[n / 4].d[n % 4 / 2], 184 * bits 31..0 for even n, and bits 63..32 for odd n 185 * (and regs[16] to regs[31] are inaccessible) 186 * In AArch64: 187 * Zn = regs[n].d[*] 188 * Qn = regs[n].d[1]:regs[n].d[0] 189 * Dn = regs[n].d[0] 190 * Sn = regs[n].d[0] bits 31..0 191 * Hn = regs[n].d[0] bits 15..0 192 * 193 * This corresponds to the architecturally defined mapping between 194 * the two execution states, and means we do not need to explicitly 195 * map these registers when changing states. 196 * 197 * Align the data for use with TCG host vector operations. 198 */ 199 200 #ifdef TARGET_AARCH64 201 # define ARM_MAX_VQ 16 202 #else 203 # define ARM_MAX_VQ 1 204 #endif 205 206 typedef struct ARMVectorReg { 207 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 208 } ARMVectorReg; 209 210 #ifdef TARGET_AARCH64 211 /* In AArch32 mode, predicate registers do not exist at all. */ 212 typedef struct ARMPredicateReg { 213 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); 214 } ARMPredicateReg; 215 216 /* In AArch32 mode, PAC keys do not exist at all. */ 217 typedef struct ARMPACKey { 218 uint64_t lo, hi; 219 } ARMPACKey; 220 #endif 221 222 /* See the commentary above the TBFLAG field definitions. */ 223 typedef struct CPUARMTBFlags { 224 uint32_t flags; 225 target_ulong flags2; 226 } CPUARMTBFlags; 227 228 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; 229 230 typedef struct NVICState NVICState; 231 232 typedef struct CPUArchState { 233 /* Regs for current mode. */ 234 uint32_t regs[16]; 235 236 /* 32/64 switch only happens when taking and returning from 237 * exceptions so the overlap semantics are taken care of then 238 * instead of having a complicated union. 239 */ 240 /* Regs for A64 mode. */ 241 uint64_t xregs[32]; 242 uint64_t pc; 243 /* PSTATE isn't an architectural register for ARMv8. However, it is 244 * convenient for us to assemble the underlying state into a 32 bit format 245 * identical to the architectural format used for the SPSR. (This is also 246 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 247 * 'pstate' register are.) Of the PSTATE bits: 248 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 249 * semantics as for AArch32, as described in the comments on each field) 250 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 251 * DAIF (exception masks) are kept in env->daif 252 * BTYPE is kept in env->btype 253 * SM and ZA are kept in env->svcr 254 * all other bits are stored in their correct places in env->pstate 255 */ 256 uint32_t pstate; 257 bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nRW */ 258 bool thumb; /* True if CPU is in thumb mode; cpsr[5] */ 259 260 /* Cached TBFLAGS state. See below for which bits are included. */ 261 CPUARMTBFlags hflags; 262 263 /* Frequently accessed CPSR bits are stored separately for efficiency. 264 This contains all the other bits. Use cpsr_{read,write} to access 265 the whole CPSR. */ 266 uint32_t uncached_cpsr; 267 uint32_t spsr; 268 269 /* Banked registers. */ 270 uint64_t banked_spsr[8]; 271 uint32_t banked_r13[8]; 272 uint32_t banked_r14[8]; 273 274 /* These hold r8-r12. */ 275 uint32_t usr_regs[5]; 276 uint32_t fiq_regs[5]; 277 278 /* cpsr flag cache for faster execution */ 279 uint32_t CF; /* 0 or 1 */ 280 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 281 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 282 uint32_t ZF; /* Z set if zero. */ 283 uint32_t QF; /* 0 or 1 */ 284 uint32_t GE; /* cpsr[19:16] */ 285 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 286 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 287 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 288 uint64_t svcr; /* PSTATE.{SM,ZA} in the bits they are in SVCR */ 289 290 uint64_t elr_el[4]; /* AArch64 exception link regs */ 291 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 292 293 /* System control coprocessor (cp15) */ 294 struct { 295 uint32_t c0_cpuid; 296 union { /* Cache size selection */ 297 struct { 298 uint64_t _unused_csselr0; 299 uint64_t csselr_ns; 300 uint64_t _unused_csselr1; 301 uint64_t csselr_s; 302 }; 303 uint64_t csselr_el[4]; 304 }; 305 union { /* System control register. */ 306 struct { 307 uint64_t _unused_sctlr; 308 uint64_t sctlr_ns; 309 uint64_t hsctlr; 310 uint64_t sctlr_s; 311 }; 312 uint64_t sctlr_el[4]; 313 }; 314 uint64_t vsctlr; /* Virtualization System control register. */ 315 uint64_t cpacr_el1; /* Architectural feature access control register */ 316 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 317 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 318 uint64_t sder; /* Secure debug enable register. */ 319 uint32_t nsacr; /* Non-secure access control register. */ 320 union { /* MMU translation table base 0. */ 321 struct { 322 uint64_t _unused_ttbr0_0; 323 uint64_t ttbr0_ns; 324 uint64_t _unused_ttbr0_1; 325 uint64_t ttbr0_s; 326 }; 327 uint64_t ttbr0_el[4]; 328 }; 329 union { /* MMU translation table base 1. */ 330 struct { 331 uint64_t _unused_ttbr1_0; 332 uint64_t ttbr1_ns; 333 uint64_t _unused_ttbr1_1; 334 uint64_t ttbr1_s; 335 }; 336 uint64_t ttbr1_el[4]; 337 }; 338 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 339 uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ 340 /* MMU translation table base control. */ 341 uint64_t tcr_el[4]; 342 uint64_t vtcr_el2; /* Virtualization Translation Control. */ 343 uint64_t vstcr_el2; /* Secure Virtualization Translation Control. */ 344 uint32_t c2_data; /* MPU data cacheable bits. */ 345 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 346 union { /* MMU domain access control register 347 * MPU write buffer control. 348 */ 349 struct { 350 uint64_t dacr_ns; 351 uint64_t dacr_s; 352 }; 353 struct { 354 uint64_t dacr32_el2; 355 }; 356 }; 357 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 358 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 359 uint64_t hcr_el2; /* Hypervisor configuration register */ 360 uint64_t hcrx_el2; /* Extended Hypervisor configuration register */ 361 uint64_t scr_el3; /* Secure configuration register. */ 362 union { /* Fault status registers. */ 363 struct { 364 uint64_t ifsr_ns; 365 uint64_t ifsr_s; 366 }; 367 struct { 368 uint64_t ifsr32_el2; 369 }; 370 }; 371 union { 372 struct { 373 uint64_t _unused_dfsr; 374 uint64_t dfsr_ns; 375 uint64_t hsr; 376 uint64_t dfsr_s; 377 }; 378 uint64_t esr_el[4]; 379 }; 380 uint32_t c6_region[8]; /* MPU base/size registers. */ 381 union { /* Fault address registers. */ 382 struct { 383 uint64_t _unused_far0; 384 #if HOST_BIG_ENDIAN 385 uint32_t ifar_ns; 386 uint32_t dfar_ns; 387 uint32_t ifar_s; 388 uint32_t dfar_s; 389 #else 390 uint32_t dfar_ns; 391 uint32_t ifar_ns; 392 uint32_t dfar_s; 393 uint32_t ifar_s; 394 #endif 395 uint64_t _unused_far3; 396 }; 397 uint64_t far_el[4]; 398 }; 399 uint64_t hpfar_el2; 400 uint64_t hstr_el2; 401 union { /* Translation result. */ 402 struct { 403 uint64_t _unused_par_0; 404 uint64_t par_ns; 405 uint64_t _unused_par_1; 406 uint64_t par_s; 407 }; 408 uint64_t par_el[4]; 409 }; 410 411 uint32_t c9_insn; /* Cache lockdown registers. */ 412 uint32_t c9_data; 413 uint64_t c9_pmcr; /* performance monitor control register */ 414 uint64_t c9_pmcnten; /* perf monitor counter enables */ 415 uint64_t c9_pmovsr; /* perf monitor overflow status */ 416 uint64_t c9_pmuserenr; /* perf monitor user enable */ 417 uint64_t c9_pmselr; /* perf monitor counter selection register */ 418 uint64_t c9_pminten; /* perf monitor interrupt enables */ 419 union { /* Memory attribute redirection */ 420 struct { 421 #if HOST_BIG_ENDIAN 422 uint64_t _unused_mair_0; 423 uint32_t mair1_ns; 424 uint32_t mair0_ns; 425 uint64_t _unused_mair_1; 426 uint32_t mair1_s; 427 uint32_t mair0_s; 428 #else 429 uint64_t _unused_mair_0; 430 uint32_t mair0_ns; 431 uint32_t mair1_ns; 432 uint64_t _unused_mair_1; 433 uint32_t mair0_s; 434 uint32_t mair1_s; 435 #endif 436 }; 437 uint64_t mair_el[4]; 438 }; 439 union { /* vector base address register */ 440 struct { 441 uint64_t _unused_vbar; 442 uint64_t vbar_ns; 443 uint64_t hvbar; 444 uint64_t vbar_s; 445 }; 446 uint64_t vbar_el[4]; 447 }; 448 uint32_t mvbar; /* (monitor) vector base address register */ 449 uint64_t rvbar; /* rvbar sampled from rvbar property at reset */ 450 struct { /* FCSE PID. */ 451 uint32_t fcseidr_ns; 452 uint32_t fcseidr_s; 453 }; 454 union { /* Context ID. */ 455 struct { 456 uint64_t _unused_contextidr_0; 457 uint64_t contextidr_ns; 458 uint64_t _unused_contextidr_1; 459 uint64_t contextidr_s; 460 }; 461 uint64_t contextidr_el[4]; 462 }; 463 union { /* User RW Thread register. */ 464 struct { 465 uint64_t tpidrurw_ns; 466 uint64_t tpidrprw_ns; 467 uint64_t htpidr; 468 uint64_t _tpidr_el3; 469 }; 470 uint64_t tpidr_el[4]; 471 }; 472 uint64_t tpidr2_el0; 473 /* The secure banks of these registers don't map anywhere */ 474 uint64_t tpidrurw_s; 475 uint64_t tpidrprw_s; 476 uint64_t tpidruro_s; 477 478 union { /* User RO Thread register. */ 479 uint64_t tpidruro_ns; 480 uint64_t tpidrro_el[1]; 481 }; 482 uint64_t c14_cntfrq; /* Counter Frequency register */ 483 uint64_t c14_cntkctl; /* Timer Control register */ 484 uint64_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 485 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 486 ARMGenericTimer c14_timer[NUM_GTIMERS]; 487 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 488 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 489 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 490 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 491 uint32_t c15_threadid; /* TI debugger thread-ID. */ 492 uint32_t c15_config_base_address; /* SCU base address. */ 493 uint32_t c15_diagnostic; /* diagnostic register */ 494 uint32_t c15_power_diagnostic; 495 uint32_t c15_power_control; /* power control */ 496 uint64_t dbgbvr[16]; /* breakpoint value registers */ 497 uint64_t dbgbcr[16]; /* breakpoint control registers */ 498 uint64_t dbgwvr[16]; /* watchpoint value registers */ 499 uint64_t dbgwcr[16]; /* watchpoint control registers */ 500 uint64_t dbgclaim; /* DBGCLAIM bits */ 501 uint64_t mdscr_el1; 502 uint64_t oslsr_el1; /* OS Lock Status */ 503 uint64_t osdlr_el1; /* OS DoubleLock status */ 504 uint64_t mdcr_el2; 505 uint64_t mdcr_el3; 506 /* Stores the architectural value of the counter *the last time it was 507 * updated* by pmccntr_op_start. Accesses should always be surrounded 508 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 509 * architecturally-correct value is being read/set. 510 */ 511 uint64_t c15_ccnt; 512 /* Stores the delta between the architectural value and the underlying 513 * cycle count during normal operation. It is used to update c15_ccnt 514 * to be the correct architectural value before accesses. During 515 * accesses, c15_ccnt_delta contains the underlying count being used 516 * for the access, after which it reverts to the delta value in 517 * pmccntr_op_finish. 518 */ 519 uint64_t c15_ccnt_delta; 520 uint64_t c14_pmevcntr[31]; 521 uint64_t c14_pmevcntr_delta[31]; 522 uint64_t c14_pmevtyper[31]; 523 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 524 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 525 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 526 uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ 527 uint64_t gcr_el1; 528 uint64_t rgsr_el1; 529 530 /* Minimal RAS registers */ 531 uint64_t disr_el1; 532 uint64_t vdisr_el2; 533 uint64_t vsesr_el2; 534 535 /* 536 * Fine-Grained Trap registers. We store these as arrays so the 537 * access checking code doesn't have to manually select 538 * HFGRTR_EL2 vs HFDFGRTR_EL2 etc when looking up the bit to test. 539 * FEAT_FGT2 will add more elements to these arrays. 540 */ 541 uint64_t fgt_read[2]; /* HFGRTR, HDFGRTR */ 542 uint64_t fgt_write[2]; /* HFGWTR, HDFGWTR */ 543 uint64_t fgt_exec[1]; /* HFGITR */ 544 } cp15; 545 546 struct { 547 /* M profile has up to 4 stack pointers: 548 * a Main Stack Pointer and a Process Stack Pointer for each 549 * of the Secure and Non-Secure states. (If the CPU doesn't support 550 * the security extension then it has only two SPs.) 551 * In QEMU we always store the currently active SP in regs[13], 552 * and the non-active SP for the current security state in 553 * v7m.other_sp. The stack pointers for the inactive security state 554 * are stored in other_ss_msp and other_ss_psp. 555 * switch_v7m_security_state() is responsible for rearranging them 556 * when we change security state. 557 */ 558 uint32_t other_sp; 559 uint32_t other_ss_msp; 560 uint32_t other_ss_psp; 561 uint32_t vecbase[M_REG_NUM_BANKS]; 562 uint32_t basepri[M_REG_NUM_BANKS]; 563 uint32_t control[M_REG_NUM_BANKS]; 564 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 565 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 566 uint32_t hfsr; /* HardFault Status */ 567 uint32_t dfsr; /* Debug Fault Status Register */ 568 uint32_t sfsr; /* Secure Fault Status Register */ 569 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 570 uint32_t bfar; /* BusFault Address */ 571 uint32_t sfar; /* Secure Fault Address Register */ 572 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 573 int exception; 574 uint32_t primask[M_REG_NUM_BANKS]; 575 uint32_t faultmask[M_REG_NUM_BANKS]; 576 uint32_t aircr; /* only holds r/w state if security extn implemented */ 577 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 578 uint32_t csselr[M_REG_NUM_BANKS]; 579 uint32_t scr[M_REG_NUM_BANKS]; 580 uint32_t msplim[M_REG_NUM_BANKS]; 581 uint32_t psplim[M_REG_NUM_BANKS]; 582 uint32_t fpcar[M_REG_NUM_BANKS]; 583 uint32_t fpccr[M_REG_NUM_BANKS]; 584 uint32_t fpdscr[M_REG_NUM_BANKS]; 585 uint32_t cpacr[M_REG_NUM_BANKS]; 586 uint32_t nsacr; 587 uint32_t ltpsize; 588 uint32_t vpr; 589 } v7m; 590 591 /* Information associated with an exception about to be taken: 592 * code which raises an exception must set cs->exception_index and 593 * the relevant parts of this structure; the cpu_do_interrupt function 594 * will then set the guest-visible registers as part of the exception 595 * entry process. 596 */ 597 struct { 598 uint32_t syndrome; /* AArch64 format syndrome register */ 599 uint32_t fsr; /* AArch32 format fault status register info */ 600 uint64_t vaddress; /* virtual addr associated with exception, if any */ 601 uint32_t target_el; /* EL the exception should be targeted for */ 602 /* If we implement EL2 we will also need to store information 603 * about the intermediate physical address for stage 2 faults. 604 */ 605 } exception; 606 607 /* Information associated with an SError */ 608 struct { 609 uint8_t pending; 610 uint8_t has_esr; 611 uint64_t esr; 612 } serror; 613 614 uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */ 615 616 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 617 uint32_t irq_line_state; 618 619 /* Thumb-2 EE state. */ 620 uint32_t teecr; 621 uint32_t teehbr; 622 623 /* VFP coprocessor state. */ 624 struct { 625 ARMVectorReg zregs[32]; 626 627 #ifdef TARGET_AARCH64 628 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 629 #define FFR_PRED_NUM 16 630 ARMPredicateReg pregs[17]; 631 /* Scratch space for aa64 sve predicate temporary. */ 632 ARMPredicateReg preg_tmp; 633 #endif 634 635 /* We store these fpcsr fields separately for convenience. */ 636 uint32_t qc[4] QEMU_ALIGNED(16); 637 int vec_len; 638 int vec_stride; 639 640 uint32_t xregs[16]; 641 642 /* Scratch space for aa32 neon expansion. */ 643 uint32_t scratch[8]; 644 645 /* There are a number of distinct float control structures: 646 * 647 * fp_status: is the "normal" fp status. 648 * fp_status_fp16: used for half-precision calculations 649 * standard_fp_status : the ARM "Standard FPSCR Value" 650 * standard_fp_status_fp16 : used for half-precision 651 * calculations with the ARM "Standard FPSCR Value" 652 * 653 * Half-precision operations are governed by a separate 654 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 655 * status structure to control this. 656 * 657 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 658 * round-to-nearest and is used by any operations (generally 659 * Neon) which the architecture defines as controlled by the 660 * standard FPSCR value rather than the FPSCR. 661 * 662 * The "standard FPSCR but for fp16 ops" is needed because 663 * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than 664 * using a fixed value for it. 665 * 666 * To avoid having to transfer exception bits around, we simply 667 * say that the FPSCR cumulative exception flags are the logical 668 * OR of the flags in the four fp statuses. This relies on the 669 * only thing which needs to read the exception flags being 670 * an explicit FPSCR read. 671 */ 672 float_status fp_status; 673 float_status fp_status_f16; 674 float_status standard_fp_status; 675 float_status standard_fp_status_f16; 676 677 uint64_t zcr_el[4]; /* ZCR_EL[1-3] */ 678 uint64_t smcr_el[4]; /* SMCR_EL[1-3] */ 679 } vfp; 680 681 uint64_t exclusive_addr; 682 uint64_t exclusive_val; 683 /* 684 * Contains the 'val' for the second 64-bit register of LDXP, which comes 685 * from the higher address, not the high part of a complete 128-bit value. 686 * In some ways it might be more convenient to record the exclusive value 687 * as the low and high halves of a 128 bit data value, but the current 688 * semantics of these fields are baked into the migration format. 689 */ 690 uint64_t exclusive_high; 691 692 /* iwMMXt coprocessor state. */ 693 struct { 694 uint64_t regs[16]; 695 uint64_t val; 696 697 uint32_t cregs[16]; 698 } iwmmxt; 699 700 #ifdef TARGET_AARCH64 701 struct { 702 ARMPACKey apia; 703 ARMPACKey apib; 704 ARMPACKey apda; 705 ARMPACKey apdb; 706 ARMPACKey apga; 707 } keys; 708 709 uint64_t scxtnum_el[4]; 710 711 /* 712 * SME ZA storage -- 256 x 256 byte array, with bytes in host word order, 713 * as we do with vfp.zregs[]. This corresponds to the architectural ZA 714 * array, where ZA[N] is in the least-significant bytes of env->zarray[N]. 715 * When SVL is less than the architectural maximum, the accessible 716 * storage is restricted, such that if the SVL is X bytes the guest can 717 * see only the bottom X elements of zarray[], and only the least 718 * significant X bytes of each element of the array. (In other words, 719 * the observable part is always square.) 720 * 721 * The ZA storage can also be considered as a set of square tiles of 722 * elements of different sizes. The mapping from tiles to the ZA array 723 * is architecturally defined, such that for tiles of elements of esz 724 * bytes, the Nth row (or "horizontal slice") of tile T is in 725 * ZA[T + N * esz]. Note that this means that each tile is not contiguous 726 * in the ZA storage, because its rows are striped through the ZA array. 727 * 728 * Because this is so large, keep this toward the end of the reset area, 729 * to keep the offsets into the rest of the structure smaller. 730 */ 731 ARMVectorReg zarray[ARM_MAX_VQ * 16]; 732 #endif 733 734 struct CPUBreakpoint *cpu_breakpoint[16]; 735 struct CPUWatchpoint *cpu_watchpoint[16]; 736 737 /* Optional fault info across tlb lookup. */ 738 ARMMMUFaultInfo *tlb_fi; 739 740 /* Fields up to this point are cleared by a CPU reset */ 741 struct {} end_reset_fields; 742 743 /* Fields after this point are preserved across CPU reset. */ 744 745 /* Internal CPU feature flags. */ 746 uint64_t features; 747 748 /* PMSAv7 MPU */ 749 struct { 750 uint32_t *drbar; 751 uint32_t *drsr; 752 uint32_t *dracr; 753 uint32_t rnr[M_REG_NUM_BANKS]; 754 } pmsav7; 755 756 /* PMSAv8 MPU */ 757 struct { 758 /* The PMSAv8 implementation also shares some PMSAv7 config 759 * and state: 760 * pmsav7.rnr (region number register) 761 * pmsav7_dregion (number of configured regions) 762 */ 763 uint32_t *rbar[M_REG_NUM_BANKS]; 764 uint32_t *rlar[M_REG_NUM_BANKS]; 765 uint32_t *hprbar; 766 uint32_t *hprlar; 767 uint32_t mair0[M_REG_NUM_BANKS]; 768 uint32_t mair1[M_REG_NUM_BANKS]; 769 uint32_t hprselr; 770 } pmsav8; 771 772 /* v8M SAU */ 773 struct { 774 uint32_t *rbar; 775 uint32_t *rlar; 776 uint32_t rnr; 777 uint32_t ctrl; 778 } sau; 779 780 #if !defined(CONFIG_USER_ONLY) 781 NVICState *nvic; 782 const struct arm_boot_info *boot_info; 783 /* Store GICv3CPUState to access from this struct */ 784 void *gicv3state; 785 #else /* CONFIG_USER_ONLY */ 786 /* For usermode syscall translation. */ 787 bool eabi; 788 #endif /* CONFIG_USER_ONLY */ 789 790 #ifdef TARGET_TAGGED_ADDRESSES 791 /* Linux syscall tagged address support */ 792 bool tagged_addr_enable; 793 #endif 794 } CPUARMState; 795 796 static inline void set_feature(CPUARMState *env, int feature) 797 { 798 env->features |= 1ULL << feature; 799 } 800 801 static inline void unset_feature(CPUARMState *env, int feature) 802 { 803 env->features &= ~(1ULL << feature); 804 } 805 806 /** 807 * ARMELChangeHookFn: 808 * type of a function which can be registered via arm_register_el_change_hook() 809 * to get callbacks when the CPU changes its exception level or mode. 810 */ 811 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 812 typedef struct ARMELChangeHook ARMELChangeHook; 813 struct ARMELChangeHook { 814 ARMELChangeHookFn *hook; 815 void *opaque; 816 QLIST_ENTRY(ARMELChangeHook) node; 817 }; 818 819 /* These values map onto the return values for 820 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 821 typedef enum ARMPSCIState { 822 PSCI_ON = 0, 823 PSCI_OFF = 1, 824 PSCI_ON_PENDING = 2 825 } ARMPSCIState; 826 827 typedef struct ARMISARegisters ARMISARegisters; 828 829 /* 830 * In map, each set bit is a supported vector length of (bit-number + 1) * 16 831 * bytes, i.e. each bit number + 1 is the vector length in quadwords. 832 * 833 * While processing properties during initialization, corresponding init bits 834 * are set for bits in sve_vq_map that have been set by properties. 835 * 836 * Bits set in supported represent valid vector lengths for the CPU type. 837 */ 838 typedef struct { 839 uint32_t map, init, supported; 840 } ARMVQMap; 841 842 /** 843 * ARMCPU: 844 * @env: #CPUARMState 845 * 846 * An ARM CPU core. 847 */ 848 struct ArchCPU { 849 /*< private >*/ 850 CPUState parent_obj; 851 /*< public >*/ 852 853 CPUNegativeOffsetState neg; 854 CPUARMState env; 855 856 /* Coprocessor information */ 857 GHashTable *cp_regs; 858 /* For marshalling (mostly coprocessor) register state between the 859 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 860 * we use these arrays. 861 */ 862 /* List of register indexes managed via these arrays; (full KVM style 863 * 64 bit indexes, not CPRegInfo 32 bit indexes) 864 */ 865 uint64_t *cpreg_indexes; 866 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 867 uint64_t *cpreg_values; 868 /* Length of the indexes, values, reset_values arrays */ 869 int32_t cpreg_array_len; 870 /* These are used only for migration: incoming data arrives in 871 * these fields and is sanity checked in post_load before copying 872 * to the working data structures above. 873 */ 874 uint64_t *cpreg_vmstate_indexes; 875 uint64_t *cpreg_vmstate_values; 876 int32_t cpreg_vmstate_array_len; 877 878 DynamicGDBXMLInfo dyn_sysreg_xml; 879 DynamicGDBXMLInfo dyn_svereg_xml; 880 DynamicGDBXMLInfo dyn_m_systemreg_xml; 881 DynamicGDBXMLInfo dyn_m_secextreg_xml; 882 883 /* Timers used by the generic (architected) timer */ 884 QEMUTimer *gt_timer[NUM_GTIMERS]; 885 /* 886 * Timer used by the PMU. Its state is restored after migration by 887 * pmu_op_finish() - it does not need other handling during migration 888 */ 889 QEMUTimer *pmu_timer; 890 /* GPIO outputs for generic timer */ 891 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 892 /* GPIO output for GICv3 maintenance interrupt signal */ 893 qemu_irq gicv3_maintenance_interrupt; 894 /* GPIO output for the PMU interrupt */ 895 qemu_irq pmu_interrupt; 896 897 /* MemoryRegion to use for secure physical accesses */ 898 MemoryRegion *secure_memory; 899 900 /* MemoryRegion to use for allocation tag accesses */ 901 MemoryRegion *tag_memory; 902 MemoryRegion *secure_tag_memory; 903 904 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 905 Object *idau; 906 907 /* 'compatible' string for this CPU for Linux device trees */ 908 const char *dtb_compatible; 909 910 /* PSCI version for this CPU 911 * Bits[31:16] = Major Version 912 * Bits[15:0] = Minor Version 913 */ 914 uint32_t psci_version; 915 916 /* Current power state, access guarded by BQL */ 917 ARMPSCIState power_state; 918 919 /* CPU has virtualization extension */ 920 bool has_el2; 921 /* CPU has security extension */ 922 bool has_el3; 923 /* CPU has PMU (Performance Monitor Unit) */ 924 bool has_pmu; 925 /* CPU has VFP */ 926 bool has_vfp; 927 /* CPU has 32 VFP registers */ 928 bool has_vfp_d32; 929 /* CPU has Neon */ 930 bool has_neon; 931 /* CPU has M-profile DSP extension */ 932 bool has_dsp; 933 934 /* CPU has memory protection unit */ 935 bool has_mpu; 936 /* PMSAv7 MPU number of supported regions */ 937 uint32_t pmsav7_dregion; 938 /* PMSAv8 MPU number of supported hyp regions */ 939 uint32_t pmsav8r_hdregion; 940 /* v8M SAU number of supported regions */ 941 uint32_t sau_sregion; 942 943 /* PSCI conduit used to invoke PSCI methods 944 * 0 - disabled, 1 - smc, 2 - hvc 945 */ 946 uint32_t psci_conduit; 947 948 /* For v8M, initial value of the Secure VTOR */ 949 uint32_t init_svtor; 950 /* For v8M, initial value of the Non-secure VTOR */ 951 uint32_t init_nsvtor; 952 953 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 954 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 955 */ 956 uint32_t kvm_target; 957 958 /* KVM init features for this CPU */ 959 uint32_t kvm_init_features[7]; 960 961 /* KVM CPU state */ 962 963 /* KVM virtual time adjustment */ 964 bool kvm_adjvtime; 965 bool kvm_vtime_dirty; 966 uint64_t kvm_vtime; 967 968 /* KVM steal time */ 969 OnOffAuto kvm_steal_time; 970 971 /* Uniprocessor system with MP extensions */ 972 bool mp_is_up; 973 974 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 975 * and the probe failed (so we need to report the error in realize) 976 */ 977 bool host_cpu_probe_failed; 978 979 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 980 * register. 981 */ 982 int32_t core_count; 983 984 /* The instance init functions for implementation-specific subclasses 985 * set these fields to specify the implementation-dependent values of 986 * various constant registers and reset values of non-constant 987 * registers. 988 * Some of these might become QOM properties eventually. 989 * Field names match the official register names as defined in the 990 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 991 * is used for reset values of non-constant registers; no reset_ 992 * prefix means a constant register. 993 * Some of these registers are split out into a substructure that 994 * is shared with the translators to control the ISA. 995 * 996 * Note that if you add an ID register to the ARMISARegisters struct 997 * you need to also update the 32-bit and 64-bit versions of the 998 * kvm_arm_get_host_cpu_features() function to correctly populate the 999 * field by reading the value from the KVM vCPU. 1000 */ 1001 struct ARMISARegisters { 1002 uint32_t id_isar0; 1003 uint32_t id_isar1; 1004 uint32_t id_isar2; 1005 uint32_t id_isar3; 1006 uint32_t id_isar4; 1007 uint32_t id_isar5; 1008 uint32_t id_isar6; 1009 uint32_t id_mmfr0; 1010 uint32_t id_mmfr1; 1011 uint32_t id_mmfr2; 1012 uint32_t id_mmfr3; 1013 uint32_t id_mmfr4; 1014 uint32_t id_mmfr5; 1015 uint32_t id_pfr0; 1016 uint32_t id_pfr1; 1017 uint32_t id_pfr2; 1018 uint32_t mvfr0; 1019 uint32_t mvfr1; 1020 uint32_t mvfr2; 1021 uint32_t id_dfr0; 1022 uint32_t id_dfr1; 1023 uint32_t dbgdidr; 1024 uint32_t dbgdevid; 1025 uint32_t dbgdevid1; 1026 uint64_t id_aa64isar0; 1027 uint64_t id_aa64isar1; 1028 uint64_t id_aa64pfr0; 1029 uint64_t id_aa64pfr1; 1030 uint64_t id_aa64mmfr0; 1031 uint64_t id_aa64mmfr1; 1032 uint64_t id_aa64mmfr2; 1033 uint64_t id_aa64dfr0; 1034 uint64_t id_aa64dfr1; 1035 uint64_t id_aa64zfr0; 1036 uint64_t id_aa64smfr0; 1037 uint64_t reset_pmcr_el0; 1038 } isar; 1039 uint64_t midr; 1040 uint32_t revidr; 1041 uint32_t reset_fpsid; 1042 uint64_t ctr; 1043 uint32_t reset_sctlr; 1044 uint64_t pmceid0; 1045 uint64_t pmceid1; 1046 uint32_t id_afr0; 1047 uint64_t id_aa64afr0; 1048 uint64_t id_aa64afr1; 1049 uint64_t clidr; 1050 uint64_t mp_affinity; /* MP ID without feature bits */ 1051 /* The elements of this array are the CCSIDR values for each cache, 1052 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 1053 */ 1054 uint64_t ccsidr[16]; 1055 uint64_t reset_cbar; 1056 uint32_t reset_auxcr; 1057 bool reset_hivecs; 1058 1059 /* 1060 * Intermediate values used during property parsing. 1061 * Once finalized, the values should be read from ID_AA64*. 1062 */ 1063 bool prop_pauth; 1064 bool prop_pauth_impdef; 1065 bool prop_lpa2; 1066 1067 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 1068 uint32_t dcz_blocksize; 1069 uint64_t rvbar_prop; /* Property/input signals. */ 1070 1071 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 1072 int gic_num_lrs; /* number of list registers */ 1073 int gic_vpribits; /* number of virtual priority bits */ 1074 int gic_vprebits; /* number of virtual preemption bits */ 1075 int gic_pribits; /* number of physical priority bits */ 1076 1077 /* Whether the cfgend input is high (i.e. this CPU should reset into 1078 * big-endian mode). This setting isn't used directly: instead it modifies 1079 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 1080 * architecture version. 1081 */ 1082 bool cfgend; 1083 1084 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 1085 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 1086 1087 int32_t node_id; /* NUMA node this CPU belongs to */ 1088 1089 /* Used to synchronize KVM and QEMU in-kernel device levels */ 1090 uint8_t device_irq_level; 1091 1092 /* Used to set the maximum vector length the cpu will support. */ 1093 uint32_t sve_max_vq; 1094 1095 #ifdef CONFIG_USER_ONLY 1096 /* Used to set the default vector length at process start. */ 1097 uint32_t sve_default_vq; 1098 uint32_t sme_default_vq; 1099 #endif 1100 1101 ARMVQMap sve_vq; 1102 ARMVQMap sme_vq; 1103 1104 /* Generic timer counter frequency, in Hz */ 1105 uint64_t gt_cntfrq_hz; 1106 }; 1107 1108 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); 1109 1110 void arm_cpu_post_init(Object *obj); 1111 1112 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); 1113 1114 #ifndef CONFIG_USER_ONLY 1115 extern const VMStateDescription vmstate_arm_cpu; 1116 1117 void arm_cpu_do_interrupt(CPUState *cpu); 1118 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 1119 1120 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 1121 MemTxAttrs *attrs); 1122 #endif /* !CONFIG_USER_ONLY */ 1123 1124 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1125 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1126 1127 /* Returns the dynamically generated XML for the gdb stub. 1128 * Returns a pointer to the XML contents for the specified XML file or NULL 1129 * if the XML name doesn't match the predefined one. 1130 */ 1131 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname); 1132 1133 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 1134 int cpuid, DumpState *s); 1135 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 1136 int cpuid, DumpState *s); 1137 1138 #ifdef TARGET_AARCH64 1139 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1140 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1141 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 1142 void aarch64_sve_change_el(CPUARMState *env, int old_el, 1143 int new_el, bool el0_a64); 1144 void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask); 1145 1146 /* 1147 * SVE registers are encoded in KVM's memory in an endianness-invariant format. 1148 * The byte at offset i from the start of the in-memory representation contains 1149 * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the 1150 * lowest offsets are stored in the lowest memory addresses, then that nearly 1151 * matches QEMU's representation, which is to use an array of host-endian 1152 * uint64_t's, where the lower offsets are at the lower indices. To complete 1153 * the translation we just need to byte swap the uint64_t's on big-endian hosts. 1154 */ 1155 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr) 1156 { 1157 #if HOST_BIG_ENDIAN 1158 int i; 1159 1160 for (i = 0; i < nr; ++i) { 1161 dst[i] = bswap64(src[i]); 1162 } 1163 1164 return dst; 1165 #else 1166 return src; 1167 #endif 1168 } 1169 1170 #else 1171 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } 1172 static inline void aarch64_sve_change_el(CPUARMState *env, int o, 1173 int n, bool a) 1174 { } 1175 #endif 1176 1177 void aarch64_sync_32_to_64(CPUARMState *env); 1178 void aarch64_sync_64_to_32(CPUARMState *env); 1179 1180 int fp_exception_el(CPUARMState *env, int cur_el); 1181 int sve_exception_el(CPUARMState *env, int cur_el); 1182 int sme_exception_el(CPUARMState *env, int cur_el); 1183 1184 /** 1185 * sve_vqm1_for_el_sm: 1186 * @env: CPUARMState 1187 * @el: exception level 1188 * @sm: streaming mode 1189 * 1190 * Compute the current vector length for @el & @sm, in units of 1191 * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN. 1192 * If @sm, compute for SVL, otherwise NVL. 1193 */ 1194 uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm); 1195 1196 /* Likewise, but using @sm = PSTATE.SM. */ 1197 uint32_t sve_vqm1_for_el(CPUARMState *env, int el); 1198 1199 static inline bool is_a64(CPUARMState *env) 1200 { 1201 return env->aarch64; 1202 } 1203 1204 /** 1205 * pmu_op_start/finish 1206 * @env: CPUARMState 1207 * 1208 * Convert all PMU counters between their delta form (the typical mode when 1209 * they are enabled) and the guest-visible values. These two calls must 1210 * surround any action which might affect the counters. 1211 */ 1212 void pmu_op_start(CPUARMState *env); 1213 void pmu_op_finish(CPUARMState *env); 1214 1215 /* 1216 * Called when a PMU counter is due to overflow 1217 */ 1218 void arm_pmu_timer_cb(void *opaque); 1219 1220 /** 1221 * Functions to register as EL change hooks for PMU mode filtering 1222 */ 1223 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1224 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1225 1226 /* 1227 * pmu_init 1228 * @cpu: ARMCPU 1229 * 1230 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1231 * for the current configuration 1232 */ 1233 void pmu_init(ARMCPU *cpu); 1234 1235 /* SCTLR bit meanings. Several bits have been reused in newer 1236 * versions of the architecture; in that case we define constants 1237 * for both old and new bit meanings. Code which tests against those 1238 * bits should probably check or otherwise arrange that the CPU 1239 * is the architectural version it expects. 1240 */ 1241 #define SCTLR_M (1U << 0) 1242 #define SCTLR_A (1U << 1) 1243 #define SCTLR_C (1U << 2) 1244 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1245 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1246 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1247 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1248 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1249 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1250 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1251 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1252 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1253 #define SCTLR_nAA (1U << 6) /* when FEAT_LSE2 is implemented */ 1254 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1255 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1256 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1257 #define SCTLR_SED (1U << 8) /* v8 onward */ 1258 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1259 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1260 #define SCTLR_F (1U << 10) /* up to v6 */ 1261 #define SCTLR_SW (1U << 10) /* v7 */ 1262 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ 1263 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1264 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1265 #define SCTLR_I (1U << 12) 1266 #define SCTLR_V (1U << 13) /* AArch32 only */ 1267 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1268 #define SCTLR_RR (1U << 14) /* up to v7 */ 1269 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1270 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1271 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1272 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1273 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1274 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1275 #define SCTLR_BR (1U << 17) /* PMSA only */ 1276 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1277 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1278 #define SCTLR_WXN (1U << 19) 1279 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1280 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1281 #define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */ 1282 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1283 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1284 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1285 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1286 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1287 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1288 #define SCTLR_VE (1U << 24) /* up to v7 */ 1289 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1290 #define SCTLR_EE (1U << 25) 1291 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1292 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1293 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1294 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1295 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1296 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1297 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1298 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1299 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1300 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1301 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1302 #define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */ 1303 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1304 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1305 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1306 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1307 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1308 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1309 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1310 #define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */ 1311 #define SCTLR_TWEDEn (1ULL << 45) /* FEAT_TWED */ 1312 #define SCTLR_TWEDEL MAKE_64_MASK(46, 4) /* FEAT_TWED */ 1313 #define SCTLR_TMT0 (1ULL << 50) /* FEAT_TME */ 1314 #define SCTLR_TMT (1ULL << 51) /* FEAT_TME */ 1315 #define SCTLR_TME0 (1ULL << 52) /* FEAT_TME */ 1316 #define SCTLR_TME (1ULL << 53) /* FEAT_TME */ 1317 #define SCTLR_EnASR (1ULL << 54) /* FEAT_LS64_V */ 1318 #define SCTLR_EnAS0 (1ULL << 55) /* FEAT_LS64_ACCDATA */ 1319 #define SCTLR_EnALS (1ULL << 56) /* FEAT_LS64 */ 1320 #define SCTLR_EPAN (1ULL << 57) /* FEAT_PAN3 */ 1321 #define SCTLR_EnTP2 (1ULL << 60) /* FEAT_SME */ 1322 #define SCTLR_NMI (1ULL << 61) /* FEAT_NMI */ 1323 #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */ 1324 #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */ 1325 1326 /* Bit definitions for CPACR (AArch32 only) */ 1327 FIELD(CPACR, CP10, 20, 2) 1328 FIELD(CPACR, CP11, 22, 2) 1329 FIELD(CPACR, TRCDIS, 28, 1) /* matches CPACR_EL1.TTA */ 1330 FIELD(CPACR, D32DIS, 30, 1) /* up to v7; RAZ in v8 */ 1331 FIELD(CPACR, ASEDIS, 31, 1) 1332 1333 /* Bit definitions for CPACR_EL1 (AArch64 only) */ 1334 FIELD(CPACR_EL1, ZEN, 16, 2) 1335 FIELD(CPACR_EL1, FPEN, 20, 2) 1336 FIELD(CPACR_EL1, SMEN, 24, 2) 1337 FIELD(CPACR_EL1, TTA, 28, 1) /* matches CPACR.TRCDIS */ 1338 1339 /* Bit definitions for HCPTR (AArch32 only) */ 1340 FIELD(HCPTR, TCP10, 10, 1) 1341 FIELD(HCPTR, TCP11, 11, 1) 1342 FIELD(HCPTR, TASE, 15, 1) 1343 FIELD(HCPTR, TTA, 20, 1) 1344 FIELD(HCPTR, TAM, 30, 1) /* matches CPTR_EL2.TAM */ 1345 FIELD(HCPTR, TCPAC, 31, 1) /* matches CPTR_EL2.TCPAC */ 1346 1347 /* Bit definitions for CPTR_EL2 (AArch64 only) */ 1348 FIELD(CPTR_EL2, TZ, 8, 1) /* !E2H */ 1349 FIELD(CPTR_EL2, TFP, 10, 1) /* !E2H, matches HCPTR.TCP10 */ 1350 FIELD(CPTR_EL2, TSM, 12, 1) /* !E2H */ 1351 FIELD(CPTR_EL2, ZEN, 16, 2) /* E2H */ 1352 FIELD(CPTR_EL2, FPEN, 20, 2) /* E2H */ 1353 FIELD(CPTR_EL2, SMEN, 24, 2) /* E2H */ 1354 FIELD(CPTR_EL2, TTA, 28, 1) 1355 FIELD(CPTR_EL2, TAM, 30, 1) /* matches HCPTR.TAM */ 1356 FIELD(CPTR_EL2, TCPAC, 31, 1) /* matches HCPTR.TCPAC */ 1357 1358 /* Bit definitions for CPTR_EL3 (AArch64 only) */ 1359 FIELD(CPTR_EL3, EZ, 8, 1) 1360 FIELD(CPTR_EL3, TFP, 10, 1) 1361 FIELD(CPTR_EL3, ESM, 12, 1) 1362 FIELD(CPTR_EL3, TTA, 20, 1) 1363 FIELD(CPTR_EL3, TAM, 30, 1) 1364 FIELD(CPTR_EL3, TCPAC, 31, 1) 1365 1366 #define MDCR_MTPME (1U << 28) 1367 #define MDCR_TDCC (1U << 27) 1368 #define MDCR_HLP (1U << 26) /* MDCR_EL2 */ 1369 #define MDCR_SCCD (1U << 23) /* MDCR_EL3 */ 1370 #define MDCR_HCCD (1U << 23) /* MDCR_EL2 */ 1371 #define MDCR_EPMAD (1U << 21) 1372 #define MDCR_EDAD (1U << 20) 1373 #define MDCR_TTRF (1U << 19) 1374 #define MDCR_STE (1U << 18) /* MDCR_EL3 */ 1375 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ 1376 #define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ 1377 #define MDCR_SDD (1U << 16) 1378 #define MDCR_SPD (3U << 14) 1379 #define MDCR_TDRA (1U << 11) 1380 #define MDCR_TDOSA (1U << 10) 1381 #define MDCR_TDA (1U << 9) 1382 #define MDCR_TDE (1U << 8) 1383 #define MDCR_HPME (1U << 7) 1384 #define MDCR_TPM (1U << 6) 1385 #define MDCR_TPMCR (1U << 5) 1386 #define MDCR_HPMN (0x1fU) 1387 1388 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 1389 #define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \ 1390 MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \ 1391 MDCR_STE | MDCR_SPME | MDCR_SPD) 1392 1393 #define CPSR_M (0x1fU) 1394 #define CPSR_T (1U << 5) 1395 #define CPSR_F (1U << 6) 1396 #define CPSR_I (1U << 7) 1397 #define CPSR_A (1U << 8) 1398 #define CPSR_E (1U << 9) 1399 #define CPSR_IT_2_7 (0xfc00U) 1400 #define CPSR_GE (0xfU << 16) 1401 #define CPSR_IL (1U << 20) 1402 #define CPSR_DIT (1U << 21) 1403 #define CPSR_PAN (1U << 22) 1404 #define CPSR_SSBS (1U << 23) 1405 #define CPSR_J (1U << 24) 1406 #define CPSR_IT_0_1 (3U << 25) 1407 #define CPSR_Q (1U << 27) 1408 #define CPSR_V (1U << 28) 1409 #define CPSR_C (1U << 29) 1410 #define CPSR_Z (1U << 30) 1411 #define CPSR_N (1U << 31) 1412 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1413 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1414 1415 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1416 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1417 | CPSR_NZCV) 1418 /* Bits writable in user mode. */ 1419 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E) 1420 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1421 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1422 1423 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1424 #define XPSR_EXCP 0x1ffU 1425 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1426 #define XPSR_IT_2_7 CPSR_IT_2_7 1427 #define XPSR_GE CPSR_GE 1428 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1429 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1430 #define XPSR_IT_0_1 CPSR_IT_0_1 1431 #define XPSR_Q CPSR_Q 1432 #define XPSR_V CPSR_V 1433 #define XPSR_C CPSR_C 1434 #define XPSR_Z CPSR_Z 1435 #define XPSR_N CPSR_N 1436 #define XPSR_NZCV CPSR_NZCV 1437 #define XPSR_IT CPSR_IT 1438 1439 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 1440 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 1441 #define TTBCR_PD0 (1U << 4) 1442 #define TTBCR_PD1 (1U << 5) 1443 #define TTBCR_EPD0 (1U << 7) 1444 #define TTBCR_IRGN0 (3U << 8) 1445 #define TTBCR_ORGN0 (3U << 10) 1446 #define TTBCR_SH0 (3U << 12) 1447 #define TTBCR_T1SZ (3U << 16) 1448 #define TTBCR_A1 (1U << 22) 1449 #define TTBCR_EPD1 (1U << 23) 1450 #define TTBCR_IRGN1 (3U << 24) 1451 #define TTBCR_ORGN1 (3U << 26) 1452 #define TTBCR_SH1 (1U << 28) 1453 #define TTBCR_EAE (1U << 31) 1454 1455 FIELD(VTCR, T0SZ, 0, 6) 1456 FIELD(VTCR, SL0, 6, 2) 1457 FIELD(VTCR, IRGN0, 8, 2) 1458 FIELD(VTCR, ORGN0, 10, 2) 1459 FIELD(VTCR, SH0, 12, 2) 1460 FIELD(VTCR, TG0, 14, 2) 1461 FIELD(VTCR, PS, 16, 3) 1462 FIELD(VTCR, VS, 19, 1) 1463 FIELD(VTCR, HA, 21, 1) 1464 FIELD(VTCR, HD, 22, 1) 1465 FIELD(VTCR, HWU59, 25, 1) 1466 FIELD(VTCR, HWU60, 26, 1) 1467 FIELD(VTCR, HWU61, 27, 1) 1468 FIELD(VTCR, HWU62, 28, 1) 1469 FIELD(VTCR, NSW, 29, 1) 1470 FIELD(VTCR, NSA, 30, 1) 1471 FIELD(VTCR, DS, 32, 1) 1472 FIELD(VTCR, SL2, 33, 1) 1473 1474 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1475 * Only these are valid when in AArch64 mode; in 1476 * AArch32 mode SPSRs are basically CPSR-format. 1477 */ 1478 #define PSTATE_SP (1U) 1479 #define PSTATE_M (0xFU) 1480 #define PSTATE_nRW (1U << 4) 1481 #define PSTATE_F (1U << 6) 1482 #define PSTATE_I (1U << 7) 1483 #define PSTATE_A (1U << 8) 1484 #define PSTATE_D (1U << 9) 1485 #define PSTATE_BTYPE (3U << 10) 1486 #define PSTATE_SSBS (1U << 12) 1487 #define PSTATE_IL (1U << 20) 1488 #define PSTATE_SS (1U << 21) 1489 #define PSTATE_PAN (1U << 22) 1490 #define PSTATE_UAO (1U << 23) 1491 #define PSTATE_DIT (1U << 24) 1492 #define PSTATE_TCO (1U << 25) 1493 #define PSTATE_V (1U << 28) 1494 #define PSTATE_C (1U << 29) 1495 #define PSTATE_Z (1U << 30) 1496 #define PSTATE_N (1U << 31) 1497 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1498 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1499 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1500 /* Mode values for AArch64 */ 1501 #define PSTATE_MODE_EL3h 13 1502 #define PSTATE_MODE_EL3t 12 1503 #define PSTATE_MODE_EL2h 9 1504 #define PSTATE_MODE_EL2t 8 1505 #define PSTATE_MODE_EL1h 5 1506 #define PSTATE_MODE_EL1t 4 1507 #define PSTATE_MODE_EL0t 0 1508 1509 /* PSTATE bits that are accessed via SVCR and not stored in SPSR_ELx. */ 1510 FIELD(SVCR, SM, 0, 1) 1511 FIELD(SVCR, ZA, 1, 1) 1512 1513 /* Fields for SMCR_ELx. */ 1514 FIELD(SMCR, LEN, 0, 4) 1515 FIELD(SMCR, FA64, 31, 1) 1516 1517 /* Write a new value to v7m.exception, thus transitioning into or out 1518 * of Handler mode; this may result in a change of active stack pointer. 1519 */ 1520 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1521 1522 /* Map EL and handler into a PSTATE_MODE. */ 1523 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1524 { 1525 return (el << 2) | handler; 1526 } 1527 1528 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1529 * interprocessing, so we don't attempt to sync with the cpsr state used by 1530 * the 32 bit decoder. 1531 */ 1532 static inline uint32_t pstate_read(CPUARMState *env) 1533 { 1534 int ZF; 1535 1536 ZF = (env->ZF == 0); 1537 return (env->NF & 0x80000000) | (ZF << 30) 1538 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1539 | env->pstate | env->daif | (env->btype << 10); 1540 } 1541 1542 static inline void pstate_write(CPUARMState *env, uint32_t val) 1543 { 1544 env->ZF = (~val) & PSTATE_Z; 1545 env->NF = val; 1546 env->CF = (val >> 29) & 1; 1547 env->VF = (val << 3) & 0x80000000; 1548 env->daif = val & PSTATE_DAIF; 1549 env->btype = (val >> 10) & 3; 1550 env->pstate = val & ~CACHED_PSTATE_BITS; 1551 } 1552 1553 /* Return the current CPSR value. */ 1554 uint32_t cpsr_read(CPUARMState *env); 1555 1556 typedef enum CPSRWriteType { 1557 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1558 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1559 CPSRWriteRaw = 2, 1560 /* trust values, no reg bank switch, no hflags rebuild */ 1561 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1562 } CPSRWriteType; 1563 1564 /* 1565 * Set the CPSR. Note that some bits of mask must be all-set or all-clear. 1566 * This will do an arm_rebuild_hflags() if any of the bits in @mask 1567 * correspond to TB flags bits cached in the hflags, unless @write_type 1568 * is CPSRWriteRaw. 1569 */ 1570 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1571 CPSRWriteType write_type); 1572 1573 /* Return the current xPSR value. */ 1574 static inline uint32_t xpsr_read(CPUARMState *env) 1575 { 1576 int ZF; 1577 ZF = (env->ZF == 0); 1578 return (env->NF & 0x80000000) | (ZF << 30) 1579 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1580 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1581 | ((env->condexec_bits & 0xfc) << 8) 1582 | (env->GE << 16) 1583 | env->v7m.exception; 1584 } 1585 1586 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1587 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1588 { 1589 if (mask & XPSR_NZCV) { 1590 env->ZF = (~val) & XPSR_Z; 1591 env->NF = val; 1592 env->CF = (val >> 29) & 1; 1593 env->VF = (val << 3) & 0x80000000; 1594 } 1595 if (mask & XPSR_Q) { 1596 env->QF = ((val & XPSR_Q) != 0); 1597 } 1598 if (mask & XPSR_GE) { 1599 env->GE = (val & XPSR_GE) >> 16; 1600 } 1601 #ifndef CONFIG_USER_ONLY 1602 if (mask & XPSR_T) { 1603 env->thumb = ((val & XPSR_T) != 0); 1604 } 1605 if (mask & XPSR_IT_0_1) { 1606 env->condexec_bits &= ~3; 1607 env->condexec_bits |= (val >> 25) & 3; 1608 } 1609 if (mask & XPSR_IT_2_7) { 1610 env->condexec_bits &= 3; 1611 env->condexec_bits |= (val >> 8) & 0xfc; 1612 } 1613 if (mask & XPSR_EXCP) { 1614 /* Note that this only happens on exception exit */ 1615 write_v7m_exception(env, val & XPSR_EXCP); 1616 } 1617 #endif 1618 } 1619 1620 #define HCR_VM (1ULL << 0) 1621 #define HCR_SWIO (1ULL << 1) 1622 #define HCR_PTW (1ULL << 2) 1623 #define HCR_FMO (1ULL << 3) 1624 #define HCR_IMO (1ULL << 4) 1625 #define HCR_AMO (1ULL << 5) 1626 #define HCR_VF (1ULL << 6) 1627 #define HCR_VI (1ULL << 7) 1628 #define HCR_VSE (1ULL << 8) 1629 #define HCR_FB (1ULL << 9) 1630 #define HCR_BSU_MASK (3ULL << 10) 1631 #define HCR_DC (1ULL << 12) 1632 #define HCR_TWI (1ULL << 13) 1633 #define HCR_TWE (1ULL << 14) 1634 #define HCR_TID0 (1ULL << 15) 1635 #define HCR_TID1 (1ULL << 16) 1636 #define HCR_TID2 (1ULL << 17) 1637 #define HCR_TID3 (1ULL << 18) 1638 #define HCR_TSC (1ULL << 19) 1639 #define HCR_TIDCP (1ULL << 20) 1640 #define HCR_TACR (1ULL << 21) 1641 #define HCR_TSW (1ULL << 22) 1642 #define HCR_TPCP (1ULL << 23) 1643 #define HCR_TPU (1ULL << 24) 1644 #define HCR_TTLB (1ULL << 25) 1645 #define HCR_TVM (1ULL << 26) 1646 #define HCR_TGE (1ULL << 27) 1647 #define HCR_TDZ (1ULL << 28) 1648 #define HCR_HCD (1ULL << 29) 1649 #define HCR_TRVM (1ULL << 30) 1650 #define HCR_RW (1ULL << 31) 1651 #define HCR_CD (1ULL << 32) 1652 #define HCR_ID (1ULL << 33) 1653 #define HCR_E2H (1ULL << 34) 1654 #define HCR_TLOR (1ULL << 35) 1655 #define HCR_TERR (1ULL << 36) 1656 #define HCR_TEA (1ULL << 37) 1657 #define HCR_MIOCNCE (1ULL << 38) 1658 /* RES0 bit 39 */ 1659 #define HCR_APK (1ULL << 40) 1660 #define HCR_API (1ULL << 41) 1661 #define HCR_NV (1ULL << 42) 1662 #define HCR_NV1 (1ULL << 43) 1663 #define HCR_AT (1ULL << 44) 1664 #define HCR_NV2 (1ULL << 45) 1665 #define HCR_FWB (1ULL << 46) 1666 #define HCR_FIEN (1ULL << 47) 1667 /* RES0 bit 48 */ 1668 #define HCR_TID4 (1ULL << 49) 1669 #define HCR_TICAB (1ULL << 50) 1670 #define HCR_AMVOFFEN (1ULL << 51) 1671 #define HCR_TOCU (1ULL << 52) 1672 #define HCR_ENSCXT (1ULL << 53) 1673 #define HCR_TTLBIS (1ULL << 54) 1674 #define HCR_TTLBOS (1ULL << 55) 1675 #define HCR_ATA (1ULL << 56) 1676 #define HCR_DCT (1ULL << 57) 1677 #define HCR_TID5 (1ULL << 58) 1678 #define HCR_TWEDEN (1ULL << 59) 1679 #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) 1680 1681 #define HCRX_ENAS0 (1ULL << 0) 1682 #define HCRX_ENALS (1ULL << 1) 1683 #define HCRX_ENASR (1ULL << 2) 1684 #define HCRX_FNXS (1ULL << 3) 1685 #define HCRX_FGTNXS (1ULL << 4) 1686 #define HCRX_SMPME (1ULL << 5) 1687 #define HCRX_TALLINT (1ULL << 6) 1688 #define HCRX_VINMI (1ULL << 7) 1689 #define HCRX_VFNMI (1ULL << 8) 1690 #define HCRX_CMOW (1ULL << 9) 1691 #define HCRX_MCE2 (1ULL << 10) 1692 #define HCRX_MSCEN (1ULL << 11) 1693 1694 #define HPFAR_NS (1ULL << 63) 1695 1696 #define SCR_NS (1ULL << 0) 1697 #define SCR_IRQ (1ULL << 1) 1698 #define SCR_FIQ (1ULL << 2) 1699 #define SCR_EA (1ULL << 3) 1700 #define SCR_FW (1ULL << 4) 1701 #define SCR_AW (1ULL << 5) 1702 #define SCR_NET (1ULL << 6) 1703 #define SCR_SMD (1ULL << 7) 1704 #define SCR_HCE (1ULL << 8) 1705 #define SCR_SIF (1ULL << 9) 1706 #define SCR_RW (1ULL << 10) 1707 #define SCR_ST (1ULL << 11) 1708 #define SCR_TWI (1ULL << 12) 1709 #define SCR_TWE (1ULL << 13) 1710 #define SCR_TLOR (1ULL << 14) 1711 #define SCR_TERR (1ULL << 15) 1712 #define SCR_APK (1ULL << 16) 1713 #define SCR_API (1ULL << 17) 1714 #define SCR_EEL2 (1ULL << 18) 1715 #define SCR_EASE (1ULL << 19) 1716 #define SCR_NMEA (1ULL << 20) 1717 #define SCR_FIEN (1ULL << 21) 1718 #define SCR_ENSCXT (1ULL << 25) 1719 #define SCR_ATA (1ULL << 26) 1720 #define SCR_FGTEN (1ULL << 27) 1721 #define SCR_ECVEN (1ULL << 28) 1722 #define SCR_TWEDEN (1ULL << 29) 1723 #define SCR_TWEDEL MAKE_64BIT_MASK(30, 4) 1724 #define SCR_TME (1ULL << 34) 1725 #define SCR_AMVOFFEN (1ULL << 35) 1726 #define SCR_ENAS0 (1ULL << 36) 1727 #define SCR_ADEN (1ULL << 37) 1728 #define SCR_HXEN (1ULL << 38) 1729 #define SCR_TRNDR (1ULL << 40) 1730 #define SCR_ENTP2 (1ULL << 41) 1731 #define SCR_GPF (1ULL << 48) 1732 1733 #define HSTR_TTEE (1 << 16) 1734 #define HSTR_TJDBX (1 << 17) 1735 1736 /* Return the current FPSCR value. */ 1737 uint32_t vfp_get_fpscr(CPUARMState *env); 1738 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1739 1740 /* FPCR, Floating Point Control Register 1741 * FPSR, Floating Poiht Status Register 1742 * 1743 * For A64 the FPSCR is split into two logically distinct registers, 1744 * FPCR and FPSR. However since they still use non-overlapping bits 1745 * we store the underlying state in fpscr and just mask on read/write. 1746 */ 1747 #define FPSR_MASK 0xf800009f 1748 #define FPCR_MASK 0x07ff9f00 1749 1750 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1751 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1752 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1753 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1754 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1755 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1756 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1757 #define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */ 1758 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1759 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1760 #define FPCR_AHP (1 << 26) /* Alternative half-precision */ 1761 #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ 1762 #define FPCR_V (1 << 28) /* FP overflow flag */ 1763 #define FPCR_C (1 << 29) /* FP carry flag */ 1764 #define FPCR_Z (1 << 30) /* FP zero flag */ 1765 #define FPCR_N (1 << 31) /* FP negative flag */ 1766 1767 #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */ 1768 #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT) 1769 #define FPCR_LTPSIZE_LENGTH 3 1770 1771 #define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V) 1772 #define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC) 1773 1774 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1775 { 1776 return vfp_get_fpscr(env) & FPSR_MASK; 1777 } 1778 1779 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1780 { 1781 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1782 vfp_set_fpscr(env, new_fpscr); 1783 } 1784 1785 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1786 { 1787 return vfp_get_fpscr(env) & FPCR_MASK; 1788 } 1789 1790 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1791 { 1792 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1793 vfp_set_fpscr(env, new_fpscr); 1794 } 1795 1796 enum arm_cpu_mode { 1797 ARM_CPU_MODE_USR = 0x10, 1798 ARM_CPU_MODE_FIQ = 0x11, 1799 ARM_CPU_MODE_IRQ = 0x12, 1800 ARM_CPU_MODE_SVC = 0x13, 1801 ARM_CPU_MODE_MON = 0x16, 1802 ARM_CPU_MODE_ABT = 0x17, 1803 ARM_CPU_MODE_HYP = 0x1a, 1804 ARM_CPU_MODE_UND = 0x1b, 1805 ARM_CPU_MODE_SYS = 0x1f 1806 }; 1807 1808 /* VFP system registers. */ 1809 #define ARM_VFP_FPSID 0 1810 #define ARM_VFP_FPSCR 1 1811 #define ARM_VFP_MVFR2 5 1812 #define ARM_VFP_MVFR1 6 1813 #define ARM_VFP_MVFR0 7 1814 #define ARM_VFP_FPEXC 8 1815 #define ARM_VFP_FPINST 9 1816 #define ARM_VFP_FPINST2 10 1817 /* These ones are M-profile only */ 1818 #define ARM_VFP_FPSCR_NZCVQC 2 1819 #define ARM_VFP_VPR 12 1820 #define ARM_VFP_P0 13 1821 #define ARM_VFP_FPCXT_NS 14 1822 #define ARM_VFP_FPCXT_S 15 1823 1824 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */ 1825 #define QEMU_VFP_FPSCR_NZCV 0xffff 1826 1827 /* iwMMXt coprocessor control registers. */ 1828 #define ARM_IWMMXT_wCID 0 1829 #define ARM_IWMMXT_wCon 1 1830 #define ARM_IWMMXT_wCSSF 2 1831 #define ARM_IWMMXT_wCASF 3 1832 #define ARM_IWMMXT_wCGR0 8 1833 #define ARM_IWMMXT_wCGR1 9 1834 #define ARM_IWMMXT_wCGR2 10 1835 #define ARM_IWMMXT_wCGR3 11 1836 1837 /* V7M CCR bits */ 1838 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1839 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1840 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1841 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1842 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1843 FIELD(V7M_CCR, STKALIGN, 9, 1) 1844 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1845 FIELD(V7M_CCR, DC, 16, 1) 1846 FIELD(V7M_CCR, IC, 17, 1) 1847 FIELD(V7M_CCR, BP, 18, 1) 1848 FIELD(V7M_CCR, LOB, 19, 1) 1849 FIELD(V7M_CCR, TRD, 20, 1) 1850 1851 /* V7M SCR bits */ 1852 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1853 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1854 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1855 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1856 1857 /* V7M AIRCR bits */ 1858 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1859 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1860 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1861 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1862 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1863 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1864 FIELD(V7M_AIRCR, PRIS, 14, 1) 1865 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1866 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1867 1868 /* V7M CFSR bits for MMFSR */ 1869 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1870 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1871 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1872 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1873 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1874 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1875 1876 /* V7M CFSR bits for BFSR */ 1877 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1878 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1879 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1880 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1881 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1882 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1883 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1884 1885 /* V7M CFSR bits for UFSR */ 1886 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1887 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1888 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1889 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1890 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1891 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1892 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1893 1894 /* V7M CFSR bit masks covering all of the subregister bits */ 1895 FIELD(V7M_CFSR, MMFSR, 0, 8) 1896 FIELD(V7M_CFSR, BFSR, 8, 8) 1897 FIELD(V7M_CFSR, UFSR, 16, 16) 1898 1899 /* V7M HFSR bits */ 1900 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1901 FIELD(V7M_HFSR, FORCED, 30, 1) 1902 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1903 1904 /* V7M DFSR bits */ 1905 FIELD(V7M_DFSR, HALTED, 0, 1) 1906 FIELD(V7M_DFSR, BKPT, 1, 1) 1907 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1908 FIELD(V7M_DFSR, VCATCH, 3, 1) 1909 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1910 1911 /* V7M SFSR bits */ 1912 FIELD(V7M_SFSR, INVEP, 0, 1) 1913 FIELD(V7M_SFSR, INVIS, 1, 1) 1914 FIELD(V7M_SFSR, INVER, 2, 1) 1915 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1916 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1917 FIELD(V7M_SFSR, LSPERR, 5, 1) 1918 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1919 FIELD(V7M_SFSR, LSERR, 7, 1) 1920 1921 /* v7M MPU_CTRL bits */ 1922 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1923 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1924 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1925 1926 /* v7M CLIDR bits */ 1927 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1928 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1929 FIELD(V7M_CLIDR, LOC, 24, 3) 1930 FIELD(V7M_CLIDR, LOUU, 27, 3) 1931 FIELD(V7M_CLIDR, ICB, 30, 2) 1932 1933 FIELD(V7M_CSSELR, IND, 0, 1) 1934 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1935 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1936 * define a mask for this and check that it doesn't permit running off 1937 * the end of the array. 1938 */ 1939 FIELD(V7M_CSSELR, INDEX, 0, 4) 1940 1941 /* v7M FPCCR bits */ 1942 FIELD(V7M_FPCCR, LSPACT, 0, 1) 1943 FIELD(V7M_FPCCR, USER, 1, 1) 1944 FIELD(V7M_FPCCR, S, 2, 1) 1945 FIELD(V7M_FPCCR, THREAD, 3, 1) 1946 FIELD(V7M_FPCCR, HFRDY, 4, 1) 1947 FIELD(V7M_FPCCR, MMRDY, 5, 1) 1948 FIELD(V7M_FPCCR, BFRDY, 6, 1) 1949 FIELD(V7M_FPCCR, SFRDY, 7, 1) 1950 FIELD(V7M_FPCCR, MONRDY, 8, 1) 1951 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) 1952 FIELD(V7M_FPCCR, UFRDY, 10, 1) 1953 FIELD(V7M_FPCCR, RES0, 11, 15) 1954 FIELD(V7M_FPCCR, TS, 26, 1) 1955 FIELD(V7M_FPCCR, CLRONRETS, 27, 1) 1956 FIELD(V7M_FPCCR, CLRONRET, 28, 1) 1957 FIELD(V7M_FPCCR, LSPENS, 29, 1) 1958 FIELD(V7M_FPCCR, LSPEN, 30, 1) 1959 FIELD(V7M_FPCCR, ASPEN, 31, 1) 1960 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */ 1961 #define R_V7M_FPCCR_BANKED_MASK \ 1962 (R_V7M_FPCCR_LSPACT_MASK | \ 1963 R_V7M_FPCCR_USER_MASK | \ 1964 R_V7M_FPCCR_THREAD_MASK | \ 1965 R_V7M_FPCCR_MMRDY_MASK | \ 1966 R_V7M_FPCCR_SPLIMVIOL_MASK | \ 1967 R_V7M_FPCCR_UFRDY_MASK | \ 1968 R_V7M_FPCCR_ASPEN_MASK) 1969 1970 /* v7M VPR bits */ 1971 FIELD(V7M_VPR, P0, 0, 16) 1972 FIELD(V7M_VPR, MASK01, 16, 4) 1973 FIELD(V7M_VPR, MASK23, 20, 4) 1974 1975 /* 1976 * System register ID fields. 1977 */ 1978 FIELD(CLIDR_EL1, CTYPE1, 0, 3) 1979 FIELD(CLIDR_EL1, CTYPE2, 3, 3) 1980 FIELD(CLIDR_EL1, CTYPE3, 6, 3) 1981 FIELD(CLIDR_EL1, CTYPE4, 9, 3) 1982 FIELD(CLIDR_EL1, CTYPE5, 12, 3) 1983 FIELD(CLIDR_EL1, CTYPE6, 15, 3) 1984 FIELD(CLIDR_EL1, CTYPE7, 18, 3) 1985 FIELD(CLIDR_EL1, LOUIS, 21, 3) 1986 FIELD(CLIDR_EL1, LOC, 24, 3) 1987 FIELD(CLIDR_EL1, LOUU, 27, 3) 1988 FIELD(CLIDR_EL1, ICB, 30, 3) 1989 1990 /* When FEAT_CCIDX is implemented */ 1991 FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3) 1992 FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21) 1993 FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24) 1994 1995 /* When FEAT_CCIDX is not implemented */ 1996 FIELD(CCSIDR_EL1, LINESIZE, 0, 3) 1997 FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10) 1998 FIELD(CCSIDR_EL1, NUMSETS, 13, 15) 1999 2000 FIELD(CTR_EL0, IMINLINE, 0, 4) 2001 FIELD(CTR_EL0, L1IP, 14, 2) 2002 FIELD(CTR_EL0, DMINLINE, 16, 4) 2003 FIELD(CTR_EL0, ERG, 20, 4) 2004 FIELD(CTR_EL0, CWG, 24, 4) 2005 FIELD(CTR_EL0, IDC, 28, 1) 2006 FIELD(CTR_EL0, DIC, 29, 1) 2007 FIELD(CTR_EL0, TMINLINE, 32, 6) 2008 2009 FIELD(MIDR_EL1, REVISION, 0, 4) 2010 FIELD(MIDR_EL1, PARTNUM, 4, 12) 2011 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) 2012 FIELD(MIDR_EL1, VARIANT, 20, 4) 2013 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) 2014 2015 FIELD(ID_ISAR0, SWAP, 0, 4) 2016 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 2017 FIELD(ID_ISAR0, BITFIELD, 8, 4) 2018 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 2019 FIELD(ID_ISAR0, COPROC, 16, 4) 2020 FIELD(ID_ISAR0, DEBUG, 20, 4) 2021 FIELD(ID_ISAR0, DIVIDE, 24, 4) 2022 2023 FIELD(ID_ISAR1, ENDIAN, 0, 4) 2024 FIELD(ID_ISAR1, EXCEPT, 4, 4) 2025 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 2026 FIELD(ID_ISAR1, EXTEND, 12, 4) 2027 FIELD(ID_ISAR1, IFTHEN, 16, 4) 2028 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 2029 FIELD(ID_ISAR1, INTERWORK, 24, 4) 2030 FIELD(ID_ISAR1, JAZELLE, 28, 4) 2031 2032 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 2033 FIELD(ID_ISAR2, MEMHINT, 4, 4) 2034 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 2035 FIELD(ID_ISAR2, MULT, 12, 4) 2036 FIELD(ID_ISAR2, MULTS, 16, 4) 2037 FIELD(ID_ISAR2, MULTU, 20, 4) 2038 FIELD(ID_ISAR2, PSR_AR, 24, 4) 2039 FIELD(ID_ISAR2, REVERSAL, 28, 4) 2040 2041 FIELD(ID_ISAR3, SATURATE, 0, 4) 2042 FIELD(ID_ISAR3, SIMD, 4, 4) 2043 FIELD(ID_ISAR3, SVC, 8, 4) 2044 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 2045 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 2046 FIELD(ID_ISAR3, T32COPY, 20, 4) 2047 FIELD(ID_ISAR3, TRUENOP, 24, 4) 2048 FIELD(ID_ISAR3, T32EE, 28, 4) 2049 2050 FIELD(ID_ISAR4, UNPRIV, 0, 4) 2051 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 2052 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 2053 FIELD(ID_ISAR4, SMC, 12, 4) 2054 FIELD(ID_ISAR4, BARRIER, 16, 4) 2055 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 2056 FIELD(ID_ISAR4, PSR_M, 24, 4) 2057 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 2058 2059 FIELD(ID_ISAR5, SEVL, 0, 4) 2060 FIELD(ID_ISAR5, AES, 4, 4) 2061 FIELD(ID_ISAR5, SHA1, 8, 4) 2062 FIELD(ID_ISAR5, SHA2, 12, 4) 2063 FIELD(ID_ISAR5, CRC32, 16, 4) 2064 FIELD(ID_ISAR5, RDM, 24, 4) 2065 FIELD(ID_ISAR5, VCMA, 28, 4) 2066 2067 FIELD(ID_ISAR6, JSCVT, 0, 4) 2068 FIELD(ID_ISAR6, DP, 4, 4) 2069 FIELD(ID_ISAR6, FHM, 8, 4) 2070 FIELD(ID_ISAR6, SB, 12, 4) 2071 FIELD(ID_ISAR6, SPECRES, 16, 4) 2072 FIELD(ID_ISAR6, BF16, 20, 4) 2073 FIELD(ID_ISAR6, I8MM, 24, 4) 2074 2075 FIELD(ID_MMFR0, VMSA, 0, 4) 2076 FIELD(ID_MMFR0, PMSA, 4, 4) 2077 FIELD(ID_MMFR0, OUTERSHR, 8, 4) 2078 FIELD(ID_MMFR0, SHARELVL, 12, 4) 2079 FIELD(ID_MMFR0, TCM, 16, 4) 2080 FIELD(ID_MMFR0, AUXREG, 20, 4) 2081 FIELD(ID_MMFR0, FCSE, 24, 4) 2082 FIELD(ID_MMFR0, INNERSHR, 28, 4) 2083 2084 FIELD(ID_MMFR1, L1HVDVA, 0, 4) 2085 FIELD(ID_MMFR1, L1UNIVA, 4, 4) 2086 FIELD(ID_MMFR1, L1HVDSW, 8, 4) 2087 FIELD(ID_MMFR1, L1UNISW, 12, 4) 2088 FIELD(ID_MMFR1, L1HVD, 16, 4) 2089 FIELD(ID_MMFR1, L1UNI, 20, 4) 2090 FIELD(ID_MMFR1, L1TSTCLN, 24, 4) 2091 FIELD(ID_MMFR1, BPRED, 28, 4) 2092 2093 FIELD(ID_MMFR2, L1HVDFG, 0, 4) 2094 FIELD(ID_MMFR2, L1HVDBG, 4, 4) 2095 FIELD(ID_MMFR2, L1HVDRNG, 8, 4) 2096 FIELD(ID_MMFR2, HVDTLB, 12, 4) 2097 FIELD(ID_MMFR2, UNITLB, 16, 4) 2098 FIELD(ID_MMFR2, MEMBARR, 20, 4) 2099 FIELD(ID_MMFR2, WFISTALL, 24, 4) 2100 FIELD(ID_MMFR2, HWACCFLG, 28, 4) 2101 2102 FIELD(ID_MMFR3, CMAINTVA, 0, 4) 2103 FIELD(ID_MMFR3, CMAINTSW, 4, 4) 2104 FIELD(ID_MMFR3, BPMAINT, 8, 4) 2105 FIELD(ID_MMFR3, MAINTBCST, 12, 4) 2106 FIELD(ID_MMFR3, PAN, 16, 4) 2107 FIELD(ID_MMFR3, COHWALK, 20, 4) 2108 FIELD(ID_MMFR3, CMEMSZ, 24, 4) 2109 FIELD(ID_MMFR3, SUPERSEC, 28, 4) 2110 2111 FIELD(ID_MMFR4, SPECSEI, 0, 4) 2112 FIELD(ID_MMFR4, AC2, 4, 4) 2113 FIELD(ID_MMFR4, XNX, 8, 4) 2114 FIELD(ID_MMFR4, CNP, 12, 4) 2115 FIELD(ID_MMFR4, HPDS, 16, 4) 2116 FIELD(ID_MMFR4, LSM, 20, 4) 2117 FIELD(ID_MMFR4, CCIDX, 24, 4) 2118 FIELD(ID_MMFR4, EVT, 28, 4) 2119 2120 FIELD(ID_MMFR5, ETS, 0, 4) 2121 FIELD(ID_MMFR5, NTLBPA, 4, 4) 2122 2123 FIELD(ID_PFR0, STATE0, 0, 4) 2124 FIELD(ID_PFR0, STATE1, 4, 4) 2125 FIELD(ID_PFR0, STATE2, 8, 4) 2126 FIELD(ID_PFR0, STATE3, 12, 4) 2127 FIELD(ID_PFR0, CSV2, 16, 4) 2128 FIELD(ID_PFR0, AMU, 20, 4) 2129 FIELD(ID_PFR0, DIT, 24, 4) 2130 FIELD(ID_PFR0, RAS, 28, 4) 2131 2132 FIELD(ID_PFR1, PROGMOD, 0, 4) 2133 FIELD(ID_PFR1, SECURITY, 4, 4) 2134 FIELD(ID_PFR1, MPROGMOD, 8, 4) 2135 FIELD(ID_PFR1, VIRTUALIZATION, 12, 4) 2136 FIELD(ID_PFR1, GENTIMER, 16, 4) 2137 FIELD(ID_PFR1, SEC_FRAC, 20, 4) 2138 FIELD(ID_PFR1, VIRT_FRAC, 24, 4) 2139 FIELD(ID_PFR1, GIC, 28, 4) 2140 2141 FIELD(ID_PFR2, CSV3, 0, 4) 2142 FIELD(ID_PFR2, SSBS, 4, 4) 2143 FIELD(ID_PFR2, RAS_FRAC, 8, 4) 2144 2145 FIELD(ID_AA64ISAR0, AES, 4, 4) 2146 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 2147 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 2148 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 2149 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 2150 FIELD(ID_AA64ISAR0, RDM, 28, 4) 2151 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 2152 FIELD(ID_AA64ISAR0, SM3, 36, 4) 2153 FIELD(ID_AA64ISAR0, SM4, 40, 4) 2154 FIELD(ID_AA64ISAR0, DP, 44, 4) 2155 FIELD(ID_AA64ISAR0, FHM, 48, 4) 2156 FIELD(ID_AA64ISAR0, TS, 52, 4) 2157 FIELD(ID_AA64ISAR0, TLB, 56, 4) 2158 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 2159 2160 FIELD(ID_AA64ISAR1, DPB, 0, 4) 2161 FIELD(ID_AA64ISAR1, APA, 4, 4) 2162 FIELD(ID_AA64ISAR1, API, 8, 4) 2163 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 2164 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 2165 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 2166 FIELD(ID_AA64ISAR1, GPA, 24, 4) 2167 FIELD(ID_AA64ISAR1, GPI, 28, 4) 2168 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 2169 FIELD(ID_AA64ISAR1, SB, 36, 4) 2170 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 2171 FIELD(ID_AA64ISAR1, BF16, 44, 4) 2172 FIELD(ID_AA64ISAR1, DGH, 48, 4) 2173 FIELD(ID_AA64ISAR1, I8MM, 52, 4) 2174 FIELD(ID_AA64ISAR1, XS, 56, 4) 2175 FIELD(ID_AA64ISAR1, LS64, 60, 4) 2176 2177 FIELD(ID_AA64ISAR2, WFXT, 0, 4) 2178 FIELD(ID_AA64ISAR2, RPRES, 4, 4) 2179 FIELD(ID_AA64ISAR2, GPA3, 8, 4) 2180 FIELD(ID_AA64ISAR2, APA3, 12, 4) 2181 FIELD(ID_AA64ISAR2, MOPS, 16, 4) 2182 FIELD(ID_AA64ISAR2, BC, 20, 4) 2183 FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4) 2184 2185 FIELD(ID_AA64PFR0, EL0, 0, 4) 2186 FIELD(ID_AA64PFR0, EL1, 4, 4) 2187 FIELD(ID_AA64PFR0, EL2, 8, 4) 2188 FIELD(ID_AA64PFR0, EL3, 12, 4) 2189 FIELD(ID_AA64PFR0, FP, 16, 4) 2190 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 2191 FIELD(ID_AA64PFR0, GIC, 24, 4) 2192 FIELD(ID_AA64PFR0, RAS, 28, 4) 2193 FIELD(ID_AA64PFR0, SVE, 32, 4) 2194 FIELD(ID_AA64PFR0, SEL2, 36, 4) 2195 FIELD(ID_AA64PFR0, MPAM, 40, 4) 2196 FIELD(ID_AA64PFR0, AMU, 44, 4) 2197 FIELD(ID_AA64PFR0, DIT, 48, 4) 2198 FIELD(ID_AA64PFR0, CSV2, 56, 4) 2199 FIELD(ID_AA64PFR0, CSV3, 60, 4) 2200 2201 FIELD(ID_AA64PFR1, BT, 0, 4) 2202 FIELD(ID_AA64PFR1, SSBS, 4, 4) 2203 FIELD(ID_AA64PFR1, MTE, 8, 4) 2204 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 2205 FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) 2206 FIELD(ID_AA64PFR1, SME, 24, 4) 2207 FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4) 2208 FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4) 2209 FIELD(ID_AA64PFR1, NMI, 36, 4) 2210 2211 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 2212 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 2213 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 2214 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 2215 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 2216 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 2217 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 2218 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 2219 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 2220 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 2221 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 2222 FIELD(ID_AA64MMFR0, EXS, 44, 4) 2223 FIELD(ID_AA64MMFR0, FGT, 56, 4) 2224 FIELD(ID_AA64MMFR0, ECV, 60, 4) 2225 2226 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 2227 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 2228 FIELD(ID_AA64MMFR1, VH, 8, 4) 2229 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 2230 FIELD(ID_AA64MMFR1, LO, 16, 4) 2231 FIELD(ID_AA64MMFR1, PAN, 20, 4) 2232 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 2233 FIELD(ID_AA64MMFR1, XNX, 28, 4) 2234 FIELD(ID_AA64MMFR1, TWED, 32, 4) 2235 FIELD(ID_AA64MMFR1, ETS, 36, 4) 2236 FIELD(ID_AA64MMFR1, HCX, 40, 4) 2237 FIELD(ID_AA64MMFR1, AFP, 44, 4) 2238 FIELD(ID_AA64MMFR1, NTLBPA, 48, 4) 2239 FIELD(ID_AA64MMFR1, TIDCP1, 52, 4) 2240 FIELD(ID_AA64MMFR1, CMOW, 56, 4) 2241 2242 FIELD(ID_AA64MMFR2, CNP, 0, 4) 2243 FIELD(ID_AA64MMFR2, UAO, 4, 4) 2244 FIELD(ID_AA64MMFR2, LSM, 8, 4) 2245 FIELD(ID_AA64MMFR2, IESB, 12, 4) 2246 FIELD(ID_AA64MMFR2, VARANGE, 16, 4) 2247 FIELD(ID_AA64MMFR2, CCIDX, 20, 4) 2248 FIELD(ID_AA64MMFR2, NV, 24, 4) 2249 FIELD(ID_AA64MMFR2, ST, 28, 4) 2250 FIELD(ID_AA64MMFR2, AT, 32, 4) 2251 FIELD(ID_AA64MMFR2, IDS, 36, 4) 2252 FIELD(ID_AA64MMFR2, FWB, 40, 4) 2253 FIELD(ID_AA64MMFR2, TTL, 48, 4) 2254 FIELD(ID_AA64MMFR2, BBM, 52, 4) 2255 FIELD(ID_AA64MMFR2, EVT, 56, 4) 2256 FIELD(ID_AA64MMFR2, E0PD, 60, 4) 2257 2258 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) 2259 FIELD(ID_AA64DFR0, TRACEVER, 4, 4) 2260 FIELD(ID_AA64DFR0, PMUVER, 8, 4) 2261 FIELD(ID_AA64DFR0, BRPS, 12, 4) 2262 FIELD(ID_AA64DFR0, WRPS, 20, 4) 2263 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) 2264 FIELD(ID_AA64DFR0, PMSVER, 32, 4) 2265 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) 2266 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) 2267 FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4) 2268 FIELD(ID_AA64DFR0, MTPMU, 48, 4) 2269 FIELD(ID_AA64DFR0, BRBE, 52, 4) 2270 FIELD(ID_AA64DFR0, HPMN0, 60, 4) 2271 2272 FIELD(ID_AA64ZFR0, SVEVER, 0, 4) 2273 FIELD(ID_AA64ZFR0, AES, 4, 4) 2274 FIELD(ID_AA64ZFR0, BITPERM, 16, 4) 2275 FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4) 2276 FIELD(ID_AA64ZFR0, SHA3, 32, 4) 2277 FIELD(ID_AA64ZFR0, SM4, 40, 4) 2278 FIELD(ID_AA64ZFR0, I8MM, 44, 4) 2279 FIELD(ID_AA64ZFR0, F32MM, 52, 4) 2280 FIELD(ID_AA64ZFR0, F64MM, 56, 4) 2281 2282 FIELD(ID_AA64SMFR0, F32F32, 32, 1) 2283 FIELD(ID_AA64SMFR0, B16F32, 34, 1) 2284 FIELD(ID_AA64SMFR0, F16F32, 35, 1) 2285 FIELD(ID_AA64SMFR0, I8I32, 36, 4) 2286 FIELD(ID_AA64SMFR0, F64F64, 48, 1) 2287 FIELD(ID_AA64SMFR0, I16I64, 52, 4) 2288 FIELD(ID_AA64SMFR0, SMEVER, 56, 4) 2289 FIELD(ID_AA64SMFR0, FA64, 63, 1) 2290 2291 FIELD(ID_DFR0, COPDBG, 0, 4) 2292 FIELD(ID_DFR0, COPSDBG, 4, 4) 2293 FIELD(ID_DFR0, MMAPDBG, 8, 4) 2294 FIELD(ID_DFR0, COPTRC, 12, 4) 2295 FIELD(ID_DFR0, MMAPTRC, 16, 4) 2296 FIELD(ID_DFR0, MPROFDBG, 20, 4) 2297 FIELD(ID_DFR0, PERFMON, 24, 4) 2298 FIELD(ID_DFR0, TRACEFILT, 28, 4) 2299 2300 FIELD(ID_DFR1, MTPMU, 0, 4) 2301 FIELD(ID_DFR1, HPMN0, 4, 4) 2302 2303 FIELD(DBGDIDR, SE_IMP, 12, 1) 2304 FIELD(DBGDIDR, NSUHD_IMP, 14, 1) 2305 FIELD(DBGDIDR, VERSION, 16, 4) 2306 FIELD(DBGDIDR, CTX_CMPS, 20, 4) 2307 FIELD(DBGDIDR, BRPS, 24, 4) 2308 FIELD(DBGDIDR, WRPS, 28, 4) 2309 2310 FIELD(DBGDEVID, PCSAMPLE, 0, 4) 2311 FIELD(DBGDEVID, WPADDRMASK, 4, 4) 2312 FIELD(DBGDEVID, BPADDRMASK, 8, 4) 2313 FIELD(DBGDEVID, VECTORCATCH, 12, 4) 2314 FIELD(DBGDEVID, VIRTEXTNS, 16, 4) 2315 FIELD(DBGDEVID, DOUBLELOCK, 20, 4) 2316 FIELD(DBGDEVID, AUXREGS, 24, 4) 2317 FIELD(DBGDEVID, CIDMASK, 28, 4) 2318 2319 FIELD(MVFR0, SIMDREG, 0, 4) 2320 FIELD(MVFR0, FPSP, 4, 4) 2321 FIELD(MVFR0, FPDP, 8, 4) 2322 FIELD(MVFR0, FPTRAP, 12, 4) 2323 FIELD(MVFR0, FPDIVIDE, 16, 4) 2324 FIELD(MVFR0, FPSQRT, 20, 4) 2325 FIELD(MVFR0, FPSHVEC, 24, 4) 2326 FIELD(MVFR0, FPROUND, 28, 4) 2327 2328 FIELD(MVFR1, FPFTZ, 0, 4) 2329 FIELD(MVFR1, FPDNAN, 4, 4) 2330 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */ 2331 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */ 2332 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */ 2333 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */ 2334 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */ 2335 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */ 2336 FIELD(MVFR1, FPHP, 24, 4) 2337 FIELD(MVFR1, SIMDFMAC, 28, 4) 2338 2339 FIELD(MVFR2, SIMDMISC, 0, 4) 2340 FIELD(MVFR2, FPMISC, 4, 4) 2341 2342 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 2343 2344 /* If adding a feature bit which corresponds to a Linux ELF 2345 * HWCAP bit, remember to update the feature-bit-to-hwcap 2346 * mapping in linux-user/elfload.c:get_elf_hwcap(). 2347 */ 2348 enum arm_features { 2349 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 2350 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 2351 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 2352 ARM_FEATURE_V6, 2353 ARM_FEATURE_V6K, 2354 ARM_FEATURE_V7, 2355 ARM_FEATURE_THUMB2, 2356 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 2357 ARM_FEATURE_NEON, 2358 ARM_FEATURE_M, /* Microcontroller profile. */ 2359 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 2360 ARM_FEATURE_THUMB2EE, 2361 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 2362 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 2363 ARM_FEATURE_V4T, 2364 ARM_FEATURE_V5, 2365 ARM_FEATURE_STRONGARM, 2366 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 2367 ARM_FEATURE_GENERIC_TIMER, 2368 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 2369 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 2370 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 2371 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 2372 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 2373 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 2374 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 2375 ARM_FEATURE_V8, 2376 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 2377 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 2378 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 2379 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 2380 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 2381 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 2382 ARM_FEATURE_PMU, /* has PMU support */ 2383 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 2384 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 2385 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 2386 ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ 2387 }; 2388 2389 static inline int arm_feature(CPUARMState *env, int feature) 2390 { 2391 return (env->features & (1ULL << feature)) != 0; 2392 } 2393 2394 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); 2395 2396 #if !defined(CONFIG_USER_ONLY) 2397 /* 2398 * Return true if exception levels below EL3 are in secure state, 2399 * or would be following an exception return to that level. 2400 * Unlike arm_is_secure() (which is always a question about the 2401 * _current_ state of the CPU) this doesn't care about the current 2402 * EL or mode. 2403 */ 2404 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2405 { 2406 assert(!arm_feature(env, ARM_FEATURE_M)); 2407 if (arm_feature(env, ARM_FEATURE_EL3)) { 2408 return !(env->cp15.scr_el3 & SCR_NS); 2409 } else { 2410 /* If EL3 is not supported then the secure state is implementation 2411 * defined, in which case QEMU defaults to non-secure. 2412 */ 2413 return false; 2414 } 2415 } 2416 2417 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 2418 static inline bool arm_is_el3_or_mon(CPUARMState *env) 2419 { 2420 assert(!arm_feature(env, ARM_FEATURE_M)); 2421 if (arm_feature(env, ARM_FEATURE_EL3)) { 2422 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 2423 /* CPU currently in AArch64 state and EL3 */ 2424 return true; 2425 } else if (!is_a64(env) && 2426 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 2427 /* CPU currently in AArch32 state and monitor mode */ 2428 return true; 2429 } 2430 } 2431 return false; 2432 } 2433 2434 /* Return true if the processor is in secure state */ 2435 static inline bool arm_is_secure(CPUARMState *env) 2436 { 2437 if (arm_feature(env, ARM_FEATURE_M)) { 2438 return env->v7m.secure; 2439 } 2440 if (arm_is_el3_or_mon(env)) { 2441 return true; 2442 } 2443 return arm_is_secure_below_el3(env); 2444 } 2445 2446 /* 2447 * Return true if the current security state has AArch64 EL2 or AArch32 Hyp. 2448 * This corresponds to the pseudocode EL2Enabled() 2449 */ 2450 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, bool secure) 2451 { 2452 return arm_feature(env, ARM_FEATURE_EL2) 2453 && (!secure || (env->cp15.scr_el3 & SCR_EEL2)); 2454 } 2455 2456 static inline bool arm_is_el2_enabled(CPUARMState *env) 2457 { 2458 return arm_is_el2_enabled_secstate(env, arm_is_secure_below_el3(env)); 2459 } 2460 2461 #else 2462 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2463 { 2464 return false; 2465 } 2466 2467 static inline bool arm_is_secure(CPUARMState *env) 2468 { 2469 return false; 2470 } 2471 2472 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, bool secure) 2473 { 2474 return false; 2475 } 2476 2477 static inline bool arm_is_el2_enabled(CPUARMState *env) 2478 { 2479 return false; 2480 } 2481 #endif 2482 2483 /** 2484 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 2485 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 2486 * "for all purposes other than a direct read or write access of HCR_EL2." 2487 * Not included here is HCR_RW. 2488 */ 2489 uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure); 2490 uint64_t arm_hcr_el2_eff(CPUARMState *env); 2491 uint64_t arm_hcrx_el2_eff(CPUARMState *env); 2492 2493 /* Return true if the specified exception level is running in AArch64 state. */ 2494 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 2495 { 2496 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 2497 * and if we're not in EL0 then the state of EL0 isn't well defined.) 2498 */ 2499 assert(el >= 1 && el <= 3); 2500 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 2501 2502 /* The highest exception level is always at the maximum supported 2503 * register width, and then lower levels have a register width controlled 2504 * by bits in the SCR or HCR registers. 2505 */ 2506 if (el == 3) { 2507 return aa64; 2508 } 2509 2510 if (arm_feature(env, ARM_FEATURE_EL3) && 2511 ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) { 2512 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 2513 } 2514 2515 if (el == 2) { 2516 return aa64; 2517 } 2518 2519 if (arm_is_el2_enabled(env)) { 2520 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 2521 } 2522 2523 return aa64; 2524 } 2525 2526 /* Function for determing whether guest cp register reads and writes should 2527 * access the secure or non-secure bank of a cp register. When EL3 is 2528 * operating in AArch32 state, the NS-bit determines whether the secure 2529 * instance of a cp register should be used. When EL3 is AArch64 (or if 2530 * it doesn't exist at all) then there is no register banking, and all 2531 * accesses are to the non-secure version. 2532 */ 2533 static inline bool access_secure_reg(CPUARMState *env) 2534 { 2535 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 2536 !arm_el_is_aa64(env, 3) && 2537 !(env->cp15.scr_el3 & SCR_NS)); 2538 2539 return ret; 2540 } 2541 2542 /* Macros for accessing a specified CP register bank */ 2543 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 2544 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 2545 2546 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 2547 do { \ 2548 if (_secure) { \ 2549 (_env)->cp15._regname##_s = (_val); \ 2550 } else { \ 2551 (_env)->cp15._regname##_ns = (_val); \ 2552 } \ 2553 } while (0) 2554 2555 /* Macros for automatically accessing a specific CP register bank depending on 2556 * the current secure state of the system. These macros are not intended for 2557 * supporting instruction translation reads/writes as these are dependent 2558 * solely on the SCR.NS bit and not the mode. 2559 */ 2560 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 2561 A32_BANKED_REG_GET((_env), _regname, \ 2562 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 2563 2564 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 2565 A32_BANKED_REG_SET((_env), _regname, \ 2566 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 2567 (_val)) 2568 2569 void arm_cpu_list(void); 2570 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 2571 uint32_t cur_el, bool secure); 2572 2573 /* Return the highest implemented Exception Level */ 2574 static inline int arm_highest_el(CPUARMState *env) 2575 { 2576 if (arm_feature(env, ARM_FEATURE_EL3)) { 2577 return 3; 2578 } 2579 if (arm_feature(env, ARM_FEATURE_EL2)) { 2580 return 2; 2581 } 2582 return 1; 2583 } 2584 2585 /* Return true if a v7M CPU is in Handler mode */ 2586 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2587 { 2588 return env->v7m.exception != 0; 2589 } 2590 2591 /* Return the current Exception Level (as per ARMv8; note that this differs 2592 * from the ARMv7 Privilege Level). 2593 */ 2594 static inline int arm_current_el(CPUARMState *env) 2595 { 2596 if (arm_feature(env, ARM_FEATURE_M)) { 2597 return arm_v7m_is_handler_mode(env) || 2598 !(env->v7m.control[env->v7m.secure] & 1); 2599 } 2600 2601 if (is_a64(env)) { 2602 return extract32(env->pstate, 2, 2); 2603 } 2604 2605 switch (env->uncached_cpsr & 0x1f) { 2606 case ARM_CPU_MODE_USR: 2607 return 0; 2608 case ARM_CPU_MODE_HYP: 2609 return 2; 2610 case ARM_CPU_MODE_MON: 2611 return 3; 2612 default: 2613 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2614 /* If EL3 is 32-bit then all secure privileged modes run in 2615 * EL3 2616 */ 2617 return 3; 2618 } 2619 2620 return 1; 2621 } 2622 } 2623 2624 /** 2625 * write_list_to_cpustate 2626 * @cpu: ARMCPU 2627 * 2628 * For each register listed in the ARMCPU cpreg_indexes list, write 2629 * its value from the cpreg_values list into the ARMCPUState structure. 2630 * This updates TCG's working data structures from KVM data or 2631 * from incoming migration state. 2632 * 2633 * Returns: true if all register values were updated correctly, 2634 * false if some register was unknown or could not be written. 2635 * Note that we do not stop early on failure -- we will attempt 2636 * writing all registers in the list. 2637 */ 2638 bool write_list_to_cpustate(ARMCPU *cpu); 2639 2640 /** 2641 * write_cpustate_to_list: 2642 * @cpu: ARMCPU 2643 * @kvm_sync: true if this is for syncing back to KVM 2644 * 2645 * For each register listed in the ARMCPU cpreg_indexes list, write 2646 * its value from the ARMCPUState structure into the cpreg_values list. 2647 * This is used to copy info from TCG's working data structures into 2648 * KVM or for outbound migration. 2649 * 2650 * @kvm_sync is true if we are doing this in order to sync the 2651 * register state back to KVM. In this case we will only update 2652 * values in the list if the previous list->cpustate sync actually 2653 * successfully wrote the CPU state. Otherwise we will keep the value 2654 * that is in the list. 2655 * 2656 * Returns: true if all register values were read correctly, 2657 * false if some register was unknown or could not be read. 2658 * Note that we do not stop early on failure -- we will attempt 2659 * reading all registers in the list. 2660 */ 2661 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); 2662 2663 #define ARM_CPUID_TI915T 0x54029152 2664 #define ARM_CPUID_TI925T 0x54029252 2665 2666 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU 2667 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) 2668 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2669 2670 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU 2671 2672 #define cpu_list arm_cpu_list 2673 2674 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2675 * 2676 * If EL3 is 64-bit: 2677 * + NonSecure EL1 & 0 stage 1 2678 * + NonSecure EL1 & 0 stage 2 2679 * + NonSecure EL2 2680 * + NonSecure EL2 & 0 (ARMv8.1-VHE) 2681 * + Secure EL1 & 0 2682 * + Secure EL3 2683 * If EL3 is 32-bit: 2684 * + NonSecure PL1 & 0 stage 1 2685 * + NonSecure PL1 & 0 stage 2 2686 * + NonSecure PL2 2687 * + Secure PL0 2688 * + Secure PL1 2689 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2690 * 2691 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2692 * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes, 2693 * because they may differ in access permissions even if the VA->PA map is 2694 * the same 2695 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2696 * translation, which means that we have one mmu_idx that deals with two 2697 * concatenated translation regimes [this sort of combined s1+2 TLB is 2698 * architecturally permitted] 2699 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2700 * handling via the TLB. The only way to do a stage 1 translation without 2701 * the immediate stage 2 translation is via the ATS or AT system insns, 2702 * which can be slow-pathed and always do a page table walk. 2703 * The only use of stage 2 translations is either as part of an s1+2 2704 * lookup or when loading the descriptors during a stage 1 page table walk, 2705 * and in both those cases we don't use the TLB. 2706 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2707 * translation regimes, because they map reasonably well to each other 2708 * and they can't both be active at the same time. 2709 * 5. we want to be able to use the TLB for accesses done as part of a 2710 * stage1 page table walk, rather than having to walk the stage2 page 2711 * table over and over. 2712 * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access 2713 * Never (PAN) bit within PSTATE. 2714 * 7. we fold together the secure and non-secure regimes for A-profile, 2715 * because there are no banked system registers for aarch64, so the 2716 * process of switching between secure and non-secure is 2717 * already heavyweight. 2718 * 2719 * This gives us the following list of cases: 2720 * 2721 * EL0 EL1&0 stage 1+2 (aka NS PL0) 2722 * EL1 EL1&0 stage 1+2 (aka NS PL1) 2723 * EL1 EL1&0 stage 1+2 +PAN 2724 * EL0 EL2&0 2725 * EL2 EL2&0 2726 * EL2 EL2&0 +PAN 2727 * EL2 (aka NS PL2) 2728 * EL3 (aka S PL1) 2729 * Physical (NS & S) 2730 * Stage2 (NS & S) 2731 * 2732 * for a total of 12 different mmu_idx. 2733 * 2734 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2735 * as A profile. They only need to distinguish EL0 and EL1 (and 2736 * EL2 if we ever model a Cortex-R52). 2737 * 2738 * M profile CPUs are rather different as they do not have a true MMU. 2739 * They have the following different MMU indexes: 2740 * User 2741 * Privileged 2742 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2743 * Privileged, execution priority negative (ditto) 2744 * If the CPU supports the v8M Security Extension then there are also: 2745 * Secure User 2746 * Secure Privileged 2747 * Secure User, execution priority negative 2748 * Secure Privileged, execution priority negative 2749 * 2750 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2751 * are not quite the same -- different CPU types (most notably M profile 2752 * vs A/R profile) would like to use MMU indexes with different semantics, 2753 * but since we don't ever need to use all of those in a single CPU we 2754 * can avoid having to set NB_MMU_MODES to "total number of A profile MMU 2755 * modes + total number of M profile MMU modes". The lower bits of 2756 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2757 * the same for any particular CPU. 2758 * Variables of type ARMMUIdx are always full values, and the core 2759 * index values are in variables of type 'int'. 2760 * 2761 * Our enumeration includes at the end some entries which are not "true" 2762 * mmu_idx values in that they don't have corresponding TLBs and are only 2763 * valid for doing slow path page table walks. 2764 * 2765 * The constant names here are patterned after the general style of the names 2766 * of the AT/ATS operations. 2767 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2768 * For M profile we arrange them to have a bit for priv, a bit for negpri 2769 * and a bit for secure. 2770 */ 2771 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2772 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2773 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2774 2775 /* Meanings of the bits for M profile mmu idx values */ 2776 #define ARM_MMU_IDX_M_PRIV 0x1 2777 #define ARM_MMU_IDX_M_NEGPRI 0x2 2778 #define ARM_MMU_IDX_M_S 0x4 /* Secure */ 2779 2780 #define ARM_MMU_IDX_TYPE_MASK \ 2781 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB) 2782 #define ARM_MMU_IDX_COREIDX_MASK 0xf 2783 2784 typedef enum ARMMMUIdx { 2785 /* 2786 * A-profile. 2787 */ 2788 ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A, 2789 ARMMMUIdx_E20_0 = 1 | ARM_MMU_IDX_A, 2790 ARMMMUIdx_E10_1 = 2 | ARM_MMU_IDX_A, 2791 ARMMMUIdx_E20_2 = 3 | ARM_MMU_IDX_A, 2792 ARMMMUIdx_E10_1_PAN = 4 | ARM_MMU_IDX_A, 2793 ARMMMUIdx_E20_2_PAN = 5 | ARM_MMU_IDX_A, 2794 ARMMMUIdx_E2 = 6 | ARM_MMU_IDX_A, 2795 ARMMMUIdx_E3 = 7 | ARM_MMU_IDX_A, 2796 2797 /* TLBs with 1-1 mapping to the physical address spaces. */ 2798 ARMMMUIdx_Phys_NS = 8 | ARM_MMU_IDX_A, 2799 ARMMMUIdx_Phys_S = 9 | ARM_MMU_IDX_A, 2800 2801 /* 2802 * Used for second stage of an S12 page table walk, or for descriptor 2803 * loads during first stage of an S1 page table walk. Note that both 2804 * are in use simultaneously for SecureEL2: the security state for 2805 * the S2 ptw is selected by the NS bit from the S1 ptw. 2806 */ 2807 ARMMMUIdx_Stage2 = 10 | ARM_MMU_IDX_A, 2808 ARMMMUIdx_Stage2_S = 11 | ARM_MMU_IDX_A, 2809 2810 /* 2811 * These are not allocated TLBs and are used only for AT system 2812 * instructions or for the first stage of an S12 page table walk. 2813 */ 2814 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, 2815 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, 2816 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB, 2817 2818 /* 2819 * M-profile. 2820 */ 2821 ARMMMUIdx_MUser = ARM_MMU_IDX_M, 2822 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV, 2823 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI, 2824 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI, 2825 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S, 2826 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S, 2827 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S, 2828 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S, 2829 } ARMMMUIdx; 2830 2831 /* 2832 * Bit macros for the core-mmu-index values for each index, 2833 * for use when calling tlb_flush_by_mmuidx() and friends. 2834 */ 2835 #define TO_CORE_BIT(NAME) \ 2836 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK) 2837 2838 typedef enum ARMMMUIdxBit { 2839 TO_CORE_BIT(E10_0), 2840 TO_CORE_BIT(E20_0), 2841 TO_CORE_BIT(E10_1), 2842 TO_CORE_BIT(E10_1_PAN), 2843 TO_CORE_BIT(E2), 2844 TO_CORE_BIT(E20_2), 2845 TO_CORE_BIT(E20_2_PAN), 2846 TO_CORE_BIT(E3), 2847 TO_CORE_BIT(Stage2), 2848 TO_CORE_BIT(Stage2_S), 2849 2850 TO_CORE_BIT(MUser), 2851 TO_CORE_BIT(MPriv), 2852 TO_CORE_BIT(MUserNegPri), 2853 TO_CORE_BIT(MPrivNegPri), 2854 TO_CORE_BIT(MSUser), 2855 TO_CORE_BIT(MSPriv), 2856 TO_CORE_BIT(MSUserNegPri), 2857 TO_CORE_BIT(MSPrivNegPri), 2858 } ARMMMUIdxBit; 2859 2860 #undef TO_CORE_BIT 2861 2862 #define MMU_USER_IDX 0 2863 2864 /* Indexes used when registering address spaces with cpu_address_space_init */ 2865 typedef enum ARMASIdx { 2866 ARMASIdx_NS = 0, 2867 ARMASIdx_S = 1, 2868 ARMASIdx_TagNS = 2, 2869 ARMASIdx_TagS = 3, 2870 } ARMASIdx; 2871 2872 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 2873 { 2874 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 2875 * CSSELR is RAZ/WI. 2876 */ 2877 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 2878 } 2879 2880 static inline bool arm_sctlr_b(CPUARMState *env) 2881 { 2882 return 2883 /* We need not implement SCTLR.ITD in user-mode emulation, so 2884 * let linux-user ignore the fact that it conflicts with SCTLR_B. 2885 * This lets people run BE32 binaries with "-cpu any". 2886 */ 2887 #ifndef CONFIG_USER_ONLY 2888 !arm_feature(env, ARM_FEATURE_V7) && 2889 #endif 2890 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 2891 } 2892 2893 uint64_t arm_sctlr(CPUARMState *env, int el); 2894 2895 static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, 2896 bool sctlr_b) 2897 { 2898 #ifdef CONFIG_USER_ONLY 2899 /* 2900 * In system mode, BE32 is modelled in line with the 2901 * architecture (as word-invariant big-endianness), where loads 2902 * and stores are done little endian but from addresses which 2903 * are adjusted by XORing with the appropriate constant. So the 2904 * endianness to use for the raw data access is not affected by 2905 * SCTLR.B. 2906 * In user mode, however, we model BE32 as byte-invariant 2907 * big-endianness (because user-only code cannot tell the 2908 * difference), and so we need to use a data access endianness 2909 * that depends on SCTLR.B. 2910 */ 2911 if (sctlr_b) { 2912 return true; 2913 } 2914 #endif 2915 /* In 32bit endianness is determined by looking at CPSR's E bit */ 2916 return env->uncached_cpsr & CPSR_E; 2917 } 2918 2919 static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr) 2920 { 2921 return sctlr & (el ? SCTLR_EE : SCTLR_E0E); 2922 } 2923 2924 /* Return true if the processor is in big-endian mode. */ 2925 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 2926 { 2927 if (!is_a64(env)) { 2928 return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); 2929 } else { 2930 int cur_el = arm_current_el(env); 2931 uint64_t sctlr = arm_sctlr(env, cur_el); 2932 return arm_cpu_data_is_big_endian_a64(cur_el, sctlr); 2933 } 2934 } 2935 2936 #include "exec/cpu-all.h" 2937 2938 /* 2939 * We have more than 32-bits worth of state per TB, so we split the data 2940 * between tb->flags and tb->cs_base, which is otherwise unused for ARM. 2941 * We collect these two parts in CPUARMTBFlags where they are named 2942 * flags and flags2 respectively. 2943 * 2944 * The flags that are shared between all execution modes, TBFLAG_ANY, 2945 * are stored in flags. The flags that are specific to a given mode 2946 * are stores in flags2. Since cs_base is sized on the configured 2947 * address size, flags2 always has 64-bits for A64, and a minimum of 2948 * 32-bits for A32 and M32. 2949 * 2950 * The bits for 32-bit A-profile and M-profile partially overlap: 2951 * 2952 * 31 23 11 10 0 2953 * +-------------+----------+----------------+ 2954 * | | | TBFLAG_A32 | 2955 * | TBFLAG_AM32 | +-----+----------+ 2956 * | | |TBFLAG_M32| 2957 * +-------------+----------------+----------+ 2958 * 31 23 6 5 0 2959 * 2960 * Unless otherwise noted, these bits are cached in env->hflags. 2961 */ 2962 FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1) 2963 FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1) 2964 FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1) /* Not cached. */ 2965 FIELD(TBFLAG_ANY, BE_DATA, 3, 1) 2966 FIELD(TBFLAG_ANY, MMUIDX, 4, 4) 2967 /* Target EL if we take a floating-point-disabled exception */ 2968 FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) 2969 /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ 2970 FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1) 2971 FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1) 2972 FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1) 2973 FIELD(TBFLAG_ANY, FGT_SVC, 13, 1) 2974 2975 /* 2976 * Bit usage when in AArch32 state, both A- and M-profile. 2977 */ 2978 FIELD(TBFLAG_AM32, CONDEXEC, 24, 8) /* Not cached. */ 2979 FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cached. */ 2980 2981 /* 2982 * Bit usage when in AArch32 state, for A-profile only. 2983 */ 2984 FIELD(TBFLAG_A32, VECLEN, 0, 3) /* Not cached. */ 2985 FIELD(TBFLAG_A32, VECSTRIDE, 3, 2) /* Not cached. */ 2986 /* 2987 * We store the bottom two bits of the CPAR as TB flags and handle 2988 * checks on the other bits at runtime. This shares the same bits as 2989 * VECSTRIDE, which is OK as no XScale CPU has VFP. 2990 * Not cached, because VECLEN+VECSTRIDE are not cached. 2991 */ 2992 FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2) 2993 FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ 2994 FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */ 2995 FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1) 2996 /* 2997 * Indicates whether cp register reads and writes by guest code should access 2998 * the secure or nonsecure bank of banked registers; note that this is not 2999 * the same thing as the current security state of the processor! 3000 */ 3001 FIELD(TBFLAG_A32, NS, 10, 1) 3002 /* 3003 * Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. 3004 * This requires an SME trap from AArch32 mode when using NEON. 3005 */ 3006 FIELD(TBFLAG_A32, SME_TRAP_NONSTREAMING, 11, 1) 3007 3008 /* 3009 * Bit usage when in AArch32 state, for M-profile only. 3010 */ 3011 /* Handler (ie not Thread) mode */ 3012 FIELD(TBFLAG_M32, HANDLER, 0, 1) 3013 /* Whether we should generate stack-limit checks */ 3014 FIELD(TBFLAG_M32, STACKCHECK, 1, 1) 3015 /* Set if FPCCR.LSPACT is set */ 3016 FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */ 3017 /* Set if we must create a new FP context */ 3018 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */ 3019 /* Set if FPCCR.S does not match current security state */ 3020 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */ 3021 /* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */ 3022 FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */ 3023 /* Set if in secure mode */ 3024 FIELD(TBFLAG_M32, SECURE, 6, 1) 3025 3026 /* 3027 * Bit usage when in AArch64 state 3028 */ 3029 FIELD(TBFLAG_A64, TBII, 0, 2) 3030 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3031 /* The current vector length, either NVL or SVL. */ 3032 FIELD(TBFLAG_A64, VL, 4, 4) 3033 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3034 FIELD(TBFLAG_A64, BT, 9, 1) 3035 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ 3036 FIELD(TBFLAG_A64, TBID, 12, 2) 3037 FIELD(TBFLAG_A64, UNPRIV, 14, 1) 3038 FIELD(TBFLAG_A64, ATA, 15, 1) 3039 FIELD(TBFLAG_A64, TCMA, 16, 2) 3040 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) 3041 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) 3042 FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2) 3043 FIELD(TBFLAG_A64, PSTATE_SM, 22, 1) 3044 FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) 3045 FIELD(TBFLAG_A64, SVL, 24, 4) 3046 /* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. */ 3047 FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1) 3048 FIELD(TBFLAG_A64, FGT_ERET, 29, 1) 3049 FIELD(TBFLAG_A64, NAA, 30, 1) 3050 3051 /* 3052 * Helpers for using the above. 3053 */ 3054 #define DP_TBFLAG_ANY(DST, WHICH, VAL) \ 3055 (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL)) 3056 #define DP_TBFLAG_A64(DST, WHICH, VAL) \ 3057 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A64, WHICH, VAL)) 3058 #define DP_TBFLAG_A32(DST, WHICH, VAL) \ 3059 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL)) 3060 #define DP_TBFLAG_M32(DST, WHICH, VAL) \ 3061 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL)) 3062 #define DP_TBFLAG_AM32(DST, WHICH, VAL) \ 3063 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL)) 3064 3065 #define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH) 3066 #define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A64, WHICH) 3067 #define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH) 3068 #define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH) 3069 #define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH) 3070 3071 /** 3072 * cpu_mmu_index: 3073 * @env: The cpu environment 3074 * @ifetch: True for code access, false for data access. 3075 * 3076 * Return the core mmu index for the current translation regime. 3077 * This function is used by generic TCG code paths. 3078 */ 3079 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) 3080 { 3081 return EX_TBFLAG_ANY(env->hflags, MMUIDX); 3082 } 3083 3084 /** 3085 * sve_vq 3086 * @env: the cpu context 3087 * 3088 * Return the VL cached within env->hflags, in units of quadwords. 3089 */ 3090 static inline int sve_vq(CPUARMState *env) 3091 { 3092 return EX_TBFLAG_A64(env->hflags, VL) + 1; 3093 } 3094 3095 /** 3096 * sme_vq 3097 * @env: the cpu context 3098 * 3099 * Return the SVL cached within env->hflags, in units of quadwords. 3100 */ 3101 static inline int sme_vq(CPUARMState *env) 3102 { 3103 return EX_TBFLAG_A64(env->hflags, SVL) + 1; 3104 } 3105 3106 static inline bool bswap_code(bool sctlr_b) 3107 { 3108 #ifdef CONFIG_USER_ONLY 3109 /* BE8 (SCTLR.B = 0, TARGET_BIG_ENDIAN = 1) is mixed endian. 3110 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_BIG_ENDIAN=0 3111 * would also end up as a mixed-endian mode with BE code, LE data. 3112 */ 3113 return 3114 #if TARGET_BIG_ENDIAN 3115 1 ^ 3116 #endif 3117 sctlr_b; 3118 #else 3119 /* All code access in ARM is little endian, and there are no loaders 3120 * doing swaps that need to be reversed 3121 */ 3122 return 0; 3123 #endif 3124 } 3125 3126 #ifdef CONFIG_USER_ONLY 3127 static inline bool arm_cpu_bswap_data(CPUARMState *env) 3128 { 3129 return 3130 #if TARGET_BIG_ENDIAN 3131 1 ^ 3132 #endif 3133 arm_cpu_data_is_big_endian(env); 3134 } 3135 #endif 3136 3137 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 3138 target_ulong *cs_base, uint32_t *flags); 3139 3140 enum { 3141 QEMU_PSCI_CONDUIT_DISABLED = 0, 3142 QEMU_PSCI_CONDUIT_SMC = 1, 3143 QEMU_PSCI_CONDUIT_HVC = 2, 3144 }; 3145 3146 #ifndef CONFIG_USER_ONLY 3147 /* Return the address space index to use for a memory access */ 3148 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3149 { 3150 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3151 } 3152 3153 /* Return the AddressSpace to use for a memory access 3154 * (which depends on whether the access is S or NS, and whether 3155 * the board gave us a separate AddressSpace for S accesses). 3156 */ 3157 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3158 { 3159 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3160 } 3161 #endif 3162 3163 /** 3164 * arm_register_pre_el_change_hook: 3165 * Register a hook function which will be called immediately before this 3166 * CPU changes exception level or mode. The hook function will be 3167 * passed a pointer to the ARMCPU and the opaque data pointer passed 3168 * to this function when the hook was registered. 3169 * 3170 * Note that if a pre-change hook is called, any registered post-change hooks 3171 * are guaranteed to subsequently be called. 3172 */ 3173 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3174 void *opaque); 3175 /** 3176 * arm_register_el_change_hook: 3177 * Register a hook function which will be called immediately after this 3178 * CPU changes exception level or mode. The hook function will be 3179 * passed a pointer to the ARMCPU and the opaque data pointer passed 3180 * to this function when the hook was registered. 3181 * 3182 * Note that any registered hooks registered here are guaranteed to be called 3183 * if pre-change hooks have been. 3184 */ 3185 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3186 *opaque); 3187 3188 /** 3189 * arm_rebuild_hflags: 3190 * Rebuild the cached TBFLAGS for arbitrary changed processor state. 3191 */ 3192 void arm_rebuild_hflags(CPUARMState *env); 3193 3194 /** 3195 * aa32_vfp_dreg: 3196 * Return a pointer to the Dn register within env in 32-bit mode. 3197 */ 3198 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3199 { 3200 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3201 } 3202 3203 /** 3204 * aa32_vfp_qreg: 3205 * Return a pointer to the Qn register within env in 32-bit mode. 3206 */ 3207 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3208 { 3209 return &env->vfp.zregs[regno].d[0]; 3210 } 3211 3212 /** 3213 * aa64_vfp_qreg: 3214 * Return a pointer to the Qn register within env in 64-bit mode. 3215 */ 3216 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3217 { 3218 return &env->vfp.zregs[regno].d[0]; 3219 } 3220 3221 /* Shared between translate-sve.c and sve_helper.c. */ 3222 extern const uint64_t pred_esz_masks[5]; 3223 3224 /* 3225 * AArch64 usage of the PAGE_TARGET_* bits for linux-user. 3226 * Note that with the Linux kernel, PROT_MTE may not be cleared by mprotect 3227 * mprotect but PROT_BTI may be cleared. C.f. the kernel's VM_ARCH_CLEAR. 3228 */ 3229 #define PAGE_BTI PAGE_TARGET_1 3230 #define PAGE_MTE PAGE_TARGET_2 3231 #define PAGE_TARGET_STICKY PAGE_MTE 3232 3233 /* We associate one allocation tag per 16 bytes, the minimum. */ 3234 #define LOG2_TAG_GRANULE 4 3235 #define TAG_GRANULE (1 << LOG2_TAG_GRANULE) 3236 3237 #ifdef CONFIG_USER_ONLY 3238 #define TARGET_PAGE_DATA_SIZE (TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1)) 3239 #endif 3240 3241 #ifdef TARGET_TAGGED_ADDRESSES 3242 /** 3243 * cpu_untagged_addr: 3244 * @cs: CPU context 3245 * @x: tagged address 3246 * 3247 * Remove any address tag from @x. This is explicitly related to the 3248 * linux syscall TIF_TAGGED_ADDR setting, not TBI in general. 3249 * 3250 * There should be a better place to put this, but we need this in 3251 * include/exec/cpu_ldst.h, and not some place linux-user specific. 3252 */ 3253 static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x) 3254 { 3255 ARMCPU *cpu = ARM_CPU(cs); 3256 if (cpu->env.tagged_addr_enable) { 3257 /* 3258 * TBI is enabled for userspace but not kernelspace addresses. 3259 * Only clear the tag if bit 55 is clear. 3260 */ 3261 x &= sextract64(x, 0, 56); 3262 } 3263 return x; 3264 } 3265 #endif 3266 3267 /* 3268 * Naming convention for isar_feature functions: 3269 * Functions which test 32-bit ID registers should have _aa32_ in 3270 * their name. Functions which test 64-bit ID registers should have 3271 * _aa64_ in their name. These must only be used in code where we 3272 * know for certain that the CPU has AArch32 or AArch64 respectively 3273 * or where the correct answer for a CPU which doesn't implement that 3274 * CPU state is "false" (eg when generating A32 or A64 code, if adding 3275 * system registers that are specific to that CPU state, for "should 3276 * we let this system register bit be set" tests where the 32-bit 3277 * flavour of the register doesn't have the bit, and so on). 3278 * Functions which simply ask "does this feature exist at all" have 3279 * _any_ in their name, and always return the logical OR of the _aa64_ 3280 * and the _aa32_ function. 3281 */ 3282 3283 /* 3284 * 32-bit feature tests via id registers. 3285 */ 3286 static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id) 3287 { 3288 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; 3289 } 3290 3291 static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id) 3292 { 3293 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; 3294 } 3295 3296 static inline bool isar_feature_aa32_lob(const ARMISARegisters *id) 3297 { 3298 /* (M-profile) low-overhead loops and branch future */ 3299 return FIELD_EX32(id->id_isar0, ID_ISAR0, CMPBRANCH) >= 3; 3300 } 3301 3302 static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id) 3303 { 3304 return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0; 3305 } 3306 3307 static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) 3308 { 3309 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0; 3310 } 3311 3312 static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id) 3313 { 3314 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1; 3315 } 3316 3317 static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id) 3318 { 3319 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0; 3320 } 3321 3322 static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id) 3323 { 3324 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0; 3325 } 3326 3327 static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id) 3328 { 3329 return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0; 3330 } 3331 3332 static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id) 3333 { 3334 return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0; 3335 } 3336 3337 static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id) 3338 { 3339 return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0; 3340 } 3341 3342 static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id) 3343 { 3344 return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0; 3345 } 3346 3347 static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) 3348 { 3349 return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0; 3350 } 3351 3352 static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id) 3353 { 3354 return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0; 3355 } 3356 3357 static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) 3358 { 3359 return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0; 3360 } 3361 3362 static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id) 3363 { 3364 return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0; 3365 } 3366 3367 static inline bool isar_feature_aa32_bf16(const ARMISARegisters *id) 3368 { 3369 return FIELD_EX32(id->id_isar6, ID_ISAR6, BF16) != 0; 3370 } 3371 3372 static inline bool isar_feature_aa32_i8mm(const ARMISARegisters *id) 3373 { 3374 return FIELD_EX32(id->id_isar6, ID_ISAR6, I8MM) != 0; 3375 } 3376 3377 static inline bool isar_feature_aa32_ras(const ARMISARegisters *id) 3378 { 3379 return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) != 0; 3380 } 3381 3382 static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id) 3383 { 3384 return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0; 3385 } 3386 3387 static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id) 3388 { 3389 /* 3390 * Return true if M-profile state handling insns 3391 * (VSCCLRM, CLRM, FPCTX access insns) are implemented 3392 */ 3393 return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >= 3; 3394 } 3395 3396 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) 3397 { 3398 /* Sadly this is encoded differently for A-profile and M-profile */ 3399 if (isar_feature_aa32_mprofile(id)) { 3400 return FIELD_EX32(id->mvfr1, MVFR1, FP16) > 0; 3401 } else { 3402 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3; 3403 } 3404 } 3405 3406 static inline bool isar_feature_aa32_mve(const ARMISARegisters *id) 3407 { 3408 /* 3409 * Return true if MVE is supported (either integer or floating point). 3410 * We must check for M-profile as the MVFR1 field means something 3411 * else for A-profile. 3412 */ 3413 return isar_feature_aa32_mprofile(id) && 3414 FIELD_EX32(id->mvfr1, MVFR1, MVE) > 0; 3415 } 3416 3417 static inline bool isar_feature_aa32_mve_fp(const ARMISARegisters *id) 3418 { 3419 /* 3420 * Return true if MVE is supported (either integer or floating point). 3421 * We must check for M-profile as the MVFR1 field means something 3422 * else for A-profile. 3423 */ 3424 return isar_feature_aa32_mprofile(id) && 3425 FIELD_EX32(id->mvfr1, MVFR1, MVE) >= 2; 3426 } 3427 3428 static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id) 3429 { 3430 /* 3431 * Return true if either VFP or SIMD is implemented. 3432 * In this case, a minimum of VFP w/ D0-D15. 3433 */ 3434 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0; 3435 } 3436 3437 static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id) 3438 { 3439 /* Return true if D16-D31 are implemented */ 3440 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2; 3441 } 3442 3443 static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id) 3444 { 3445 return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0; 3446 } 3447 3448 static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id) 3449 { 3450 /* Return true if CPU supports single precision floating point, VFPv2 */ 3451 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0; 3452 } 3453 3454 static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id) 3455 { 3456 /* Return true if CPU supports single precision floating point, VFPv3 */ 3457 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2; 3458 } 3459 3460 static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id) 3461 { 3462 /* Return true if CPU supports double precision floating point, VFPv2 */ 3463 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0; 3464 } 3465 3466 static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id) 3467 { 3468 /* Return true if CPU supports double precision floating point, VFPv3 */ 3469 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2; 3470 } 3471 3472 static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id) 3473 { 3474 return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id); 3475 } 3476 3477 /* 3478 * We always set the FP and SIMD FP16 fields to indicate identical 3479 * levels of support (assuming SIMD is implemented at all), so 3480 * we only need one set of accessors. 3481 */ 3482 static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id) 3483 { 3484 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0; 3485 } 3486 3487 static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id) 3488 { 3489 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1; 3490 } 3491 3492 /* 3493 * Note that this ID register field covers both VFP and Neon FMAC, 3494 * so should usually be tested in combination with some other 3495 * check that confirms the presence of whichever of VFP or Neon is 3496 * relevant, to avoid accidentally enabling a Neon feature on 3497 * a VFP-no-Neon core or vice-versa. 3498 */ 3499 static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id) 3500 { 3501 return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0; 3502 } 3503 3504 static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id) 3505 { 3506 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1; 3507 } 3508 3509 static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id) 3510 { 3511 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2; 3512 } 3513 3514 static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id) 3515 { 3516 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3; 3517 } 3518 3519 static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id) 3520 { 3521 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4; 3522 } 3523 3524 static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id) 3525 { 3526 return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >= 4; 3527 } 3528 3529 static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) 3530 { 3531 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0; 3532 } 3533 3534 static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id) 3535 { 3536 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2; 3537 } 3538 3539 static inline bool isar_feature_aa32_pmuv3p1(const ARMISARegisters *id) 3540 { 3541 /* 0xf means "non-standard IMPDEF PMU" */ 3542 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 && 3543 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3544 } 3545 3546 static inline bool isar_feature_aa32_pmuv3p4(const ARMISARegisters *id) 3547 { 3548 /* 0xf means "non-standard IMPDEF PMU" */ 3549 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 5 && 3550 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3551 } 3552 3553 static inline bool isar_feature_aa32_pmuv3p5(const ARMISARegisters *id) 3554 { 3555 /* 0xf means "non-standard IMPDEF PMU" */ 3556 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 6 && 3557 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3558 } 3559 3560 static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id) 3561 { 3562 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0; 3563 } 3564 3565 static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id) 3566 { 3567 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0; 3568 } 3569 3570 static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id) 3571 { 3572 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0; 3573 } 3574 3575 static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id) 3576 { 3577 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0; 3578 } 3579 3580 static inline bool isar_feature_aa32_half_evt(const ARMISARegisters *id) 3581 { 3582 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 1; 3583 } 3584 3585 static inline bool isar_feature_aa32_evt(const ARMISARegisters *id) 3586 { 3587 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 2; 3588 } 3589 3590 static inline bool isar_feature_aa32_dit(const ARMISARegisters *id) 3591 { 3592 return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0; 3593 } 3594 3595 static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id) 3596 { 3597 return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0; 3598 } 3599 3600 static inline bool isar_feature_aa32_debugv7p1(const ARMISARegisters *id) 3601 { 3602 return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 5; 3603 } 3604 3605 static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id) 3606 { 3607 return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 8; 3608 } 3609 3610 static inline bool isar_feature_aa32_doublelock(const ARMISARegisters *id) 3611 { 3612 return FIELD_EX32(id->dbgdevid, DBGDEVID, DOUBLELOCK) > 0; 3613 } 3614 3615 /* 3616 * 64-bit feature tests via id registers. 3617 */ 3618 static inline bool isar_feature_aa64_aes(const ARMISARegisters *id) 3619 { 3620 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0; 3621 } 3622 3623 static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id) 3624 { 3625 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1; 3626 } 3627 3628 static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id) 3629 { 3630 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0; 3631 } 3632 3633 static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id) 3634 { 3635 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0; 3636 } 3637 3638 static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id) 3639 { 3640 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1; 3641 } 3642 3643 static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id) 3644 { 3645 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0; 3646 } 3647 3648 static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id) 3649 { 3650 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0; 3651 } 3652 3653 static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) 3654 { 3655 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0; 3656 } 3657 3658 static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id) 3659 { 3660 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0; 3661 } 3662 3663 static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id) 3664 { 3665 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0; 3666 } 3667 3668 static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id) 3669 { 3670 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0; 3671 } 3672 3673 static inline bool isar_feature_aa64_dp(const ARMISARegisters *id) 3674 { 3675 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0; 3676 } 3677 3678 static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id) 3679 { 3680 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0; 3681 } 3682 3683 static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id) 3684 { 3685 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0; 3686 } 3687 3688 static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id) 3689 { 3690 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2; 3691 } 3692 3693 static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id) 3694 { 3695 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0; 3696 } 3697 3698 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) 3699 { 3700 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0; 3701 } 3702 3703 static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) 3704 { 3705 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0; 3706 } 3707 3708 static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) 3709 { 3710 /* 3711 * Return true if any form of pauth is enabled, as this 3712 * predicate controls migration of the 128-bit keys. 3713 */ 3714 return (id->id_aa64isar1 & 3715 (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) | 3716 FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) | 3717 FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) | 3718 FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0; 3719 } 3720 3721 static inline bool isar_feature_aa64_pauth_arch(const ARMISARegisters *id) 3722 { 3723 /* 3724 * Return true if pauth is enabled with the architected QARMA algorithm. 3725 * QEMU will always set APA+GPA to the same value. 3726 */ 3727 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0; 3728 } 3729 3730 static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id) 3731 { 3732 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2; 3733 } 3734 3735 static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id) 3736 { 3737 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) != 0; 3738 } 3739 3740 static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) 3741 { 3742 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0; 3743 } 3744 3745 static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id) 3746 { 3747 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0; 3748 } 3749 3750 static inline bool isar_feature_aa64_frint(const ARMISARegisters *id) 3751 { 3752 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0; 3753 } 3754 3755 static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id) 3756 { 3757 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) != 0; 3758 } 3759 3760 static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id) 3761 { 3762 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2; 3763 } 3764 3765 static inline bool isar_feature_aa64_bf16(const ARMISARegisters *id) 3766 { 3767 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) != 0; 3768 } 3769 3770 static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id) 3771 { 3772 /* We always set the AdvSIMD and FP fields identically. */ 3773 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf; 3774 } 3775 3776 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) 3777 { 3778 /* We always set the AdvSIMD and FP fields identically wrt FP16. */ 3779 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 3780 } 3781 3782 static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id) 3783 { 3784 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2; 3785 } 3786 3787 static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id) 3788 { 3789 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2; 3790 } 3791 3792 static inline bool isar_feature_aa64_aa32_el2(const ARMISARegisters *id) 3793 { 3794 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL2) >= 2; 3795 } 3796 3797 static inline bool isar_feature_aa64_ras(const ARMISARegisters *id) 3798 { 3799 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) != 0; 3800 } 3801 3802 static inline bool isar_feature_aa64_doublefault(const ARMISARegisters *id) 3803 { 3804 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) >= 2; 3805 } 3806 3807 static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) 3808 { 3809 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; 3810 } 3811 3812 static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id) 3813 { 3814 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) != 0; 3815 } 3816 3817 static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) 3818 { 3819 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0; 3820 } 3821 3822 static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) 3823 { 3824 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; 3825 } 3826 3827 static inline bool isar_feature_aa64_pan(const ARMISARegisters *id) 3828 { 3829 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0; 3830 } 3831 3832 static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id) 3833 { 3834 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2; 3835 } 3836 3837 static inline bool isar_feature_aa64_pan3(const ARMISARegisters *id) 3838 { 3839 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 3; 3840 } 3841 3842 static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id) 3843 { 3844 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HCX) != 0; 3845 } 3846 3847 static inline bool isar_feature_aa64_uao(const ARMISARegisters *id) 3848 { 3849 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0; 3850 } 3851 3852 static inline bool isar_feature_aa64_st(const ARMISARegisters *id) 3853 { 3854 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0; 3855 } 3856 3857 static inline bool isar_feature_aa64_lse2(const ARMISARegisters *id) 3858 { 3859 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, AT) != 0; 3860 } 3861 3862 static inline bool isar_feature_aa64_fwb(const ARMISARegisters *id) 3863 { 3864 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, FWB) != 0; 3865 } 3866 3867 static inline bool isar_feature_aa64_ids(const ARMISARegisters *id) 3868 { 3869 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, IDS) != 0; 3870 } 3871 3872 static inline bool isar_feature_aa64_half_evt(const ARMISARegisters *id) 3873 { 3874 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 1; 3875 } 3876 3877 static inline bool isar_feature_aa64_evt(const ARMISARegisters *id) 3878 { 3879 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 2; 3880 } 3881 3882 static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) 3883 { 3884 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; 3885 } 3886 3887 static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id) 3888 { 3889 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0; 3890 } 3891 3892 static inline bool isar_feature_aa64_mte(const ARMISARegisters *id) 3893 { 3894 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2; 3895 } 3896 3897 static inline bool isar_feature_aa64_sme(const ARMISARegisters *id) 3898 { 3899 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SME) != 0; 3900 } 3901 3902 static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id) 3903 { 3904 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 && 3905 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 3906 } 3907 3908 static inline bool isar_feature_aa64_pmuv3p4(const ARMISARegisters *id) 3909 { 3910 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 && 3911 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 3912 } 3913 3914 static inline bool isar_feature_aa64_pmuv3p5(const ARMISARegisters *id) 3915 { 3916 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 6 && 3917 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 3918 } 3919 3920 static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id) 3921 { 3922 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0; 3923 } 3924 3925 static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id) 3926 { 3927 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2; 3928 } 3929 3930 static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id) 3931 { 3932 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0; 3933 } 3934 3935 static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id) 3936 { 3937 return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1; 3938 } 3939 3940 static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *id) 3941 { 3942 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2); 3943 return t >= 3 || (t == 0 && isar_feature_aa64_tgran4_lpa2(id)); 3944 } 3945 3946 static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *id) 3947 { 3948 return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 2; 3949 } 3950 3951 static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id) 3952 { 3953 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2); 3954 return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id)); 3955 } 3956 3957 static inline bool isar_feature_aa64_tgran4(const ARMISARegisters *id) 3958 { 3959 return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 0; 3960 } 3961 3962 static inline bool isar_feature_aa64_tgran16(const ARMISARegisters *id) 3963 { 3964 return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 1; 3965 } 3966 3967 static inline bool isar_feature_aa64_tgran64(const ARMISARegisters *id) 3968 { 3969 return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64) >= 0; 3970 } 3971 3972 static inline bool isar_feature_aa64_tgran4_2(const ARMISARegisters *id) 3973 { 3974 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2); 3975 return t >= 2 || (t == 0 && isar_feature_aa64_tgran4(id)); 3976 } 3977 3978 static inline bool isar_feature_aa64_tgran16_2(const ARMISARegisters *id) 3979 { 3980 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2); 3981 return t >= 2 || (t == 0 && isar_feature_aa64_tgran16(id)); 3982 } 3983 3984 static inline bool isar_feature_aa64_tgran64_2(const ARMISARegisters *id) 3985 { 3986 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64_2); 3987 return t >= 2 || (t == 0 && isar_feature_aa64_tgran64(id)); 3988 } 3989 3990 static inline bool isar_feature_aa64_fgt(const ARMISARegisters *id) 3991 { 3992 return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, FGT) != 0; 3993 } 3994 3995 static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) 3996 { 3997 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0; 3998 } 3999 4000 static inline bool isar_feature_aa64_lva(const ARMISARegisters *id) 4001 { 4002 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) != 0; 4003 } 4004 4005 static inline bool isar_feature_aa64_e0pd(const ARMISARegisters *id) 4006 { 4007 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, E0PD) != 0; 4008 } 4009 4010 static inline bool isar_feature_aa64_hafs(const ARMISARegisters *id) 4011 { 4012 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) != 0; 4013 } 4014 4015 static inline bool isar_feature_aa64_hdbs(const ARMISARegisters *id) 4016 { 4017 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) >= 2; 4018 } 4019 4020 static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id) 4021 { 4022 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0; 4023 } 4024 4025 static inline bool isar_feature_aa64_dit(const ARMISARegisters *id) 4026 { 4027 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0; 4028 } 4029 4030 static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id) 4031 { 4032 int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2); 4033 if (key >= 2) { 4034 return true; /* FEAT_CSV2_2 */ 4035 } 4036 if (key == 1) { 4037 key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC); 4038 return key >= 2; /* FEAT_CSV2_1p2 */ 4039 } 4040 return false; 4041 } 4042 4043 static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id) 4044 { 4045 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0; 4046 } 4047 4048 static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id) 4049 { 4050 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >= 8; 4051 } 4052 4053 static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id) 4054 { 4055 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0; 4056 } 4057 4058 static inline bool isar_feature_aa64_sve2_aes(const ARMISARegisters *id) 4059 { 4060 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) != 0; 4061 } 4062 4063 static inline bool isar_feature_aa64_sve2_pmull128(const ARMISARegisters *id) 4064 { 4065 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) >= 2; 4066 } 4067 4068 static inline bool isar_feature_aa64_sve2_bitperm(const ARMISARegisters *id) 4069 { 4070 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BITPERM) != 0; 4071 } 4072 4073 static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id) 4074 { 4075 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BFLOAT16) != 0; 4076 } 4077 4078 static inline bool isar_feature_aa64_sve2_sha3(const ARMISARegisters *id) 4079 { 4080 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SHA3) != 0; 4081 } 4082 4083 static inline bool isar_feature_aa64_sve2_sm4(const ARMISARegisters *id) 4084 { 4085 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SM4) != 0; 4086 } 4087 4088 static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id) 4089 { 4090 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, I8MM) != 0; 4091 } 4092 4093 static inline bool isar_feature_aa64_sve_f32mm(const ARMISARegisters *id) 4094 { 4095 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F32MM) != 0; 4096 } 4097 4098 static inline bool isar_feature_aa64_sve_f64mm(const ARMISARegisters *id) 4099 { 4100 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F64MM) != 0; 4101 } 4102 4103 static inline bool isar_feature_aa64_sme_f64f64(const ARMISARegisters *id) 4104 { 4105 return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, F64F64); 4106 } 4107 4108 static inline bool isar_feature_aa64_sme_i16i64(const ARMISARegisters *id) 4109 { 4110 return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, I16I64) == 0xf; 4111 } 4112 4113 static inline bool isar_feature_aa64_sme_fa64(const ARMISARegisters *id) 4114 { 4115 return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, FA64); 4116 } 4117 4118 static inline bool isar_feature_aa64_doublelock(const ARMISARegisters *id) 4119 { 4120 return FIELD_SEX64(id->id_aa64dfr0, ID_AA64DFR0, DOUBLELOCK) >= 0; 4121 } 4122 4123 /* 4124 * Feature tests for "does this exist in either 32-bit or 64-bit?" 4125 */ 4126 static inline bool isar_feature_any_fp16(const ARMISARegisters *id) 4127 { 4128 return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id); 4129 } 4130 4131 static inline bool isar_feature_any_predinv(const ARMISARegisters *id) 4132 { 4133 return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id); 4134 } 4135 4136 static inline bool isar_feature_any_pmuv3p1(const ARMISARegisters *id) 4137 { 4138 return isar_feature_aa64_pmuv3p1(id) || isar_feature_aa32_pmuv3p1(id); 4139 } 4140 4141 static inline bool isar_feature_any_pmuv3p4(const ARMISARegisters *id) 4142 { 4143 return isar_feature_aa64_pmuv3p4(id) || isar_feature_aa32_pmuv3p4(id); 4144 } 4145 4146 static inline bool isar_feature_any_pmuv3p5(const ARMISARegisters *id) 4147 { 4148 return isar_feature_aa64_pmuv3p5(id) || isar_feature_aa32_pmuv3p5(id); 4149 } 4150 4151 static inline bool isar_feature_any_ccidx(const ARMISARegisters *id) 4152 { 4153 return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id); 4154 } 4155 4156 static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id) 4157 { 4158 return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id); 4159 } 4160 4161 static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id) 4162 { 4163 return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(id); 4164 } 4165 4166 static inline bool isar_feature_any_ras(const ARMISARegisters *id) 4167 { 4168 return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id); 4169 } 4170 4171 static inline bool isar_feature_any_half_evt(const ARMISARegisters *id) 4172 { 4173 return isar_feature_aa64_half_evt(id) || isar_feature_aa32_half_evt(id); 4174 } 4175 4176 static inline bool isar_feature_any_evt(const ARMISARegisters *id) 4177 { 4178 return isar_feature_aa64_evt(id) || isar_feature_aa32_evt(id); 4179 } 4180 4181 /* 4182 * Forward to the above feature tests given an ARMCPU pointer. 4183 */ 4184 #define cpu_isar_feature(name, cpu) \ 4185 ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); }) 4186 4187 #endif 4188