1 #include "qemu/osdep.h" 2 #include "trace.h" 3 #include "cpu.h" 4 #include "internals.h" 5 #include "exec/gdbstub.h" 6 #include "exec/helper-proto.h" 7 #include "qemu/host-utils.h" 8 #include "sysemu/arch_init.h" 9 #include "sysemu/sysemu.h" 10 #include "qemu/bitops.h" 11 #include "qemu/crc32c.h" 12 #include "exec/exec-all.h" 13 #include "exec/cpu_ldst.h" 14 #include "arm_ldst.h" 15 #include <zlib.h> /* For crc32 */ 16 #include "exec/semihost.h" 17 #include "sysemu/kvm.h" 18 19 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ 20 21 #ifndef CONFIG_USER_ONLY 22 static bool get_phys_addr(CPUARMState *env, target_ulong address, 23 int access_type, ARMMMUIdx mmu_idx, 24 hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, 25 target_ulong *page_size, uint32_t *fsr, 26 ARMMMUFaultInfo *fi); 27 28 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, 29 int access_type, ARMMMUIdx mmu_idx, 30 hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, 31 target_ulong *page_size_ptr, uint32_t *fsr, 32 ARMMMUFaultInfo *fi); 33 34 /* Definitions for the PMCCNTR and PMCR registers */ 35 #define PMCRD 0x8 36 #define PMCRC 0x4 37 #define PMCRE 0x1 38 #endif 39 40 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) 41 { 42 int nregs; 43 44 /* VFP data registers are always little-endian. */ 45 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; 46 if (reg < nregs) { 47 stfq_le_p(buf, env->vfp.regs[reg]); 48 return 8; 49 } 50 if (arm_feature(env, ARM_FEATURE_NEON)) { 51 /* Aliases for Q regs. */ 52 nregs += 16; 53 if (reg < nregs) { 54 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]); 55 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]); 56 return 16; 57 } 58 } 59 switch (reg - nregs) { 60 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4; 61 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4; 62 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4; 63 } 64 return 0; 65 } 66 67 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) 68 { 69 int nregs; 70 71 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; 72 if (reg < nregs) { 73 env->vfp.regs[reg] = ldfq_le_p(buf); 74 return 8; 75 } 76 if (arm_feature(env, ARM_FEATURE_NEON)) { 77 nregs += 16; 78 if (reg < nregs) { 79 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf); 80 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8); 81 return 16; 82 } 83 } 84 switch (reg - nregs) { 85 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4; 86 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4; 87 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4; 88 } 89 return 0; 90 } 91 92 static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) 93 { 94 switch (reg) { 95 case 0 ... 31: 96 /* 128 bit FP register */ 97 stfq_le_p(buf, env->vfp.regs[reg * 2]); 98 stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]); 99 return 16; 100 case 32: 101 /* FPSR */ 102 stl_p(buf, vfp_get_fpsr(env)); 103 return 4; 104 case 33: 105 /* FPCR */ 106 stl_p(buf, vfp_get_fpcr(env)); 107 return 4; 108 default: 109 return 0; 110 } 111 } 112 113 static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) 114 { 115 switch (reg) { 116 case 0 ... 31: 117 /* 128 bit FP register */ 118 env->vfp.regs[reg * 2] = ldfq_le_p(buf); 119 env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8); 120 return 16; 121 case 32: 122 /* FPSR */ 123 vfp_set_fpsr(env, ldl_p(buf)); 124 return 4; 125 case 33: 126 /* FPCR */ 127 vfp_set_fpcr(env, ldl_p(buf)); 128 return 4; 129 default: 130 return 0; 131 } 132 } 133 134 static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) 135 { 136 assert(ri->fieldoffset); 137 if (cpreg_field_is_64bit(ri)) { 138 return CPREG_FIELD64(env, ri); 139 } else { 140 return CPREG_FIELD32(env, ri); 141 } 142 } 143 144 static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, 145 uint64_t value) 146 { 147 assert(ri->fieldoffset); 148 if (cpreg_field_is_64bit(ri)) { 149 CPREG_FIELD64(env, ri) = value; 150 } else { 151 CPREG_FIELD32(env, ri) = value; 152 } 153 } 154 155 static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri) 156 { 157 return (char *)env + ri->fieldoffset; 158 } 159 160 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri) 161 { 162 /* Raw read of a coprocessor register (as needed for migration, etc). */ 163 if (ri->type & ARM_CP_CONST) { 164 return ri->resetvalue; 165 } else if (ri->raw_readfn) { 166 return ri->raw_readfn(env, ri); 167 } else if (ri->readfn) { 168 return ri->readfn(env, ri); 169 } else { 170 return raw_read(env, ri); 171 } 172 } 173 174 static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, 175 uint64_t v) 176 { 177 /* Raw write of a coprocessor register (as needed for migration, etc). 178 * Note that constant registers are treated as write-ignored; the 179 * caller should check for success by whether a readback gives the 180 * value written. 181 */ 182 if (ri->type & ARM_CP_CONST) { 183 return; 184 } else if (ri->raw_writefn) { 185 ri->raw_writefn(env, ri, v); 186 } else if (ri->writefn) { 187 ri->writefn(env, ri, v); 188 } else { 189 raw_write(env, ri, v); 190 } 191 } 192 193 static bool raw_accessors_invalid(const ARMCPRegInfo *ri) 194 { 195 /* Return true if the regdef would cause an assertion if you called 196 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a 197 * program bug for it not to have the NO_RAW flag). 198 * NB that returning false here doesn't necessarily mean that calling 199 * read/write_raw_cp_reg() is safe, because we can't distinguish "has 200 * read/write access functions which are safe for raw use" from "has 201 * read/write access functions which have side effects but has forgotten 202 * to provide raw access functions". 203 * The tests here line up with the conditions in read/write_raw_cp_reg() 204 * and assertions in raw_read()/raw_write(). 205 */ 206 if ((ri->type & ARM_CP_CONST) || 207 ri->fieldoffset || 208 ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) { 209 return false; 210 } 211 return true; 212 } 213 214 bool write_cpustate_to_list(ARMCPU *cpu) 215 { 216 /* Write the coprocessor state from cpu->env to the (index,value) list. */ 217 int i; 218 bool ok = true; 219 220 for (i = 0; i < cpu->cpreg_array_len; i++) { 221 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); 222 const ARMCPRegInfo *ri; 223 224 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); 225 if (!ri) { 226 ok = false; 227 continue; 228 } 229 if (ri->type & ARM_CP_NO_RAW) { 230 continue; 231 } 232 cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri); 233 } 234 return ok; 235 } 236 237 bool write_list_to_cpustate(ARMCPU *cpu) 238 { 239 int i; 240 bool ok = true; 241 242 for (i = 0; i < cpu->cpreg_array_len; i++) { 243 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); 244 uint64_t v = cpu->cpreg_values[i]; 245 const ARMCPRegInfo *ri; 246 247 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); 248 if (!ri) { 249 ok = false; 250 continue; 251 } 252 if (ri->type & ARM_CP_NO_RAW) { 253 continue; 254 } 255 /* Write value and confirm it reads back as written 256 * (to catch read-only registers and partially read-only 257 * registers where the incoming migration value doesn't match) 258 */ 259 write_raw_cp_reg(&cpu->env, ri, v); 260 if (read_raw_cp_reg(&cpu->env, ri) != v) { 261 ok = false; 262 } 263 } 264 return ok; 265 } 266 267 static void add_cpreg_to_list(gpointer key, gpointer opaque) 268 { 269 ARMCPU *cpu = opaque; 270 uint64_t regidx; 271 const ARMCPRegInfo *ri; 272 273 regidx = *(uint32_t *)key; 274 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); 275 276 if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { 277 cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx); 278 /* The value array need not be initialized at this point */ 279 cpu->cpreg_array_len++; 280 } 281 } 282 283 static void count_cpreg(gpointer key, gpointer opaque) 284 { 285 ARMCPU *cpu = opaque; 286 uint64_t regidx; 287 const ARMCPRegInfo *ri; 288 289 regidx = *(uint32_t *)key; 290 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); 291 292 if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { 293 cpu->cpreg_array_len++; 294 } 295 } 296 297 static gint cpreg_key_compare(gconstpointer a, gconstpointer b) 298 { 299 uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a); 300 uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b); 301 302 if (aidx > bidx) { 303 return 1; 304 } 305 if (aidx < bidx) { 306 return -1; 307 } 308 return 0; 309 } 310 311 void init_cpreg_list(ARMCPU *cpu) 312 { 313 /* Initialise the cpreg_tuples[] array based on the cp_regs hash. 314 * Note that we require cpreg_tuples[] to be sorted by key ID. 315 */ 316 GList *keys; 317 int arraylen; 318 319 keys = g_hash_table_get_keys(cpu->cp_regs); 320 keys = g_list_sort(keys, cpreg_key_compare); 321 322 cpu->cpreg_array_len = 0; 323 324 g_list_foreach(keys, count_cpreg, cpu); 325 326 arraylen = cpu->cpreg_array_len; 327 cpu->cpreg_indexes = g_new(uint64_t, arraylen); 328 cpu->cpreg_values = g_new(uint64_t, arraylen); 329 cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen); 330 cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen); 331 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len; 332 cpu->cpreg_array_len = 0; 333 334 g_list_foreach(keys, add_cpreg_to_list, cpu); 335 336 assert(cpu->cpreg_array_len == arraylen); 337 338 g_list_free(keys); 339 } 340 341 /* 342 * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but 343 * they are accessible when EL3 is using AArch64 regardless of EL3.NS. 344 * 345 * access_el3_aa32ns: Used to check AArch32 register views. 346 * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views. 347 */ 348 static CPAccessResult access_el3_aa32ns(CPUARMState *env, 349 const ARMCPRegInfo *ri, 350 bool isread) 351 { 352 bool secure = arm_is_secure_below_el3(env); 353 354 assert(!arm_el_is_aa64(env, 3)); 355 if (secure) { 356 return CP_ACCESS_TRAP_UNCATEGORIZED; 357 } 358 return CP_ACCESS_OK; 359 } 360 361 static CPAccessResult access_el3_aa32ns_aa64any(CPUARMState *env, 362 const ARMCPRegInfo *ri, 363 bool isread) 364 { 365 if (!arm_el_is_aa64(env, 3)) { 366 return access_el3_aa32ns(env, ri, isread); 367 } 368 return CP_ACCESS_OK; 369 } 370 371 /* Some secure-only AArch32 registers trap to EL3 if used from 372 * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts). 373 * Note that an access from Secure EL1 can only happen if EL3 is AArch64. 374 * We assume that the .access field is set to PL1_RW. 375 */ 376 static CPAccessResult access_trap_aa32s_el1(CPUARMState *env, 377 const ARMCPRegInfo *ri, 378 bool isread) 379 { 380 if (arm_current_el(env) == 3) { 381 return CP_ACCESS_OK; 382 } 383 if (arm_is_secure_below_el3(env)) { 384 return CP_ACCESS_TRAP_EL3; 385 } 386 /* This will be EL1 NS and EL2 NS, which just UNDEF */ 387 return CP_ACCESS_TRAP_UNCATEGORIZED; 388 } 389 390 /* Check for traps to "powerdown debug" registers, which are controlled 391 * by MDCR.TDOSA 392 */ 393 static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *ri, 394 bool isread) 395 { 396 int el = arm_current_el(env); 397 398 if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDOSA) 399 && !arm_is_secure_below_el3(env)) { 400 return CP_ACCESS_TRAP_EL2; 401 } 402 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDOSA)) { 403 return CP_ACCESS_TRAP_EL3; 404 } 405 return CP_ACCESS_OK; 406 } 407 408 /* Check for traps to "debug ROM" registers, which are controlled 409 * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3. 410 */ 411 static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri, 412 bool isread) 413 { 414 int el = arm_current_el(env); 415 416 if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDRA) 417 && !arm_is_secure_below_el3(env)) { 418 return CP_ACCESS_TRAP_EL2; 419 } 420 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { 421 return CP_ACCESS_TRAP_EL3; 422 } 423 return CP_ACCESS_OK; 424 } 425 426 /* Check for traps to general debug registers, which are controlled 427 * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3. 428 */ 429 static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri, 430 bool isread) 431 { 432 int el = arm_current_el(env); 433 434 if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDA) 435 && !arm_is_secure_below_el3(env)) { 436 return CP_ACCESS_TRAP_EL2; 437 } 438 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { 439 return CP_ACCESS_TRAP_EL3; 440 } 441 return CP_ACCESS_OK; 442 } 443 444 /* Check for traps to performance monitor registers, which are controlled 445 * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3. 446 */ 447 static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri, 448 bool isread) 449 { 450 int el = arm_current_el(env); 451 452 if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM) 453 && !arm_is_secure_below_el3(env)) { 454 return CP_ACCESS_TRAP_EL2; 455 } 456 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { 457 return CP_ACCESS_TRAP_EL3; 458 } 459 return CP_ACCESS_OK; 460 } 461 462 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) 463 { 464 ARMCPU *cpu = arm_env_get_cpu(env); 465 466 raw_write(env, ri, value); 467 tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */ 468 } 469 470 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) 471 { 472 ARMCPU *cpu = arm_env_get_cpu(env); 473 474 if (raw_read(env, ri) != value) { 475 /* Unlike real hardware the qemu TLB uses virtual addresses, 476 * not modified virtual addresses, so this causes a TLB flush. 477 */ 478 tlb_flush(CPU(cpu), 1); 479 raw_write(env, ri, value); 480 } 481 } 482 483 static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, 484 uint64_t value) 485 { 486 ARMCPU *cpu = arm_env_get_cpu(env); 487 488 if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_MPU) 489 && !extended_addresses_enabled(env)) { 490 /* For VMSA (when not using the LPAE long descriptor page table 491 * format) this register includes the ASID, so do a TLB flush. 492 * For PMSA it is purely a process ID and no action is needed. 493 */ 494 tlb_flush(CPU(cpu), 1); 495 } 496 raw_write(env, ri, value); 497 } 498 499 static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, 500 uint64_t value) 501 { 502 /* Invalidate all (TLBIALL) */ 503 ARMCPU *cpu = arm_env_get_cpu(env); 504 505 tlb_flush(CPU(cpu), 1); 506 } 507 508 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, 509 uint64_t value) 510 { 511 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ 512 ARMCPU *cpu = arm_env_get_cpu(env); 513 514 tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); 515 } 516 517 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, 518 uint64_t value) 519 { 520 /* Invalidate by ASID (TLBIASID) */ 521 ARMCPU *cpu = arm_env_get_cpu(env); 522 523 tlb_flush(CPU(cpu), value == 0); 524 } 525 526 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, 527 uint64_t value) 528 { 529 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ 530 ARMCPU *cpu = arm_env_get_cpu(env); 531 532 tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); 533 } 534 535 /* IS variants of TLB operations must affect all cores */ 536 static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 537 uint64_t value) 538 { 539 CPUState *other_cs; 540 541 CPU_FOREACH(other_cs) { 542 tlb_flush(other_cs, 1); 543 } 544 } 545 546 static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 547 uint64_t value) 548 { 549 CPUState *other_cs; 550 551 CPU_FOREACH(other_cs) { 552 tlb_flush(other_cs, value == 0); 553 } 554 } 555 556 static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 557 uint64_t value) 558 { 559 CPUState *other_cs; 560 561 CPU_FOREACH(other_cs) { 562 tlb_flush_page(other_cs, value & TARGET_PAGE_MASK); 563 } 564 } 565 566 static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 567 uint64_t value) 568 { 569 CPUState *other_cs; 570 571 CPU_FOREACH(other_cs) { 572 tlb_flush_page(other_cs, value & TARGET_PAGE_MASK); 573 } 574 } 575 576 static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri, 577 uint64_t value) 578 { 579 CPUState *cs = ENV_GET_CPU(env); 580 581 tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, 582 ARMMMUIdx_S2NS, -1); 583 } 584 585 static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 586 uint64_t value) 587 { 588 CPUState *other_cs; 589 590 CPU_FOREACH(other_cs) { 591 tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1, 592 ARMMMUIdx_S12NSE0, ARMMMUIdx_S2NS, -1); 593 } 594 } 595 596 static void tlbiipas2_write(CPUARMState *env, const ARMCPRegInfo *ri, 597 uint64_t value) 598 { 599 /* Invalidate by IPA. This has to invalidate any structures that 600 * contain only stage 2 translation information, but does not need 601 * to apply to structures that contain combined stage 1 and stage 2 602 * translation information. 603 * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero. 604 */ 605 CPUState *cs = ENV_GET_CPU(env); 606 uint64_t pageaddr; 607 608 if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { 609 return; 610 } 611 612 pageaddr = sextract64(value << 12, 0, 40); 613 614 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S2NS, -1); 615 } 616 617 static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 618 uint64_t value) 619 { 620 CPUState *other_cs; 621 uint64_t pageaddr; 622 623 if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { 624 return; 625 } 626 627 pageaddr = sextract64(value << 12, 0, 40); 628 629 CPU_FOREACH(other_cs) { 630 tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S2NS, -1); 631 } 632 } 633 634 static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, 635 uint64_t value) 636 { 637 CPUState *cs = ENV_GET_CPU(env); 638 639 tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1E2, -1); 640 } 641 642 static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 643 uint64_t value) 644 { 645 CPUState *other_cs; 646 647 CPU_FOREACH(other_cs) { 648 tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1E2, -1); 649 } 650 } 651 652 static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, 653 uint64_t value) 654 { 655 CPUState *cs = ENV_GET_CPU(env); 656 uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12); 657 658 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1E2, -1); 659 } 660 661 static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 662 uint64_t value) 663 { 664 CPUState *other_cs; 665 uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12); 666 667 CPU_FOREACH(other_cs) { 668 tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E2, -1); 669 } 670 } 671 672 static const ARMCPRegInfo cp_reginfo[] = { 673 /* Define the secure and non-secure FCSE identifier CP registers 674 * separately because there is no secure bank in V8 (no _EL3). This allows 675 * the secure register to be properly reset and migrated. There is also no 676 * v8 EL1 version of the register so the non-secure instance stands alone. 677 */ 678 { .name = "FCSEIDR(NS)", 679 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0, 680 .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS, 681 .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_ns), 682 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, 683 { .name = "FCSEIDR(S)", 684 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0, 685 .access = PL1_RW, .secure = ARM_CP_SECSTATE_S, 686 .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s), 687 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, 688 /* Define the secure and non-secure context identifier CP registers 689 * separately because there is no secure bank in V8 (no _EL3). This allows 690 * the secure register to be properly reset and migrated. In the 691 * non-secure case, the 32-bit register will have reset and migration 692 * disabled during registration as it is handled by the 64-bit instance. 693 */ 694 { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH, 695 .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, 696 .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS, 697 .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]), 698 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, 699 { .name = "CONTEXTIDR(S)", .state = ARM_CP_STATE_AA32, 700 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, 701 .access = PL1_RW, .secure = ARM_CP_SECSTATE_S, 702 .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s), 703 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, 704 REGINFO_SENTINEL 705 }; 706 707 static const ARMCPRegInfo not_v8_cp_reginfo[] = { 708 /* NB: Some of these registers exist in v8 but with more precise 709 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]). 710 */ 711 /* MMU Domain access control / MPU write buffer control */ 712 { .name = "DACR", 713 .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY, 714 .access = PL1_RW, .resetvalue = 0, 715 .writefn = dacr_write, .raw_writefn = raw_write, 716 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s), 717 offsetoflow32(CPUARMState, cp15.dacr_ns) } }, 718 /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs. 719 * For v6 and v5, these mappings are overly broad. 720 */ 721 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 0, 722 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, 723 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 1, 724 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, 725 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 4, 726 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, 727 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 8, 728 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, 729 /* Cache maintenance ops; some of this space may be overridden later. */ 730 { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, 731 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, 732 .type = ARM_CP_NOP | ARM_CP_OVERRIDE }, 733 REGINFO_SENTINEL 734 }; 735 736 static const ARMCPRegInfo not_v6_cp_reginfo[] = { 737 /* Not all pre-v6 cores implemented this WFI, so this is slightly 738 * over-broad. 739 */ 740 { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2, 741 .access = PL1_W, .type = ARM_CP_WFI }, 742 REGINFO_SENTINEL 743 }; 744 745 static const ARMCPRegInfo not_v7_cp_reginfo[] = { 746 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which 747 * is UNPREDICTABLE; we choose to NOP as most implementations do). 748 */ 749 { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, 750 .access = PL1_W, .type = ARM_CP_WFI }, 751 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice 752 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and 753 * OMAPCP will override this space. 754 */ 755 { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0, 756 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data), 757 .resetvalue = 0 }, 758 { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1, 759 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn), 760 .resetvalue = 0 }, 761 /* v6 doesn't have the cache ID registers but Linux reads them anyway */ 762 { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY, 763 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, 764 .resetvalue = 0 }, 765 /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR; 766 * implementing it as RAZ means the "debug architecture version" bits 767 * will read as a reserved value, which should cause Linux to not try 768 * to use the debug hardware. 769 */ 770 { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, 771 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 772 /* MMU TLB control. Note that the wildcarding means we cover not just 773 * the unified TLB ops but also the dside/iside/inner-shareable variants. 774 */ 775 { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY, 776 .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write, 777 .type = ARM_CP_NO_RAW }, 778 { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY, 779 .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write, 780 .type = ARM_CP_NO_RAW }, 781 { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY, 782 .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write, 783 .type = ARM_CP_NO_RAW }, 784 { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY, 785 .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write, 786 .type = ARM_CP_NO_RAW }, 787 { .name = "PRRR", .cp = 15, .crn = 10, .crm = 2, 788 .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP }, 789 { .name = "NMRR", .cp = 15, .crn = 10, .crm = 2, 790 .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP }, 791 REGINFO_SENTINEL 792 }; 793 794 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, 795 uint64_t value) 796 { 797 uint32_t mask = 0; 798 799 /* In ARMv8 most bits of CPACR_EL1 are RES0. */ 800 if (!arm_feature(env, ARM_FEATURE_V8)) { 801 /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI. 802 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP. 803 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell. 804 */ 805 if (arm_feature(env, ARM_FEATURE_VFP)) { 806 /* VFP coprocessor: cp10 & cp11 [23:20] */ 807 mask |= (1 << 31) | (1 << 30) | (0xf << 20); 808 809 if (!arm_feature(env, ARM_FEATURE_NEON)) { 810 /* ASEDIS [31] bit is RAO/WI */ 811 value |= (1 << 31); 812 } 813 814 /* VFPv3 and upwards with NEON implement 32 double precision 815 * registers (D0-D31). 816 */ 817 if (!arm_feature(env, ARM_FEATURE_NEON) || 818 !arm_feature(env, ARM_FEATURE_VFP3)) { 819 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */ 820 value |= (1 << 30); 821 } 822 } 823 value &= mask; 824 } 825 env->cp15.cpacr_el1 = value; 826 } 827 828 static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri, 829 bool isread) 830 { 831 if (arm_feature(env, ARM_FEATURE_V8)) { 832 /* Check if CPACR accesses are to be trapped to EL2 */ 833 if (arm_current_el(env) == 1 && 834 (env->cp15.cptr_el[2] & CPTR_TCPAC) && !arm_is_secure(env)) { 835 return CP_ACCESS_TRAP_EL2; 836 /* Check if CPACR accesses are to be trapped to EL3 */ 837 } else if (arm_current_el(env) < 3 && 838 (env->cp15.cptr_el[3] & CPTR_TCPAC)) { 839 return CP_ACCESS_TRAP_EL3; 840 } 841 } 842 843 return CP_ACCESS_OK; 844 } 845 846 static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri, 847 bool isread) 848 { 849 /* Check if CPTR accesses are set to trap to EL3 */ 850 if (arm_current_el(env) == 2 && (env->cp15.cptr_el[3] & CPTR_TCPAC)) { 851 return CP_ACCESS_TRAP_EL3; 852 } 853 854 return CP_ACCESS_OK; 855 } 856 857 static const ARMCPRegInfo v6_cp_reginfo[] = { 858 /* prefetch by MVA in v6, NOP in v7 */ 859 { .name = "MVA_prefetch", 860 .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1, 861 .access = PL1_W, .type = ARM_CP_NOP }, 862 /* We need to break the TB after ISB to execute self-modifying code 863 * correctly and also to take any pending interrupts immediately. 864 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag. 865 */ 866 { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4, 867 .access = PL0_W, .type = ARM_CP_NO_RAW, .writefn = arm_cp_write_ignore }, 868 { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4, 869 .access = PL0_W, .type = ARM_CP_NOP }, 870 { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5, 871 .access = PL0_W, .type = ARM_CP_NOP }, 872 { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2, 873 .access = PL1_RW, 874 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s), 875 offsetof(CPUARMState, cp15.ifar_ns) }, 876 .resetvalue = 0, }, 877 /* Watchpoint Fault Address Register : should actually only be present 878 * for 1136, 1176, 11MPCore. 879 */ 880 { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, 881 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, }, 882 { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, 883 .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access, 884 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1), 885 .resetvalue = 0, .writefn = cpacr_write }, 886 REGINFO_SENTINEL 887 }; 888 889 static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri, 890 bool isread) 891 { 892 /* Performance monitor registers user accessibility is controlled 893 * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable 894 * trapping to EL2 or EL3 for other accesses. 895 */ 896 int el = arm_current_el(env); 897 898 if (el == 0 && !env->cp15.c9_pmuserenr) { 899 return CP_ACCESS_TRAP; 900 } 901 if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM) 902 && !arm_is_secure_below_el3(env)) { 903 return CP_ACCESS_TRAP_EL2; 904 } 905 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { 906 return CP_ACCESS_TRAP_EL3; 907 } 908 909 return CP_ACCESS_OK; 910 } 911 912 #ifndef CONFIG_USER_ONLY 913 914 static inline bool arm_ccnt_enabled(CPUARMState *env) 915 { 916 /* This does not support checking PMCCFILTR_EL0 register */ 917 918 if (!(env->cp15.c9_pmcr & PMCRE)) { 919 return false; 920 } 921 922 return true; 923 } 924 925 void pmccntr_sync(CPUARMState *env) 926 { 927 uint64_t temp_ticks; 928 929 temp_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 930 ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); 931 932 if (env->cp15.c9_pmcr & PMCRD) { 933 /* Increment once every 64 processor clock cycles */ 934 temp_ticks /= 64; 935 } 936 937 if (arm_ccnt_enabled(env)) { 938 env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt; 939 } 940 } 941 942 static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, 943 uint64_t value) 944 { 945 pmccntr_sync(env); 946 947 if (value & PMCRC) { 948 /* The counter has been reset */ 949 env->cp15.c15_ccnt = 0; 950 } 951 952 /* only the DP, X, D and E bits are writable */ 953 env->cp15.c9_pmcr &= ~0x39; 954 env->cp15.c9_pmcr |= (value & 0x39); 955 956 pmccntr_sync(env); 957 } 958 959 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) 960 { 961 uint64_t total_ticks; 962 963 if (!arm_ccnt_enabled(env)) { 964 /* Counter is disabled, do not change value */ 965 return env->cp15.c15_ccnt; 966 } 967 968 total_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 969 ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); 970 971 if (env->cp15.c9_pmcr & PMCRD) { 972 /* Increment once every 64 processor clock cycles */ 973 total_ticks /= 64; 974 } 975 return total_ticks - env->cp15.c15_ccnt; 976 } 977 978 static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, 979 uint64_t value) 980 { 981 uint64_t total_ticks; 982 983 if (!arm_ccnt_enabled(env)) { 984 /* Counter is disabled, set the absolute value */ 985 env->cp15.c15_ccnt = value; 986 return; 987 } 988 989 total_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 990 ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); 991 992 if (env->cp15.c9_pmcr & PMCRD) { 993 /* Increment once every 64 processor clock cycles */ 994 total_ticks /= 64; 995 } 996 env->cp15.c15_ccnt = total_ticks - value; 997 } 998 999 static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri, 1000 uint64_t value) 1001 { 1002 uint64_t cur_val = pmccntr_read(env, NULL); 1003 1004 pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value)); 1005 } 1006 1007 #else /* CONFIG_USER_ONLY */ 1008 1009 void pmccntr_sync(CPUARMState *env) 1010 { 1011 } 1012 1013 #endif 1014 1015 static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1016 uint64_t value) 1017 { 1018 pmccntr_sync(env); 1019 env->cp15.pmccfiltr_el0 = value & 0x7E000000; 1020 pmccntr_sync(env); 1021 } 1022 1023 static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, 1024 uint64_t value) 1025 { 1026 value &= (1 << 31); 1027 env->cp15.c9_pmcnten |= value; 1028 } 1029 1030 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1031 uint64_t value) 1032 { 1033 value &= (1 << 31); 1034 env->cp15.c9_pmcnten &= ~value; 1035 } 1036 1037 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1038 uint64_t value) 1039 { 1040 env->cp15.c9_pmovsr &= ~value; 1041 } 1042 1043 static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, 1044 uint64_t value) 1045 { 1046 env->cp15.c9_pmxevtyper = value & 0xff; 1047 } 1048 1049 static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1050 uint64_t value) 1051 { 1052 env->cp15.c9_pmuserenr = value & 1; 1053 } 1054 1055 static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri, 1056 uint64_t value) 1057 { 1058 /* We have no event counters so only the C bit can be changed */ 1059 value &= (1 << 31); 1060 env->cp15.c9_pminten |= value; 1061 } 1062 1063 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1064 uint64_t value) 1065 { 1066 value &= (1 << 31); 1067 env->cp15.c9_pminten &= ~value; 1068 } 1069 1070 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, 1071 uint64_t value) 1072 { 1073 /* Note that even though the AArch64 view of this register has bits 1074 * [10:0] all RES0 we can only mask the bottom 5, to comply with the 1075 * architectural requirements for bits which are RES0 only in some 1076 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7 1077 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.) 1078 */ 1079 raw_write(env, ri, value & ~0x1FULL); 1080 } 1081 1082 static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) 1083 { 1084 /* We only mask off bits that are RES0 both for AArch64 and AArch32. 1085 * For bits that vary between AArch32/64, code needs to check the 1086 * current execution mode before directly using the feature bit. 1087 */ 1088 uint32_t valid_mask = SCR_AARCH64_MASK | SCR_AARCH32_MASK; 1089 1090 if (!arm_feature(env, ARM_FEATURE_EL2)) { 1091 valid_mask &= ~SCR_HCE; 1092 1093 /* On ARMv7, SMD (or SCD as it is called in v7) is only 1094 * supported if EL2 exists. The bit is UNK/SBZP when 1095 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero 1096 * when EL2 is unavailable. 1097 * On ARMv8, this bit is always available. 1098 */ 1099 if (arm_feature(env, ARM_FEATURE_V7) && 1100 !arm_feature(env, ARM_FEATURE_V8)) { 1101 valid_mask &= ~SCR_SMD; 1102 } 1103 } 1104 1105 /* Clear all-context RES0 bits. */ 1106 value &= valid_mask; 1107 raw_write(env, ri, value); 1108 } 1109 1110 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1111 { 1112 ARMCPU *cpu = arm_env_get_cpu(env); 1113 1114 /* Acquire the CSSELR index from the bank corresponding to the CCSIDR 1115 * bank 1116 */ 1117 uint32_t index = A32_BANKED_REG_GET(env, csselr, 1118 ri->secure & ARM_CP_SECSTATE_S); 1119 1120 return cpu->ccsidr[index]; 1121 } 1122 1123 static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1124 uint64_t value) 1125 { 1126 raw_write(env, ri, value & 0xf); 1127 } 1128 1129 static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1130 { 1131 CPUState *cs = ENV_GET_CPU(env); 1132 uint64_t ret = 0; 1133 1134 if (cs->interrupt_request & CPU_INTERRUPT_HARD) { 1135 ret |= CPSR_I; 1136 } 1137 if (cs->interrupt_request & CPU_INTERRUPT_FIQ) { 1138 ret |= CPSR_F; 1139 } 1140 /* External aborts are not possible in QEMU so A bit is always clear */ 1141 return ret; 1142 } 1143 1144 static const ARMCPRegInfo v7_cp_reginfo[] = { 1145 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */ 1146 { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, 1147 .access = PL1_W, .type = ARM_CP_NOP }, 1148 /* Performance monitors are implementation defined in v7, 1149 * but with an ARM recommended set of registers, which we 1150 * follow (although we don't actually implement any counters) 1151 * 1152 * Performance registers fall into three categories: 1153 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR) 1154 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR) 1155 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others) 1156 * For the cases controlled by PMUSERENR we must set .access to PL0_RW 1157 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn. 1158 */ 1159 { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1, 1160 .access = PL0_RW, .type = ARM_CP_ALIAS, 1161 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), 1162 .writefn = pmcntenset_write, 1163 .accessfn = pmreg_access, 1164 .raw_writefn = raw_write }, 1165 { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64, 1166 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1, 1167 .access = PL0_RW, .accessfn = pmreg_access, 1168 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0, 1169 .writefn = pmcntenset_write, .raw_writefn = raw_write }, 1170 { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2, 1171 .access = PL0_RW, 1172 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), 1173 .accessfn = pmreg_access, 1174 .writefn = pmcntenclr_write, 1175 .type = ARM_CP_ALIAS }, 1176 { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64, 1177 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2, 1178 .access = PL0_RW, .accessfn = pmreg_access, 1179 .type = ARM_CP_ALIAS, 1180 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), 1181 .writefn = pmcntenclr_write }, 1182 { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3, 1183 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), 1184 .accessfn = pmreg_access, 1185 .writefn = pmovsr_write, 1186 .raw_writefn = raw_write }, 1187 { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64, 1188 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3, 1189 .access = PL0_RW, .accessfn = pmreg_access, 1190 .type = ARM_CP_ALIAS, 1191 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), 1192 .writefn = pmovsr_write, 1193 .raw_writefn = raw_write }, 1194 /* Unimplemented so WI. */ 1195 { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4, 1196 .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP }, 1197 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE. 1198 * We choose to RAZ/WI. 1199 */ 1200 { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5, 1201 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0, 1202 .accessfn = pmreg_access }, 1203 #ifndef CONFIG_USER_ONLY 1204 { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0, 1205 .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO, 1206 .readfn = pmccntr_read, .writefn = pmccntr_write32, 1207 .accessfn = pmreg_access }, 1208 { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64, 1209 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0, 1210 .access = PL0_RW, .accessfn = pmreg_access, 1211 .type = ARM_CP_IO, 1212 .readfn = pmccntr_read, .writefn = pmccntr_write, }, 1213 #endif 1214 { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64, 1215 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7, 1216 .writefn = pmccfiltr_write, 1217 .access = PL0_RW, .accessfn = pmreg_access, 1218 .type = ARM_CP_IO, 1219 .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0), 1220 .resetvalue = 0, }, 1221 { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1, 1222 .access = PL0_RW, 1223 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper), 1224 .accessfn = pmreg_access, .writefn = pmxevtyper_write, 1225 .raw_writefn = raw_write }, 1226 /* Unimplemented, RAZ/WI. */ 1227 { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2, 1228 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0, 1229 .accessfn = pmreg_access }, 1230 { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0, 1231 .access = PL0_R | PL1_RW, .accessfn = access_tpm, 1232 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr), 1233 .resetvalue = 0, 1234 .writefn = pmuserenr_write, .raw_writefn = raw_write }, 1235 { .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64, 1236 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 0, 1237 .access = PL0_R | PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS, 1238 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr), 1239 .resetvalue = 0, 1240 .writefn = pmuserenr_write, .raw_writefn = raw_write }, 1241 { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1, 1242 .access = PL1_RW, .accessfn = access_tpm, 1243 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), 1244 .resetvalue = 0, 1245 .writefn = pmintenset_write, .raw_writefn = raw_write }, 1246 { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2, 1247 .access = PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS, 1248 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), 1249 .writefn = pmintenclr_write, }, 1250 { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64, 1251 .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2, 1252 .access = PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS, 1253 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), 1254 .writefn = pmintenclr_write }, 1255 { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, 1256 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, 1257 .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_RAW }, 1258 { .name = "CSSELR", .state = ARM_CP_STATE_BOTH, 1259 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0, 1260 .access = PL1_RW, .writefn = csselr_write, .resetvalue = 0, 1261 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s), 1262 offsetof(CPUARMState, cp15.csselr_ns) } }, 1263 /* Auxiliary ID register: this actually has an IMPDEF value but for now 1264 * just RAZ for all cores: 1265 */ 1266 { .name = "AIDR", .state = ARM_CP_STATE_BOTH, 1267 .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7, 1268 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 1269 /* Auxiliary fault status registers: these also are IMPDEF, and we 1270 * choose to RAZ/WI for all cores. 1271 */ 1272 { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH, 1273 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0, 1274 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1275 { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH, 1276 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1, 1277 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1278 /* MAIR can just read-as-written because we don't implement caches 1279 * and so don't need to care about memory attributes. 1280 */ 1281 { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64, 1282 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, 1283 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]), 1284 .resetvalue = 0 }, 1285 { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64, 1286 .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0, 1287 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]), 1288 .resetvalue = 0 }, 1289 /* For non-long-descriptor page tables these are PRRR and NMRR; 1290 * regardless they still act as reads-as-written for QEMU. 1291 */ 1292 /* MAIR0/1 are defined separately from their 64-bit counterpart which 1293 * allows them to assign the correct fieldoffset based on the endianness 1294 * handled in the field definitions. 1295 */ 1296 { .name = "MAIR0", .state = ARM_CP_STATE_AA32, 1297 .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW, 1298 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s), 1299 offsetof(CPUARMState, cp15.mair0_ns) }, 1300 .resetfn = arm_cp_reset_ignore }, 1301 { .name = "MAIR1", .state = ARM_CP_STATE_AA32, 1302 .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW, 1303 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s), 1304 offsetof(CPUARMState, cp15.mair1_ns) }, 1305 .resetfn = arm_cp_reset_ignore }, 1306 { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH, 1307 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0, 1308 .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read }, 1309 /* 32 bit ITLB invalidates */ 1310 { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0, 1311 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write }, 1312 { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1, 1313 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, 1314 { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2, 1315 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write }, 1316 /* 32 bit DTLB invalidates */ 1317 { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0, 1318 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write }, 1319 { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1, 1320 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, 1321 { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2, 1322 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write }, 1323 /* 32 bit TLB invalidates */ 1324 { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, 1325 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write }, 1326 { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, 1327 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, 1328 { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, 1329 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write }, 1330 { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, 1331 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write }, 1332 REGINFO_SENTINEL 1333 }; 1334 1335 static const ARMCPRegInfo v7mp_cp_reginfo[] = { 1336 /* 32 bit TLB invalidates, Inner Shareable */ 1337 { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, 1338 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_is_write }, 1339 { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, 1340 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write }, 1341 { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, 1342 .type = ARM_CP_NO_RAW, .access = PL1_W, 1343 .writefn = tlbiasid_is_write }, 1344 { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, 1345 .type = ARM_CP_NO_RAW, .access = PL1_W, 1346 .writefn = tlbimvaa_is_write }, 1347 REGINFO_SENTINEL 1348 }; 1349 1350 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1351 uint64_t value) 1352 { 1353 value &= 1; 1354 env->teecr = value; 1355 } 1356 1357 static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri, 1358 bool isread) 1359 { 1360 if (arm_current_el(env) == 0 && (env->teecr & 1)) { 1361 return CP_ACCESS_TRAP; 1362 } 1363 return CP_ACCESS_OK; 1364 } 1365 1366 static const ARMCPRegInfo t2ee_cp_reginfo[] = { 1367 { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0, 1368 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr), 1369 .resetvalue = 0, 1370 .writefn = teecr_write }, 1371 { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0, 1372 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr), 1373 .accessfn = teehbr_access, .resetvalue = 0 }, 1374 REGINFO_SENTINEL 1375 }; 1376 1377 static const ARMCPRegInfo v6k_cp_reginfo[] = { 1378 { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64, 1379 .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0, 1380 .access = PL0_RW, 1381 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 }, 1382 { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2, 1383 .access = PL0_RW, 1384 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s), 1385 offsetoflow32(CPUARMState, cp15.tpidrurw_ns) }, 1386 .resetfn = arm_cp_reset_ignore }, 1387 { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64, 1388 .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0, 1389 .access = PL0_R|PL1_W, 1390 .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]), 1391 .resetvalue = 0}, 1392 { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3, 1393 .access = PL0_R|PL1_W, 1394 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s), 1395 offsetoflow32(CPUARMState, cp15.tpidruro_ns) }, 1396 .resetfn = arm_cp_reset_ignore }, 1397 { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64, 1398 .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0, 1399 .access = PL1_RW, 1400 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 }, 1401 { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4, 1402 .access = PL1_RW, 1403 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s), 1404 offsetoflow32(CPUARMState, cp15.tpidrprw_ns) }, 1405 .resetvalue = 0 }, 1406 REGINFO_SENTINEL 1407 }; 1408 1409 #ifndef CONFIG_USER_ONLY 1410 1411 static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri, 1412 bool isread) 1413 { 1414 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero. 1415 * Writable only at the highest implemented exception level. 1416 */ 1417 int el = arm_current_el(env); 1418 1419 switch (el) { 1420 case 0: 1421 if (!extract32(env->cp15.c14_cntkctl, 0, 2)) { 1422 return CP_ACCESS_TRAP; 1423 } 1424 break; 1425 case 1: 1426 if (!isread && ri->state == ARM_CP_STATE_AA32 && 1427 arm_is_secure_below_el3(env)) { 1428 /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */ 1429 return CP_ACCESS_TRAP_UNCATEGORIZED; 1430 } 1431 break; 1432 case 2: 1433 case 3: 1434 break; 1435 } 1436 1437 if (!isread && el < arm_highest_el(env)) { 1438 return CP_ACCESS_TRAP_UNCATEGORIZED; 1439 } 1440 1441 return CP_ACCESS_OK; 1442 } 1443 1444 static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx, 1445 bool isread) 1446 { 1447 unsigned int cur_el = arm_current_el(env); 1448 bool secure = arm_is_secure(env); 1449 1450 /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */ 1451 if (cur_el == 0 && 1452 !extract32(env->cp15.c14_cntkctl, timeridx, 1)) { 1453 return CP_ACCESS_TRAP; 1454 } 1455 1456 if (arm_feature(env, ARM_FEATURE_EL2) && 1457 timeridx == GTIMER_PHYS && !secure && cur_el < 2 && 1458 !extract32(env->cp15.cnthctl_el2, 0, 1)) { 1459 return CP_ACCESS_TRAP_EL2; 1460 } 1461 return CP_ACCESS_OK; 1462 } 1463 1464 static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx, 1465 bool isread) 1466 { 1467 unsigned int cur_el = arm_current_el(env); 1468 bool secure = arm_is_secure(env); 1469 1470 /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if 1471 * EL0[PV]TEN is zero. 1472 */ 1473 if (cur_el == 0 && 1474 !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) { 1475 return CP_ACCESS_TRAP; 1476 } 1477 1478 if (arm_feature(env, ARM_FEATURE_EL2) && 1479 timeridx == GTIMER_PHYS && !secure && cur_el < 2 && 1480 !extract32(env->cp15.cnthctl_el2, 1, 1)) { 1481 return CP_ACCESS_TRAP_EL2; 1482 } 1483 return CP_ACCESS_OK; 1484 } 1485 1486 static CPAccessResult gt_pct_access(CPUARMState *env, 1487 const ARMCPRegInfo *ri, 1488 bool isread) 1489 { 1490 return gt_counter_access(env, GTIMER_PHYS, isread); 1491 } 1492 1493 static CPAccessResult gt_vct_access(CPUARMState *env, 1494 const ARMCPRegInfo *ri, 1495 bool isread) 1496 { 1497 return gt_counter_access(env, GTIMER_VIRT, isread); 1498 } 1499 1500 static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri, 1501 bool isread) 1502 { 1503 return gt_timer_access(env, GTIMER_PHYS, isread); 1504 } 1505 1506 static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri, 1507 bool isread) 1508 { 1509 return gt_timer_access(env, GTIMER_VIRT, isread); 1510 } 1511 1512 static CPAccessResult gt_stimer_access(CPUARMState *env, 1513 const ARMCPRegInfo *ri, 1514 bool isread) 1515 { 1516 /* The AArch64 register view of the secure physical timer is 1517 * always accessible from EL3, and configurably accessible from 1518 * Secure EL1. 1519 */ 1520 switch (arm_current_el(env)) { 1521 case 1: 1522 if (!arm_is_secure(env)) { 1523 return CP_ACCESS_TRAP; 1524 } 1525 if (!(env->cp15.scr_el3 & SCR_ST)) { 1526 return CP_ACCESS_TRAP_EL3; 1527 } 1528 return CP_ACCESS_OK; 1529 case 0: 1530 case 2: 1531 return CP_ACCESS_TRAP; 1532 case 3: 1533 return CP_ACCESS_OK; 1534 default: 1535 g_assert_not_reached(); 1536 } 1537 } 1538 1539 static uint64_t gt_get_countervalue(CPUARMState *env) 1540 { 1541 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE; 1542 } 1543 1544 static void gt_recalc_timer(ARMCPU *cpu, int timeridx) 1545 { 1546 ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx]; 1547 1548 if (gt->ctl & 1) { 1549 /* Timer enabled: calculate and set current ISTATUS, irq, and 1550 * reset timer to when ISTATUS next has to change 1551 */ 1552 uint64_t offset = timeridx == GTIMER_VIRT ? 1553 cpu->env.cp15.cntvoff_el2 : 0; 1554 uint64_t count = gt_get_countervalue(&cpu->env); 1555 /* Note that this must be unsigned 64 bit arithmetic: */ 1556 int istatus = count - offset >= gt->cval; 1557 uint64_t nexttick; 1558 int irqstate; 1559 1560 gt->ctl = deposit32(gt->ctl, 2, 1, istatus); 1561 1562 irqstate = (istatus && !(gt->ctl & 2)); 1563 qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); 1564 1565 if (istatus) { 1566 /* Next transition is when count rolls back over to zero */ 1567 nexttick = UINT64_MAX; 1568 } else { 1569 /* Next transition is when we hit cval */ 1570 nexttick = gt->cval + offset; 1571 } 1572 /* Note that the desired next expiry time might be beyond the 1573 * signed-64-bit range of a QEMUTimer -- in this case we just 1574 * set the timer for as far in the future as possible. When the 1575 * timer expires we will reset the timer for any remaining period. 1576 */ 1577 if (nexttick > INT64_MAX / GTIMER_SCALE) { 1578 nexttick = INT64_MAX / GTIMER_SCALE; 1579 } 1580 timer_mod(cpu->gt_timer[timeridx], nexttick); 1581 trace_arm_gt_recalc(timeridx, irqstate, nexttick); 1582 } else { 1583 /* Timer disabled: ISTATUS and timer output always clear */ 1584 gt->ctl &= ~4; 1585 qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0); 1586 timer_del(cpu->gt_timer[timeridx]); 1587 trace_arm_gt_recalc_disabled(timeridx); 1588 } 1589 } 1590 1591 static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri, 1592 int timeridx) 1593 { 1594 ARMCPU *cpu = arm_env_get_cpu(env); 1595 1596 timer_del(cpu->gt_timer[timeridx]); 1597 } 1598 1599 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) 1600 { 1601 return gt_get_countervalue(env); 1602 } 1603 1604 static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) 1605 { 1606 return gt_get_countervalue(env) - env->cp15.cntvoff_el2; 1607 } 1608 1609 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1610 int timeridx, 1611 uint64_t value) 1612 { 1613 trace_arm_gt_cval_write(timeridx, value); 1614 env->cp15.c14_timer[timeridx].cval = value; 1615 gt_recalc_timer(arm_env_get_cpu(env), timeridx); 1616 } 1617 1618 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri, 1619 int timeridx) 1620 { 1621 uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0; 1622 1623 return (uint32_t)(env->cp15.c14_timer[timeridx].cval - 1624 (gt_get_countervalue(env) - offset)); 1625 } 1626 1627 static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1628 int timeridx, 1629 uint64_t value) 1630 { 1631 uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0; 1632 1633 trace_arm_gt_tval_write(timeridx, value); 1634 env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset + 1635 sextract64(value, 0, 32); 1636 gt_recalc_timer(arm_env_get_cpu(env), timeridx); 1637 } 1638 1639 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, 1640 int timeridx, 1641 uint64_t value) 1642 { 1643 ARMCPU *cpu = arm_env_get_cpu(env); 1644 uint32_t oldval = env->cp15.c14_timer[timeridx].ctl; 1645 1646 trace_arm_gt_ctl_write(timeridx, value); 1647 env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value); 1648 if ((oldval ^ value) & 1) { 1649 /* Enable toggled */ 1650 gt_recalc_timer(cpu, timeridx); 1651 } else if ((oldval ^ value) & 2) { 1652 /* IMASK toggled: don't need to recalculate, 1653 * just set the interrupt line based on ISTATUS 1654 */ 1655 int irqstate = (oldval & 4) && !(value & 2); 1656 1657 trace_arm_gt_imask_toggle(timeridx, irqstate); 1658 qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); 1659 } 1660 } 1661 1662 static void gt_phys_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) 1663 { 1664 gt_timer_reset(env, ri, GTIMER_PHYS); 1665 } 1666 1667 static void gt_phys_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1668 uint64_t value) 1669 { 1670 gt_cval_write(env, ri, GTIMER_PHYS, value); 1671 } 1672 1673 static uint64_t gt_phys_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) 1674 { 1675 return gt_tval_read(env, ri, GTIMER_PHYS); 1676 } 1677 1678 static void gt_phys_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1679 uint64_t value) 1680 { 1681 gt_tval_write(env, ri, GTIMER_PHYS, value); 1682 } 1683 1684 static void gt_phys_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, 1685 uint64_t value) 1686 { 1687 gt_ctl_write(env, ri, GTIMER_PHYS, value); 1688 } 1689 1690 static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) 1691 { 1692 gt_timer_reset(env, ri, GTIMER_VIRT); 1693 } 1694 1695 static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1696 uint64_t value) 1697 { 1698 gt_cval_write(env, ri, GTIMER_VIRT, value); 1699 } 1700 1701 static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) 1702 { 1703 return gt_tval_read(env, ri, GTIMER_VIRT); 1704 } 1705 1706 static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1707 uint64_t value) 1708 { 1709 gt_tval_write(env, ri, GTIMER_VIRT, value); 1710 } 1711 1712 static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, 1713 uint64_t value) 1714 { 1715 gt_ctl_write(env, ri, GTIMER_VIRT, value); 1716 } 1717 1718 static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri, 1719 uint64_t value) 1720 { 1721 ARMCPU *cpu = arm_env_get_cpu(env); 1722 1723 trace_arm_gt_cntvoff_write(value); 1724 raw_write(env, ri, value); 1725 gt_recalc_timer(cpu, GTIMER_VIRT); 1726 } 1727 1728 static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) 1729 { 1730 gt_timer_reset(env, ri, GTIMER_HYP); 1731 } 1732 1733 static void gt_hyp_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1734 uint64_t value) 1735 { 1736 gt_cval_write(env, ri, GTIMER_HYP, value); 1737 } 1738 1739 static uint64_t gt_hyp_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) 1740 { 1741 return gt_tval_read(env, ri, GTIMER_HYP); 1742 } 1743 1744 static void gt_hyp_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1745 uint64_t value) 1746 { 1747 gt_tval_write(env, ri, GTIMER_HYP, value); 1748 } 1749 1750 static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, 1751 uint64_t value) 1752 { 1753 gt_ctl_write(env, ri, GTIMER_HYP, value); 1754 } 1755 1756 static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) 1757 { 1758 gt_timer_reset(env, ri, GTIMER_SEC); 1759 } 1760 1761 static void gt_sec_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1762 uint64_t value) 1763 { 1764 gt_cval_write(env, ri, GTIMER_SEC, value); 1765 } 1766 1767 static uint64_t gt_sec_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) 1768 { 1769 return gt_tval_read(env, ri, GTIMER_SEC); 1770 } 1771 1772 static void gt_sec_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1773 uint64_t value) 1774 { 1775 gt_tval_write(env, ri, GTIMER_SEC, value); 1776 } 1777 1778 static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, 1779 uint64_t value) 1780 { 1781 gt_ctl_write(env, ri, GTIMER_SEC, value); 1782 } 1783 1784 void arm_gt_ptimer_cb(void *opaque) 1785 { 1786 ARMCPU *cpu = opaque; 1787 1788 gt_recalc_timer(cpu, GTIMER_PHYS); 1789 } 1790 1791 void arm_gt_vtimer_cb(void *opaque) 1792 { 1793 ARMCPU *cpu = opaque; 1794 1795 gt_recalc_timer(cpu, GTIMER_VIRT); 1796 } 1797 1798 void arm_gt_htimer_cb(void *opaque) 1799 { 1800 ARMCPU *cpu = opaque; 1801 1802 gt_recalc_timer(cpu, GTIMER_HYP); 1803 } 1804 1805 void arm_gt_stimer_cb(void *opaque) 1806 { 1807 ARMCPU *cpu = opaque; 1808 1809 gt_recalc_timer(cpu, GTIMER_SEC); 1810 } 1811 1812 static const ARMCPRegInfo generic_timer_cp_reginfo[] = { 1813 /* Note that CNTFRQ is purely reads-as-written for the benefit 1814 * of software; writing it doesn't actually change the timer frequency. 1815 * Our reset value matches the fixed frequency we implement the timer at. 1816 */ 1817 { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0, 1818 .type = ARM_CP_ALIAS, 1819 .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, 1820 .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq), 1821 }, 1822 { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64, 1823 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0, 1824 .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, 1825 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq), 1826 .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE, 1827 }, 1828 /* overall control: mostly access permissions */ 1829 { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH, 1830 .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0, 1831 .access = PL1_RW, 1832 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl), 1833 .resetvalue = 0, 1834 }, 1835 /* per-timer control */ 1836 { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1, 1837 .secure = ARM_CP_SECSTATE_NS, 1838 .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R, 1839 .accessfn = gt_ptimer_access, 1840 .fieldoffset = offsetoflow32(CPUARMState, 1841 cp15.c14_timer[GTIMER_PHYS].ctl), 1842 .writefn = gt_phys_ctl_write, .raw_writefn = raw_write, 1843 }, 1844 { .name = "CNTP_CTL(S)", 1845 .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1, 1846 .secure = ARM_CP_SECSTATE_S, 1847 .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R, 1848 .accessfn = gt_ptimer_access, 1849 .fieldoffset = offsetoflow32(CPUARMState, 1850 cp15.c14_timer[GTIMER_SEC].ctl), 1851 .writefn = gt_sec_ctl_write, .raw_writefn = raw_write, 1852 }, 1853 { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64, 1854 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1, 1855 .type = ARM_CP_IO, .access = PL1_RW | PL0_R, 1856 .accessfn = gt_ptimer_access, 1857 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), 1858 .resetvalue = 0, 1859 .writefn = gt_phys_ctl_write, .raw_writefn = raw_write, 1860 }, 1861 { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1, 1862 .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R, 1863 .accessfn = gt_vtimer_access, 1864 .fieldoffset = offsetoflow32(CPUARMState, 1865 cp15.c14_timer[GTIMER_VIRT].ctl), 1866 .writefn = gt_virt_ctl_write, .raw_writefn = raw_write, 1867 }, 1868 { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64, 1869 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1, 1870 .type = ARM_CP_IO, .access = PL1_RW | PL0_R, 1871 .accessfn = gt_vtimer_access, 1872 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl), 1873 .resetvalue = 0, 1874 .writefn = gt_virt_ctl_write, .raw_writefn = raw_write, 1875 }, 1876 /* TimerValue views: a 32 bit downcounting view of the underlying state */ 1877 { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0, 1878 .secure = ARM_CP_SECSTATE_NS, 1879 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, 1880 .accessfn = gt_ptimer_access, 1881 .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write, 1882 }, 1883 { .name = "CNTP_TVAL(S)", 1884 .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0, 1885 .secure = ARM_CP_SECSTATE_S, 1886 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, 1887 .accessfn = gt_ptimer_access, 1888 .readfn = gt_sec_tval_read, .writefn = gt_sec_tval_write, 1889 }, 1890 { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64, 1891 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0, 1892 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, 1893 .accessfn = gt_ptimer_access, .resetfn = gt_phys_timer_reset, 1894 .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write, 1895 }, 1896 { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0, 1897 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, 1898 .accessfn = gt_vtimer_access, 1899 .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write, 1900 }, 1901 { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64, 1902 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0, 1903 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, 1904 .accessfn = gt_vtimer_access, .resetfn = gt_virt_timer_reset, 1905 .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write, 1906 }, 1907 /* The counter itself */ 1908 { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0, 1909 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, 1910 .accessfn = gt_pct_access, 1911 .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore, 1912 }, 1913 { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64, 1914 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1, 1915 .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, 1916 .accessfn = gt_pct_access, .readfn = gt_cnt_read, 1917 }, 1918 { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1, 1919 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, 1920 .accessfn = gt_vct_access, 1921 .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore, 1922 }, 1923 { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64, 1924 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2, 1925 .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, 1926 .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read, 1927 }, 1928 /* Comparison value, indicating when the timer goes off */ 1929 { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2, 1930 .secure = ARM_CP_SECSTATE_NS, 1931 .access = PL1_RW | PL0_R, 1932 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, 1933 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), 1934 .accessfn = gt_ptimer_access, 1935 .writefn = gt_phys_cval_write, .raw_writefn = raw_write, 1936 }, 1937 { .name = "CNTP_CVAL(S)", .cp = 15, .crm = 14, .opc1 = 2, 1938 .secure = ARM_CP_SECSTATE_S, 1939 .access = PL1_RW | PL0_R, 1940 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, 1941 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval), 1942 .accessfn = gt_ptimer_access, 1943 .writefn = gt_sec_cval_write, .raw_writefn = raw_write, 1944 }, 1945 { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64, 1946 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2, 1947 .access = PL1_RW | PL0_R, 1948 .type = ARM_CP_IO, 1949 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), 1950 .resetvalue = 0, .accessfn = gt_ptimer_access, 1951 .writefn = gt_phys_cval_write, .raw_writefn = raw_write, 1952 }, 1953 { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3, 1954 .access = PL1_RW | PL0_R, 1955 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, 1956 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), 1957 .accessfn = gt_vtimer_access, 1958 .writefn = gt_virt_cval_write, .raw_writefn = raw_write, 1959 }, 1960 { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64, 1961 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2, 1962 .access = PL1_RW | PL0_R, 1963 .type = ARM_CP_IO, 1964 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), 1965 .resetvalue = 0, .accessfn = gt_vtimer_access, 1966 .writefn = gt_virt_cval_write, .raw_writefn = raw_write, 1967 }, 1968 /* Secure timer -- this is actually restricted to only EL3 1969 * and configurably Secure-EL1 via the accessfn. 1970 */ 1971 { .name = "CNTPS_TVAL_EL1", .state = ARM_CP_STATE_AA64, 1972 .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 0, 1973 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW, 1974 .accessfn = gt_stimer_access, 1975 .readfn = gt_sec_tval_read, 1976 .writefn = gt_sec_tval_write, 1977 .resetfn = gt_sec_timer_reset, 1978 }, 1979 { .name = "CNTPS_CTL_EL1", .state = ARM_CP_STATE_AA64, 1980 .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 1, 1981 .type = ARM_CP_IO, .access = PL1_RW, 1982 .accessfn = gt_stimer_access, 1983 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].ctl), 1984 .resetvalue = 0, 1985 .writefn = gt_sec_ctl_write, .raw_writefn = raw_write, 1986 }, 1987 { .name = "CNTPS_CVAL_EL1", .state = ARM_CP_STATE_AA64, 1988 .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 2, 1989 .type = ARM_CP_IO, .access = PL1_RW, 1990 .accessfn = gt_stimer_access, 1991 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval), 1992 .writefn = gt_sec_cval_write, .raw_writefn = raw_write, 1993 }, 1994 REGINFO_SENTINEL 1995 }; 1996 1997 #else 1998 /* In user-mode none of the generic timer registers are accessible, 1999 * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs, 2000 * so instead just don't register any of them. 2001 */ 2002 static const ARMCPRegInfo generic_timer_cp_reginfo[] = { 2003 REGINFO_SENTINEL 2004 }; 2005 2006 #endif 2007 2008 static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) 2009 { 2010 if (arm_feature(env, ARM_FEATURE_LPAE)) { 2011 raw_write(env, ri, value); 2012 } else if (arm_feature(env, ARM_FEATURE_V7)) { 2013 raw_write(env, ri, value & 0xfffff6ff); 2014 } else { 2015 raw_write(env, ri, value & 0xfffff1ff); 2016 } 2017 } 2018 2019 #ifndef CONFIG_USER_ONLY 2020 /* get_phys_addr() isn't present for user-mode-only targets */ 2021 2022 static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri, 2023 bool isread) 2024 { 2025 if (ri->opc2 & 4) { 2026 /* The ATS12NSO* operations must trap to EL3 if executed in 2027 * Secure EL1 (which can only happen if EL3 is AArch64). 2028 * They are simply UNDEF if executed from NS EL1. 2029 * They function normally from EL2 or EL3. 2030 */ 2031 if (arm_current_el(env) == 1) { 2032 if (arm_is_secure_below_el3(env)) { 2033 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3; 2034 } 2035 return CP_ACCESS_TRAP_UNCATEGORIZED; 2036 } 2037 } 2038 return CP_ACCESS_OK; 2039 } 2040 2041 static uint64_t do_ats_write(CPUARMState *env, uint64_t value, 2042 int access_type, ARMMMUIdx mmu_idx) 2043 { 2044 hwaddr phys_addr; 2045 target_ulong page_size; 2046 int prot; 2047 uint32_t fsr; 2048 bool ret; 2049 uint64_t par64; 2050 MemTxAttrs attrs = {}; 2051 ARMMMUFaultInfo fi = {}; 2052 2053 ret = get_phys_addr(env, value, access_type, mmu_idx, 2054 &phys_addr, &attrs, &prot, &page_size, &fsr, &fi); 2055 if (extended_addresses_enabled(env)) { 2056 /* fsr is a DFSR/IFSR value for the long descriptor 2057 * translation table format, but with WnR always clear. 2058 * Convert it to a 64-bit PAR. 2059 */ 2060 par64 = (1 << 11); /* LPAE bit always set */ 2061 if (!ret) { 2062 par64 |= phys_addr & ~0xfffULL; 2063 if (!attrs.secure) { 2064 par64 |= (1 << 9); /* NS */ 2065 } 2066 /* We don't set the ATTR or SH fields in the PAR. */ 2067 } else { 2068 par64 |= 1; /* F */ 2069 par64 |= (fsr & 0x3f) << 1; /* FS */ 2070 /* Note that S2WLK and FSTAGE are always zero, because we don't 2071 * implement virtualization and therefore there can't be a stage 2 2072 * fault. 2073 */ 2074 } 2075 } else { 2076 /* fsr is a DFSR/IFSR value for the short descriptor 2077 * translation table format (with WnR always clear). 2078 * Convert it to a 32-bit PAR. 2079 */ 2080 if (!ret) { 2081 /* We do not set any attribute bits in the PAR */ 2082 if (page_size == (1 << 24) 2083 && arm_feature(env, ARM_FEATURE_V7)) { 2084 par64 = (phys_addr & 0xff000000) | (1 << 1); 2085 } else { 2086 par64 = phys_addr & 0xfffff000; 2087 } 2088 if (!attrs.secure) { 2089 par64 |= (1 << 9); /* NS */ 2090 } 2091 } else { 2092 par64 = ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) | 2093 ((fsr & 0xf) << 1) | 1; 2094 } 2095 } 2096 return par64; 2097 } 2098 2099 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) 2100 { 2101 int access_type = ri->opc2 & 1; 2102 uint64_t par64; 2103 ARMMMUIdx mmu_idx; 2104 int el = arm_current_el(env); 2105 bool secure = arm_is_secure_below_el3(env); 2106 2107 switch (ri->opc2 & 6) { 2108 case 0: 2109 /* stage 1 current state PL1: ATS1CPR, ATS1CPW */ 2110 switch (el) { 2111 case 3: 2112 mmu_idx = ARMMMUIdx_S1E3; 2113 break; 2114 case 2: 2115 mmu_idx = ARMMMUIdx_S1NSE1; 2116 break; 2117 case 1: 2118 mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1; 2119 break; 2120 default: 2121 g_assert_not_reached(); 2122 } 2123 break; 2124 case 2: 2125 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */ 2126 switch (el) { 2127 case 3: 2128 mmu_idx = ARMMMUIdx_S1SE0; 2129 break; 2130 case 2: 2131 mmu_idx = ARMMMUIdx_S1NSE0; 2132 break; 2133 case 1: 2134 mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0; 2135 break; 2136 default: 2137 g_assert_not_reached(); 2138 } 2139 break; 2140 case 4: 2141 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */ 2142 mmu_idx = ARMMMUIdx_S12NSE1; 2143 break; 2144 case 6: 2145 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */ 2146 mmu_idx = ARMMMUIdx_S12NSE0; 2147 break; 2148 default: 2149 g_assert_not_reached(); 2150 } 2151 2152 par64 = do_ats_write(env, value, access_type, mmu_idx); 2153 2154 A32_BANKED_CURRENT_REG_SET(env, par, par64); 2155 } 2156 2157 static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri, 2158 uint64_t value) 2159 { 2160 int access_type = ri->opc2 & 1; 2161 uint64_t par64; 2162 2163 par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S2NS); 2164 2165 A32_BANKED_CURRENT_REG_SET(env, par, par64); 2166 } 2167 2168 static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri, 2169 bool isread) 2170 { 2171 if (arm_current_el(env) == 3 && !(env->cp15.scr_el3 & SCR_NS)) { 2172 return CP_ACCESS_TRAP; 2173 } 2174 return CP_ACCESS_OK; 2175 } 2176 2177 static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, 2178 uint64_t value) 2179 { 2180 int access_type = ri->opc2 & 1; 2181 ARMMMUIdx mmu_idx; 2182 int secure = arm_is_secure_below_el3(env); 2183 2184 switch (ri->opc2 & 6) { 2185 case 0: 2186 switch (ri->opc1) { 2187 case 0: /* AT S1E1R, AT S1E1W */ 2188 mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1; 2189 break; 2190 case 4: /* AT S1E2R, AT S1E2W */ 2191 mmu_idx = ARMMMUIdx_S1E2; 2192 break; 2193 case 6: /* AT S1E3R, AT S1E3W */ 2194 mmu_idx = ARMMMUIdx_S1E3; 2195 break; 2196 default: 2197 g_assert_not_reached(); 2198 } 2199 break; 2200 case 2: /* AT S1E0R, AT S1E0W */ 2201 mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0; 2202 break; 2203 case 4: /* AT S12E1R, AT S12E1W */ 2204 mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S12NSE1; 2205 break; 2206 case 6: /* AT S12E0R, AT S12E0W */ 2207 mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S12NSE0; 2208 break; 2209 default: 2210 g_assert_not_reached(); 2211 } 2212 2213 env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx); 2214 } 2215 #endif 2216 2217 static const ARMCPRegInfo vapa_cp_reginfo[] = { 2218 { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0, 2219 .access = PL1_RW, .resetvalue = 0, 2220 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s), 2221 offsetoflow32(CPUARMState, cp15.par_ns) }, 2222 .writefn = par_write }, 2223 #ifndef CONFIG_USER_ONLY 2224 /* This underdecoding is safe because the reginfo is NO_RAW. */ 2225 { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY, 2226 .access = PL1_W, .accessfn = ats_access, 2227 .writefn = ats_write, .type = ARM_CP_NO_RAW }, 2228 #endif 2229 REGINFO_SENTINEL 2230 }; 2231 2232 /* Return basic MPU access permission bits. */ 2233 static uint32_t simple_mpu_ap_bits(uint32_t val) 2234 { 2235 uint32_t ret; 2236 uint32_t mask; 2237 int i; 2238 ret = 0; 2239 mask = 3; 2240 for (i = 0; i < 16; i += 2) { 2241 ret |= (val >> i) & mask; 2242 mask <<= 2; 2243 } 2244 return ret; 2245 } 2246 2247 /* Pad basic MPU access permission bits to extended format. */ 2248 static uint32_t extended_mpu_ap_bits(uint32_t val) 2249 { 2250 uint32_t ret; 2251 uint32_t mask; 2252 int i; 2253 ret = 0; 2254 mask = 3; 2255 for (i = 0; i < 16; i += 2) { 2256 ret |= (val & mask) << i; 2257 mask <<= 2; 2258 } 2259 return ret; 2260 } 2261 2262 static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, 2263 uint64_t value) 2264 { 2265 env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value); 2266 } 2267 2268 static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) 2269 { 2270 return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap); 2271 } 2272 2273 static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, 2274 uint64_t value) 2275 { 2276 env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value); 2277 } 2278 2279 static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) 2280 { 2281 return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap); 2282 } 2283 2284 static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri) 2285 { 2286 uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); 2287 2288 if (!u32p) { 2289 return 0; 2290 } 2291 2292 u32p += env->cp15.c6_rgnr; 2293 return *u32p; 2294 } 2295 2296 static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri, 2297 uint64_t value) 2298 { 2299 ARMCPU *cpu = arm_env_get_cpu(env); 2300 uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); 2301 2302 if (!u32p) { 2303 return; 2304 } 2305 2306 u32p += env->cp15.c6_rgnr; 2307 tlb_flush(CPU(cpu), 1); /* Mappings may have changed - purge! */ 2308 *u32p = value; 2309 } 2310 2311 static void pmsav7_reset(CPUARMState *env, const ARMCPRegInfo *ri) 2312 { 2313 ARMCPU *cpu = arm_env_get_cpu(env); 2314 uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); 2315 2316 if (!u32p) { 2317 return; 2318 } 2319 2320 memset(u32p, 0, sizeof(*u32p) * cpu->pmsav7_dregion); 2321 } 2322 2323 static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri, 2324 uint64_t value) 2325 { 2326 ARMCPU *cpu = arm_env_get_cpu(env); 2327 uint32_t nrgs = cpu->pmsav7_dregion; 2328 2329 if (value >= nrgs) { 2330 qemu_log_mask(LOG_GUEST_ERROR, 2331 "PMSAv7 RGNR write >= # supported regions, %" PRIu32 2332 " > %" PRIu32 "\n", (uint32_t)value, nrgs); 2333 return; 2334 } 2335 2336 raw_write(env, ri, value); 2337 } 2338 2339 static const ARMCPRegInfo pmsav7_cp_reginfo[] = { 2340 { .name = "DRBAR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 0, 2341 .access = PL1_RW, .type = ARM_CP_NO_RAW, 2342 .fieldoffset = offsetof(CPUARMState, pmsav7.drbar), 2343 .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset }, 2344 { .name = "DRSR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 2, 2345 .access = PL1_RW, .type = ARM_CP_NO_RAW, 2346 .fieldoffset = offsetof(CPUARMState, pmsav7.drsr), 2347 .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset }, 2348 { .name = "DRACR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 4, 2349 .access = PL1_RW, .type = ARM_CP_NO_RAW, 2350 .fieldoffset = offsetof(CPUARMState, pmsav7.dracr), 2351 .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset }, 2352 { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0, 2353 .access = PL1_RW, 2354 .fieldoffset = offsetof(CPUARMState, cp15.c6_rgnr), 2355 .writefn = pmsav7_rgnr_write }, 2356 REGINFO_SENTINEL 2357 }; 2358 2359 static const ARMCPRegInfo pmsav5_cp_reginfo[] = { 2360 { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, 2361 .access = PL1_RW, .type = ARM_CP_ALIAS, 2362 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap), 2363 .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, }, 2364 { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, 2365 .access = PL1_RW, .type = ARM_CP_ALIAS, 2366 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap), 2367 .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, }, 2368 { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2, 2369 .access = PL1_RW, 2370 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap), 2371 .resetvalue = 0, }, 2372 { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3, 2373 .access = PL1_RW, 2374 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap), 2375 .resetvalue = 0, }, 2376 { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, 2377 .access = PL1_RW, 2378 .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, }, 2379 { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1, 2380 .access = PL1_RW, 2381 .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, }, 2382 /* Protection region base and size registers */ 2383 { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, 2384 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 2385 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) }, 2386 { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0, 2387 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 2388 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) }, 2389 { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0, 2390 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 2391 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) }, 2392 { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0, 2393 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 2394 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) }, 2395 { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0, 2396 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 2397 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) }, 2398 { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0, 2399 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 2400 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) }, 2401 { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0, 2402 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 2403 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) }, 2404 { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0, 2405 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 2406 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) }, 2407 REGINFO_SENTINEL 2408 }; 2409 2410 static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, 2411 uint64_t value) 2412 { 2413 TCR *tcr = raw_ptr(env, ri); 2414 int maskshift = extract32(value, 0, 3); 2415 2416 if (!arm_feature(env, ARM_FEATURE_V8)) { 2417 if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) { 2418 /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when 2419 * using Long-desciptor translation table format */ 2420 value &= ~((7 << 19) | (3 << 14) | (0xf << 3)); 2421 } else if (arm_feature(env, ARM_FEATURE_EL3)) { 2422 /* In an implementation that includes the Security Extensions 2423 * TTBCR has additional fields PD0 [4] and PD1 [5] for 2424 * Short-descriptor translation table format. 2425 */ 2426 value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N; 2427 } else { 2428 value &= TTBCR_N; 2429 } 2430 } 2431 2432 /* Update the masks corresponding to the TCR bank being written 2433 * Note that we always calculate mask and base_mask, but 2434 * they are only used for short-descriptor tables (ie if EAE is 0); 2435 * for long-descriptor tables the TCR fields are used differently 2436 * and the mask and base_mask values are meaningless. 2437 */ 2438 tcr->raw_tcr = value; 2439 tcr->mask = ~(((uint32_t)0xffffffffu) >> maskshift); 2440 tcr->base_mask = ~((uint32_t)0x3fffu >> maskshift); 2441 } 2442 2443 static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, 2444 uint64_t value) 2445 { 2446 ARMCPU *cpu = arm_env_get_cpu(env); 2447 2448 if (arm_feature(env, ARM_FEATURE_LPAE)) { 2449 /* With LPAE the TTBCR could result in a change of ASID 2450 * via the TTBCR.A1 bit, so do a TLB flush. 2451 */ 2452 tlb_flush(CPU(cpu), 1); 2453 } 2454 vmsa_ttbcr_raw_write(env, ri, value); 2455 } 2456 2457 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) 2458 { 2459 TCR *tcr = raw_ptr(env, ri); 2460 2461 /* Reset both the TCR as well as the masks corresponding to the bank of 2462 * the TCR being reset. 2463 */ 2464 tcr->raw_tcr = 0; 2465 tcr->mask = 0; 2466 tcr->base_mask = 0xffffc000u; 2467 } 2468 2469 static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, 2470 uint64_t value) 2471 { 2472 ARMCPU *cpu = arm_env_get_cpu(env); 2473 TCR *tcr = raw_ptr(env, ri); 2474 2475 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */ 2476 tlb_flush(CPU(cpu), 1); 2477 tcr->raw_tcr = value; 2478 } 2479 2480 static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, 2481 uint64_t value) 2482 { 2483 /* 64 bit accesses to the TTBRs can change the ASID and so we 2484 * must flush the TLB. 2485 */ 2486 if (cpreg_field_is_64bit(ri)) { 2487 ARMCPU *cpu = arm_env_get_cpu(env); 2488 2489 tlb_flush(CPU(cpu), 1); 2490 } 2491 raw_write(env, ri, value); 2492 } 2493 2494 static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, 2495 uint64_t value) 2496 { 2497 ARMCPU *cpu = arm_env_get_cpu(env); 2498 CPUState *cs = CPU(cpu); 2499 2500 /* Accesses to VTTBR may change the VMID so we must flush the TLB. */ 2501 if (raw_read(env, ri) != value) { 2502 tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, 2503 ARMMMUIdx_S2NS, -1); 2504 raw_write(env, ri, value); 2505 } 2506 } 2507 2508 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = { 2509 { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, 2510 .access = PL1_RW, .type = ARM_CP_ALIAS, 2511 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s), 2512 offsetoflow32(CPUARMState, cp15.dfsr_ns) }, }, 2513 { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, 2514 .access = PL1_RW, .resetvalue = 0, 2515 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s), 2516 offsetoflow32(CPUARMState, cp15.ifsr_ns) } }, 2517 { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0, 2518 .access = PL1_RW, .resetvalue = 0, 2519 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s), 2520 offsetof(CPUARMState, cp15.dfar_ns) } }, 2521 { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64, 2522 .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, 2523 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]), 2524 .resetvalue = 0, }, 2525 REGINFO_SENTINEL 2526 }; 2527 2528 static const ARMCPRegInfo vmsa_cp_reginfo[] = { 2529 { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64, 2530 .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0, 2531 .access = PL1_RW, 2532 .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, }, 2533 { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH, 2534 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0, 2535 .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, 2536 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), 2537 offsetof(CPUARMState, cp15.ttbr0_ns) } }, 2538 { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH, 2539 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1, 2540 .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, 2541 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), 2542 offsetof(CPUARMState, cp15.ttbr1_ns) } }, 2543 { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64, 2544 .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, 2545 .access = PL1_RW, .writefn = vmsa_tcr_el1_write, 2546 .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write, 2547 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) }, 2548 { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, 2549 .access = PL1_RW, .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write, 2550 .raw_writefn = vmsa_ttbcr_raw_write, 2551 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]), 2552 offsetoflow32(CPUARMState, cp15.tcr_el[1])} }, 2553 REGINFO_SENTINEL 2554 }; 2555 2556 static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri, 2557 uint64_t value) 2558 { 2559 env->cp15.c15_ticonfig = value & 0xe7; 2560 /* The OS_TYPE bit in this register changes the reported CPUID! */ 2561 env->cp15.c0_cpuid = (value & (1 << 5)) ? 2562 ARM_CPUID_TI915T : ARM_CPUID_TI925T; 2563 } 2564 2565 static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri, 2566 uint64_t value) 2567 { 2568 env->cp15.c15_threadid = value & 0xffff; 2569 } 2570 2571 static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri, 2572 uint64_t value) 2573 { 2574 /* Wait-for-interrupt (deprecated) */ 2575 cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT); 2576 } 2577 2578 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, 2579 uint64_t value) 2580 { 2581 /* On OMAP there are registers indicating the max/min index of dcache lines 2582 * containing a dirty line; cache flush operations have to reset these. 2583 */ 2584 env->cp15.c15_i_max = 0x000; 2585 env->cp15.c15_i_min = 0xff0; 2586 } 2587 2588 static const ARMCPRegInfo omap_cp_reginfo[] = { 2589 { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY, 2590 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE, 2591 .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]), 2592 .resetvalue = 0, }, 2593 { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 2594 .access = PL1_RW, .type = ARM_CP_NOP }, 2595 { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 2596 .access = PL1_RW, 2597 .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0, 2598 .writefn = omap_ticonfig_write }, 2599 { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0, 2600 .access = PL1_RW, 2601 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, }, 2602 { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0, 2603 .access = PL1_RW, .resetvalue = 0xff0, 2604 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) }, 2605 { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0, 2606 .access = PL1_RW, 2607 .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0, 2608 .writefn = omap_threadid_write }, 2609 { .name = "TI925T_STATUS", .cp = 15, .crn = 15, 2610 .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW, 2611 .type = ARM_CP_NO_RAW, 2612 .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, }, 2613 /* TODO: Peripheral port remap register: 2614 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller 2615 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff), 2616 * when MMU is off. 2617 */ 2618 { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, 2619 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, 2620 .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW, 2621 .writefn = omap_cachemaint_write }, 2622 { .name = "C9", .cp = 15, .crn = 9, 2623 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, 2624 .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 }, 2625 REGINFO_SENTINEL 2626 }; 2627 2628 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri, 2629 uint64_t value) 2630 { 2631 env->cp15.c15_cpar = value & 0x3fff; 2632 } 2633 2634 static const ARMCPRegInfo xscale_cp_reginfo[] = { 2635 { .name = "XSCALE_CPAR", 2636 .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW, 2637 .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0, 2638 .writefn = xscale_cpar_write, }, 2639 { .name = "XSCALE_AUXCR", 2640 .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, 2641 .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr), 2642 .resetvalue = 0, }, 2643 /* XScale specific cache-lockdown: since we have no cache we NOP these 2644 * and hope the guest does not really rely on cache behaviour. 2645 */ 2646 { .name = "XSCALE_LOCK_ICACHE_LINE", 2647 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, 2648 .access = PL1_W, .type = ARM_CP_NOP }, 2649 { .name = "XSCALE_UNLOCK_ICACHE", 2650 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, 2651 .access = PL1_W, .type = ARM_CP_NOP }, 2652 { .name = "XSCALE_DCACHE_LOCK", 2653 .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0, 2654 .access = PL1_RW, .type = ARM_CP_NOP }, 2655 { .name = "XSCALE_UNLOCK_DCACHE", 2656 .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1, 2657 .access = PL1_W, .type = ARM_CP_NOP }, 2658 REGINFO_SENTINEL 2659 }; 2660 2661 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = { 2662 /* RAZ/WI the whole crn=15 space, when we don't have a more specific 2663 * implementation of this implementation-defined space. 2664 * Ideally this should eventually disappear in favour of actually 2665 * implementing the correct behaviour for all cores. 2666 */ 2667 { .name = "C15_IMPDEF", .cp = 15, .crn = 15, 2668 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, 2669 .access = PL1_RW, 2670 .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE, 2671 .resetvalue = 0 }, 2672 REGINFO_SENTINEL 2673 }; 2674 2675 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = { 2676 /* Cache status: RAZ because we have no cache so it's always clean */ 2677 { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6, 2678 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, 2679 .resetvalue = 0 }, 2680 REGINFO_SENTINEL 2681 }; 2682 2683 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = { 2684 /* We never have a a block transfer operation in progress */ 2685 { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4, 2686 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, 2687 .resetvalue = 0 }, 2688 /* The cache ops themselves: these all NOP for QEMU */ 2689 { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0, 2690 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, 2691 { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0, 2692 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, 2693 { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0, 2694 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, 2695 { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1, 2696 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, 2697 { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2, 2698 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, 2699 { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0, 2700 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, 2701 REGINFO_SENTINEL 2702 }; 2703 2704 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = { 2705 /* The cache test-and-clean instructions always return (1 << 30) 2706 * to indicate that there are no dirty cache lines. 2707 */ 2708 { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3, 2709 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, 2710 .resetvalue = (1 << 30) }, 2711 { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3, 2712 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, 2713 .resetvalue = (1 << 30) }, 2714 REGINFO_SENTINEL 2715 }; 2716 2717 static const ARMCPRegInfo strongarm_cp_reginfo[] = { 2718 /* Ignore ReadBuffer accesses */ 2719 { .name = "C9_READBUFFER", .cp = 15, .crn = 9, 2720 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, 2721 .access = PL1_RW, .resetvalue = 0, 2722 .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW }, 2723 REGINFO_SENTINEL 2724 }; 2725 2726 static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri) 2727 { 2728 ARMCPU *cpu = arm_env_get_cpu(env); 2729 unsigned int cur_el = arm_current_el(env); 2730 bool secure = arm_is_secure(env); 2731 2732 if (arm_feature(&cpu->env, ARM_FEATURE_EL2) && !secure && cur_el == 1) { 2733 return env->cp15.vpidr_el2; 2734 } 2735 return raw_read(env, ri); 2736 } 2737 2738 static uint64_t mpidr_read_val(CPUARMState *env) 2739 { 2740 ARMCPU *cpu = ARM_CPU(arm_env_get_cpu(env)); 2741 uint64_t mpidr = cpu->mp_affinity; 2742 2743 if (arm_feature(env, ARM_FEATURE_V7MP)) { 2744 mpidr |= (1U << 31); 2745 /* Cores which are uniprocessor (non-coherent) 2746 * but still implement the MP extensions set 2747 * bit 30. (For instance, Cortex-R5). 2748 */ 2749 if (cpu->mp_is_up) { 2750 mpidr |= (1u << 30); 2751 } 2752 } 2753 return mpidr; 2754 } 2755 2756 static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) 2757 { 2758 unsigned int cur_el = arm_current_el(env); 2759 bool secure = arm_is_secure(env); 2760 2761 if (arm_feature(env, ARM_FEATURE_EL2) && !secure && cur_el == 1) { 2762 return env->cp15.vmpidr_el2; 2763 } 2764 return mpidr_read_val(env); 2765 } 2766 2767 static const ARMCPRegInfo mpidr_cp_reginfo[] = { 2768 { .name = "MPIDR", .state = ARM_CP_STATE_BOTH, 2769 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5, 2770 .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW }, 2771 REGINFO_SENTINEL 2772 }; 2773 2774 static const ARMCPRegInfo lpae_cp_reginfo[] = { 2775 /* NOP AMAIR0/1 */ 2776 { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH, 2777 .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0, 2778 .access = PL1_RW, .type = ARM_CP_CONST, 2779 .resetvalue = 0 }, 2780 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */ 2781 { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1, 2782 .access = PL1_RW, .type = ARM_CP_CONST, 2783 .resetvalue = 0 }, 2784 { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0, 2785 .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0, 2786 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s), 2787 offsetof(CPUARMState, cp15.par_ns)} }, 2788 { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0, 2789 .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, 2790 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), 2791 offsetof(CPUARMState, cp15.ttbr0_ns) }, 2792 .writefn = vmsa_ttbr_write, }, 2793 { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1, 2794 .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, 2795 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), 2796 offsetof(CPUARMState, cp15.ttbr1_ns) }, 2797 .writefn = vmsa_ttbr_write, }, 2798 REGINFO_SENTINEL 2799 }; 2800 2801 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri) 2802 { 2803 return vfp_get_fpcr(env); 2804 } 2805 2806 static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri, 2807 uint64_t value) 2808 { 2809 vfp_set_fpcr(env, value); 2810 } 2811 2812 static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri) 2813 { 2814 return vfp_get_fpsr(env); 2815 } 2816 2817 static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri, 2818 uint64_t value) 2819 { 2820 vfp_set_fpsr(env, value); 2821 } 2822 2823 static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri, 2824 bool isread) 2825 { 2826 if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) { 2827 return CP_ACCESS_TRAP; 2828 } 2829 return CP_ACCESS_OK; 2830 } 2831 2832 static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri, 2833 uint64_t value) 2834 { 2835 env->daif = value & PSTATE_DAIF; 2836 } 2837 2838 static CPAccessResult aa64_cacheop_access(CPUARMState *env, 2839 const ARMCPRegInfo *ri, 2840 bool isread) 2841 { 2842 /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless 2843 * SCTLR_EL1.UCI is set. 2844 */ 2845 if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCI)) { 2846 return CP_ACCESS_TRAP; 2847 } 2848 return CP_ACCESS_OK; 2849 } 2850 2851 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions 2852 * Page D4-1736 (DDI0487A.b) 2853 */ 2854 2855 static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri, 2856 uint64_t value) 2857 { 2858 ARMCPU *cpu = arm_env_get_cpu(env); 2859 CPUState *cs = CPU(cpu); 2860 2861 if (arm_is_secure_below_el3(env)) { 2862 tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1); 2863 } else { 2864 tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, -1); 2865 } 2866 } 2867 2868 static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, 2869 uint64_t value) 2870 { 2871 bool sec = arm_is_secure_below_el3(env); 2872 CPUState *other_cs; 2873 2874 CPU_FOREACH(other_cs) { 2875 if (sec) { 2876 tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1); 2877 } else { 2878 tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1, 2879 ARMMMUIdx_S12NSE0, -1); 2880 } 2881 } 2882 } 2883 2884 static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, 2885 uint64_t value) 2886 { 2887 /* Note that the 'ALL' scope must invalidate both stage 1 and 2888 * stage 2 translations, whereas most other scopes only invalidate 2889 * stage 1 translations. 2890 */ 2891 ARMCPU *cpu = arm_env_get_cpu(env); 2892 CPUState *cs = CPU(cpu); 2893 2894 if (arm_is_secure_below_el3(env)) { 2895 tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1); 2896 } else { 2897 if (arm_feature(env, ARM_FEATURE_EL2)) { 2898 tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, 2899 ARMMMUIdx_S2NS, -1); 2900 } else { 2901 tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, -1); 2902 } 2903 } 2904 } 2905 2906 static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri, 2907 uint64_t value) 2908 { 2909 ARMCPU *cpu = arm_env_get_cpu(env); 2910 CPUState *cs = CPU(cpu); 2911 2912 tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1E2, -1); 2913 } 2914 2915 static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri, 2916 uint64_t value) 2917 { 2918 ARMCPU *cpu = arm_env_get_cpu(env); 2919 CPUState *cs = CPU(cpu); 2920 2921 tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1E3, -1); 2922 } 2923 2924 static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, 2925 uint64_t value) 2926 { 2927 /* Note that the 'ALL' scope must invalidate both stage 1 and 2928 * stage 2 translations, whereas most other scopes only invalidate 2929 * stage 1 translations. 2930 */ 2931 bool sec = arm_is_secure_below_el3(env); 2932 bool has_el2 = arm_feature(env, ARM_FEATURE_EL2); 2933 CPUState *other_cs; 2934 2935 CPU_FOREACH(other_cs) { 2936 if (sec) { 2937 tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1); 2938 } else if (has_el2) { 2939 tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1, 2940 ARMMMUIdx_S12NSE0, ARMMMUIdx_S2NS, -1); 2941 } else { 2942 tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1, 2943 ARMMMUIdx_S12NSE0, -1); 2944 } 2945 } 2946 } 2947 2948 static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri, 2949 uint64_t value) 2950 { 2951 CPUState *other_cs; 2952 2953 CPU_FOREACH(other_cs) { 2954 tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1E2, -1); 2955 } 2956 } 2957 2958 static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri, 2959 uint64_t value) 2960 { 2961 CPUState *other_cs; 2962 2963 CPU_FOREACH(other_cs) { 2964 tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1E3, -1); 2965 } 2966 } 2967 2968 static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri, 2969 uint64_t value) 2970 { 2971 /* Invalidate by VA, EL1&0 (AArch64 version). 2972 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1, 2973 * since we don't support flush-for-specific-ASID-only or 2974 * flush-last-level-only. 2975 */ 2976 ARMCPU *cpu = arm_env_get_cpu(env); 2977 CPUState *cs = CPU(cpu); 2978 uint64_t pageaddr = sextract64(value << 12, 0, 56); 2979 2980 if (arm_is_secure_below_el3(env)) { 2981 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1SE1, 2982 ARMMMUIdx_S1SE0, -1); 2983 } else { 2984 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S12NSE1, 2985 ARMMMUIdx_S12NSE0, -1); 2986 } 2987 } 2988 2989 static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri, 2990 uint64_t value) 2991 { 2992 /* Invalidate by VA, EL2 2993 * Currently handles both VAE2 and VALE2, since we don't support 2994 * flush-last-level-only. 2995 */ 2996 ARMCPU *cpu = arm_env_get_cpu(env); 2997 CPUState *cs = CPU(cpu); 2998 uint64_t pageaddr = sextract64(value << 12, 0, 56); 2999 3000 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1E2, -1); 3001 } 3002 3003 static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, 3004 uint64_t value) 3005 { 3006 /* Invalidate by VA, EL3 3007 * Currently handles both VAE3 and VALE3, since we don't support 3008 * flush-last-level-only. 3009 */ 3010 ARMCPU *cpu = arm_env_get_cpu(env); 3011 CPUState *cs = CPU(cpu); 3012 uint64_t pageaddr = sextract64(value << 12, 0, 56); 3013 3014 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1E3, -1); 3015 } 3016 3017 static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri, 3018 uint64_t value) 3019 { 3020 bool sec = arm_is_secure_below_el3(env); 3021 CPUState *other_cs; 3022 uint64_t pageaddr = sextract64(value << 12, 0, 56); 3023 3024 CPU_FOREACH(other_cs) { 3025 if (sec) { 3026 tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1SE1, 3027 ARMMMUIdx_S1SE0, -1); 3028 } else { 3029 tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S12NSE1, 3030 ARMMMUIdx_S12NSE0, -1); 3031 } 3032 } 3033 } 3034 3035 static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri, 3036 uint64_t value) 3037 { 3038 CPUState *other_cs; 3039 uint64_t pageaddr = sextract64(value << 12, 0, 56); 3040 3041 CPU_FOREACH(other_cs) { 3042 tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E2, -1); 3043 } 3044 } 3045 3046 static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri, 3047 uint64_t value) 3048 { 3049 CPUState *other_cs; 3050 uint64_t pageaddr = sextract64(value << 12, 0, 56); 3051 3052 CPU_FOREACH(other_cs) { 3053 tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E3, -1); 3054 } 3055 } 3056 3057 static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri, 3058 uint64_t value) 3059 { 3060 /* Invalidate by IPA. This has to invalidate any structures that 3061 * contain only stage 2 translation information, but does not need 3062 * to apply to structures that contain combined stage 1 and stage 2 3063 * translation information. 3064 * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero. 3065 */ 3066 ARMCPU *cpu = arm_env_get_cpu(env); 3067 CPUState *cs = CPU(cpu); 3068 uint64_t pageaddr; 3069 3070 if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { 3071 return; 3072 } 3073 3074 pageaddr = sextract64(value << 12, 0, 48); 3075 3076 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S2NS, -1); 3077 } 3078 3079 static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri, 3080 uint64_t value) 3081 { 3082 CPUState *other_cs; 3083 uint64_t pageaddr; 3084 3085 if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { 3086 return; 3087 } 3088 3089 pageaddr = sextract64(value << 12, 0, 48); 3090 3091 CPU_FOREACH(other_cs) { 3092 tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S2NS, -1); 3093 } 3094 } 3095 3096 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri, 3097 bool isread) 3098 { 3099 /* We don't implement EL2, so the only control on DC ZVA is the 3100 * bit in the SCTLR which can prohibit access for EL0. 3101 */ 3102 if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_DZE)) { 3103 return CP_ACCESS_TRAP; 3104 } 3105 return CP_ACCESS_OK; 3106 } 3107 3108 static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri) 3109 { 3110 ARMCPU *cpu = arm_env_get_cpu(env); 3111 int dzp_bit = 1 << 4; 3112 3113 /* DZP indicates whether DC ZVA access is allowed */ 3114 if (aa64_zva_access(env, NULL, false) == CP_ACCESS_OK) { 3115 dzp_bit = 0; 3116 } 3117 return cpu->dcz_blocksize | dzp_bit; 3118 } 3119 3120 static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, 3121 bool isread) 3122 { 3123 if (!(env->pstate & PSTATE_SP)) { 3124 /* Access to SP_EL0 is undefined if it's being used as 3125 * the stack pointer. 3126 */ 3127 return CP_ACCESS_TRAP_UNCATEGORIZED; 3128 } 3129 return CP_ACCESS_OK; 3130 } 3131 3132 static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri) 3133 { 3134 return env->pstate & PSTATE_SP; 3135 } 3136 3137 static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) 3138 { 3139 update_spsel(env, val); 3140 } 3141 3142 static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, 3143 uint64_t value) 3144 { 3145 ARMCPU *cpu = arm_env_get_cpu(env); 3146 3147 if (raw_read(env, ri) == value) { 3148 /* Skip the TLB flush if nothing actually changed; Linux likes 3149 * to do a lot of pointless SCTLR writes. 3150 */ 3151 return; 3152 } 3153 3154 raw_write(env, ri, value); 3155 /* ??? Lots of these bits are not implemented. */ 3156 /* This may enable/disable the MMU, so do a TLB flush. */ 3157 tlb_flush(CPU(cpu), 1); 3158 } 3159 3160 static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri, 3161 bool isread) 3162 { 3163 if ((env->cp15.cptr_el[2] & CPTR_TFP) && arm_current_el(env) == 2) { 3164 return CP_ACCESS_TRAP_FP_EL2; 3165 } 3166 if (env->cp15.cptr_el[3] & CPTR_TFP) { 3167 return CP_ACCESS_TRAP_FP_EL3; 3168 } 3169 return CP_ACCESS_OK; 3170 } 3171 3172 static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri, 3173 uint64_t value) 3174 { 3175 env->cp15.mdcr_el3 = value & SDCR_VALID_MASK; 3176 } 3177 3178 static const ARMCPRegInfo v8_cp_reginfo[] = { 3179 /* Minimal set of EL0-visible registers. This will need to be expanded 3180 * significantly for system emulation of AArch64 CPUs. 3181 */ 3182 { .name = "NZCV", .state = ARM_CP_STATE_AA64, 3183 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2, 3184 .access = PL0_RW, .type = ARM_CP_NZCV }, 3185 { .name = "DAIF", .state = ARM_CP_STATE_AA64, 3186 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2, 3187 .type = ARM_CP_NO_RAW, 3188 .access = PL0_RW, .accessfn = aa64_daif_access, 3189 .fieldoffset = offsetof(CPUARMState, daif), 3190 .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore }, 3191 { .name = "FPCR", .state = ARM_CP_STATE_AA64, 3192 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4, 3193 .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write }, 3194 { .name = "FPSR", .state = ARM_CP_STATE_AA64, 3195 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4, 3196 .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write }, 3197 { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64, 3198 .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0, 3199 .access = PL0_R, .type = ARM_CP_NO_RAW, 3200 .readfn = aa64_dczid_read }, 3201 { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64, 3202 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1, 3203 .access = PL0_W, .type = ARM_CP_DC_ZVA, 3204 #ifndef CONFIG_USER_ONLY 3205 /* Avoid overhead of an access check that always passes in user-mode */ 3206 .accessfn = aa64_zva_access, 3207 #endif 3208 }, 3209 { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64, 3210 .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2, 3211 .access = PL1_R, .type = ARM_CP_CURRENTEL }, 3212 /* Cache ops: all NOPs since we don't emulate caches */ 3213 { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64, 3214 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, 3215 .access = PL1_W, .type = ARM_CP_NOP }, 3216 { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64, 3217 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, 3218 .access = PL1_W, .type = ARM_CP_NOP }, 3219 { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64, 3220 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1, 3221 .access = PL0_W, .type = ARM_CP_NOP, 3222 .accessfn = aa64_cacheop_access }, 3223 { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64, 3224 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, 3225 .access = PL1_W, .type = ARM_CP_NOP }, 3226 { .name = "DC_ISW", .state = ARM_CP_STATE_AA64, 3227 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, 3228 .access = PL1_W, .type = ARM_CP_NOP }, 3229 { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64, 3230 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1, 3231 .access = PL0_W, .type = ARM_CP_NOP, 3232 .accessfn = aa64_cacheop_access }, 3233 { .name = "DC_CSW", .state = ARM_CP_STATE_AA64, 3234 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, 3235 .access = PL1_W, .type = ARM_CP_NOP }, 3236 { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64, 3237 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1, 3238 .access = PL0_W, .type = ARM_CP_NOP, 3239 .accessfn = aa64_cacheop_access }, 3240 { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64, 3241 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1, 3242 .access = PL0_W, .type = ARM_CP_NOP, 3243 .accessfn = aa64_cacheop_access }, 3244 { .name = "DC_CISW", .state = ARM_CP_STATE_AA64, 3245 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, 3246 .access = PL1_W, .type = ARM_CP_NOP }, 3247 /* TLBI operations */ 3248 { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64, 3249 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, 3250 .access = PL1_W, .type = ARM_CP_NO_RAW, 3251 .writefn = tlbi_aa64_vmalle1is_write }, 3252 { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64, 3253 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, 3254 .access = PL1_W, .type = ARM_CP_NO_RAW, 3255 .writefn = tlbi_aa64_vae1is_write }, 3256 { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64, 3257 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, 3258 .access = PL1_W, .type = ARM_CP_NO_RAW, 3259 .writefn = tlbi_aa64_vmalle1is_write }, 3260 { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64, 3261 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, 3262 .access = PL1_W, .type = ARM_CP_NO_RAW, 3263 .writefn = tlbi_aa64_vae1is_write }, 3264 { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64, 3265 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, 3266 .access = PL1_W, .type = ARM_CP_NO_RAW, 3267 .writefn = tlbi_aa64_vae1is_write }, 3268 { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64, 3269 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, 3270 .access = PL1_W, .type = ARM_CP_NO_RAW, 3271 .writefn = tlbi_aa64_vae1is_write }, 3272 { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64, 3273 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, 3274 .access = PL1_W, .type = ARM_CP_NO_RAW, 3275 .writefn = tlbi_aa64_vmalle1_write }, 3276 { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64, 3277 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, 3278 .access = PL1_W, .type = ARM_CP_NO_RAW, 3279 .writefn = tlbi_aa64_vae1_write }, 3280 { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64, 3281 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, 3282 .access = PL1_W, .type = ARM_CP_NO_RAW, 3283 .writefn = tlbi_aa64_vmalle1_write }, 3284 { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64, 3285 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, 3286 .access = PL1_W, .type = ARM_CP_NO_RAW, 3287 .writefn = tlbi_aa64_vae1_write }, 3288 { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64, 3289 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, 3290 .access = PL1_W, .type = ARM_CP_NO_RAW, 3291 .writefn = tlbi_aa64_vae1_write }, 3292 { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64, 3293 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, 3294 .access = PL1_W, .type = ARM_CP_NO_RAW, 3295 .writefn = tlbi_aa64_vae1_write }, 3296 { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64, 3297 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1, 3298 .access = PL2_W, .type = ARM_CP_NO_RAW, 3299 .writefn = tlbi_aa64_ipas2e1is_write }, 3300 { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64, 3301 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5, 3302 .access = PL2_W, .type = ARM_CP_NO_RAW, 3303 .writefn = tlbi_aa64_ipas2e1is_write }, 3304 { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64, 3305 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4, 3306 .access = PL2_W, .type = ARM_CP_NO_RAW, 3307 .writefn = tlbi_aa64_alle1is_write }, 3308 { .name = "TLBI_VMALLS12E1IS", .state = ARM_CP_STATE_AA64, 3309 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6, 3310 .access = PL2_W, .type = ARM_CP_NO_RAW, 3311 .writefn = tlbi_aa64_alle1is_write }, 3312 { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64, 3313 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1, 3314 .access = PL2_W, .type = ARM_CP_NO_RAW, 3315 .writefn = tlbi_aa64_ipas2e1_write }, 3316 { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64, 3317 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5, 3318 .access = PL2_W, .type = ARM_CP_NO_RAW, 3319 .writefn = tlbi_aa64_ipas2e1_write }, 3320 { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64, 3321 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4, 3322 .access = PL2_W, .type = ARM_CP_NO_RAW, 3323 .writefn = tlbi_aa64_alle1_write }, 3324 { .name = "TLBI_VMALLS12E1", .state = ARM_CP_STATE_AA64, 3325 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6, 3326 .access = PL2_W, .type = ARM_CP_NO_RAW, 3327 .writefn = tlbi_aa64_alle1is_write }, 3328 #ifndef CONFIG_USER_ONLY 3329 /* 64 bit address translation operations */ 3330 { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64, 3331 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0, 3332 .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3333 { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64, 3334 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1, 3335 .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3336 { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64, 3337 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2, 3338 .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3339 { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64, 3340 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3, 3341 .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3342 { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64, 3343 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4, 3344 .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3345 { .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64, 3346 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 5, 3347 .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3348 { .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64, 3349 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 6, 3350 .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3351 { .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64, 3352 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 7, 3353 .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3354 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */ 3355 { .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64, 3356 .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 0, 3357 .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3358 { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64, 3359 .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1, 3360 .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3361 { .name = "PAR_EL1", .state = ARM_CP_STATE_AA64, 3362 .type = ARM_CP_ALIAS, 3363 .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0, 3364 .access = PL1_RW, .resetvalue = 0, 3365 .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]), 3366 .writefn = par_write }, 3367 #endif 3368 /* TLB invalidate last level of translation table walk */ 3369 { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, 3370 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write }, 3371 { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, 3372 .type = ARM_CP_NO_RAW, .access = PL1_W, 3373 .writefn = tlbimvaa_is_write }, 3374 { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, 3375 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, 3376 { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, 3377 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write }, 3378 { .name = "TLBIMVALH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, 3379 .type = ARM_CP_NO_RAW, .access = PL2_W, 3380 .writefn = tlbimva_hyp_write }, 3381 { .name = "TLBIMVALHIS", 3382 .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, 3383 .type = ARM_CP_NO_RAW, .access = PL2_W, 3384 .writefn = tlbimva_hyp_is_write }, 3385 { .name = "TLBIIPAS2", 3386 .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1, 3387 .type = ARM_CP_NO_RAW, .access = PL2_W, 3388 .writefn = tlbiipas2_write }, 3389 { .name = "TLBIIPAS2IS", 3390 .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1, 3391 .type = ARM_CP_NO_RAW, .access = PL2_W, 3392 .writefn = tlbiipas2_is_write }, 3393 { .name = "TLBIIPAS2L", 3394 .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5, 3395 .type = ARM_CP_NO_RAW, .access = PL2_W, 3396 .writefn = tlbiipas2_write }, 3397 { .name = "TLBIIPAS2LIS", 3398 .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5, 3399 .type = ARM_CP_NO_RAW, .access = PL2_W, 3400 .writefn = tlbiipas2_is_write }, 3401 /* 32 bit cache operations */ 3402 { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, 3403 .type = ARM_CP_NOP, .access = PL1_W }, 3404 { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6, 3405 .type = ARM_CP_NOP, .access = PL1_W }, 3406 { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, 3407 .type = ARM_CP_NOP, .access = PL1_W }, 3408 { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1, 3409 .type = ARM_CP_NOP, .access = PL1_W }, 3410 { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6, 3411 .type = ARM_CP_NOP, .access = PL1_W }, 3412 { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7, 3413 .type = ARM_CP_NOP, .access = PL1_W }, 3414 { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, 3415 .type = ARM_CP_NOP, .access = PL1_W }, 3416 { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, 3417 .type = ARM_CP_NOP, .access = PL1_W }, 3418 { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1, 3419 .type = ARM_CP_NOP, .access = PL1_W }, 3420 { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, 3421 .type = ARM_CP_NOP, .access = PL1_W }, 3422 { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1, 3423 .type = ARM_CP_NOP, .access = PL1_W }, 3424 { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1, 3425 .type = ARM_CP_NOP, .access = PL1_W }, 3426 { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, 3427 .type = ARM_CP_NOP, .access = PL1_W }, 3428 /* MMU Domain access control / MPU write buffer control */ 3429 { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0, 3430 .access = PL1_RW, .resetvalue = 0, 3431 .writefn = dacr_write, .raw_writefn = raw_write, 3432 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s), 3433 offsetoflow32(CPUARMState, cp15.dacr_ns) } }, 3434 { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64, 3435 .type = ARM_CP_ALIAS, 3436 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1, 3437 .access = PL1_RW, 3438 .fieldoffset = offsetof(CPUARMState, elr_el[1]) }, 3439 { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64, 3440 .type = ARM_CP_ALIAS, 3441 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0, 3442 .access = PL1_RW, 3443 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_SVC]) }, 3444 /* We rely on the access checks not allowing the guest to write to the 3445 * state field when SPSel indicates that it's being used as the stack 3446 * pointer. 3447 */ 3448 { .name = "SP_EL0", .state = ARM_CP_STATE_AA64, 3449 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0, 3450 .access = PL1_RW, .accessfn = sp_el0_access, 3451 .type = ARM_CP_ALIAS, 3452 .fieldoffset = offsetof(CPUARMState, sp_el[0]) }, 3453 { .name = "SP_EL1", .state = ARM_CP_STATE_AA64, 3454 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0, 3455 .access = PL2_RW, .type = ARM_CP_ALIAS, 3456 .fieldoffset = offsetof(CPUARMState, sp_el[1]) }, 3457 { .name = "SPSel", .state = ARM_CP_STATE_AA64, 3458 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0, 3459 .type = ARM_CP_NO_RAW, 3460 .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write }, 3461 { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64, 3462 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0, 3463 .type = ARM_CP_ALIAS, 3464 .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]), 3465 .access = PL2_RW, .accessfn = fpexc32_access }, 3466 { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64, 3467 .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0, 3468 .access = PL2_RW, .resetvalue = 0, 3469 .writefn = dacr_write, .raw_writefn = raw_write, 3470 .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) }, 3471 { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64, 3472 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1, 3473 .access = PL2_RW, .resetvalue = 0, 3474 .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) }, 3475 { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64, 3476 .type = ARM_CP_ALIAS, 3477 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 0, 3478 .access = PL2_RW, 3479 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_IRQ]) }, 3480 { .name = "SPSR_ABT", .state = ARM_CP_STATE_AA64, 3481 .type = ARM_CP_ALIAS, 3482 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 1, 3483 .access = PL2_RW, 3484 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_ABT]) }, 3485 { .name = "SPSR_UND", .state = ARM_CP_STATE_AA64, 3486 .type = ARM_CP_ALIAS, 3487 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 2, 3488 .access = PL2_RW, 3489 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_UND]) }, 3490 { .name = "SPSR_FIQ", .state = ARM_CP_STATE_AA64, 3491 .type = ARM_CP_ALIAS, 3492 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 3, 3493 .access = PL2_RW, 3494 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) }, 3495 { .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64, 3496 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1, 3497 .resetvalue = 0, 3498 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) }, 3499 { .name = "SDCR", .type = ARM_CP_ALIAS, 3500 .cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1, 3501 .access = PL1_RW, .accessfn = access_trap_aa32s_el1, 3502 .writefn = sdcr_write, 3503 .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) }, 3504 REGINFO_SENTINEL 3505 }; 3506 3507 /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */ 3508 static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { 3509 { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64, 3510 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, 3511 .access = PL2_RW, 3512 .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, 3513 { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64, 3514 .type = ARM_CP_NO_RAW, 3515 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, 3516 .access = PL2_RW, 3517 .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, 3518 { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH, 3519 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, 3520 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3521 { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH, 3522 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0, 3523 .access = PL2_RW, .type = ARM_CP_CONST, 3524 .resetvalue = 0 }, 3525 { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, 3526 .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, 3527 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3528 { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH, 3529 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0, 3530 .access = PL2_RW, .type = ARM_CP_CONST, 3531 .resetvalue = 0 }, 3532 { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, 3533 .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, 3534 .access = PL2_RW, .type = ARM_CP_CONST, 3535 .resetvalue = 0 }, 3536 { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH, 3537 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0, 3538 .access = PL2_RW, .type = ARM_CP_CONST, 3539 .resetvalue = 0 }, 3540 { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH, 3541 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1, 3542 .access = PL2_RW, .type = ARM_CP_CONST, 3543 .resetvalue = 0 }, 3544 { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, 3545 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, 3546 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3547 { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH, 3548 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, 3549 .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, 3550 .type = ARM_CP_CONST, .resetvalue = 0 }, 3551 { .name = "VTTBR", .state = ARM_CP_STATE_AA32, 3552 .cp = 15, .opc1 = 6, .crm = 2, 3553 .access = PL2_RW, .accessfn = access_el3_aa32ns, 3554 .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 3555 { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64, 3556 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0, 3557 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3558 { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, 3559 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, 3560 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3561 { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH, 3562 .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2, 3563 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3564 { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, 3565 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, 3566 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3567 { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2, 3568 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, 3569 .resetvalue = 0 }, 3570 { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH, 3571 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, 3572 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3573 { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64, 3574 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3, 3575 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3576 { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14, 3577 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, 3578 .resetvalue = 0 }, 3579 { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64, 3580 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2, 3581 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3582 { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14, 3583 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, 3584 .resetvalue = 0 }, 3585 { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH, 3586 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0, 3587 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3588 { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, 3589 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, 3590 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3591 { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, 3592 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, 3593 .access = PL2_RW, .accessfn = access_tda, 3594 .type = ARM_CP_CONST, .resetvalue = 0 }, 3595 { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH, 3596 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, 3597 .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, 3598 .type = ARM_CP_CONST, .resetvalue = 0 }, 3599 { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH, 3600 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3, 3601 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3602 REGINFO_SENTINEL 3603 }; 3604 3605 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) 3606 { 3607 ARMCPU *cpu = arm_env_get_cpu(env); 3608 uint64_t valid_mask = HCR_MASK; 3609 3610 if (arm_feature(env, ARM_FEATURE_EL3)) { 3611 valid_mask &= ~HCR_HCD; 3612 } else { 3613 valid_mask &= ~HCR_TSC; 3614 } 3615 3616 /* Clear RES0 bits. */ 3617 value &= valid_mask; 3618 3619 /* These bits change the MMU setup: 3620 * HCR_VM enables stage 2 translation 3621 * HCR_PTW forbids certain page-table setups 3622 * HCR_DC Disables stage1 and enables stage2 translation 3623 */ 3624 if ((raw_read(env, ri) ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) { 3625 tlb_flush(CPU(cpu), 1); 3626 } 3627 raw_write(env, ri, value); 3628 } 3629 3630 static const ARMCPRegInfo el2_cp_reginfo[] = { 3631 { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64, 3632 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, 3633 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), 3634 .writefn = hcr_write }, 3635 { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64, 3636 .type = ARM_CP_ALIAS, 3637 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1, 3638 .access = PL2_RW, 3639 .fieldoffset = offsetof(CPUARMState, elr_el[2]) }, 3640 { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64, 3641 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, 3642 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) }, 3643 { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64, 3644 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, 3645 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) }, 3646 { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64, 3647 .type = ARM_CP_ALIAS, 3648 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0, 3649 .access = PL2_RW, 3650 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_HYP]) }, 3651 { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64, 3652 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, 3653 .access = PL2_RW, .writefn = vbar_write, 3654 .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]), 3655 .resetvalue = 0 }, 3656 { .name = "SP_EL2", .state = ARM_CP_STATE_AA64, 3657 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0, 3658 .access = PL3_RW, .type = ARM_CP_ALIAS, 3659 .fieldoffset = offsetof(CPUARMState, sp_el[2]) }, 3660 { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH, 3661 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, 3662 .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0, 3663 .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[2]) }, 3664 { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH, 3665 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0, 3666 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[2]), 3667 .resetvalue = 0 }, 3668 { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, 3669 .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, 3670 .access = PL2_RW, .type = ARM_CP_ALIAS, 3671 .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el[2]) }, 3672 { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH, 3673 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0, 3674 .access = PL2_RW, .type = ARM_CP_CONST, 3675 .resetvalue = 0 }, 3676 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */ 3677 { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, 3678 .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, 3679 .access = PL2_RW, .type = ARM_CP_CONST, 3680 .resetvalue = 0 }, 3681 { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH, 3682 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0, 3683 .access = PL2_RW, .type = ARM_CP_CONST, 3684 .resetvalue = 0 }, 3685 { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH, 3686 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1, 3687 .access = PL2_RW, .type = ARM_CP_CONST, 3688 .resetvalue = 0 }, 3689 { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, 3690 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, 3691 .access = PL2_RW, 3692 /* no .writefn needed as this can't cause an ASID change; 3693 * no .raw_writefn or .resetfn needed as we never use mask/base_mask 3694 */ 3695 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) }, 3696 { .name = "VTCR", .state = ARM_CP_STATE_AA32, 3697 .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, 3698 .type = ARM_CP_ALIAS, 3699 .access = PL2_RW, .accessfn = access_el3_aa32ns, 3700 .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) }, 3701 { .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64, 3702 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, 3703 .access = PL2_RW, 3704 /* no .writefn needed as this can't cause an ASID change; 3705 * no .raw_writefn or .resetfn needed as we never use mask/base_mask 3706 */ 3707 .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) }, 3708 { .name = "VTTBR", .state = ARM_CP_STATE_AA32, 3709 .cp = 15, .opc1 = 6, .crm = 2, 3710 .type = ARM_CP_64BIT | ARM_CP_ALIAS, 3711 .access = PL2_RW, .accessfn = access_el3_aa32ns, 3712 .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2), 3713 .writefn = vttbr_write }, 3714 { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64, 3715 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0, 3716 .access = PL2_RW, .writefn = vttbr_write, 3717 .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) }, 3718 { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, 3719 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, 3720 .access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write, 3721 .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[2]) }, 3722 { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH, 3723 .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2, 3724 .access = PL2_RW, .resetvalue = 0, 3725 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) }, 3726 { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, 3727 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, 3728 .access = PL2_RW, .resetvalue = 0, 3729 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, 3730 { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2, 3731 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, 3732 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, 3733 { .name = "TLBIALLNSNH", 3734 .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4, 3735 .type = ARM_CP_NO_RAW, .access = PL2_W, 3736 .writefn = tlbiall_nsnh_write }, 3737 { .name = "TLBIALLNSNHIS", 3738 .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4, 3739 .type = ARM_CP_NO_RAW, .access = PL2_W, 3740 .writefn = tlbiall_nsnh_is_write }, 3741 { .name = "TLBIALLH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0, 3742 .type = ARM_CP_NO_RAW, .access = PL2_W, 3743 .writefn = tlbiall_hyp_write }, 3744 { .name = "TLBIALLHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, 3745 .type = ARM_CP_NO_RAW, .access = PL2_W, 3746 .writefn = tlbiall_hyp_is_write }, 3747 { .name = "TLBIMVAH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, 3748 .type = ARM_CP_NO_RAW, .access = PL2_W, 3749 .writefn = tlbimva_hyp_write }, 3750 { .name = "TLBIMVAHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, 3751 .type = ARM_CP_NO_RAW, .access = PL2_W, 3752 .writefn = tlbimva_hyp_is_write }, 3753 { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64, 3754 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0, 3755 .type = ARM_CP_NO_RAW, .access = PL2_W, 3756 .writefn = tlbi_aa64_alle2_write }, 3757 { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64, 3758 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, 3759 .type = ARM_CP_NO_RAW, .access = PL2_W, 3760 .writefn = tlbi_aa64_vae2_write }, 3761 { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64, 3762 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, 3763 .access = PL2_W, .type = ARM_CP_NO_RAW, 3764 .writefn = tlbi_aa64_vae2_write }, 3765 { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64, 3766 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, 3767 .access = PL2_W, .type = ARM_CP_NO_RAW, 3768 .writefn = tlbi_aa64_alle2is_write }, 3769 { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64, 3770 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, 3771 .type = ARM_CP_NO_RAW, .access = PL2_W, 3772 .writefn = tlbi_aa64_vae2is_write }, 3773 { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64, 3774 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, 3775 .access = PL2_W, .type = ARM_CP_NO_RAW, 3776 .writefn = tlbi_aa64_vae2is_write }, 3777 #ifndef CONFIG_USER_ONLY 3778 /* Unlike the other EL2-related AT operations, these must 3779 * UNDEF from EL3 if EL2 is not implemented, which is why we 3780 * define them here rather than with the rest of the AT ops. 3781 */ 3782 { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64, 3783 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, 3784 .access = PL2_W, .accessfn = at_s1e2_access, 3785 .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3786 { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64, 3787 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, 3788 .access = PL2_W, .accessfn = at_s1e2_access, 3789 .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3790 /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE 3791 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3 3792 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose 3793 * to behave as if SCR.NS was 1. 3794 */ 3795 { .name = "ATS1HR", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, 3796 .access = PL2_W, 3797 .writefn = ats1h_write, .type = ARM_CP_NO_RAW }, 3798 { .name = "ATS1HW", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, 3799 .access = PL2_W, 3800 .writefn = ats1h_write, .type = ARM_CP_NO_RAW }, 3801 { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH, 3802 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, 3803 /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the 3804 * reset values as IMPDEF. We choose to reset to 3 to comply with 3805 * both ARMv7 and ARMv8. 3806 */ 3807 .access = PL2_RW, .resetvalue = 3, 3808 .fieldoffset = offsetof(CPUARMState, cp15.cnthctl_el2) }, 3809 { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64, 3810 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3, 3811 .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0, 3812 .writefn = gt_cntvoff_write, 3813 .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) }, 3814 { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14, 3815 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_IO, 3816 .writefn = gt_cntvoff_write, 3817 .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) }, 3818 { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64, 3819 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2, 3820 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval), 3821 .type = ARM_CP_IO, .access = PL2_RW, 3822 .writefn = gt_hyp_cval_write, .raw_writefn = raw_write }, 3823 { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14, 3824 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval), 3825 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_IO, 3826 .writefn = gt_hyp_cval_write, .raw_writefn = raw_write }, 3827 { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH, 3828 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0, 3829 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW, 3830 .resetfn = gt_hyp_timer_reset, 3831 .readfn = gt_hyp_tval_read, .writefn = gt_hyp_tval_write }, 3832 { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, 3833 .type = ARM_CP_IO, 3834 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, 3835 .access = PL2_RW, 3836 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].ctl), 3837 .resetvalue = 0, 3838 .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write }, 3839 #endif 3840 /* The only field of MDCR_EL2 that has a defined architectural reset value 3841 * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we 3842 * don't impelment any PMU event counters, so using zero as a reset 3843 * value for MDCR_EL2 is okay 3844 */ 3845 { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, 3846 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, 3847 .access = PL2_RW, .resetvalue = 0, 3848 .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), }, 3849 { .name = "HPFAR", .state = ARM_CP_STATE_AA32, 3850 .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, 3851 .access = PL2_RW, .accessfn = access_el3_aa32ns, 3852 .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, 3853 { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64, 3854 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, 3855 .access = PL2_RW, 3856 .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, 3857 { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH, 3858 .cp = 15, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3, 3859 .access = PL2_RW, 3860 .fieldoffset = offsetof(CPUARMState, cp15.hstr_el2) }, 3861 REGINFO_SENTINEL 3862 }; 3863 3864 static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri, 3865 bool isread) 3866 { 3867 /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2. 3868 * At Secure EL1 it traps to EL3. 3869 */ 3870 if (arm_current_el(env) == 3) { 3871 return CP_ACCESS_OK; 3872 } 3873 if (arm_is_secure_below_el3(env)) { 3874 return CP_ACCESS_TRAP_EL3; 3875 } 3876 /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */ 3877 if (isread) { 3878 return CP_ACCESS_OK; 3879 } 3880 return CP_ACCESS_TRAP_UNCATEGORIZED; 3881 } 3882 3883 static const ARMCPRegInfo el3_cp_reginfo[] = { 3884 { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64, 3885 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0, 3886 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), 3887 .resetvalue = 0, .writefn = scr_write }, 3888 { .name = "SCR", .type = ARM_CP_ALIAS, 3889 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0, 3890 .access = PL1_RW, .accessfn = access_trap_aa32s_el1, 3891 .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), 3892 .writefn = scr_write }, 3893 { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64, 3894 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1, 3895 .access = PL3_RW, .resetvalue = 0, 3896 .fieldoffset = offsetof(CPUARMState, cp15.sder) }, 3897 { .name = "SDER", 3898 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1, 3899 .access = PL3_RW, .resetvalue = 0, 3900 .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) }, 3901 { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, 3902 .access = PL1_RW, .accessfn = access_trap_aa32s_el1, 3903 .writefn = vbar_write, .resetvalue = 0, 3904 .fieldoffset = offsetof(CPUARMState, cp15.mvbar) }, 3905 { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64, 3906 .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0, 3907 .access = PL3_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, 3908 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) }, 3909 { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64, 3910 .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2, 3911 .access = PL3_RW, 3912 /* no .writefn needed as this can't cause an ASID change; 3913 * we must provide a .raw_writefn and .resetfn because we handle 3914 * reset and migration for the AArch32 TTBCR(S), which might be 3915 * using mask and base_mask. 3916 */ 3917 .resetfn = vmsa_ttbcr_reset, .raw_writefn = vmsa_ttbcr_raw_write, 3918 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) }, 3919 { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64, 3920 .type = ARM_CP_ALIAS, 3921 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1, 3922 .access = PL3_RW, 3923 .fieldoffset = offsetof(CPUARMState, elr_el[3]) }, 3924 { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64, 3925 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0, 3926 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) }, 3927 { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64, 3928 .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0, 3929 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) }, 3930 { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64, 3931 .type = ARM_CP_ALIAS, 3932 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0, 3933 .access = PL3_RW, 3934 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_MON]) }, 3935 { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64, 3936 .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0, 3937 .access = PL3_RW, .writefn = vbar_write, 3938 .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]), 3939 .resetvalue = 0 }, 3940 { .name = "CPTR_EL3", .state = ARM_CP_STATE_AA64, 3941 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2, 3942 .access = PL3_RW, .accessfn = cptr_access, .resetvalue = 0, 3943 .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) }, 3944 { .name = "TPIDR_EL3", .state = ARM_CP_STATE_AA64, 3945 .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2, 3946 .access = PL3_RW, .resetvalue = 0, 3947 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) }, 3948 { .name = "AMAIR_EL3", .state = ARM_CP_STATE_AA64, 3949 .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0, 3950 .access = PL3_RW, .type = ARM_CP_CONST, 3951 .resetvalue = 0 }, 3952 { .name = "AFSR0_EL3", .state = ARM_CP_STATE_BOTH, 3953 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0, 3954 .access = PL3_RW, .type = ARM_CP_CONST, 3955 .resetvalue = 0 }, 3956 { .name = "AFSR1_EL3", .state = ARM_CP_STATE_BOTH, 3957 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1, 3958 .access = PL3_RW, .type = ARM_CP_CONST, 3959 .resetvalue = 0 }, 3960 { .name = "TLBI_ALLE3IS", .state = ARM_CP_STATE_AA64, 3961 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 0, 3962 .access = PL3_W, .type = ARM_CP_NO_RAW, 3963 .writefn = tlbi_aa64_alle3is_write }, 3964 { .name = "TLBI_VAE3IS", .state = ARM_CP_STATE_AA64, 3965 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 1, 3966 .access = PL3_W, .type = ARM_CP_NO_RAW, 3967 .writefn = tlbi_aa64_vae3is_write }, 3968 { .name = "TLBI_VALE3IS", .state = ARM_CP_STATE_AA64, 3969 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 5, 3970 .access = PL3_W, .type = ARM_CP_NO_RAW, 3971 .writefn = tlbi_aa64_vae3is_write }, 3972 { .name = "TLBI_ALLE3", .state = ARM_CP_STATE_AA64, 3973 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 0, 3974 .access = PL3_W, .type = ARM_CP_NO_RAW, 3975 .writefn = tlbi_aa64_alle3_write }, 3976 { .name = "TLBI_VAE3", .state = ARM_CP_STATE_AA64, 3977 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 1, 3978 .access = PL3_W, .type = ARM_CP_NO_RAW, 3979 .writefn = tlbi_aa64_vae3_write }, 3980 { .name = "TLBI_VALE3", .state = ARM_CP_STATE_AA64, 3981 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5, 3982 .access = PL3_W, .type = ARM_CP_NO_RAW, 3983 .writefn = tlbi_aa64_vae3_write }, 3984 REGINFO_SENTINEL 3985 }; 3986 3987 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, 3988 bool isread) 3989 { 3990 /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64, 3991 * but the AArch32 CTR has its own reginfo struct) 3992 */ 3993 if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCT)) { 3994 return CP_ACCESS_TRAP; 3995 } 3996 return CP_ACCESS_OK; 3997 } 3998 3999 static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri, 4000 uint64_t value) 4001 { 4002 /* Writes to OSLAR_EL1 may update the OS lock status, which can be 4003 * read via a bit in OSLSR_EL1. 4004 */ 4005 int oslock; 4006 4007 if (ri->state == ARM_CP_STATE_AA32) { 4008 oslock = (value == 0xC5ACCE55); 4009 } else { 4010 oslock = value & 1; 4011 } 4012 4013 env->cp15.oslsr_el1 = deposit32(env->cp15.oslsr_el1, 1, 1, oslock); 4014 } 4015 4016 static const ARMCPRegInfo debug_cp_reginfo[] = { 4017 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped 4018 * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1; 4019 * unlike DBGDRAR it is never accessible from EL0. 4020 * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64 4021 * accessor. 4022 */ 4023 { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0, 4024 .access = PL0_R, .accessfn = access_tdra, 4025 .type = ARM_CP_CONST, .resetvalue = 0 }, 4026 { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64, 4027 .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, 4028 .access = PL1_R, .accessfn = access_tdra, 4029 .type = ARM_CP_CONST, .resetvalue = 0 }, 4030 { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, 4031 .access = PL0_R, .accessfn = access_tdra, 4032 .type = ARM_CP_CONST, .resetvalue = 0 }, 4033 /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */ 4034 { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH, 4035 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, 4036 .access = PL1_RW, .accessfn = access_tda, 4037 .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), 4038 .resetvalue = 0 }, 4039 /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1. 4040 * We don't implement the configurable EL0 access. 4041 */ 4042 { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH, 4043 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, 4044 .type = ARM_CP_ALIAS, 4045 .access = PL1_R, .accessfn = access_tda, 4046 .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), }, 4047 { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH, 4048 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4, 4049 .access = PL1_W, .type = ARM_CP_NO_RAW, 4050 .accessfn = access_tdosa, 4051 .writefn = oslar_write }, 4052 { .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH, 4053 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4, 4054 .access = PL1_R, .resetvalue = 10, 4055 .accessfn = access_tdosa, 4056 .fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) }, 4057 /* Dummy OSDLR_EL1: 32-bit Linux will read this */ 4058 { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH, 4059 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4, 4060 .access = PL1_RW, .accessfn = access_tdosa, 4061 .type = ARM_CP_NOP }, 4062 /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't 4063 * implement vector catch debug events yet. 4064 */ 4065 { .name = "DBGVCR", 4066 .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, 4067 .access = PL1_RW, .accessfn = access_tda, 4068 .type = ARM_CP_NOP }, 4069 /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications 4070 * Channel but Linux may try to access this register. The 32-bit 4071 * alias is DBGDCCINT. 4072 */ 4073 { .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH, 4074 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, 4075 .access = PL1_RW, .accessfn = access_tda, 4076 .type = ARM_CP_NOP }, 4077 REGINFO_SENTINEL 4078 }; 4079 4080 static const ARMCPRegInfo debug_lpae_cp_reginfo[] = { 4081 /* 64 bit access versions of the (dummy) debug registers */ 4082 { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0, 4083 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, 4084 { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0, 4085 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, 4086 REGINFO_SENTINEL 4087 }; 4088 4089 void hw_watchpoint_update(ARMCPU *cpu, int n) 4090 { 4091 CPUARMState *env = &cpu->env; 4092 vaddr len = 0; 4093 vaddr wvr = env->cp15.dbgwvr[n]; 4094 uint64_t wcr = env->cp15.dbgwcr[n]; 4095 int mask; 4096 int flags = BP_CPU | BP_STOP_BEFORE_ACCESS; 4097 4098 if (env->cpu_watchpoint[n]) { 4099 cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]); 4100 env->cpu_watchpoint[n] = NULL; 4101 } 4102 4103 if (!extract64(wcr, 0, 1)) { 4104 /* E bit clear : watchpoint disabled */ 4105 return; 4106 } 4107 4108 switch (extract64(wcr, 3, 2)) { 4109 case 0: 4110 /* LSC 00 is reserved and must behave as if the wp is disabled */ 4111 return; 4112 case 1: 4113 flags |= BP_MEM_READ; 4114 break; 4115 case 2: 4116 flags |= BP_MEM_WRITE; 4117 break; 4118 case 3: 4119 flags |= BP_MEM_ACCESS; 4120 break; 4121 } 4122 4123 /* Attempts to use both MASK and BAS fields simultaneously are 4124 * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case, 4125 * thus generating a watchpoint for every byte in the masked region. 4126 */ 4127 mask = extract64(wcr, 24, 4); 4128 if (mask == 1 || mask == 2) { 4129 /* Reserved values of MASK; we must act as if the mask value was 4130 * some non-reserved value, or as if the watchpoint were disabled. 4131 * We choose the latter. 4132 */ 4133 return; 4134 } else if (mask) { 4135 /* Watchpoint covers an aligned area up to 2GB in size */ 4136 len = 1ULL << mask; 4137 /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE 4138 * whether the watchpoint fires when the unmasked bits match; we opt 4139 * to generate the exceptions. 4140 */ 4141 wvr &= ~(len - 1); 4142 } else { 4143 /* Watchpoint covers bytes defined by the byte address select bits */ 4144 int bas = extract64(wcr, 5, 8); 4145 int basstart; 4146 4147 if (bas == 0) { 4148 /* This must act as if the watchpoint is disabled */ 4149 return; 4150 } 4151 4152 if (extract64(wvr, 2, 1)) { 4153 /* Deprecated case of an only 4-aligned address. BAS[7:4] are 4154 * ignored, and BAS[3:0] define which bytes to watch. 4155 */ 4156 bas &= 0xf; 4157 } 4158 /* The BAS bits are supposed to be programmed to indicate a contiguous 4159 * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether 4160 * we fire for each byte in the word/doubleword addressed by the WVR. 4161 * We choose to ignore any non-zero bits after the first range of 1s. 4162 */ 4163 basstart = ctz32(bas); 4164 len = cto32(bas >> basstart); 4165 wvr += basstart; 4166 } 4167 4168 cpu_watchpoint_insert(CPU(cpu), wvr, len, flags, 4169 &env->cpu_watchpoint[n]); 4170 } 4171 4172 void hw_watchpoint_update_all(ARMCPU *cpu) 4173 { 4174 int i; 4175 CPUARMState *env = &cpu->env; 4176 4177 /* Completely clear out existing QEMU watchpoints and our array, to 4178 * avoid possible stale entries following migration load. 4179 */ 4180 cpu_watchpoint_remove_all(CPU(cpu), BP_CPU); 4181 memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint)); 4182 4183 for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) { 4184 hw_watchpoint_update(cpu, i); 4185 } 4186 } 4187 4188 static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri, 4189 uint64_t value) 4190 { 4191 ARMCPU *cpu = arm_env_get_cpu(env); 4192 int i = ri->crm; 4193 4194 /* Bits [63:49] are hardwired to the value of bit [48]; that is, the 4195 * register reads and behaves as if values written are sign extended. 4196 * Bits [1:0] are RES0. 4197 */ 4198 value = sextract64(value, 0, 49) & ~3ULL; 4199 4200 raw_write(env, ri, value); 4201 hw_watchpoint_update(cpu, i); 4202 } 4203 4204 static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri, 4205 uint64_t value) 4206 { 4207 ARMCPU *cpu = arm_env_get_cpu(env); 4208 int i = ri->crm; 4209 4210 raw_write(env, ri, value); 4211 hw_watchpoint_update(cpu, i); 4212 } 4213 4214 void hw_breakpoint_update(ARMCPU *cpu, int n) 4215 { 4216 CPUARMState *env = &cpu->env; 4217 uint64_t bvr = env->cp15.dbgbvr[n]; 4218 uint64_t bcr = env->cp15.dbgbcr[n]; 4219 vaddr addr; 4220 int bt; 4221 int flags = BP_CPU; 4222 4223 if (env->cpu_breakpoint[n]) { 4224 cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]); 4225 env->cpu_breakpoint[n] = NULL; 4226 } 4227 4228 if (!extract64(bcr, 0, 1)) { 4229 /* E bit clear : watchpoint disabled */ 4230 return; 4231 } 4232 4233 bt = extract64(bcr, 20, 4); 4234 4235 switch (bt) { 4236 case 4: /* unlinked address mismatch (reserved if AArch64) */ 4237 case 5: /* linked address mismatch (reserved if AArch64) */ 4238 qemu_log_mask(LOG_UNIMP, 4239 "arm: address mismatch breakpoint types not implemented"); 4240 return; 4241 case 0: /* unlinked address match */ 4242 case 1: /* linked address match */ 4243 { 4244 /* Bits [63:49] are hardwired to the value of bit [48]; that is, 4245 * we behave as if the register was sign extended. Bits [1:0] are 4246 * RES0. The BAS field is used to allow setting breakpoints on 16 4247 * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether 4248 * a bp will fire if the addresses covered by the bp and the addresses 4249 * covered by the insn overlap but the insn doesn't start at the 4250 * start of the bp address range. We choose to require the insn and 4251 * the bp to have the same address. The constraints on writing to 4252 * BAS enforced in dbgbcr_write mean we have only four cases: 4253 * 0b0000 => no breakpoint 4254 * 0b0011 => breakpoint on addr 4255 * 0b1100 => breakpoint on addr + 2 4256 * 0b1111 => breakpoint on addr 4257 * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c). 4258 */ 4259 int bas = extract64(bcr, 5, 4); 4260 addr = sextract64(bvr, 0, 49) & ~3ULL; 4261 if (bas == 0) { 4262 return; 4263 } 4264 if (bas == 0xc) { 4265 addr += 2; 4266 } 4267 break; 4268 } 4269 case 2: /* unlinked context ID match */ 4270 case 8: /* unlinked VMID match (reserved if no EL2) */ 4271 case 10: /* unlinked context ID and VMID match (reserved if no EL2) */ 4272 qemu_log_mask(LOG_UNIMP, 4273 "arm: unlinked context breakpoint types not implemented"); 4274 return; 4275 case 9: /* linked VMID match (reserved if no EL2) */ 4276 case 11: /* linked context ID and VMID match (reserved if no EL2) */ 4277 case 3: /* linked context ID match */ 4278 default: 4279 /* We must generate no events for Linked context matches (unless 4280 * they are linked to by some other bp/wp, which is handled in 4281 * updates for the linking bp/wp). We choose to also generate no events 4282 * for reserved values. 4283 */ 4284 return; 4285 } 4286 4287 cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]); 4288 } 4289 4290 void hw_breakpoint_update_all(ARMCPU *cpu) 4291 { 4292 int i; 4293 CPUARMState *env = &cpu->env; 4294 4295 /* Completely clear out existing QEMU breakpoints and our array, to 4296 * avoid possible stale entries following migration load. 4297 */ 4298 cpu_breakpoint_remove_all(CPU(cpu), BP_CPU); 4299 memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint)); 4300 4301 for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) { 4302 hw_breakpoint_update(cpu, i); 4303 } 4304 } 4305 4306 static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri, 4307 uint64_t value) 4308 { 4309 ARMCPU *cpu = arm_env_get_cpu(env); 4310 int i = ri->crm; 4311 4312 raw_write(env, ri, value); 4313 hw_breakpoint_update(cpu, i); 4314 } 4315 4316 static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, 4317 uint64_t value) 4318 { 4319 ARMCPU *cpu = arm_env_get_cpu(env); 4320 int i = ri->crm; 4321 4322 /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only 4323 * copy of BAS[0]. 4324 */ 4325 value = deposit64(value, 6, 1, extract64(value, 5, 1)); 4326 value = deposit64(value, 8, 1, extract64(value, 7, 1)); 4327 4328 raw_write(env, ri, value); 4329 hw_breakpoint_update(cpu, i); 4330 } 4331 4332 static void define_debug_regs(ARMCPU *cpu) 4333 { 4334 /* Define v7 and v8 architectural debug registers. 4335 * These are just dummy implementations for now. 4336 */ 4337 int i; 4338 int wrps, brps, ctx_cmps; 4339 ARMCPRegInfo dbgdidr = { 4340 .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, 4341 .access = PL0_R, .accessfn = access_tda, 4342 .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr, 4343 }; 4344 4345 /* Note that all these register fields hold "number of Xs minus 1". */ 4346 brps = extract32(cpu->dbgdidr, 24, 4); 4347 wrps = extract32(cpu->dbgdidr, 28, 4); 4348 ctx_cmps = extract32(cpu->dbgdidr, 20, 4); 4349 4350 assert(ctx_cmps <= brps); 4351 4352 /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties 4353 * of the debug registers such as number of breakpoints; 4354 * check that if they both exist then they agree. 4355 */ 4356 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 4357 assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps); 4358 assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps); 4359 assert(extract32(cpu->id_aa64dfr0, 28, 4) == ctx_cmps); 4360 } 4361 4362 define_one_arm_cp_reg(cpu, &dbgdidr); 4363 define_arm_cp_regs(cpu, debug_cp_reginfo); 4364 4365 if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) { 4366 define_arm_cp_regs(cpu, debug_lpae_cp_reginfo); 4367 } 4368 4369 for (i = 0; i < brps + 1; i++) { 4370 ARMCPRegInfo dbgregs[] = { 4371 { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH, 4372 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4, 4373 .access = PL1_RW, .accessfn = access_tda, 4374 .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]), 4375 .writefn = dbgbvr_write, .raw_writefn = raw_write 4376 }, 4377 { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH, 4378 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5, 4379 .access = PL1_RW, .accessfn = access_tda, 4380 .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]), 4381 .writefn = dbgbcr_write, .raw_writefn = raw_write 4382 }, 4383 REGINFO_SENTINEL 4384 }; 4385 define_arm_cp_regs(cpu, dbgregs); 4386 } 4387 4388 for (i = 0; i < wrps + 1; i++) { 4389 ARMCPRegInfo dbgregs[] = { 4390 { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH, 4391 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6, 4392 .access = PL1_RW, .accessfn = access_tda, 4393 .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]), 4394 .writefn = dbgwvr_write, .raw_writefn = raw_write 4395 }, 4396 { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH, 4397 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7, 4398 .access = PL1_RW, .accessfn = access_tda, 4399 .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]), 4400 .writefn = dbgwcr_write, .raw_writefn = raw_write 4401 }, 4402 REGINFO_SENTINEL 4403 }; 4404 define_arm_cp_regs(cpu, dbgregs); 4405 } 4406 } 4407 4408 void register_cp_regs_for_features(ARMCPU *cpu) 4409 { 4410 /* Register all the coprocessor registers based on feature bits */ 4411 CPUARMState *env = &cpu->env; 4412 if (arm_feature(env, ARM_FEATURE_M)) { 4413 /* M profile has no coprocessor registers */ 4414 return; 4415 } 4416 4417 define_arm_cp_regs(cpu, cp_reginfo); 4418 if (!arm_feature(env, ARM_FEATURE_V8)) { 4419 /* Must go early as it is full of wildcards that may be 4420 * overridden by later definitions. 4421 */ 4422 define_arm_cp_regs(cpu, not_v8_cp_reginfo); 4423 } 4424 4425 if (arm_feature(env, ARM_FEATURE_V6)) { 4426 /* The ID registers all have impdef reset values */ 4427 ARMCPRegInfo v6_idregs[] = { 4428 { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH, 4429 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, 4430 .access = PL1_R, .type = ARM_CP_CONST, 4431 .resetvalue = cpu->id_pfr0 }, 4432 { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH, 4433 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1, 4434 .access = PL1_R, .type = ARM_CP_CONST, 4435 .resetvalue = cpu->id_pfr1 }, 4436 { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH, 4437 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2, 4438 .access = PL1_R, .type = ARM_CP_CONST, 4439 .resetvalue = cpu->id_dfr0 }, 4440 { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH, 4441 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3, 4442 .access = PL1_R, .type = ARM_CP_CONST, 4443 .resetvalue = cpu->id_afr0 }, 4444 { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH, 4445 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4, 4446 .access = PL1_R, .type = ARM_CP_CONST, 4447 .resetvalue = cpu->id_mmfr0 }, 4448 { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH, 4449 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5, 4450 .access = PL1_R, .type = ARM_CP_CONST, 4451 .resetvalue = cpu->id_mmfr1 }, 4452 { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH, 4453 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6, 4454 .access = PL1_R, .type = ARM_CP_CONST, 4455 .resetvalue = cpu->id_mmfr2 }, 4456 { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH, 4457 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7, 4458 .access = PL1_R, .type = ARM_CP_CONST, 4459 .resetvalue = cpu->id_mmfr3 }, 4460 { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH, 4461 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, 4462 .access = PL1_R, .type = ARM_CP_CONST, 4463 .resetvalue = cpu->id_isar0 }, 4464 { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH, 4465 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1, 4466 .access = PL1_R, .type = ARM_CP_CONST, 4467 .resetvalue = cpu->id_isar1 }, 4468 { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH, 4469 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, 4470 .access = PL1_R, .type = ARM_CP_CONST, 4471 .resetvalue = cpu->id_isar2 }, 4472 { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH, 4473 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3, 4474 .access = PL1_R, .type = ARM_CP_CONST, 4475 .resetvalue = cpu->id_isar3 }, 4476 { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH, 4477 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4, 4478 .access = PL1_R, .type = ARM_CP_CONST, 4479 .resetvalue = cpu->id_isar4 }, 4480 { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH, 4481 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5, 4482 .access = PL1_R, .type = ARM_CP_CONST, 4483 .resetvalue = cpu->id_isar5 }, 4484 { .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH, 4485 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6, 4486 .access = PL1_R, .type = ARM_CP_CONST, 4487 .resetvalue = cpu->id_mmfr4 }, 4488 /* 7 is as yet unallocated and must RAZ */ 4489 { .name = "ID_ISAR7_RESERVED", .state = ARM_CP_STATE_BOTH, 4490 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7, 4491 .access = PL1_R, .type = ARM_CP_CONST, 4492 .resetvalue = 0 }, 4493 REGINFO_SENTINEL 4494 }; 4495 define_arm_cp_regs(cpu, v6_idregs); 4496 define_arm_cp_regs(cpu, v6_cp_reginfo); 4497 } else { 4498 define_arm_cp_regs(cpu, not_v6_cp_reginfo); 4499 } 4500 if (arm_feature(env, ARM_FEATURE_V6K)) { 4501 define_arm_cp_regs(cpu, v6k_cp_reginfo); 4502 } 4503 if (arm_feature(env, ARM_FEATURE_V7MP) && 4504 !arm_feature(env, ARM_FEATURE_MPU)) { 4505 define_arm_cp_regs(cpu, v7mp_cp_reginfo); 4506 } 4507 if (arm_feature(env, ARM_FEATURE_V7)) { 4508 /* v7 performance monitor control register: same implementor 4509 * field as main ID register, and we implement only the cycle 4510 * count register. 4511 */ 4512 #ifndef CONFIG_USER_ONLY 4513 ARMCPRegInfo pmcr = { 4514 .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0, 4515 .access = PL0_RW, 4516 .type = ARM_CP_IO | ARM_CP_ALIAS, 4517 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr), 4518 .accessfn = pmreg_access, .writefn = pmcr_write, 4519 .raw_writefn = raw_write, 4520 }; 4521 ARMCPRegInfo pmcr64 = { 4522 .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64, 4523 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0, 4524 .access = PL0_RW, .accessfn = pmreg_access, 4525 .type = ARM_CP_IO, 4526 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr), 4527 .resetvalue = cpu->midr & 0xff000000, 4528 .writefn = pmcr_write, .raw_writefn = raw_write, 4529 }; 4530 define_one_arm_cp_reg(cpu, &pmcr); 4531 define_one_arm_cp_reg(cpu, &pmcr64); 4532 #endif 4533 ARMCPRegInfo clidr = { 4534 .name = "CLIDR", .state = ARM_CP_STATE_BOTH, 4535 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1, 4536 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr 4537 }; 4538 define_one_arm_cp_reg(cpu, &clidr); 4539 define_arm_cp_regs(cpu, v7_cp_reginfo); 4540 define_debug_regs(cpu); 4541 } else { 4542 define_arm_cp_regs(cpu, not_v7_cp_reginfo); 4543 } 4544 if (arm_feature(env, ARM_FEATURE_V8)) { 4545 /* AArch64 ID registers, which all have impdef reset values. 4546 * Note that within the ID register ranges the unused slots 4547 * must all RAZ, not UNDEF; future architecture versions may 4548 * define new registers here. 4549 */ 4550 ARMCPRegInfo v8_idregs[] = { 4551 { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64, 4552 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0, 4553 .access = PL1_R, .type = ARM_CP_CONST, 4554 .resetvalue = cpu->id_aa64pfr0 }, 4555 { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64, 4556 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1, 4557 .access = PL1_R, .type = ARM_CP_CONST, 4558 .resetvalue = cpu->id_aa64pfr1}, 4559 { .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4560 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2, 4561 .access = PL1_R, .type = ARM_CP_CONST, 4562 .resetvalue = 0 }, 4563 { .name = "ID_AA64PFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4564 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3, 4565 .access = PL1_R, .type = ARM_CP_CONST, 4566 .resetvalue = 0 }, 4567 { .name = "ID_AA64PFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4568 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4, 4569 .access = PL1_R, .type = ARM_CP_CONST, 4570 .resetvalue = 0 }, 4571 { .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4572 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5, 4573 .access = PL1_R, .type = ARM_CP_CONST, 4574 .resetvalue = 0 }, 4575 { .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4576 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6, 4577 .access = PL1_R, .type = ARM_CP_CONST, 4578 .resetvalue = 0 }, 4579 { .name = "ID_AA64PFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4580 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7, 4581 .access = PL1_R, .type = ARM_CP_CONST, 4582 .resetvalue = 0 }, 4583 { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64, 4584 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0, 4585 .access = PL1_R, .type = ARM_CP_CONST, 4586 /* We mask out the PMUVer field, because we don't currently 4587 * implement the PMU. Not advertising it prevents the guest 4588 * from trying to use it and getting UNDEFs on registers we 4589 * don't implement. 4590 */ 4591 .resetvalue = cpu->id_aa64dfr0 & ~0xf00 }, 4592 { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64, 4593 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1, 4594 .access = PL1_R, .type = ARM_CP_CONST, 4595 .resetvalue = cpu->id_aa64dfr1 }, 4596 { .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4597 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2, 4598 .access = PL1_R, .type = ARM_CP_CONST, 4599 .resetvalue = 0 }, 4600 { .name = "ID_AA64DFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4601 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 3, 4602 .access = PL1_R, .type = ARM_CP_CONST, 4603 .resetvalue = 0 }, 4604 { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64, 4605 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4, 4606 .access = PL1_R, .type = ARM_CP_CONST, 4607 .resetvalue = cpu->id_aa64afr0 }, 4608 { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64, 4609 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5, 4610 .access = PL1_R, .type = ARM_CP_CONST, 4611 .resetvalue = cpu->id_aa64afr1 }, 4612 { .name = "ID_AA64AFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4613 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6, 4614 .access = PL1_R, .type = ARM_CP_CONST, 4615 .resetvalue = 0 }, 4616 { .name = "ID_AA64AFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4617 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 7, 4618 .access = PL1_R, .type = ARM_CP_CONST, 4619 .resetvalue = 0 }, 4620 { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64, 4621 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0, 4622 .access = PL1_R, .type = ARM_CP_CONST, 4623 .resetvalue = cpu->id_aa64isar0 }, 4624 { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64, 4625 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1, 4626 .access = PL1_R, .type = ARM_CP_CONST, 4627 .resetvalue = cpu->id_aa64isar1 }, 4628 { .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4629 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2, 4630 .access = PL1_R, .type = ARM_CP_CONST, 4631 .resetvalue = 0 }, 4632 { .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4633 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3, 4634 .access = PL1_R, .type = ARM_CP_CONST, 4635 .resetvalue = 0 }, 4636 { .name = "ID_AA64ISAR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4637 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4, 4638 .access = PL1_R, .type = ARM_CP_CONST, 4639 .resetvalue = 0 }, 4640 { .name = "ID_AA64ISAR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4641 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 5, 4642 .access = PL1_R, .type = ARM_CP_CONST, 4643 .resetvalue = 0 }, 4644 { .name = "ID_AA64ISAR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4645 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 6, 4646 .access = PL1_R, .type = ARM_CP_CONST, 4647 .resetvalue = 0 }, 4648 { .name = "ID_AA64ISAR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4649 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 7, 4650 .access = PL1_R, .type = ARM_CP_CONST, 4651 .resetvalue = 0 }, 4652 { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64, 4653 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, 4654 .access = PL1_R, .type = ARM_CP_CONST, 4655 .resetvalue = cpu->id_aa64mmfr0 }, 4656 { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64, 4657 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1, 4658 .access = PL1_R, .type = ARM_CP_CONST, 4659 .resetvalue = cpu->id_aa64mmfr1 }, 4660 { .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4661 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2, 4662 .access = PL1_R, .type = ARM_CP_CONST, 4663 .resetvalue = 0 }, 4664 { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4665 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3, 4666 .access = PL1_R, .type = ARM_CP_CONST, 4667 .resetvalue = 0 }, 4668 { .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4669 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4, 4670 .access = PL1_R, .type = ARM_CP_CONST, 4671 .resetvalue = 0 }, 4672 { .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4673 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5, 4674 .access = PL1_R, .type = ARM_CP_CONST, 4675 .resetvalue = 0 }, 4676 { .name = "ID_AA64MMFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4677 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 6, 4678 .access = PL1_R, .type = ARM_CP_CONST, 4679 .resetvalue = 0 }, 4680 { .name = "ID_AA64MMFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4681 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 7, 4682 .access = PL1_R, .type = ARM_CP_CONST, 4683 .resetvalue = 0 }, 4684 { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64, 4685 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0, 4686 .access = PL1_R, .type = ARM_CP_CONST, 4687 .resetvalue = cpu->mvfr0 }, 4688 { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64, 4689 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1, 4690 .access = PL1_R, .type = ARM_CP_CONST, 4691 .resetvalue = cpu->mvfr1 }, 4692 { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64, 4693 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2, 4694 .access = PL1_R, .type = ARM_CP_CONST, 4695 .resetvalue = cpu->mvfr2 }, 4696 { .name = "MVFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4697 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3, 4698 .access = PL1_R, .type = ARM_CP_CONST, 4699 .resetvalue = 0 }, 4700 { .name = "MVFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4701 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4, 4702 .access = PL1_R, .type = ARM_CP_CONST, 4703 .resetvalue = 0 }, 4704 { .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4705 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5, 4706 .access = PL1_R, .type = ARM_CP_CONST, 4707 .resetvalue = 0 }, 4708 { .name = "MVFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4709 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6, 4710 .access = PL1_R, .type = ARM_CP_CONST, 4711 .resetvalue = 0 }, 4712 { .name = "MVFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4713 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7, 4714 .access = PL1_R, .type = ARM_CP_CONST, 4715 .resetvalue = 0 }, 4716 { .name = "PMCEID0", .state = ARM_CP_STATE_AA32, 4717 .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6, 4718 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, 4719 .resetvalue = cpu->pmceid0 }, 4720 { .name = "PMCEID0_EL0", .state = ARM_CP_STATE_AA64, 4721 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6, 4722 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, 4723 .resetvalue = cpu->pmceid0 }, 4724 { .name = "PMCEID1", .state = ARM_CP_STATE_AA32, 4725 .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 7, 4726 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, 4727 .resetvalue = cpu->pmceid1 }, 4728 { .name = "PMCEID1_EL0", .state = ARM_CP_STATE_AA64, 4729 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7, 4730 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, 4731 .resetvalue = cpu->pmceid1 }, 4732 REGINFO_SENTINEL 4733 }; 4734 /* RVBAR_EL1 is only implemented if EL1 is the highest EL */ 4735 if (!arm_feature(env, ARM_FEATURE_EL3) && 4736 !arm_feature(env, ARM_FEATURE_EL2)) { 4737 ARMCPRegInfo rvbar = { 4738 .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64, 4739 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, 4740 .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar 4741 }; 4742 define_one_arm_cp_reg(cpu, &rvbar); 4743 } 4744 define_arm_cp_regs(cpu, v8_idregs); 4745 define_arm_cp_regs(cpu, v8_cp_reginfo); 4746 } 4747 if (arm_feature(env, ARM_FEATURE_EL2)) { 4748 uint64_t vmpidr_def = mpidr_read_val(env); 4749 ARMCPRegInfo vpidr_regs[] = { 4750 { .name = "VPIDR", .state = ARM_CP_STATE_AA32, 4751 .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, 4752 .access = PL2_RW, .accessfn = access_el3_aa32ns, 4753 .resetvalue = cpu->midr, 4754 .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, 4755 { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64, 4756 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, 4757 .access = PL2_RW, .resetvalue = cpu->midr, 4758 .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, 4759 { .name = "VMPIDR", .state = ARM_CP_STATE_AA32, 4760 .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, 4761 .access = PL2_RW, .accessfn = access_el3_aa32ns, 4762 .resetvalue = vmpidr_def, 4763 .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) }, 4764 { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64, 4765 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, 4766 .access = PL2_RW, 4767 .resetvalue = vmpidr_def, 4768 .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) }, 4769 REGINFO_SENTINEL 4770 }; 4771 define_arm_cp_regs(cpu, vpidr_regs); 4772 define_arm_cp_regs(cpu, el2_cp_reginfo); 4773 /* RVBAR_EL2 is only implemented if EL2 is the highest EL */ 4774 if (!arm_feature(env, ARM_FEATURE_EL3)) { 4775 ARMCPRegInfo rvbar = { 4776 .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64, 4777 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1, 4778 .type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar 4779 }; 4780 define_one_arm_cp_reg(cpu, &rvbar); 4781 } 4782 } else { 4783 /* If EL2 is missing but higher ELs are enabled, we need to 4784 * register the no_el2 reginfos. 4785 */ 4786 if (arm_feature(env, ARM_FEATURE_EL3)) { 4787 /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value 4788 * of MIDR_EL1 and MPIDR_EL1. 4789 */ 4790 ARMCPRegInfo vpidr_regs[] = { 4791 { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH, 4792 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, 4793 .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, 4794 .type = ARM_CP_CONST, .resetvalue = cpu->midr, 4795 .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, 4796 { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH, 4797 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, 4798 .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, 4799 .type = ARM_CP_NO_RAW, 4800 .writefn = arm_cp_write_ignore, .readfn = mpidr_read }, 4801 REGINFO_SENTINEL 4802 }; 4803 define_arm_cp_regs(cpu, vpidr_regs); 4804 define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo); 4805 } 4806 } 4807 if (arm_feature(env, ARM_FEATURE_EL3)) { 4808 define_arm_cp_regs(cpu, el3_cp_reginfo); 4809 ARMCPRegInfo el3_regs[] = { 4810 { .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64, 4811 .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1, 4812 .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar }, 4813 { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64, 4814 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0, 4815 .access = PL3_RW, 4816 .raw_writefn = raw_write, .writefn = sctlr_write, 4817 .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]), 4818 .resetvalue = cpu->reset_sctlr }, 4819 REGINFO_SENTINEL 4820 }; 4821 4822 define_arm_cp_regs(cpu, el3_regs); 4823 } 4824 /* The behaviour of NSACR is sufficiently various that we don't 4825 * try to describe it in a single reginfo: 4826 * if EL3 is 64 bit, then trap to EL3 from S EL1, 4827 * reads as constant 0xc00 from NS EL1 and NS EL2 4828 * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2 4829 * if v7 without EL3, register doesn't exist 4830 * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2 4831 */ 4832 if (arm_feature(env, ARM_FEATURE_EL3)) { 4833 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 4834 ARMCPRegInfo nsacr = { 4835 .name = "NSACR", .type = ARM_CP_CONST, 4836 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, 4837 .access = PL1_RW, .accessfn = nsacr_access, 4838 .resetvalue = 0xc00 4839 }; 4840 define_one_arm_cp_reg(cpu, &nsacr); 4841 } else { 4842 ARMCPRegInfo nsacr = { 4843 .name = "NSACR", 4844 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, 4845 .access = PL3_RW | PL1_R, 4846 .resetvalue = 0, 4847 .fieldoffset = offsetof(CPUARMState, cp15.nsacr) 4848 }; 4849 define_one_arm_cp_reg(cpu, &nsacr); 4850 } 4851 } else { 4852 if (arm_feature(env, ARM_FEATURE_V8)) { 4853 ARMCPRegInfo nsacr = { 4854 .name = "NSACR", .type = ARM_CP_CONST, 4855 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, 4856 .access = PL1_R, 4857 .resetvalue = 0xc00 4858 }; 4859 define_one_arm_cp_reg(cpu, &nsacr); 4860 } 4861 } 4862 4863 if (arm_feature(env, ARM_FEATURE_MPU)) { 4864 if (arm_feature(env, ARM_FEATURE_V6)) { 4865 /* PMSAv6 not implemented */ 4866 assert(arm_feature(env, ARM_FEATURE_V7)); 4867 define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); 4868 define_arm_cp_regs(cpu, pmsav7_cp_reginfo); 4869 } else { 4870 define_arm_cp_regs(cpu, pmsav5_cp_reginfo); 4871 } 4872 } else { 4873 define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); 4874 define_arm_cp_regs(cpu, vmsa_cp_reginfo); 4875 } 4876 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { 4877 define_arm_cp_regs(cpu, t2ee_cp_reginfo); 4878 } 4879 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { 4880 define_arm_cp_regs(cpu, generic_timer_cp_reginfo); 4881 } 4882 if (arm_feature(env, ARM_FEATURE_VAPA)) { 4883 define_arm_cp_regs(cpu, vapa_cp_reginfo); 4884 } 4885 if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) { 4886 define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo); 4887 } 4888 if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) { 4889 define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo); 4890 } 4891 if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) { 4892 define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo); 4893 } 4894 if (arm_feature(env, ARM_FEATURE_OMAPCP)) { 4895 define_arm_cp_regs(cpu, omap_cp_reginfo); 4896 } 4897 if (arm_feature(env, ARM_FEATURE_STRONGARM)) { 4898 define_arm_cp_regs(cpu, strongarm_cp_reginfo); 4899 } 4900 if (arm_feature(env, ARM_FEATURE_XSCALE)) { 4901 define_arm_cp_regs(cpu, xscale_cp_reginfo); 4902 } 4903 if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) { 4904 define_arm_cp_regs(cpu, dummy_c15_cp_reginfo); 4905 } 4906 if (arm_feature(env, ARM_FEATURE_LPAE)) { 4907 define_arm_cp_regs(cpu, lpae_cp_reginfo); 4908 } 4909 /* Slightly awkwardly, the OMAP and StrongARM cores need all of 4910 * cp15 crn=0 to be writes-ignored, whereas for other cores they should 4911 * be read-only (ie write causes UNDEF exception). 4912 */ 4913 { 4914 ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = { 4915 /* Pre-v8 MIDR space. 4916 * Note that the MIDR isn't a simple constant register because 4917 * of the TI925 behaviour where writes to another register can 4918 * cause the MIDR value to change. 4919 * 4920 * Unimplemented registers in the c15 0 0 0 space default to 4921 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR 4922 * and friends override accordingly. 4923 */ 4924 { .name = "MIDR", 4925 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY, 4926 .access = PL1_R, .resetvalue = cpu->midr, 4927 .writefn = arm_cp_write_ignore, .raw_writefn = raw_write, 4928 .readfn = midr_read, 4929 .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), 4930 .type = ARM_CP_OVERRIDE }, 4931 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */ 4932 { .name = "DUMMY", 4933 .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY, 4934 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 4935 { .name = "DUMMY", 4936 .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY, 4937 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 4938 { .name = "DUMMY", 4939 .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY, 4940 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 4941 { .name = "DUMMY", 4942 .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY, 4943 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 4944 { .name = "DUMMY", 4945 .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY, 4946 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 4947 REGINFO_SENTINEL 4948 }; 4949 ARMCPRegInfo id_v8_midr_cp_reginfo[] = { 4950 { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH, 4951 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0, 4952 .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr, 4953 .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), 4954 .readfn = midr_read }, 4955 /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */ 4956 { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST, 4957 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4, 4958 .access = PL1_R, .resetvalue = cpu->midr }, 4959 { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST, 4960 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7, 4961 .access = PL1_R, .resetvalue = cpu->midr }, 4962 { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH, 4963 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6, 4964 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->revidr }, 4965 REGINFO_SENTINEL 4966 }; 4967 ARMCPRegInfo id_cp_reginfo[] = { 4968 /* These are common to v8 and pre-v8 */ 4969 { .name = "CTR", 4970 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1, 4971 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, 4972 { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64, 4973 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0, 4974 .access = PL0_R, .accessfn = ctr_el0_access, 4975 .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, 4976 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */ 4977 { .name = "TCMTR", 4978 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2, 4979 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 4980 REGINFO_SENTINEL 4981 }; 4982 /* TLBTR is specific to VMSA */ 4983 ARMCPRegInfo id_tlbtr_reginfo = { 4984 .name = "TLBTR", 4985 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3, 4986 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0, 4987 }; 4988 /* MPUIR is specific to PMSA V6+ */ 4989 ARMCPRegInfo id_mpuir_reginfo = { 4990 .name = "MPUIR", 4991 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4, 4992 .access = PL1_R, .type = ARM_CP_CONST, 4993 .resetvalue = cpu->pmsav7_dregion << 8 4994 }; 4995 ARMCPRegInfo crn0_wi_reginfo = { 4996 .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY, 4997 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W, 4998 .type = ARM_CP_NOP | ARM_CP_OVERRIDE 4999 }; 5000 if (arm_feature(env, ARM_FEATURE_OMAPCP) || 5001 arm_feature(env, ARM_FEATURE_STRONGARM)) { 5002 ARMCPRegInfo *r; 5003 /* Register the blanket "writes ignored" value first to cover the 5004 * whole space. Then update the specific ID registers to allow write 5005 * access, so that they ignore writes rather than causing them to 5006 * UNDEF. 5007 */ 5008 define_one_arm_cp_reg(cpu, &crn0_wi_reginfo); 5009 for (r = id_pre_v8_midr_cp_reginfo; 5010 r->type != ARM_CP_SENTINEL; r++) { 5011 r->access = PL1_RW; 5012 } 5013 for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) { 5014 r->access = PL1_RW; 5015 } 5016 id_tlbtr_reginfo.access = PL1_RW; 5017 id_tlbtr_reginfo.access = PL1_RW; 5018 } 5019 if (arm_feature(env, ARM_FEATURE_V8)) { 5020 define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo); 5021 } else { 5022 define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo); 5023 } 5024 define_arm_cp_regs(cpu, id_cp_reginfo); 5025 if (!arm_feature(env, ARM_FEATURE_MPU)) { 5026 define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo); 5027 } else if (arm_feature(env, ARM_FEATURE_V7)) { 5028 define_one_arm_cp_reg(cpu, &id_mpuir_reginfo); 5029 } 5030 } 5031 5032 if (arm_feature(env, ARM_FEATURE_MPIDR)) { 5033 define_arm_cp_regs(cpu, mpidr_cp_reginfo); 5034 } 5035 5036 if (arm_feature(env, ARM_FEATURE_AUXCR)) { 5037 ARMCPRegInfo auxcr_reginfo[] = { 5038 { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH, 5039 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1, 5040 .access = PL1_RW, .type = ARM_CP_CONST, 5041 .resetvalue = cpu->reset_auxcr }, 5042 { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH, 5043 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1, 5044 .access = PL2_RW, .type = ARM_CP_CONST, 5045 .resetvalue = 0 }, 5046 { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64, 5047 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1, 5048 .access = PL3_RW, .type = ARM_CP_CONST, 5049 .resetvalue = 0 }, 5050 REGINFO_SENTINEL 5051 }; 5052 define_arm_cp_regs(cpu, auxcr_reginfo); 5053 } 5054 5055 if (arm_feature(env, ARM_FEATURE_CBAR)) { 5056 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 5057 /* 32 bit view is [31:18] 0...0 [43:32]. */ 5058 uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18) 5059 | extract64(cpu->reset_cbar, 32, 12); 5060 ARMCPRegInfo cbar_reginfo[] = { 5061 { .name = "CBAR", 5062 .type = ARM_CP_CONST, 5063 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0, 5064 .access = PL1_R, .resetvalue = cpu->reset_cbar }, 5065 { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64, 5066 .type = ARM_CP_CONST, 5067 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0, 5068 .access = PL1_R, .resetvalue = cbar32 }, 5069 REGINFO_SENTINEL 5070 }; 5071 /* We don't implement a r/w 64 bit CBAR currently */ 5072 assert(arm_feature(env, ARM_FEATURE_CBAR_RO)); 5073 define_arm_cp_regs(cpu, cbar_reginfo); 5074 } else { 5075 ARMCPRegInfo cbar = { 5076 .name = "CBAR", 5077 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0, 5078 .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar, 5079 .fieldoffset = offsetof(CPUARMState, 5080 cp15.c15_config_base_address) 5081 }; 5082 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 5083 cbar.access = PL1_R; 5084 cbar.fieldoffset = 0; 5085 cbar.type = ARM_CP_CONST; 5086 } 5087 define_one_arm_cp_reg(cpu, &cbar); 5088 } 5089 } 5090 5091 if (arm_feature(env, ARM_FEATURE_VBAR)) { 5092 ARMCPRegInfo vbar_cp_reginfo[] = { 5093 { .name = "VBAR", .state = ARM_CP_STATE_BOTH, 5094 .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0, 5095 .access = PL1_RW, .writefn = vbar_write, 5096 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s), 5097 offsetof(CPUARMState, cp15.vbar_ns) }, 5098 .resetvalue = 0 }, 5099 REGINFO_SENTINEL 5100 }; 5101 define_arm_cp_regs(cpu, vbar_cp_reginfo); 5102 } 5103 5104 /* Generic registers whose values depend on the implementation */ 5105 { 5106 ARMCPRegInfo sctlr = { 5107 .name = "SCTLR", .state = ARM_CP_STATE_BOTH, 5108 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, 5109 .access = PL1_RW, 5110 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s), 5111 offsetof(CPUARMState, cp15.sctlr_ns) }, 5112 .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr, 5113 .raw_writefn = raw_write, 5114 }; 5115 if (arm_feature(env, ARM_FEATURE_XSCALE)) { 5116 /* Normally we would always end the TB on an SCTLR write, but Linux 5117 * arch/arm/mach-pxa/sleep.S expects two instructions following 5118 * an MMU enable to execute from cache. Imitate this behaviour. 5119 */ 5120 sctlr.type |= ARM_CP_SUPPRESS_TB_END; 5121 } 5122 define_one_arm_cp_reg(cpu, &sctlr); 5123 } 5124 } 5125 5126 ARMCPU *cpu_arm_init(const char *cpu_model) 5127 { 5128 return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model)); 5129 } 5130 5131 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) 5132 { 5133 CPUState *cs = CPU(cpu); 5134 CPUARMState *env = &cpu->env; 5135 5136 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 5137 gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg, 5138 aarch64_fpu_gdb_set_reg, 5139 34, "aarch64-fpu.xml", 0); 5140 } else if (arm_feature(env, ARM_FEATURE_NEON)) { 5141 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 5142 51, "arm-neon.xml", 0); 5143 } else if (arm_feature(env, ARM_FEATURE_VFP3)) { 5144 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 5145 35, "arm-vfp3.xml", 0); 5146 } else if (arm_feature(env, ARM_FEATURE_VFP)) { 5147 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 5148 19, "arm-vfp.xml", 0); 5149 } 5150 } 5151 5152 /* Sort alphabetically by type name, except for "any". */ 5153 static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b) 5154 { 5155 ObjectClass *class_a = (ObjectClass *)a; 5156 ObjectClass *class_b = (ObjectClass *)b; 5157 const char *name_a, *name_b; 5158 5159 name_a = object_class_get_name(class_a); 5160 name_b = object_class_get_name(class_b); 5161 if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) { 5162 return 1; 5163 } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) { 5164 return -1; 5165 } else { 5166 return strcmp(name_a, name_b); 5167 } 5168 } 5169 5170 static void arm_cpu_list_entry(gpointer data, gpointer user_data) 5171 { 5172 ObjectClass *oc = data; 5173 CPUListState *s = user_data; 5174 const char *typename; 5175 char *name; 5176 5177 typename = object_class_get_name(oc); 5178 name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU)); 5179 (*s->cpu_fprintf)(s->file, " %s\n", 5180 name); 5181 g_free(name); 5182 } 5183 5184 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf) 5185 { 5186 CPUListState s = { 5187 .file = f, 5188 .cpu_fprintf = cpu_fprintf, 5189 }; 5190 GSList *list; 5191 5192 list = object_class_get_list(TYPE_ARM_CPU, false); 5193 list = g_slist_sort(list, arm_cpu_list_compare); 5194 (*cpu_fprintf)(f, "Available CPUs:\n"); 5195 g_slist_foreach(list, arm_cpu_list_entry, &s); 5196 g_slist_free(list); 5197 #ifdef CONFIG_KVM 5198 /* The 'host' CPU type is dynamically registered only if KVM is 5199 * enabled, so we have to special-case it here: 5200 */ 5201 (*cpu_fprintf)(f, " host (only available in KVM mode)\n"); 5202 #endif 5203 } 5204 5205 static void arm_cpu_add_definition(gpointer data, gpointer user_data) 5206 { 5207 ObjectClass *oc = data; 5208 CpuDefinitionInfoList **cpu_list = user_data; 5209 CpuDefinitionInfoList *entry; 5210 CpuDefinitionInfo *info; 5211 const char *typename; 5212 5213 typename = object_class_get_name(oc); 5214 info = g_malloc0(sizeof(*info)); 5215 info->name = g_strndup(typename, 5216 strlen(typename) - strlen("-" TYPE_ARM_CPU)); 5217 5218 entry = g_malloc0(sizeof(*entry)); 5219 entry->value = info; 5220 entry->next = *cpu_list; 5221 *cpu_list = entry; 5222 } 5223 5224 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) 5225 { 5226 CpuDefinitionInfoList *cpu_list = NULL; 5227 GSList *list; 5228 5229 list = object_class_get_list(TYPE_ARM_CPU, false); 5230 g_slist_foreach(list, arm_cpu_add_definition, &cpu_list); 5231 g_slist_free(list); 5232 5233 return cpu_list; 5234 } 5235 5236 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, 5237 void *opaque, int state, int secstate, 5238 int crm, int opc1, int opc2) 5239 { 5240 /* Private utility function for define_one_arm_cp_reg_with_opaque(): 5241 * add a single reginfo struct to the hash table. 5242 */ 5243 uint32_t *key = g_new(uint32_t, 1); 5244 ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo)); 5245 int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0; 5246 int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; 5247 5248 /* Reset the secure state to the specific incoming state. This is 5249 * necessary as the register may have been defined with both states. 5250 */ 5251 r2->secure = secstate; 5252 5253 if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { 5254 /* Register is banked (using both entries in array). 5255 * Overwriting fieldoffset as the array is only used to define 5256 * banked registers but later only fieldoffset is used. 5257 */ 5258 r2->fieldoffset = r->bank_fieldoffsets[ns]; 5259 } 5260 5261 if (state == ARM_CP_STATE_AA32) { 5262 if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { 5263 /* If the register is banked then we don't need to migrate or 5264 * reset the 32-bit instance in certain cases: 5265 * 5266 * 1) If the register has both 32-bit and 64-bit instances then we 5267 * can count on the 64-bit instance taking care of the 5268 * non-secure bank. 5269 * 2) If ARMv8 is enabled then we can count on a 64-bit version 5270 * taking care of the secure bank. This requires that separate 5271 * 32 and 64-bit definitions are provided. 5272 */ 5273 if ((r->state == ARM_CP_STATE_BOTH && ns) || 5274 (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) { 5275 r2->type |= ARM_CP_ALIAS; 5276 } 5277 } else if ((secstate != r->secure) && !ns) { 5278 /* The register is not banked so we only want to allow migration of 5279 * the non-secure instance. 5280 */ 5281 r2->type |= ARM_CP_ALIAS; 5282 } 5283 5284 if (r->state == ARM_CP_STATE_BOTH) { 5285 /* We assume it is a cp15 register if the .cp field is left unset. 5286 */ 5287 if (r2->cp == 0) { 5288 r2->cp = 15; 5289 } 5290 5291 #ifdef HOST_WORDS_BIGENDIAN 5292 if (r2->fieldoffset) { 5293 r2->fieldoffset += sizeof(uint32_t); 5294 } 5295 #endif 5296 } 5297 } 5298 if (state == ARM_CP_STATE_AA64) { 5299 /* To allow abbreviation of ARMCPRegInfo 5300 * definitions, we treat cp == 0 as equivalent to 5301 * the value for "standard guest-visible sysreg". 5302 * STATE_BOTH definitions are also always "standard 5303 * sysreg" in their AArch64 view (the .cp value may 5304 * be non-zero for the benefit of the AArch32 view). 5305 */ 5306 if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) { 5307 r2->cp = CP_REG_ARM64_SYSREG_CP; 5308 } 5309 *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm, 5310 r2->opc0, opc1, opc2); 5311 } else { 5312 *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2); 5313 } 5314 if (opaque) { 5315 r2->opaque = opaque; 5316 } 5317 /* reginfo passed to helpers is correct for the actual access, 5318 * and is never ARM_CP_STATE_BOTH: 5319 */ 5320 r2->state = state; 5321 /* Make sure reginfo passed to helpers for wildcarded regs 5322 * has the correct crm/opc1/opc2 for this reg, not CP_ANY: 5323 */ 5324 r2->crm = crm; 5325 r2->opc1 = opc1; 5326 r2->opc2 = opc2; 5327 /* By convention, for wildcarded registers only the first 5328 * entry is used for migration; the others are marked as 5329 * ALIAS so we don't try to transfer the register 5330 * multiple times. Special registers (ie NOP/WFI) are 5331 * never migratable and not even raw-accessible. 5332 */ 5333 if ((r->type & ARM_CP_SPECIAL)) { 5334 r2->type |= ARM_CP_NO_RAW; 5335 } 5336 if (((r->crm == CP_ANY) && crm != 0) || 5337 ((r->opc1 == CP_ANY) && opc1 != 0) || 5338 ((r->opc2 == CP_ANY) && opc2 != 0)) { 5339 r2->type |= ARM_CP_ALIAS; 5340 } 5341 5342 /* Check that raw accesses are either forbidden or handled. Note that 5343 * we can't assert this earlier because the setup of fieldoffset for 5344 * banked registers has to be done first. 5345 */ 5346 if (!(r2->type & ARM_CP_NO_RAW)) { 5347 assert(!raw_accessors_invalid(r2)); 5348 } 5349 5350 /* Overriding of an existing definition must be explicitly 5351 * requested. 5352 */ 5353 if (!(r->type & ARM_CP_OVERRIDE)) { 5354 ARMCPRegInfo *oldreg; 5355 oldreg = g_hash_table_lookup(cpu->cp_regs, key); 5356 if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) { 5357 fprintf(stderr, "Register redefined: cp=%d %d bit " 5358 "crn=%d crm=%d opc1=%d opc2=%d, " 5359 "was %s, now %s\n", r2->cp, 32 + 32 * is64, 5360 r2->crn, r2->crm, r2->opc1, r2->opc2, 5361 oldreg->name, r2->name); 5362 g_assert_not_reached(); 5363 } 5364 } 5365 g_hash_table_insert(cpu->cp_regs, key, r2); 5366 } 5367 5368 5369 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, 5370 const ARMCPRegInfo *r, void *opaque) 5371 { 5372 /* Define implementations of coprocessor registers. 5373 * We store these in a hashtable because typically 5374 * there are less than 150 registers in a space which 5375 * is 16*16*16*8*8 = 262144 in size. 5376 * Wildcarding is supported for the crm, opc1 and opc2 fields. 5377 * If a register is defined twice then the second definition is 5378 * used, so this can be used to define some generic registers and 5379 * then override them with implementation specific variations. 5380 * At least one of the original and the second definition should 5381 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard 5382 * against accidental use. 5383 * 5384 * The state field defines whether the register is to be 5385 * visible in the AArch32 or AArch64 execution state. If the 5386 * state is set to ARM_CP_STATE_BOTH then we synthesise a 5387 * reginfo structure for the AArch32 view, which sees the lower 5388 * 32 bits of the 64 bit register. 5389 * 5390 * Only registers visible in AArch64 may set r->opc0; opc0 cannot 5391 * be wildcarded. AArch64 registers are always considered to be 64 5392 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of 5393 * the register, if any. 5394 */ 5395 int crm, opc1, opc2, state; 5396 int crmmin = (r->crm == CP_ANY) ? 0 : r->crm; 5397 int crmmax = (r->crm == CP_ANY) ? 15 : r->crm; 5398 int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1; 5399 int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1; 5400 int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2; 5401 int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2; 5402 /* 64 bit registers have only CRm and Opc1 fields */ 5403 assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn))); 5404 /* op0 only exists in the AArch64 encodings */ 5405 assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0)); 5406 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */ 5407 assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT)); 5408 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1 5409 * encodes a minimum access level for the register. We roll this 5410 * runtime check into our general permission check code, so check 5411 * here that the reginfo's specified permissions are strict enough 5412 * to encompass the generic architectural permission check. 5413 */ 5414 if (r->state != ARM_CP_STATE_AA32) { 5415 int mask = 0; 5416 switch (r->opc1) { 5417 case 0: case 1: case 2: 5418 /* min_EL EL1 */ 5419 mask = PL1_RW; 5420 break; 5421 case 3: 5422 /* min_EL EL0 */ 5423 mask = PL0_RW; 5424 break; 5425 case 4: 5426 /* min_EL EL2 */ 5427 mask = PL2_RW; 5428 break; 5429 case 5: 5430 /* unallocated encoding, so not possible */ 5431 assert(false); 5432 break; 5433 case 6: 5434 /* min_EL EL3 */ 5435 mask = PL3_RW; 5436 break; 5437 case 7: 5438 /* min_EL EL1, secure mode only (we don't check the latter) */ 5439 mask = PL1_RW; 5440 break; 5441 default: 5442 /* broken reginfo with out-of-range opc1 */ 5443 assert(false); 5444 break; 5445 } 5446 /* assert our permissions are not too lax (stricter is fine) */ 5447 assert((r->access & ~mask) == 0); 5448 } 5449 5450 /* Check that the register definition has enough info to handle 5451 * reads and writes if they are permitted. 5452 */ 5453 if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) { 5454 if (r->access & PL3_R) { 5455 assert((r->fieldoffset || 5456 (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || 5457 r->readfn); 5458 } 5459 if (r->access & PL3_W) { 5460 assert((r->fieldoffset || 5461 (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || 5462 r->writefn); 5463 } 5464 } 5465 /* Bad type field probably means missing sentinel at end of reg list */ 5466 assert(cptype_valid(r->type)); 5467 for (crm = crmmin; crm <= crmmax; crm++) { 5468 for (opc1 = opc1min; opc1 <= opc1max; opc1++) { 5469 for (opc2 = opc2min; opc2 <= opc2max; opc2++) { 5470 for (state = ARM_CP_STATE_AA32; 5471 state <= ARM_CP_STATE_AA64; state++) { 5472 if (r->state != state && r->state != ARM_CP_STATE_BOTH) { 5473 continue; 5474 } 5475 if (state == ARM_CP_STATE_AA32) { 5476 /* Under AArch32 CP registers can be common 5477 * (same for secure and non-secure world) or banked. 5478 */ 5479 switch (r->secure) { 5480 case ARM_CP_SECSTATE_S: 5481 case ARM_CP_SECSTATE_NS: 5482 add_cpreg_to_hashtable(cpu, r, opaque, state, 5483 r->secure, crm, opc1, opc2); 5484 break; 5485 default: 5486 add_cpreg_to_hashtable(cpu, r, opaque, state, 5487 ARM_CP_SECSTATE_S, 5488 crm, opc1, opc2); 5489 add_cpreg_to_hashtable(cpu, r, opaque, state, 5490 ARM_CP_SECSTATE_NS, 5491 crm, opc1, opc2); 5492 break; 5493 } 5494 } else { 5495 /* AArch64 registers get mapped to non-secure instance 5496 * of AArch32 */ 5497 add_cpreg_to_hashtable(cpu, r, opaque, state, 5498 ARM_CP_SECSTATE_NS, 5499 crm, opc1, opc2); 5500 } 5501 } 5502 } 5503 } 5504 } 5505 } 5506 5507 void define_arm_cp_regs_with_opaque(ARMCPU *cpu, 5508 const ARMCPRegInfo *regs, void *opaque) 5509 { 5510 /* Define a whole list of registers */ 5511 const ARMCPRegInfo *r; 5512 for (r = regs; r->type != ARM_CP_SENTINEL; r++) { 5513 define_one_arm_cp_reg_with_opaque(cpu, r, opaque); 5514 } 5515 } 5516 5517 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp) 5518 { 5519 return g_hash_table_lookup(cpregs, &encoded_cp); 5520 } 5521 5522 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, 5523 uint64_t value) 5524 { 5525 /* Helper coprocessor write function for write-ignore registers */ 5526 } 5527 5528 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri) 5529 { 5530 /* Helper coprocessor write function for read-as-zero registers */ 5531 return 0; 5532 } 5533 5534 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque) 5535 { 5536 /* Helper coprocessor reset function for do-nothing-on-reset registers */ 5537 } 5538 5539 static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type) 5540 { 5541 /* Return true if it is not valid for us to switch to 5542 * this CPU mode (ie all the UNPREDICTABLE cases in 5543 * the ARM ARM CPSRWriteByInstr pseudocode). 5544 */ 5545 5546 /* Changes to or from Hyp via MSR and CPS are illegal. */ 5547 if (write_type == CPSRWriteByInstr && 5548 ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_HYP || 5549 mode == ARM_CPU_MODE_HYP)) { 5550 return 1; 5551 } 5552 5553 switch (mode) { 5554 case ARM_CPU_MODE_USR: 5555 return 0; 5556 case ARM_CPU_MODE_SYS: 5557 case ARM_CPU_MODE_SVC: 5558 case ARM_CPU_MODE_ABT: 5559 case ARM_CPU_MODE_UND: 5560 case ARM_CPU_MODE_IRQ: 5561 case ARM_CPU_MODE_FIQ: 5562 /* Note that we don't implement the IMPDEF NSACR.RFR which in v7 5563 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.) 5564 */ 5565 /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR 5566 * and CPS are treated as illegal mode changes. 5567 */ 5568 if (write_type == CPSRWriteByInstr && 5569 (env->cp15.hcr_el2 & HCR_TGE) && 5570 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON && 5571 !arm_is_secure_below_el3(env)) { 5572 return 1; 5573 } 5574 return 0; 5575 case ARM_CPU_MODE_HYP: 5576 return !arm_feature(env, ARM_FEATURE_EL2) 5577 || arm_current_el(env) < 2 || arm_is_secure(env); 5578 case ARM_CPU_MODE_MON: 5579 return arm_current_el(env) < 3; 5580 default: 5581 return 1; 5582 } 5583 } 5584 5585 uint32_t cpsr_read(CPUARMState *env) 5586 { 5587 int ZF; 5588 ZF = (env->ZF == 0); 5589 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) | 5590 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 5591 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25) 5592 | ((env->condexec_bits & 0xfc) << 8) 5593 | (env->GE << 16) | (env->daif & CPSR_AIF); 5594 } 5595 5596 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 5597 CPSRWriteType write_type) 5598 { 5599 uint32_t changed_daif; 5600 5601 if (mask & CPSR_NZCV) { 5602 env->ZF = (~val) & CPSR_Z; 5603 env->NF = val; 5604 env->CF = (val >> 29) & 1; 5605 env->VF = (val << 3) & 0x80000000; 5606 } 5607 if (mask & CPSR_Q) 5608 env->QF = ((val & CPSR_Q) != 0); 5609 if (mask & CPSR_T) 5610 env->thumb = ((val & CPSR_T) != 0); 5611 if (mask & CPSR_IT_0_1) { 5612 env->condexec_bits &= ~3; 5613 env->condexec_bits |= (val >> 25) & 3; 5614 } 5615 if (mask & CPSR_IT_2_7) { 5616 env->condexec_bits &= 3; 5617 env->condexec_bits |= (val >> 8) & 0xfc; 5618 } 5619 if (mask & CPSR_GE) { 5620 env->GE = (val >> 16) & 0xf; 5621 } 5622 5623 /* In a V7 implementation that includes the security extensions but does 5624 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control 5625 * whether non-secure software is allowed to change the CPSR_F and CPSR_A 5626 * bits respectively. 5627 * 5628 * In a V8 implementation, it is permitted for privileged software to 5629 * change the CPSR A/F bits regardless of the SCR.AW/FW bits. 5630 */ 5631 if (write_type != CPSRWriteRaw && !arm_feature(env, ARM_FEATURE_V8) && 5632 arm_feature(env, ARM_FEATURE_EL3) && 5633 !arm_feature(env, ARM_FEATURE_EL2) && 5634 !arm_is_secure(env)) { 5635 5636 changed_daif = (env->daif ^ val) & mask; 5637 5638 if (changed_daif & CPSR_A) { 5639 /* Check to see if we are allowed to change the masking of async 5640 * abort exceptions from a non-secure state. 5641 */ 5642 if (!(env->cp15.scr_el3 & SCR_AW)) { 5643 qemu_log_mask(LOG_GUEST_ERROR, 5644 "Ignoring attempt to switch CPSR_A flag from " 5645 "non-secure world with SCR.AW bit clear\n"); 5646 mask &= ~CPSR_A; 5647 } 5648 } 5649 5650 if (changed_daif & CPSR_F) { 5651 /* Check to see if we are allowed to change the masking of FIQ 5652 * exceptions from a non-secure state. 5653 */ 5654 if (!(env->cp15.scr_el3 & SCR_FW)) { 5655 qemu_log_mask(LOG_GUEST_ERROR, 5656 "Ignoring attempt to switch CPSR_F flag from " 5657 "non-secure world with SCR.FW bit clear\n"); 5658 mask &= ~CPSR_F; 5659 } 5660 5661 /* Check whether non-maskable FIQ (NMFI) support is enabled. 5662 * If this bit is set software is not allowed to mask 5663 * FIQs, but is allowed to set CPSR_F to 0. 5664 */ 5665 if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) && 5666 (val & CPSR_F)) { 5667 qemu_log_mask(LOG_GUEST_ERROR, 5668 "Ignoring attempt to enable CPSR_F flag " 5669 "(non-maskable FIQ [NMFI] support enabled)\n"); 5670 mask &= ~CPSR_F; 5671 } 5672 } 5673 } 5674 5675 env->daif &= ~(CPSR_AIF & mask); 5676 env->daif |= val & CPSR_AIF & mask; 5677 5678 if (write_type != CPSRWriteRaw && 5679 ((env->uncached_cpsr ^ val) & mask & CPSR_M)) { 5680 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR) { 5681 /* Note that we can only get here in USR mode if this is a 5682 * gdb stub write; for this case we follow the architectural 5683 * behaviour for guest writes in USR mode of ignoring an attempt 5684 * to switch mode. (Those are caught by translate.c for writes 5685 * triggered by guest instructions.) 5686 */ 5687 mask &= ~CPSR_M; 5688 } else if (bad_mode_switch(env, val & CPSR_M, write_type)) { 5689 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in 5690 * v7, and has defined behaviour in v8: 5691 * + leave CPSR.M untouched 5692 * + allow changes to the other CPSR fields 5693 * + set PSTATE.IL 5694 * For user changes via the GDB stub, we don't set PSTATE.IL, 5695 * as this would be unnecessarily harsh for a user error. 5696 */ 5697 mask &= ~CPSR_M; 5698 if (write_type != CPSRWriteByGDBStub && 5699 arm_feature(env, ARM_FEATURE_V8)) { 5700 mask |= CPSR_IL; 5701 val |= CPSR_IL; 5702 } 5703 } else { 5704 switch_mode(env, val & CPSR_M); 5705 } 5706 } 5707 mask &= ~CACHED_CPSR_BITS; 5708 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask); 5709 } 5710 5711 /* Sign/zero extend */ 5712 uint32_t HELPER(sxtb16)(uint32_t x) 5713 { 5714 uint32_t res; 5715 res = (uint16_t)(int8_t)x; 5716 res |= (uint32_t)(int8_t)(x >> 16) << 16; 5717 return res; 5718 } 5719 5720 uint32_t HELPER(uxtb16)(uint32_t x) 5721 { 5722 uint32_t res; 5723 res = (uint16_t)(uint8_t)x; 5724 res |= (uint32_t)(uint8_t)(x >> 16) << 16; 5725 return res; 5726 } 5727 5728 uint32_t HELPER(clz)(uint32_t x) 5729 { 5730 return clz32(x); 5731 } 5732 5733 int32_t HELPER(sdiv)(int32_t num, int32_t den) 5734 { 5735 if (den == 0) 5736 return 0; 5737 if (num == INT_MIN && den == -1) 5738 return INT_MIN; 5739 return num / den; 5740 } 5741 5742 uint32_t HELPER(udiv)(uint32_t num, uint32_t den) 5743 { 5744 if (den == 0) 5745 return 0; 5746 return num / den; 5747 } 5748 5749 uint32_t HELPER(rbit)(uint32_t x) 5750 { 5751 return revbit32(x); 5752 } 5753 5754 #if defined(CONFIG_USER_ONLY) 5755 5756 /* These should probably raise undefined insn exceptions. */ 5757 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) 5758 { 5759 ARMCPU *cpu = arm_env_get_cpu(env); 5760 5761 cpu_abort(CPU(cpu), "v7m_msr %d\n", reg); 5762 } 5763 5764 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) 5765 { 5766 ARMCPU *cpu = arm_env_get_cpu(env); 5767 5768 cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg); 5769 return 0; 5770 } 5771 5772 void switch_mode(CPUARMState *env, int mode) 5773 { 5774 ARMCPU *cpu = arm_env_get_cpu(env); 5775 5776 if (mode != ARM_CPU_MODE_USR) { 5777 cpu_abort(CPU(cpu), "Tried to switch out of user mode\n"); 5778 } 5779 } 5780 5781 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 5782 uint32_t cur_el, bool secure) 5783 { 5784 return 1; 5785 } 5786 5787 void aarch64_sync_64_to_32(CPUARMState *env) 5788 { 5789 g_assert_not_reached(); 5790 } 5791 5792 #else 5793 5794 void switch_mode(CPUARMState *env, int mode) 5795 { 5796 int old_mode; 5797 int i; 5798 5799 old_mode = env->uncached_cpsr & CPSR_M; 5800 if (mode == old_mode) 5801 return; 5802 5803 if (old_mode == ARM_CPU_MODE_FIQ) { 5804 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t)); 5805 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); 5806 } else if (mode == ARM_CPU_MODE_FIQ) { 5807 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t)); 5808 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t)); 5809 } 5810 5811 i = bank_number(old_mode); 5812 env->banked_r13[i] = env->regs[13]; 5813 env->banked_r14[i] = env->regs[14]; 5814 env->banked_spsr[i] = env->spsr; 5815 5816 i = bank_number(mode); 5817 env->regs[13] = env->banked_r13[i]; 5818 env->regs[14] = env->banked_r14[i]; 5819 env->spsr = env->banked_spsr[i]; 5820 } 5821 5822 /* Physical Interrupt Target EL Lookup Table 5823 * 5824 * [ From ARM ARM section G1.13.4 (Table G1-15) ] 5825 * 5826 * The below multi-dimensional table is used for looking up the target 5827 * exception level given numerous condition criteria. Specifically, the 5828 * target EL is based on SCR and HCR routing controls as well as the 5829 * currently executing EL and secure state. 5830 * 5831 * Dimensions: 5832 * target_el_table[2][2][2][2][2][4] 5833 * | | | | | +--- Current EL 5834 * | | | | +------ Non-secure(0)/Secure(1) 5835 * | | | +--------- HCR mask override 5836 * | | +------------ SCR exec state control 5837 * | +--------------- SCR mask override 5838 * +------------------ 32-bit(0)/64-bit(1) EL3 5839 * 5840 * The table values are as such: 5841 * 0-3 = EL0-EL3 5842 * -1 = Cannot occur 5843 * 5844 * The ARM ARM target EL table includes entries indicating that an "exception 5845 * is not taken". The two cases where this is applicable are: 5846 * 1) An exception is taken from EL3 but the SCR does not have the exception 5847 * routed to EL3. 5848 * 2) An exception is taken from EL2 but the HCR does not have the exception 5849 * routed to EL2. 5850 * In these two cases, the below table contain a target of EL1. This value is 5851 * returned as it is expected that the consumer of the table data will check 5852 * for "target EL >= current EL" to ensure the exception is not taken. 5853 * 5854 * SCR HCR 5855 * 64 EA AMO From 5856 * BIT IRQ IMO Non-secure Secure 5857 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3 5858 */ 5859 static const int8_t target_el_table[2][2][2][2][2][4] = { 5860 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },}, 5861 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},}, 5862 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },}, 5863 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},}, 5864 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },}, 5865 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},}, 5866 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },}, 5867 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},}, 5868 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },}, 5869 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},}, 5870 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, -1, 1 },}, 5871 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},}, 5872 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },}, 5873 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},}, 5874 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },}, 5875 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},},}, 5876 }; 5877 5878 /* 5879 * Determine the target EL for physical exceptions 5880 */ 5881 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 5882 uint32_t cur_el, bool secure) 5883 { 5884 CPUARMState *env = cs->env_ptr; 5885 int rw; 5886 int scr; 5887 int hcr; 5888 int target_el; 5889 /* Is the highest EL AArch64? */ 5890 int is64 = arm_feature(env, ARM_FEATURE_AARCH64); 5891 5892 if (arm_feature(env, ARM_FEATURE_EL3)) { 5893 rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW); 5894 } else { 5895 /* Either EL2 is the highest EL (and so the EL2 register width 5896 * is given by is64); or there is no EL2 or EL3, in which case 5897 * the value of 'rw' does not affect the table lookup anyway. 5898 */ 5899 rw = is64; 5900 } 5901 5902 switch (excp_idx) { 5903 case EXCP_IRQ: 5904 scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ); 5905 hcr = ((env->cp15.hcr_el2 & HCR_IMO) == HCR_IMO); 5906 break; 5907 case EXCP_FIQ: 5908 scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ); 5909 hcr = ((env->cp15.hcr_el2 & HCR_FMO) == HCR_FMO); 5910 break; 5911 default: 5912 scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA); 5913 hcr = ((env->cp15.hcr_el2 & HCR_AMO) == HCR_AMO); 5914 break; 5915 }; 5916 5917 /* If HCR.TGE is set then HCR is treated as being 1 */ 5918 hcr |= ((env->cp15.hcr_el2 & HCR_TGE) == HCR_TGE); 5919 5920 /* Perform a table-lookup for the target EL given the current state */ 5921 target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el]; 5922 5923 assert(target_el > 0); 5924 5925 return target_el; 5926 } 5927 5928 static void v7m_push(CPUARMState *env, uint32_t val) 5929 { 5930 CPUState *cs = CPU(arm_env_get_cpu(env)); 5931 5932 env->regs[13] -= 4; 5933 stl_phys(cs->as, env->regs[13], val); 5934 } 5935 5936 static uint32_t v7m_pop(CPUARMState *env) 5937 { 5938 CPUState *cs = CPU(arm_env_get_cpu(env)); 5939 uint32_t val; 5940 5941 val = ldl_phys(cs->as, env->regs[13]); 5942 env->regs[13] += 4; 5943 return val; 5944 } 5945 5946 /* Switch to V7M main or process stack pointer. */ 5947 static void switch_v7m_sp(CPUARMState *env, int process) 5948 { 5949 uint32_t tmp; 5950 if (env->v7m.current_sp != process) { 5951 tmp = env->v7m.other_sp; 5952 env->v7m.other_sp = env->regs[13]; 5953 env->regs[13] = tmp; 5954 env->v7m.current_sp = process; 5955 } 5956 } 5957 5958 static void do_v7m_exception_exit(CPUARMState *env) 5959 { 5960 uint32_t type; 5961 uint32_t xpsr; 5962 5963 type = env->regs[15]; 5964 if (env->v7m.exception != 0) 5965 armv7m_nvic_complete_irq(env->nvic, env->v7m.exception); 5966 5967 /* Switch to the target stack. */ 5968 switch_v7m_sp(env, (type & 4) != 0); 5969 /* Pop registers. */ 5970 env->regs[0] = v7m_pop(env); 5971 env->regs[1] = v7m_pop(env); 5972 env->regs[2] = v7m_pop(env); 5973 env->regs[3] = v7m_pop(env); 5974 env->regs[12] = v7m_pop(env); 5975 env->regs[14] = v7m_pop(env); 5976 env->regs[15] = v7m_pop(env); 5977 if (env->regs[15] & 1) { 5978 qemu_log_mask(LOG_GUEST_ERROR, 5979 "M profile return from interrupt with misaligned " 5980 "PC is UNPREDICTABLE\n"); 5981 /* Actual hardware seems to ignore the lsbit, and there are several 5982 * RTOSes out there which incorrectly assume the r15 in the stack 5983 * frame should be a Thumb-style "lsbit indicates ARM/Thumb" value. 5984 */ 5985 env->regs[15] &= ~1U; 5986 } 5987 xpsr = v7m_pop(env); 5988 xpsr_write(env, xpsr, 0xfffffdff); 5989 /* Undo stack alignment. */ 5990 if (xpsr & 0x200) 5991 env->regs[13] |= 4; 5992 /* ??? The exception return type specifies Thread/Handler mode. However 5993 this is also implied by the xPSR value. Not sure what to do 5994 if there is a mismatch. */ 5995 /* ??? Likewise for mismatches between the CONTROL register and the stack 5996 pointer. */ 5997 } 5998 5999 static void arm_log_exception(int idx) 6000 { 6001 if (qemu_loglevel_mask(CPU_LOG_INT)) { 6002 const char *exc = NULL; 6003 6004 if (idx >= 0 && idx < ARRAY_SIZE(excnames)) { 6005 exc = excnames[idx]; 6006 } 6007 if (!exc) { 6008 exc = "unknown"; 6009 } 6010 qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc); 6011 } 6012 } 6013 6014 void arm_v7m_cpu_do_interrupt(CPUState *cs) 6015 { 6016 ARMCPU *cpu = ARM_CPU(cs); 6017 CPUARMState *env = &cpu->env; 6018 uint32_t xpsr = xpsr_read(env); 6019 uint32_t lr; 6020 uint32_t addr; 6021 6022 arm_log_exception(cs->exception_index); 6023 6024 lr = 0xfffffff1; 6025 if (env->v7m.current_sp) 6026 lr |= 4; 6027 if (env->v7m.exception == 0) 6028 lr |= 8; 6029 6030 /* For exceptions we just mark as pending on the NVIC, and let that 6031 handle it. */ 6032 /* TODO: Need to escalate if the current priority is higher than the 6033 one we're raising. */ 6034 switch (cs->exception_index) { 6035 case EXCP_UDEF: 6036 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); 6037 return; 6038 case EXCP_SWI: 6039 /* The PC already points to the next instruction. */ 6040 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC); 6041 return; 6042 case EXCP_PREFETCH_ABORT: 6043 case EXCP_DATA_ABORT: 6044 /* TODO: if we implemented the MPU registers, this is where we 6045 * should set the MMFAR, etc from exception.fsr and exception.vaddress. 6046 */ 6047 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM); 6048 return; 6049 case EXCP_BKPT: 6050 if (semihosting_enabled()) { 6051 int nr; 6052 nr = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env)) & 0xff; 6053 if (nr == 0xab) { 6054 env->regs[15] += 2; 6055 qemu_log_mask(CPU_LOG_INT, 6056 "...handling as semihosting call 0x%x\n", 6057 env->regs[0]); 6058 env->regs[0] = do_arm_semihosting(env); 6059 return; 6060 } 6061 } 6062 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG); 6063 return; 6064 case EXCP_IRQ: 6065 env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic); 6066 break; 6067 case EXCP_EXCEPTION_EXIT: 6068 do_v7m_exception_exit(env); 6069 return; 6070 default: 6071 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); 6072 return; /* Never happens. Keep compiler happy. */ 6073 } 6074 6075 /* Align stack pointer. */ 6076 /* ??? Should only do this if Configuration Control Register 6077 STACKALIGN bit is set. */ 6078 if (env->regs[13] & 4) { 6079 env->regs[13] -= 4; 6080 xpsr |= 0x200; 6081 } 6082 /* Switch to the handler mode. */ 6083 v7m_push(env, xpsr); 6084 v7m_push(env, env->regs[15]); 6085 v7m_push(env, env->regs[14]); 6086 v7m_push(env, env->regs[12]); 6087 v7m_push(env, env->regs[3]); 6088 v7m_push(env, env->regs[2]); 6089 v7m_push(env, env->regs[1]); 6090 v7m_push(env, env->regs[0]); 6091 switch_v7m_sp(env, 0); 6092 /* Clear IT bits */ 6093 env->condexec_bits = 0; 6094 env->regs[14] = lr; 6095 addr = ldl_phys(cs->as, env->v7m.vecbase + env->v7m.exception * 4); 6096 env->regs[15] = addr & 0xfffffffe; 6097 env->thumb = addr & 1; 6098 } 6099 6100 /* Function used to synchronize QEMU's AArch64 register set with AArch32 6101 * register set. This is necessary when switching between AArch32 and AArch64 6102 * execution state. 6103 */ 6104 void aarch64_sync_32_to_64(CPUARMState *env) 6105 { 6106 int i; 6107 uint32_t mode = env->uncached_cpsr & CPSR_M; 6108 6109 /* We can blanket copy R[0:7] to X[0:7] */ 6110 for (i = 0; i < 8; i++) { 6111 env->xregs[i] = env->regs[i]; 6112 } 6113 6114 /* Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12. 6115 * Otherwise, they come from the banked user regs. 6116 */ 6117 if (mode == ARM_CPU_MODE_FIQ) { 6118 for (i = 8; i < 13; i++) { 6119 env->xregs[i] = env->usr_regs[i - 8]; 6120 } 6121 } else { 6122 for (i = 8; i < 13; i++) { 6123 env->xregs[i] = env->regs[i]; 6124 } 6125 } 6126 6127 /* Registers x13-x23 are the various mode SP and FP registers. Registers 6128 * r13 and r14 are only copied if we are in that mode, otherwise we copy 6129 * from the mode banked register. 6130 */ 6131 if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) { 6132 env->xregs[13] = env->regs[13]; 6133 env->xregs[14] = env->regs[14]; 6134 } else { 6135 env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)]; 6136 /* HYP is an exception in that it is copied from r14 */ 6137 if (mode == ARM_CPU_MODE_HYP) { 6138 env->xregs[14] = env->regs[14]; 6139 } else { 6140 env->xregs[14] = env->banked_r14[bank_number(ARM_CPU_MODE_USR)]; 6141 } 6142 } 6143 6144 if (mode == ARM_CPU_MODE_HYP) { 6145 env->xregs[15] = env->regs[13]; 6146 } else { 6147 env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)]; 6148 } 6149 6150 if (mode == ARM_CPU_MODE_IRQ) { 6151 env->xregs[16] = env->regs[14]; 6152 env->xregs[17] = env->regs[13]; 6153 } else { 6154 env->xregs[16] = env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)]; 6155 env->xregs[17] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)]; 6156 } 6157 6158 if (mode == ARM_CPU_MODE_SVC) { 6159 env->xregs[18] = env->regs[14]; 6160 env->xregs[19] = env->regs[13]; 6161 } else { 6162 env->xregs[18] = env->banked_r14[bank_number(ARM_CPU_MODE_SVC)]; 6163 env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)]; 6164 } 6165 6166 if (mode == ARM_CPU_MODE_ABT) { 6167 env->xregs[20] = env->regs[14]; 6168 env->xregs[21] = env->regs[13]; 6169 } else { 6170 env->xregs[20] = env->banked_r14[bank_number(ARM_CPU_MODE_ABT)]; 6171 env->xregs[21] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)]; 6172 } 6173 6174 if (mode == ARM_CPU_MODE_UND) { 6175 env->xregs[22] = env->regs[14]; 6176 env->xregs[23] = env->regs[13]; 6177 } else { 6178 env->xregs[22] = env->banked_r14[bank_number(ARM_CPU_MODE_UND)]; 6179 env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)]; 6180 } 6181 6182 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ 6183 * mode, then we can copy from r8-r14. Otherwise, we copy from the 6184 * FIQ bank for r8-r14. 6185 */ 6186 if (mode == ARM_CPU_MODE_FIQ) { 6187 for (i = 24; i < 31; i++) { 6188 env->xregs[i] = env->regs[i - 16]; /* X[24:30] <- R[8:14] */ 6189 } 6190 } else { 6191 for (i = 24; i < 29; i++) { 6192 env->xregs[i] = env->fiq_regs[i - 24]; 6193 } 6194 env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)]; 6195 env->xregs[30] = env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)]; 6196 } 6197 6198 env->pc = env->regs[15]; 6199 } 6200 6201 /* Function used to synchronize QEMU's AArch32 register set with AArch64 6202 * register set. This is necessary when switching between AArch32 and AArch64 6203 * execution state. 6204 */ 6205 void aarch64_sync_64_to_32(CPUARMState *env) 6206 { 6207 int i; 6208 uint32_t mode = env->uncached_cpsr & CPSR_M; 6209 6210 /* We can blanket copy X[0:7] to R[0:7] */ 6211 for (i = 0; i < 8; i++) { 6212 env->regs[i] = env->xregs[i]; 6213 } 6214 6215 /* Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12. 6216 * Otherwise, we copy x8-x12 into the banked user regs. 6217 */ 6218 if (mode == ARM_CPU_MODE_FIQ) { 6219 for (i = 8; i < 13; i++) { 6220 env->usr_regs[i - 8] = env->xregs[i]; 6221 } 6222 } else { 6223 for (i = 8; i < 13; i++) { 6224 env->regs[i] = env->xregs[i]; 6225 } 6226 } 6227 6228 /* Registers r13 & r14 depend on the current mode. 6229 * If we are in a given mode, we copy the corresponding x registers to r13 6230 * and r14. Otherwise, we copy the x register to the banked r13 and r14 6231 * for the mode. 6232 */ 6233 if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) { 6234 env->regs[13] = env->xregs[13]; 6235 env->regs[14] = env->xregs[14]; 6236 } else { 6237 env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13]; 6238 6239 /* HYP is an exception in that it does not have its own banked r14 but 6240 * shares the USR r14 6241 */ 6242 if (mode == ARM_CPU_MODE_HYP) { 6243 env->regs[14] = env->xregs[14]; 6244 } else { 6245 env->banked_r14[bank_number(ARM_CPU_MODE_USR)] = env->xregs[14]; 6246 } 6247 } 6248 6249 if (mode == ARM_CPU_MODE_HYP) { 6250 env->regs[13] = env->xregs[15]; 6251 } else { 6252 env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15]; 6253 } 6254 6255 if (mode == ARM_CPU_MODE_IRQ) { 6256 env->regs[14] = env->xregs[16]; 6257 env->regs[13] = env->xregs[17]; 6258 } else { 6259 env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16]; 6260 env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17]; 6261 } 6262 6263 if (mode == ARM_CPU_MODE_SVC) { 6264 env->regs[14] = env->xregs[18]; 6265 env->regs[13] = env->xregs[19]; 6266 } else { 6267 env->banked_r14[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18]; 6268 env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19]; 6269 } 6270 6271 if (mode == ARM_CPU_MODE_ABT) { 6272 env->regs[14] = env->xregs[20]; 6273 env->regs[13] = env->xregs[21]; 6274 } else { 6275 env->banked_r14[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20]; 6276 env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21]; 6277 } 6278 6279 if (mode == ARM_CPU_MODE_UND) { 6280 env->regs[14] = env->xregs[22]; 6281 env->regs[13] = env->xregs[23]; 6282 } else { 6283 env->banked_r14[bank_number(ARM_CPU_MODE_UND)] = env->xregs[22]; 6284 env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23]; 6285 } 6286 6287 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ 6288 * mode, then we can copy to r8-r14. Otherwise, we copy to the 6289 * FIQ bank for r8-r14. 6290 */ 6291 if (mode == ARM_CPU_MODE_FIQ) { 6292 for (i = 24; i < 31; i++) { 6293 env->regs[i - 16] = env->xregs[i]; /* X[24:30] -> R[8:14] */ 6294 } 6295 } else { 6296 for (i = 24; i < 29; i++) { 6297 env->fiq_regs[i - 24] = env->xregs[i]; 6298 } 6299 env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29]; 6300 env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30]; 6301 } 6302 6303 env->regs[15] = env->pc; 6304 } 6305 6306 static void arm_cpu_do_interrupt_aarch32(CPUState *cs) 6307 { 6308 ARMCPU *cpu = ARM_CPU(cs); 6309 CPUARMState *env = &cpu->env; 6310 uint32_t addr; 6311 uint32_t mask; 6312 int new_mode; 6313 uint32_t offset; 6314 uint32_t moe; 6315 6316 /* If this is a debug exception we must update the DBGDSCR.MOE bits */ 6317 switch (env->exception.syndrome >> ARM_EL_EC_SHIFT) { 6318 case EC_BREAKPOINT: 6319 case EC_BREAKPOINT_SAME_EL: 6320 moe = 1; 6321 break; 6322 case EC_WATCHPOINT: 6323 case EC_WATCHPOINT_SAME_EL: 6324 moe = 10; 6325 break; 6326 case EC_AA32_BKPT: 6327 moe = 3; 6328 break; 6329 case EC_VECTORCATCH: 6330 moe = 5; 6331 break; 6332 default: 6333 moe = 0; 6334 break; 6335 } 6336 6337 if (moe) { 6338 env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe); 6339 } 6340 6341 /* TODO: Vectored interrupt controller. */ 6342 switch (cs->exception_index) { 6343 case EXCP_UDEF: 6344 new_mode = ARM_CPU_MODE_UND; 6345 addr = 0x04; 6346 mask = CPSR_I; 6347 if (env->thumb) 6348 offset = 2; 6349 else 6350 offset = 4; 6351 break; 6352 case EXCP_SWI: 6353 new_mode = ARM_CPU_MODE_SVC; 6354 addr = 0x08; 6355 mask = CPSR_I; 6356 /* The PC already points to the next instruction. */ 6357 offset = 0; 6358 break; 6359 case EXCP_BKPT: 6360 env->exception.fsr = 2; 6361 /* Fall through to prefetch abort. */ 6362 case EXCP_PREFETCH_ABORT: 6363 A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr); 6364 A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress); 6365 qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n", 6366 env->exception.fsr, (uint32_t)env->exception.vaddress); 6367 new_mode = ARM_CPU_MODE_ABT; 6368 addr = 0x0c; 6369 mask = CPSR_A | CPSR_I; 6370 offset = 4; 6371 break; 6372 case EXCP_DATA_ABORT: 6373 A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); 6374 A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress); 6375 qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n", 6376 env->exception.fsr, 6377 (uint32_t)env->exception.vaddress); 6378 new_mode = ARM_CPU_MODE_ABT; 6379 addr = 0x10; 6380 mask = CPSR_A | CPSR_I; 6381 offset = 8; 6382 break; 6383 case EXCP_IRQ: 6384 new_mode = ARM_CPU_MODE_IRQ; 6385 addr = 0x18; 6386 /* Disable IRQ and imprecise data aborts. */ 6387 mask = CPSR_A | CPSR_I; 6388 offset = 4; 6389 if (env->cp15.scr_el3 & SCR_IRQ) { 6390 /* IRQ routed to monitor mode */ 6391 new_mode = ARM_CPU_MODE_MON; 6392 mask |= CPSR_F; 6393 } 6394 break; 6395 case EXCP_FIQ: 6396 new_mode = ARM_CPU_MODE_FIQ; 6397 addr = 0x1c; 6398 /* Disable FIQ, IRQ and imprecise data aborts. */ 6399 mask = CPSR_A | CPSR_I | CPSR_F; 6400 if (env->cp15.scr_el3 & SCR_FIQ) { 6401 /* FIQ routed to monitor mode */ 6402 new_mode = ARM_CPU_MODE_MON; 6403 } 6404 offset = 4; 6405 break; 6406 case EXCP_SMC: 6407 new_mode = ARM_CPU_MODE_MON; 6408 addr = 0x08; 6409 mask = CPSR_A | CPSR_I | CPSR_F; 6410 offset = 0; 6411 break; 6412 default: 6413 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); 6414 return; /* Never happens. Keep compiler happy. */ 6415 } 6416 6417 if (new_mode == ARM_CPU_MODE_MON) { 6418 addr += env->cp15.mvbar; 6419 } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 6420 /* High vectors. When enabled, base address cannot be remapped. */ 6421 addr += 0xffff0000; 6422 } else { 6423 /* ARM v7 architectures provide a vector base address register to remap 6424 * the interrupt vector table. 6425 * This register is only followed in non-monitor mode, and is banked. 6426 * Note: only bits 31:5 are valid. 6427 */ 6428 addr += A32_BANKED_CURRENT_REG_GET(env, vbar); 6429 } 6430 6431 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 6432 env->cp15.scr_el3 &= ~SCR_NS; 6433 } 6434 6435 switch_mode (env, new_mode); 6436 /* For exceptions taken to AArch32 we must clear the SS bit in both 6437 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now. 6438 */ 6439 env->uncached_cpsr &= ~PSTATE_SS; 6440 env->spsr = cpsr_read(env); 6441 /* Clear IT bits. */ 6442 env->condexec_bits = 0; 6443 /* Switch to the new mode, and to the correct instruction set. */ 6444 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; 6445 /* Set new mode endianness */ 6446 env->uncached_cpsr &= ~CPSR_E; 6447 if (env->cp15.sctlr_el[arm_current_el(env)] & SCTLR_EE) { 6448 env->uncached_cpsr |= CPSR_E; 6449 } 6450 env->daif |= mask; 6451 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares 6452 * and we should just guard the thumb mode on V4 */ 6453 if (arm_feature(env, ARM_FEATURE_V4T)) { 6454 env->thumb = (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0; 6455 } 6456 env->regs[14] = env->regs[15] + offset; 6457 env->regs[15] = addr; 6458 } 6459 6460 /* Handle exception entry to a target EL which is using AArch64 */ 6461 static void arm_cpu_do_interrupt_aarch64(CPUState *cs) 6462 { 6463 ARMCPU *cpu = ARM_CPU(cs); 6464 CPUARMState *env = &cpu->env; 6465 unsigned int new_el = env->exception.target_el; 6466 target_ulong addr = env->cp15.vbar_el[new_el]; 6467 unsigned int new_mode = aarch64_pstate_mode(new_el, true); 6468 6469 if (arm_current_el(env) < new_el) { 6470 /* Entry vector offset depends on whether the implemented EL 6471 * immediately lower than the target level is using AArch32 or AArch64 6472 */ 6473 bool is_aa64; 6474 6475 switch (new_el) { 6476 case 3: 6477 is_aa64 = (env->cp15.scr_el3 & SCR_RW) != 0; 6478 break; 6479 case 2: 6480 is_aa64 = (env->cp15.hcr_el2 & HCR_RW) != 0; 6481 break; 6482 case 1: 6483 is_aa64 = is_a64(env); 6484 break; 6485 default: 6486 g_assert_not_reached(); 6487 } 6488 6489 if (is_aa64) { 6490 addr += 0x400; 6491 } else { 6492 addr += 0x600; 6493 } 6494 } else if (pstate_read(env) & PSTATE_SP) { 6495 addr += 0x200; 6496 } 6497 6498 switch (cs->exception_index) { 6499 case EXCP_PREFETCH_ABORT: 6500 case EXCP_DATA_ABORT: 6501 env->cp15.far_el[new_el] = env->exception.vaddress; 6502 qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n", 6503 env->cp15.far_el[new_el]); 6504 /* fall through */ 6505 case EXCP_BKPT: 6506 case EXCP_UDEF: 6507 case EXCP_SWI: 6508 case EXCP_HVC: 6509 case EXCP_HYP_TRAP: 6510 case EXCP_SMC: 6511 env->cp15.esr_el[new_el] = env->exception.syndrome; 6512 break; 6513 case EXCP_IRQ: 6514 case EXCP_VIRQ: 6515 addr += 0x80; 6516 break; 6517 case EXCP_FIQ: 6518 case EXCP_VFIQ: 6519 addr += 0x100; 6520 break; 6521 case EXCP_SEMIHOST: 6522 qemu_log_mask(CPU_LOG_INT, 6523 "...handling as semihosting call 0x%" PRIx64 "\n", 6524 env->xregs[0]); 6525 env->xregs[0] = do_arm_semihosting(env); 6526 return; 6527 default: 6528 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); 6529 } 6530 6531 if (is_a64(env)) { 6532 env->banked_spsr[aarch64_banked_spsr_index(new_el)] = pstate_read(env); 6533 aarch64_save_sp(env, arm_current_el(env)); 6534 env->elr_el[new_el] = env->pc; 6535 } else { 6536 env->banked_spsr[aarch64_banked_spsr_index(new_el)] = cpsr_read(env); 6537 env->elr_el[new_el] = env->regs[15]; 6538 6539 aarch64_sync_32_to_64(env); 6540 6541 env->condexec_bits = 0; 6542 } 6543 qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n", 6544 env->elr_el[new_el]); 6545 6546 pstate_write(env, PSTATE_DAIF | new_mode); 6547 env->aarch64 = 1; 6548 aarch64_restore_sp(env, new_el); 6549 6550 env->pc = addr; 6551 6552 qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 " PSTATE 0x%x\n", 6553 new_el, env->pc, pstate_read(env)); 6554 } 6555 6556 static inline bool check_for_semihosting(CPUState *cs) 6557 { 6558 /* Check whether this exception is a semihosting call; if so 6559 * then handle it and return true; otherwise return false. 6560 */ 6561 ARMCPU *cpu = ARM_CPU(cs); 6562 CPUARMState *env = &cpu->env; 6563 6564 if (is_a64(env)) { 6565 if (cs->exception_index == EXCP_SEMIHOST) { 6566 /* This is always the 64-bit semihosting exception. 6567 * The "is this usermode" and "is semihosting enabled" 6568 * checks have been done at translate time. 6569 */ 6570 qemu_log_mask(CPU_LOG_INT, 6571 "...handling as semihosting call 0x%" PRIx64 "\n", 6572 env->xregs[0]); 6573 env->xregs[0] = do_arm_semihosting(env); 6574 return true; 6575 } 6576 return false; 6577 } else { 6578 uint32_t imm; 6579 6580 /* Only intercept calls from privileged modes, to provide some 6581 * semblance of security. 6582 */ 6583 if (cs->exception_index != EXCP_SEMIHOST && 6584 (!semihosting_enabled() || 6585 ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR))) { 6586 return false; 6587 } 6588 6589 switch (cs->exception_index) { 6590 case EXCP_SEMIHOST: 6591 /* This is always a semihosting call; the "is this usermode" 6592 * and "is semihosting enabled" checks have been done at 6593 * translate time. 6594 */ 6595 break; 6596 case EXCP_SWI: 6597 /* Check for semihosting interrupt. */ 6598 if (env->thumb) { 6599 imm = arm_lduw_code(env, env->regs[15] - 2, arm_sctlr_b(env)) 6600 & 0xff; 6601 if (imm == 0xab) { 6602 break; 6603 } 6604 } else { 6605 imm = arm_ldl_code(env, env->regs[15] - 4, arm_sctlr_b(env)) 6606 & 0xffffff; 6607 if (imm == 0x123456) { 6608 break; 6609 } 6610 } 6611 return false; 6612 case EXCP_BKPT: 6613 /* See if this is a semihosting syscall. */ 6614 if (env->thumb) { 6615 imm = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env)) 6616 & 0xff; 6617 if (imm == 0xab) { 6618 env->regs[15] += 2; 6619 break; 6620 } 6621 } 6622 return false; 6623 default: 6624 return false; 6625 } 6626 6627 qemu_log_mask(CPU_LOG_INT, 6628 "...handling as semihosting call 0x%x\n", 6629 env->regs[0]); 6630 env->regs[0] = do_arm_semihosting(env); 6631 return true; 6632 } 6633 } 6634 6635 /* Handle a CPU exception for A and R profile CPUs. 6636 * Do any appropriate logging, handle PSCI calls, and then hand off 6637 * to the AArch64-entry or AArch32-entry function depending on the 6638 * target exception level's register width. 6639 */ 6640 void arm_cpu_do_interrupt(CPUState *cs) 6641 { 6642 ARMCPU *cpu = ARM_CPU(cs); 6643 CPUARMState *env = &cpu->env; 6644 unsigned int new_el = env->exception.target_el; 6645 6646 assert(!IS_M(env)); 6647 6648 arm_log_exception(cs->exception_index); 6649 qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(env), 6650 new_el); 6651 if (qemu_loglevel_mask(CPU_LOG_INT) 6652 && !excp_is_internal(cs->exception_index)) { 6653 qemu_log_mask(CPU_LOG_INT, "...with ESR %x/0x%" PRIx32 "\n", 6654 env->exception.syndrome >> ARM_EL_EC_SHIFT, 6655 env->exception.syndrome); 6656 } 6657 6658 if (arm_is_psci_call(cpu, cs->exception_index)) { 6659 arm_handle_psci_call(cpu); 6660 qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); 6661 return; 6662 } 6663 6664 /* Semihosting semantics depend on the register width of the 6665 * code that caused the exception, not the target exception level, 6666 * so must be handled here. 6667 */ 6668 if (check_for_semihosting(cs)) { 6669 return; 6670 } 6671 6672 assert(!excp_is_internal(cs->exception_index)); 6673 if (arm_el_is_aa64(env, new_el)) { 6674 arm_cpu_do_interrupt_aarch64(cs); 6675 } else { 6676 arm_cpu_do_interrupt_aarch32(cs); 6677 } 6678 6679 arm_call_el_change_hook(cpu); 6680 6681 if (!kvm_enabled()) { 6682 cs->interrupt_request |= CPU_INTERRUPT_EXITTB; 6683 } 6684 } 6685 6686 /* Return the exception level which controls this address translation regime */ 6687 static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) 6688 { 6689 switch (mmu_idx) { 6690 case ARMMMUIdx_S2NS: 6691 case ARMMMUIdx_S1E2: 6692 return 2; 6693 case ARMMMUIdx_S1E3: 6694 return 3; 6695 case ARMMMUIdx_S1SE0: 6696 return arm_el_is_aa64(env, 3) ? 1 : 3; 6697 case ARMMMUIdx_S1SE1: 6698 case ARMMMUIdx_S1NSE0: 6699 case ARMMMUIdx_S1NSE1: 6700 return 1; 6701 default: 6702 g_assert_not_reached(); 6703 } 6704 } 6705 6706 /* Return true if this address translation regime is secure */ 6707 static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) 6708 { 6709 switch (mmu_idx) { 6710 case ARMMMUIdx_S12NSE0: 6711 case ARMMMUIdx_S12NSE1: 6712 case ARMMMUIdx_S1NSE0: 6713 case ARMMMUIdx_S1NSE1: 6714 case ARMMMUIdx_S1E2: 6715 case ARMMMUIdx_S2NS: 6716 return false; 6717 case ARMMMUIdx_S1E3: 6718 case ARMMMUIdx_S1SE0: 6719 case ARMMMUIdx_S1SE1: 6720 return true; 6721 default: 6722 g_assert_not_reached(); 6723 } 6724 } 6725 6726 /* Return the SCTLR value which controls this address translation regime */ 6727 static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) 6728 { 6729 return env->cp15.sctlr_el[regime_el(env, mmu_idx)]; 6730 } 6731 6732 /* Return true if the specified stage of address translation is disabled */ 6733 static inline bool regime_translation_disabled(CPUARMState *env, 6734 ARMMMUIdx mmu_idx) 6735 { 6736 if (mmu_idx == ARMMMUIdx_S2NS) { 6737 return (env->cp15.hcr_el2 & HCR_VM) == 0; 6738 } 6739 return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0; 6740 } 6741 6742 static inline bool regime_translation_big_endian(CPUARMState *env, 6743 ARMMMUIdx mmu_idx) 6744 { 6745 return (regime_sctlr(env, mmu_idx) & SCTLR_EE) != 0; 6746 } 6747 6748 /* Return the TCR controlling this translation regime */ 6749 static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) 6750 { 6751 if (mmu_idx == ARMMMUIdx_S2NS) { 6752 return &env->cp15.vtcr_el2; 6753 } 6754 return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; 6755 } 6756 6757 /* Returns TBI0 value for current regime el */ 6758 uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx) 6759 { 6760 TCR *tcr; 6761 uint32_t el; 6762 6763 /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert 6764 * a stage 1+2 mmu index into the appropriate stage 1 mmu index. 6765 */ 6766 if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { 6767 mmu_idx += ARMMMUIdx_S1NSE0; 6768 } 6769 6770 tcr = regime_tcr(env, mmu_idx); 6771 el = regime_el(env, mmu_idx); 6772 6773 if (el > 1) { 6774 return extract64(tcr->raw_tcr, 20, 1); 6775 } else { 6776 return extract64(tcr->raw_tcr, 37, 1); 6777 } 6778 } 6779 6780 /* Returns TBI1 value for current regime el */ 6781 uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx) 6782 { 6783 TCR *tcr; 6784 uint32_t el; 6785 6786 /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert 6787 * a stage 1+2 mmu index into the appropriate stage 1 mmu index. 6788 */ 6789 if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { 6790 mmu_idx += ARMMMUIdx_S1NSE0; 6791 } 6792 6793 tcr = regime_tcr(env, mmu_idx); 6794 el = regime_el(env, mmu_idx); 6795 6796 if (el > 1) { 6797 return 0; 6798 } else { 6799 return extract64(tcr->raw_tcr, 38, 1); 6800 } 6801 } 6802 6803 /* Return the TTBR associated with this translation regime */ 6804 static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, 6805 int ttbrn) 6806 { 6807 if (mmu_idx == ARMMMUIdx_S2NS) { 6808 return env->cp15.vttbr_el2; 6809 } 6810 if (ttbrn == 0) { 6811 return env->cp15.ttbr0_el[regime_el(env, mmu_idx)]; 6812 } else { 6813 return env->cp15.ttbr1_el[regime_el(env, mmu_idx)]; 6814 } 6815 } 6816 6817 /* Return true if the translation regime is using LPAE format page tables */ 6818 static inline bool regime_using_lpae_format(CPUARMState *env, 6819 ARMMMUIdx mmu_idx) 6820 { 6821 int el = regime_el(env, mmu_idx); 6822 if (el == 2 || arm_el_is_aa64(env, el)) { 6823 return true; 6824 } 6825 if (arm_feature(env, ARM_FEATURE_LPAE) 6826 && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) { 6827 return true; 6828 } 6829 return false; 6830 } 6831 6832 /* Returns true if the stage 1 translation regime is using LPAE format page 6833 * tables. Used when raising alignment exceptions, whose FSR changes depending 6834 * on whether the long or short descriptor format is in use. */ 6835 bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) 6836 { 6837 if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { 6838 mmu_idx += ARMMMUIdx_S1NSE0; 6839 } 6840 6841 return regime_using_lpae_format(env, mmu_idx); 6842 } 6843 6844 static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) 6845 { 6846 switch (mmu_idx) { 6847 case ARMMMUIdx_S1SE0: 6848 case ARMMMUIdx_S1NSE0: 6849 return true; 6850 default: 6851 return false; 6852 case ARMMMUIdx_S12NSE0: 6853 case ARMMMUIdx_S12NSE1: 6854 g_assert_not_reached(); 6855 } 6856 } 6857 6858 /* Translate section/page access permissions to page 6859 * R/W protection flags 6860 * 6861 * @env: CPUARMState 6862 * @mmu_idx: MMU index indicating required translation regime 6863 * @ap: The 3-bit access permissions (AP[2:0]) 6864 * @domain_prot: The 2-bit domain access permissions 6865 */ 6866 static inline int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, 6867 int ap, int domain_prot) 6868 { 6869 bool is_user = regime_is_user(env, mmu_idx); 6870 6871 if (domain_prot == 3) { 6872 return PAGE_READ | PAGE_WRITE; 6873 } 6874 6875 switch (ap) { 6876 case 0: 6877 if (arm_feature(env, ARM_FEATURE_V7)) { 6878 return 0; 6879 } 6880 switch (regime_sctlr(env, mmu_idx) & (SCTLR_S | SCTLR_R)) { 6881 case SCTLR_S: 6882 return is_user ? 0 : PAGE_READ; 6883 case SCTLR_R: 6884 return PAGE_READ; 6885 default: 6886 return 0; 6887 } 6888 case 1: 6889 return is_user ? 0 : PAGE_READ | PAGE_WRITE; 6890 case 2: 6891 if (is_user) { 6892 return PAGE_READ; 6893 } else { 6894 return PAGE_READ | PAGE_WRITE; 6895 } 6896 case 3: 6897 return PAGE_READ | PAGE_WRITE; 6898 case 4: /* Reserved. */ 6899 return 0; 6900 case 5: 6901 return is_user ? 0 : PAGE_READ; 6902 case 6: 6903 return PAGE_READ; 6904 case 7: 6905 if (!arm_feature(env, ARM_FEATURE_V6K)) { 6906 return 0; 6907 } 6908 return PAGE_READ; 6909 default: 6910 g_assert_not_reached(); 6911 } 6912 } 6913 6914 /* Translate section/page access permissions to page 6915 * R/W protection flags. 6916 * 6917 * @ap: The 2-bit simple AP (AP[2:1]) 6918 * @is_user: TRUE if accessing from PL0 6919 */ 6920 static inline int simple_ap_to_rw_prot_is_user(int ap, bool is_user) 6921 { 6922 switch (ap) { 6923 case 0: 6924 return is_user ? 0 : PAGE_READ | PAGE_WRITE; 6925 case 1: 6926 return PAGE_READ | PAGE_WRITE; 6927 case 2: 6928 return is_user ? 0 : PAGE_READ; 6929 case 3: 6930 return PAGE_READ; 6931 default: 6932 g_assert_not_reached(); 6933 } 6934 } 6935 6936 static inline int 6937 simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap) 6938 { 6939 return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx)); 6940 } 6941 6942 /* Translate S2 section/page access permissions to protection flags 6943 * 6944 * @env: CPUARMState 6945 * @s2ap: The 2-bit stage2 access permissions (S2AP) 6946 * @xn: XN (execute-never) bit 6947 */ 6948 static int get_S2prot(CPUARMState *env, int s2ap, int xn) 6949 { 6950 int prot = 0; 6951 6952 if (s2ap & 1) { 6953 prot |= PAGE_READ; 6954 } 6955 if (s2ap & 2) { 6956 prot |= PAGE_WRITE; 6957 } 6958 if (!xn) { 6959 if (arm_el_is_aa64(env, 2) || prot & PAGE_READ) { 6960 prot |= PAGE_EXEC; 6961 } 6962 } 6963 return prot; 6964 } 6965 6966 /* Translate section/page access permissions to protection flags 6967 * 6968 * @env: CPUARMState 6969 * @mmu_idx: MMU index indicating required translation regime 6970 * @is_aa64: TRUE if AArch64 6971 * @ap: The 2-bit simple AP (AP[2:1]) 6972 * @ns: NS (non-secure) bit 6973 * @xn: XN (execute-never) bit 6974 * @pxn: PXN (privileged execute-never) bit 6975 */ 6976 static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, 6977 int ap, int ns, int xn, int pxn) 6978 { 6979 bool is_user = regime_is_user(env, mmu_idx); 6980 int prot_rw, user_rw; 6981 bool have_wxn; 6982 int wxn = 0; 6983 6984 assert(mmu_idx != ARMMMUIdx_S2NS); 6985 6986 user_rw = simple_ap_to_rw_prot_is_user(ap, true); 6987 if (is_user) { 6988 prot_rw = user_rw; 6989 } else { 6990 prot_rw = simple_ap_to_rw_prot_is_user(ap, false); 6991 } 6992 6993 if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) { 6994 return prot_rw; 6995 } 6996 6997 /* TODO have_wxn should be replaced with 6998 * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2) 6999 * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE 7000 * compatible processors have EL2, which is required for [U]WXN. 7001 */ 7002 have_wxn = arm_feature(env, ARM_FEATURE_LPAE); 7003 7004 if (have_wxn) { 7005 wxn = regime_sctlr(env, mmu_idx) & SCTLR_WXN; 7006 } 7007 7008 if (is_aa64) { 7009 switch (regime_el(env, mmu_idx)) { 7010 case 1: 7011 if (!is_user) { 7012 xn = pxn || (user_rw & PAGE_WRITE); 7013 } 7014 break; 7015 case 2: 7016 case 3: 7017 break; 7018 } 7019 } else if (arm_feature(env, ARM_FEATURE_V7)) { 7020 switch (regime_el(env, mmu_idx)) { 7021 case 1: 7022 case 3: 7023 if (is_user) { 7024 xn = xn || !(user_rw & PAGE_READ); 7025 } else { 7026 int uwxn = 0; 7027 if (have_wxn) { 7028 uwxn = regime_sctlr(env, mmu_idx) & SCTLR_UWXN; 7029 } 7030 xn = xn || !(prot_rw & PAGE_READ) || pxn || 7031 (uwxn && (user_rw & PAGE_WRITE)); 7032 } 7033 break; 7034 case 2: 7035 break; 7036 } 7037 } else { 7038 xn = wxn = 0; 7039 } 7040 7041 if (xn || (wxn && (prot_rw & PAGE_WRITE))) { 7042 return prot_rw; 7043 } 7044 return prot_rw | PAGE_EXEC; 7045 } 7046 7047 static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, 7048 uint32_t *table, uint32_t address) 7049 { 7050 /* Note that we can only get here for an AArch32 PL0/PL1 lookup */ 7051 TCR *tcr = regime_tcr(env, mmu_idx); 7052 7053 if (address & tcr->mask) { 7054 if (tcr->raw_tcr & TTBCR_PD1) { 7055 /* Translation table walk disabled for TTBR1 */ 7056 return false; 7057 } 7058 *table = regime_ttbr(env, mmu_idx, 1) & 0xffffc000; 7059 } else { 7060 if (tcr->raw_tcr & TTBCR_PD0) { 7061 /* Translation table walk disabled for TTBR0 */ 7062 return false; 7063 } 7064 *table = regime_ttbr(env, mmu_idx, 0) & tcr->base_mask; 7065 } 7066 *table |= (address >> 18) & 0x3ffc; 7067 return true; 7068 } 7069 7070 /* Translate a S1 pagetable walk through S2 if needed. */ 7071 static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, 7072 hwaddr addr, MemTxAttrs txattrs, 7073 uint32_t *fsr, 7074 ARMMMUFaultInfo *fi) 7075 { 7076 if ((mmu_idx == ARMMMUIdx_S1NSE0 || mmu_idx == ARMMMUIdx_S1NSE1) && 7077 !regime_translation_disabled(env, ARMMMUIdx_S2NS)) { 7078 target_ulong s2size; 7079 hwaddr s2pa; 7080 int s2prot; 7081 int ret; 7082 7083 ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_S2NS, &s2pa, 7084 &txattrs, &s2prot, &s2size, fsr, fi); 7085 if (ret) { 7086 fi->s2addr = addr; 7087 fi->stage2 = true; 7088 fi->s1ptw = true; 7089 return ~0; 7090 } 7091 addr = s2pa; 7092 } 7093 return addr; 7094 } 7095 7096 /* All loads done in the course of a page table walk go through here. 7097 * TODO: rather than ignoring errors from physical memory reads (which 7098 * are external aborts in ARM terminology) we should propagate this 7099 * error out so that we can turn it into a Data Abort if this walk 7100 * was being done for a CPU load/store or an address translation instruction 7101 * (but not if it was for a debug access). 7102 */ 7103 static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure, 7104 ARMMMUIdx mmu_idx, uint32_t *fsr, 7105 ARMMMUFaultInfo *fi) 7106 { 7107 ARMCPU *cpu = ARM_CPU(cs); 7108 CPUARMState *env = &cpu->env; 7109 MemTxAttrs attrs = {}; 7110 AddressSpace *as; 7111 7112 attrs.secure = is_secure; 7113 as = arm_addressspace(cs, attrs); 7114 addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi); 7115 if (fi->s1ptw) { 7116 return 0; 7117 } 7118 if (regime_translation_big_endian(env, mmu_idx)) { 7119 return address_space_ldl_be(as, addr, attrs, NULL); 7120 } else { 7121 return address_space_ldl_le(as, addr, attrs, NULL); 7122 } 7123 } 7124 7125 static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, 7126 ARMMMUIdx mmu_idx, uint32_t *fsr, 7127 ARMMMUFaultInfo *fi) 7128 { 7129 ARMCPU *cpu = ARM_CPU(cs); 7130 CPUARMState *env = &cpu->env; 7131 MemTxAttrs attrs = {}; 7132 AddressSpace *as; 7133 7134 attrs.secure = is_secure; 7135 as = arm_addressspace(cs, attrs); 7136 addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi); 7137 if (fi->s1ptw) { 7138 return 0; 7139 } 7140 if (regime_translation_big_endian(env, mmu_idx)) { 7141 return address_space_ldq_be(as, addr, attrs, NULL); 7142 } else { 7143 return address_space_ldq_le(as, addr, attrs, NULL); 7144 } 7145 } 7146 7147 static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, 7148 int access_type, ARMMMUIdx mmu_idx, 7149 hwaddr *phys_ptr, int *prot, 7150 target_ulong *page_size, uint32_t *fsr, 7151 ARMMMUFaultInfo *fi) 7152 { 7153 CPUState *cs = CPU(arm_env_get_cpu(env)); 7154 int code; 7155 uint32_t table; 7156 uint32_t desc; 7157 int type; 7158 int ap; 7159 int domain = 0; 7160 int domain_prot; 7161 hwaddr phys_addr; 7162 uint32_t dacr; 7163 7164 /* Pagetable walk. */ 7165 /* Lookup l1 descriptor. */ 7166 if (!get_level1_table_address(env, mmu_idx, &table, address)) { 7167 /* Section translation fault if page walk is disabled by PD0 or PD1 */ 7168 code = 5; 7169 goto do_fault; 7170 } 7171 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), 7172 mmu_idx, fsr, fi); 7173 type = (desc & 3); 7174 domain = (desc >> 5) & 0x0f; 7175 if (regime_el(env, mmu_idx) == 1) { 7176 dacr = env->cp15.dacr_ns; 7177 } else { 7178 dacr = env->cp15.dacr_s; 7179 } 7180 domain_prot = (dacr >> (domain * 2)) & 3; 7181 if (type == 0) { 7182 /* Section translation fault. */ 7183 code = 5; 7184 goto do_fault; 7185 } 7186 if (domain_prot == 0 || domain_prot == 2) { 7187 if (type == 2) 7188 code = 9; /* Section domain fault. */ 7189 else 7190 code = 11; /* Page domain fault. */ 7191 goto do_fault; 7192 } 7193 if (type == 2) { 7194 /* 1Mb section. */ 7195 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); 7196 ap = (desc >> 10) & 3; 7197 code = 13; 7198 *page_size = 1024 * 1024; 7199 } else { 7200 /* Lookup l2 entry. */ 7201 if (type == 1) { 7202 /* Coarse pagetable. */ 7203 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); 7204 } else { 7205 /* Fine pagetable. */ 7206 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc); 7207 } 7208 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), 7209 mmu_idx, fsr, fi); 7210 switch (desc & 3) { 7211 case 0: /* Page translation fault. */ 7212 code = 7; 7213 goto do_fault; 7214 case 1: /* 64k page. */ 7215 phys_addr = (desc & 0xffff0000) | (address & 0xffff); 7216 ap = (desc >> (4 + ((address >> 13) & 6))) & 3; 7217 *page_size = 0x10000; 7218 break; 7219 case 2: /* 4k page. */ 7220 phys_addr = (desc & 0xfffff000) | (address & 0xfff); 7221 ap = (desc >> (4 + ((address >> 9) & 6))) & 3; 7222 *page_size = 0x1000; 7223 break; 7224 case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */ 7225 if (type == 1) { 7226 /* ARMv6/XScale extended small page format */ 7227 if (arm_feature(env, ARM_FEATURE_XSCALE) 7228 || arm_feature(env, ARM_FEATURE_V6)) { 7229 phys_addr = (desc & 0xfffff000) | (address & 0xfff); 7230 *page_size = 0x1000; 7231 } else { 7232 /* UNPREDICTABLE in ARMv5; we choose to take a 7233 * page translation fault. 7234 */ 7235 code = 7; 7236 goto do_fault; 7237 } 7238 } else { 7239 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff); 7240 *page_size = 0x400; 7241 } 7242 ap = (desc >> 4) & 3; 7243 break; 7244 default: 7245 /* Never happens, but compiler isn't smart enough to tell. */ 7246 abort(); 7247 } 7248 code = 15; 7249 } 7250 *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot); 7251 *prot |= *prot ? PAGE_EXEC : 0; 7252 if (!(*prot & (1 << access_type))) { 7253 /* Access permission fault. */ 7254 goto do_fault; 7255 } 7256 *phys_ptr = phys_addr; 7257 return false; 7258 do_fault: 7259 *fsr = code | (domain << 4); 7260 return true; 7261 } 7262 7263 static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, 7264 int access_type, ARMMMUIdx mmu_idx, 7265 hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, 7266 target_ulong *page_size, uint32_t *fsr, 7267 ARMMMUFaultInfo *fi) 7268 { 7269 CPUState *cs = CPU(arm_env_get_cpu(env)); 7270 int code; 7271 uint32_t table; 7272 uint32_t desc; 7273 uint32_t xn; 7274 uint32_t pxn = 0; 7275 int type; 7276 int ap; 7277 int domain = 0; 7278 int domain_prot; 7279 hwaddr phys_addr; 7280 uint32_t dacr; 7281 bool ns; 7282 7283 /* Pagetable walk. */ 7284 /* Lookup l1 descriptor. */ 7285 if (!get_level1_table_address(env, mmu_idx, &table, address)) { 7286 /* Section translation fault if page walk is disabled by PD0 or PD1 */ 7287 code = 5; 7288 goto do_fault; 7289 } 7290 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), 7291 mmu_idx, fsr, fi); 7292 type = (desc & 3); 7293 if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) { 7294 /* Section translation fault, or attempt to use the encoding 7295 * which is Reserved on implementations without PXN. 7296 */ 7297 code = 5; 7298 goto do_fault; 7299 } 7300 if ((type == 1) || !(desc & (1 << 18))) { 7301 /* Page or Section. */ 7302 domain = (desc >> 5) & 0x0f; 7303 } 7304 if (regime_el(env, mmu_idx) == 1) { 7305 dacr = env->cp15.dacr_ns; 7306 } else { 7307 dacr = env->cp15.dacr_s; 7308 } 7309 domain_prot = (dacr >> (domain * 2)) & 3; 7310 if (domain_prot == 0 || domain_prot == 2) { 7311 if (type != 1) { 7312 code = 9; /* Section domain fault. */ 7313 } else { 7314 code = 11; /* Page domain fault. */ 7315 } 7316 goto do_fault; 7317 } 7318 if (type != 1) { 7319 if (desc & (1 << 18)) { 7320 /* Supersection. */ 7321 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff); 7322 phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32; 7323 phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36; 7324 *page_size = 0x1000000; 7325 } else { 7326 /* Section. */ 7327 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); 7328 *page_size = 0x100000; 7329 } 7330 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4); 7331 xn = desc & (1 << 4); 7332 pxn = desc & 1; 7333 code = 13; 7334 ns = extract32(desc, 19, 1); 7335 } else { 7336 if (arm_feature(env, ARM_FEATURE_PXN)) { 7337 pxn = (desc >> 2) & 1; 7338 } 7339 ns = extract32(desc, 3, 1); 7340 /* Lookup l2 entry. */ 7341 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); 7342 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), 7343 mmu_idx, fsr, fi); 7344 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4); 7345 switch (desc & 3) { 7346 case 0: /* Page translation fault. */ 7347 code = 7; 7348 goto do_fault; 7349 case 1: /* 64k page. */ 7350 phys_addr = (desc & 0xffff0000) | (address & 0xffff); 7351 xn = desc & (1 << 15); 7352 *page_size = 0x10000; 7353 break; 7354 case 2: case 3: /* 4k page. */ 7355 phys_addr = (desc & 0xfffff000) | (address & 0xfff); 7356 xn = desc & 1; 7357 *page_size = 0x1000; 7358 break; 7359 default: 7360 /* Never happens, but compiler isn't smart enough to tell. */ 7361 abort(); 7362 } 7363 code = 15; 7364 } 7365 if (domain_prot == 3) { 7366 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 7367 } else { 7368 if (pxn && !regime_is_user(env, mmu_idx)) { 7369 xn = 1; 7370 } 7371 if (xn && access_type == 2) 7372 goto do_fault; 7373 7374 if (arm_feature(env, ARM_FEATURE_V6K) && 7375 (regime_sctlr(env, mmu_idx) & SCTLR_AFE)) { 7376 /* The simplified model uses AP[0] as an access control bit. */ 7377 if ((ap & 1) == 0) { 7378 /* Access flag fault. */ 7379 code = (code == 15) ? 6 : 3; 7380 goto do_fault; 7381 } 7382 *prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1); 7383 } else { 7384 *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot); 7385 } 7386 if (*prot && !xn) { 7387 *prot |= PAGE_EXEC; 7388 } 7389 if (!(*prot & (1 << access_type))) { 7390 /* Access permission fault. */ 7391 goto do_fault; 7392 } 7393 } 7394 if (ns) { 7395 /* The NS bit will (as required by the architecture) have no effect if 7396 * the CPU doesn't support TZ or this is a non-secure translation 7397 * regime, because the attribute will already be non-secure. 7398 */ 7399 attrs->secure = false; 7400 } 7401 *phys_ptr = phys_addr; 7402 return false; 7403 do_fault: 7404 *fsr = code | (domain << 4); 7405 return true; 7406 } 7407 7408 /* Fault type for long-descriptor MMU fault reporting; this corresponds 7409 * to bits [5..2] in the STATUS field in long-format DFSR/IFSR. 7410 */ 7411 typedef enum { 7412 translation_fault = 1, 7413 access_fault = 2, 7414 permission_fault = 3, 7415 } MMUFaultType; 7416 7417 /* 7418 * check_s2_mmu_setup 7419 * @cpu: ARMCPU 7420 * @is_aa64: True if the translation regime is in AArch64 state 7421 * @startlevel: Suggested starting level 7422 * @inputsize: Bitsize of IPAs 7423 * @stride: Page-table stride (See the ARM ARM) 7424 * 7425 * Returns true if the suggested S2 translation parameters are OK and 7426 * false otherwise. 7427 */ 7428 static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, 7429 int inputsize, int stride) 7430 { 7431 const int grainsize = stride + 3; 7432 int startsizecheck; 7433 7434 /* Negative levels are never allowed. */ 7435 if (level < 0) { 7436 return false; 7437 } 7438 7439 startsizecheck = inputsize - ((3 - level) * stride + grainsize); 7440 if (startsizecheck < 1 || startsizecheck > stride + 4) { 7441 return false; 7442 } 7443 7444 if (is_aa64) { 7445 CPUARMState *env = &cpu->env; 7446 unsigned int pamax = arm_pamax(cpu); 7447 7448 switch (stride) { 7449 case 13: /* 64KB Pages. */ 7450 if (level == 0 || (level == 1 && pamax <= 42)) { 7451 return false; 7452 } 7453 break; 7454 case 11: /* 16KB Pages. */ 7455 if (level == 0 || (level == 1 && pamax <= 40)) { 7456 return false; 7457 } 7458 break; 7459 case 9: /* 4KB Pages. */ 7460 if (level == 0 && pamax <= 42) { 7461 return false; 7462 } 7463 break; 7464 default: 7465 g_assert_not_reached(); 7466 } 7467 7468 /* Inputsize checks. */ 7469 if (inputsize > pamax && 7470 (arm_el_is_aa64(env, 1) || inputsize > 40)) { 7471 /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */ 7472 return false; 7473 } 7474 } else { 7475 /* AArch32 only supports 4KB pages. Assert on that. */ 7476 assert(stride == 9); 7477 7478 if (level == 0) { 7479 return false; 7480 } 7481 } 7482 return true; 7483 } 7484 7485 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, 7486 int access_type, ARMMMUIdx mmu_idx, 7487 hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, 7488 target_ulong *page_size_ptr, uint32_t *fsr, 7489 ARMMMUFaultInfo *fi) 7490 { 7491 ARMCPU *cpu = arm_env_get_cpu(env); 7492 CPUState *cs = CPU(cpu); 7493 /* Read an LPAE long-descriptor translation table. */ 7494 MMUFaultType fault_type = translation_fault; 7495 uint32_t level; 7496 uint32_t epd = 0; 7497 int32_t t0sz, t1sz; 7498 uint32_t tg; 7499 uint64_t ttbr; 7500 int ttbr_select; 7501 hwaddr descaddr, indexmask, indexmask_grainsize; 7502 uint32_t tableattrs; 7503 target_ulong page_size; 7504 uint32_t attrs; 7505 int32_t stride = 9; 7506 int32_t addrsize; 7507 int inputsize; 7508 int32_t tbi = 0; 7509 TCR *tcr = regime_tcr(env, mmu_idx); 7510 int ap, ns, xn, pxn; 7511 uint32_t el = regime_el(env, mmu_idx); 7512 bool ttbr1_valid = true; 7513 uint64_t descaddrmask; 7514 bool aarch64 = arm_el_is_aa64(env, el); 7515 7516 /* TODO: 7517 * This code does not handle the different format TCR for VTCR_EL2. 7518 * This code also does not support shareability levels. 7519 * Attribute and permission bit handling should also be checked when adding 7520 * support for those page table walks. 7521 */ 7522 if (aarch64) { 7523 level = 0; 7524 addrsize = 64; 7525 if (el > 1) { 7526 if (mmu_idx != ARMMMUIdx_S2NS) { 7527 tbi = extract64(tcr->raw_tcr, 20, 1); 7528 } 7529 } else { 7530 if (extract64(address, 55, 1)) { 7531 tbi = extract64(tcr->raw_tcr, 38, 1); 7532 } else { 7533 tbi = extract64(tcr->raw_tcr, 37, 1); 7534 } 7535 } 7536 tbi *= 8; 7537 7538 /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it 7539 * invalid. 7540 */ 7541 if (el > 1) { 7542 ttbr1_valid = false; 7543 } 7544 } else { 7545 level = 1; 7546 addrsize = 32; 7547 /* There is no TTBR1 for EL2 */ 7548 if (el == 2) { 7549 ttbr1_valid = false; 7550 } 7551 } 7552 7553 /* Determine whether this address is in the region controlled by 7554 * TTBR0 or TTBR1 (or if it is in neither region and should fault). 7555 * This is a Non-secure PL0/1 stage 1 translation, so controlled by 7556 * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32: 7557 */ 7558 if (aarch64) { 7559 /* AArch64 translation. */ 7560 t0sz = extract32(tcr->raw_tcr, 0, 6); 7561 t0sz = MIN(t0sz, 39); 7562 t0sz = MAX(t0sz, 16); 7563 } else if (mmu_idx != ARMMMUIdx_S2NS) { 7564 /* AArch32 stage 1 translation. */ 7565 t0sz = extract32(tcr->raw_tcr, 0, 3); 7566 } else { 7567 /* AArch32 stage 2 translation. */ 7568 bool sext = extract32(tcr->raw_tcr, 4, 1); 7569 bool sign = extract32(tcr->raw_tcr, 3, 1); 7570 /* Address size is 40-bit for a stage 2 translation, 7571 * and t0sz can be negative (from -8 to 7), 7572 * so we need to adjust it to use the TTBR selecting logic below. 7573 */ 7574 addrsize = 40; 7575 t0sz = sextract32(tcr->raw_tcr, 0, 4) + 8; 7576 7577 /* If the sign-extend bit is not the same as t0sz[3], the result 7578 * is unpredictable. Flag this as a guest error. */ 7579 if (sign != sext) { 7580 qemu_log_mask(LOG_GUEST_ERROR, 7581 "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n"); 7582 } 7583 } 7584 t1sz = extract32(tcr->raw_tcr, 16, 6); 7585 if (aarch64) { 7586 t1sz = MIN(t1sz, 39); 7587 t1sz = MAX(t1sz, 16); 7588 } 7589 if (t0sz && !extract64(address, addrsize - t0sz, t0sz - tbi)) { 7590 /* there is a ttbr0 region and we are in it (high bits all zero) */ 7591 ttbr_select = 0; 7592 } else if (ttbr1_valid && t1sz && 7593 !extract64(~address, addrsize - t1sz, t1sz - tbi)) { 7594 /* there is a ttbr1 region and we are in it (high bits all one) */ 7595 ttbr_select = 1; 7596 } else if (!t0sz) { 7597 /* ttbr0 region is "everything not in the ttbr1 region" */ 7598 ttbr_select = 0; 7599 } else if (!t1sz && ttbr1_valid) { 7600 /* ttbr1 region is "everything not in the ttbr0 region" */ 7601 ttbr_select = 1; 7602 } else { 7603 /* in the gap between the two regions, this is a Translation fault */ 7604 fault_type = translation_fault; 7605 goto do_fault; 7606 } 7607 7608 /* Note that QEMU ignores shareability and cacheability attributes, 7609 * so we don't need to do anything with the SH, ORGN, IRGN fields 7610 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the 7611 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently 7612 * implement any ASID-like capability so we can ignore it (instead 7613 * we will always flush the TLB any time the ASID is changed). 7614 */ 7615 if (ttbr_select == 0) { 7616 ttbr = regime_ttbr(env, mmu_idx, 0); 7617 if (el < 2) { 7618 epd = extract32(tcr->raw_tcr, 7, 1); 7619 } 7620 inputsize = addrsize - t0sz; 7621 7622 tg = extract32(tcr->raw_tcr, 14, 2); 7623 if (tg == 1) { /* 64KB pages */ 7624 stride = 13; 7625 } 7626 if (tg == 2) { /* 16KB pages */ 7627 stride = 11; 7628 } 7629 } else { 7630 /* We should only be here if TTBR1 is valid */ 7631 assert(ttbr1_valid); 7632 7633 ttbr = regime_ttbr(env, mmu_idx, 1); 7634 epd = extract32(tcr->raw_tcr, 23, 1); 7635 inputsize = addrsize - t1sz; 7636 7637 tg = extract32(tcr->raw_tcr, 30, 2); 7638 if (tg == 3) { /* 64KB pages */ 7639 stride = 13; 7640 } 7641 if (tg == 1) { /* 16KB pages */ 7642 stride = 11; 7643 } 7644 } 7645 7646 /* Here we should have set up all the parameters for the translation: 7647 * inputsize, ttbr, epd, stride, tbi 7648 */ 7649 7650 if (epd) { 7651 /* Translation table walk disabled => Translation fault on TLB miss 7652 * Note: This is always 0 on 64-bit EL2 and EL3. 7653 */ 7654 goto do_fault; 7655 } 7656 7657 if (mmu_idx != ARMMMUIdx_S2NS) { 7658 /* The starting level depends on the virtual address size (which can 7659 * be up to 48 bits) and the translation granule size. It indicates 7660 * the number of strides (stride bits at a time) needed to 7661 * consume the bits of the input address. In the pseudocode this is: 7662 * level = 4 - RoundUp((inputsize - grainsize) / stride) 7663 * where their 'inputsize' is our 'inputsize', 'grainsize' is 7664 * our 'stride + 3' and 'stride' is our 'stride'. 7665 * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying: 7666 * = 4 - (inputsize - stride - 3 + stride - 1) / stride 7667 * = 4 - (inputsize - 4) / stride; 7668 */ 7669 level = 4 - (inputsize - 4) / stride; 7670 } else { 7671 /* For stage 2 translations the starting level is specified by the 7672 * VTCR_EL2.SL0 field (whose interpretation depends on the page size) 7673 */ 7674 uint32_t sl0 = extract32(tcr->raw_tcr, 6, 2); 7675 uint32_t startlevel; 7676 bool ok; 7677 7678 if (!aarch64 || stride == 9) { 7679 /* AArch32 or 4KB pages */ 7680 startlevel = 2 - sl0; 7681 } else { 7682 /* 16KB or 64KB pages */ 7683 startlevel = 3 - sl0; 7684 } 7685 7686 /* Check that the starting level is valid. */ 7687 ok = check_s2_mmu_setup(cpu, aarch64, startlevel, 7688 inputsize, stride); 7689 if (!ok) { 7690 fault_type = translation_fault; 7691 goto do_fault; 7692 } 7693 level = startlevel; 7694 } 7695 7696 indexmask_grainsize = (1ULL << (stride + 3)) - 1; 7697 indexmask = (1ULL << (inputsize - (stride * (4 - level)))) - 1; 7698 7699 /* Now we can extract the actual base address from the TTBR */ 7700 descaddr = extract64(ttbr, 0, 48); 7701 descaddr &= ~indexmask; 7702 7703 /* The address field in the descriptor goes up to bit 39 for ARMv7 7704 * but up to bit 47 for ARMv8, but we use the descaddrmask 7705 * up to bit 39 for AArch32, because we don't need other bits in that case 7706 * to construct next descriptor address (anyway they should be all zeroes). 7707 */ 7708 descaddrmask = ((1ull << (aarch64 ? 48 : 40)) - 1) & 7709 ~indexmask_grainsize; 7710 7711 /* Secure accesses start with the page table in secure memory and 7712 * can be downgraded to non-secure at any step. Non-secure accesses 7713 * remain non-secure. We implement this by just ORing in the NSTable/NS 7714 * bits at each step. 7715 */ 7716 tableattrs = regime_is_secure(env, mmu_idx) ? 0 : (1 << 4); 7717 for (;;) { 7718 uint64_t descriptor; 7719 bool nstable; 7720 7721 descaddr |= (address >> (stride * (4 - level))) & indexmask; 7722 descaddr &= ~7ULL; 7723 nstable = extract32(tableattrs, 4, 1); 7724 descriptor = arm_ldq_ptw(cs, descaddr, !nstable, mmu_idx, fsr, fi); 7725 if (fi->s1ptw) { 7726 goto do_fault; 7727 } 7728 7729 if (!(descriptor & 1) || 7730 (!(descriptor & 2) && (level == 3))) { 7731 /* Invalid, or the Reserved level 3 encoding */ 7732 goto do_fault; 7733 } 7734 descaddr = descriptor & descaddrmask; 7735 7736 if ((descriptor & 2) && (level < 3)) { 7737 /* Table entry. The top five bits are attributes which may 7738 * propagate down through lower levels of the table (and 7739 * which are all arranged so that 0 means "no effect", so 7740 * we can gather them up by ORing in the bits at each level). 7741 */ 7742 tableattrs |= extract64(descriptor, 59, 5); 7743 level++; 7744 indexmask = indexmask_grainsize; 7745 continue; 7746 } 7747 /* Block entry at level 1 or 2, or page entry at level 3. 7748 * These are basically the same thing, although the number 7749 * of bits we pull in from the vaddr varies. 7750 */ 7751 page_size = (1ULL << ((stride * (4 - level)) + 3)); 7752 descaddr |= (address & (page_size - 1)); 7753 /* Extract attributes from the descriptor */ 7754 attrs = extract64(descriptor, 2, 10) 7755 | (extract64(descriptor, 52, 12) << 10); 7756 7757 if (mmu_idx == ARMMMUIdx_S2NS) { 7758 /* Stage 2 table descriptors do not include any attribute fields */ 7759 break; 7760 } 7761 /* Merge in attributes from table descriptors */ 7762 attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ 7763 attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */ 7764 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1 7765 * means "force PL1 access only", which means forcing AP[1] to 0. 7766 */ 7767 if (extract32(tableattrs, 2, 1)) { 7768 attrs &= ~(1 << 4); 7769 } 7770 attrs |= nstable << 3; /* NS */ 7771 break; 7772 } 7773 /* Here descaddr is the final physical address, and attributes 7774 * are all in attrs. 7775 */ 7776 fault_type = access_fault; 7777 if ((attrs & (1 << 8)) == 0) { 7778 /* Access flag */ 7779 goto do_fault; 7780 } 7781 7782 ap = extract32(attrs, 4, 2); 7783 xn = extract32(attrs, 12, 1); 7784 7785 if (mmu_idx == ARMMMUIdx_S2NS) { 7786 ns = true; 7787 *prot = get_S2prot(env, ap, xn); 7788 } else { 7789 ns = extract32(attrs, 3, 1); 7790 pxn = extract32(attrs, 11, 1); 7791 *prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn); 7792 } 7793 7794 fault_type = permission_fault; 7795 if (!(*prot & (1 << access_type))) { 7796 goto do_fault; 7797 } 7798 7799 if (ns) { 7800 /* The NS bit will (as required by the architecture) have no effect if 7801 * the CPU doesn't support TZ or this is a non-secure translation 7802 * regime, because the attribute will already be non-secure. 7803 */ 7804 txattrs->secure = false; 7805 } 7806 *phys_ptr = descaddr; 7807 *page_size_ptr = page_size; 7808 return false; 7809 7810 do_fault: 7811 /* Long-descriptor format IFSR/DFSR value */ 7812 *fsr = (1 << 9) | (fault_type << 2) | level; 7813 /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */ 7814 fi->stage2 = fi->s1ptw || (mmu_idx == ARMMMUIdx_S2NS); 7815 return true; 7816 } 7817 7818 static inline void get_phys_addr_pmsav7_default(CPUARMState *env, 7819 ARMMMUIdx mmu_idx, 7820 int32_t address, int *prot) 7821 { 7822 *prot = PAGE_READ | PAGE_WRITE; 7823 switch (address) { 7824 case 0xF0000000 ... 0xFFFFFFFF: 7825 if (regime_sctlr(env, mmu_idx) & SCTLR_V) { /* hivecs execing is ok */ 7826 *prot |= PAGE_EXEC; 7827 } 7828 break; 7829 case 0x00000000 ... 0x7FFFFFFF: 7830 *prot |= PAGE_EXEC; 7831 break; 7832 } 7833 7834 } 7835 7836 static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, 7837 int access_type, ARMMMUIdx mmu_idx, 7838 hwaddr *phys_ptr, int *prot, uint32_t *fsr) 7839 { 7840 ARMCPU *cpu = arm_env_get_cpu(env); 7841 int n; 7842 bool is_user = regime_is_user(env, mmu_idx); 7843 7844 *phys_ptr = address; 7845 *prot = 0; 7846 7847 if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */ 7848 get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); 7849 } else { /* MPU enabled */ 7850 for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) { 7851 /* region search */ 7852 uint32_t base = env->pmsav7.drbar[n]; 7853 uint32_t rsize = extract32(env->pmsav7.drsr[n], 1, 5); 7854 uint32_t rmask; 7855 bool srdis = false; 7856 7857 if (!(env->pmsav7.drsr[n] & 0x1)) { 7858 continue; 7859 } 7860 7861 if (!rsize) { 7862 qemu_log_mask(LOG_GUEST_ERROR, "DRSR.Rsize field can not be 0"); 7863 continue; 7864 } 7865 rsize++; 7866 rmask = (1ull << rsize) - 1; 7867 7868 if (base & rmask) { 7869 qemu_log_mask(LOG_GUEST_ERROR, "DRBAR %" PRIx32 " misaligned " 7870 "to DRSR region size, mask = %" PRIx32, 7871 base, rmask); 7872 continue; 7873 } 7874 7875 if (address < base || address > base + rmask) { 7876 continue; 7877 } 7878 7879 /* Region matched */ 7880 7881 if (rsize >= 8) { /* no subregions for regions < 256 bytes */ 7882 int i, snd; 7883 uint32_t srdis_mask; 7884 7885 rsize -= 3; /* sub region size (power of 2) */ 7886 snd = ((address - base) >> rsize) & 0x7; 7887 srdis = extract32(env->pmsav7.drsr[n], snd + 8, 1); 7888 7889 srdis_mask = srdis ? 0x3 : 0x0; 7890 for (i = 2; i <= 8 && rsize < TARGET_PAGE_BITS; i *= 2) { 7891 /* This will check in groups of 2, 4 and then 8, whether 7892 * the subregion bits are consistent. rsize is incremented 7893 * back up to give the region size, considering consistent 7894 * adjacent subregions as one region. Stop testing if rsize 7895 * is already big enough for an entire QEMU page. 7896 */ 7897 int snd_rounded = snd & ~(i - 1); 7898 uint32_t srdis_multi = extract32(env->pmsav7.drsr[n], 7899 snd_rounded + 8, i); 7900 if (srdis_mask ^ srdis_multi) { 7901 break; 7902 } 7903 srdis_mask = (srdis_mask << i) | srdis_mask; 7904 rsize++; 7905 } 7906 } 7907 if (rsize < TARGET_PAGE_BITS) { 7908 qemu_log_mask(LOG_UNIMP, "No support for MPU (sub)region" 7909 "alignment of %" PRIu32 " bits. Minimum is %d\n", 7910 rsize, TARGET_PAGE_BITS); 7911 continue; 7912 } 7913 if (srdis) { 7914 continue; 7915 } 7916 break; 7917 } 7918 7919 if (n == -1) { /* no hits */ 7920 if (cpu->pmsav7_dregion && 7921 (is_user || !(regime_sctlr(env, mmu_idx) & SCTLR_BR))) { 7922 /* background fault */ 7923 *fsr = 0; 7924 return true; 7925 } 7926 get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); 7927 } else { /* a MPU hit! */ 7928 uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3); 7929 7930 if (is_user) { /* User mode AP bit decoding */ 7931 switch (ap) { 7932 case 0: 7933 case 1: 7934 case 5: 7935 break; /* no access */ 7936 case 3: 7937 *prot |= PAGE_WRITE; 7938 /* fall through */ 7939 case 2: 7940 case 6: 7941 *prot |= PAGE_READ | PAGE_EXEC; 7942 break; 7943 default: 7944 qemu_log_mask(LOG_GUEST_ERROR, 7945 "Bad value for AP bits in DRACR %" 7946 PRIx32 "\n", ap); 7947 } 7948 } else { /* Priv. mode AP bits decoding */ 7949 switch (ap) { 7950 case 0: 7951 break; /* no access */ 7952 case 1: 7953 case 2: 7954 case 3: 7955 *prot |= PAGE_WRITE; 7956 /* fall through */ 7957 case 5: 7958 case 6: 7959 *prot |= PAGE_READ | PAGE_EXEC; 7960 break; 7961 default: 7962 qemu_log_mask(LOG_GUEST_ERROR, 7963 "Bad value for AP bits in DRACR %" 7964 PRIx32 "\n", ap); 7965 } 7966 } 7967 7968 /* execute never */ 7969 if (env->pmsav7.dracr[n] & (1 << 12)) { 7970 *prot &= ~PAGE_EXEC; 7971 } 7972 } 7973 } 7974 7975 *fsr = 0x00d; /* Permission fault */ 7976 return !(*prot & (1 << access_type)); 7977 } 7978 7979 static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, 7980 int access_type, ARMMMUIdx mmu_idx, 7981 hwaddr *phys_ptr, int *prot, uint32_t *fsr) 7982 { 7983 int n; 7984 uint32_t mask; 7985 uint32_t base; 7986 bool is_user = regime_is_user(env, mmu_idx); 7987 7988 *phys_ptr = address; 7989 for (n = 7; n >= 0; n--) { 7990 base = env->cp15.c6_region[n]; 7991 if ((base & 1) == 0) { 7992 continue; 7993 } 7994 mask = 1 << ((base >> 1) & 0x1f); 7995 /* Keep this shift separate from the above to avoid an 7996 (undefined) << 32. */ 7997 mask = (mask << 1) - 1; 7998 if (((base ^ address) & ~mask) == 0) { 7999 break; 8000 } 8001 } 8002 if (n < 0) { 8003 *fsr = 2; 8004 return true; 8005 } 8006 8007 if (access_type == 2) { 8008 mask = env->cp15.pmsav5_insn_ap; 8009 } else { 8010 mask = env->cp15.pmsav5_data_ap; 8011 } 8012 mask = (mask >> (n * 4)) & 0xf; 8013 switch (mask) { 8014 case 0: 8015 *fsr = 1; 8016 return true; 8017 case 1: 8018 if (is_user) { 8019 *fsr = 1; 8020 return true; 8021 } 8022 *prot = PAGE_READ | PAGE_WRITE; 8023 break; 8024 case 2: 8025 *prot = PAGE_READ; 8026 if (!is_user) { 8027 *prot |= PAGE_WRITE; 8028 } 8029 break; 8030 case 3: 8031 *prot = PAGE_READ | PAGE_WRITE; 8032 break; 8033 case 5: 8034 if (is_user) { 8035 *fsr = 1; 8036 return true; 8037 } 8038 *prot = PAGE_READ; 8039 break; 8040 case 6: 8041 *prot = PAGE_READ; 8042 break; 8043 default: 8044 /* Bad permission. */ 8045 *fsr = 1; 8046 return true; 8047 } 8048 *prot |= PAGE_EXEC; 8049 return false; 8050 } 8051 8052 /* get_phys_addr - get the physical address for this virtual address 8053 * 8054 * Find the physical address corresponding to the given virtual address, 8055 * by doing a translation table walk on MMU based systems or using the 8056 * MPU state on MPU based systems. 8057 * 8058 * Returns false if the translation was successful. Otherwise, phys_ptr, attrs, 8059 * prot and page_size may not be filled in, and the populated fsr value provides 8060 * information on why the translation aborted, in the format of a 8061 * DFSR/IFSR fault register, with the following caveats: 8062 * * we honour the short vs long DFSR format differences. 8063 * * the WnR bit is never set (the caller must do this). 8064 * * for PSMAv5 based systems we don't bother to return a full FSR format 8065 * value. 8066 * 8067 * @env: CPUARMState 8068 * @address: virtual address to get physical address for 8069 * @access_type: 0 for read, 1 for write, 2 for execute 8070 * @mmu_idx: MMU index indicating required translation regime 8071 * @phys_ptr: set to the physical address corresponding to the virtual address 8072 * @attrs: set to the memory transaction attributes to use 8073 * @prot: set to the permissions for the page containing phys_ptr 8074 * @page_size: set to the size of the page containing phys_ptr 8075 * @fsr: set to the DFSR/IFSR value on failure 8076 */ 8077 static bool get_phys_addr(CPUARMState *env, target_ulong address, 8078 int access_type, ARMMMUIdx mmu_idx, 8079 hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, 8080 target_ulong *page_size, uint32_t *fsr, 8081 ARMMMUFaultInfo *fi) 8082 { 8083 if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { 8084 /* Call ourselves recursively to do the stage 1 and then stage 2 8085 * translations. 8086 */ 8087 if (arm_feature(env, ARM_FEATURE_EL2)) { 8088 hwaddr ipa; 8089 int s2_prot; 8090 int ret; 8091 8092 ret = get_phys_addr(env, address, access_type, 8093 mmu_idx + ARMMMUIdx_S1NSE0, &ipa, attrs, 8094 prot, page_size, fsr, fi); 8095 8096 /* If S1 fails or S2 is disabled, return early. */ 8097 if (ret || regime_translation_disabled(env, ARMMMUIdx_S2NS)) { 8098 *phys_ptr = ipa; 8099 return ret; 8100 } 8101 8102 /* S1 is done. Now do S2 translation. */ 8103 ret = get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_S2NS, 8104 phys_ptr, attrs, &s2_prot, 8105 page_size, fsr, fi); 8106 fi->s2addr = ipa; 8107 /* Combine the S1 and S2 perms. */ 8108 *prot &= s2_prot; 8109 return ret; 8110 } else { 8111 /* 8112 * For non-EL2 CPUs a stage1+stage2 translation is just stage 1. 8113 */ 8114 mmu_idx += ARMMMUIdx_S1NSE0; 8115 } 8116 } 8117 8118 /* The page table entries may downgrade secure to non-secure, but 8119 * cannot upgrade an non-secure translation regime's attributes 8120 * to secure. 8121 */ 8122 attrs->secure = regime_is_secure(env, mmu_idx); 8123 attrs->user = regime_is_user(env, mmu_idx); 8124 8125 /* Fast Context Switch Extension. This doesn't exist at all in v8. 8126 * In v7 and earlier it affects all stage 1 translations. 8127 */ 8128 if (address < 0x02000000 && mmu_idx != ARMMMUIdx_S2NS 8129 && !arm_feature(env, ARM_FEATURE_V8)) { 8130 if (regime_el(env, mmu_idx) == 3) { 8131 address += env->cp15.fcseidr_s; 8132 } else { 8133 address += env->cp15.fcseidr_ns; 8134 } 8135 } 8136 8137 /* pmsav7 has special handling for when MPU is disabled so call it before 8138 * the common MMU/MPU disabled check below. 8139 */ 8140 if (arm_feature(env, ARM_FEATURE_MPU) && 8141 arm_feature(env, ARM_FEATURE_V7)) { 8142 *page_size = TARGET_PAGE_SIZE; 8143 return get_phys_addr_pmsav7(env, address, access_type, mmu_idx, 8144 phys_ptr, prot, fsr); 8145 } 8146 8147 if (regime_translation_disabled(env, mmu_idx)) { 8148 /* MMU/MPU disabled. */ 8149 *phys_ptr = address; 8150 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 8151 *page_size = TARGET_PAGE_SIZE; 8152 return 0; 8153 } 8154 8155 if (arm_feature(env, ARM_FEATURE_MPU)) { 8156 /* Pre-v7 MPU */ 8157 *page_size = TARGET_PAGE_SIZE; 8158 return get_phys_addr_pmsav5(env, address, access_type, mmu_idx, 8159 phys_ptr, prot, fsr); 8160 } 8161 8162 if (regime_using_lpae_format(env, mmu_idx)) { 8163 return get_phys_addr_lpae(env, address, access_type, mmu_idx, phys_ptr, 8164 attrs, prot, page_size, fsr, fi); 8165 } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { 8166 return get_phys_addr_v6(env, address, access_type, mmu_idx, phys_ptr, 8167 attrs, prot, page_size, fsr, fi); 8168 } else { 8169 return get_phys_addr_v5(env, address, access_type, mmu_idx, phys_ptr, 8170 prot, page_size, fsr, fi); 8171 } 8172 } 8173 8174 /* Walk the page table and (if the mapping exists) add the page 8175 * to the TLB. Return false on success, or true on failure. Populate 8176 * fsr with ARM DFSR/IFSR fault register format value on failure. 8177 */ 8178 bool arm_tlb_fill(CPUState *cs, vaddr address, 8179 int access_type, int mmu_idx, uint32_t *fsr, 8180 ARMMMUFaultInfo *fi) 8181 { 8182 ARMCPU *cpu = ARM_CPU(cs); 8183 CPUARMState *env = &cpu->env; 8184 hwaddr phys_addr; 8185 target_ulong page_size; 8186 int prot; 8187 int ret; 8188 MemTxAttrs attrs = {}; 8189 8190 ret = get_phys_addr(env, address, access_type, mmu_idx, &phys_addr, 8191 &attrs, &prot, &page_size, fsr, fi); 8192 if (!ret) { 8193 /* Map a single [sub]page. */ 8194 phys_addr &= TARGET_PAGE_MASK; 8195 address &= TARGET_PAGE_MASK; 8196 tlb_set_page_with_attrs(cs, address, phys_addr, attrs, 8197 prot, mmu_idx, page_size); 8198 return 0; 8199 } 8200 8201 return ret; 8202 } 8203 8204 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, 8205 MemTxAttrs *attrs) 8206 { 8207 ARMCPU *cpu = ARM_CPU(cs); 8208 CPUARMState *env = &cpu->env; 8209 hwaddr phys_addr; 8210 target_ulong page_size; 8211 int prot; 8212 bool ret; 8213 uint32_t fsr; 8214 ARMMMUFaultInfo fi = {}; 8215 8216 *attrs = (MemTxAttrs) {}; 8217 8218 ret = get_phys_addr(env, addr, 0, cpu_mmu_index(env, false), &phys_addr, 8219 attrs, &prot, &page_size, &fsr, &fi); 8220 8221 if (ret) { 8222 return -1; 8223 } 8224 return phys_addr; 8225 } 8226 8227 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) 8228 { 8229 ARMCPU *cpu = arm_env_get_cpu(env); 8230 8231 switch (reg) { 8232 case 0: /* APSR */ 8233 return xpsr_read(env) & 0xf8000000; 8234 case 1: /* IAPSR */ 8235 return xpsr_read(env) & 0xf80001ff; 8236 case 2: /* EAPSR */ 8237 return xpsr_read(env) & 0xff00fc00; 8238 case 3: /* xPSR */ 8239 return xpsr_read(env) & 0xff00fdff; 8240 case 5: /* IPSR */ 8241 return xpsr_read(env) & 0x000001ff; 8242 case 6: /* EPSR */ 8243 return xpsr_read(env) & 0x0700fc00; 8244 case 7: /* IEPSR */ 8245 return xpsr_read(env) & 0x0700edff; 8246 case 8: /* MSP */ 8247 return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13]; 8248 case 9: /* PSP */ 8249 return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp; 8250 case 16: /* PRIMASK */ 8251 return (env->daif & PSTATE_I) != 0; 8252 case 17: /* BASEPRI */ 8253 case 18: /* BASEPRI_MAX */ 8254 return env->v7m.basepri; 8255 case 19: /* FAULTMASK */ 8256 return (env->daif & PSTATE_F) != 0; 8257 case 20: /* CONTROL */ 8258 return env->v7m.control; 8259 default: 8260 /* ??? For debugging only. */ 8261 cpu_abort(CPU(cpu), "Unimplemented system register read (%d)\n", reg); 8262 return 0; 8263 } 8264 } 8265 8266 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) 8267 { 8268 ARMCPU *cpu = arm_env_get_cpu(env); 8269 8270 switch (reg) { 8271 case 0: /* APSR */ 8272 xpsr_write(env, val, 0xf8000000); 8273 break; 8274 case 1: /* IAPSR */ 8275 xpsr_write(env, val, 0xf8000000); 8276 break; 8277 case 2: /* EAPSR */ 8278 xpsr_write(env, val, 0xfe00fc00); 8279 break; 8280 case 3: /* xPSR */ 8281 xpsr_write(env, val, 0xfe00fc00); 8282 break; 8283 case 5: /* IPSR */ 8284 /* IPSR bits are readonly. */ 8285 break; 8286 case 6: /* EPSR */ 8287 xpsr_write(env, val, 0x0600fc00); 8288 break; 8289 case 7: /* IEPSR */ 8290 xpsr_write(env, val, 0x0600fc00); 8291 break; 8292 case 8: /* MSP */ 8293 if (env->v7m.current_sp) 8294 env->v7m.other_sp = val; 8295 else 8296 env->regs[13] = val; 8297 break; 8298 case 9: /* PSP */ 8299 if (env->v7m.current_sp) 8300 env->regs[13] = val; 8301 else 8302 env->v7m.other_sp = val; 8303 break; 8304 case 16: /* PRIMASK */ 8305 if (val & 1) { 8306 env->daif |= PSTATE_I; 8307 } else { 8308 env->daif &= ~PSTATE_I; 8309 } 8310 break; 8311 case 17: /* BASEPRI */ 8312 env->v7m.basepri = val & 0xff; 8313 break; 8314 case 18: /* BASEPRI_MAX */ 8315 val &= 0xff; 8316 if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0)) 8317 env->v7m.basepri = val; 8318 break; 8319 case 19: /* FAULTMASK */ 8320 if (val & 1) { 8321 env->daif |= PSTATE_F; 8322 } else { 8323 env->daif &= ~PSTATE_F; 8324 } 8325 break; 8326 case 20: /* CONTROL */ 8327 env->v7m.control = val & 3; 8328 switch_v7m_sp(env, (val & 2) != 0); 8329 break; 8330 default: 8331 /* ??? For debugging only. */ 8332 cpu_abort(CPU(cpu), "Unimplemented system register write (%d)\n", reg); 8333 return; 8334 } 8335 } 8336 8337 #endif 8338 8339 void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in) 8340 { 8341 /* Implement DC ZVA, which zeroes a fixed-length block of memory. 8342 * Note that we do not implement the (architecturally mandated) 8343 * alignment fault for attempts to use this on Device memory 8344 * (which matches the usual QEMU behaviour of not implementing either 8345 * alignment faults or any memory attribute handling). 8346 */ 8347 8348 ARMCPU *cpu = arm_env_get_cpu(env); 8349 uint64_t blocklen = 4 << cpu->dcz_blocksize; 8350 uint64_t vaddr = vaddr_in & ~(blocklen - 1); 8351 8352 #ifndef CONFIG_USER_ONLY 8353 { 8354 /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than 8355 * the block size so we might have to do more than one TLB lookup. 8356 * We know that in fact for any v8 CPU the page size is at least 4K 8357 * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only 8358 * 1K as an artefact of legacy v5 subpage support being present in the 8359 * same QEMU executable. 8360 */ 8361 int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE); 8362 void *hostaddr[maxidx]; 8363 int try, i; 8364 unsigned mmu_idx = cpu_mmu_index(env, false); 8365 TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx); 8366 8367 for (try = 0; try < 2; try++) { 8368 8369 for (i = 0; i < maxidx; i++) { 8370 hostaddr[i] = tlb_vaddr_to_host(env, 8371 vaddr + TARGET_PAGE_SIZE * i, 8372 1, mmu_idx); 8373 if (!hostaddr[i]) { 8374 break; 8375 } 8376 } 8377 if (i == maxidx) { 8378 /* If it's all in the TLB it's fair game for just writing to; 8379 * we know we don't need to update dirty status, etc. 8380 */ 8381 for (i = 0; i < maxidx - 1; i++) { 8382 memset(hostaddr[i], 0, TARGET_PAGE_SIZE); 8383 } 8384 memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE)); 8385 return; 8386 } 8387 /* OK, try a store and see if we can populate the tlb. This 8388 * might cause an exception if the memory isn't writable, 8389 * in which case we will longjmp out of here. We must for 8390 * this purpose use the actual register value passed to us 8391 * so that we get the fault address right. 8392 */ 8393 helper_ret_stb_mmu(env, vaddr_in, 0, oi, GETPC()); 8394 /* Now we can populate the other TLB entries, if any */ 8395 for (i = 0; i < maxidx; i++) { 8396 uint64_t va = vaddr + TARGET_PAGE_SIZE * i; 8397 if (va != (vaddr_in & TARGET_PAGE_MASK)) { 8398 helper_ret_stb_mmu(env, va, 0, oi, GETPC()); 8399 } 8400 } 8401 } 8402 8403 /* Slow path (probably attempt to do this to an I/O device or 8404 * similar, or clearing of a block of code we have translations 8405 * cached for). Just do a series of byte writes as the architecture 8406 * demands. It's not worth trying to use a cpu_physical_memory_map(), 8407 * memset(), unmap() sequence here because: 8408 * + we'd need to account for the blocksize being larger than a page 8409 * + the direct-RAM access case is almost always going to be dealt 8410 * with in the fastpath code above, so there's no speed benefit 8411 * + we would have to deal with the map returning NULL because the 8412 * bounce buffer was in use 8413 */ 8414 for (i = 0; i < blocklen; i++) { 8415 helper_ret_stb_mmu(env, vaddr + i, 0, oi, GETPC()); 8416 } 8417 } 8418 #else 8419 memset(g2h(vaddr), 0, blocklen); 8420 #endif 8421 } 8422 8423 /* Note that signed overflow is undefined in C. The following routines are 8424 careful to use unsigned types where modulo arithmetic is required. 8425 Failure to do so _will_ break on newer gcc. */ 8426 8427 /* Signed saturating arithmetic. */ 8428 8429 /* Perform 16-bit signed saturating addition. */ 8430 static inline uint16_t add16_sat(uint16_t a, uint16_t b) 8431 { 8432 uint16_t res; 8433 8434 res = a + b; 8435 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) { 8436 if (a & 0x8000) 8437 res = 0x8000; 8438 else 8439 res = 0x7fff; 8440 } 8441 return res; 8442 } 8443 8444 /* Perform 8-bit signed saturating addition. */ 8445 static inline uint8_t add8_sat(uint8_t a, uint8_t b) 8446 { 8447 uint8_t res; 8448 8449 res = a + b; 8450 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) { 8451 if (a & 0x80) 8452 res = 0x80; 8453 else 8454 res = 0x7f; 8455 } 8456 return res; 8457 } 8458 8459 /* Perform 16-bit signed saturating subtraction. */ 8460 static inline uint16_t sub16_sat(uint16_t a, uint16_t b) 8461 { 8462 uint16_t res; 8463 8464 res = a - b; 8465 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) { 8466 if (a & 0x8000) 8467 res = 0x8000; 8468 else 8469 res = 0x7fff; 8470 } 8471 return res; 8472 } 8473 8474 /* Perform 8-bit signed saturating subtraction. */ 8475 static inline uint8_t sub8_sat(uint8_t a, uint8_t b) 8476 { 8477 uint8_t res; 8478 8479 res = a - b; 8480 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) { 8481 if (a & 0x80) 8482 res = 0x80; 8483 else 8484 res = 0x7f; 8485 } 8486 return res; 8487 } 8488 8489 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16); 8490 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16); 8491 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8); 8492 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8); 8493 #define PFX q 8494 8495 #include "op_addsub.h" 8496 8497 /* Unsigned saturating arithmetic. */ 8498 static inline uint16_t add16_usat(uint16_t a, uint16_t b) 8499 { 8500 uint16_t res; 8501 res = a + b; 8502 if (res < a) 8503 res = 0xffff; 8504 return res; 8505 } 8506 8507 static inline uint16_t sub16_usat(uint16_t a, uint16_t b) 8508 { 8509 if (a > b) 8510 return a - b; 8511 else 8512 return 0; 8513 } 8514 8515 static inline uint8_t add8_usat(uint8_t a, uint8_t b) 8516 { 8517 uint8_t res; 8518 res = a + b; 8519 if (res < a) 8520 res = 0xff; 8521 return res; 8522 } 8523 8524 static inline uint8_t sub8_usat(uint8_t a, uint8_t b) 8525 { 8526 if (a > b) 8527 return a - b; 8528 else 8529 return 0; 8530 } 8531 8532 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16); 8533 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16); 8534 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8); 8535 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8); 8536 #define PFX uq 8537 8538 #include "op_addsub.h" 8539 8540 /* Signed modulo arithmetic. */ 8541 #define SARITH16(a, b, n, op) do { \ 8542 int32_t sum; \ 8543 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \ 8544 RESULT(sum, n, 16); \ 8545 if (sum >= 0) \ 8546 ge |= 3 << (n * 2); \ 8547 } while(0) 8548 8549 #define SARITH8(a, b, n, op) do { \ 8550 int32_t sum; \ 8551 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \ 8552 RESULT(sum, n, 8); \ 8553 if (sum >= 0) \ 8554 ge |= 1 << n; \ 8555 } while(0) 8556 8557 8558 #define ADD16(a, b, n) SARITH16(a, b, n, +) 8559 #define SUB16(a, b, n) SARITH16(a, b, n, -) 8560 #define ADD8(a, b, n) SARITH8(a, b, n, +) 8561 #define SUB8(a, b, n) SARITH8(a, b, n, -) 8562 #define PFX s 8563 #define ARITH_GE 8564 8565 #include "op_addsub.h" 8566 8567 /* Unsigned modulo arithmetic. */ 8568 #define ADD16(a, b, n) do { \ 8569 uint32_t sum; \ 8570 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \ 8571 RESULT(sum, n, 16); \ 8572 if ((sum >> 16) == 1) \ 8573 ge |= 3 << (n * 2); \ 8574 } while(0) 8575 8576 #define ADD8(a, b, n) do { \ 8577 uint32_t sum; \ 8578 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \ 8579 RESULT(sum, n, 8); \ 8580 if ((sum >> 8) == 1) \ 8581 ge |= 1 << n; \ 8582 } while(0) 8583 8584 #define SUB16(a, b, n) do { \ 8585 uint32_t sum; \ 8586 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \ 8587 RESULT(sum, n, 16); \ 8588 if ((sum >> 16) == 0) \ 8589 ge |= 3 << (n * 2); \ 8590 } while(0) 8591 8592 #define SUB8(a, b, n) do { \ 8593 uint32_t sum; \ 8594 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \ 8595 RESULT(sum, n, 8); \ 8596 if ((sum >> 8) == 0) \ 8597 ge |= 1 << n; \ 8598 } while(0) 8599 8600 #define PFX u 8601 #define ARITH_GE 8602 8603 #include "op_addsub.h" 8604 8605 /* Halved signed arithmetic. */ 8606 #define ADD16(a, b, n) \ 8607 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16) 8608 #define SUB16(a, b, n) \ 8609 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16) 8610 #define ADD8(a, b, n) \ 8611 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8) 8612 #define SUB8(a, b, n) \ 8613 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8) 8614 #define PFX sh 8615 8616 #include "op_addsub.h" 8617 8618 /* Halved unsigned arithmetic. */ 8619 #define ADD16(a, b, n) \ 8620 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16) 8621 #define SUB16(a, b, n) \ 8622 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16) 8623 #define ADD8(a, b, n) \ 8624 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8) 8625 #define SUB8(a, b, n) \ 8626 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8) 8627 #define PFX uh 8628 8629 #include "op_addsub.h" 8630 8631 static inline uint8_t do_usad(uint8_t a, uint8_t b) 8632 { 8633 if (a > b) 8634 return a - b; 8635 else 8636 return b - a; 8637 } 8638 8639 /* Unsigned sum of absolute byte differences. */ 8640 uint32_t HELPER(usad8)(uint32_t a, uint32_t b) 8641 { 8642 uint32_t sum; 8643 sum = do_usad(a, b); 8644 sum += do_usad(a >> 8, b >> 8); 8645 sum += do_usad(a >> 16, b >>16); 8646 sum += do_usad(a >> 24, b >> 24); 8647 return sum; 8648 } 8649 8650 /* For ARMv6 SEL instruction. */ 8651 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b) 8652 { 8653 uint32_t mask; 8654 8655 mask = 0; 8656 if (flags & 1) 8657 mask |= 0xff; 8658 if (flags & 2) 8659 mask |= 0xff00; 8660 if (flags & 4) 8661 mask |= 0xff0000; 8662 if (flags & 8) 8663 mask |= 0xff000000; 8664 return (a & mask) | (b & ~mask); 8665 } 8666 8667 /* VFP support. We follow the convention used for VFP instructions: 8668 Single precision routines have a "s" suffix, double precision a 8669 "d" suffix. */ 8670 8671 /* Convert host exception flags to vfp form. */ 8672 static inline int vfp_exceptbits_from_host(int host_bits) 8673 { 8674 int target_bits = 0; 8675 8676 if (host_bits & float_flag_invalid) 8677 target_bits |= 1; 8678 if (host_bits & float_flag_divbyzero) 8679 target_bits |= 2; 8680 if (host_bits & float_flag_overflow) 8681 target_bits |= 4; 8682 if (host_bits & (float_flag_underflow | float_flag_output_denormal)) 8683 target_bits |= 8; 8684 if (host_bits & float_flag_inexact) 8685 target_bits |= 0x10; 8686 if (host_bits & float_flag_input_denormal) 8687 target_bits |= 0x80; 8688 return target_bits; 8689 } 8690 8691 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env) 8692 { 8693 int i; 8694 uint32_t fpscr; 8695 8696 fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff) 8697 | (env->vfp.vec_len << 16) 8698 | (env->vfp.vec_stride << 20); 8699 i = get_float_exception_flags(&env->vfp.fp_status); 8700 i |= get_float_exception_flags(&env->vfp.standard_fp_status); 8701 fpscr |= vfp_exceptbits_from_host(i); 8702 return fpscr; 8703 } 8704 8705 uint32_t vfp_get_fpscr(CPUARMState *env) 8706 { 8707 return HELPER(vfp_get_fpscr)(env); 8708 } 8709 8710 /* Convert vfp exception flags to target form. */ 8711 static inline int vfp_exceptbits_to_host(int target_bits) 8712 { 8713 int host_bits = 0; 8714 8715 if (target_bits & 1) 8716 host_bits |= float_flag_invalid; 8717 if (target_bits & 2) 8718 host_bits |= float_flag_divbyzero; 8719 if (target_bits & 4) 8720 host_bits |= float_flag_overflow; 8721 if (target_bits & 8) 8722 host_bits |= float_flag_underflow; 8723 if (target_bits & 0x10) 8724 host_bits |= float_flag_inexact; 8725 if (target_bits & 0x80) 8726 host_bits |= float_flag_input_denormal; 8727 return host_bits; 8728 } 8729 8730 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) 8731 { 8732 int i; 8733 uint32_t changed; 8734 8735 changed = env->vfp.xregs[ARM_VFP_FPSCR]; 8736 env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff); 8737 env->vfp.vec_len = (val >> 16) & 7; 8738 env->vfp.vec_stride = (val >> 20) & 3; 8739 8740 changed ^= val; 8741 if (changed & (3 << 22)) { 8742 i = (val >> 22) & 3; 8743 switch (i) { 8744 case FPROUNDING_TIEEVEN: 8745 i = float_round_nearest_even; 8746 break; 8747 case FPROUNDING_POSINF: 8748 i = float_round_up; 8749 break; 8750 case FPROUNDING_NEGINF: 8751 i = float_round_down; 8752 break; 8753 case FPROUNDING_ZERO: 8754 i = float_round_to_zero; 8755 break; 8756 } 8757 set_float_rounding_mode(i, &env->vfp.fp_status); 8758 } 8759 if (changed & (1 << 24)) { 8760 set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status); 8761 set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status); 8762 } 8763 if (changed & (1 << 25)) 8764 set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status); 8765 8766 i = vfp_exceptbits_to_host(val); 8767 set_float_exception_flags(i, &env->vfp.fp_status); 8768 set_float_exception_flags(0, &env->vfp.standard_fp_status); 8769 } 8770 8771 void vfp_set_fpscr(CPUARMState *env, uint32_t val) 8772 { 8773 HELPER(vfp_set_fpscr)(env, val); 8774 } 8775 8776 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p)) 8777 8778 #define VFP_BINOP(name) \ 8779 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \ 8780 { \ 8781 float_status *fpst = fpstp; \ 8782 return float32_ ## name(a, b, fpst); \ 8783 } \ 8784 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \ 8785 { \ 8786 float_status *fpst = fpstp; \ 8787 return float64_ ## name(a, b, fpst); \ 8788 } 8789 VFP_BINOP(add) 8790 VFP_BINOP(sub) 8791 VFP_BINOP(mul) 8792 VFP_BINOP(div) 8793 VFP_BINOP(min) 8794 VFP_BINOP(max) 8795 VFP_BINOP(minnum) 8796 VFP_BINOP(maxnum) 8797 #undef VFP_BINOP 8798 8799 float32 VFP_HELPER(neg, s)(float32 a) 8800 { 8801 return float32_chs(a); 8802 } 8803 8804 float64 VFP_HELPER(neg, d)(float64 a) 8805 { 8806 return float64_chs(a); 8807 } 8808 8809 float32 VFP_HELPER(abs, s)(float32 a) 8810 { 8811 return float32_abs(a); 8812 } 8813 8814 float64 VFP_HELPER(abs, d)(float64 a) 8815 { 8816 return float64_abs(a); 8817 } 8818 8819 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env) 8820 { 8821 return float32_sqrt(a, &env->vfp.fp_status); 8822 } 8823 8824 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env) 8825 { 8826 return float64_sqrt(a, &env->vfp.fp_status); 8827 } 8828 8829 /* XXX: check quiet/signaling case */ 8830 #define DO_VFP_cmp(p, type) \ 8831 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \ 8832 { \ 8833 uint32_t flags; \ 8834 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \ 8835 case 0: flags = 0x6; break; \ 8836 case -1: flags = 0x8; break; \ 8837 case 1: flags = 0x2; break; \ 8838 default: case 2: flags = 0x3; break; \ 8839 } \ 8840 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \ 8841 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \ 8842 } \ 8843 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \ 8844 { \ 8845 uint32_t flags; \ 8846 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \ 8847 case 0: flags = 0x6; break; \ 8848 case -1: flags = 0x8; break; \ 8849 case 1: flags = 0x2; break; \ 8850 default: case 2: flags = 0x3; break; \ 8851 } \ 8852 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \ 8853 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \ 8854 } 8855 DO_VFP_cmp(s, float32) 8856 DO_VFP_cmp(d, float64) 8857 #undef DO_VFP_cmp 8858 8859 /* Integer to float and float to integer conversions */ 8860 8861 #define CONV_ITOF(name, fsz, sign) \ 8862 float##fsz HELPER(name)(uint32_t x, void *fpstp) \ 8863 { \ 8864 float_status *fpst = fpstp; \ 8865 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \ 8866 } 8867 8868 #define CONV_FTOI(name, fsz, sign, round) \ 8869 uint32_t HELPER(name)(float##fsz x, void *fpstp) \ 8870 { \ 8871 float_status *fpst = fpstp; \ 8872 if (float##fsz##_is_any_nan(x)) { \ 8873 float_raise(float_flag_invalid, fpst); \ 8874 return 0; \ 8875 } \ 8876 return float##fsz##_to_##sign##int32##round(x, fpst); \ 8877 } 8878 8879 #define FLOAT_CONVS(name, p, fsz, sign) \ 8880 CONV_ITOF(vfp_##name##to##p, fsz, sign) \ 8881 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \ 8882 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero) 8883 8884 FLOAT_CONVS(si, s, 32, ) 8885 FLOAT_CONVS(si, d, 64, ) 8886 FLOAT_CONVS(ui, s, 32, u) 8887 FLOAT_CONVS(ui, d, 64, u) 8888 8889 #undef CONV_ITOF 8890 #undef CONV_FTOI 8891 #undef FLOAT_CONVS 8892 8893 /* floating point conversion */ 8894 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env) 8895 { 8896 float64 r = float32_to_float64(x, &env->vfp.fp_status); 8897 /* ARM requires that S<->D conversion of any kind of NaN generates 8898 * a quiet NaN by forcing the most significant frac bit to 1. 8899 */ 8900 return float64_maybe_silence_nan(r, &env->vfp.fp_status); 8901 } 8902 8903 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env) 8904 { 8905 float32 r = float64_to_float32(x, &env->vfp.fp_status); 8906 /* ARM requires that S<->D conversion of any kind of NaN generates 8907 * a quiet NaN by forcing the most significant frac bit to 1. 8908 */ 8909 return float32_maybe_silence_nan(r, &env->vfp.fp_status); 8910 } 8911 8912 /* VFP3 fixed point conversion. */ 8913 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ 8914 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \ 8915 void *fpstp) \ 8916 { \ 8917 float_status *fpst = fpstp; \ 8918 float##fsz tmp; \ 8919 tmp = itype##_to_##float##fsz(x, fpst); \ 8920 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \ 8921 } 8922 8923 /* Notice that we want only input-denormal exception flags from the 8924 * scalbn operation: the other possible flags (overflow+inexact if 8925 * we overflow to infinity, output-denormal) aren't correct for the 8926 * complete scale-and-convert operation. 8927 */ 8928 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \ 8929 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \ 8930 uint32_t shift, \ 8931 void *fpstp) \ 8932 { \ 8933 float_status *fpst = fpstp; \ 8934 int old_exc_flags = get_float_exception_flags(fpst); \ 8935 float##fsz tmp; \ 8936 if (float##fsz##_is_any_nan(x)) { \ 8937 float_raise(float_flag_invalid, fpst); \ 8938 return 0; \ 8939 } \ 8940 tmp = float##fsz##_scalbn(x, shift, fpst); \ 8941 old_exc_flags |= get_float_exception_flags(fpst) \ 8942 & float_flag_input_denormal; \ 8943 set_float_exception_flags(old_exc_flags, fpst); \ 8944 return float##fsz##_to_##itype##round(tmp, fpst); \ 8945 } 8946 8947 #define VFP_CONV_FIX(name, p, fsz, isz, itype) \ 8948 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ 8949 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \ 8950 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, ) 8951 8952 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \ 8953 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ 8954 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, ) 8955 8956 VFP_CONV_FIX(sh, d, 64, 64, int16) 8957 VFP_CONV_FIX(sl, d, 64, 64, int32) 8958 VFP_CONV_FIX_A64(sq, d, 64, 64, int64) 8959 VFP_CONV_FIX(uh, d, 64, 64, uint16) 8960 VFP_CONV_FIX(ul, d, 64, 64, uint32) 8961 VFP_CONV_FIX_A64(uq, d, 64, 64, uint64) 8962 VFP_CONV_FIX(sh, s, 32, 32, int16) 8963 VFP_CONV_FIX(sl, s, 32, 32, int32) 8964 VFP_CONV_FIX_A64(sq, s, 32, 64, int64) 8965 VFP_CONV_FIX(uh, s, 32, 32, uint16) 8966 VFP_CONV_FIX(ul, s, 32, 32, uint32) 8967 VFP_CONV_FIX_A64(uq, s, 32, 64, uint64) 8968 #undef VFP_CONV_FIX 8969 #undef VFP_CONV_FIX_FLOAT 8970 #undef VFP_CONV_FLOAT_FIX_ROUND 8971 8972 /* Set the current fp rounding mode and return the old one. 8973 * The argument is a softfloat float_round_ value. 8974 */ 8975 uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env) 8976 { 8977 float_status *fp_status = &env->vfp.fp_status; 8978 8979 uint32_t prev_rmode = get_float_rounding_mode(fp_status); 8980 set_float_rounding_mode(rmode, fp_status); 8981 8982 return prev_rmode; 8983 } 8984 8985 /* Set the current fp rounding mode in the standard fp status and return 8986 * the old one. This is for NEON instructions that need to change the 8987 * rounding mode but wish to use the standard FPSCR values for everything 8988 * else. Always set the rounding mode back to the correct value after 8989 * modifying it. 8990 * The argument is a softfloat float_round_ value. 8991 */ 8992 uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env) 8993 { 8994 float_status *fp_status = &env->vfp.standard_fp_status; 8995 8996 uint32_t prev_rmode = get_float_rounding_mode(fp_status); 8997 set_float_rounding_mode(rmode, fp_status); 8998 8999 return prev_rmode; 9000 } 9001 9002 /* Half precision conversions. */ 9003 static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s) 9004 { 9005 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; 9006 float32 r = float16_to_float32(make_float16(a), ieee, s); 9007 if (ieee) { 9008 return float32_maybe_silence_nan(r, s); 9009 } 9010 return r; 9011 } 9012 9013 static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s) 9014 { 9015 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; 9016 float16 r = float32_to_float16(a, ieee, s); 9017 if (ieee) { 9018 r = float16_maybe_silence_nan(r, s); 9019 } 9020 return float16_val(r); 9021 } 9022 9023 float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env) 9024 { 9025 return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status); 9026 } 9027 9028 uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env) 9029 { 9030 return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status); 9031 } 9032 9033 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env) 9034 { 9035 return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status); 9036 } 9037 9038 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env) 9039 { 9040 return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status); 9041 } 9042 9043 float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env) 9044 { 9045 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; 9046 float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status); 9047 if (ieee) { 9048 return float64_maybe_silence_nan(r, &env->vfp.fp_status); 9049 } 9050 return r; 9051 } 9052 9053 uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env) 9054 { 9055 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; 9056 float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status); 9057 if (ieee) { 9058 r = float16_maybe_silence_nan(r, &env->vfp.fp_status); 9059 } 9060 return float16_val(r); 9061 } 9062 9063 #define float32_two make_float32(0x40000000) 9064 #define float32_three make_float32(0x40400000) 9065 #define float32_one_point_five make_float32(0x3fc00000) 9066 9067 float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env) 9068 { 9069 float_status *s = &env->vfp.standard_fp_status; 9070 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) || 9071 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) { 9072 if (!(float32_is_zero(a) || float32_is_zero(b))) { 9073 float_raise(float_flag_input_denormal, s); 9074 } 9075 return float32_two; 9076 } 9077 return float32_sub(float32_two, float32_mul(a, b, s), s); 9078 } 9079 9080 float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env) 9081 { 9082 float_status *s = &env->vfp.standard_fp_status; 9083 float32 product; 9084 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) || 9085 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) { 9086 if (!(float32_is_zero(a) || float32_is_zero(b))) { 9087 float_raise(float_flag_input_denormal, s); 9088 } 9089 return float32_one_point_five; 9090 } 9091 product = float32_mul(a, b, s); 9092 return float32_div(float32_sub(float32_three, product, s), float32_two, s); 9093 } 9094 9095 /* NEON helpers. */ 9096 9097 /* Constants 256 and 512 are used in some helpers; we avoid relying on 9098 * int->float conversions at run-time. */ 9099 #define float64_256 make_float64(0x4070000000000000LL) 9100 #define float64_512 make_float64(0x4080000000000000LL) 9101 #define float32_maxnorm make_float32(0x7f7fffff) 9102 #define float64_maxnorm make_float64(0x7fefffffffffffffLL) 9103 9104 /* Reciprocal functions 9105 * 9106 * The algorithm that must be used to calculate the estimate 9107 * is specified by the ARM ARM, see FPRecipEstimate() 9108 */ 9109 9110 static float64 recip_estimate(float64 a, float_status *real_fp_status) 9111 { 9112 /* These calculations mustn't set any fp exception flags, 9113 * so we use a local copy of the fp_status. 9114 */ 9115 float_status dummy_status = *real_fp_status; 9116 float_status *s = &dummy_status; 9117 /* q = (int)(a * 512.0) */ 9118 float64 q = float64_mul(float64_512, a, s); 9119 int64_t q_int = float64_to_int64_round_to_zero(q, s); 9120 9121 /* r = 1.0 / (((double)q + 0.5) / 512.0) */ 9122 q = int64_to_float64(q_int, s); 9123 q = float64_add(q, float64_half, s); 9124 q = float64_div(q, float64_512, s); 9125 q = float64_div(float64_one, q, s); 9126 9127 /* s = (int)(256.0 * r + 0.5) */ 9128 q = float64_mul(q, float64_256, s); 9129 q = float64_add(q, float64_half, s); 9130 q_int = float64_to_int64_round_to_zero(q, s); 9131 9132 /* return (double)s / 256.0 */ 9133 return float64_div(int64_to_float64(q_int, s), float64_256, s); 9134 } 9135 9136 /* Common wrapper to call recip_estimate */ 9137 static float64 call_recip_estimate(float64 num, int off, float_status *fpst) 9138 { 9139 uint64_t val64 = float64_val(num); 9140 uint64_t frac = extract64(val64, 0, 52); 9141 int64_t exp = extract64(val64, 52, 11); 9142 uint64_t sbit; 9143 float64 scaled, estimate; 9144 9145 /* Generate the scaled number for the estimate function */ 9146 if (exp == 0) { 9147 if (extract64(frac, 51, 1) == 0) { 9148 exp = -1; 9149 frac = extract64(frac, 0, 50) << 2; 9150 } else { 9151 frac = extract64(frac, 0, 51) << 1; 9152 } 9153 } 9154 9155 /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */ 9156 scaled = make_float64((0x3feULL << 52) 9157 | extract64(frac, 44, 8) << 44); 9158 9159 estimate = recip_estimate(scaled, fpst); 9160 9161 /* Build new result */ 9162 val64 = float64_val(estimate); 9163 sbit = 0x8000000000000000ULL & val64; 9164 exp = off - exp; 9165 frac = extract64(val64, 0, 52); 9166 9167 if (exp == 0) { 9168 frac = 1ULL << 51 | extract64(frac, 1, 51); 9169 } else if (exp == -1) { 9170 frac = 1ULL << 50 | extract64(frac, 2, 50); 9171 exp = 0; 9172 } 9173 9174 return make_float64(sbit | (exp << 52) | frac); 9175 } 9176 9177 static bool round_to_inf(float_status *fpst, bool sign_bit) 9178 { 9179 switch (fpst->float_rounding_mode) { 9180 case float_round_nearest_even: /* Round to Nearest */ 9181 return true; 9182 case float_round_up: /* Round to +Inf */ 9183 return !sign_bit; 9184 case float_round_down: /* Round to -Inf */ 9185 return sign_bit; 9186 case float_round_to_zero: /* Round to Zero */ 9187 return false; 9188 } 9189 9190 g_assert_not_reached(); 9191 } 9192 9193 float32 HELPER(recpe_f32)(float32 input, void *fpstp) 9194 { 9195 float_status *fpst = fpstp; 9196 float32 f32 = float32_squash_input_denormal(input, fpst); 9197 uint32_t f32_val = float32_val(f32); 9198 uint32_t f32_sbit = 0x80000000ULL & f32_val; 9199 int32_t f32_exp = extract32(f32_val, 23, 8); 9200 uint32_t f32_frac = extract32(f32_val, 0, 23); 9201 float64 f64, r64; 9202 uint64_t r64_val; 9203 int64_t r64_exp; 9204 uint64_t r64_frac; 9205 9206 if (float32_is_any_nan(f32)) { 9207 float32 nan = f32; 9208 if (float32_is_signaling_nan(f32, fpst)) { 9209 float_raise(float_flag_invalid, fpst); 9210 nan = float32_maybe_silence_nan(f32, fpst); 9211 } 9212 if (fpst->default_nan_mode) { 9213 nan = float32_default_nan(fpst); 9214 } 9215 return nan; 9216 } else if (float32_is_infinity(f32)) { 9217 return float32_set_sign(float32_zero, float32_is_neg(f32)); 9218 } else if (float32_is_zero(f32)) { 9219 float_raise(float_flag_divbyzero, fpst); 9220 return float32_set_sign(float32_infinity, float32_is_neg(f32)); 9221 } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) { 9222 /* Abs(value) < 2.0^-128 */ 9223 float_raise(float_flag_overflow | float_flag_inexact, fpst); 9224 if (round_to_inf(fpst, f32_sbit)) { 9225 return float32_set_sign(float32_infinity, float32_is_neg(f32)); 9226 } else { 9227 return float32_set_sign(float32_maxnorm, float32_is_neg(f32)); 9228 } 9229 } else if (f32_exp >= 253 && fpst->flush_to_zero) { 9230 float_raise(float_flag_underflow, fpst); 9231 return float32_set_sign(float32_zero, float32_is_neg(f32)); 9232 } 9233 9234 9235 f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29); 9236 r64 = call_recip_estimate(f64, 253, fpst); 9237 r64_val = float64_val(r64); 9238 r64_exp = extract64(r64_val, 52, 11); 9239 r64_frac = extract64(r64_val, 0, 52); 9240 9241 /* result = sign : result_exp<7:0> : fraction<51:29>; */ 9242 return make_float32(f32_sbit | 9243 (r64_exp & 0xff) << 23 | 9244 extract64(r64_frac, 29, 24)); 9245 } 9246 9247 float64 HELPER(recpe_f64)(float64 input, void *fpstp) 9248 { 9249 float_status *fpst = fpstp; 9250 float64 f64 = float64_squash_input_denormal(input, fpst); 9251 uint64_t f64_val = float64_val(f64); 9252 uint64_t f64_sbit = 0x8000000000000000ULL & f64_val; 9253 int64_t f64_exp = extract64(f64_val, 52, 11); 9254 float64 r64; 9255 uint64_t r64_val; 9256 int64_t r64_exp; 9257 uint64_t r64_frac; 9258 9259 /* Deal with any special cases */ 9260 if (float64_is_any_nan(f64)) { 9261 float64 nan = f64; 9262 if (float64_is_signaling_nan(f64, fpst)) { 9263 float_raise(float_flag_invalid, fpst); 9264 nan = float64_maybe_silence_nan(f64, fpst); 9265 } 9266 if (fpst->default_nan_mode) { 9267 nan = float64_default_nan(fpst); 9268 } 9269 return nan; 9270 } else if (float64_is_infinity(f64)) { 9271 return float64_set_sign(float64_zero, float64_is_neg(f64)); 9272 } else if (float64_is_zero(f64)) { 9273 float_raise(float_flag_divbyzero, fpst); 9274 return float64_set_sign(float64_infinity, float64_is_neg(f64)); 9275 } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) { 9276 /* Abs(value) < 2.0^-1024 */ 9277 float_raise(float_flag_overflow | float_flag_inexact, fpst); 9278 if (round_to_inf(fpst, f64_sbit)) { 9279 return float64_set_sign(float64_infinity, float64_is_neg(f64)); 9280 } else { 9281 return float64_set_sign(float64_maxnorm, float64_is_neg(f64)); 9282 } 9283 } else if (f64_exp >= 2045 && fpst->flush_to_zero) { 9284 float_raise(float_flag_underflow, fpst); 9285 return float64_set_sign(float64_zero, float64_is_neg(f64)); 9286 } 9287 9288 r64 = call_recip_estimate(f64, 2045, fpst); 9289 r64_val = float64_val(r64); 9290 r64_exp = extract64(r64_val, 52, 11); 9291 r64_frac = extract64(r64_val, 0, 52); 9292 9293 /* result = sign : result_exp<10:0> : fraction<51:0> */ 9294 return make_float64(f64_sbit | 9295 ((r64_exp & 0x7ff) << 52) | 9296 r64_frac); 9297 } 9298 9299 /* The algorithm that must be used to calculate the estimate 9300 * is specified by the ARM ARM. 9301 */ 9302 static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status) 9303 { 9304 /* These calculations mustn't set any fp exception flags, 9305 * so we use a local copy of the fp_status. 9306 */ 9307 float_status dummy_status = *real_fp_status; 9308 float_status *s = &dummy_status; 9309 float64 q; 9310 int64_t q_int; 9311 9312 if (float64_lt(a, float64_half, s)) { 9313 /* range 0.25 <= a < 0.5 */ 9314 9315 /* a in units of 1/512 rounded down */ 9316 /* q0 = (int)(a * 512.0); */ 9317 q = float64_mul(float64_512, a, s); 9318 q_int = float64_to_int64_round_to_zero(q, s); 9319 9320 /* reciprocal root r */ 9321 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */ 9322 q = int64_to_float64(q_int, s); 9323 q = float64_add(q, float64_half, s); 9324 q = float64_div(q, float64_512, s); 9325 q = float64_sqrt(q, s); 9326 q = float64_div(float64_one, q, s); 9327 } else { 9328 /* range 0.5 <= a < 1.0 */ 9329 9330 /* a in units of 1/256 rounded down */ 9331 /* q1 = (int)(a * 256.0); */ 9332 q = float64_mul(float64_256, a, s); 9333 int64_t q_int = float64_to_int64_round_to_zero(q, s); 9334 9335 /* reciprocal root r */ 9336 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */ 9337 q = int64_to_float64(q_int, s); 9338 q = float64_add(q, float64_half, s); 9339 q = float64_div(q, float64_256, s); 9340 q = float64_sqrt(q, s); 9341 q = float64_div(float64_one, q, s); 9342 } 9343 /* r in units of 1/256 rounded to nearest */ 9344 /* s = (int)(256.0 * r + 0.5); */ 9345 9346 q = float64_mul(q, float64_256,s ); 9347 q = float64_add(q, float64_half, s); 9348 q_int = float64_to_int64_round_to_zero(q, s); 9349 9350 /* return (double)s / 256.0;*/ 9351 return float64_div(int64_to_float64(q_int, s), float64_256, s); 9352 } 9353 9354 float32 HELPER(rsqrte_f32)(float32 input, void *fpstp) 9355 { 9356 float_status *s = fpstp; 9357 float32 f32 = float32_squash_input_denormal(input, s); 9358 uint32_t val = float32_val(f32); 9359 uint32_t f32_sbit = 0x80000000 & val; 9360 int32_t f32_exp = extract32(val, 23, 8); 9361 uint32_t f32_frac = extract32(val, 0, 23); 9362 uint64_t f64_frac; 9363 uint64_t val64; 9364 int result_exp; 9365 float64 f64; 9366 9367 if (float32_is_any_nan(f32)) { 9368 float32 nan = f32; 9369 if (float32_is_signaling_nan(f32, s)) { 9370 float_raise(float_flag_invalid, s); 9371 nan = float32_maybe_silence_nan(f32, s); 9372 } 9373 if (s->default_nan_mode) { 9374 nan = float32_default_nan(s); 9375 } 9376 return nan; 9377 } else if (float32_is_zero(f32)) { 9378 float_raise(float_flag_divbyzero, s); 9379 return float32_set_sign(float32_infinity, float32_is_neg(f32)); 9380 } else if (float32_is_neg(f32)) { 9381 float_raise(float_flag_invalid, s); 9382 return float32_default_nan(s); 9383 } else if (float32_is_infinity(f32)) { 9384 return float32_zero; 9385 } 9386 9387 /* Scale and normalize to a double-precision value between 0.25 and 1.0, 9388 * preserving the parity of the exponent. */ 9389 9390 f64_frac = ((uint64_t) f32_frac) << 29; 9391 if (f32_exp == 0) { 9392 while (extract64(f64_frac, 51, 1) == 0) { 9393 f64_frac = f64_frac << 1; 9394 f32_exp = f32_exp-1; 9395 } 9396 f64_frac = extract64(f64_frac, 0, 51) << 1; 9397 } 9398 9399 if (extract64(f32_exp, 0, 1) == 0) { 9400 f64 = make_float64(((uint64_t) f32_sbit) << 32 9401 | (0x3feULL << 52) 9402 | f64_frac); 9403 } else { 9404 f64 = make_float64(((uint64_t) f32_sbit) << 32 9405 | (0x3fdULL << 52) 9406 | f64_frac); 9407 } 9408 9409 result_exp = (380 - f32_exp) / 2; 9410 9411 f64 = recip_sqrt_estimate(f64, s); 9412 9413 val64 = float64_val(f64); 9414 9415 val = ((result_exp & 0xff) << 23) 9416 | ((val64 >> 29) & 0x7fffff); 9417 return make_float32(val); 9418 } 9419 9420 float64 HELPER(rsqrte_f64)(float64 input, void *fpstp) 9421 { 9422 float_status *s = fpstp; 9423 float64 f64 = float64_squash_input_denormal(input, s); 9424 uint64_t val = float64_val(f64); 9425 uint64_t f64_sbit = 0x8000000000000000ULL & val; 9426 int64_t f64_exp = extract64(val, 52, 11); 9427 uint64_t f64_frac = extract64(val, 0, 52); 9428 int64_t result_exp; 9429 uint64_t result_frac; 9430 9431 if (float64_is_any_nan(f64)) { 9432 float64 nan = f64; 9433 if (float64_is_signaling_nan(f64, s)) { 9434 float_raise(float_flag_invalid, s); 9435 nan = float64_maybe_silence_nan(f64, s); 9436 } 9437 if (s->default_nan_mode) { 9438 nan = float64_default_nan(s); 9439 } 9440 return nan; 9441 } else if (float64_is_zero(f64)) { 9442 float_raise(float_flag_divbyzero, s); 9443 return float64_set_sign(float64_infinity, float64_is_neg(f64)); 9444 } else if (float64_is_neg(f64)) { 9445 float_raise(float_flag_invalid, s); 9446 return float64_default_nan(s); 9447 } else if (float64_is_infinity(f64)) { 9448 return float64_zero; 9449 } 9450 9451 /* Scale and normalize to a double-precision value between 0.25 and 1.0, 9452 * preserving the parity of the exponent. */ 9453 9454 if (f64_exp == 0) { 9455 while (extract64(f64_frac, 51, 1) == 0) { 9456 f64_frac = f64_frac << 1; 9457 f64_exp = f64_exp - 1; 9458 } 9459 f64_frac = extract64(f64_frac, 0, 51) << 1; 9460 } 9461 9462 if (extract64(f64_exp, 0, 1) == 0) { 9463 f64 = make_float64(f64_sbit 9464 | (0x3feULL << 52) 9465 | f64_frac); 9466 } else { 9467 f64 = make_float64(f64_sbit 9468 | (0x3fdULL << 52) 9469 | f64_frac); 9470 } 9471 9472 result_exp = (3068 - f64_exp) / 2; 9473 9474 f64 = recip_sqrt_estimate(f64, s); 9475 9476 result_frac = extract64(float64_val(f64), 0, 52); 9477 9478 return make_float64(f64_sbit | 9479 ((result_exp & 0x7ff) << 52) | 9480 result_frac); 9481 } 9482 9483 uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp) 9484 { 9485 float_status *s = fpstp; 9486 float64 f64; 9487 9488 if ((a & 0x80000000) == 0) { 9489 return 0xffffffff; 9490 } 9491 9492 f64 = make_float64((0x3feULL << 52) 9493 | ((int64_t)(a & 0x7fffffff) << 21)); 9494 9495 f64 = recip_estimate(f64, s); 9496 9497 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff); 9498 } 9499 9500 uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp) 9501 { 9502 float_status *fpst = fpstp; 9503 float64 f64; 9504 9505 if ((a & 0xc0000000) == 0) { 9506 return 0xffffffff; 9507 } 9508 9509 if (a & 0x80000000) { 9510 f64 = make_float64((0x3feULL << 52) 9511 | ((uint64_t)(a & 0x7fffffff) << 21)); 9512 } else { /* bits 31-30 == '01' */ 9513 f64 = make_float64((0x3fdULL << 52) 9514 | ((uint64_t)(a & 0x3fffffff) << 22)); 9515 } 9516 9517 f64 = recip_sqrt_estimate(f64, fpst); 9518 9519 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff); 9520 } 9521 9522 /* VFPv4 fused multiply-accumulate */ 9523 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp) 9524 { 9525 float_status *fpst = fpstp; 9526 return float32_muladd(a, b, c, 0, fpst); 9527 } 9528 9529 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp) 9530 { 9531 float_status *fpst = fpstp; 9532 return float64_muladd(a, b, c, 0, fpst); 9533 } 9534 9535 /* ARMv8 round to integral */ 9536 float32 HELPER(rints_exact)(float32 x, void *fp_status) 9537 { 9538 return float32_round_to_int(x, fp_status); 9539 } 9540 9541 float64 HELPER(rintd_exact)(float64 x, void *fp_status) 9542 { 9543 return float64_round_to_int(x, fp_status); 9544 } 9545 9546 float32 HELPER(rints)(float32 x, void *fp_status) 9547 { 9548 int old_flags = get_float_exception_flags(fp_status), new_flags; 9549 float32 ret; 9550 9551 ret = float32_round_to_int(x, fp_status); 9552 9553 /* Suppress any inexact exceptions the conversion produced */ 9554 if (!(old_flags & float_flag_inexact)) { 9555 new_flags = get_float_exception_flags(fp_status); 9556 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); 9557 } 9558 9559 return ret; 9560 } 9561 9562 float64 HELPER(rintd)(float64 x, void *fp_status) 9563 { 9564 int old_flags = get_float_exception_flags(fp_status), new_flags; 9565 float64 ret; 9566 9567 ret = float64_round_to_int(x, fp_status); 9568 9569 new_flags = get_float_exception_flags(fp_status); 9570 9571 /* Suppress any inexact exceptions the conversion produced */ 9572 if (!(old_flags & float_flag_inexact)) { 9573 new_flags = get_float_exception_flags(fp_status); 9574 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); 9575 } 9576 9577 return ret; 9578 } 9579 9580 /* Convert ARM rounding mode to softfloat */ 9581 int arm_rmode_to_sf(int rmode) 9582 { 9583 switch (rmode) { 9584 case FPROUNDING_TIEAWAY: 9585 rmode = float_round_ties_away; 9586 break; 9587 case FPROUNDING_ODD: 9588 /* FIXME: add support for TIEAWAY and ODD */ 9589 qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n", 9590 rmode); 9591 case FPROUNDING_TIEEVEN: 9592 default: 9593 rmode = float_round_nearest_even; 9594 break; 9595 case FPROUNDING_POSINF: 9596 rmode = float_round_up; 9597 break; 9598 case FPROUNDING_NEGINF: 9599 rmode = float_round_down; 9600 break; 9601 case FPROUNDING_ZERO: 9602 rmode = float_round_to_zero; 9603 break; 9604 } 9605 return rmode; 9606 } 9607 9608 /* CRC helpers. 9609 * The upper bytes of val (above the number specified by 'bytes') must have 9610 * been zeroed out by the caller. 9611 */ 9612 uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes) 9613 { 9614 uint8_t buf[4]; 9615 9616 stl_le_p(buf, val); 9617 9618 /* zlib crc32 converts the accumulator and output to one's complement. */ 9619 return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff; 9620 } 9621 9622 uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes) 9623 { 9624 uint8_t buf[4]; 9625 9626 stl_le_p(buf, val); 9627 9628 /* Linux crc32c converts the output to one's complement. */ 9629 return crc32c(acc, buf, bytes) ^ 0xffffffff; 9630 } 9631