1 #include "qemu/osdep.h" 2 #include "trace.h" 3 #include "cpu.h" 4 #include "internals.h" 5 #include "exec/gdbstub.h" 6 #include "exec/helper-proto.h" 7 #include "qemu/host-utils.h" 8 #include "sysemu/arch_init.h" 9 #include "sysemu/sysemu.h" 10 #include "qemu/bitops.h" 11 #include "qemu/crc32c.h" 12 #include "exec/exec-all.h" 13 #include "exec/cpu_ldst.h" 14 #include "arm_ldst.h" 15 #include <zlib.h> /* For crc32 */ 16 #include "exec/semihost.h" 17 #include "sysemu/kvm.h" 18 19 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ 20 21 #ifndef CONFIG_USER_ONLY 22 static bool get_phys_addr(CPUARMState *env, target_ulong address, 23 int access_type, ARMMMUIdx mmu_idx, 24 hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, 25 target_ulong *page_size, uint32_t *fsr, 26 ARMMMUFaultInfo *fi); 27 28 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, 29 int access_type, ARMMMUIdx mmu_idx, 30 hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, 31 target_ulong *page_size_ptr, uint32_t *fsr, 32 ARMMMUFaultInfo *fi); 33 34 /* Definitions for the PMCCNTR and PMCR registers */ 35 #define PMCRD 0x8 36 #define PMCRC 0x4 37 #define PMCRE 0x1 38 #endif 39 40 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) 41 { 42 int nregs; 43 44 /* VFP data registers are always little-endian. */ 45 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; 46 if (reg < nregs) { 47 stfq_le_p(buf, env->vfp.regs[reg]); 48 return 8; 49 } 50 if (arm_feature(env, ARM_FEATURE_NEON)) { 51 /* Aliases for Q regs. */ 52 nregs += 16; 53 if (reg < nregs) { 54 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]); 55 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]); 56 return 16; 57 } 58 } 59 switch (reg - nregs) { 60 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4; 61 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4; 62 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4; 63 } 64 return 0; 65 } 66 67 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) 68 { 69 int nregs; 70 71 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; 72 if (reg < nregs) { 73 env->vfp.regs[reg] = ldfq_le_p(buf); 74 return 8; 75 } 76 if (arm_feature(env, ARM_FEATURE_NEON)) { 77 nregs += 16; 78 if (reg < nregs) { 79 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf); 80 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8); 81 return 16; 82 } 83 } 84 switch (reg - nregs) { 85 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4; 86 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4; 87 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4; 88 } 89 return 0; 90 } 91 92 static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) 93 { 94 switch (reg) { 95 case 0 ... 31: 96 /* 128 bit FP register */ 97 stfq_le_p(buf, env->vfp.regs[reg * 2]); 98 stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]); 99 return 16; 100 case 32: 101 /* FPSR */ 102 stl_p(buf, vfp_get_fpsr(env)); 103 return 4; 104 case 33: 105 /* FPCR */ 106 stl_p(buf, vfp_get_fpcr(env)); 107 return 4; 108 default: 109 return 0; 110 } 111 } 112 113 static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) 114 { 115 switch (reg) { 116 case 0 ... 31: 117 /* 128 bit FP register */ 118 env->vfp.regs[reg * 2] = ldfq_le_p(buf); 119 env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8); 120 return 16; 121 case 32: 122 /* FPSR */ 123 vfp_set_fpsr(env, ldl_p(buf)); 124 return 4; 125 case 33: 126 /* FPCR */ 127 vfp_set_fpcr(env, ldl_p(buf)); 128 return 4; 129 default: 130 return 0; 131 } 132 } 133 134 static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) 135 { 136 assert(ri->fieldoffset); 137 if (cpreg_field_is_64bit(ri)) { 138 return CPREG_FIELD64(env, ri); 139 } else { 140 return CPREG_FIELD32(env, ri); 141 } 142 } 143 144 static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, 145 uint64_t value) 146 { 147 assert(ri->fieldoffset); 148 if (cpreg_field_is_64bit(ri)) { 149 CPREG_FIELD64(env, ri) = value; 150 } else { 151 CPREG_FIELD32(env, ri) = value; 152 } 153 } 154 155 static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri) 156 { 157 return (char *)env + ri->fieldoffset; 158 } 159 160 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri) 161 { 162 /* Raw read of a coprocessor register (as needed for migration, etc). */ 163 if (ri->type & ARM_CP_CONST) { 164 return ri->resetvalue; 165 } else if (ri->raw_readfn) { 166 return ri->raw_readfn(env, ri); 167 } else if (ri->readfn) { 168 return ri->readfn(env, ri); 169 } else { 170 return raw_read(env, ri); 171 } 172 } 173 174 static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, 175 uint64_t v) 176 { 177 /* Raw write of a coprocessor register (as needed for migration, etc). 178 * Note that constant registers are treated as write-ignored; the 179 * caller should check for success by whether a readback gives the 180 * value written. 181 */ 182 if (ri->type & ARM_CP_CONST) { 183 return; 184 } else if (ri->raw_writefn) { 185 ri->raw_writefn(env, ri, v); 186 } else if (ri->writefn) { 187 ri->writefn(env, ri, v); 188 } else { 189 raw_write(env, ri, v); 190 } 191 } 192 193 static bool raw_accessors_invalid(const ARMCPRegInfo *ri) 194 { 195 /* Return true if the regdef would cause an assertion if you called 196 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a 197 * program bug for it not to have the NO_RAW flag). 198 * NB that returning false here doesn't necessarily mean that calling 199 * read/write_raw_cp_reg() is safe, because we can't distinguish "has 200 * read/write access functions which are safe for raw use" from "has 201 * read/write access functions which have side effects but has forgotten 202 * to provide raw access functions". 203 * The tests here line up with the conditions in read/write_raw_cp_reg() 204 * and assertions in raw_read()/raw_write(). 205 */ 206 if ((ri->type & ARM_CP_CONST) || 207 ri->fieldoffset || 208 ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) { 209 return false; 210 } 211 return true; 212 } 213 214 bool write_cpustate_to_list(ARMCPU *cpu) 215 { 216 /* Write the coprocessor state from cpu->env to the (index,value) list. */ 217 int i; 218 bool ok = true; 219 220 for (i = 0; i < cpu->cpreg_array_len; i++) { 221 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); 222 const ARMCPRegInfo *ri; 223 224 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); 225 if (!ri) { 226 ok = false; 227 continue; 228 } 229 if (ri->type & ARM_CP_NO_RAW) { 230 continue; 231 } 232 cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri); 233 } 234 return ok; 235 } 236 237 bool write_list_to_cpustate(ARMCPU *cpu) 238 { 239 int i; 240 bool ok = true; 241 242 for (i = 0; i < cpu->cpreg_array_len; i++) { 243 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); 244 uint64_t v = cpu->cpreg_values[i]; 245 const ARMCPRegInfo *ri; 246 247 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); 248 if (!ri) { 249 ok = false; 250 continue; 251 } 252 if (ri->type & ARM_CP_NO_RAW) { 253 continue; 254 } 255 /* Write value and confirm it reads back as written 256 * (to catch read-only registers and partially read-only 257 * registers where the incoming migration value doesn't match) 258 */ 259 write_raw_cp_reg(&cpu->env, ri, v); 260 if (read_raw_cp_reg(&cpu->env, ri) != v) { 261 ok = false; 262 } 263 } 264 return ok; 265 } 266 267 static void add_cpreg_to_list(gpointer key, gpointer opaque) 268 { 269 ARMCPU *cpu = opaque; 270 uint64_t regidx; 271 const ARMCPRegInfo *ri; 272 273 regidx = *(uint32_t *)key; 274 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); 275 276 if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { 277 cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx); 278 /* The value array need not be initialized at this point */ 279 cpu->cpreg_array_len++; 280 } 281 } 282 283 static void count_cpreg(gpointer key, gpointer opaque) 284 { 285 ARMCPU *cpu = opaque; 286 uint64_t regidx; 287 const ARMCPRegInfo *ri; 288 289 regidx = *(uint32_t *)key; 290 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); 291 292 if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { 293 cpu->cpreg_array_len++; 294 } 295 } 296 297 static gint cpreg_key_compare(gconstpointer a, gconstpointer b) 298 { 299 uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a); 300 uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b); 301 302 if (aidx > bidx) { 303 return 1; 304 } 305 if (aidx < bidx) { 306 return -1; 307 } 308 return 0; 309 } 310 311 void init_cpreg_list(ARMCPU *cpu) 312 { 313 /* Initialise the cpreg_tuples[] array based on the cp_regs hash. 314 * Note that we require cpreg_tuples[] to be sorted by key ID. 315 */ 316 GList *keys; 317 int arraylen; 318 319 keys = g_hash_table_get_keys(cpu->cp_regs); 320 keys = g_list_sort(keys, cpreg_key_compare); 321 322 cpu->cpreg_array_len = 0; 323 324 g_list_foreach(keys, count_cpreg, cpu); 325 326 arraylen = cpu->cpreg_array_len; 327 cpu->cpreg_indexes = g_new(uint64_t, arraylen); 328 cpu->cpreg_values = g_new(uint64_t, arraylen); 329 cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen); 330 cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen); 331 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len; 332 cpu->cpreg_array_len = 0; 333 334 g_list_foreach(keys, add_cpreg_to_list, cpu); 335 336 assert(cpu->cpreg_array_len == arraylen); 337 338 g_list_free(keys); 339 } 340 341 /* 342 * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but 343 * they are accessible when EL3 is using AArch64 regardless of EL3.NS. 344 * 345 * access_el3_aa32ns: Used to check AArch32 register views. 346 * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views. 347 */ 348 static CPAccessResult access_el3_aa32ns(CPUARMState *env, 349 const ARMCPRegInfo *ri, 350 bool isread) 351 { 352 bool secure = arm_is_secure_below_el3(env); 353 354 assert(!arm_el_is_aa64(env, 3)); 355 if (secure) { 356 return CP_ACCESS_TRAP_UNCATEGORIZED; 357 } 358 return CP_ACCESS_OK; 359 } 360 361 static CPAccessResult access_el3_aa32ns_aa64any(CPUARMState *env, 362 const ARMCPRegInfo *ri, 363 bool isread) 364 { 365 if (!arm_el_is_aa64(env, 3)) { 366 return access_el3_aa32ns(env, ri, isread); 367 } 368 return CP_ACCESS_OK; 369 } 370 371 /* Some secure-only AArch32 registers trap to EL3 if used from 372 * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts). 373 * Note that an access from Secure EL1 can only happen if EL3 is AArch64. 374 * We assume that the .access field is set to PL1_RW. 375 */ 376 static CPAccessResult access_trap_aa32s_el1(CPUARMState *env, 377 const ARMCPRegInfo *ri, 378 bool isread) 379 { 380 if (arm_current_el(env) == 3) { 381 return CP_ACCESS_OK; 382 } 383 if (arm_is_secure_below_el3(env)) { 384 return CP_ACCESS_TRAP_EL3; 385 } 386 /* This will be EL1 NS and EL2 NS, which just UNDEF */ 387 return CP_ACCESS_TRAP_UNCATEGORIZED; 388 } 389 390 /* Check for traps to "powerdown debug" registers, which are controlled 391 * by MDCR.TDOSA 392 */ 393 static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *ri, 394 bool isread) 395 { 396 int el = arm_current_el(env); 397 398 if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDOSA) 399 && !arm_is_secure_below_el3(env)) { 400 return CP_ACCESS_TRAP_EL2; 401 } 402 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDOSA)) { 403 return CP_ACCESS_TRAP_EL3; 404 } 405 return CP_ACCESS_OK; 406 } 407 408 /* Check for traps to "debug ROM" registers, which are controlled 409 * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3. 410 */ 411 static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri, 412 bool isread) 413 { 414 int el = arm_current_el(env); 415 416 if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDRA) 417 && !arm_is_secure_below_el3(env)) { 418 return CP_ACCESS_TRAP_EL2; 419 } 420 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { 421 return CP_ACCESS_TRAP_EL3; 422 } 423 return CP_ACCESS_OK; 424 } 425 426 /* Check for traps to general debug registers, which are controlled 427 * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3. 428 */ 429 static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri, 430 bool isread) 431 { 432 int el = arm_current_el(env); 433 434 if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDA) 435 && !arm_is_secure_below_el3(env)) { 436 return CP_ACCESS_TRAP_EL2; 437 } 438 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { 439 return CP_ACCESS_TRAP_EL3; 440 } 441 return CP_ACCESS_OK; 442 } 443 444 /* Check for traps to performance monitor registers, which are controlled 445 * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3. 446 */ 447 static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri, 448 bool isread) 449 { 450 int el = arm_current_el(env); 451 452 if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM) 453 && !arm_is_secure_below_el3(env)) { 454 return CP_ACCESS_TRAP_EL2; 455 } 456 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { 457 return CP_ACCESS_TRAP_EL3; 458 } 459 return CP_ACCESS_OK; 460 } 461 462 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) 463 { 464 ARMCPU *cpu = arm_env_get_cpu(env); 465 466 raw_write(env, ri, value); 467 tlb_flush(CPU(cpu)); /* Flush TLB as domain not tracked in TLB */ 468 } 469 470 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) 471 { 472 ARMCPU *cpu = arm_env_get_cpu(env); 473 474 if (raw_read(env, ri) != value) { 475 /* Unlike real hardware the qemu TLB uses virtual addresses, 476 * not modified virtual addresses, so this causes a TLB flush. 477 */ 478 tlb_flush(CPU(cpu)); 479 raw_write(env, ri, value); 480 } 481 } 482 483 static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, 484 uint64_t value) 485 { 486 ARMCPU *cpu = arm_env_get_cpu(env); 487 488 if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_PMSA) 489 && !extended_addresses_enabled(env)) { 490 /* For VMSA (when not using the LPAE long descriptor page table 491 * format) this register includes the ASID, so do a TLB flush. 492 * For PMSA it is purely a process ID and no action is needed. 493 */ 494 tlb_flush(CPU(cpu)); 495 } 496 raw_write(env, ri, value); 497 } 498 499 static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, 500 uint64_t value) 501 { 502 /* Invalidate all (TLBIALL) */ 503 ARMCPU *cpu = arm_env_get_cpu(env); 504 505 tlb_flush(CPU(cpu)); 506 } 507 508 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, 509 uint64_t value) 510 { 511 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ 512 ARMCPU *cpu = arm_env_get_cpu(env); 513 514 tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); 515 } 516 517 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, 518 uint64_t value) 519 { 520 /* Invalidate by ASID (TLBIASID) */ 521 ARMCPU *cpu = arm_env_get_cpu(env); 522 523 tlb_flush(CPU(cpu)); 524 } 525 526 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, 527 uint64_t value) 528 { 529 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ 530 ARMCPU *cpu = arm_env_get_cpu(env); 531 532 tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); 533 } 534 535 /* IS variants of TLB operations must affect all cores */ 536 static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 537 uint64_t value) 538 { 539 CPUState *cs = ENV_GET_CPU(env); 540 541 tlb_flush_all_cpus_synced(cs); 542 } 543 544 static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 545 uint64_t value) 546 { 547 CPUState *cs = ENV_GET_CPU(env); 548 549 tlb_flush_all_cpus_synced(cs); 550 } 551 552 static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 553 uint64_t value) 554 { 555 CPUState *cs = ENV_GET_CPU(env); 556 557 tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); 558 } 559 560 static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 561 uint64_t value) 562 { 563 CPUState *cs = ENV_GET_CPU(env); 564 565 tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); 566 } 567 568 static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri, 569 uint64_t value) 570 { 571 CPUState *cs = ENV_GET_CPU(env); 572 573 tlb_flush_by_mmuidx(cs, 574 ARMMMUIdxBit_S12NSE1 | 575 ARMMMUIdxBit_S12NSE0 | 576 ARMMMUIdxBit_S2NS); 577 } 578 579 static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 580 uint64_t value) 581 { 582 CPUState *cs = ENV_GET_CPU(env); 583 584 tlb_flush_by_mmuidx_all_cpus_synced(cs, 585 ARMMMUIdxBit_S12NSE1 | 586 ARMMMUIdxBit_S12NSE0 | 587 ARMMMUIdxBit_S2NS); 588 } 589 590 static void tlbiipas2_write(CPUARMState *env, const ARMCPRegInfo *ri, 591 uint64_t value) 592 { 593 /* Invalidate by IPA. This has to invalidate any structures that 594 * contain only stage 2 translation information, but does not need 595 * to apply to structures that contain combined stage 1 and stage 2 596 * translation information. 597 * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero. 598 */ 599 CPUState *cs = ENV_GET_CPU(env); 600 uint64_t pageaddr; 601 602 if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { 603 return; 604 } 605 606 pageaddr = sextract64(value << 12, 0, 40); 607 608 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S2NS); 609 } 610 611 static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 612 uint64_t value) 613 { 614 CPUState *cs = ENV_GET_CPU(env); 615 uint64_t pageaddr; 616 617 if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { 618 return; 619 } 620 621 pageaddr = sextract64(value << 12, 0, 40); 622 623 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, 624 ARMMMUIdxBit_S2NS); 625 } 626 627 static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, 628 uint64_t value) 629 { 630 CPUState *cs = ENV_GET_CPU(env); 631 632 tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2); 633 } 634 635 static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 636 uint64_t value) 637 { 638 CPUState *cs = ENV_GET_CPU(env); 639 640 tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2); 641 } 642 643 static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, 644 uint64_t value) 645 { 646 CPUState *cs = ENV_GET_CPU(env); 647 uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12); 648 649 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2); 650 } 651 652 static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 653 uint64_t value) 654 { 655 CPUState *cs = ENV_GET_CPU(env); 656 uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12); 657 658 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, 659 ARMMMUIdxBit_S1E2); 660 } 661 662 static const ARMCPRegInfo cp_reginfo[] = { 663 /* Define the secure and non-secure FCSE identifier CP registers 664 * separately because there is no secure bank in V8 (no _EL3). This allows 665 * the secure register to be properly reset and migrated. There is also no 666 * v8 EL1 version of the register so the non-secure instance stands alone. 667 */ 668 { .name = "FCSEIDR(NS)", 669 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0, 670 .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS, 671 .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_ns), 672 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, 673 { .name = "FCSEIDR(S)", 674 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0, 675 .access = PL1_RW, .secure = ARM_CP_SECSTATE_S, 676 .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s), 677 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, 678 /* Define the secure and non-secure context identifier CP registers 679 * separately because there is no secure bank in V8 (no _EL3). This allows 680 * the secure register to be properly reset and migrated. In the 681 * non-secure case, the 32-bit register will have reset and migration 682 * disabled during registration as it is handled by the 64-bit instance. 683 */ 684 { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH, 685 .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, 686 .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS, 687 .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]), 688 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, 689 { .name = "CONTEXTIDR(S)", .state = ARM_CP_STATE_AA32, 690 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, 691 .access = PL1_RW, .secure = ARM_CP_SECSTATE_S, 692 .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s), 693 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, 694 REGINFO_SENTINEL 695 }; 696 697 static const ARMCPRegInfo not_v8_cp_reginfo[] = { 698 /* NB: Some of these registers exist in v8 but with more precise 699 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]). 700 */ 701 /* MMU Domain access control / MPU write buffer control */ 702 { .name = "DACR", 703 .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY, 704 .access = PL1_RW, .resetvalue = 0, 705 .writefn = dacr_write, .raw_writefn = raw_write, 706 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s), 707 offsetoflow32(CPUARMState, cp15.dacr_ns) } }, 708 /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs. 709 * For v6 and v5, these mappings are overly broad. 710 */ 711 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 0, 712 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, 713 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 1, 714 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, 715 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 4, 716 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, 717 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 8, 718 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, 719 /* Cache maintenance ops; some of this space may be overridden later. */ 720 { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, 721 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, 722 .type = ARM_CP_NOP | ARM_CP_OVERRIDE }, 723 REGINFO_SENTINEL 724 }; 725 726 static const ARMCPRegInfo not_v6_cp_reginfo[] = { 727 /* Not all pre-v6 cores implemented this WFI, so this is slightly 728 * over-broad. 729 */ 730 { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2, 731 .access = PL1_W, .type = ARM_CP_WFI }, 732 REGINFO_SENTINEL 733 }; 734 735 static const ARMCPRegInfo not_v7_cp_reginfo[] = { 736 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which 737 * is UNPREDICTABLE; we choose to NOP as most implementations do). 738 */ 739 { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, 740 .access = PL1_W, .type = ARM_CP_WFI }, 741 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice 742 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and 743 * OMAPCP will override this space. 744 */ 745 { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0, 746 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data), 747 .resetvalue = 0 }, 748 { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1, 749 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn), 750 .resetvalue = 0 }, 751 /* v6 doesn't have the cache ID registers but Linux reads them anyway */ 752 { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY, 753 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, 754 .resetvalue = 0 }, 755 /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR; 756 * implementing it as RAZ means the "debug architecture version" bits 757 * will read as a reserved value, which should cause Linux to not try 758 * to use the debug hardware. 759 */ 760 { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, 761 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 762 /* MMU TLB control. Note that the wildcarding means we cover not just 763 * the unified TLB ops but also the dside/iside/inner-shareable variants. 764 */ 765 { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY, 766 .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write, 767 .type = ARM_CP_NO_RAW }, 768 { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY, 769 .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write, 770 .type = ARM_CP_NO_RAW }, 771 { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY, 772 .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write, 773 .type = ARM_CP_NO_RAW }, 774 { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY, 775 .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write, 776 .type = ARM_CP_NO_RAW }, 777 { .name = "PRRR", .cp = 15, .crn = 10, .crm = 2, 778 .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP }, 779 { .name = "NMRR", .cp = 15, .crn = 10, .crm = 2, 780 .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP }, 781 REGINFO_SENTINEL 782 }; 783 784 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, 785 uint64_t value) 786 { 787 uint32_t mask = 0; 788 789 /* In ARMv8 most bits of CPACR_EL1 are RES0. */ 790 if (!arm_feature(env, ARM_FEATURE_V8)) { 791 /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI. 792 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP. 793 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell. 794 */ 795 if (arm_feature(env, ARM_FEATURE_VFP)) { 796 /* VFP coprocessor: cp10 & cp11 [23:20] */ 797 mask |= (1 << 31) | (1 << 30) | (0xf << 20); 798 799 if (!arm_feature(env, ARM_FEATURE_NEON)) { 800 /* ASEDIS [31] bit is RAO/WI */ 801 value |= (1 << 31); 802 } 803 804 /* VFPv3 and upwards with NEON implement 32 double precision 805 * registers (D0-D31). 806 */ 807 if (!arm_feature(env, ARM_FEATURE_NEON) || 808 !arm_feature(env, ARM_FEATURE_VFP3)) { 809 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */ 810 value |= (1 << 30); 811 } 812 } 813 value &= mask; 814 } 815 env->cp15.cpacr_el1 = value; 816 } 817 818 static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri, 819 bool isread) 820 { 821 if (arm_feature(env, ARM_FEATURE_V8)) { 822 /* Check if CPACR accesses are to be trapped to EL2 */ 823 if (arm_current_el(env) == 1 && 824 (env->cp15.cptr_el[2] & CPTR_TCPAC) && !arm_is_secure(env)) { 825 return CP_ACCESS_TRAP_EL2; 826 /* Check if CPACR accesses are to be trapped to EL3 */ 827 } else if (arm_current_el(env) < 3 && 828 (env->cp15.cptr_el[3] & CPTR_TCPAC)) { 829 return CP_ACCESS_TRAP_EL3; 830 } 831 } 832 833 return CP_ACCESS_OK; 834 } 835 836 static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri, 837 bool isread) 838 { 839 /* Check if CPTR accesses are set to trap to EL3 */ 840 if (arm_current_el(env) == 2 && (env->cp15.cptr_el[3] & CPTR_TCPAC)) { 841 return CP_ACCESS_TRAP_EL3; 842 } 843 844 return CP_ACCESS_OK; 845 } 846 847 static const ARMCPRegInfo v6_cp_reginfo[] = { 848 /* prefetch by MVA in v6, NOP in v7 */ 849 { .name = "MVA_prefetch", 850 .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1, 851 .access = PL1_W, .type = ARM_CP_NOP }, 852 /* We need to break the TB after ISB to execute self-modifying code 853 * correctly and also to take any pending interrupts immediately. 854 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag. 855 */ 856 { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4, 857 .access = PL0_W, .type = ARM_CP_NO_RAW, .writefn = arm_cp_write_ignore }, 858 { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4, 859 .access = PL0_W, .type = ARM_CP_NOP }, 860 { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5, 861 .access = PL0_W, .type = ARM_CP_NOP }, 862 { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2, 863 .access = PL1_RW, 864 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s), 865 offsetof(CPUARMState, cp15.ifar_ns) }, 866 .resetvalue = 0, }, 867 /* Watchpoint Fault Address Register : should actually only be present 868 * for 1136, 1176, 11MPCore. 869 */ 870 { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, 871 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, }, 872 { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, 873 .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access, 874 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1), 875 .resetvalue = 0, .writefn = cpacr_write }, 876 REGINFO_SENTINEL 877 }; 878 879 static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri, 880 bool isread) 881 { 882 /* Performance monitor registers user accessibility is controlled 883 * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable 884 * trapping to EL2 or EL3 for other accesses. 885 */ 886 int el = arm_current_el(env); 887 888 if (el == 0 && !(env->cp15.c9_pmuserenr & 1)) { 889 return CP_ACCESS_TRAP; 890 } 891 if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM) 892 && !arm_is_secure_below_el3(env)) { 893 return CP_ACCESS_TRAP_EL2; 894 } 895 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { 896 return CP_ACCESS_TRAP_EL3; 897 } 898 899 return CP_ACCESS_OK; 900 } 901 902 static CPAccessResult pmreg_access_xevcntr(CPUARMState *env, 903 const ARMCPRegInfo *ri, 904 bool isread) 905 { 906 /* ER: event counter read trap control */ 907 if (arm_feature(env, ARM_FEATURE_V8) 908 && arm_current_el(env) == 0 909 && (env->cp15.c9_pmuserenr & (1 << 3)) != 0 910 && isread) { 911 return CP_ACCESS_OK; 912 } 913 914 return pmreg_access(env, ri, isread); 915 } 916 917 static CPAccessResult pmreg_access_swinc(CPUARMState *env, 918 const ARMCPRegInfo *ri, 919 bool isread) 920 { 921 /* SW: software increment write trap control */ 922 if (arm_feature(env, ARM_FEATURE_V8) 923 && arm_current_el(env) == 0 924 && (env->cp15.c9_pmuserenr & (1 << 1)) != 0 925 && !isread) { 926 return CP_ACCESS_OK; 927 } 928 929 return pmreg_access(env, ri, isread); 930 } 931 932 #ifndef CONFIG_USER_ONLY 933 934 static CPAccessResult pmreg_access_selr(CPUARMState *env, 935 const ARMCPRegInfo *ri, 936 bool isread) 937 { 938 /* ER: event counter read trap control */ 939 if (arm_feature(env, ARM_FEATURE_V8) 940 && arm_current_el(env) == 0 941 && (env->cp15.c9_pmuserenr & (1 << 3)) != 0) { 942 return CP_ACCESS_OK; 943 } 944 945 return pmreg_access(env, ri, isread); 946 } 947 948 static CPAccessResult pmreg_access_ccntr(CPUARMState *env, 949 const ARMCPRegInfo *ri, 950 bool isread) 951 { 952 /* CR: cycle counter read trap control */ 953 if (arm_feature(env, ARM_FEATURE_V8) 954 && arm_current_el(env) == 0 955 && (env->cp15.c9_pmuserenr & (1 << 2)) != 0 956 && isread) { 957 return CP_ACCESS_OK; 958 } 959 960 return pmreg_access(env, ri, isread); 961 } 962 963 static inline bool arm_ccnt_enabled(CPUARMState *env) 964 { 965 /* This does not support checking PMCCFILTR_EL0 register */ 966 967 if (!(env->cp15.c9_pmcr & PMCRE)) { 968 return false; 969 } 970 971 return true; 972 } 973 974 void pmccntr_sync(CPUARMState *env) 975 { 976 uint64_t temp_ticks; 977 978 temp_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 979 ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); 980 981 if (env->cp15.c9_pmcr & PMCRD) { 982 /* Increment once every 64 processor clock cycles */ 983 temp_ticks /= 64; 984 } 985 986 if (arm_ccnt_enabled(env)) { 987 env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt; 988 } 989 } 990 991 static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, 992 uint64_t value) 993 { 994 pmccntr_sync(env); 995 996 if (value & PMCRC) { 997 /* The counter has been reset */ 998 env->cp15.c15_ccnt = 0; 999 } 1000 1001 /* only the DP, X, D and E bits are writable */ 1002 env->cp15.c9_pmcr &= ~0x39; 1003 env->cp15.c9_pmcr |= (value & 0x39); 1004 1005 pmccntr_sync(env); 1006 } 1007 1008 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1009 { 1010 uint64_t total_ticks; 1011 1012 if (!arm_ccnt_enabled(env)) { 1013 /* Counter is disabled, do not change value */ 1014 return env->cp15.c15_ccnt; 1015 } 1016 1017 total_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 1018 ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); 1019 1020 if (env->cp15.c9_pmcr & PMCRD) { 1021 /* Increment once every 64 processor clock cycles */ 1022 total_ticks /= 64; 1023 } 1024 return total_ticks - env->cp15.c15_ccnt; 1025 } 1026 1027 static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1028 uint64_t value) 1029 { 1030 /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and 1031 * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the 1032 * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are 1033 * accessed. 1034 */ 1035 env->cp15.c9_pmselr = value & 0x1f; 1036 } 1037 1038 static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1039 uint64_t value) 1040 { 1041 uint64_t total_ticks; 1042 1043 if (!arm_ccnt_enabled(env)) { 1044 /* Counter is disabled, set the absolute value */ 1045 env->cp15.c15_ccnt = value; 1046 return; 1047 } 1048 1049 total_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 1050 ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); 1051 1052 if (env->cp15.c9_pmcr & PMCRD) { 1053 /* Increment once every 64 processor clock cycles */ 1054 total_ticks /= 64; 1055 } 1056 env->cp15.c15_ccnt = total_ticks - value; 1057 } 1058 1059 static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri, 1060 uint64_t value) 1061 { 1062 uint64_t cur_val = pmccntr_read(env, NULL); 1063 1064 pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value)); 1065 } 1066 1067 #else /* CONFIG_USER_ONLY */ 1068 1069 void pmccntr_sync(CPUARMState *env) 1070 { 1071 } 1072 1073 #endif 1074 1075 static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1076 uint64_t value) 1077 { 1078 pmccntr_sync(env); 1079 env->cp15.pmccfiltr_el0 = value & 0x7E000000; 1080 pmccntr_sync(env); 1081 } 1082 1083 static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, 1084 uint64_t value) 1085 { 1086 value &= (1 << 31); 1087 env->cp15.c9_pmcnten |= value; 1088 } 1089 1090 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1091 uint64_t value) 1092 { 1093 value &= (1 << 31); 1094 env->cp15.c9_pmcnten &= ~value; 1095 } 1096 1097 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1098 uint64_t value) 1099 { 1100 env->cp15.c9_pmovsr &= ~value; 1101 } 1102 1103 static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, 1104 uint64_t value) 1105 { 1106 /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when 1107 * PMSELR value is equal to or greater than the number of implemented 1108 * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI. 1109 */ 1110 if (env->cp15.c9_pmselr == 0x1f) { 1111 pmccfiltr_write(env, ri, value); 1112 } 1113 } 1114 1115 static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri) 1116 { 1117 /* We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER 1118 * are CONSTRAINED UNPREDICTABLE. See comments in pmxevtyper_write(). 1119 */ 1120 if (env->cp15.c9_pmselr == 0x1f) { 1121 return env->cp15.pmccfiltr_el0; 1122 } else { 1123 return 0; 1124 } 1125 } 1126 1127 static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1128 uint64_t value) 1129 { 1130 if (arm_feature(env, ARM_FEATURE_V8)) { 1131 env->cp15.c9_pmuserenr = value & 0xf; 1132 } else { 1133 env->cp15.c9_pmuserenr = value & 1; 1134 } 1135 } 1136 1137 static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri, 1138 uint64_t value) 1139 { 1140 /* We have no event counters so only the C bit can be changed */ 1141 value &= (1 << 31); 1142 env->cp15.c9_pminten |= value; 1143 } 1144 1145 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1146 uint64_t value) 1147 { 1148 value &= (1 << 31); 1149 env->cp15.c9_pminten &= ~value; 1150 } 1151 1152 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, 1153 uint64_t value) 1154 { 1155 /* Note that even though the AArch64 view of this register has bits 1156 * [10:0] all RES0 we can only mask the bottom 5, to comply with the 1157 * architectural requirements for bits which are RES0 only in some 1158 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7 1159 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.) 1160 */ 1161 raw_write(env, ri, value & ~0x1FULL); 1162 } 1163 1164 static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) 1165 { 1166 /* We only mask off bits that are RES0 both for AArch64 and AArch32. 1167 * For bits that vary between AArch32/64, code needs to check the 1168 * current execution mode before directly using the feature bit. 1169 */ 1170 uint32_t valid_mask = SCR_AARCH64_MASK | SCR_AARCH32_MASK; 1171 1172 if (!arm_feature(env, ARM_FEATURE_EL2)) { 1173 valid_mask &= ~SCR_HCE; 1174 1175 /* On ARMv7, SMD (or SCD as it is called in v7) is only 1176 * supported if EL2 exists. The bit is UNK/SBZP when 1177 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero 1178 * when EL2 is unavailable. 1179 * On ARMv8, this bit is always available. 1180 */ 1181 if (arm_feature(env, ARM_FEATURE_V7) && 1182 !arm_feature(env, ARM_FEATURE_V8)) { 1183 valid_mask &= ~SCR_SMD; 1184 } 1185 } 1186 1187 /* Clear all-context RES0 bits. */ 1188 value &= valid_mask; 1189 raw_write(env, ri, value); 1190 } 1191 1192 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1193 { 1194 ARMCPU *cpu = arm_env_get_cpu(env); 1195 1196 /* Acquire the CSSELR index from the bank corresponding to the CCSIDR 1197 * bank 1198 */ 1199 uint32_t index = A32_BANKED_REG_GET(env, csselr, 1200 ri->secure & ARM_CP_SECSTATE_S); 1201 1202 return cpu->ccsidr[index]; 1203 } 1204 1205 static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1206 uint64_t value) 1207 { 1208 raw_write(env, ri, value & 0xf); 1209 } 1210 1211 static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1212 { 1213 CPUState *cs = ENV_GET_CPU(env); 1214 uint64_t ret = 0; 1215 1216 if (cs->interrupt_request & CPU_INTERRUPT_HARD) { 1217 ret |= CPSR_I; 1218 } 1219 if (cs->interrupt_request & CPU_INTERRUPT_FIQ) { 1220 ret |= CPSR_F; 1221 } 1222 /* External aborts are not possible in QEMU so A bit is always clear */ 1223 return ret; 1224 } 1225 1226 static const ARMCPRegInfo v7_cp_reginfo[] = { 1227 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */ 1228 { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, 1229 .access = PL1_W, .type = ARM_CP_NOP }, 1230 /* Performance monitors are implementation defined in v7, 1231 * but with an ARM recommended set of registers, which we 1232 * follow (although we don't actually implement any counters) 1233 * 1234 * Performance registers fall into three categories: 1235 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR) 1236 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR) 1237 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others) 1238 * For the cases controlled by PMUSERENR we must set .access to PL0_RW 1239 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn. 1240 */ 1241 { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1, 1242 .access = PL0_RW, .type = ARM_CP_ALIAS, 1243 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), 1244 .writefn = pmcntenset_write, 1245 .accessfn = pmreg_access, 1246 .raw_writefn = raw_write }, 1247 { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64, 1248 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1, 1249 .access = PL0_RW, .accessfn = pmreg_access, 1250 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0, 1251 .writefn = pmcntenset_write, .raw_writefn = raw_write }, 1252 { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2, 1253 .access = PL0_RW, 1254 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), 1255 .accessfn = pmreg_access, 1256 .writefn = pmcntenclr_write, 1257 .type = ARM_CP_ALIAS }, 1258 { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64, 1259 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2, 1260 .access = PL0_RW, .accessfn = pmreg_access, 1261 .type = ARM_CP_ALIAS, 1262 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), 1263 .writefn = pmcntenclr_write }, 1264 { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3, 1265 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), 1266 .accessfn = pmreg_access, 1267 .writefn = pmovsr_write, 1268 .raw_writefn = raw_write }, 1269 { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64, 1270 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3, 1271 .access = PL0_RW, .accessfn = pmreg_access, 1272 .type = ARM_CP_ALIAS, 1273 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), 1274 .writefn = pmovsr_write, 1275 .raw_writefn = raw_write }, 1276 /* Unimplemented so WI. */ 1277 { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4, 1278 .access = PL0_W, .accessfn = pmreg_access_swinc, .type = ARM_CP_NOP }, 1279 #ifndef CONFIG_USER_ONLY 1280 { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5, 1281 .access = PL0_RW, .type = ARM_CP_ALIAS, 1282 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr), 1283 .accessfn = pmreg_access_selr, .writefn = pmselr_write, 1284 .raw_writefn = raw_write}, 1285 { .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64, 1286 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 5, 1287 .access = PL0_RW, .accessfn = pmreg_access_selr, 1288 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr), 1289 .writefn = pmselr_write, .raw_writefn = raw_write, }, 1290 { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0, 1291 .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO, 1292 .readfn = pmccntr_read, .writefn = pmccntr_write32, 1293 .accessfn = pmreg_access_ccntr }, 1294 { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64, 1295 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0, 1296 .access = PL0_RW, .accessfn = pmreg_access_ccntr, 1297 .type = ARM_CP_IO, 1298 .readfn = pmccntr_read, .writefn = pmccntr_write, }, 1299 #endif 1300 { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64, 1301 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7, 1302 .writefn = pmccfiltr_write, 1303 .access = PL0_RW, .accessfn = pmreg_access, 1304 .type = ARM_CP_IO, 1305 .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0), 1306 .resetvalue = 0, }, 1307 { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1, 1308 .access = PL0_RW, .type = ARM_CP_NO_RAW, .accessfn = pmreg_access, 1309 .writefn = pmxevtyper_write, .readfn = pmxevtyper_read }, 1310 { .name = "PMXEVTYPER_EL0", .state = ARM_CP_STATE_AA64, 1311 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 1, 1312 .access = PL0_RW, .type = ARM_CP_NO_RAW, .accessfn = pmreg_access, 1313 .writefn = pmxevtyper_write, .readfn = pmxevtyper_read }, 1314 /* Unimplemented, RAZ/WI. */ 1315 { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2, 1316 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0, 1317 .accessfn = pmreg_access_xevcntr }, 1318 { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0, 1319 .access = PL0_R | PL1_RW, .accessfn = access_tpm, 1320 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr), 1321 .resetvalue = 0, 1322 .writefn = pmuserenr_write, .raw_writefn = raw_write }, 1323 { .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64, 1324 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 0, 1325 .access = PL0_R | PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS, 1326 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr), 1327 .resetvalue = 0, 1328 .writefn = pmuserenr_write, .raw_writefn = raw_write }, 1329 { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1, 1330 .access = PL1_RW, .accessfn = access_tpm, 1331 .type = ARM_CP_ALIAS, 1332 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pminten), 1333 .resetvalue = 0, 1334 .writefn = pmintenset_write, .raw_writefn = raw_write }, 1335 { .name = "PMINTENSET_EL1", .state = ARM_CP_STATE_AA64, 1336 .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 1, 1337 .access = PL1_RW, .accessfn = access_tpm, 1338 .type = ARM_CP_IO, 1339 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), 1340 .writefn = pmintenset_write, .raw_writefn = raw_write, 1341 .resetvalue = 0x0 }, 1342 { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2, 1343 .access = PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS, 1344 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), 1345 .writefn = pmintenclr_write, }, 1346 { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64, 1347 .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2, 1348 .access = PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS, 1349 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), 1350 .writefn = pmintenclr_write }, 1351 { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, 1352 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, 1353 .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_RAW }, 1354 { .name = "CSSELR", .state = ARM_CP_STATE_BOTH, 1355 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0, 1356 .access = PL1_RW, .writefn = csselr_write, .resetvalue = 0, 1357 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s), 1358 offsetof(CPUARMState, cp15.csselr_ns) } }, 1359 /* Auxiliary ID register: this actually has an IMPDEF value but for now 1360 * just RAZ for all cores: 1361 */ 1362 { .name = "AIDR", .state = ARM_CP_STATE_BOTH, 1363 .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7, 1364 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 1365 /* Auxiliary fault status registers: these also are IMPDEF, and we 1366 * choose to RAZ/WI for all cores. 1367 */ 1368 { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH, 1369 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0, 1370 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1371 { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH, 1372 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1, 1373 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1374 /* MAIR can just read-as-written because we don't implement caches 1375 * and so don't need to care about memory attributes. 1376 */ 1377 { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64, 1378 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, 1379 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]), 1380 .resetvalue = 0 }, 1381 { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64, 1382 .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0, 1383 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]), 1384 .resetvalue = 0 }, 1385 /* For non-long-descriptor page tables these are PRRR and NMRR; 1386 * regardless they still act as reads-as-written for QEMU. 1387 */ 1388 /* MAIR0/1 are defined separately from their 64-bit counterpart which 1389 * allows them to assign the correct fieldoffset based on the endianness 1390 * handled in the field definitions. 1391 */ 1392 { .name = "MAIR0", .state = ARM_CP_STATE_AA32, 1393 .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW, 1394 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s), 1395 offsetof(CPUARMState, cp15.mair0_ns) }, 1396 .resetfn = arm_cp_reset_ignore }, 1397 { .name = "MAIR1", .state = ARM_CP_STATE_AA32, 1398 .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW, 1399 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s), 1400 offsetof(CPUARMState, cp15.mair1_ns) }, 1401 .resetfn = arm_cp_reset_ignore }, 1402 { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH, 1403 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0, 1404 .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read }, 1405 /* 32 bit ITLB invalidates */ 1406 { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0, 1407 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write }, 1408 { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1, 1409 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, 1410 { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2, 1411 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write }, 1412 /* 32 bit DTLB invalidates */ 1413 { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0, 1414 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write }, 1415 { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1, 1416 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, 1417 { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2, 1418 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write }, 1419 /* 32 bit TLB invalidates */ 1420 { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, 1421 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write }, 1422 { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, 1423 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, 1424 { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, 1425 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write }, 1426 { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, 1427 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write }, 1428 REGINFO_SENTINEL 1429 }; 1430 1431 static const ARMCPRegInfo v7mp_cp_reginfo[] = { 1432 /* 32 bit TLB invalidates, Inner Shareable */ 1433 { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, 1434 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_is_write }, 1435 { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, 1436 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write }, 1437 { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, 1438 .type = ARM_CP_NO_RAW, .access = PL1_W, 1439 .writefn = tlbiasid_is_write }, 1440 { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, 1441 .type = ARM_CP_NO_RAW, .access = PL1_W, 1442 .writefn = tlbimvaa_is_write }, 1443 REGINFO_SENTINEL 1444 }; 1445 1446 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1447 uint64_t value) 1448 { 1449 value &= 1; 1450 env->teecr = value; 1451 } 1452 1453 static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri, 1454 bool isread) 1455 { 1456 if (arm_current_el(env) == 0 && (env->teecr & 1)) { 1457 return CP_ACCESS_TRAP; 1458 } 1459 return CP_ACCESS_OK; 1460 } 1461 1462 static const ARMCPRegInfo t2ee_cp_reginfo[] = { 1463 { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0, 1464 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr), 1465 .resetvalue = 0, 1466 .writefn = teecr_write }, 1467 { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0, 1468 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr), 1469 .accessfn = teehbr_access, .resetvalue = 0 }, 1470 REGINFO_SENTINEL 1471 }; 1472 1473 static const ARMCPRegInfo v6k_cp_reginfo[] = { 1474 { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64, 1475 .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0, 1476 .access = PL0_RW, 1477 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 }, 1478 { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2, 1479 .access = PL0_RW, 1480 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s), 1481 offsetoflow32(CPUARMState, cp15.tpidrurw_ns) }, 1482 .resetfn = arm_cp_reset_ignore }, 1483 { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64, 1484 .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0, 1485 .access = PL0_R|PL1_W, 1486 .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]), 1487 .resetvalue = 0}, 1488 { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3, 1489 .access = PL0_R|PL1_W, 1490 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s), 1491 offsetoflow32(CPUARMState, cp15.tpidruro_ns) }, 1492 .resetfn = arm_cp_reset_ignore }, 1493 { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64, 1494 .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0, 1495 .access = PL1_RW, 1496 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 }, 1497 { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4, 1498 .access = PL1_RW, 1499 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s), 1500 offsetoflow32(CPUARMState, cp15.tpidrprw_ns) }, 1501 .resetvalue = 0 }, 1502 REGINFO_SENTINEL 1503 }; 1504 1505 #ifndef CONFIG_USER_ONLY 1506 1507 static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri, 1508 bool isread) 1509 { 1510 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero. 1511 * Writable only at the highest implemented exception level. 1512 */ 1513 int el = arm_current_el(env); 1514 1515 switch (el) { 1516 case 0: 1517 if (!extract32(env->cp15.c14_cntkctl, 0, 2)) { 1518 return CP_ACCESS_TRAP; 1519 } 1520 break; 1521 case 1: 1522 if (!isread && ri->state == ARM_CP_STATE_AA32 && 1523 arm_is_secure_below_el3(env)) { 1524 /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */ 1525 return CP_ACCESS_TRAP_UNCATEGORIZED; 1526 } 1527 break; 1528 case 2: 1529 case 3: 1530 break; 1531 } 1532 1533 if (!isread && el < arm_highest_el(env)) { 1534 return CP_ACCESS_TRAP_UNCATEGORIZED; 1535 } 1536 1537 return CP_ACCESS_OK; 1538 } 1539 1540 static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx, 1541 bool isread) 1542 { 1543 unsigned int cur_el = arm_current_el(env); 1544 bool secure = arm_is_secure(env); 1545 1546 /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */ 1547 if (cur_el == 0 && 1548 !extract32(env->cp15.c14_cntkctl, timeridx, 1)) { 1549 return CP_ACCESS_TRAP; 1550 } 1551 1552 if (arm_feature(env, ARM_FEATURE_EL2) && 1553 timeridx == GTIMER_PHYS && !secure && cur_el < 2 && 1554 !extract32(env->cp15.cnthctl_el2, 0, 1)) { 1555 return CP_ACCESS_TRAP_EL2; 1556 } 1557 return CP_ACCESS_OK; 1558 } 1559 1560 static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx, 1561 bool isread) 1562 { 1563 unsigned int cur_el = arm_current_el(env); 1564 bool secure = arm_is_secure(env); 1565 1566 /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if 1567 * EL0[PV]TEN is zero. 1568 */ 1569 if (cur_el == 0 && 1570 !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) { 1571 return CP_ACCESS_TRAP; 1572 } 1573 1574 if (arm_feature(env, ARM_FEATURE_EL2) && 1575 timeridx == GTIMER_PHYS && !secure && cur_el < 2 && 1576 !extract32(env->cp15.cnthctl_el2, 1, 1)) { 1577 return CP_ACCESS_TRAP_EL2; 1578 } 1579 return CP_ACCESS_OK; 1580 } 1581 1582 static CPAccessResult gt_pct_access(CPUARMState *env, 1583 const ARMCPRegInfo *ri, 1584 bool isread) 1585 { 1586 return gt_counter_access(env, GTIMER_PHYS, isread); 1587 } 1588 1589 static CPAccessResult gt_vct_access(CPUARMState *env, 1590 const ARMCPRegInfo *ri, 1591 bool isread) 1592 { 1593 return gt_counter_access(env, GTIMER_VIRT, isread); 1594 } 1595 1596 static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri, 1597 bool isread) 1598 { 1599 return gt_timer_access(env, GTIMER_PHYS, isread); 1600 } 1601 1602 static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri, 1603 bool isread) 1604 { 1605 return gt_timer_access(env, GTIMER_VIRT, isread); 1606 } 1607 1608 static CPAccessResult gt_stimer_access(CPUARMState *env, 1609 const ARMCPRegInfo *ri, 1610 bool isread) 1611 { 1612 /* The AArch64 register view of the secure physical timer is 1613 * always accessible from EL3, and configurably accessible from 1614 * Secure EL1. 1615 */ 1616 switch (arm_current_el(env)) { 1617 case 1: 1618 if (!arm_is_secure(env)) { 1619 return CP_ACCESS_TRAP; 1620 } 1621 if (!(env->cp15.scr_el3 & SCR_ST)) { 1622 return CP_ACCESS_TRAP_EL3; 1623 } 1624 return CP_ACCESS_OK; 1625 case 0: 1626 case 2: 1627 return CP_ACCESS_TRAP; 1628 case 3: 1629 return CP_ACCESS_OK; 1630 default: 1631 g_assert_not_reached(); 1632 } 1633 } 1634 1635 static uint64_t gt_get_countervalue(CPUARMState *env) 1636 { 1637 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE; 1638 } 1639 1640 static void gt_recalc_timer(ARMCPU *cpu, int timeridx) 1641 { 1642 ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx]; 1643 1644 if (gt->ctl & 1) { 1645 /* Timer enabled: calculate and set current ISTATUS, irq, and 1646 * reset timer to when ISTATUS next has to change 1647 */ 1648 uint64_t offset = timeridx == GTIMER_VIRT ? 1649 cpu->env.cp15.cntvoff_el2 : 0; 1650 uint64_t count = gt_get_countervalue(&cpu->env); 1651 /* Note that this must be unsigned 64 bit arithmetic: */ 1652 int istatus = count - offset >= gt->cval; 1653 uint64_t nexttick; 1654 int irqstate; 1655 1656 gt->ctl = deposit32(gt->ctl, 2, 1, istatus); 1657 1658 irqstate = (istatus && !(gt->ctl & 2)); 1659 qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); 1660 1661 if (istatus) { 1662 /* Next transition is when count rolls back over to zero */ 1663 nexttick = UINT64_MAX; 1664 } else { 1665 /* Next transition is when we hit cval */ 1666 nexttick = gt->cval + offset; 1667 } 1668 /* Note that the desired next expiry time might be beyond the 1669 * signed-64-bit range of a QEMUTimer -- in this case we just 1670 * set the timer for as far in the future as possible. When the 1671 * timer expires we will reset the timer for any remaining period. 1672 */ 1673 if (nexttick > INT64_MAX / GTIMER_SCALE) { 1674 nexttick = INT64_MAX / GTIMER_SCALE; 1675 } 1676 timer_mod(cpu->gt_timer[timeridx], nexttick); 1677 trace_arm_gt_recalc(timeridx, irqstate, nexttick); 1678 } else { 1679 /* Timer disabled: ISTATUS and timer output always clear */ 1680 gt->ctl &= ~4; 1681 qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0); 1682 timer_del(cpu->gt_timer[timeridx]); 1683 trace_arm_gt_recalc_disabled(timeridx); 1684 } 1685 } 1686 1687 static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri, 1688 int timeridx) 1689 { 1690 ARMCPU *cpu = arm_env_get_cpu(env); 1691 1692 timer_del(cpu->gt_timer[timeridx]); 1693 } 1694 1695 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) 1696 { 1697 return gt_get_countervalue(env); 1698 } 1699 1700 static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) 1701 { 1702 return gt_get_countervalue(env) - env->cp15.cntvoff_el2; 1703 } 1704 1705 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1706 int timeridx, 1707 uint64_t value) 1708 { 1709 trace_arm_gt_cval_write(timeridx, value); 1710 env->cp15.c14_timer[timeridx].cval = value; 1711 gt_recalc_timer(arm_env_get_cpu(env), timeridx); 1712 } 1713 1714 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri, 1715 int timeridx) 1716 { 1717 uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0; 1718 1719 return (uint32_t)(env->cp15.c14_timer[timeridx].cval - 1720 (gt_get_countervalue(env) - offset)); 1721 } 1722 1723 static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1724 int timeridx, 1725 uint64_t value) 1726 { 1727 uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0; 1728 1729 trace_arm_gt_tval_write(timeridx, value); 1730 env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset + 1731 sextract64(value, 0, 32); 1732 gt_recalc_timer(arm_env_get_cpu(env), timeridx); 1733 } 1734 1735 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, 1736 int timeridx, 1737 uint64_t value) 1738 { 1739 ARMCPU *cpu = arm_env_get_cpu(env); 1740 uint32_t oldval = env->cp15.c14_timer[timeridx].ctl; 1741 1742 trace_arm_gt_ctl_write(timeridx, value); 1743 env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value); 1744 if ((oldval ^ value) & 1) { 1745 /* Enable toggled */ 1746 gt_recalc_timer(cpu, timeridx); 1747 } else if ((oldval ^ value) & 2) { 1748 /* IMASK toggled: don't need to recalculate, 1749 * just set the interrupt line based on ISTATUS 1750 */ 1751 int irqstate = (oldval & 4) && !(value & 2); 1752 1753 trace_arm_gt_imask_toggle(timeridx, irqstate); 1754 qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); 1755 } 1756 } 1757 1758 static void gt_phys_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) 1759 { 1760 gt_timer_reset(env, ri, GTIMER_PHYS); 1761 } 1762 1763 static void gt_phys_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1764 uint64_t value) 1765 { 1766 gt_cval_write(env, ri, GTIMER_PHYS, value); 1767 } 1768 1769 static uint64_t gt_phys_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) 1770 { 1771 return gt_tval_read(env, ri, GTIMER_PHYS); 1772 } 1773 1774 static void gt_phys_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1775 uint64_t value) 1776 { 1777 gt_tval_write(env, ri, GTIMER_PHYS, value); 1778 } 1779 1780 static void gt_phys_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, 1781 uint64_t value) 1782 { 1783 gt_ctl_write(env, ri, GTIMER_PHYS, value); 1784 } 1785 1786 static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) 1787 { 1788 gt_timer_reset(env, ri, GTIMER_VIRT); 1789 } 1790 1791 static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1792 uint64_t value) 1793 { 1794 gt_cval_write(env, ri, GTIMER_VIRT, value); 1795 } 1796 1797 static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) 1798 { 1799 return gt_tval_read(env, ri, GTIMER_VIRT); 1800 } 1801 1802 static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1803 uint64_t value) 1804 { 1805 gt_tval_write(env, ri, GTIMER_VIRT, value); 1806 } 1807 1808 static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, 1809 uint64_t value) 1810 { 1811 gt_ctl_write(env, ri, GTIMER_VIRT, value); 1812 } 1813 1814 static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri, 1815 uint64_t value) 1816 { 1817 ARMCPU *cpu = arm_env_get_cpu(env); 1818 1819 trace_arm_gt_cntvoff_write(value); 1820 raw_write(env, ri, value); 1821 gt_recalc_timer(cpu, GTIMER_VIRT); 1822 } 1823 1824 static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) 1825 { 1826 gt_timer_reset(env, ri, GTIMER_HYP); 1827 } 1828 1829 static void gt_hyp_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1830 uint64_t value) 1831 { 1832 gt_cval_write(env, ri, GTIMER_HYP, value); 1833 } 1834 1835 static uint64_t gt_hyp_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) 1836 { 1837 return gt_tval_read(env, ri, GTIMER_HYP); 1838 } 1839 1840 static void gt_hyp_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1841 uint64_t value) 1842 { 1843 gt_tval_write(env, ri, GTIMER_HYP, value); 1844 } 1845 1846 static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, 1847 uint64_t value) 1848 { 1849 gt_ctl_write(env, ri, GTIMER_HYP, value); 1850 } 1851 1852 static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) 1853 { 1854 gt_timer_reset(env, ri, GTIMER_SEC); 1855 } 1856 1857 static void gt_sec_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1858 uint64_t value) 1859 { 1860 gt_cval_write(env, ri, GTIMER_SEC, value); 1861 } 1862 1863 static uint64_t gt_sec_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) 1864 { 1865 return gt_tval_read(env, ri, GTIMER_SEC); 1866 } 1867 1868 static void gt_sec_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1869 uint64_t value) 1870 { 1871 gt_tval_write(env, ri, GTIMER_SEC, value); 1872 } 1873 1874 static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, 1875 uint64_t value) 1876 { 1877 gt_ctl_write(env, ri, GTIMER_SEC, value); 1878 } 1879 1880 void arm_gt_ptimer_cb(void *opaque) 1881 { 1882 ARMCPU *cpu = opaque; 1883 1884 gt_recalc_timer(cpu, GTIMER_PHYS); 1885 } 1886 1887 void arm_gt_vtimer_cb(void *opaque) 1888 { 1889 ARMCPU *cpu = opaque; 1890 1891 gt_recalc_timer(cpu, GTIMER_VIRT); 1892 } 1893 1894 void arm_gt_htimer_cb(void *opaque) 1895 { 1896 ARMCPU *cpu = opaque; 1897 1898 gt_recalc_timer(cpu, GTIMER_HYP); 1899 } 1900 1901 void arm_gt_stimer_cb(void *opaque) 1902 { 1903 ARMCPU *cpu = opaque; 1904 1905 gt_recalc_timer(cpu, GTIMER_SEC); 1906 } 1907 1908 static const ARMCPRegInfo generic_timer_cp_reginfo[] = { 1909 /* Note that CNTFRQ is purely reads-as-written for the benefit 1910 * of software; writing it doesn't actually change the timer frequency. 1911 * Our reset value matches the fixed frequency we implement the timer at. 1912 */ 1913 { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0, 1914 .type = ARM_CP_ALIAS, 1915 .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, 1916 .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq), 1917 }, 1918 { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64, 1919 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0, 1920 .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, 1921 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq), 1922 .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE, 1923 }, 1924 /* overall control: mostly access permissions */ 1925 { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH, 1926 .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0, 1927 .access = PL1_RW, 1928 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl), 1929 .resetvalue = 0, 1930 }, 1931 /* per-timer control */ 1932 { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1, 1933 .secure = ARM_CP_SECSTATE_NS, 1934 .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R, 1935 .accessfn = gt_ptimer_access, 1936 .fieldoffset = offsetoflow32(CPUARMState, 1937 cp15.c14_timer[GTIMER_PHYS].ctl), 1938 .writefn = gt_phys_ctl_write, .raw_writefn = raw_write, 1939 }, 1940 { .name = "CNTP_CTL(S)", 1941 .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1, 1942 .secure = ARM_CP_SECSTATE_S, 1943 .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R, 1944 .accessfn = gt_ptimer_access, 1945 .fieldoffset = offsetoflow32(CPUARMState, 1946 cp15.c14_timer[GTIMER_SEC].ctl), 1947 .writefn = gt_sec_ctl_write, .raw_writefn = raw_write, 1948 }, 1949 { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64, 1950 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1, 1951 .type = ARM_CP_IO, .access = PL1_RW | PL0_R, 1952 .accessfn = gt_ptimer_access, 1953 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), 1954 .resetvalue = 0, 1955 .writefn = gt_phys_ctl_write, .raw_writefn = raw_write, 1956 }, 1957 { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1, 1958 .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R, 1959 .accessfn = gt_vtimer_access, 1960 .fieldoffset = offsetoflow32(CPUARMState, 1961 cp15.c14_timer[GTIMER_VIRT].ctl), 1962 .writefn = gt_virt_ctl_write, .raw_writefn = raw_write, 1963 }, 1964 { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64, 1965 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1, 1966 .type = ARM_CP_IO, .access = PL1_RW | PL0_R, 1967 .accessfn = gt_vtimer_access, 1968 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl), 1969 .resetvalue = 0, 1970 .writefn = gt_virt_ctl_write, .raw_writefn = raw_write, 1971 }, 1972 /* TimerValue views: a 32 bit downcounting view of the underlying state */ 1973 { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0, 1974 .secure = ARM_CP_SECSTATE_NS, 1975 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, 1976 .accessfn = gt_ptimer_access, 1977 .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write, 1978 }, 1979 { .name = "CNTP_TVAL(S)", 1980 .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0, 1981 .secure = ARM_CP_SECSTATE_S, 1982 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, 1983 .accessfn = gt_ptimer_access, 1984 .readfn = gt_sec_tval_read, .writefn = gt_sec_tval_write, 1985 }, 1986 { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64, 1987 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0, 1988 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, 1989 .accessfn = gt_ptimer_access, .resetfn = gt_phys_timer_reset, 1990 .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write, 1991 }, 1992 { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0, 1993 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, 1994 .accessfn = gt_vtimer_access, 1995 .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write, 1996 }, 1997 { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64, 1998 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0, 1999 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, 2000 .accessfn = gt_vtimer_access, .resetfn = gt_virt_timer_reset, 2001 .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write, 2002 }, 2003 /* The counter itself */ 2004 { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0, 2005 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, 2006 .accessfn = gt_pct_access, 2007 .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore, 2008 }, 2009 { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64, 2010 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1, 2011 .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, 2012 .accessfn = gt_pct_access, .readfn = gt_cnt_read, 2013 }, 2014 { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1, 2015 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, 2016 .accessfn = gt_vct_access, 2017 .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore, 2018 }, 2019 { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64, 2020 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2, 2021 .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, 2022 .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read, 2023 }, 2024 /* Comparison value, indicating when the timer goes off */ 2025 { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2, 2026 .secure = ARM_CP_SECSTATE_NS, 2027 .access = PL1_RW | PL0_R, 2028 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, 2029 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), 2030 .accessfn = gt_ptimer_access, 2031 .writefn = gt_phys_cval_write, .raw_writefn = raw_write, 2032 }, 2033 { .name = "CNTP_CVAL(S)", .cp = 15, .crm = 14, .opc1 = 2, 2034 .secure = ARM_CP_SECSTATE_S, 2035 .access = PL1_RW | PL0_R, 2036 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, 2037 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval), 2038 .accessfn = gt_ptimer_access, 2039 .writefn = gt_sec_cval_write, .raw_writefn = raw_write, 2040 }, 2041 { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64, 2042 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2, 2043 .access = PL1_RW | PL0_R, 2044 .type = ARM_CP_IO, 2045 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), 2046 .resetvalue = 0, .accessfn = gt_ptimer_access, 2047 .writefn = gt_phys_cval_write, .raw_writefn = raw_write, 2048 }, 2049 { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3, 2050 .access = PL1_RW | PL0_R, 2051 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, 2052 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), 2053 .accessfn = gt_vtimer_access, 2054 .writefn = gt_virt_cval_write, .raw_writefn = raw_write, 2055 }, 2056 { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64, 2057 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2, 2058 .access = PL1_RW | PL0_R, 2059 .type = ARM_CP_IO, 2060 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), 2061 .resetvalue = 0, .accessfn = gt_vtimer_access, 2062 .writefn = gt_virt_cval_write, .raw_writefn = raw_write, 2063 }, 2064 /* Secure timer -- this is actually restricted to only EL3 2065 * and configurably Secure-EL1 via the accessfn. 2066 */ 2067 { .name = "CNTPS_TVAL_EL1", .state = ARM_CP_STATE_AA64, 2068 .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 0, 2069 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW, 2070 .accessfn = gt_stimer_access, 2071 .readfn = gt_sec_tval_read, 2072 .writefn = gt_sec_tval_write, 2073 .resetfn = gt_sec_timer_reset, 2074 }, 2075 { .name = "CNTPS_CTL_EL1", .state = ARM_CP_STATE_AA64, 2076 .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 1, 2077 .type = ARM_CP_IO, .access = PL1_RW, 2078 .accessfn = gt_stimer_access, 2079 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].ctl), 2080 .resetvalue = 0, 2081 .writefn = gt_sec_ctl_write, .raw_writefn = raw_write, 2082 }, 2083 { .name = "CNTPS_CVAL_EL1", .state = ARM_CP_STATE_AA64, 2084 .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 2, 2085 .type = ARM_CP_IO, .access = PL1_RW, 2086 .accessfn = gt_stimer_access, 2087 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval), 2088 .writefn = gt_sec_cval_write, .raw_writefn = raw_write, 2089 }, 2090 REGINFO_SENTINEL 2091 }; 2092 2093 #else 2094 /* In user-mode none of the generic timer registers are accessible, 2095 * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs, 2096 * so instead just don't register any of them. 2097 */ 2098 static const ARMCPRegInfo generic_timer_cp_reginfo[] = { 2099 REGINFO_SENTINEL 2100 }; 2101 2102 #endif 2103 2104 static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) 2105 { 2106 if (arm_feature(env, ARM_FEATURE_LPAE)) { 2107 raw_write(env, ri, value); 2108 } else if (arm_feature(env, ARM_FEATURE_V7)) { 2109 raw_write(env, ri, value & 0xfffff6ff); 2110 } else { 2111 raw_write(env, ri, value & 0xfffff1ff); 2112 } 2113 } 2114 2115 #ifndef CONFIG_USER_ONLY 2116 /* get_phys_addr() isn't present for user-mode-only targets */ 2117 2118 static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri, 2119 bool isread) 2120 { 2121 if (ri->opc2 & 4) { 2122 /* The ATS12NSO* operations must trap to EL3 if executed in 2123 * Secure EL1 (which can only happen if EL3 is AArch64). 2124 * They are simply UNDEF if executed from NS EL1. 2125 * They function normally from EL2 or EL3. 2126 */ 2127 if (arm_current_el(env) == 1) { 2128 if (arm_is_secure_below_el3(env)) { 2129 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3; 2130 } 2131 return CP_ACCESS_TRAP_UNCATEGORIZED; 2132 } 2133 } 2134 return CP_ACCESS_OK; 2135 } 2136 2137 static uint64_t do_ats_write(CPUARMState *env, uint64_t value, 2138 int access_type, ARMMMUIdx mmu_idx) 2139 { 2140 hwaddr phys_addr; 2141 target_ulong page_size; 2142 int prot; 2143 uint32_t fsr; 2144 bool ret; 2145 uint64_t par64; 2146 MemTxAttrs attrs = {}; 2147 ARMMMUFaultInfo fi = {}; 2148 2149 ret = get_phys_addr(env, value, access_type, mmu_idx, 2150 &phys_addr, &attrs, &prot, &page_size, &fsr, &fi); 2151 if (extended_addresses_enabled(env)) { 2152 /* fsr is a DFSR/IFSR value for the long descriptor 2153 * translation table format, but with WnR always clear. 2154 * Convert it to a 64-bit PAR. 2155 */ 2156 par64 = (1 << 11); /* LPAE bit always set */ 2157 if (!ret) { 2158 par64 |= phys_addr & ~0xfffULL; 2159 if (!attrs.secure) { 2160 par64 |= (1 << 9); /* NS */ 2161 } 2162 /* We don't set the ATTR or SH fields in the PAR. */ 2163 } else { 2164 par64 |= 1; /* F */ 2165 par64 |= (fsr & 0x3f) << 1; /* FS */ 2166 /* Note that S2WLK and FSTAGE are always zero, because we don't 2167 * implement virtualization and therefore there can't be a stage 2 2168 * fault. 2169 */ 2170 } 2171 } else { 2172 /* fsr is a DFSR/IFSR value for the short descriptor 2173 * translation table format (with WnR always clear). 2174 * Convert it to a 32-bit PAR. 2175 */ 2176 if (!ret) { 2177 /* We do not set any attribute bits in the PAR */ 2178 if (page_size == (1 << 24) 2179 && arm_feature(env, ARM_FEATURE_V7)) { 2180 par64 = (phys_addr & 0xff000000) | (1 << 1); 2181 } else { 2182 par64 = phys_addr & 0xfffff000; 2183 } 2184 if (!attrs.secure) { 2185 par64 |= (1 << 9); /* NS */ 2186 } 2187 } else { 2188 par64 = ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) | 2189 ((fsr & 0xf) << 1) | 1; 2190 } 2191 } 2192 return par64; 2193 } 2194 2195 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) 2196 { 2197 int access_type = ri->opc2 & 1; 2198 uint64_t par64; 2199 ARMMMUIdx mmu_idx; 2200 int el = arm_current_el(env); 2201 bool secure = arm_is_secure_below_el3(env); 2202 2203 switch (ri->opc2 & 6) { 2204 case 0: 2205 /* stage 1 current state PL1: ATS1CPR, ATS1CPW */ 2206 switch (el) { 2207 case 3: 2208 mmu_idx = ARMMMUIdx_S1E3; 2209 break; 2210 case 2: 2211 mmu_idx = ARMMMUIdx_S1NSE1; 2212 break; 2213 case 1: 2214 mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1; 2215 break; 2216 default: 2217 g_assert_not_reached(); 2218 } 2219 break; 2220 case 2: 2221 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */ 2222 switch (el) { 2223 case 3: 2224 mmu_idx = ARMMMUIdx_S1SE0; 2225 break; 2226 case 2: 2227 mmu_idx = ARMMMUIdx_S1NSE0; 2228 break; 2229 case 1: 2230 mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0; 2231 break; 2232 default: 2233 g_assert_not_reached(); 2234 } 2235 break; 2236 case 4: 2237 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */ 2238 mmu_idx = ARMMMUIdx_S12NSE1; 2239 break; 2240 case 6: 2241 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */ 2242 mmu_idx = ARMMMUIdx_S12NSE0; 2243 break; 2244 default: 2245 g_assert_not_reached(); 2246 } 2247 2248 par64 = do_ats_write(env, value, access_type, mmu_idx); 2249 2250 A32_BANKED_CURRENT_REG_SET(env, par, par64); 2251 } 2252 2253 static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri, 2254 uint64_t value) 2255 { 2256 int access_type = ri->opc2 & 1; 2257 uint64_t par64; 2258 2259 par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S2NS); 2260 2261 A32_BANKED_CURRENT_REG_SET(env, par, par64); 2262 } 2263 2264 static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri, 2265 bool isread) 2266 { 2267 if (arm_current_el(env) == 3 && !(env->cp15.scr_el3 & SCR_NS)) { 2268 return CP_ACCESS_TRAP; 2269 } 2270 return CP_ACCESS_OK; 2271 } 2272 2273 static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, 2274 uint64_t value) 2275 { 2276 int access_type = ri->opc2 & 1; 2277 ARMMMUIdx mmu_idx; 2278 int secure = arm_is_secure_below_el3(env); 2279 2280 switch (ri->opc2 & 6) { 2281 case 0: 2282 switch (ri->opc1) { 2283 case 0: /* AT S1E1R, AT S1E1W */ 2284 mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1; 2285 break; 2286 case 4: /* AT S1E2R, AT S1E2W */ 2287 mmu_idx = ARMMMUIdx_S1E2; 2288 break; 2289 case 6: /* AT S1E3R, AT S1E3W */ 2290 mmu_idx = ARMMMUIdx_S1E3; 2291 break; 2292 default: 2293 g_assert_not_reached(); 2294 } 2295 break; 2296 case 2: /* AT S1E0R, AT S1E0W */ 2297 mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0; 2298 break; 2299 case 4: /* AT S12E1R, AT S12E1W */ 2300 mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S12NSE1; 2301 break; 2302 case 6: /* AT S12E0R, AT S12E0W */ 2303 mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S12NSE0; 2304 break; 2305 default: 2306 g_assert_not_reached(); 2307 } 2308 2309 env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx); 2310 } 2311 #endif 2312 2313 static const ARMCPRegInfo vapa_cp_reginfo[] = { 2314 { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0, 2315 .access = PL1_RW, .resetvalue = 0, 2316 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s), 2317 offsetoflow32(CPUARMState, cp15.par_ns) }, 2318 .writefn = par_write }, 2319 #ifndef CONFIG_USER_ONLY 2320 /* This underdecoding is safe because the reginfo is NO_RAW. */ 2321 { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY, 2322 .access = PL1_W, .accessfn = ats_access, 2323 .writefn = ats_write, .type = ARM_CP_NO_RAW }, 2324 #endif 2325 REGINFO_SENTINEL 2326 }; 2327 2328 /* Return basic MPU access permission bits. */ 2329 static uint32_t simple_mpu_ap_bits(uint32_t val) 2330 { 2331 uint32_t ret; 2332 uint32_t mask; 2333 int i; 2334 ret = 0; 2335 mask = 3; 2336 for (i = 0; i < 16; i += 2) { 2337 ret |= (val >> i) & mask; 2338 mask <<= 2; 2339 } 2340 return ret; 2341 } 2342 2343 /* Pad basic MPU access permission bits to extended format. */ 2344 static uint32_t extended_mpu_ap_bits(uint32_t val) 2345 { 2346 uint32_t ret; 2347 uint32_t mask; 2348 int i; 2349 ret = 0; 2350 mask = 3; 2351 for (i = 0; i < 16; i += 2) { 2352 ret |= (val & mask) << i; 2353 mask <<= 2; 2354 } 2355 return ret; 2356 } 2357 2358 static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, 2359 uint64_t value) 2360 { 2361 env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value); 2362 } 2363 2364 static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) 2365 { 2366 return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap); 2367 } 2368 2369 static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, 2370 uint64_t value) 2371 { 2372 env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value); 2373 } 2374 2375 static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) 2376 { 2377 return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap); 2378 } 2379 2380 static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri) 2381 { 2382 uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); 2383 2384 if (!u32p) { 2385 return 0; 2386 } 2387 2388 u32p += env->pmsav7.rnr; 2389 return *u32p; 2390 } 2391 2392 static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri, 2393 uint64_t value) 2394 { 2395 ARMCPU *cpu = arm_env_get_cpu(env); 2396 uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); 2397 2398 if (!u32p) { 2399 return; 2400 } 2401 2402 u32p += env->pmsav7.rnr; 2403 tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ 2404 *u32p = value; 2405 } 2406 2407 static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri, 2408 uint64_t value) 2409 { 2410 ARMCPU *cpu = arm_env_get_cpu(env); 2411 uint32_t nrgs = cpu->pmsav7_dregion; 2412 2413 if (value >= nrgs) { 2414 qemu_log_mask(LOG_GUEST_ERROR, 2415 "PMSAv7 RGNR write >= # supported regions, %" PRIu32 2416 " > %" PRIu32 "\n", (uint32_t)value, nrgs); 2417 return; 2418 } 2419 2420 raw_write(env, ri, value); 2421 } 2422 2423 static const ARMCPRegInfo pmsav7_cp_reginfo[] = { 2424 /* Reset for all these registers is handled in arm_cpu_reset(), 2425 * because the PMSAv7 is also used by M-profile CPUs, which do 2426 * not register cpregs but still need the state to be reset. 2427 */ 2428 { .name = "DRBAR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 0, 2429 .access = PL1_RW, .type = ARM_CP_NO_RAW, 2430 .fieldoffset = offsetof(CPUARMState, pmsav7.drbar), 2431 .readfn = pmsav7_read, .writefn = pmsav7_write, 2432 .resetfn = arm_cp_reset_ignore }, 2433 { .name = "DRSR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 2, 2434 .access = PL1_RW, .type = ARM_CP_NO_RAW, 2435 .fieldoffset = offsetof(CPUARMState, pmsav7.drsr), 2436 .readfn = pmsav7_read, .writefn = pmsav7_write, 2437 .resetfn = arm_cp_reset_ignore }, 2438 { .name = "DRACR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 4, 2439 .access = PL1_RW, .type = ARM_CP_NO_RAW, 2440 .fieldoffset = offsetof(CPUARMState, pmsav7.dracr), 2441 .readfn = pmsav7_read, .writefn = pmsav7_write, 2442 .resetfn = arm_cp_reset_ignore }, 2443 { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0, 2444 .access = PL1_RW, 2445 .fieldoffset = offsetof(CPUARMState, pmsav7.rnr), 2446 .writefn = pmsav7_rgnr_write, 2447 .resetfn = arm_cp_reset_ignore }, 2448 REGINFO_SENTINEL 2449 }; 2450 2451 static const ARMCPRegInfo pmsav5_cp_reginfo[] = { 2452 { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, 2453 .access = PL1_RW, .type = ARM_CP_ALIAS, 2454 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap), 2455 .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, }, 2456 { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, 2457 .access = PL1_RW, .type = ARM_CP_ALIAS, 2458 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap), 2459 .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, }, 2460 { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2, 2461 .access = PL1_RW, 2462 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap), 2463 .resetvalue = 0, }, 2464 { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3, 2465 .access = PL1_RW, 2466 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap), 2467 .resetvalue = 0, }, 2468 { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, 2469 .access = PL1_RW, 2470 .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, }, 2471 { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1, 2472 .access = PL1_RW, 2473 .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, }, 2474 /* Protection region base and size registers */ 2475 { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, 2476 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 2477 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) }, 2478 { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0, 2479 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 2480 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) }, 2481 { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0, 2482 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 2483 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) }, 2484 { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0, 2485 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 2486 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) }, 2487 { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0, 2488 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 2489 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) }, 2490 { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0, 2491 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 2492 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) }, 2493 { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0, 2494 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 2495 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) }, 2496 { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0, 2497 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 2498 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) }, 2499 REGINFO_SENTINEL 2500 }; 2501 2502 static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, 2503 uint64_t value) 2504 { 2505 TCR *tcr = raw_ptr(env, ri); 2506 int maskshift = extract32(value, 0, 3); 2507 2508 if (!arm_feature(env, ARM_FEATURE_V8)) { 2509 if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) { 2510 /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when 2511 * using Long-desciptor translation table format */ 2512 value &= ~((7 << 19) | (3 << 14) | (0xf << 3)); 2513 } else if (arm_feature(env, ARM_FEATURE_EL3)) { 2514 /* In an implementation that includes the Security Extensions 2515 * TTBCR has additional fields PD0 [4] and PD1 [5] for 2516 * Short-descriptor translation table format. 2517 */ 2518 value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N; 2519 } else { 2520 value &= TTBCR_N; 2521 } 2522 } 2523 2524 /* Update the masks corresponding to the TCR bank being written 2525 * Note that we always calculate mask and base_mask, but 2526 * they are only used for short-descriptor tables (ie if EAE is 0); 2527 * for long-descriptor tables the TCR fields are used differently 2528 * and the mask and base_mask values are meaningless. 2529 */ 2530 tcr->raw_tcr = value; 2531 tcr->mask = ~(((uint32_t)0xffffffffu) >> maskshift); 2532 tcr->base_mask = ~((uint32_t)0x3fffu >> maskshift); 2533 } 2534 2535 static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, 2536 uint64_t value) 2537 { 2538 ARMCPU *cpu = arm_env_get_cpu(env); 2539 2540 if (arm_feature(env, ARM_FEATURE_LPAE)) { 2541 /* With LPAE the TTBCR could result in a change of ASID 2542 * via the TTBCR.A1 bit, so do a TLB flush. 2543 */ 2544 tlb_flush(CPU(cpu)); 2545 } 2546 vmsa_ttbcr_raw_write(env, ri, value); 2547 } 2548 2549 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) 2550 { 2551 TCR *tcr = raw_ptr(env, ri); 2552 2553 /* Reset both the TCR as well as the masks corresponding to the bank of 2554 * the TCR being reset. 2555 */ 2556 tcr->raw_tcr = 0; 2557 tcr->mask = 0; 2558 tcr->base_mask = 0xffffc000u; 2559 } 2560 2561 static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, 2562 uint64_t value) 2563 { 2564 ARMCPU *cpu = arm_env_get_cpu(env); 2565 TCR *tcr = raw_ptr(env, ri); 2566 2567 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */ 2568 tlb_flush(CPU(cpu)); 2569 tcr->raw_tcr = value; 2570 } 2571 2572 static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, 2573 uint64_t value) 2574 { 2575 /* 64 bit accesses to the TTBRs can change the ASID and so we 2576 * must flush the TLB. 2577 */ 2578 if (cpreg_field_is_64bit(ri)) { 2579 ARMCPU *cpu = arm_env_get_cpu(env); 2580 2581 tlb_flush(CPU(cpu)); 2582 } 2583 raw_write(env, ri, value); 2584 } 2585 2586 static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, 2587 uint64_t value) 2588 { 2589 ARMCPU *cpu = arm_env_get_cpu(env); 2590 CPUState *cs = CPU(cpu); 2591 2592 /* Accesses to VTTBR may change the VMID so we must flush the TLB. */ 2593 if (raw_read(env, ri) != value) { 2594 tlb_flush_by_mmuidx(cs, 2595 ARMMMUIdxBit_S12NSE1 | 2596 ARMMMUIdxBit_S12NSE0 | 2597 ARMMMUIdxBit_S2NS); 2598 raw_write(env, ri, value); 2599 } 2600 } 2601 2602 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = { 2603 { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, 2604 .access = PL1_RW, .type = ARM_CP_ALIAS, 2605 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s), 2606 offsetoflow32(CPUARMState, cp15.dfsr_ns) }, }, 2607 { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, 2608 .access = PL1_RW, .resetvalue = 0, 2609 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s), 2610 offsetoflow32(CPUARMState, cp15.ifsr_ns) } }, 2611 { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0, 2612 .access = PL1_RW, .resetvalue = 0, 2613 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s), 2614 offsetof(CPUARMState, cp15.dfar_ns) } }, 2615 { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64, 2616 .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, 2617 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]), 2618 .resetvalue = 0, }, 2619 REGINFO_SENTINEL 2620 }; 2621 2622 static const ARMCPRegInfo vmsa_cp_reginfo[] = { 2623 { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64, 2624 .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0, 2625 .access = PL1_RW, 2626 .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, }, 2627 { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH, 2628 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0, 2629 .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, 2630 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), 2631 offsetof(CPUARMState, cp15.ttbr0_ns) } }, 2632 { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH, 2633 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1, 2634 .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, 2635 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), 2636 offsetof(CPUARMState, cp15.ttbr1_ns) } }, 2637 { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64, 2638 .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, 2639 .access = PL1_RW, .writefn = vmsa_tcr_el1_write, 2640 .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write, 2641 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) }, 2642 { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, 2643 .access = PL1_RW, .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write, 2644 .raw_writefn = vmsa_ttbcr_raw_write, 2645 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]), 2646 offsetoflow32(CPUARMState, cp15.tcr_el[1])} }, 2647 REGINFO_SENTINEL 2648 }; 2649 2650 static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri, 2651 uint64_t value) 2652 { 2653 env->cp15.c15_ticonfig = value & 0xe7; 2654 /* The OS_TYPE bit in this register changes the reported CPUID! */ 2655 env->cp15.c0_cpuid = (value & (1 << 5)) ? 2656 ARM_CPUID_TI915T : ARM_CPUID_TI925T; 2657 } 2658 2659 static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri, 2660 uint64_t value) 2661 { 2662 env->cp15.c15_threadid = value & 0xffff; 2663 } 2664 2665 static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri, 2666 uint64_t value) 2667 { 2668 /* Wait-for-interrupt (deprecated) */ 2669 cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT); 2670 } 2671 2672 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, 2673 uint64_t value) 2674 { 2675 /* On OMAP there are registers indicating the max/min index of dcache lines 2676 * containing a dirty line; cache flush operations have to reset these. 2677 */ 2678 env->cp15.c15_i_max = 0x000; 2679 env->cp15.c15_i_min = 0xff0; 2680 } 2681 2682 static const ARMCPRegInfo omap_cp_reginfo[] = { 2683 { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY, 2684 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE, 2685 .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]), 2686 .resetvalue = 0, }, 2687 { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 2688 .access = PL1_RW, .type = ARM_CP_NOP }, 2689 { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 2690 .access = PL1_RW, 2691 .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0, 2692 .writefn = omap_ticonfig_write }, 2693 { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0, 2694 .access = PL1_RW, 2695 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, }, 2696 { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0, 2697 .access = PL1_RW, .resetvalue = 0xff0, 2698 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) }, 2699 { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0, 2700 .access = PL1_RW, 2701 .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0, 2702 .writefn = omap_threadid_write }, 2703 { .name = "TI925T_STATUS", .cp = 15, .crn = 15, 2704 .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW, 2705 .type = ARM_CP_NO_RAW, 2706 .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, }, 2707 /* TODO: Peripheral port remap register: 2708 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller 2709 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff), 2710 * when MMU is off. 2711 */ 2712 { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, 2713 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, 2714 .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW, 2715 .writefn = omap_cachemaint_write }, 2716 { .name = "C9", .cp = 15, .crn = 9, 2717 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, 2718 .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 }, 2719 REGINFO_SENTINEL 2720 }; 2721 2722 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri, 2723 uint64_t value) 2724 { 2725 env->cp15.c15_cpar = value & 0x3fff; 2726 } 2727 2728 static const ARMCPRegInfo xscale_cp_reginfo[] = { 2729 { .name = "XSCALE_CPAR", 2730 .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW, 2731 .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0, 2732 .writefn = xscale_cpar_write, }, 2733 { .name = "XSCALE_AUXCR", 2734 .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, 2735 .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr), 2736 .resetvalue = 0, }, 2737 /* XScale specific cache-lockdown: since we have no cache we NOP these 2738 * and hope the guest does not really rely on cache behaviour. 2739 */ 2740 { .name = "XSCALE_LOCK_ICACHE_LINE", 2741 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, 2742 .access = PL1_W, .type = ARM_CP_NOP }, 2743 { .name = "XSCALE_UNLOCK_ICACHE", 2744 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, 2745 .access = PL1_W, .type = ARM_CP_NOP }, 2746 { .name = "XSCALE_DCACHE_LOCK", 2747 .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0, 2748 .access = PL1_RW, .type = ARM_CP_NOP }, 2749 { .name = "XSCALE_UNLOCK_DCACHE", 2750 .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1, 2751 .access = PL1_W, .type = ARM_CP_NOP }, 2752 REGINFO_SENTINEL 2753 }; 2754 2755 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = { 2756 /* RAZ/WI the whole crn=15 space, when we don't have a more specific 2757 * implementation of this implementation-defined space. 2758 * Ideally this should eventually disappear in favour of actually 2759 * implementing the correct behaviour for all cores. 2760 */ 2761 { .name = "C15_IMPDEF", .cp = 15, .crn = 15, 2762 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, 2763 .access = PL1_RW, 2764 .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE, 2765 .resetvalue = 0 }, 2766 REGINFO_SENTINEL 2767 }; 2768 2769 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = { 2770 /* Cache status: RAZ because we have no cache so it's always clean */ 2771 { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6, 2772 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, 2773 .resetvalue = 0 }, 2774 REGINFO_SENTINEL 2775 }; 2776 2777 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = { 2778 /* We never have a a block transfer operation in progress */ 2779 { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4, 2780 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, 2781 .resetvalue = 0 }, 2782 /* The cache ops themselves: these all NOP for QEMU */ 2783 { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0, 2784 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, 2785 { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0, 2786 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, 2787 { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0, 2788 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, 2789 { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1, 2790 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, 2791 { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2, 2792 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, 2793 { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0, 2794 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, 2795 REGINFO_SENTINEL 2796 }; 2797 2798 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = { 2799 /* The cache test-and-clean instructions always return (1 << 30) 2800 * to indicate that there are no dirty cache lines. 2801 */ 2802 { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3, 2803 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, 2804 .resetvalue = (1 << 30) }, 2805 { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3, 2806 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, 2807 .resetvalue = (1 << 30) }, 2808 REGINFO_SENTINEL 2809 }; 2810 2811 static const ARMCPRegInfo strongarm_cp_reginfo[] = { 2812 /* Ignore ReadBuffer accesses */ 2813 { .name = "C9_READBUFFER", .cp = 15, .crn = 9, 2814 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, 2815 .access = PL1_RW, .resetvalue = 0, 2816 .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW }, 2817 REGINFO_SENTINEL 2818 }; 2819 2820 static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri) 2821 { 2822 ARMCPU *cpu = arm_env_get_cpu(env); 2823 unsigned int cur_el = arm_current_el(env); 2824 bool secure = arm_is_secure(env); 2825 2826 if (arm_feature(&cpu->env, ARM_FEATURE_EL2) && !secure && cur_el == 1) { 2827 return env->cp15.vpidr_el2; 2828 } 2829 return raw_read(env, ri); 2830 } 2831 2832 static uint64_t mpidr_read_val(CPUARMState *env) 2833 { 2834 ARMCPU *cpu = ARM_CPU(arm_env_get_cpu(env)); 2835 uint64_t mpidr = cpu->mp_affinity; 2836 2837 if (arm_feature(env, ARM_FEATURE_V7MP)) { 2838 mpidr |= (1U << 31); 2839 /* Cores which are uniprocessor (non-coherent) 2840 * but still implement the MP extensions set 2841 * bit 30. (For instance, Cortex-R5). 2842 */ 2843 if (cpu->mp_is_up) { 2844 mpidr |= (1u << 30); 2845 } 2846 } 2847 return mpidr; 2848 } 2849 2850 static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) 2851 { 2852 unsigned int cur_el = arm_current_el(env); 2853 bool secure = arm_is_secure(env); 2854 2855 if (arm_feature(env, ARM_FEATURE_EL2) && !secure && cur_el == 1) { 2856 return env->cp15.vmpidr_el2; 2857 } 2858 return mpidr_read_val(env); 2859 } 2860 2861 static const ARMCPRegInfo mpidr_cp_reginfo[] = { 2862 { .name = "MPIDR", .state = ARM_CP_STATE_BOTH, 2863 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5, 2864 .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW }, 2865 REGINFO_SENTINEL 2866 }; 2867 2868 static const ARMCPRegInfo lpae_cp_reginfo[] = { 2869 /* NOP AMAIR0/1 */ 2870 { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH, 2871 .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0, 2872 .access = PL1_RW, .type = ARM_CP_CONST, 2873 .resetvalue = 0 }, 2874 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */ 2875 { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1, 2876 .access = PL1_RW, .type = ARM_CP_CONST, 2877 .resetvalue = 0 }, 2878 { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0, 2879 .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0, 2880 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s), 2881 offsetof(CPUARMState, cp15.par_ns)} }, 2882 { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0, 2883 .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, 2884 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), 2885 offsetof(CPUARMState, cp15.ttbr0_ns) }, 2886 .writefn = vmsa_ttbr_write, }, 2887 { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1, 2888 .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, 2889 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), 2890 offsetof(CPUARMState, cp15.ttbr1_ns) }, 2891 .writefn = vmsa_ttbr_write, }, 2892 REGINFO_SENTINEL 2893 }; 2894 2895 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri) 2896 { 2897 return vfp_get_fpcr(env); 2898 } 2899 2900 static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri, 2901 uint64_t value) 2902 { 2903 vfp_set_fpcr(env, value); 2904 } 2905 2906 static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri) 2907 { 2908 return vfp_get_fpsr(env); 2909 } 2910 2911 static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri, 2912 uint64_t value) 2913 { 2914 vfp_set_fpsr(env, value); 2915 } 2916 2917 static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri, 2918 bool isread) 2919 { 2920 if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) { 2921 return CP_ACCESS_TRAP; 2922 } 2923 return CP_ACCESS_OK; 2924 } 2925 2926 static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri, 2927 uint64_t value) 2928 { 2929 env->daif = value & PSTATE_DAIF; 2930 } 2931 2932 static CPAccessResult aa64_cacheop_access(CPUARMState *env, 2933 const ARMCPRegInfo *ri, 2934 bool isread) 2935 { 2936 /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless 2937 * SCTLR_EL1.UCI is set. 2938 */ 2939 if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCI)) { 2940 return CP_ACCESS_TRAP; 2941 } 2942 return CP_ACCESS_OK; 2943 } 2944 2945 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions 2946 * Page D4-1736 (DDI0487A.b) 2947 */ 2948 2949 static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri, 2950 uint64_t value) 2951 { 2952 CPUState *cs = ENV_GET_CPU(env); 2953 2954 if (arm_is_secure_below_el3(env)) { 2955 tlb_flush_by_mmuidx(cs, 2956 ARMMMUIdxBit_S1SE1 | 2957 ARMMMUIdxBit_S1SE0); 2958 } else { 2959 tlb_flush_by_mmuidx(cs, 2960 ARMMMUIdxBit_S12NSE1 | 2961 ARMMMUIdxBit_S12NSE0); 2962 } 2963 } 2964 2965 static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, 2966 uint64_t value) 2967 { 2968 CPUState *cs = ENV_GET_CPU(env); 2969 bool sec = arm_is_secure_below_el3(env); 2970 2971 if (sec) { 2972 tlb_flush_by_mmuidx_all_cpus_synced(cs, 2973 ARMMMUIdxBit_S1SE1 | 2974 ARMMMUIdxBit_S1SE0); 2975 } else { 2976 tlb_flush_by_mmuidx_all_cpus_synced(cs, 2977 ARMMMUIdxBit_S12NSE1 | 2978 ARMMMUIdxBit_S12NSE0); 2979 } 2980 } 2981 2982 static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, 2983 uint64_t value) 2984 { 2985 /* Note that the 'ALL' scope must invalidate both stage 1 and 2986 * stage 2 translations, whereas most other scopes only invalidate 2987 * stage 1 translations. 2988 */ 2989 ARMCPU *cpu = arm_env_get_cpu(env); 2990 CPUState *cs = CPU(cpu); 2991 2992 if (arm_is_secure_below_el3(env)) { 2993 tlb_flush_by_mmuidx(cs, 2994 ARMMMUIdxBit_S1SE1 | 2995 ARMMMUIdxBit_S1SE0); 2996 } else { 2997 if (arm_feature(env, ARM_FEATURE_EL2)) { 2998 tlb_flush_by_mmuidx(cs, 2999 ARMMMUIdxBit_S12NSE1 | 3000 ARMMMUIdxBit_S12NSE0 | 3001 ARMMMUIdxBit_S2NS); 3002 } else { 3003 tlb_flush_by_mmuidx(cs, 3004 ARMMMUIdxBit_S12NSE1 | 3005 ARMMMUIdxBit_S12NSE0); 3006 } 3007 } 3008 } 3009 3010 static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri, 3011 uint64_t value) 3012 { 3013 ARMCPU *cpu = arm_env_get_cpu(env); 3014 CPUState *cs = CPU(cpu); 3015 3016 tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2); 3017 } 3018 3019 static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri, 3020 uint64_t value) 3021 { 3022 ARMCPU *cpu = arm_env_get_cpu(env); 3023 CPUState *cs = CPU(cpu); 3024 3025 tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E3); 3026 } 3027 3028 static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, 3029 uint64_t value) 3030 { 3031 /* Note that the 'ALL' scope must invalidate both stage 1 and 3032 * stage 2 translations, whereas most other scopes only invalidate 3033 * stage 1 translations. 3034 */ 3035 CPUState *cs = ENV_GET_CPU(env); 3036 bool sec = arm_is_secure_below_el3(env); 3037 bool has_el2 = arm_feature(env, ARM_FEATURE_EL2); 3038 3039 if (sec) { 3040 tlb_flush_by_mmuidx_all_cpus_synced(cs, 3041 ARMMMUIdxBit_S1SE1 | 3042 ARMMMUIdxBit_S1SE0); 3043 } else if (has_el2) { 3044 tlb_flush_by_mmuidx_all_cpus_synced(cs, 3045 ARMMMUIdxBit_S12NSE1 | 3046 ARMMMUIdxBit_S12NSE0 | 3047 ARMMMUIdxBit_S2NS); 3048 } else { 3049 tlb_flush_by_mmuidx_all_cpus_synced(cs, 3050 ARMMMUIdxBit_S12NSE1 | 3051 ARMMMUIdxBit_S12NSE0); 3052 } 3053 } 3054 3055 static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri, 3056 uint64_t value) 3057 { 3058 CPUState *cs = ENV_GET_CPU(env); 3059 3060 tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2); 3061 } 3062 3063 static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri, 3064 uint64_t value) 3065 { 3066 CPUState *cs = ENV_GET_CPU(env); 3067 3068 tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E3); 3069 } 3070 3071 static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri, 3072 uint64_t value) 3073 { 3074 /* Invalidate by VA, EL1&0 (AArch64 version). 3075 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1, 3076 * since we don't support flush-for-specific-ASID-only or 3077 * flush-last-level-only. 3078 */ 3079 ARMCPU *cpu = arm_env_get_cpu(env); 3080 CPUState *cs = CPU(cpu); 3081 uint64_t pageaddr = sextract64(value << 12, 0, 56); 3082 3083 if (arm_is_secure_below_el3(env)) { 3084 tlb_flush_page_by_mmuidx(cs, pageaddr, 3085 ARMMMUIdxBit_S1SE1 | 3086 ARMMMUIdxBit_S1SE0); 3087 } else { 3088 tlb_flush_page_by_mmuidx(cs, pageaddr, 3089 ARMMMUIdxBit_S12NSE1 | 3090 ARMMMUIdxBit_S12NSE0); 3091 } 3092 } 3093 3094 static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri, 3095 uint64_t value) 3096 { 3097 /* Invalidate by VA, EL2 3098 * Currently handles both VAE2 and VALE2, since we don't support 3099 * flush-last-level-only. 3100 */ 3101 ARMCPU *cpu = arm_env_get_cpu(env); 3102 CPUState *cs = CPU(cpu); 3103 uint64_t pageaddr = sextract64(value << 12, 0, 56); 3104 3105 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2); 3106 } 3107 3108 static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, 3109 uint64_t value) 3110 { 3111 /* Invalidate by VA, EL3 3112 * Currently handles both VAE3 and VALE3, since we don't support 3113 * flush-last-level-only. 3114 */ 3115 ARMCPU *cpu = arm_env_get_cpu(env); 3116 CPUState *cs = CPU(cpu); 3117 uint64_t pageaddr = sextract64(value << 12, 0, 56); 3118 3119 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E3); 3120 } 3121 3122 static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri, 3123 uint64_t value) 3124 { 3125 ARMCPU *cpu = arm_env_get_cpu(env); 3126 CPUState *cs = CPU(cpu); 3127 bool sec = arm_is_secure_below_el3(env); 3128 uint64_t pageaddr = sextract64(value << 12, 0, 56); 3129 3130 if (sec) { 3131 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, 3132 ARMMMUIdxBit_S1SE1 | 3133 ARMMMUIdxBit_S1SE0); 3134 } else { 3135 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, 3136 ARMMMUIdxBit_S12NSE1 | 3137 ARMMMUIdxBit_S12NSE0); 3138 } 3139 } 3140 3141 static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri, 3142 uint64_t value) 3143 { 3144 CPUState *cs = ENV_GET_CPU(env); 3145 uint64_t pageaddr = sextract64(value << 12, 0, 56); 3146 3147 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, 3148 ARMMMUIdxBit_S1E2); 3149 } 3150 3151 static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri, 3152 uint64_t value) 3153 { 3154 CPUState *cs = ENV_GET_CPU(env); 3155 uint64_t pageaddr = sextract64(value << 12, 0, 56); 3156 3157 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, 3158 ARMMMUIdxBit_S1E3); 3159 } 3160 3161 static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri, 3162 uint64_t value) 3163 { 3164 /* Invalidate by IPA. This has to invalidate any structures that 3165 * contain only stage 2 translation information, but does not need 3166 * to apply to structures that contain combined stage 1 and stage 2 3167 * translation information. 3168 * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero. 3169 */ 3170 ARMCPU *cpu = arm_env_get_cpu(env); 3171 CPUState *cs = CPU(cpu); 3172 uint64_t pageaddr; 3173 3174 if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { 3175 return; 3176 } 3177 3178 pageaddr = sextract64(value << 12, 0, 48); 3179 3180 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S2NS); 3181 } 3182 3183 static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri, 3184 uint64_t value) 3185 { 3186 CPUState *cs = ENV_GET_CPU(env); 3187 uint64_t pageaddr; 3188 3189 if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { 3190 return; 3191 } 3192 3193 pageaddr = sextract64(value << 12, 0, 48); 3194 3195 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, 3196 ARMMMUIdxBit_S2NS); 3197 } 3198 3199 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri, 3200 bool isread) 3201 { 3202 /* We don't implement EL2, so the only control on DC ZVA is the 3203 * bit in the SCTLR which can prohibit access for EL0. 3204 */ 3205 if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_DZE)) { 3206 return CP_ACCESS_TRAP; 3207 } 3208 return CP_ACCESS_OK; 3209 } 3210 3211 static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri) 3212 { 3213 ARMCPU *cpu = arm_env_get_cpu(env); 3214 int dzp_bit = 1 << 4; 3215 3216 /* DZP indicates whether DC ZVA access is allowed */ 3217 if (aa64_zva_access(env, NULL, false) == CP_ACCESS_OK) { 3218 dzp_bit = 0; 3219 } 3220 return cpu->dcz_blocksize | dzp_bit; 3221 } 3222 3223 static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, 3224 bool isread) 3225 { 3226 if (!(env->pstate & PSTATE_SP)) { 3227 /* Access to SP_EL0 is undefined if it's being used as 3228 * the stack pointer. 3229 */ 3230 return CP_ACCESS_TRAP_UNCATEGORIZED; 3231 } 3232 return CP_ACCESS_OK; 3233 } 3234 3235 static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri) 3236 { 3237 return env->pstate & PSTATE_SP; 3238 } 3239 3240 static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) 3241 { 3242 update_spsel(env, val); 3243 } 3244 3245 static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, 3246 uint64_t value) 3247 { 3248 ARMCPU *cpu = arm_env_get_cpu(env); 3249 3250 if (raw_read(env, ri) == value) { 3251 /* Skip the TLB flush if nothing actually changed; Linux likes 3252 * to do a lot of pointless SCTLR writes. 3253 */ 3254 return; 3255 } 3256 3257 if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) { 3258 /* M bit is RAZ/WI for PMSA with no MPU implemented */ 3259 value &= ~SCTLR_M; 3260 } 3261 3262 raw_write(env, ri, value); 3263 /* ??? Lots of these bits are not implemented. */ 3264 /* This may enable/disable the MMU, so do a TLB flush. */ 3265 tlb_flush(CPU(cpu)); 3266 } 3267 3268 static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri, 3269 bool isread) 3270 { 3271 if ((env->cp15.cptr_el[2] & CPTR_TFP) && arm_current_el(env) == 2) { 3272 return CP_ACCESS_TRAP_FP_EL2; 3273 } 3274 if (env->cp15.cptr_el[3] & CPTR_TFP) { 3275 return CP_ACCESS_TRAP_FP_EL3; 3276 } 3277 return CP_ACCESS_OK; 3278 } 3279 3280 static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri, 3281 uint64_t value) 3282 { 3283 env->cp15.mdcr_el3 = value & SDCR_VALID_MASK; 3284 } 3285 3286 static const ARMCPRegInfo v8_cp_reginfo[] = { 3287 /* Minimal set of EL0-visible registers. This will need to be expanded 3288 * significantly for system emulation of AArch64 CPUs. 3289 */ 3290 { .name = "NZCV", .state = ARM_CP_STATE_AA64, 3291 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2, 3292 .access = PL0_RW, .type = ARM_CP_NZCV }, 3293 { .name = "DAIF", .state = ARM_CP_STATE_AA64, 3294 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2, 3295 .type = ARM_CP_NO_RAW, 3296 .access = PL0_RW, .accessfn = aa64_daif_access, 3297 .fieldoffset = offsetof(CPUARMState, daif), 3298 .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore }, 3299 { .name = "FPCR", .state = ARM_CP_STATE_AA64, 3300 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4, 3301 .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write }, 3302 { .name = "FPSR", .state = ARM_CP_STATE_AA64, 3303 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4, 3304 .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write }, 3305 { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64, 3306 .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0, 3307 .access = PL0_R, .type = ARM_CP_NO_RAW, 3308 .readfn = aa64_dczid_read }, 3309 { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64, 3310 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1, 3311 .access = PL0_W, .type = ARM_CP_DC_ZVA, 3312 #ifndef CONFIG_USER_ONLY 3313 /* Avoid overhead of an access check that always passes in user-mode */ 3314 .accessfn = aa64_zva_access, 3315 #endif 3316 }, 3317 { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64, 3318 .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2, 3319 .access = PL1_R, .type = ARM_CP_CURRENTEL }, 3320 /* Cache ops: all NOPs since we don't emulate caches */ 3321 { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64, 3322 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, 3323 .access = PL1_W, .type = ARM_CP_NOP }, 3324 { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64, 3325 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, 3326 .access = PL1_W, .type = ARM_CP_NOP }, 3327 { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64, 3328 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1, 3329 .access = PL0_W, .type = ARM_CP_NOP, 3330 .accessfn = aa64_cacheop_access }, 3331 { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64, 3332 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, 3333 .access = PL1_W, .type = ARM_CP_NOP }, 3334 { .name = "DC_ISW", .state = ARM_CP_STATE_AA64, 3335 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, 3336 .access = PL1_W, .type = ARM_CP_NOP }, 3337 { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64, 3338 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1, 3339 .access = PL0_W, .type = ARM_CP_NOP, 3340 .accessfn = aa64_cacheop_access }, 3341 { .name = "DC_CSW", .state = ARM_CP_STATE_AA64, 3342 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, 3343 .access = PL1_W, .type = ARM_CP_NOP }, 3344 { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64, 3345 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1, 3346 .access = PL0_W, .type = ARM_CP_NOP, 3347 .accessfn = aa64_cacheop_access }, 3348 { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64, 3349 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1, 3350 .access = PL0_W, .type = ARM_CP_NOP, 3351 .accessfn = aa64_cacheop_access }, 3352 { .name = "DC_CISW", .state = ARM_CP_STATE_AA64, 3353 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, 3354 .access = PL1_W, .type = ARM_CP_NOP }, 3355 /* TLBI operations */ 3356 { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64, 3357 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, 3358 .access = PL1_W, .type = ARM_CP_NO_RAW, 3359 .writefn = tlbi_aa64_vmalle1is_write }, 3360 { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64, 3361 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, 3362 .access = PL1_W, .type = ARM_CP_NO_RAW, 3363 .writefn = tlbi_aa64_vae1is_write }, 3364 { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64, 3365 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, 3366 .access = PL1_W, .type = ARM_CP_NO_RAW, 3367 .writefn = tlbi_aa64_vmalle1is_write }, 3368 { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64, 3369 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, 3370 .access = PL1_W, .type = ARM_CP_NO_RAW, 3371 .writefn = tlbi_aa64_vae1is_write }, 3372 { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64, 3373 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, 3374 .access = PL1_W, .type = ARM_CP_NO_RAW, 3375 .writefn = tlbi_aa64_vae1is_write }, 3376 { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64, 3377 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, 3378 .access = PL1_W, .type = ARM_CP_NO_RAW, 3379 .writefn = tlbi_aa64_vae1is_write }, 3380 { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64, 3381 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, 3382 .access = PL1_W, .type = ARM_CP_NO_RAW, 3383 .writefn = tlbi_aa64_vmalle1_write }, 3384 { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64, 3385 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, 3386 .access = PL1_W, .type = ARM_CP_NO_RAW, 3387 .writefn = tlbi_aa64_vae1_write }, 3388 { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64, 3389 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, 3390 .access = PL1_W, .type = ARM_CP_NO_RAW, 3391 .writefn = tlbi_aa64_vmalle1_write }, 3392 { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64, 3393 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, 3394 .access = PL1_W, .type = ARM_CP_NO_RAW, 3395 .writefn = tlbi_aa64_vae1_write }, 3396 { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64, 3397 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, 3398 .access = PL1_W, .type = ARM_CP_NO_RAW, 3399 .writefn = tlbi_aa64_vae1_write }, 3400 { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64, 3401 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, 3402 .access = PL1_W, .type = ARM_CP_NO_RAW, 3403 .writefn = tlbi_aa64_vae1_write }, 3404 { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64, 3405 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1, 3406 .access = PL2_W, .type = ARM_CP_NO_RAW, 3407 .writefn = tlbi_aa64_ipas2e1is_write }, 3408 { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64, 3409 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5, 3410 .access = PL2_W, .type = ARM_CP_NO_RAW, 3411 .writefn = tlbi_aa64_ipas2e1is_write }, 3412 { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64, 3413 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4, 3414 .access = PL2_W, .type = ARM_CP_NO_RAW, 3415 .writefn = tlbi_aa64_alle1is_write }, 3416 { .name = "TLBI_VMALLS12E1IS", .state = ARM_CP_STATE_AA64, 3417 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6, 3418 .access = PL2_W, .type = ARM_CP_NO_RAW, 3419 .writefn = tlbi_aa64_alle1is_write }, 3420 { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64, 3421 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1, 3422 .access = PL2_W, .type = ARM_CP_NO_RAW, 3423 .writefn = tlbi_aa64_ipas2e1_write }, 3424 { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64, 3425 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5, 3426 .access = PL2_W, .type = ARM_CP_NO_RAW, 3427 .writefn = tlbi_aa64_ipas2e1_write }, 3428 { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64, 3429 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4, 3430 .access = PL2_W, .type = ARM_CP_NO_RAW, 3431 .writefn = tlbi_aa64_alle1_write }, 3432 { .name = "TLBI_VMALLS12E1", .state = ARM_CP_STATE_AA64, 3433 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6, 3434 .access = PL2_W, .type = ARM_CP_NO_RAW, 3435 .writefn = tlbi_aa64_alle1is_write }, 3436 #ifndef CONFIG_USER_ONLY 3437 /* 64 bit address translation operations */ 3438 { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64, 3439 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0, 3440 .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3441 { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64, 3442 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1, 3443 .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3444 { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64, 3445 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2, 3446 .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3447 { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64, 3448 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3, 3449 .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3450 { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64, 3451 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4, 3452 .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3453 { .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64, 3454 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 5, 3455 .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3456 { .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64, 3457 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 6, 3458 .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3459 { .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64, 3460 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 7, 3461 .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3462 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */ 3463 { .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64, 3464 .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 0, 3465 .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3466 { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64, 3467 .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1, 3468 .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3469 { .name = "PAR_EL1", .state = ARM_CP_STATE_AA64, 3470 .type = ARM_CP_ALIAS, 3471 .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0, 3472 .access = PL1_RW, .resetvalue = 0, 3473 .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]), 3474 .writefn = par_write }, 3475 #endif 3476 /* TLB invalidate last level of translation table walk */ 3477 { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, 3478 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write }, 3479 { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, 3480 .type = ARM_CP_NO_RAW, .access = PL1_W, 3481 .writefn = tlbimvaa_is_write }, 3482 { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, 3483 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, 3484 { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, 3485 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write }, 3486 { .name = "TLBIMVALH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, 3487 .type = ARM_CP_NO_RAW, .access = PL2_W, 3488 .writefn = tlbimva_hyp_write }, 3489 { .name = "TLBIMVALHIS", 3490 .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, 3491 .type = ARM_CP_NO_RAW, .access = PL2_W, 3492 .writefn = tlbimva_hyp_is_write }, 3493 { .name = "TLBIIPAS2", 3494 .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1, 3495 .type = ARM_CP_NO_RAW, .access = PL2_W, 3496 .writefn = tlbiipas2_write }, 3497 { .name = "TLBIIPAS2IS", 3498 .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1, 3499 .type = ARM_CP_NO_RAW, .access = PL2_W, 3500 .writefn = tlbiipas2_is_write }, 3501 { .name = "TLBIIPAS2L", 3502 .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5, 3503 .type = ARM_CP_NO_RAW, .access = PL2_W, 3504 .writefn = tlbiipas2_write }, 3505 { .name = "TLBIIPAS2LIS", 3506 .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5, 3507 .type = ARM_CP_NO_RAW, .access = PL2_W, 3508 .writefn = tlbiipas2_is_write }, 3509 /* 32 bit cache operations */ 3510 { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, 3511 .type = ARM_CP_NOP, .access = PL1_W }, 3512 { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6, 3513 .type = ARM_CP_NOP, .access = PL1_W }, 3514 { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, 3515 .type = ARM_CP_NOP, .access = PL1_W }, 3516 { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1, 3517 .type = ARM_CP_NOP, .access = PL1_W }, 3518 { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6, 3519 .type = ARM_CP_NOP, .access = PL1_W }, 3520 { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7, 3521 .type = ARM_CP_NOP, .access = PL1_W }, 3522 { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, 3523 .type = ARM_CP_NOP, .access = PL1_W }, 3524 { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, 3525 .type = ARM_CP_NOP, .access = PL1_W }, 3526 { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1, 3527 .type = ARM_CP_NOP, .access = PL1_W }, 3528 { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, 3529 .type = ARM_CP_NOP, .access = PL1_W }, 3530 { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1, 3531 .type = ARM_CP_NOP, .access = PL1_W }, 3532 { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1, 3533 .type = ARM_CP_NOP, .access = PL1_W }, 3534 { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, 3535 .type = ARM_CP_NOP, .access = PL1_W }, 3536 /* MMU Domain access control / MPU write buffer control */ 3537 { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0, 3538 .access = PL1_RW, .resetvalue = 0, 3539 .writefn = dacr_write, .raw_writefn = raw_write, 3540 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s), 3541 offsetoflow32(CPUARMState, cp15.dacr_ns) } }, 3542 { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64, 3543 .type = ARM_CP_ALIAS, 3544 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1, 3545 .access = PL1_RW, 3546 .fieldoffset = offsetof(CPUARMState, elr_el[1]) }, 3547 { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64, 3548 .type = ARM_CP_ALIAS, 3549 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0, 3550 .access = PL1_RW, 3551 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_SVC]) }, 3552 /* We rely on the access checks not allowing the guest to write to the 3553 * state field when SPSel indicates that it's being used as the stack 3554 * pointer. 3555 */ 3556 { .name = "SP_EL0", .state = ARM_CP_STATE_AA64, 3557 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0, 3558 .access = PL1_RW, .accessfn = sp_el0_access, 3559 .type = ARM_CP_ALIAS, 3560 .fieldoffset = offsetof(CPUARMState, sp_el[0]) }, 3561 { .name = "SP_EL1", .state = ARM_CP_STATE_AA64, 3562 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0, 3563 .access = PL2_RW, .type = ARM_CP_ALIAS, 3564 .fieldoffset = offsetof(CPUARMState, sp_el[1]) }, 3565 { .name = "SPSel", .state = ARM_CP_STATE_AA64, 3566 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0, 3567 .type = ARM_CP_NO_RAW, 3568 .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write }, 3569 { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64, 3570 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0, 3571 .type = ARM_CP_ALIAS, 3572 .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]), 3573 .access = PL2_RW, .accessfn = fpexc32_access }, 3574 { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64, 3575 .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0, 3576 .access = PL2_RW, .resetvalue = 0, 3577 .writefn = dacr_write, .raw_writefn = raw_write, 3578 .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) }, 3579 { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64, 3580 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1, 3581 .access = PL2_RW, .resetvalue = 0, 3582 .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) }, 3583 { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64, 3584 .type = ARM_CP_ALIAS, 3585 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 0, 3586 .access = PL2_RW, 3587 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_IRQ]) }, 3588 { .name = "SPSR_ABT", .state = ARM_CP_STATE_AA64, 3589 .type = ARM_CP_ALIAS, 3590 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 1, 3591 .access = PL2_RW, 3592 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_ABT]) }, 3593 { .name = "SPSR_UND", .state = ARM_CP_STATE_AA64, 3594 .type = ARM_CP_ALIAS, 3595 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 2, 3596 .access = PL2_RW, 3597 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_UND]) }, 3598 { .name = "SPSR_FIQ", .state = ARM_CP_STATE_AA64, 3599 .type = ARM_CP_ALIAS, 3600 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 3, 3601 .access = PL2_RW, 3602 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) }, 3603 { .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64, 3604 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1, 3605 .resetvalue = 0, 3606 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) }, 3607 { .name = "SDCR", .type = ARM_CP_ALIAS, 3608 .cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1, 3609 .access = PL1_RW, .accessfn = access_trap_aa32s_el1, 3610 .writefn = sdcr_write, 3611 .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) }, 3612 REGINFO_SENTINEL 3613 }; 3614 3615 /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */ 3616 static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { 3617 { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64, 3618 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, 3619 .access = PL2_RW, 3620 .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, 3621 { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64, 3622 .type = ARM_CP_NO_RAW, 3623 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, 3624 .access = PL2_RW, 3625 .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, 3626 { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH, 3627 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, 3628 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3629 { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH, 3630 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0, 3631 .access = PL2_RW, .type = ARM_CP_CONST, 3632 .resetvalue = 0 }, 3633 { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, 3634 .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, 3635 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3636 { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH, 3637 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0, 3638 .access = PL2_RW, .type = ARM_CP_CONST, 3639 .resetvalue = 0 }, 3640 { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, 3641 .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, 3642 .access = PL2_RW, .type = ARM_CP_CONST, 3643 .resetvalue = 0 }, 3644 { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH, 3645 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0, 3646 .access = PL2_RW, .type = ARM_CP_CONST, 3647 .resetvalue = 0 }, 3648 { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH, 3649 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1, 3650 .access = PL2_RW, .type = ARM_CP_CONST, 3651 .resetvalue = 0 }, 3652 { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, 3653 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, 3654 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3655 { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH, 3656 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, 3657 .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, 3658 .type = ARM_CP_CONST, .resetvalue = 0 }, 3659 { .name = "VTTBR", .state = ARM_CP_STATE_AA32, 3660 .cp = 15, .opc1 = 6, .crm = 2, 3661 .access = PL2_RW, .accessfn = access_el3_aa32ns, 3662 .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 3663 { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64, 3664 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0, 3665 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3666 { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, 3667 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, 3668 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3669 { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH, 3670 .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2, 3671 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3672 { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, 3673 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, 3674 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3675 { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2, 3676 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, 3677 .resetvalue = 0 }, 3678 { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH, 3679 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, 3680 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3681 { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64, 3682 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3, 3683 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3684 { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14, 3685 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, 3686 .resetvalue = 0 }, 3687 { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64, 3688 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2, 3689 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3690 { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14, 3691 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, 3692 .resetvalue = 0 }, 3693 { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH, 3694 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0, 3695 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3696 { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, 3697 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, 3698 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3699 { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, 3700 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, 3701 .access = PL2_RW, .accessfn = access_tda, 3702 .type = ARM_CP_CONST, .resetvalue = 0 }, 3703 { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH, 3704 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, 3705 .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, 3706 .type = ARM_CP_CONST, .resetvalue = 0 }, 3707 { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH, 3708 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3, 3709 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3710 REGINFO_SENTINEL 3711 }; 3712 3713 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) 3714 { 3715 ARMCPU *cpu = arm_env_get_cpu(env); 3716 uint64_t valid_mask = HCR_MASK; 3717 3718 if (arm_feature(env, ARM_FEATURE_EL3)) { 3719 valid_mask &= ~HCR_HCD; 3720 } else { 3721 valid_mask &= ~HCR_TSC; 3722 } 3723 3724 /* Clear RES0 bits. */ 3725 value &= valid_mask; 3726 3727 /* These bits change the MMU setup: 3728 * HCR_VM enables stage 2 translation 3729 * HCR_PTW forbids certain page-table setups 3730 * HCR_DC Disables stage1 and enables stage2 translation 3731 */ 3732 if ((raw_read(env, ri) ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) { 3733 tlb_flush(CPU(cpu)); 3734 } 3735 raw_write(env, ri, value); 3736 } 3737 3738 static const ARMCPRegInfo el2_cp_reginfo[] = { 3739 { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64, 3740 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, 3741 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), 3742 .writefn = hcr_write }, 3743 { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64, 3744 .type = ARM_CP_ALIAS, 3745 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1, 3746 .access = PL2_RW, 3747 .fieldoffset = offsetof(CPUARMState, elr_el[2]) }, 3748 { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64, 3749 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, 3750 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) }, 3751 { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64, 3752 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, 3753 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) }, 3754 { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64, 3755 .type = ARM_CP_ALIAS, 3756 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0, 3757 .access = PL2_RW, 3758 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_HYP]) }, 3759 { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64, 3760 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, 3761 .access = PL2_RW, .writefn = vbar_write, 3762 .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]), 3763 .resetvalue = 0 }, 3764 { .name = "SP_EL2", .state = ARM_CP_STATE_AA64, 3765 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0, 3766 .access = PL3_RW, .type = ARM_CP_ALIAS, 3767 .fieldoffset = offsetof(CPUARMState, sp_el[2]) }, 3768 { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH, 3769 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, 3770 .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0, 3771 .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[2]) }, 3772 { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH, 3773 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0, 3774 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[2]), 3775 .resetvalue = 0 }, 3776 { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, 3777 .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, 3778 .access = PL2_RW, .type = ARM_CP_ALIAS, 3779 .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el[2]) }, 3780 { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH, 3781 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0, 3782 .access = PL2_RW, .type = ARM_CP_CONST, 3783 .resetvalue = 0 }, 3784 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */ 3785 { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, 3786 .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, 3787 .access = PL2_RW, .type = ARM_CP_CONST, 3788 .resetvalue = 0 }, 3789 { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH, 3790 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0, 3791 .access = PL2_RW, .type = ARM_CP_CONST, 3792 .resetvalue = 0 }, 3793 { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH, 3794 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1, 3795 .access = PL2_RW, .type = ARM_CP_CONST, 3796 .resetvalue = 0 }, 3797 { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, 3798 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, 3799 .access = PL2_RW, 3800 /* no .writefn needed as this can't cause an ASID change; 3801 * no .raw_writefn or .resetfn needed as we never use mask/base_mask 3802 */ 3803 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) }, 3804 { .name = "VTCR", .state = ARM_CP_STATE_AA32, 3805 .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, 3806 .type = ARM_CP_ALIAS, 3807 .access = PL2_RW, .accessfn = access_el3_aa32ns, 3808 .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) }, 3809 { .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64, 3810 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, 3811 .access = PL2_RW, 3812 /* no .writefn needed as this can't cause an ASID change; 3813 * no .raw_writefn or .resetfn needed as we never use mask/base_mask 3814 */ 3815 .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) }, 3816 { .name = "VTTBR", .state = ARM_CP_STATE_AA32, 3817 .cp = 15, .opc1 = 6, .crm = 2, 3818 .type = ARM_CP_64BIT | ARM_CP_ALIAS, 3819 .access = PL2_RW, .accessfn = access_el3_aa32ns, 3820 .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2), 3821 .writefn = vttbr_write }, 3822 { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64, 3823 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0, 3824 .access = PL2_RW, .writefn = vttbr_write, 3825 .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) }, 3826 { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, 3827 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, 3828 .access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write, 3829 .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[2]) }, 3830 { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH, 3831 .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2, 3832 .access = PL2_RW, .resetvalue = 0, 3833 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) }, 3834 { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, 3835 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, 3836 .access = PL2_RW, .resetvalue = 0, 3837 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, 3838 { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2, 3839 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, 3840 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, 3841 { .name = "TLBIALLNSNH", 3842 .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4, 3843 .type = ARM_CP_NO_RAW, .access = PL2_W, 3844 .writefn = tlbiall_nsnh_write }, 3845 { .name = "TLBIALLNSNHIS", 3846 .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4, 3847 .type = ARM_CP_NO_RAW, .access = PL2_W, 3848 .writefn = tlbiall_nsnh_is_write }, 3849 { .name = "TLBIALLH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0, 3850 .type = ARM_CP_NO_RAW, .access = PL2_W, 3851 .writefn = tlbiall_hyp_write }, 3852 { .name = "TLBIALLHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, 3853 .type = ARM_CP_NO_RAW, .access = PL2_W, 3854 .writefn = tlbiall_hyp_is_write }, 3855 { .name = "TLBIMVAH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, 3856 .type = ARM_CP_NO_RAW, .access = PL2_W, 3857 .writefn = tlbimva_hyp_write }, 3858 { .name = "TLBIMVAHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, 3859 .type = ARM_CP_NO_RAW, .access = PL2_W, 3860 .writefn = tlbimva_hyp_is_write }, 3861 { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64, 3862 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0, 3863 .type = ARM_CP_NO_RAW, .access = PL2_W, 3864 .writefn = tlbi_aa64_alle2_write }, 3865 { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64, 3866 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, 3867 .type = ARM_CP_NO_RAW, .access = PL2_W, 3868 .writefn = tlbi_aa64_vae2_write }, 3869 { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64, 3870 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, 3871 .access = PL2_W, .type = ARM_CP_NO_RAW, 3872 .writefn = tlbi_aa64_vae2_write }, 3873 { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64, 3874 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, 3875 .access = PL2_W, .type = ARM_CP_NO_RAW, 3876 .writefn = tlbi_aa64_alle2is_write }, 3877 { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64, 3878 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, 3879 .type = ARM_CP_NO_RAW, .access = PL2_W, 3880 .writefn = tlbi_aa64_vae2is_write }, 3881 { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64, 3882 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, 3883 .access = PL2_W, .type = ARM_CP_NO_RAW, 3884 .writefn = tlbi_aa64_vae2is_write }, 3885 #ifndef CONFIG_USER_ONLY 3886 /* Unlike the other EL2-related AT operations, these must 3887 * UNDEF from EL3 if EL2 is not implemented, which is why we 3888 * define them here rather than with the rest of the AT ops. 3889 */ 3890 { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64, 3891 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, 3892 .access = PL2_W, .accessfn = at_s1e2_access, 3893 .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3894 { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64, 3895 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, 3896 .access = PL2_W, .accessfn = at_s1e2_access, 3897 .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3898 /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE 3899 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3 3900 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose 3901 * to behave as if SCR.NS was 1. 3902 */ 3903 { .name = "ATS1HR", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, 3904 .access = PL2_W, 3905 .writefn = ats1h_write, .type = ARM_CP_NO_RAW }, 3906 { .name = "ATS1HW", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, 3907 .access = PL2_W, 3908 .writefn = ats1h_write, .type = ARM_CP_NO_RAW }, 3909 { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH, 3910 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, 3911 /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the 3912 * reset values as IMPDEF. We choose to reset to 3 to comply with 3913 * both ARMv7 and ARMv8. 3914 */ 3915 .access = PL2_RW, .resetvalue = 3, 3916 .fieldoffset = offsetof(CPUARMState, cp15.cnthctl_el2) }, 3917 { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64, 3918 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3, 3919 .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0, 3920 .writefn = gt_cntvoff_write, 3921 .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) }, 3922 { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14, 3923 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_IO, 3924 .writefn = gt_cntvoff_write, 3925 .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) }, 3926 { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64, 3927 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2, 3928 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval), 3929 .type = ARM_CP_IO, .access = PL2_RW, 3930 .writefn = gt_hyp_cval_write, .raw_writefn = raw_write }, 3931 { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14, 3932 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval), 3933 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_IO, 3934 .writefn = gt_hyp_cval_write, .raw_writefn = raw_write }, 3935 { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH, 3936 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0, 3937 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW, 3938 .resetfn = gt_hyp_timer_reset, 3939 .readfn = gt_hyp_tval_read, .writefn = gt_hyp_tval_write }, 3940 { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, 3941 .type = ARM_CP_IO, 3942 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, 3943 .access = PL2_RW, 3944 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].ctl), 3945 .resetvalue = 0, 3946 .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write }, 3947 #endif 3948 /* The only field of MDCR_EL2 that has a defined architectural reset value 3949 * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we 3950 * don't impelment any PMU event counters, so using zero as a reset 3951 * value for MDCR_EL2 is okay 3952 */ 3953 { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, 3954 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, 3955 .access = PL2_RW, .resetvalue = 0, 3956 .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), }, 3957 { .name = "HPFAR", .state = ARM_CP_STATE_AA32, 3958 .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, 3959 .access = PL2_RW, .accessfn = access_el3_aa32ns, 3960 .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, 3961 { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64, 3962 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, 3963 .access = PL2_RW, 3964 .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, 3965 { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH, 3966 .cp = 15, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3, 3967 .access = PL2_RW, 3968 .fieldoffset = offsetof(CPUARMState, cp15.hstr_el2) }, 3969 REGINFO_SENTINEL 3970 }; 3971 3972 static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri, 3973 bool isread) 3974 { 3975 /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2. 3976 * At Secure EL1 it traps to EL3. 3977 */ 3978 if (arm_current_el(env) == 3) { 3979 return CP_ACCESS_OK; 3980 } 3981 if (arm_is_secure_below_el3(env)) { 3982 return CP_ACCESS_TRAP_EL3; 3983 } 3984 /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */ 3985 if (isread) { 3986 return CP_ACCESS_OK; 3987 } 3988 return CP_ACCESS_TRAP_UNCATEGORIZED; 3989 } 3990 3991 static const ARMCPRegInfo el3_cp_reginfo[] = { 3992 { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64, 3993 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0, 3994 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), 3995 .resetvalue = 0, .writefn = scr_write }, 3996 { .name = "SCR", .type = ARM_CP_ALIAS, 3997 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0, 3998 .access = PL1_RW, .accessfn = access_trap_aa32s_el1, 3999 .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), 4000 .writefn = scr_write }, 4001 { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64, 4002 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1, 4003 .access = PL3_RW, .resetvalue = 0, 4004 .fieldoffset = offsetof(CPUARMState, cp15.sder) }, 4005 { .name = "SDER", 4006 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1, 4007 .access = PL3_RW, .resetvalue = 0, 4008 .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) }, 4009 { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, 4010 .access = PL1_RW, .accessfn = access_trap_aa32s_el1, 4011 .writefn = vbar_write, .resetvalue = 0, 4012 .fieldoffset = offsetof(CPUARMState, cp15.mvbar) }, 4013 { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64, 4014 .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0, 4015 .access = PL3_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, 4016 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) }, 4017 { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64, 4018 .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2, 4019 .access = PL3_RW, 4020 /* no .writefn needed as this can't cause an ASID change; 4021 * we must provide a .raw_writefn and .resetfn because we handle 4022 * reset and migration for the AArch32 TTBCR(S), which might be 4023 * using mask and base_mask. 4024 */ 4025 .resetfn = vmsa_ttbcr_reset, .raw_writefn = vmsa_ttbcr_raw_write, 4026 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) }, 4027 { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64, 4028 .type = ARM_CP_ALIAS, 4029 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1, 4030 .access = PL3_RW, 4031 .fieldoffset = offsetof(CPUARMState, elr_el[3]) }, 4032 { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64, 4033 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0, 4034 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) }, 4035 { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64, 4036 .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0, 4037 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) }, 4038 { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64, 4039 .type = ARM_CP_ALIAS, 4040 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0, 4041 .access = PL3_RW, 4042 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_MON]) }, 4043 { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64, 4044 .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0, 4045 .access = PL3_RW, .writefn = vbar_write, 4046 .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]), 4047 .resetvalue = 0 }, 4048 { .name = "CPTR_EL3", .state = ARM_CP_STATE_AA64, 4049 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2, 4050 .access = PL3_RW, .accessfn = cptr_access, .resetvalue = 0, 4051 .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) }, 4052 { .name = "TPIDR_EL3", .state = ARM_CP_STATE_AA64, 4053 .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2, 4054 .access = PL3_RW, .resetvalue = 0, 4055 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) }, 4056 { .name = "AMAIR_EL3", .state = ARM_CP_STATE_AA64, 4057 .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0, 4058 .access = PL3_RW, .type = ARM_CP_CONST, 4059 .resetvalue = 0 }, 4060 { .name = "AFSR0_EL3", .state = ARM_CP_STATE_BOTH, 4061 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0, 4062 .access = PL3_RW, .type = ARM_CP_CONST, 4063 .resetvalue = 0 }, 4064 { .name = "AFSR1_EL3", .state = ARM_CP_STATE_BOTH, 4065 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1, 4066 .access = PL3_RW, .type = ARM_CP_CONST, 4067 .resetvalue = 0 }, 4068 { .name = "TLBI_ALLE3IS", .state = ARM_CP_STATE_AA64, 4069 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 0, 4070 .access = PL3_W, .type = ARM_CP_NO_RAW, 4071 .writefn = tlbi_aa64_alle3is_write }, 4072 { .name = "TLBI_VAE3IS", .state = ARM_CP_STATE_AA64, 4073 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 1, 4074 .access = PL3_W, .type = ARM_CP_NO_RAW, 4075 .writefn = tlbi_aa64_vae3is_write }, 4076 { .name = "TLBI_VALE3IS", .state = ARM_CP_STATE_AA64, 4077 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 5, 4078 .access = PL3_W, .type = ARM_CP_NO_RAW, 4079 .writefn = tlbi_aa64_vae3is_write }, 4080 { .name = "TLBI_ALLE3", .state = ARM_CP_STATE_AA64, 4081 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 0, 4082 .access = PL3_W, .type = ARM_CP_NO_RAW, 4083 .writefn = tlbi_aa64_alle3_write }, 4084 { .name = "TLBI_VAE3", .state = ARM_CP_STATE_AA64, 4085 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 1, 4086 .access = PL3_W, .type = ARM_CP_NO_RAW, 4087 .writefn = tlbi_aa64_vae3_write }, 4088 { .name = "TLBI_VALE3", .state = ARM_CP_STATE_AA64, 4089 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5, 4090 .access = PL3_W, .type = ARM_CP_NO_RAW, 4091 .writefn = tlbi_aa64_vae3_write }, 4092 REGINFO_SENTINEL 4093 }; 4094 4095 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, 4096 bool isread) 4097 { 4098 /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64, 4099 * but the AArch32 CTR has its own reginfo struct) 4100 */ 4101 if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCT)) { 4102 return CP_ACCESS_TRAP; 4103 } 4104 return CP_ACCESS_OK; 4105 } 4106 4107 static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri, 4108 uint64_t value) 4109 { 4110 /* Writes to OSLAR_EL1 may update the OS lock status, which can be 4111 * read via a bit in OSLSR_EL1. 4112 */ 4113 int oslock; 4114 4115 if (ri->state == ARM_CP_STATE_AA32) { 4116 oslock = (value == 0xC5ACCE55); 4117 } else { 4118 oslock = value & 1; 4119 } 4120 4121 env->cp15.oslsr_el1 = deposit32(env->cp15.oslsr_el1, 1, 1, oslock); 4122 } 4123 4124 static const ARMCPRegInfo debug_cp_reginfo[] = { 4125 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped 4126 * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1; 4127 * unlike DBGDRAR it is never accessible from EL0. 4128 * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64 4129 * accessor. 4130 */ 4131 { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0, 4132 .access = PL0_R, .accessfn = access_tdra, 4133 .type = ARM_CP_CONST, .resetvalue = 0 }, 4134 { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64, 4135 .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, 4136 .access = PL1_R, .accessfn = access_tdra, 4137 .type = ARM_CP_CONST, .resetvalue = 0 }, 4138 { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, 4139 .access = PL0_R, .accessfn = access_tdra, 4140 .type = ARM_CP_CONST, .resetvalue = 0 }, 4141 /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */ 4142 { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH, 4143 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, 4144 .access = PL1_RW, .accessfn = access_tda, 4145 .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), 4146 .resetvalue = 0 }, 4147 /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1. 4148 * We don't implement the configurable EL0 access. 4149 */ 4150 { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH, 4151 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, 4152 .type = ARM_CP_ALIAS, 4153 .access = PL1_R, .accessfn = access_tda, 4154 .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), }, 4155 { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH, 4156 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4, 4157 .access = PL1_W, .type = ARM_CP_NO_RAW, 4158 .accessfn = access_tdosa, 4159 .writefn = oslar_write }, 4160 { .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH, 4161 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4, 4162 .access = PL1_R, .resetvalue = 10, 4163 .accessfn = access_tdosa, 4164 .fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) }, 4165 /* Dummy OSDLR_EL1: 32-bit Linux will read this */ 4166 { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH, 4167 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4, 4168 .access = PL1_RW, .accessfn = access_tdosa, 4169 .type = ARM_CP_NOP }, 4170 /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't 4171 * implement vector catch debug events yet. 4172 */ 4173 { .name = "DBGVCR", 4174 .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, 4175 .access = PL1_RW, .accessfn = access_tda, 4176 .type = ARM_CP_NOP }, 4177 /* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor 4178 * to save and restore a 32-bit guest's DBGVCR) 4179 */ 4180 { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64, 4181 .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0, 4182 .access = PL2_RW, .accessfn = access_tda, 4183 .type = ARM_CP_NOP }, 4184 /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications 4185 * Channel but Linux may try to access this register. The 32-bit 4186 * alias is DBGDCCINT. 4187 */ 4188 { .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH, 4189 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, 4190 .access = PL1_RW, .accessfn = access_tda, 4191 .type = ARM_CP_NOP }, 4192 REGINFO_SENTINEL 4193 }; 4194 4195 static const ARMCPRegInfo debug_lpae_cp_reginfo[] = { 4196 /* 64 bit access versions of the (dummy) debug registers */ 4197 { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0, 4198 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, 4199 { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0, 4200 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, 4201 REGINFO_SENTINEL 4202 }; 4203 4204 void hw_watchpoint_update(ARMCPU *cpu, int n) 4205 { 4206 CPUARMState *env = &cpu->env; 4207 vaddr len = 0; 4208 vaddr wvr = env->cp15.dbgwvr[n]; 4209 uint64_t wcr = env->cp15.dbgwcr[n]; 4210 int mask; 4211 int flags = BP_CPU | BP_STOP_BEFORE_ACCESS; 4212 4213 if (env->cpu_watchpoint[n]) { 4214 cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]); 4215 env->cpu_watchpoint[n] = NULL; 4216 } 4217 4218 if (!extract64(wcr, 0, 1)) { 4219 /* E bit clear : watchpoint disabled */ 4220 return; 4221 } 4222 4223 switch (extract64(wcr, 3, 2)) { 4224 case 0: 4225 /* LSC 00 is reserved and must behave as if the wp is disabled */ 4226 return; 4227 case 1: 4228 flags |= BP_MEM_READ; 4229 break; 4230 case 2: 4231 flags |= BP_MEM_WRITE; 4232 break; 4233 case 3: 4234 flags |= BP_MEM_ACCESS; 4235 break; 4236 } 4237 4238 /* Attempts to use both MASK and BAS fields simultaneously are 4239 * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case, 4240 * thus generating a watchpoint for every byte in the masked region. 4241 */ 4242 mask = extract64(wcr, 24, 4); 4243 if (mask == 1 || mask == 2) { 4244 /* Reserved values of MASK; we must act as if the mask value was 4245 * some non-reserved value, or as if the watchpoint were disabled. 4246 * We choose the latter. 4247 */ 4248 return; 4249 } else if (mask) { 4250 /* Watchpoint covers an aligned area up to 2GB in size */ 4251 len = 1ULL << mask; 4252 /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE 4253 * whether the watchpoint fires when the unmasked bits match; we opt 4254 * to generate the exceptions. 4255 */ 4256 wvr &= ~(len - 1); 4257 } else { 4258 /* Watchpoint covers bytes defined by the byte address select bits */ 4259 int bas = extract64(wcr, 5, 8); 4260 int basstart; 4261 4262 if (bas == 0) { 4263 /* This must act as if the watchpoint is disabled */ 4264 return; 4265 } 4266 4267 if (extract64(wvr, 2, 1)) { 4268 /* Deprecated case of an only 4-aligned address. BAS[7:4] are 4269 * ignored, and BAS[3:0] define which bytes to watch. 4270 */ 4271 bas &= 0xf; 4272 } 4273 /* The BAS bits are supposed to be programmed to indicate a contiguous 4274 * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether 4275 * we fire for each byte in the word/doubleword addressed by the WVR. 4276 * We choose to ignore any non-zero bits after the first range of 1s. 4277 */ 4278 basstart = ctz32(bas); 4279 len = cto32(bas >> basstart); 4280 wvr += basstart; 4281 } 4282 4283 cpu_watchpoint_insert(CPU(cpu), wvr, len, flags, 4284 &env->cpu_watchpoint[n]); 4285 } 4286 4287 void hw_watchpoint_update_all(ARMCPU *cpu) 4288 { 4289 int i; 4290 CPUARMState *env = &cpu->env; 4291 4292 /* Completely clear out existing QEMU watchpoints and our array, to 4293 * avoid possible stale entries following migration load. 4294 */ 4295 cpu_watchpoint_remove_all(CPU(cpu), BP_CPU); 4296 memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint)); 4297 4298 for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) { 4299 hw_watchpoint_update(cpu, i); 4300 } 4301 } 4302 4303 static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri, 4304 uint64_t value) 4305 { 4306 ARMCPU *cpu = arm_env_get_cpu(env); 4307 int i = ri->crm; 4308 4309 /* Bits [63:49] are hardwired to the value of bit [48]; that is, the 4310 * register reads and behaves as if values written are sign extended. 4311 * Bits [1:0] are RES0. 4312 */ 4313 value = sextract64(value, 0, 49) & ~3ULL; 4314 4315 raw_write(env, ri, value); 4316 hw_watchpoint_update(cpu, i); 4317 } 4318 4319 static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri, 4320 uint64_t value) 4321 { 4322 ARMCPU *cpu = arm_env_get_cpu(env); 4323 int i = ri->crm; 4324 4325 raw_write(env, ri, value); 4326 hw_watchpoint_update(cpu, i); 4327 } 4328 4329 void hw_breakpoint_update(ARMCPU *cpu, int n) 4330 { 4331 CPUARMState *env = &cpu->env; 4332 uint64_t bvr = env->cp15.dbgbvr[n]; 4333 uint64_t bcr = env->cp15.dbgbcr[n]; 4334 vaddr addr; 4335 int bt; 4336 int flags = BP_CPU; 4337 4338 if (env->cpu_breakpoint[n]) { 4339 cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]); 4340 env->cpu_breakpoint[n] = NULL; 4341 } 4342 4343 if (!extract64(bcr, 0, 1)) { 4344 /* E bit clear : watchpoint disabled */ 4345 return; 4346 } 4347 4348 bt = extract64(bcr, 20, 4); 4349 4350 switch (bt) { 4351 case 4: /* unlinked address mismatch (reserved if AArch64) */ 4352 case 5: /* linked address mismatch (reserved if AArch64) */ 4353 qemu_log_mask(LOG_UNIMP, 4354 "arm: address mismatch breakpoint types not implemented"); 4355 return; 4356 case 0: /* unlinked address match */ 4357 case 1: /* linked address match */ 4358 { 4359 /* Bits [63:49] are hardwired to the value of bit [48]; that is, 4360 * we behave as if the register was sign extended. Bits [1:0] are 4361 * RES0. The BAS field is used to allow setting breakpoints on 16 4362 * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether 4363 * a bp will fire if the addresses covered by the bp and the addresses 4364 * covered by the insn overlap but the insn doesn't start at the 4365 * start of the bp address range. We choose to require the insn and 4366 * the bp to have the same address. The constraints on writing to 4367 * BAS enforced in dbgbcr_write mean we have only four cases: 4368 * 0b0000 => no breakpoint 4369 * 0b0011 => breakpoint on addr 4370 * 0b1100 => breakpoint on addr + 2 4371 * 0b1111 => breakpoint on addr 4372 * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c). 4373 */ 4374 int bas = extract64(bcr, 5, 4); 4375 addr = sextract64(bvr, 0, 49) & ~3ULL; 4376 if (bas == 0) { 4377 return; 4378 } 4379 if (bas == 0xc) { 4380 addr += 2; 4381 } 4382 break; 4383 } 4384 case 2: /* unlinked context ID match */ 4385 case 8: /* unlinked VMID match (reserved if no EL2) */ 4386 case 10: /* unlinked context ID and VMID match (reserved if no EL2) */ 4387 qemu_log_mask(LOG_UNIMP, 4388 "arm: unlinked context breakpoint types not implemented"); 4389 return; 4390 case 9: /* linked VMID match (reserved if no EL2) */ 4391 case 11: /* linked context ID and VMID match (reserved if no EL2) */ 4392 case 3: /* linked context ID match */ 4393 default: 4394 /* We must generate no events for Linked context matches (unless 4395 * they are linked to by some other bp/wp, which is handled in 4396 * updates for the linking bp/wp). We choose to also generate no events 4397 * for reserved values. 4398 */ 4399 return; 4400 } 4401 4402 cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]); 4403 } 4404 4405 void hw_breakpoint_update_all(ARMCPU *cpu) 4406 { 4407 int i; 4408 CPUARMState *env = &cpu->env; 4409 4410 /* Completely clear out existing QEMU breakpoints and our array, to 4411 * avoid possible stale entries following migration load. 4412 */ 4413 cpu_breakpoint_remove_all(CPU(cpu), BP_CPU); 4414 memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint)); 4415 4416 for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) { 4417 hw_breakpoint_update(cpu, i); 4418 } 4419 } 4420 4421 static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri, 4422 uint64_t value) 4423 { 4424 ARMCPU *cpu = arm_env_get_cpu(env); 4425 int i = ri->crm; 4426 4427 raw_write(env, ri, value); 4428 hw_breakpoint_update(cpu, i); 4429 } 4430 4431 static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, 4432 uint64_t value) 4433 { 4434 ARMCPU *cpu = arm_env_get_cpu(env); 4435 int i = ri->crm; 4436 4437 /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only 4438 * copy of BAS[0]. 4439 */ 4440 value = deposit64(value, 6, 1, extract64(value, 5, 1)); 4441 value = deposit64(value, 8, 1, extract64(value, 7, 1)); 4442 4443 raw_write(env, ri, value); 4444 hw_breakpoint_update(cpu, i); 4445 } 4446 4447 static void define_debug_regs(ARMCPU *cpu) 4448 { 4449 /* Define v7 and v8 architectural debug registers. 4450 * These are just dummy implementations for now. 4451 */ 4452 int i; 4453 int wrps, brps, ctx_cmps; 4454 ARMCPRegInfo dbgdidr = { 4455 .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, 4456 .access = PL0_R, .accessfn = access_tda, 4457 .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr, 4458 }; 4459 4460 /* Note that all these register fields hold "number of Xs minus 1". */ 4461 brps = extract32(cpu->dbgdidr, 24, 4); 4462 wrps = extract32(cpu->dbgdidr, 28, 4); 4463 ctx_cmps = extract32(cpu->dbgdidr, 20, 4); 4464 4465 assert(ctx_cmps <= brps); 4466 4467 /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties 4468 * of the debug registers such as number of breakpoints; 4469 * check that if they both exist then they agree. 4470 */ 4471 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 4472 assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps); 4473 assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps); 4474 assert(extract32(cpu->id_aa64dfr0, 28, 4) == ctx_cmps); 4475 } 4476 4477 define_one_arm_cp_reg(cpu, &dbgdidr); 4478 define_arm_cp_regs(cpu, debug_cp_reginfo); 4479 4480 if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) { 4481 define_arm_cp_regs(cpu, debug_lpae_cp_reginfo); 4482 } 4483 4484 for (i = 0; i < brps + 1; i++) { 4485 ARMCPRegInfo dbgregs[] = { 4486 { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH, 4487 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4, 4488 .access = PL1_RW, .accessfn = access_tda, 4489 .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]), 4490 .writefn = dbgbvr_write, .raw_writefn = raw_write 4491 }, 4492 { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH, 4493 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5, 4494 .access = PL1_RW, .accessfn = access_tda, 4495 .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]), 4496 .writefn = dbgbcr_write, .raw_writefn = raw_write 4497 }, 4498 REGINFO_SENTINEL 4499 }; 4500 define_arm_cp_regs(cpu, dbgregs); 4501 } 4502 4503 for (i = 0; i < wrps + 1; i++) { 4504 ARMCPRegInfo dbgregs[] = { 4505 { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH, 4506 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6, 4507 .access = PL1_RW, .accessfn = access_tda, 4508 .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]), 4509 .writefn = dbgwvr_write, .raw_writefn = raw_write 4510 }, 4511 { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH, 4512 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7, 4513 .access = PL1_RW, .accessfn = access_tda, 4514 .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]), 4515 .writefn = dbgwcr_write, .raw_writefn = raw_write 4516 }, 4517 REGINFO_SENTINEL 4518 }; 4519 define_arm_cp_regs(cpu, dbgregs); 4520 } 4521 } 4522 4523 void register_cp_regs_for_features(ARMCPU *cpu) 4524 { 4525 /* Register all the coprocessor registers based on feature bits */ 4526 CPUARMState *env = &cpu->env; 4527 if (arm_feature(env, ARM_FEATURE_M)) { 4528 /* M profile has no coprocessor registers */ 4529 return; 4530 } 4531 4532 define_arm_cp_regs(cpu, cp_reginfo); 4533 if (!arm_feature(env, ARM_FEATURE_V8)) { 4534 /* Must go early as it is full of wildcards that may be 4535 * overridden by later definitions. 4536 */ 4537 define_arm_cp_regs(cpu, not_v8_cp_reginfo); 4538 } 4539 4540 if (arm_feature(env, ARM_FEATURE_V6)) { 4541 /* The ID registers all have impdef reset values */ 4542 ARMCPRegInfo v6_idregs[] = { 4543 { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH, 4544 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, 4545 .access = PL1_R, .type = ARM_CP_CONST, 4546 .resetvalue = cpu->id_pfr0 }, 4547 { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH, 4548 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1, 4549 .access = PL1_R, .type = ARM_CP_CONST, 4550 .resetvalue = cpu->id_pfr1 }, 4551 { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH, 4552 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2, 4553 .access = PL1_R, .type = ARM_CP_CONST, 4554 .resetvalue = cpu->id_dfr0 }, 4555 { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH, 4556 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3, 4557 .access = PL1_R, .type = ARM_CP_CONST, 4558 .resetvalue = cpu->id_afr0 }, 4559 { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH, 4560 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4, 4561 .access = PL1_R, .type = ARM_CP_CONST, 4562 .resetvalue = cpu->id_mmfr0 }, 4563 { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH, 4564 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5, 4565 .access = PL1_R, .type = ARM_CP_CONST, 4566 .resetvalue = cpu->id_mmfr1 }, 4567 { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH, 4568 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6, 4569 .access = PL1_R, .type = ARM_CP_CONST, 4570 .resetvalue = cpu->id_mmfr2 }, 4571 { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH, 4572 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7, 4573 .access = PL1_R, .type = ARM_CP_CONST, 4574 .resetvalue = cpu->id_mmfr3 }, 4575 { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH, 4576 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, 4577 .access = PL1_R, .type = ARM_CP_CONST, 4578 .resetvalue = cpu->id_isar0 }, 4579 { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH, 4580 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1, 4581 .access = PL1_R, .type = ARM_CP_CONST, 4582 .resetvalue = cpu->id_isar1 }, 4583 { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH, 4584 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, 4585 .access = PL1_R, .type = ARM_CP_CONST, 4586 .resetvalue = cpu->id_isar2 }, 4587 { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH, 4588 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3, 4589 .access = PL1_R, .type = ARM_CP_CONST, 4590 .resetvalue = cpu->id_isar3 }, 4591 { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH, 4592 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4, 4593 .access = PL1_R, .type = ARM_CP_CONST, 4594 .resetvalue = cpu->id_isar4 }, 4595 { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH, 4596 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5, 4597 .access = PL1_R, .type = ARM_CP_CONST, 4598 .resetvalue = cpu->id_isar5 }, 4599 { .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH, 4600 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6, 4601 .access = PL1_R, .type = ARM_CP_CONST, 4602 .resetvalue = cpu->id_mmfr4 }, 4603 /* 7 is as yet unallocated and must RAZ */ 4604 { .name = "ID_ISAR7_RESERVED", .state = ARM_CP_STATE_BOTH, 4605 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7, 4606 .access = PL1_R, .type = ARM_CP_CONST, 4607 .resetvalue = 0 }, 4608 REGINFO_SENTINEL 4609 }; 4610 define_arm_cp_regs(cpu, v6_idregs); 4611 define_arm_cp_regs(cpu, v6_cp_reginfo); 4612 } else { 4613 define_arm_cp_regs(cpu, not_v6_cp_reginfo); 4614 } 4615 if (arm_feature(env, ARM_FEATURE_V6K)) { 4616 define_arm_cp_regs(cpu, v6k_cp_reginfo); 4617 } 4618 if (arm_feature(env, ARM_FEATURE_V7MP) && 4619 !arm_feature(env, ARM_FEATURE_PMSA)) { 4620 define_arm_cp_regs(cpu, v7mp_cp_reginfo); 4621 } 4622 if (arm_feature(env, ARM_FEATURE_V7)) { 4623 /* v7 performance monitor control register: same implementor 4624 * field as main ID register, and we implement only the cycle 4625 * count register. 4626 */ 4627 #ifndef CONFIG_USER_ONLY 4628 ARMCPRegInfo pmcr = { 4629 .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0, 4630 .access = PL0_RW, 4631 .type = ARM_CP_IO | ARM_CP_ALIAS, 4632 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr), 4633 .accessfn = pmreg_access, .writefn = pmcr_write, 4634 .raw_writefn = raw_write, 4635 }; 4636 ARMCPRegInfo pmcr64 = { 4637 .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64, 4638 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0, 4639 .access = PL0_RW, .accessfn = pmreg_access, 4640 .type = ARM_CP_IO, 4641 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr), 4642 .resetvalue = cpu->midr & 0xff000000, 4643 .writefn = pmcr_write, .raw_writefn = raw_write, 4644 }; 4645 define_one_arm_cp_reg(cpu, &pmcr); 4646 define_one_arm_cp_reg(cpu, &pmcr64); 4647 #endif 4648 ARMCPRegInfo clidr = { 4649 .name = "CLIDR", .state = ARM_CP_STATE_BOTH, 4650 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1, 4651 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr 4652 }; 4653 define_one_arm_cp_reg(cpu, &clidr); 4654 define_arm_cp_regs(cpu, v7_cp_reginfo); 4655 define_debug_regs(cpu); 4656 } else { 4657 define_arm_cp_regs(cpu, not_v7_cp_reginfo); 4658 } 4659 if (arm_feature(env, ARM_FEATURE_V8)) { 4660 /* AArch64 ID registers, which all have impdef reset values. 4661 * Note that within the ID register ranges the unused slots 4662 * must all RAZ, not UNDEF; future architecture versions may 4663 * define new registers here. 4664 */ 4665 ARMCPRegInfo v8_idregs[] = { 4666 { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64, 4667 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0, 4668 .access = PL1_R, .type = ARM_CP_CONST, 4669 .resetvalue = cpu->id_aa64pfr0 }, 4670 { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64, 4671 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1, 4672 .access = PL1_R, .type = ARM_CP_CONST, 4673 .resetvalue = cpu->id_aa64pfr1}, 4674 { .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4675 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2, 4676 .access = PL1_R, .type = ARM_CP_CONST, 4677 .resetvalue = 0 }, 4678 { .name = "ID_AA64PFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4679 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3, 4680 .access = PL1_R, .type = ARM_CP_CONST, 4681 .resetvalue = 0 }, 4682 { .name = "ID_AA64PFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4683 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4, 4684 .access = PL1_R, .type = ARM_CP_CONST, 4685 .resetvalue = 0 }, 4686 { .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4687 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5, 4688 .access = PL1_R, .type = ARM_CP_CONST, 4689 .resetvalue = 0 }, 4690 { .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4691 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6, 4692 .access = PL1_R, .type = ARM_CP_CONST, 4693 .resetvalue = 0 }, 4694 { .name = "ID_AA64PFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4695 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7, 4696 .access = PL1_R, .type = ARM_CP_CONST, 4697 .resetvalue = 0 }, 4698 { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64, 4699 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0, 4700 .access = PL1_R, .type = ARM_CP_CONST, 4701 .resetvalue = cpu->id_aa64dfr0 }, 4702 { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64, 4703 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1, 4704 .access = PL1_R, .type = ARM_CP_CONST, 4705 .resetvalue = cpu->id_aa64dfr1 }, 4706 { .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4707 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2, 4708 .access = PL1_R, .type = ARM_CP_CONST, 4709 .resetvalue = 0 }, 4710 { .name = "ID_AA64DFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4711 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 3, 4712 .access = PL1_R, .type = ARM_CP_CONST, 4713 .resetvalue = 0 }, 4714 { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64, 4715 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4, 4716 .access = PL1_R, .type = ARM_CP_CONST, 4717 .resetvalue = cpu->id_aa64afr0 }, 4718 { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64, 4719 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5, 4720 .access = PL1_R, .type = ARM_CP_CONST, 4721 .resetvalue = cpu->id_aa64afr1 }, 4722 { .name = "ID_AA64AFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4723 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6, 4724 .access = PL1_R, .type = ARM_CP_CONST, 4725 .resetvalue = 0 }, 4726 { .name = "ID_AA64AFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4727 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 7, 4728 .access = PL1_R, .type = ARM_CP_CONST, 4729 .resetvalue = 0 }, 4730 { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64, 4731 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0, 4732 .access = PL1_R, .type = ARM_CP_CONST, 4733 .resetvalue = cpu->id_aa64isar0 }, 4734 { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64, 4735 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1, 4736 .access = PL1_R, .type = ARM_CP_CONST, 4737 .resetvalue = cpu->id_aa64isar1 }, 4738 { .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4739 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2, 4740 .access = PL1_R, .type = ARM_CP_CONST, 4741 .resetvalue = 0 }, 4742 { .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4743 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3, 4744 .access = PL1_R, .type = ARM_CP_CONST, 4745 .resetvalue = 0 }, 4746 { .name = "ID_AA64ISAR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4747 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4, 4748 .access = PL1_R, .type = ARM_CP_CONST, 4749 .resetvalue = 0 }, 4750 { .name = "ID_AA64ISAR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4751 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 5, 4752 .access = PL1_R, .type = ARM_CP_CONST, 4753 .resetvalue = 0 }, 4754 { .name = "ID_AA64ISAR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4755 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 6, 4756 .access = PL1_R, .type = ARM_CP_CONST, 4757 .resetvalue = 0 }, 4758 { .name = "ID_AA64ISAR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4759 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 7, 4760 .access = PL1_R, .type = ARM_CP_CONST, 4761 .resetvalue = 0 }, 4762 { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64, 4763 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, 4764 .access = PL1_R, .type = ARM_CP_CONST, 4765 .resetvalue = cpu->id_aa64mmfr0 }, 4766 { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64, 4767 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1, 4768 .access = PL1_R, .type = ARM_CP_CONST, 4769 .resetvalue = cpu->id_aa64mmfr1 }, 4770 { .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4771 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2, 4772 .access = PL1_R, .type = ARM_CP_CONST, 4773 .resetvalue = 0 }, 4774 { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4775 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3, 4776 .access = PL1_R, .type = ARM_CP_CONST, 4777 .resetvalue = 0 }, 4778 { .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4779 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4, 4780 .access = PL1_R, .type = ARM_CP_CONST, 4781 .resetvalue = 0 }, 4782 { .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4783 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5, 4784 .access = PL1_R, .type = ARM_CP_CONST, 4785 .resetvalue = 0 }, 4786 { .name = "ID_AA64MMFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4787 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 6, 4788 .access = PL1_R, .type = ARM_CP_CONST, 4789 .resetvalue = 0 }, 4790 { .name = "ID_AA64MMFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4791 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 7, 4792 .access = PL1_R, .type = ARM_CP_CONST, 4793 .resetvalue = 0 }, 4794 { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64, 4795 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0, 4796 .access = PL1_R, .type = ARM_CP_CONST, 4797 .resetvalue = cpu->mvfr0 }, 4798 { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64, 4799 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1, 4800 .access = PL1_R, .type = ARM_CP_CONST, 4801 .resetvalue = cpu->mvfr1 }, 4802 { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64, 4803 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2, 4804 .access = PL1_R, .type = ARM_CP_CONST, 4805 .resetvalue = cpu->mvfr2 }, 4806 { .name = "MVFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4807 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3, 4808 .access = PL1_R, .type = ARM_CP_CONST, 4809 .resetvalue = 0 }, 4810 { .name = "MVFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4811 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4, 4812 .access = PL1_R, .type = ARM_CP_CONST, 4813 .resetvalue = 0 }, 4814 { .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4815 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5, 4816 .access = PL1_R, .type = ARM_CP_CONST, 4817 .resetvalue = 0 }, 4818 { .name = "MVFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4819 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6, 4820 .access = PL1_R, .type = ARM_CP_CONST, 4821 .resetvalue = 0 }, 4822 { .name = "MVFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4823 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7, 4824 .access = PL1_R, .type = ARM_CP_CONST, 4825 .resetvalue = 0 }, 4826 { .name = "PMCEID0", .state = ARM_CP_STATE_AA32, 4827 .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6, 4828 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, 4829 .resetvalue = cpu->pmceid0 }, 4830 { .name = "PMCEID0_EL0", .state = ARM_CP_STATE_AA64, 4831 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6, 4832 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, 4833 .resetvalue = cpu->pmceid0 }, 4834 { .name = "PMCEID1", .state = ARM_CP_STATE_AA32, 4835 .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 7, 4836 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, 4837 .resetvalue = cpu->pmceid1 }, 4838 { .name = "PMCEID1_EL0", .state = ARM_CP_STATE_AA64, 4839 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7, 4840 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, 4841 .resetvalue = cpu->pmceid1 }, 4842 REGINFO_SENTINEL 4843 }; 4844 /* RVBAR_EL1 is only implemented if EL1 is the highest EL */ 4845 if (!arm_feature(env, ARM_FEATURE_EL3) && 4846 !arm_feature(env, ARM_FEATURE_EL2)) { 4847 ARMCPRegInfo rvbar = { 4848 .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64, 4849 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, 4850 .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar 4851 }; 4852 define_one_arm_cp_reg(cpu, &rvbar); 4853 } 4854 define_arm_cp_regs(cpu, v8_idregs); 4855 define_arm_cp_regs(cpu, v8_cp_reginfo); 4856 } 4857 if (arm_feature(env, ARM_FEATURE_EL2)) { 4858 uint64_t vmpidr_def = mpidr_read_val(env); 4859 ARMCPRegInfo vpidr_regs[] = { 4860 { .name = "VPIDR", .state = ARM_CP_STATE_AA32, 4861 .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, 4862 .access = PL2_RW, .accessfn = access_el3_aa32ns, 4863 .resetvalue = cpu->midr, 4864 .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, 4865 { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64, 4866 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, 4867 .access = PL2_RW, .resetvalue = cpu->midr, 4868 .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, 4869 { .name = "VMPIDR", .state = ARM_CP_STATE_AA32, 4870 .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, 4871 .access = PL2_RW, .accessfn = access_el3_aa32ns, 4872 .resetvalue = vmpidr_def, 4873 .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) }, 4874 { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64, 4875 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, 4876 .access = PL2_RW, 4877 .resetvalue = vmpidr_def, 4878 .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) }, 4879 REGINFO_SENTINEL 4880 }; 4881 define_arm_cp_regs(cpu, vpidr_regs); 4882 define_arm_cp_regs(cpu, el2_cp_reginfo); 4883 /* RVBAR_EL2 is only implemented if EL2 is the highest EL */ 4884 if (!arm_feature(env, ARM_FEATURE_EL3)) { 4885 ARMCPRegInfo rvbar = { 4886 .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64, 4887 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1, 4888 .type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar 4889 }; 4890 define_one_arm_cp_reg(cpu, &rvbar); 4891 } 4892 } else { 4893 /* If EL2 is missing but higher ELs are enabled, we need to 4894 * register the no_el2 reginfos. 4895 */ 4896 if (arm_feature(env, ARM_FEATURE_EL3)) { 4897 /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value 4898 * of MIDR_EL1 and MPIDR_EL1. 4899 */ 4900 ARMCPRegInfo vpidr_regs[] = { 4901 { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH, 4902 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, 4903 .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, 4904 .type = ARM_CP_CONST, .resetvalue = cpu->midr, 4905 .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, 4906 { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH, 4907 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, 4908 .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, 4909 .type = ARM_CP_NO_RAW, 4910 .writefn = arm_cp_write_ignore, .readfn = mpidr_read }, 4911 REGINFO_SENTINEL 4912 }; 4913 define_arm_cp_regs(cpu, vpidr_regs); 4914 define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo); 4915 } 4916 } 4917 if (arm_feature(env, ARM_FEATURE_EL3)) { 4918 define_arm_cp_regs(cpu, el3_cp_reginfo); 4919 ARMCPRegInfo el3_regs[] = { 4920 { .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64, 4921 .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1, 4922 .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar }, 4923 { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64, 4924 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0, 4925 .access = PL3_RW, 4926 .raw_writefn = raw_write, .writefn = sctlr_write, 4927 .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]), 4928 .resetvalue = cpu->reset_sctlr }, 4929 REGINFO_SENTINEL 4930 }; 4931 4932 define_arm_cp_regs(cpu, el3_regs); 4933 } 4934 /* The behaviour of NSACR is sufficiently various that we don't 4935 * try to describe it in a single reginfo: 4936 * if EL3 is 64 bit, then trap to EL3 from S EL1, 4937 * reads as constant 0xc00 from NS EL1 and NS EL2 4938 * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2 4939 * if v7 without EL3, register doesn't exist 4940 * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2 4941 */ 4942 if (arm_feature(env, ARM_FEATURE_EL3)) { 4943 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 4944 ARMCPRegInfo nsacr = { 4945 .name = "NSACR", .type = ARM_CP_CONST, 4946 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, 4947 .access = PL1_RW, .accessfn = nsacr_access, 4948 .resetvalue = 0xc00 4949 }; 4950 define_one_arm_cp_reg(cpu, &nsacr); 4951 } else { 4952 ARMCPRegInfo nsacr = { 4953 .name = "NSACR", 4954 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, 4955 .access = PL3_RW | PL1_R, 4956 .resetvalue = 0, 4957 .fieldoffset = offsetof(CPUARMState, cp15.nsacr) 4958 }; 4959 define_one_arm_cp_reg(cpu, &nsacr); 4960 } 4961 } else { 4962 if (arm_feature(env, ARM_FEATURE_V8)) { 4963 ARMCPRegInfo nsacr = { 4964 .name = "NSACR", .type = ARM_CP_CONST, 4965 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, 4966 .access = PL1_R, 4967 .resetvalue = 0xc00 4968 }; 4969 define_one_arm_cp_reg(cpu, &nsacr); 4970 } 4971 } 4972 4973 if (arm_feature(env, ARM_FEATURE_PMSA)) { 4974 if (arm_feature(env, ARM_FEATURE_V6)) { 4975 /* PMSAv6 not implemented */ 4976 assert(arm_feature(env, ARM_FEATURE_V7)); 4977 define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); 4978 define_arm_cp_regs(cpu, pmsav7_cp_reginfo); 4979 } else { 4980 define_arm_cp_regs(cpu, pmsav5_cp_reginfo); 4981 } 4982 } else { 4983 define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); 4984 define_arm_cp_regs(cpu, vmsa_cp_reginfo); 4985 } 4986 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { 4987 define_arm_cp_regs(cpu, t2ee_cp_reginfo); 4988 } 4989 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { 4990 define_arm_cp_regs(cpu, generic_timer_cp_reginfo); 4991 } 4992 if (arm_feature(env, ARM_FEATURE_VAPA)) { 4993 define_arm_cp_regs(cpu, vapa_cp_reginfo); 4994 } 4995 if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) { 4996 define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo); 4997 } 4998 if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) { 4999 define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo); 5000 } 5001 if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) { 5002 define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo); 5003 } 5004 if (arm_feature(env, ARM_FEATURE_OMAPCP)) { 5005 define_arm_cp_regs(cpu, omap_cp_reginfo); 5006 } 5007 if (arm_feature(env, ARM_FEATURE_STRONGARM)) { 5008 define_arm_cp_regs(cpu, strongarm_cp_reginfo); 5009 } 5010 if (arm_feature(env, ARM_FEATURE_XSCALE)) { 5011 define_arm_cp_regs(cpu, xscale_cp_reginfo); 5012 } 5013 if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) { 5014 define_arm_cp_regs(cpu, dummy_c15_cp_reginfo); 5015 } 5016 if (arm_feature(env, ARM_FEATURE_LPAE)) { 5017 define_arm_cp_regs(cpu, lpae_cp_reginfo); 5018 } 5019 /* Slightly awkwardly, the OMAP and StrongARM cores need all of 5020 * cp15 crn=0 to be writes-ignored, whereas for other cores they should 5021 * be read-only (ie write causes UNDEF exception). 5022 */ 5023 { 5024 ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = { 5025 /* Pre-v8 MIDR space. 5026 * Note that the MIDR isn't a simple constant register because 5027 * of the TI925 behaviour where writes to another register can 5028 * cause the MIDR value to change. 5029 * 5030 * Unimplemented registers in the c15 0 0 0 space default to 5031 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR 5032 * and friends override accordingly. 5033 */ 5034 { .name = "MIDR", 5035 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY, 5036 .access = PL1_R, .resetvalue = cpu->midr, 5037 .writefn = arm_cp_write_ignore, .raw_writefn = raw_write, 5038 .readfn = midr_read, 5039 .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), 5040 .type = ARM_CP_OVERRIDE }, 5041 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */ 5042 { .name = "DUMMY", 5043 .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY, 5044 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 5045 { .name = "DUMMY", 5046 .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY, 5047 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 5048 { .name = "DUMMY", 5049 .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY, 5050 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 5051 { .name = "DUMMY", 5052 .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY, 5053 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 5054 { .name = "DUMMY", 5055 .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY, 5056 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 5057 REGINFO_SENTINEL 5058 }; 5059 ARMCPRegInfo id_v8_midr_cp_reginfo[] = { 5060 { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH, 5061 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0, 5062 .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr, 5063 .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), 5064 .readfn = midr_read }, 5065 /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */ 5066 { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST, 5067 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4, 5068 .access = PL1_R, .resetvalue = cpu->midr }, 5069 { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST, 5070 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7, 5071 .access = PL1_R, .resetvalue = cpu->midr }, 5072 { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH, 5073 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6, 5074 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->revidr }, 5075 REGINFO_SENTINEL 5076 }; 5077 ARMCPRegInfo id_cp_reginfo[] = { 5078 /* These are common to v8 and pre-v8 */ 5079 { .name = "CTR", 5080 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1, 5081 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, 5082 { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64, 5083 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0, 5084 .access = PL0_R, .accessfn = ctr_el0_access, 5085 .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, 5086 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */ 5087 { .name = "TCMTR", 5088 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2, 5089 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 5090 REGINFO_SENTINEL 5091 }; 5092 /* TLBTR is specific to VMSA */ 5093 ARMCPRegInfo id_tlbtr_reginfo = { 5094 .name = "TLBTR", 5095 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3, 5096 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0, 5097 }; 5098 /* MPUIR is specific to PMSA V6+ */ 5099 ARMCPRegInfo id_mpuir_reginfo = { 5100 .name = "MPUIR", 5101 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4, 5102 .access = PL1_R, .type = ARM_CP_CONST, 5103 .resetvalue = cpu->pmsav7_dregion << 8 5104 }; 5105 ARMCPRegInfo crn0_wi_reginfo = { 5106 .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY, 5107 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W, 5108 .type = ARM_CP_NOP | ARM_CP_OVERRIDE 5109 }; 5110 if (arm_feature(env, ARM_FEATURE_OMAPCP) || 5111 arm_feature(env, ARM_FEATURE_STRONGARM)) { 5112 ARMCPRegInfo *r; 5113 /* Register the blanket "writes ignored" value first to cover the 5114 * whole space. Then update the specific ID registers to allow write 5115 * access, so that they ignore writes rather than causing them to 5116 * UNDEF. 5117 */ 5118 define_one_arm_cp_reg(cpu, &crn0_wi_reginfo); 5119 for (r = id_pre_v8_midr_cp_reginfo; 5120 r->type != ARM_CP_SENTINEL; r++) { 5121 r->access = PL1_RW; 5122 } 5123 for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) { 5124 r->access = PL1_RW; 5125 } 5126 id_tlbtr_reginfo.access = PL1_RW; 5127 id_tlbtr_reginfo.access = PL1_RW; 5128 } 5129 if (arm_feature(env, ARM_FEATURE_V8)) { 5130 define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo); 5131 } else { 5132 define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo); 5133 } 5134 define_arm_cp_regs(cpu, id_cp_reginfo); 5135 if (!arm_feature(env, ARM_FEATURE_PMSA)) { 5136 define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo); 5137 } else if (arm_feature(env, ARM_FEATURE_V7)) { 5138 define_one_arm_cp_reg(cpu, &id_mpuir_reginfo); 5139 } 5140 } 5141 5142 if (arm_feature(env, ARM_FEATURE_MPIDR)) { 5143 define_arm_cp_regs(cpu, mpidr_cp_reginfo); 5144 } 5145 5146 if (arm_feature(env, ARM_FEATURE_AUXCR)) { 5147 ARMCPRegInfo auxcr_reginfo[] = { 5148 { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH, 5149 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1, 5150 .access = PL1_RW, .type = ARM_CP_CONST, 5151 .resetvalue = cpu->reset_auxcr }, 5152 { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH, 5153 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1, 5154 .access = PL2_RW, .type = ARM_CP_CONST, 5155 .resetvalue = 0 }, 5156 { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64, 5157 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1, 5158 .access = PL3_RW, .type = ARM_CP_CONST, 5159 .resetvalue = 0 }, 5160 REGINFO_SENTINEL 5161 }; 5162 define_arm_cp_regs(cpu, auxcr_reginfo); 5163 } 5164 5165 if (arm_feature(env, ARM_FEATURE_CBAR)) { 5166 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 5167 /* 32 bit view is [31:18] 0...0 [43:32]. */ 5168 uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18) 5169 | extract64(cpu->reset_cbar, 32, 12); 5170 ARMCPRegInfo cbar_reginfo[] = { 5171 { .name = "CBAR", 5172 .type = ARM_CP_CONST, 5173 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0, 5174 .access = PL1_R, .resetvalue = cpu->reset_cbar }, 5175 { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64, 5176 .type = ARM_CP_CONST, 5177 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0, 5178 .access = PL1_R, .resetvalue = cbar32 }, 5179 REGINFO_SENTINEL 5180 }; 5181 /* We don't implement a r/w 64 bit CBAR currently */ 5182 assert(arm_feature(env, ARM_FEATURE_CBAR_RO)); 5183 define_arm_cp_regs(cpu, cbar_reginfo); 5184 } else { 5185 ARMCPRegInfo cbar = { 5186 .name = "CBAR", 5187 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0, 5188 .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar, 5189 .fieldoffset = offsetof(CPUARMState, 5190 cp15.c15_config_base_address) 5191 }; 5192 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 5193 cbar.access = PL1_R; 5194 cbar.fieldoffset = 0; 5195 cbar.type = ARM_CP_CONST; 5196 } 5197 define_one_arm_cp_reg(cpu, &cbar); 5198 } 5199 } 5200 5201 if (arm_feature(env, ARM_FEATURE_VBAR)) { 5202 ARMCPRegInfo vbar_cp_reginfo[] = { 5203 { .name = "VBAR", .state = ARM_CP_STATE_BOTH, 5204 .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0, 5205 .access = PL1_RW, .writefn = vbar_write, 5206 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s), 5207 offsetof(CPUARMState, cp15.vbar_ns) }, 5208 .resetvalue = 0 }, 5209 REGINFO_SENTINEL 5210 }; 5211 define_arm_cp_regs(cpu, vbar_cp_reginfo); 5212 } 5213 5214 /* Generic registers whose values depend on the implementation */ 5215 { 5216 ARMCPRegInfo sctlr = { 5217 .name = "SCTLR", .state = ARM_CP_STATE_BOTH, 5218 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, 5219 .access = PL1_RW, 5220 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s), 5221 offsetof(CPUARMState, cp15.sctlr_ns) }, 5222 .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr, 5223 .raw_writefn = raw_write, 5224 }; 5225 if (arm_feature(env, ARM_FEATURE_XSCALE)) { 5226 /* Normally we would always end the TB on an SCTLR write, but Linux 5227 * arch/arm/mach-pxa/sleep.S expects two instructions following 5228 * an MMU enable to execute from cache. Imitate this behaviour. 5229 */ 5230 sctlr.type |= ARM_CP_SUPPRESS_TB_END; 5231 } 5232 define_one_arm_cp_reg(cpu, &sctlr); 5233 } 5234 } 5235 5236 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) 5237 { 5238 CPUState *cs = CPU(cpu); 5239 CPUARMState *env = &cpu->env; 5240 5241 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 5242 gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg, 5243 aarch64_fpu_gdb_set_reg, 5244 34, "aarch64-fpu.xml", 0); 5245 } else if (arm_feature(env, ARM_FEATURE_NEON)) { 5246 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 5247 51, "arm-neon.xml", 0); 5248 } else if (arm_feature(env, ARM_FEATURE_VFP3)) { 5249 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 5250 35, "arm-vfp3.xml", 0); 5251 } else if (arm_feature(env, ARM_FEATURE_VFP)) { 5252 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 5253 19, "arm-vfp.xml", 0); 5254 } 5255 } 5256 5257 /* Sort alphabetically by type name, except for "any". */ 5258 static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b) 5259 { 5260 ObjectClass *class_a = (ObjectClass *)a; 5261 ObjectClass *class_b = (ObjectClass *)b; 5262 const char *name_a, *name_b; 5263 5264 name_a = object_class_get_name(class_a); 5265 name_b = object_class_get_name(class_b); 5266 if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) { 5267 return 1; 5268 } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) { 5269 return -1; 5270 } else { 5271 return strcmp(name_a, name_b); 5272 } 5273 } 5274 5275 static void arm_cpu_list_entry(gpointer data, gpointer user_data) 5276 { 5277 ObjectClass *oc = data; 5278 CPUListState *s = user_data; 5279 const char *typename; 5280 char *name; 5281 5282 typename = object_class_get_name(oc); 5283 name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU)); 5284 (*s->cpu_fprintf)(s->file, " %s\n", 5285 name); 5286 g_free(name); 5287 } 5288 5289 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf) 5290 { 5291 CPUListState s = { 5292 .file = f, 5293 .cpu_fprintf = cpu_fprintf, 5294 }; 5295 GSList *list; 5296 5297 list = object_class_get_list(TYPE_ARM_CPU, false); 5298 list = g_slist_sort(list, arm_cpu_list_compare); 5299 (*cpu_fprintf)(f, "Available CPUs:\n"); 5300 g_slist_foreach(list, arm_cpu_list_entry, &s); 5301 g_slist_free(list); 5302 #ifdef CONFIG_KVM 5303 /* The 'host' CPU type is dynamically registered only if KVM is 5304 * enabled, so we have to special-case it here: 5305 */ 5306 (*cpu_fprintf)(f, " host (only available in KVM mode)\n"); 5307 #endif 5308 } 5309 5310 static void arm_cpu_add_definition(gpointer data, gpointer user_data) 5311 { 5312 ObjectClass *oc = data; 5313 CpuDefinitionInfoList **cpu_list = user_data; 5314 CpuDefinitionInfoList *entry; 5315 CpuDefinitionInfo *info; 5316 const char *typename; 5317 5318 typename = object_class_get_name(oc); 5319 info = g_malloc0(sizeof(*info)); 5320 info->name = g_strndup(typename, 5321 strlen(typename) - strlen("-" TYPE_ARM_CPU)); 5322 info->q_typename = g_strdup(typename); 5323 5324 entry = g_malloc0(sizeof(*entry)); 5325 entry->value = info; 5326 entry->next = *cpu_list; 5327 *cpu_list = entry; 5328 } 5329 5330 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) 5331 { 5332 CpuDefinitionInfoList *cpu_list = NULL; 5333 GSList *list; 5334 5335 list = object_class_get_list(TYPE_ARM_CPU, false); 5336 g_slist_foreach(list, arm_cpu_add_definition, &cpu_list); 5337 g_slist_free(list); 5338 5339 return cpu_list; 5340 } 5341 5342 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, 5343 void *opaque, int state, int secstate, 5344 int crm, int opc1, int opc2) 5345 { 5346 /* Private utility function for define_one_arm_cp_reg_with_opaque(): 5347 * add a single reginfo struct to the hash table. 5348 */ 5349 uint32_t *key = g_new(uint32_t, 1); 5350 ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo)); 5351 int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0; 5352 int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; 5353 5354 /* Reset the secure state to the specific incoming state. This is 5355 * necessary as the register may have been defined with both states. 5356 */ 5357 r2->secure = secstate; 5358 5359 if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { 5360 /* Register is banked (using both entries in array). 5361 * Overwriting fieldoffset as the array is only used to define 5362 * banked registers but later only fieldoffset is used. 5363 */ 5364 r2->fieldoffset = r->bank_fieldoffsets[ns]; 5365 } 5366 5367 if (state == ARM_CP_STATE_AA32) { 5368 if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { 5369 /* If the register is banked then we don't need to migrate or 5370 * reset the 32-bit instance in certain cases: 5371 * 5372 * 1) If the register has both 32-bit and 64-bit instances then we 5373 * can count on the 64-bit instance taking care of the 5374 * non-secure bank. 5375 * 2) If ARMv8 is enabled then we can count on a 64-bit version 5376 * taking care of the secure bank. This requires that separate 5377 * 32 and 64-bit definitions are provided. 5378 */ 5379 if ((r->state == ARM_CP_STATE_BOTH && ns) || 5380 (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) { 5381 r2->type |= ARM_CP_ALIAS; 5382 } 5383 } else if ((secstate != r->secure) && !ns) { 5384 /* The register is not banked so we only want to allow migration of 5385 * the non-secure instance. 5386 */ 5387 r2->type |= ARM_CP_ALIAS; 5388 } 5389 5390 if (r->state == ARM_CP_STATE_BOTH) { 5391 /* We assume it is a cp15 register if the .cp field is left unset. 5392 */ 5393 if (r2->cp == 0) { 5394 r2->cp = 15; 5395 } 5396 5397 #ifdef HOST_WORDS_BIGENDIAN 5398 if (r2->fieldoffset) { 5399 r2->fieldoffset += sizeof(uint32_t); 5400 } 5401 #endif 5402 } 5403 } 5404 if (state == ARM_CP_STATE_AA64) { 5405 /* To allow abbreviation of ARMCPRegInfo 5406 * definitions, we treat cp == 0 as equivalent to 5407 * the value for "standard guest-visible sysreg". 5408 * STATE_BOTH definitions are also always "standard 5409 * sysreg" in their AArch64 view (the .cp value may 5410 * be non-zero for the benefit of the AArch32 view). 5411 */ 5412 if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) { 5413 r2->cp = CP_REG_ARM64_SYSREG_CP; 5414 } 5415 *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm, 5416 r2->opc0, opc1, opc2); 5417 } else { 5418 *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2); 5419 } 5420 if (opaque) { 5421 r2->opaque = opaque; 5422 } 5423 /* reginfo passed to helpers is correct for the actual access, 5424 * and is never ARM_CP_STATE_BOTH: 5425 */ 5426 r2->state = state; 5427 /* Make sure reginfo passed to helpers for wildcarded regs 5428 * has the correct crm/opc1/opc2 for this reg, not CP_ANY: 5429 */ 5430 r2->crm = crm; 5431 r2->opc1 = opc1; 5432 r2->opc2 = opc2; 5433 /* By convention, for wildcarded registers only the first 5434 * entry is used for migration; the others are marked as 5435 * ALIAS so we don't try to transfer the register 5436 * multiple times. Special registers (ie NOP/WFI) are 5437 * never migratable and not even raw-accessible. 5438 */ 5439 if ((r->type & ARM_CP_SPECIAL)) { 5440 r2->type |= ARM_CP_NO_RAW; 5441 } 5442 if (((r->crm == CP_ANY) && crm != 0) || 5443 ((r->opc1 == CP_ANY) && opc1 != 0) || 5444 ((r->opc2 == CP_ANY) && opc2 != 0)) { 5445 r2->type |= ARM_CP_ALIAS; 5446 } 5447 5448 /* Check that raw accesses are either forbidden or handled. Note that 5449 * we can't assert this earlier because the setup of fieldoffset for 5450 * banked registers has to be done first. 5451 */ 5452 if (!(r2->type & ARM_CP_NO_RAW)) { 5453 assert(!raw_accessors_invalid(r2)); 5454 } 5455 5456 /* Overriding of an existing definition must be explicitly 5457 * requested. 5458 */ 5459 if (!(r->type & ARM_CP_OVERRIDE)) { 5460 ARMCPRegInfo *oldreg; 5461 oldreg = g_hash_table_lookup(cpu->cp_regs, key); 5462 if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) { 5463 fprintf(stderr, "Register redefined: cp=%d %d bit " 5464 "crn=%d crm=%d opc1=%d opc2=%d, " 5465 "was %s, now %s\n", r2->cp, 32 + 32 * is64, 5466 r2->crn, r2->crm, r2->opc1, r2->opc2, 5467 oldreg->name, r2->name); 5468 g_assert_not_reached(); 5469 } 5470 } 5471 g_hash_table_insert(cpu->cp_regs, key, r2); 5472 } 5473 5474 5475 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, 5476 const ARMCPRegInfo *r, void *opaque) 5477 { 5478 /* Define implementations of coprocessor registers. 5479 * We store these in a hashtable because typically 5480 * there are less than 150 registers in a space which 5481 * is 16*16*16*8*8 = 262144 in size. 5482 * Wildcarding is supported for the crm, opc1 and opc2 fields. 5483 * If a register is defined twice then the second definition is 5484 * used, so this can be used to define some generic registers and 5485 * then override them with implementation specific variations. 5486 * At least one of the original and the second definition should 5487 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard 5488 * against accidental use. 5489 * 5490 * The state field defines whether the register is to be 5491 * visible in the AArch32 or AArch64 execution state. If the 5492 * state is set to ARM_CP_STATE_BOTH then we synthesise a 5493 * reginfo structure for the AArch32 view, which sees the lower 5494 * 32 bits of the 64 bit register. 5495 * 5496 * Only registers visible in AArch64 may set r->opc0; opc0 cannot 5497 * be wildcarded. AArch64 registers are always considered to be 64 5498 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of 5499 * the register, if any. 5500 */ 5501 int crm, opc1, opc2, state; 5502 int crmmin = (r->crm == CP_ANY) ? 0 : r->crm; 5503 int crmmax = (r->crm == CP_ANY) ? 15 : r->crm; 5504 int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1; 5505 int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1; 5506 int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2; 5507 int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2; 5508 /* 64 bit registers have only CRm and Opc1 fields */ 5509 assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn))); 5510 /* op0 only exists in the AArch64 encodings */ 5511 assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0)); 5512 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */ 5513 assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT)); 5514 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1 5515 * encodes a minimum access level for the register. We roll this 5516 * runtime check into our general permission check code, so check 5517 * here that the reginfo's specified permissions are strict enough 5518 * to encompass the generic architectural permission check. 5519 */ 5520 if (r->state != ARM_CP_STATE_AA32) { 5521 int mask = 0; 5522 switch (r->opc1) { 5523 case 0: case 1: case 2: 5524 /* min_EL EL1 */ 5525 mask = PL1_RW; 5526 break; 5527 case 3: 5528 /* min_EL EL0 */ 5529 mask = PL0_RW; 5530 break; 5531 case 4: 5532 /* min_EL EL2 */ 5533 mask = PL2_RW; 5534 break; 5535 case 5: 5536 /* unallocated encoding, so not possible */ 5537 assert(false); 5538 break; 5539 case 6: 5540 /* min_EL EL3 */ 5541 mask = PL3_RW; 5542 break; 5543 case 7: 5544 /* min_EL EL1, secure mode only (we don't check the latter) */ 5545 mask = PL1_RW; 5546 break; 5547 default: 5548 /* broken reginfo with out-of-range opc1 */ 5549 assert(false); 5550 break; 5551 } 5552 /* assert our permissions are not too lax (stricter is fine) */ 5553 assert((r->access & ~mask) == 0); 5554 } 5555 5556 /* Check that the register definition has enough info to handle 5557 * reads and writes if they are permitted. 5558 */ 5559 if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) { 5560 if (r->access & PL3_R) { 5561 assert((r->fieldoffset || 5562 (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || 5563 r->readfn); 5564 } 5565 if (r->access & PL3_W) { 5566 assert((r->fieldoffset || 5567 (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || 5568 r->writefn); 5569 } 5570 } 5571 /* Bad type field probably means missing sentinel at end of reg list */ 5572 assert(cptype_valid(r->type)); 5573 for (crm = crmmin; crm <= crmmax; crm++) { 5574 for (opc1 = opc1min; opc1 <= opc1max; opc1++) { 5575 for (opc2 = opc2min; opc2 <= opc2max; opc2++) { 5576 for (state = ARM_CP_STATE_AA32; 5577 state <= ARM_CP_STATE_AA64; state++) { 5578 if (r->state != state && r->state != ARM_CP_STATE_BOTH) { 5579 continue; 5580 } 5581 if (state == ARM_CP_STATE_AA32) { 5582 /* Under AArch32 CP registers can be common 5583 * (same for secure and non-secure world) or banked. 5584 */ 5585 switch (r->secure) { 5586 case ARM_CP_SECSTATE_S: 5587 case ARM_CP_SECSTATE_NS: 5588 add_cpreg_to_hashtable(cpu, r, opaque, state, 5589 r->secure, crm, opc1, opc2); 5590 break; 5591 default: 5592 add_cpreg_to_hashtable(cpu, r, opaque, state, 5593 ARM_CP_SECSTATE_S, 5594 crm, opc1, opc2); 5595 add_cpreg_to_hashtable(cpu, r, opaque, state, 5596 ARM_CP_SECSTATE_NS, 5597 crm, opc1, opc2); 5598 break; 5599 } 5600 } else { 5601 /* AArch64 registers get mapped to non-secure instance 5602 * of AArch32 */ 5603 add_cpreg_to_hashtable(cpu, r, opaque, state, 5604 ARM_CP_SECSTATE_NS, 5605 crm, opc1, opc2); 5606 } 5607 } 5608 } 5609 } 5610 } 5611 } 5612 5613 void define_arm_cp_regs_with_opaque(ARMCPU *cpu, 5614 const ARMCPRegInfo *regs, void *opaque) 5615 { 5616 /* Define a whole list of registers */ 5617 const ARMCPRegInfo *r; 5618 for (r = regs; r->type != ARM_CP_SENTINEL; r++) { 5619 define_one_arm_cp_reg_with_opaque(cpu, r, opaque); 5620 } 5621 } 5622 5623 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp) 5624 { 5625 return g_hash_table_lookup(cpregs, &encoded_cp); 5626 } 5627 5628 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, 5629 uint64_t value) 5630 { 5631 /* Helper coprocessor write function for write-ignore registers */ 5632 } 5633 5634 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri) 5635 { 5636 /* Helper coprocessor write function for read-as-zero registers */ 5637 return 0; 5638 } 5639 5640 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque) 5641 { 5642 /* Helper coprocessor reset function for do-nothing-on-reset registers */ 5643 } 5644 5645 static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type) 5646 { 5647 /* Return true if it is not valid for us to switch to 5648 * this CPU mode (ie all the UNPREDICTABLE cases in 5649 * the ARM ARM CPSRWriteByInstr pseudocode). 5650 */ 5651 5652 /* Changes to or from Hyp via MSR and CPS are illegal. */ 5653 if (write_type == CPSRWriteByInstr && 5654 ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_HYP || 5655 mode == ARM_CPU_MODE_HYP)) { 5656 return 1; 5657 } 5658 5659 switch (mode) { 5660 case ARM_CPU_MODE_USR: 5661 return 0; 5662 case ARM_CPU_MODE_SYS: 5663 case ARM_CPU_MODE_SVC: 5664 case ARM_CPU_MODE_ABT: 5665 case ARM_CPU_MODE_UND: 5666 case ARM_CPU_MODE_IRQ: 5667 case ARM_CPU_MODE_FIQ: 5668 /* Note that we don't implement the IMPDEF NSACR.RFR which in v7 5669 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.) 5670 */ 5671 /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR 5672 * and CPS are treated as illegal mode changes. 5673 */ 5674 if (write_type == CPSRWriteByInstr && 5675 (env->cp15.hcr_el2 & HCR_TGE) && 5676 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON && 5677 !arm_is_secure_below_el3(env)) { 5678 return 1; 5679 } 5680 return 0; 5681 case ARM_CPU_MODE_HYP: 5682 return !arm_feature(env, ARM_FEATURE_EL2) 5683 || arm_current_el(env) < 2 || arm_is_secure(env); 5684 case ARM_CPU_MODE_MON: 5685 return arm_current_el(env) < 3; 5686 default: 5687 return 1; 5688 } 5689 } 5690 5691 uint32_t cpsr_read(CPUARMState *env) 5692 { 5693 int ZF; 5694 ZF = (env->ZF == 0); 5695 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) | 5696 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 5697 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25) 5698 | ((env->condexec_bits & 0xfc) << 8) 5699 | (env->GE << 16) | (env->daif & CPSR_AIF); 5700 } 5701 5702 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 5703 CPSRWriteType write_type) 5704 { 5705 uint32_t changed_daif; 5706 5707 if (mask & CPSR_NZCV) { 5708 env->ZF = (~val) & CPSR_Z; 5709 env->NF = val; 5710 env->CF = (val >> 29) & 1; 5711 env->VF = (val << 3) & 0x80000000; 5712 } 5713 if (mask & CPSR_Q) 5714 env->QF = ((val & CPSR_Q) != 0); 5715 if (mask & CPSR_T) 5716 env->thumb = ((val & CPSR_T) != 0); 5717 if (mask & CPSR_IT_0_1) { 5718 env->condexec_bits &= ~3; 5719 env->condexec_bits |= (val >> 25) & 3; 5720 } 5721 if (mask & CPSR_IT_2_7) { 5722 env->condexec_bits &= 3; 5723 env->condexec_bits |= (val >> 8) & 0xfc; 5724 } 5725 if (mask & CPSR_GE) { 5726 env->GE = (val >> 16) & 0xf; 5727 } 5728 5729 /* In a V7 implementation that includes the security extensions but does 5730 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control 5731 * whether non-secure software is allowed to change the CPSR_F and CPSR_A 5732 * bits respectively. 5733 * 5734 * In a V8 implementation, it is permitted for privileged software to 5735 * change the CPSR A/F bits regardless of the SCR.AW/FW bits. 5736 */ 5737 if (write_type != CPSRWriteRaw && !arm_feature(env, ARM_FEATURE_V8) && 5738 arm_feature(env, ARM_FEATURE_EL3) && 5739 !arm_feature(env, ARM_FEATURE_EL2) && 5740 !arm_is_secure(env)) { 5741 5742 changed_daif = (env->daif ^ val) & mask; 5743 5744 if (changed_daif & CPSR_A) { 5745 /* Check to see if we are allowed to change the masking of async 5746 * abort exceptions from a non-secure state. 5747 */ 5748 if (!(env->cp15.scr_el3 & SCR_AW)) { 5749 qemu_log_mask(LOG_GUEST_ERROR, 5750 "Ignoring attempt to switch CPSR_A flag from " 5751 "non-secure world with SCR.AW bit clear\n"); 5752 mask &= ~CPSR_A; 5753 } 5754 } 5755 5756 if (changed_daif & CPSR_F) { 5757 /* Check to see if we are allowed to change the masking of FIQ 5758 * exceptions from a non-secure state. 5759 */ 5760 if (!(env->cp15.scr_el3 & SCR_FW)) { 5761 qemu_log_mask(LOG_GUEST_ERROR, 5762 "Ignoring attempt to switch CPSR_F flag from " 5763 "non-secure world with SCR.FW bit clear\n"); 5764 mask &= ~CPSR_F; 5765 } 5766 5767 /* Check whether non-maskable FIQ (NMFI) support is enabled. 5768 * If this bit is set software is not allowed to mask 5769 * FIQs, but is allowed to set CPSR_F to 0. 5770 */ 5771 if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) && 5772 (val & CPSR_F)) { 5773 qemu_log_mask(LOG_GUEST_ERROR, 5774 "Ignoring attempt to enable CPSR_F flag " 5775 "(non-maskable FIQ [NMFI] support enabled)\n"); 5776 mask &= ~CPSR_F; 5777 } 5778 } 5779 } 5780 5781 env->daif &= ~(CPSR_AIF & mask); 5782 env->daif |= val & CPSR_AIF & mask; 5783 5784 if (write_type != CPSRWriteRaw && 5785 ((env->uncached_cpsr ^ val) & mask & CPSR_M)) { 5786 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR) { 5787 /* Note that we can only get here in USR mode if this is a 5788 * gdb stub write; for this case we follow the architectural 5789 * behaviour for guest writes in USR mode of ignoring an attempt 5790 * to switch mode. (Those are caught by translate.c for writes 5791 * triggered by guest instructions.) 5792 */ 5793 mask &= ~CPSR_M; 5794 } else if (bad_mode_switch(env, val & CPSR_M, write_type)) { 5795 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in 5796 * v7, and has defined behaviour in v8: 5797 * + leave CPSR.M untouched 5798 * + allow changes to the other CPSR fields 5799 * + set PSTATE.IL 5800 * For user changes via the GDB stub, we don't set PSTATE.IL, 5801 * as this would be unnecessarily harsh for a user error. 5802 */ 5803 mask &= ~CPSR_M; 5804 if (write_type != CPSRWriteByGDBStub && 5805 arm_feature(env, ARM_FEATURE_V8)) { 5806 mask |= CPSR_IL; 5807 val |= CPSR_IL; 5808 } 5809 } else { 5810 switch_mode(env, val & CPSR_M); 5811 } 5812 } 5813 mask &= ~CACHED_CPSR_BITS; 5814 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask); 5815 } 5816 5817 /* Sign/zero extend */ 5818 uint32_t HELPER(sxtb16)(uint32_t x) 5819 { 5820 uint32_t res; 5821 res = (uint16_t)(int8_t)x; 5822 res |= (uint32_t)(int8_t)(x >> 16) << 16; 5823 return res; 5824 } 5825 5826 uint32_t HELPER(uxtb16)(uint32_t x) 5827 { 5828 uint32_t res; 5829 res = (uint16_t)(uint8_t)x; 5830 res |= (uint32_t)(uint8_t)(x >> 16) << 16; 5831 return res; 5832 } 5833 5834 int32_t HELPER(sdiv)(int32_t num, int32_t den) 5835 { 5836 if (den == 0) 5837 return 0; 5838 if (num == INT_MIN && den == -1) 5839 return INT_MIN; 5840 return num / den; 5841 } 5842 5843 uint32_t HELPER(udiv)(uint32_t num, uint32_t den) 5844 { 5845 if (den == 0) 5846 return 0; 5847 return num / den; 5848 } 5849 5850 uint32_t HELPER(rbit)(uint32_t x) 5851 { 5852 return revbit32(x); 5853 } 5854 5855 #if defined(CONFIG_USER_ONLY) 5856 5857 /* These should probably raise undefined insn exceptions. */ 5858 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) 5859 { 5860 ARMCPU *cpu = arm_env_get_cpu(env); 5861 5862 cpu_abort(CPU(cpu), "v7m_msr %d\n", reg); 5863 } 5864 5865 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) 5866 { 5867 ARMCPU *cpu = arm_env_get_cpu(env); 5868 5869 cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg); 5870 return 0; 5871 } 5872 5873 void switch_mode(CPUARMState *env, int mode) 5874 { 5875 ARMCPU *cpu = arm_env_get_cpu(env); 5876 5877 if (mode != ARM_CPU_MODE_USR) { 5878 cpu_abort(CPU(cpu), "Tried to switch out of user mode\n"); 5879 } 5880 } 5881 5882 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 5883 uint32_t cur_el, bool secure) 5884 { 5885 return 1; 5886 } 5887 5888 void aarch64_sync_64_to_32(CPUARMState *env) 5889 { 5890 g_assert_not_reached(); 5891 } 5892 5893 #else 5894 5895 void switch_mode(CPUARMState *env, int mode) 5896 { 5897 int old_mode; 5898 int i; 5899 5900 old_mode = env->uncached_cpsr & CPSR_M; 5901 if (mode == old_mode) 5902 return; 5903 5904 if (old_mode == ARM_CPU_MODE_FIQ) { 5905 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t)); 5906 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); 5907 } else if (mode == ARM_CPU_MODE_FIQ) { 5908 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t)); 5909 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t)); 5910 } 5911 5912 i = bank_number(old_mode); 5913 env->banked_r13[i] = env->regs[13]; 5914 env->banked_r14[i] = env->regs[14]; 5915 env->banked_spsr[i] = env->spsr; 5916 5917 i = bank_number(mode); 5918 env->regs[13] = env->banked_r13[i]; 5919 env->regs[14] = env->banked_r14[i]; 5920 env->spsr = env->banked_spsr[i]; 5921 } 5922 5923 /* Physical Interrupt Target EL Lookup Table 5924 * 5925 * [ From ARM ARM section G1.13.4 (Table G1-15) ] 5926 * 5927 * The below multi-dimensional table is used for looking up the target 5928 * exception level given numerous condition criteria. Specifically, the 5929 * target EL is based on SCR and HCR routing controls as well as the 5930 * currently executing EL and secure state. 5931 * 5932 * Dimensions: 5933 * target_el_table[2][2][2][2][2][4] 5934 * | | | | | +--- Current EL 5935 * | | | | +------ Non-secure(0)/Secure(1) 5936 * | | | +--------- HCR mask override 5937 * | | +------------ SCR exec state control 5938 * | +--------------- SCR mask override 5939 * +------------------ 32-bit(0)/64-bit(1) EL3 5940 * 5941 * The table values are as such: 5942 * 0-3 = EL0-EL3 5943 * -1 = Cannot occur 5944 * 5945 * The ARM ARM target EL table includes entries indicating that an "exception 5946 * is not taken". The two cases where this is applicable are: 5947 * 1) An exception is taken from EL3 but the SCR does not have the exception 5948 * routed to EL3. 5949 * 2) An exception is taken from EL2 but the HCR does not have the exception 5950 * routed to EL2. 5951 * In these two cases, the below table contain a target of EL1. This value is 5952 * returned as it is expected that the consumer of the table data will check 5953 * for "target EL >= current EL" to ensure the exception is not taken. 5954 * 5955 * SCR HCR 5956 * 64 EA AMO From 5957 * BIT IRQ IMO Non-secure Secure 5958 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3 5959 */ 5960 static const int8_t target_el_table[2][2][2][2][2][4] = { 5961 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },}, 5962 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},}, 5963 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },}, 5964 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},}, 5965 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },}, 5966 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},}, 5967 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },}, 5968 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},}, 5969 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },}, 5970 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},}, 5971 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, -1, 1 },}, 5972 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},}, 5973 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },}, 5974 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},}, 5975 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },}, 5976 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},},}, 5977 }; 5978 5979 /* 5980 * Determine the target EL for physical exceptions 5981 */ 5982 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 5983 uint32_t cur_el, bool secure) 5984 { 5985 CPUARMState *env = cs->env_ptr; 5986 int rw; 5987 int scr; 5988 int hcr; 5989 int target_el; 5990 /* Is the highest EL AArch64? */ 5991 int is64 = arm_feature(env, ARM_FEATURE_AARCH64); 5992 5993 if (arm_feature(env, ARM_FEATURE_EL3)) { 5994 rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW); 5995 } else { 5996 /* Either EL2 is the highest EL (and so the EL2 register width 5997 * is given by is64); or there is no EL2 or EL3, in which case 5998 * the value of 'rw' does not affect the table lookup anyway. 5999 */ 6000 rw = is64; 6001 } 6002 6003 switch (excp_idx) { 6004 case EXCP_IRQ: 6005 scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ); 6006 hcr = ((env->cp15.hcr_el2 & HCR_IMO) == HCR_IMO); 6007 break; 6008 case EXCP_FIQ: 6009 scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ); 6010 hcr = ((env->cp15.hcr_el2 & HCR_FMO) == HCR_FMO); 6011 break; 6012 default: 6013 scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA); 6014 hcr = ((env->cp15.hcr_el2 & HCR_AMO) == HCR_AMO); 6015 break; 6016 }; 6017 6018 /* If HCR.TGE is set then HCR is treated as being 1 */ 6019 hcr |= ((env->cp15.hcr_el2 & HCR_TGE) == HCR_TGE); 6020 6021 /* Perform a table-lookup for the target EL given the current state */ 6022 target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el]; 6023 6024 assert(target_el > 0); 6025 6026 return target_el; 6027 } 6028 6029 static void v7m_push(CPUARMState *env, uint32_t val) 6030 { 6031 CPUState *cs = CPU(arm_env_get_cpu(env)); 6032 6033 env->regs[13] -= 4; 6034 stl_phys(cs->as, env->regs[13], val); 6035 } 6036 6037 static uint32_t v7m_pop(CPUARMState *env) 6038 { 6039 CPUState *cs = CPU(arm_env_get_cpu(env)); 6040 uint32_t val; 6041 6042 val = ldl_phys(cs->as, env->regs[13]); 6043 env->regs[13] += 4; 6044 return val; 6045 } 6046 6047 /* Switch to V7M main or process stack pointer. */ 6048 static void switch_v7m_sp(CPUARMState *env, bool new_spsel) 6049 { 6050 uint32_t tmp; 6051 bool old_spsel = env->v7m.control & R_V7M_CONTROL_SPSEL_MASK; 6052 6053 if (old_spsel != new_spsel) { 6054 tmp = env->v7m.other_sp; 6055 env->v7m.other_sp = env->regs[13]; 6056 env->regs[13] = tmp; 6057 6058 env->v7m.control = deposit32(env->v7m.control, 6059 R_V7M_CONTROL_SPSEL_SHIFT, 6060 R_V7M_CONTROL_SPSEL_LENGTH, new_spsel); 6061 } 6062 } 6063 6064 static uint32_t arm_v7m_load_vector(ARMCPU *cpu) 6065 { 6066 CPUState *cs = CPU(cpu); 6067 CPUARMState *env = &cpu->env; 6068 MemTxResult result; 6069 hwaddr vec = env->v7m.vecbase + env->v7m.exception * 4; 6070 uint32_t addr; 6071 6072 addr = address_space_ldl(cs->as, vec, 6073 MEMTXATTRS_UNSPECIFIED, &result); 6074 if (result != MEMTX_OK) { 6075 /* Architecturally this should cause a HardFault setting HSFR.VECTTBL, 6076 * which would then be immediately followed by our failing to load 6077 * the entry vector for that HardFault, which is a Lockup case. 6078 * Since we don't model Lockup, we just report this guest error 6079 * via cpu_abort(). 6080 */ 6081 cpu_abort(cs, "Failed to read from exception vector table " 6082 "entry %08x\n", (unsigned)vec); 6083 } 6084 return addr; 6085 } 6086 6087 static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr) 6088 { 6089 /* Do the "take the exception" parts of exception entry, 6090 * but not the pushing of state to the stack. This is 6091 * similar to the pseudocode ExceptionTaken() function. 6092 */ 6093 CPUARMState *env = &cpu->env; 6094 uint32_t addr; 6095 6096 armv7m_nvic_acknowledge_irq(env->nvic); 6097 switch_v7m_sp(env, 0); 6098 /* Clear IT bits */ 6099 env->condexec_bits = 0; 6100 env->regs[14] = lr; 6101 addr = arm_v7m_load_vector(cpu); 6102 env->regs[15] = addr & 0xfffffffe; 6103 env->thumb = addr & 1; 6104 } 6105 6106 static void v7m_push_stack(ARMCPU *cpu) 6107 { 6108 /* Do the "set up stack frame" part of exception entry, 6109 * similar to pseudocode PushStack(). 6110 */ 6111 CPUARMState *env = &cpu->env; 6112 uint32_t xpsr = xpsr_read(env); 6113 6114 /* Align stack pointer if the guest wants that */ 6115 if ((env->regs[13] & 4) && (env->v7m.ccr & R_V7M_CCR_STKALIGN_MASK)) { 6116 env->regs[13] -= 4; 6117 xpsr |= 0x200; 6118 } 6119 /* Switch to the handler mode. */ 6120 v7m_push(env, xpsr); 6121 v7m_push(env, env->regs[15]); 6122 v7m_push(env, env->regs[14]); 6123 v7m_push(env, env->regs[12]); 6124 v7m_push(env, env->regs[3]); 6125 v7m_push(env, env->regs[2]); 6126 v7m_push(env, env->regs[1]); 6127 v7m_push(env, env->regs[0]); 6128 } 6129 6130 static void do_v7m_exception_exit(ARMCPU *cpu) 6131 { 6132 CPUARMState *env = &cpu->env; 6133 uint32_t type; 6134 uint32_t xpsr; 6135 bool ufault = false; 6136 bool return_to_sp_process = false; 6137 bool return_to_handler = false; 6138 bool rettobase = false; 6139 6140 /* We can only get here from an EXCP_EXCEPTION_EXIT, and 6141 * arm_v7m_do_unassigned_access() enforces the architectural rule 6142 * that jumps to magic addresses don't have magic behaviour unless 6143 * we're in Handler mode (compare pseudocode BXWritePC()). 6144 */ 6145 assert(env->v7m.exception != 0); 6146 6147 /* In the spec pseudocode ExceptionReturn() is called directly 6148 * from BXWritePC() and gets the full target PC value including 6149 * bit zero. In QEMU's implementation we treat it as a normal 6150 * jump-to-register (which is then caught later on), and so split 6151 * the target value up between env->regs[15] and env->thumb in 6152 * gen_bx(). Reconstitute it. 6153 */ 6154 type = env->regs[15]; 6155 if (env->thumb) { 6156 type |= 1; 6157 } 6158 6159 qemu_log_mask(CPU_LOG_INT, "Exception return: magic PC %" PRIx32 6160 " previous exception %d\n", 6161 type, env->v7m.exception); 6162 6163 if (extract32(type, 5, 23) != extract32(-1, 5, 23)) { 6164 qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero high bits in exception " 6165 "exit PC value 0x%" PRIx32 " are UNPREDICTABLE\n", type); 6166 } 6167 6168 if (env->v7m.exception != ARMV7M_EXCP_NMI) { 6169 /* Auto-clear FAULTMASK on return from other than NMI */ 6170 env->daif &= ~PSTATE_F; 6171 } 6172 6173 switch (armv7m_nvic_complete_irq(env->nvic, env->v7m.exception)) { 6174 case -1: 6175 /* attempt to exit an exception that isn't active */ 6176 ufault = true; 6177 break; 6178 case 0: 6179 /* still an irq active now */ 6180 break; 6181 case 1: 6182 /* we returned to base exception level, no nesting. 6183 * (In the pseudocode this is written using "NestedActivation != 1" 6184 * where we have 'rettobase == false'.) 6185 */ 6186 rettobase = true; 6187 break; 6188 default: 6189 g_assert_not_reached(); 6190 } 6191 6192 switch (type & 0xf) { 6193 case 1: /* Return to Handler */ 6194 return_to_handler = true; 6195 break; 6196 case 13: /* Return to Thread using Process stack */ 6197 return_to_sp_process = true; 6198 /* fall through */ 6199 case 9: /* Return to Thread using Main stack */ 6200 if (!rettobase && 6201 !(env->v7m.ccr & R_V7M_CCR_NONBASETHRDENA_MASK)) { 6202 ufault = true; 6203 } 6204 break; 6205 default: 6206 ufault = true; 6207 } 6208 6209 if (ufault) { 6210 /* Bad exception return: instead of popping the exception 6211 * stack, directly take a usage fault on the current stack. 6212 */ 6213 env->v7m.cfsr |= R_V7M_CFSR_INVPC_MASK; 6214 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); 6215 v7m_exception_taken(cpu, type | 0xf0000000); 6216 qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing " 6217 "stackframe: failed exception return integrity check\n"); 6218 return; 6219 } 6220 6221 /* Switch to the target stack. */ 6222 switch_v7m_sp(env, return_to_sp_process); 6223 /* Pop registers. */ 6224 env->regs[0] = v7m_pop(env); 6225 env->regs[1] = v7m_pop(env); 6226 env->regs[2] = v7m_pop(env); 6227 env->regs[3] = v7m_pop(env); 6228 env->regs[12] = v7m_pop(env); 6229 env->regs[14] = v7m_pop(env); 6230 env->regs[15] = v7m_pop(env); 6231 if (env->regs[15] & 1) { 6232 qemu_log_mask(LOG_GUEST_ERROR, 6233 "M profile return from interrupt with misaligned " 6234 "PC is UNPREDICTABLE\n"); 6235 /* Actual hardware seems to ignore the lsbit, and there are several 6236 * RTOSes out there which incorrectly assume the r15 in the stack 6237 * frame should be a Thumb-style "lsbit indicates ARM/Thumb" value. 6238 */ 6239 env->regs[15] &= ~1U; 6240 } 6241 xpsr = v7m_pop(env); 6242 xpsr_write(env, xpsr, 0xfffffdff); 6243 /* Undo stack alignment. */ 6244 if (xpsr & 0x200) 6245 env->regs[13] |= 4; 6246 6247 /* The restored xPSR exception field will be zero if we're 6248 * resuming in Thread mode. If that doesn't match what the 6249 * exception return type specified then this is a UsageFault. 6250 */ 6251 if (return_to_handler == (env->v7m.exception == 0)) { 6252 /* Take an INVPC UsageFault by pushing the stack again. */ 6253 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); 6254 env->v7m.cfsr |= R_V7M_CFSR_INVPC_MASK; 6255 v7m_push_stack(cpu); 6256 v7m_exception_taken(cpu, type | 0xf0000000); 6257 qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on new stackframe: " 6258 "failed exception return integrity check\n"); 6259 return; 6260 } 6261 6262 /* Otherwise, we have a successful exception exit. */ 6263 qemu_log_mask(CPU_LOG_INT, "...successful exception return\n"); 6264 } 6265 6266 static void arm_log_exception(int idx) 6267 { 6268 if (qemu_loglevel_mask(CPU_LOG_INT)) { 6269 const char *exc = NULL; 6270 static const char * const excnames[] = { 6271 [EXCP_UDEF] = "Undefined Instruction", 6272 [EXCP_SWI] = "SVC", 6273 [EXCP_PREFETCH_ABORT] = "Prefetch Abort", 6274 [EXCP_DATA_ABORT] = "Data Abort", 6275 [EXCP_IRQ] = "IRQ", 6276 [EXCP_FIQ] = "FIQ", 6277 [EXCP_BKPT] = "Breakpoint", 6278 [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit", 6279 [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage", 6280 [EXCP_HVC] = "Hypervisor Call", 6281 [EXCP_HYP_TRAP] = "Hypervisor Trap", 6282 [EXCP_SMC] = "Secure Monitor Call", 6283 [EXCP_VIRQ] = "Virtual IRQ", 6284 [EXCP_VFIQ] = "Virtual FIQ", 6285 [EXCP_SEMIHOST] = "Semihosting call", 6286 [EXCP_NOCP] = "v7M NOCP UsageFault", 6287 [EXCP_INVSTATE] = "v7M INVSTATE UsageFault", 6288 }; 6289 6290 if (idx >= 0 && idx < ARRAY_SIZE(excnames)) { 6291 exc = excnames[idx]; 6292 } 6293 if (!exc) { 6294 exc = "unknown"; 6295 } 6296 qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc); 6297 } 6298 } 6299 6300 void arm_v7m_cpu_do_interrupt(CPUState *cs) 6301 { 6302 ARMCPU *cpu = ARM_CPU(cs); 6303 CPUARMState *env = &cpu->env; 6304 uint32_t lr; 6305 6306 arm_log_exception(cs->exception_index); 6307 6308 lr = 0xfffffff1; 6309 if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) { 6310 lr |= 4; 6311 } 6312 if (env->v7m.exception == 0) 6313 lr |= 8; 6314 6315 /* For exceptions we just mark as pending on the NVIC, and let that 6316 handle it. */ 6317 switch (cs->exception_index) { 6318 case EXCP_UDEF: 6319 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); 6320 env->v7m.cfsr |= R_V7M_CFSR_UNDEFINSTR_MASK; 6321 break; 6322 case EXCP_NOCP: 6323 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); 6324 env->v7m.cfsr |= R_V7M_CFSR_NOCP_MASK; 6325 break; 6326 case EXCP_INVSTATE: 6327 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); 6328 env->v7m.cfsr |= R_V7M_CFSR_INVSTATE_MASK; 6329 break; 6330 case EXCP_SWI: 6331 /* The PC already points to the next instruction. */ 6332 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC); 6333 break; 6334 case EXCP_PREFETCH_ABORT: 6335 case EXCP_DATA_ABORT: 6336 /* Note that for M profile we don't have a guest facing FSR, but 6337 * the env->exception.fsr will be populated by the code that 6338 * raises the fault, in the A profile short-descriptor format. 6339 */ 6340 switch (env->exception.fsr & 0xf) { 6341 case 0x8: /* External Abort */ 6342 switch (cs->exception_index) { 6343 case EXCP_PREFETCH_ABORT: 6344 env->v7m.cfsr |= R_V7M_CFSR_PRECISERR_MASK; 6345 qemu_log_mask(CPU_LOG_INT, "...with CFSR.PRECISERR\n"); 6346 break; 6347 case EXCP_DATA_ABORT: 6348 env->v7m.cfsr |= 6349 (R_V7M_CFSR_IBUSERR_MASK | R_V7M_CFSR_BFARVALID_MASK); 6350 env->v7m.bfar = env->exception.vaddress; 6351 qemu_log_mask(CPU_LOG_INT, 6352 "...with CFSR.IBUSERR and BFAR 0x%x\n", 6353 env->v7m.bfar); 6354 break; 6355 } 6356 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS); 6357 break; 6358 default: 6359 /* All other FSR values are either MPU faults or "can't happen 6360 * for M profile" cases. 6361 */ 6362 switch (cs->exception_index) { 6363 case EXCP_PREFETCH_ABORT: 6364 env->v7m.cfsr |= R_V7M_CFSR_IACCVIOL_MASK; 6365 qemu_log_mask(CPU_LOG_INT, "...with CFSR.IACCVIOL\n"); 6366 break; 6367 case EXCP_DATA_ABORT: 6368 env->v7m.cfsr |= 6369 (R_V7M_CFSR_DACCVIOL_MASK | R_V7M_CFSR_MMARVALID_MASK); 6370 env->v7m.mmfar = env->exception.vaddress; 6371 qemu_log_mask(CPU_LOG_INT, 6372 "...with CFSR.DACCVIOL and MMFAR 0x%x\n", 6373 env->v7m.mmfar); 6374 break; 6375 } 6376 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM); 6377 break; 6378 } 6379 break; 6380 case EXCP_BKPT: 6381 if (semihosting_enabled()) { 6382 int nr; 6383 nr = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env)) & 0xff; 6384 if (nr == 0xab) { 6385 env->regs[15] += 2; 6386 qemu_log_mask(CPU_LOG_INT, 6387 "...handling as semihosting call 0x%x\n", 6388 env->regs[0]); 6389 env->regs[0] = do_arm_semihosting(env); 6390 return; 6391 } 6392 } 6393 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG); 6394 break; 6395 case EXCP_IRQ: 6396 break; 6397 case EXCP_EXCEPTION_EXIT: 6398 do_v7m_exception_exit(cpu); 6399 return; 6400 default: 6401 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); 6402 return; /* Never happens. Keep compiler happy. */ 6403 } 6404 6405 v7m_push_stack(cpu); 6406 v7m_exception_taken(cpu, lr); 6407 qemu_log_mask(CPU_LOG_INT, "... as %d\n", env->v7m.exception); 6408 } 6409 6410 /* Function used to synchronize QEMU's AArch64 register set with AArch32 6411 * register set. This is necessary when switching between AArch32 and AArch64 6412 * execution state. 6413 */ 6414 void aarch64_sync_32_to_64(CPUARMState *env) 6415 { 6416 int i; 6417 uint32_t mode = env->uncached_cpsr & CPSR_M; 6418 6419 /* We can blanket copy R[0:7] to X[0:7] */ 6420 for (i = 0; i < 8; i++) { 6421 env->xregs[i] = env->regs[i]; 6422 } 6423 6424 /* Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12. 6425 * Otherwise, they come from the banked user regs. 6426 */ 6427 if (mode == ARM_CPU_MODE_FIQ) { 6428 for (i = 8; i < 13; i++) { 6429 env->xregs[i] = env->usr_regs[i - 8]; 6430 } 6431 } else { 6432 for (i = 8; i < 13; i++) { 6433 env->xregs[i] = env->regs[i]; 6434 } 6435 } 6436 6437 /* Registers x13-x23 are the various mode SP and FP registers. Registers 6438 * r13 and r14 are only copied if we are in that mode, otherwise we copy 6439 * from the mode banked register. 6440 */ 6441 if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) { 6442 env->xregs[13] = env->regs[13]; 6443 env->xregs[14] = env->regs[14]; 6444 } else { 6445 env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)]; 6446 /* HYP is an exception in that it is copied from r14 */ 6447 if (mode == ARM_CPU_MODE_HYP) { 6448 env->xregs[14] = env->regs[14]; 6449 } else { 6450 env->xregs[14] = env->banked_r14[bank_number(ARM_CPU_MODE_USR)]; 6451 } 6452 } 6453 6454 if (mode == ARM_CPU_MODE_HYP) { 6455 env->xregs[15] = env->regs[13]; 6456 } else { 6457 env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)]; 6458 } 6459 6460 if (mode == ARM_CPU_MODE_IRQ) { 6461 env->xregs[16] = env->regs[14]; 6462 env->xregs[17] = env->regs[13]; 6463 } else { 6464 env->xregs[16] = env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)]; 6465 env->xregs[17] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)]; 6466 } 6467 6468 if (mode == ARM_CPU_MODE_SVC) { 6469 env->xregs[18] = env->regs[14]; 6470 env->xregs[19] = env->regs[13]; 6471 } else { 6472 env->xregs[18] = env->banked_r14[bank_number(ARM_CPU_MODE_SVC)]; 6473 env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)]; 6474 } 6475 6476 if (mode == ARM_CPU_MODE_ABT) { 6477 env->xregs[20] = env->regs[14]; 6478 env->xregs[21] = env->regs[13]; 6479 } else { 6480 env->xregs[20] = env->banked_r14[bank_number(ARM_CPU_MODE_ABT)]; 6481 env->xregs[21] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)]; 6482 } 6483 6484 if (mode == ARM_CPU_MODE_UND) { 6485 env->xregs[22] = env->regs[14]; 6486 env->xregs[23] = env->regs[13]; 6487 } else { 6488 env->xregs[22] = env->banked_r14[bank_number(ARM_CPU_MODE_UND)]; 6489 env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)]; 6490 } 6491 6492 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ 6493 * mode, then we can copy from r8-r14. Otherwise, we copy from the 6494 * FIQ bank for r8-r14. 6495 */ 6496 if (mode == ARM_CPU_MODE_FIQ) { 6497 for (i = 24; i < 31; i++) { 6498 env->xregs[i] = env->regs[i - 16]; /* X[24:30] <- R[8:14] */ 6499 } 6500 } else { 6501 for (i = 24; i < 29; i++) { 6502 env->xregs[i] = env->fiq_regs[i - 24]; 6503 } 6504 env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)]; 6505 env->xregs[30] = env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)]; 6506 } 6507 6508 env->pc = env->regs[15]; 6509 } 6510 6511 /* Function used to synchronize QEMU's AArch32 register set with AArch64 6512 * register set. This is necessary when switching between AArch32 and AArch64 6513 * execution state. 6514 */ 6515 void aarch64_sync_64_to_32(CPUARMState *env) 6516 { 6517 int i; 6518 uint32_t mode = env->uncached_cpsr & CPSR_M; 6519 6520 /* We can blanket copy X[0:7] to R[0:7] */ 6521 for (i = 0; i < 8; i++) { 6522 env->regs[i] = env->xregs[i]; 6523 } 6524 6525 /* Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12. 6526 * Otherwise, we copy x8-x12 into the banked user regs. 6527 */ 6528 if (mode == ARM_CPU_MODE_FIQ) { 6529 for (i = 8; i < 13; i++) { 6530 env->usr_regs[i - 8] = env->xregs[i]; 6531 } 6532 } else { 6533 for (i = 8; i < 13; i++) { 6534 env->regs[i] = env->xregs[i]; 6535 } 6536 } 6537 6538 /* Registers r13 & r14 depend on the current mode. 6539 * If we are in a given mode, we copy the corresponding x registers to r13 6540 * and r14. Otherwise, we copy the x register to the banked r13 and r14 6541 * for the mode. 6542 */ 6543 if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) { 6544 env->regs[13] = env->xregs[13]; 6545 env->regs[14] = env->xregs[14]; 6546 } else { 6547 env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13]; 6548 6549 /* HYP is an exception in that it does not have its own banked r14 but 6550 * shares the USR r14 6551 */ 6552 if (mode == ARM_CPU_MODE_HYP) { 6553 env->regs[14] = env->xregs[14]; 6554 } else { 6555 env->banked_r14[bank_number(ARM_CPU_MODE_USR)] = env->xregs[14]; 6556 } 6557 } 6558 6559 if (mode == ARM_CPU_MODE_HYP) { 6560 env->regs[13] = env->xregs[15]; 6561 } else { 6562 env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15]; 6563 } 6564 6565 if (mode == ARM_CPU_MODE_IRQ) { 6566 env->regs[14] = env->xregs[16]; 6567 env->regs[13] = env->xregs[17]; 6568 } else { 6569 env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16]; 6570 env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17]; 6571 } 6572 6573 if (mode == ARM_CPU_MODE_SVC) { 6574 env->regs[14] = env->xregs[18]; 6575 env->regs[13] = env->xregs[19]; 6576 } else { 6577 env->banked_r14[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18]; 6578 env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19]; 6579 } 6580 6581 if (mode == ARM_CPU_MODE_ABT) { 6582 env->regs[14] = env->xregs[20]; 6583 env->regs[13] = env->xregs[21]; 6584 } else { 6585 env->banked_r14[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20]; 6586 env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21]; 6587 } 6588 6589 if (mode == ARM_CPU_MODE_UND) { 6590 env->regs[14] = env->xregs[22]; 6591 env->regs[13] = env->xregs[23]; 6592 } else { 6593 env->banked_r14[bank_number(ARM_CPU_MODE_UND)] = env->xregs[22]; 6594 env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23]; 6595 } 6596 6597 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ 6598 * mode, then we can copy to r8-r14. Otherwise, we copy to the 6599 * FIQ bank for r8-r14. 6600 */ 6601 if (mode == ARM_CPU_MODE_FIQ) { 6602 for (i = 24; i < 31; i++) { 6603 env->regs[i - 16] = env->xregs[i]; /* X[24:30] -> R[8:14] */ 6604 } 6605 } else { 6606 for (i = 24; i < 29; i++) { 6607 env->fiq_regs[i - 24] = env->xregs[i]; 6608 } 6609 env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29]; 6610 env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30]; 6611 } 6612 6613 env->regs[15] = env->pc; 6614 } 6615 6616 static void arm_cpu_do_interrupt_aarch32(CPUState *cs) 6617 { 6618 ARMCPU *cpu = ARM_CPU(cs); 6619 CPUARMState *env = &cpu->env; 6620 uint32_t addr; 6621 uint32_t mask; 6622 int new_mode; 6623 uint32_t offset; 6624 uint32_t moe; 6625 6626 /* If this is a debug exception we must update the DBGDSCR.MOE bits */ 6627 switch (env->exception.syndrome >> ARM_EL_EC_SHIFT) { 6628 case EC_BREAKPOINT: 6629 case EC_BREAKPOINT_SAME_EL: 6630 moe = 1; 6631 break; 6632 case EC_WATCHPOINT: 6633 case EC_WATCHPOINT_SAME_EL: 6634 moe = 10; 6635 break; 6636 case EC_AA32_BKPT: 6637 moe = 3; 6638 break; 6639 case EC_VECTORCATCH: 6640 moe = 5; 6641 break; 6642 default: 6643 moe = 0; 6644 break; 6645 } 6646 6647 if (moe) { 6648 env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe); 6649 } 6650 6651 /* TODO: Vectored interrupt controller. */ 6652 switch (cs->exception_index) { 6653 case EXCP_UDEF: 6654 new_mode = ARM_CPU_MODE_UND; 6655 addr = 0x04; 6656 mask = CPSR_I; 6657 if (env->thumb) 6658 offset = 2; 6659 else 6660 offset = 4; 6661 break; 6662 case EXCP_SWI: 6663 new_mode = ARM_CPU_MODE_SVC; 6664 addr = 0x08; 6665 mask = CPSR_I; 6666 /* The PC already points to the next instruction. */ 6667 offset = 0; 6668 break; 6669 case EXCP_BKPT: 6670 env->exception.fsr = 2; 6671 /* Fall through to prefetch abort. */ 6672 case EXCP_PREFETCH_ABORT: 6673 A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr); 6674 A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress); 6675 qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n", 6676 env->exception.fsr, (uint32_t)env->exception.vaddress); 6677 new_mode = ARM_CPU_MODE_ABT; 6678 addr = 0x0c; 6679 mask = CPSR_A | CPSR_I; 6680 offset = 4; 6681 break; 6682 case EXCP_DATA_ABORT: 6683 A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); 6684 A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress); 6685 qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n", 6686 env->exception.fsr, 6687 (uint32_t)env->exception.vaddress); 6688 new_mode = ARM_CPU_MODE_ABT; 6689 addr = 0x10; 6690 mask = CPSR_A | CPSR_I; 6691 offset = 8; 6692 break; 6693 case EXCP_IRQ: 6694 new_mode = ARM_CPU_MODE_IRQ; 6695 addr = 0x18; 6696 /* Disable IRQ and imprecise data aborts. */ 6697 mask = CPSR_A | CPSR_I; 6698 offset = 4; 6699 if (env->cp15.scr_el3 & SCR_IRQ) { 6700 /* IRQ routed to monitor mode */ 6701 new_mode = ARM_CPU_MODE_MON; 6702 mask |= CPSR_F; 6703 } 6704 break; 6705 case EXCP_FIQ: 6706 new_mode = ARM_CPU_MODE_FIQ; 6707 addr = 0x1c; 6708 /* Disable FIQ, IRQ and imprecise data aborts. */ 6709 mask = CPSR_A | CPSR_I | CPSR_F; 6710 if (env->cp15.scr_el3 & SCR_FIQ) { 6711 /* FIQ routed to monitor mode */ 6712 new_mode = ARM_CPU_MODE_MON; 6713 } 6714 offset = 4; 6715 break; 6716 case EXCP_VIRQ: 6717 new_mode = ARM_CPU_MODE_IRQ; 6718 addr = 0x18; 6719 /* Disable IRQ and imprecise data aborts. */ 6720 mask = CPSR_A | CPSR_I; 6721 offset = 4; 6722 break; 6723 case EXCP_VFIQ: 6724 new_mode = ARM_CPU_MODE_FIQ; 6725 addr = 0x1c; 6726 /* Disable FIQ, IRQ and imprecise data aborts. */ 6727 mask = CPSR_A | CPSR_I | CPSR_F; 6728 offset = 4; 6729 break; 6730 case EXCP_SMC: 6731 new_mode = ARM_CPU_MODE_MON; 6732 addr = 0x08; 6733 mask = CPSR_A | CPSR_I | CPSR_F; 6734 offset = 0; 6735 break; 6736 default: 6737 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); 6738 return; /* Never happens. Keep compiler happy. */ 6739 } 6740 6741 if (new_mode == ARM_CPU_MODE_MON) { 6742 addr += env->cp15.mvbar; 6743 } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 6744 /* High vectors. When enabled, base address cannot be remapped. */ 6745 addr += 0xffff0000; 6746 } else { 6747 /* ARM v7 architectures provide a vector base address register to remap 6748 * the interrupt vector table. 6749 * This register is only followed in non-monitor mode, and is banked. 6750 * Note: only bits 31:5 are valid. 6751 */ 6752 addr += A32_BANKED_CURRENT_REG_GET(env, vbar); 6753 } 6754 6755 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 6756 env->cp15.scr_el3 &= ~SCR_NS; 6757 } 6758 6759 switch_mode (env, new_mode); 6760 /* For exceptions taken to AArch32 we must clear the SS bit in both 6761 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now. 6762 */ 6763 env->uncached_cpsr &= ~PSTATE_SS; 6764 env->spsr = cpsr_read(env); 6765 /* Clear IT bits. */ 6766 env->condexec_bits = 0; 6767 /* Switch to the new mode, and to the correct instruction set. */ 6768 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; 6769 /* Set new mode endianness */ 6770 env->uncached_cpsr &= ~CPSR_E; 6771 if (env->cp15.sctlr_el[arm_current_el(env)] & SCTLR_EE) { 6772 env->uncached_cpsr |= CPSR_E; 6773 } 6774 env->daif |= mask; 6775 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares 6776 * and we should just guard the thumb mode on V4 */ 6777 if (arm_feature(env, ARM_FEATURE_V4T)) { 6778 env->thumb = (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0; 6779 } 6780 env->regs[14] = env->regs[15] + offset; 6781 env->regs[15] = addr; 6782 } 6783 6784 /* Handle exception entry to a target EL which is using AArch64 */ 6785 static void arm_cpu_do_interrupt_aarch64(CPUState *cs) 6786 { 6787 ARMCPU *cpu = ARM_CPU(cs); 6788 CPUARMState *env = &cpu->env; 6789 unsigned int new_el = env->exception.target_el; 6790 target_ulong addr = env->cp15.vbar_el[new_el]; 6791 unsigned int new_mode = aarch64_pstate_mode(new_el, true); 6792 6793 if (arm_current_el(env) < new_el) { 6794 /* Entry vector offset depends on whether the implemented EL 6795 * immediately lower than the target level is using AArch32 or AArch64 6796 */ 6797 bool is_aa64; 6798 6799 switch (new_el) { 6800 case 3: 6801 is_aa64 = (env->cp15.scr_el3 & SCR_RW) != 0; 6802 break; 6803 case 2: 6804 is_aa64 = (env->cp15.hcr_el2 & HCR_RW) != 0; 6805 break; 6806 case 1: 6807 is_aa64 = is_a64(env); 6808 break; 6809 default: 6810 g_assert_not_reached(); 6811 } 6812 6813 if (is_aa64) { 6814 addr += 0x400; 6815 } else { 6816 addr += 0x600; 6817 } 6818 } else if (pstate_read(env) & PSTATE_SP) { 6819 addr += 0x200; 6820 } 6821 6822 switch (cs->exception_index) { 6823 case EXCP_PREFETCH_ABORT: 6824 case EXCP_DATA_ABORT: 6825 env->cp15.far_el[new_el] = env->exception.vaddress; 6826 qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n", 6827 env->cp15.far_el[new_el]); 6828 /* fall through */ 6829 case EXCP_BKPT: 6830 case EXCP_UDEF: 6831 case EXCP_SWI: 6832 case EXCP_HVC: 6833 case EXCP_HYP_TRAP: 6834 case EXCP_SMC: 6835 env->cp15.esr_el[new_el] = env->exception.syndrome; 6836 break; 6837 case EXCP_IRQ: 6838 case EXCP_VIRQ: 6839 addr += 0x80; 6840 break; 6841 case EXCP_FIQ: 6842 case EXCP_VFIQ: 6843 addr += 0x100; 6844 break; 6845 case EXCP_SEMIHOST: 6846 qemu_log_mask(CPU_LOG_INT, 6847 "...handling as semihosting call 0x%" PRIx64 "\n", 6848 env->xregs[0]); 6849 env->xregs[0] = do_arm_semihosting(env); 6850 return; 6851 default: 6852 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); 6853 } 6854 6855 if (is_a64(env)) { 6856 env->banked_spsr[aarch64_banked_spsr_index(new_el)] = pstate_read(env); 6857 aarch64_save_sp(env, arm_current_el(env)); 6858 env->elr_el[new_el] = env->pc; 6859 } else { 6860 env->banked_spsr[aarch64_banked_spsr_index(new_el)] = cpsr_read(env); 6861 env->elr_el[new_el] = env->regs[15]; 6862 6863 aarch64_sync_32_to_64(env); 6864 6865 env->condexec_bits = 0; 6866 } 6867 qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n", 6868 env->elr_el[new_el]); 6869 6870 pstate_write(env, PSTATE_DAIF | new_mode); 6871 env->aarch64 = 1; 6872 aarch64_restore_sp(env, new_el); 6873 6874 env->pc = addr; 6875 6876 qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 " PSTATE 0x%x\n", 6877 new_el, env->pc, pstate_read(env)); 6878 } 6879 6880 static inline bool check_for_semihosting(CPUState *cs) 6881 { 6882 /* Check whether this exception is a semihosting call; if so 6883 * then handle it and return true; otherwise return false. 6884 */ 6885 ARMCPU *cpu = ARM_CPU(cs); 6886 CPUARMState *env = &cpu->env; 6887 6888 if (is_a64(env)) { 6889 if (cs->exception_index == EXCP_SEMIHOST) { 6890 /* This is always the 64-bit semihosting exception. 6891 * The "is this usermode" and "is semihosting enabled" 6892 * checks have been done at translate time. 6893 */ 6894 qemu_log_mask(CPU_LOG_INT, 6895 "...handling as semihosting call 0x%" PRIx64 "\n", 6896 env->xregs[0]); 6897 env->xregs[0] = do_arm_semihosting(env); 6898 return true; 6899 } 6900 return false; 6901 } else { 6902 uint32_t imm; 6903 6904 /* Only intercept calls from privileged modes, to provide some 6905 * semblance of security. 6906 */ 6907 if (cs->exception_index != EXCP_SEMIHOST && 6908 (!semihosting_enabled() || 6909 ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR))) { 6910 return false; 6911 } 6912 6913 switch (cs->exception_index) { 6914 case EXCP_SEMIHOST: 6915 /* This is always a semihosting call; the "is this usermode" 6916 * and "is semihosting enabled" checks have been done at 6917 * translate time. 6918 */ 6919 break; 6920 case EXCP_SWI: 6921 /* Check for semihosting interrupt. */ 6922 if (env->thumb) { 6923 imm = arm_lduw_code(env, env->regs[15] - 2, arm_sctlr_b(env)) 6924 & 0xff; 6925 if (imm == 0xab) { 6926 break; 6927 } 6928 } else { 6929 imm = arm_ldl_code(env, env->regs[15] - 4, arm_sctlr_b(env)) 6930 & 0xffffff; 6931 if (imm == 0x123456) { 6932 break; 6933 } 6934 } 6935 return false; 6936 case EXCP_BKPT: 6937 /* See if this is a semihosting syscall. */ 6938 if (env->thumb) { 6939 imm = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env)) 6940 & 0xff; 6941 if (imm == 0xab) { 6942 env->regs[15] += 2; 6943 break; 6944 } 6945 } 6946 return false; 6947 default: 6948 return false; 6949 } 6950 6951 qemu_log_mask(CPU_LOG_INT, 6952 "...handling as semihosting call 0x%x\n", 6953 env->regs[0]); 6954 env->regs[0] = do_arm_semihosting(env); 6955 return true; 6956 } 6957 } 6958 6959 /* Handle a CPU exception for A and R profile CPUs. 6960 * Do any appropriate logging, handle PSCI calls, and then hand off 6961 * to the AArch64-entry or AArch32-entry function depending on the 6962 * target exception level's register width. 6963 */ 6964 void arm_cpu_do_interrupt(CPUState *cs) 6965 { 6966 ARMCPU *cpu = ARM_CPU(cs); 6967 CPUARMState *env = &cpu->env; 6968 unsigned int new_el = env->exception.target_el; 6969 6970 assert(!arm_feature(env, ARM_FEATURE_M)); 6971 6972 arm_log_exception(cs->exception_index); 6973 qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(env), 6974 new_el); 6975 if (qemu_loglevel_mask(CPU_LOG_INT) 6976 && !excp_is_internal(cs->exception_index)) { 6977 qemu_log_mask(CPU_LOG_INT, "...with ESR 0x%x/0x%" PRIx32 "\n", 6978 env->exception.syndrome >> ARM_EL_EC_SHIFT, 6979 env->exception.syndrome); 6980 } 6981 6982 if (arm_is_psci_call(cpu, cs->exception_index)) { 6983 arm_handle_psci_call(cpu); 6984 qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); 6985 return; 6986 } 6987 6988 /* Semihosting semantics depend on the register width of the 6989 * code that caused the exception, not the target exception level, 6990 * so must be handled here. 6991 */ 6992 if (check_for_semihosting(cs)) { 6993 return; 6994 } 6995 6996 assert(!excp_is_internal(cs->exception_index)); 6997 if (arm_el_is_aa64(env, new_el)) { 6998 arm_cpu_do_interrupt_aarch64(cs); 6999 } else { 7000 arm_cpu_do_interrupt_aarch32(cs); 7001 } 7002 7003 /* Hooks may change global state so BQL should be held, also the 7004 * BQL needs to be held for any modification of 7005 * cs->interrupt_request. 7006 */ 7007 g_assert(qemu_mutex_iothread_locked()); 7008 7009 arm_call_el_change_hook(cpu); 7010 7011 if (!kvm_enabled()) { 7012 cs->interrupt_request |= CPU_INTERRUPT_EXITTB; 7013 } 7014 } 7015 7016 /* Return the exception level which controls this address translation regime */ 7017 static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) 7018 { 7019 switch (mmu_idx) { 7020 case ARMMMUIdx_S2NS: 7021 case ARMMMUIdx_S1E2: 7022 return 2; 7023 case ARMMMUIdx_S1E3: 7024 return 3; 7025 case ARMMMUIdx_S1SE0: 7026 return arm_el_is_aa64(env, 3) ? 1 : 3; 7027 case ARMMMUIdx_S1SE1: 7028 case ARMMMUIdx_S1NSE0: 7029 case ARMMMUIdx_S1NSE1: 7030 case ARMMMUIdx_MPriv: 7031 case ARMMMUIdx_MNegPri: 7032 case ARMMMUIdx_MUser: 7033 return 1; 7034 default: 7035 g_assert_not_reached(); 7036 } 7037 } 7038 7039 /* Return true if this address translation regime is secure */ 7040 static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) 7041 { 7042 switch (mmu_idx) { 7043 case ARMMMUIdx_S12NSE0: 7044 case ARMMMUIdx_S12NSE1: 7045 case ARMMMUIdx_S1NSE0: 7046 case ARMMMUIdx_S1NSE1: 7047 case ARMMMUIdx_S1E2: 7048 case ARMMMUIdx_S2NS: 7049 case ARMMMUIdx_MPriv: 7050 case ARMMMUIdx_MNegPri: 7051 case ARMMMUIdx_MUser: 7052 return false; 7053 case ARMMMUIdx_S1E3: 7054 case ARMMMUIdx_S1SE0: 7055 case ARMMMUIdx_S1SE1: 7056 return true; 7057 default: 7058 g_assert_not_reached(); 7059 } 7060 } 7061 7062 /* Return the SCTLR value which controls this address translation regime */ 7063 static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) 7064 { 7065 return env->cp15.sctlr_el[regime_el(env, mmu_idx)]; 7066 } 7067 7068 /* Return true if the specified stage of address translation is disabled */ 7069 static inline bool regime_translation_disabled(CPUARMState *env, 7070 ARMMMUIdx mmu_idx) 7071 { 7072 if (arm_feature(env, ARM_FEATURE_M)) { 7073 switch (env->v7m.mpu_ctrl & 7074 (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) { 7075 case R_V7M_MPU_CTRL_ENABLE_MASK: 7076 /* Enabled, but not for HardFault and NMI */ 7077 return mmu_idx == ARMMMUIdx_MNegPri; 7078 case R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK: 7079 /* Enabled for all cases */ 7080 return false; 7081 case 0: 7082 default: 7083 /* HFNMIENA set and ENABLE clear is UNPREDICTABLE, but 7084 * we warned about that in armv7m_nvic.c when the guest set it. 7085 */ 7086 return true; 7087 } 7088 } 7089 7090 if (mmu_idx == ARMMMUIdx_S2NS) { 7091 return (env->cp15.hcr_el2 & HCR_VM) == 0; 7092 } 7093 return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0; 7094 } 7095 7096 static inline bool regime_translation_big_endian(CPUARMState *env, 7097 ARMMMUIdx mmu_idx) 7098 { 7099 return (regime_sctlr(env, mmu_idx) & SCTLR_EE) != 0; 7100 } 7101 7102 /* Return the TCR controlling this translation regime */ 7103 static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) 7104 { 7105 if (mmu_idx == ARMMMUIdx_S2NS) { 7106 return &env->cp15.vtcr_el2; 7107 } 7108 return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; 7109 } 7110 7111 /* Convert a possible stage1+2 MMU index into the appropriate 7112 * stage 1 MMU index 7113 */ 7114 static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) 7115 { 7116 if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { 7117 mmu_idx += (ARMMMUIdx_S1NSE0 - ARMMMUIdx_S12NSE0); 7118 } 7119 return mmu_idx; 7120 } 7121 7122 /* Returns TBI0 value for current regime el */ 7123 uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx) 7124 { 7125 TCR *tcr; 7126 uint32_t el; 7127 7128 /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert 7129 * a stage 1+2 mmu index into the appropriate stage 1 mmu index. 7130 */ 7131 mmu_idx = stage_1_mmu_idx(mmu_idx); 7132 7133 tcr = regime_tcr(env, mmu_idx); 7134 el = regime_el(env, mmu_idx); 7135 7136 if (el > 1) { 7137 return extract64(tcr->raw_tcr, 20, 1); 7138 } else { 7139 return extract64(tcr->raw_tcr, 37, 1); 7140 } 7141 } 7142 7143 /* Returns TBI1 value for current regime el */ 7144 uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx) 7145 { 7146 TCR *tcr; 7147 uint32_t el; 7148 7149 /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert 7150 * a stage 1+2 mmu index into the appropriate stage 1 mmu index. 7151 */ 7152 mmu_idx = stage_1_mmu_idx(mmu_idx); 7153 7154 tcr = regime_tcr(env, mmu_idx); 7155 el = regime_el(env, mmu_idx); 7156 7157 if (el > 1) { 7158 return 0; 7159 } else { 7160 return extract64(tcr->raw_tcr, 38, 1); 7161 } 7162 } 7163 7164 /* Return the TTBR associated with this translation regime */ 7165 static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, 7166 int ttbrn) 7167 { 7168 if (mmu_idx == ARMMMUIdx_S2NS) { 7169 return env->cp15.vttbr_el2; 7170 } 7171 if (ttbrn == 0) { 7172 return env->cp15.ttbr0_el[regime_el(env, mmu_idx)]; 7173 } else { 7174 return env->cp15.ttbr1_el[regime_el(env, mmu_idx)]; 7175 } 7176 } 7177 7178 /* Return true if the translation regime is using LPAE format page tables */ 7179 static inline bool regime_using_lpae_format(CPUARMState *env, 7180 ARMMMUIdx mmu_idx) 7181 { 7182 int el = regime_el(env, mmu_idx); 7183 if (el == 2 || arm_el_is_aa64(env, el)) { 7184 return true; 7185 } 7186 if (arm_feature(env, ARM_FEATURE_LPAE) 7187 && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) { 7188 return true; 7189 } 7190 return false; 7191 } 7192 7193 /* Returns true if the stage 1 translation regime is using LPAE format page 7194 * tables. Used when raising alignment exceptions, whose FSR changes depending 7195 * on whether the long or short descriptor format is in use. */ 7196 bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) 7197 { 7198 mmu_idx = stage_1_mmu_idx(mmu_idx); 7199 7200 return regime_using_lpae_format(env, mmu_idx); 7201 } 7202 7203 static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) 7204 { 7205 switch (mmu_idx) { 7206 case ARMMMUIdx_S1SE0: 7207 case ARMMMUIdx_S1NSE0: 7208 case ARMMMUIdx_MUser: 7209 return true; 7210 default: 7211 return false; 7212 case ARMMMUIdx_S12NSE0: 7213 case ARMMMUIdx_S12NSE1: 7214 g_assert_not_reached(); 7215 } 7216 } 7217 7218 /* Translate section/page access permissions to page 7219 * R/W protection flags 7220 * 7221 * @env: CPUARMState 7222 * @mmu_idx: MMU index indicating required translation regime 7223 * @ap: The 3-bit access permissions (AP[2:0]) 7224 * @domain_prot: The 2-bit domain access permissions 7225 */ 7226 static inline int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, 7227 int ap, int domain_prot) 7228 { 7229 bool is_user = regime_is_user(env, mmu_idx); 7230 7231 if (domain_prot == 3) { 7232 return PAGE_READ | PAGE_WRITE; 7233 } 7234 7235 switch (ap) { 7236 case 0: 7237 if (arm_feature(env, ARM_FEATURE_V7)) { 7238 return 0; 7239 } 7240 switch (regime_sctlr(env, mmu_idx) & (SCTLR_S | SCTLR_R)) { 7241 case SCTLR_S: 7242 return is_user ? 0 : PAGE_READ; 7243 case SCTLR_R: 7244 return PAGE_READ; 7245 default: 7246 return 0; 7247 } 7248 case 1: 7249 return is_user ? 0 : PAGE_READ | PAGE_WRITE; 7250 case 2: 7251 if (is_user) { 7252 return PAGE_READ; 7253 } else { 7254 return PAGE_READ | PAGE_WRITE; 7255 } 7256 case 3: 7257 return PAGE_READ | PAGE_WRITE; 7258 case 4: /* Reserved. */ 7259 return 0; 7260 case 5: 7261 return is_user ? 0 : PAGE_READ; 7262 case 6: 7263 return PAGE_READ; 7264 case 7: 7265 if (!arm_feature(env, ARM_FEATURE_V6K)) { 7266 return 0; 7267 } 7268 return PAGE_READ; 7269 default: 7270 g_assert_not_reached(); 7271 } 7272 } 7273 7274 /* Translate section/page access permissions to page 7275 * R/W protection flags. 7276 * 7277 * @ap: The 2-bit simple AP (AP[2:1]) 7278 * @is_user: TRUE if accessing from PL0 7279 */ 7280 static inline int simple_ap_to_rw_prot_is_user(int ap, bool is_user) 7281 { 7282 switch (ap) { 7283 case 0: 7284 return is_user ? 0 : PAGE_READ | PAGE_WRITE; 7285 case 1: 7286 return PAGE_READ | PAGE_WRITE; 7287 case 2: 7288 return is_user ? 0 : PAGE_READ; 7289 case 3: 7290 return PAGE_READ; 7291 default: 7292 g_assert_not_reached(); 7293 } 7294 } 7295 7296 static inline int 7297 simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap) 7298 { 7299 return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx)); 7300 } 7301 7302 /* Translate S2 section/page access permissions to protection flags 7303 * 7304 * @env: CPUARMState 7305 * @s2ap: The 2-bit stage2 access permissions (S2AP) 7306 * @xn: XN (execute-never) bit 7307 */ 7308 static int get_S2prot(CPUARMState *env, int s2ap, int xn) 7309 { 7310 int prot = 0; 7311 7312 if (s2ap & 1) { 7313 prot |= PAGE_READ; 7314 } 7315 if (s2ap & 2) { 7316 prot |= PAGE_WRITE; 7317 } 7318 if (!xn) { 7319 if (arm_el_is_aa64(env, 2) || prot & PAGE_READ) { 7320 prot |= PAGE_EXEC; 7321 } 7322 } 7323 return prot; 7324 } 7325 7326 /* Translate section/page access permissions to protection flags 7327 * 7328 * @env: CPUARMState 7329 * @mmu_idx: MMU index indicating required translation regime 7330 * @is_aa64: TRUE if AArch64 7331 * @ap: The 2-bit simple AP (AP[2:1]) 7332 * @ns: NS (non-secure) bit 7333 * @xn: XN (execute-never) bit 7334 * @pxn: PXN (privileged execute-never) bit 7335 */ 7336 static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, 7337 int ap, int ns, int xn, int pxn) 7338 { 7339 bool is_user = regime_is_user(env, mmu_idx); 7340 int prot_rw, user_rw; 7341 bool have_wxn; 7342 int wxn = 0; 7343 7344 assert(mmu_idx != ARMMMUIdx_S2NS); 7345 7346 user_rw = simple_ap_to_rw_prot_is_user(ap, true); 7347 if (is_user) { 7348 prot_rw = user_rw; 7349 } else { 7350 prot_rw = simple_ap_to_rw_prot_is_user(ap, false); 7351 } 7352 7353 if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) { 7354 return prot_rw; 7355 } 7356 7357 /* TODO have_wxn should be replaced with 7358 * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2) 7359 * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE 7360 * compatible processors have EL2, which is required for [U]WXN. 7361 */ 7362 have_wxn = arm_feature(env, ARM_FEATURE_LPAE); 7363 7364 if (have_wxn) { 7365 wxn = regime_sctlr(env, mmu_idx) & SCTLR_WXN; 7366 } 7367 7368 if (is_aa64) { 7369 switch (regime_el(env, mmu_idx)) { 7370 case 1: 7371 if (!is_user) { 7372 xn = pxn || (user_rw & PAGE_WRITE); 7373 } 7374 break; 7375 case 2: 7376 case 3: 7377 break; 7378 } 7379 } else if (arm_feature(env, ARM_FEATURE_V7)) { 7380 switch (regime_el(env, mmu_idx)) { 7381 case 1: 7382 case 3: 7383 if (is_user) { 7384 xn = xn || !(user_rw & PAGE_READ); 7385 } else { 7386 int uwxn = 0; 7387 if (have_wxn) { 7388 uwxn = regime_sctlr(env, mmu_idx) & SCTLR_UWXN; 7389 } 7390 xn = xn || !(prot_rw & PAGE_READ) || pxn || 7391 (uwxn && (user_rw & PAGE_WRITE)); 7392 } 7393 break; 7394 case 2: 7395 break; 7396 } 7397 } else { 7398 xn = wxn = 0; 7399 } 7400 7401 if (xn || (wxn && (prot_rw & PAGE_WRITE))) { 7402 return prot_rw; 7403 } 7404 return prot_rw | PAGE_EXEC; 7405 } 7406 7407 static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, 7408 uint32_t *table, uint32_t address) 7409 { 7410 /* Note that we can only get here for an AArch32 PL0/PL1 lookup */ 7411 TCR *tcr = regime_tcr(env, mmu_idx); 7412 7413 if (address & tcr->mask) { 7414 if (tcr->raw_tcr & TTBCR_PD1) { 7415 /* Translation table walk disabled for TTBR1 */ 7416 return false; 7417 } 7418 *table = regime_ttbr(env, mmu_idx, 1) & 0xffffc000; 7419 } else { 7420 if (tcr->raw_tcr & TTBCR_PD0) { 7421 /* Translation table walk disabled for TTBR0 */ 7422 return false; 7423 } 7424 *table = regime_ttbr(env, mmu_idx, 0) & tcr->base_mask; 7425 } 7426 *table |= (address >> 18) & 0x3ffc; 7427 return true; 7428 } 7429 7430 /* Translate a S1 pagetable walk through S2 if needed. */ 7431 static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, 7432 hwaddr addr, MemTxAttrs txattrs, 7433 uint32_t *fsr, 7434 ARMMMUFaultInfo *fi) 7435 { 7436 if ((mmu_idx == ARMMMUIdx_S1NSE0 || mmu_idx == ARMMMUIdx_S1NSE1) && 7437 !regime_translation_disabled(env, ARMMMUIdx_S2NS)) { 7438 target_ulong s2size; 7439 hwaddr s2pa; 7440 int s2prot; 7441 int ret; 7442 7443 ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_S2NS, &s2pa, 7444 &txattrs, &s2prot, &s2size, fsr, fi); 7445 if (ret) { 7446 fi->s2addr = addr; 7447 fi->stage2 = true; 7448 fi->s1ptw = true; 7449 return ~0; 7450 } 7451 addr = s2pa; 7452 } 7453 return addr; 7454 } 7455 7456 /* All loads done in the course of a page table walk go through here. 7457 * TODO: rather than ignoring errors from physical memory reads (which 7458 * are external aborts in ARM terminology) we should propagate this 7459 * error out so that we can turn it into a Data Abort if this walk 7460 * was being done for a CPU load/store or an address translation instruction 7461 * (but not if it was for a debug access). 7462 */ 7463 static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure, 7464 ARMMMUIdx mmu_idx, uint32_t *fsr, 7465 ARMMMUFaultInfo *fi) 7466 { 7467 ARMCPU *cpu = ARM_CPU(cs); 7468 CPUARMState *env = &cpu->env; 7469 MemTxAttrs attrs = {}; 7470 AddressSpace *as; 7471 7472 attrs.secure = is_secure; 7473 as = arm_addressspace(cs, attrs); 7474 addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi); 7475 if (fi->s1ptw) { 7476 return 0; 7477 } 7478 if (regime_translation_big_endian(env, mmu_idx)) { 7479 return address_space_ldl_be(as, addr, attrs, NULL); 7480 } else { 7481 return address_space_ldl_le(as, addr, attrs, NULL); 7482 } 7483 } 7484 7485 static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, 7486 ARMMMUIdx mmu_idx, uint32_t *fsr, 7487 ARMMMUFaultInfo *fi) 7488 { 7489 ARMCPU *cpu = ARM_CPU(cs); 7490 CPUARMState *env = &cpu->env; 7491 MemTxAttrs attrs = {}; 7492 AddressSpace *as; 7493 7494 attrs.secure = is_secure; 7495 as = arm_addressspace(cs, attrs); 7496 addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi); 7497 if (fi->s1ptw) { 7498 return 0; 7499 } 7500 if (regime_translation_big_endian(env, mmu_idx)) { 7501 return address_space_ldq_be(as, addr, attrs, NULL); 7502 } else { 7503 return address_space_ldq_le(as, addr, attrs, NULL); 7504 } 7505 } 7506 7507 static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, 7508 int access_type, ARMMMUIdx mmu_idx, 7509 hwaddr *phys_ptr, int *prot, 7510 target_ulong *page_size, uint32_t *fsr, 7511 ARMMMUFaultInfo *fi) 7512 { 7513 CPUState *cs = CPU(arm_env_get_cpu(env)); 7514 int code; 7515 uint32_t table; 7516 uint32_t desc; 7517 int type; 7518 int ap; 7519 int domain = 0; 7520 int domain_prot; 7521 hwaddr phys_addr; 7522 uint32_t dacr; 7523 7524 /* Pagetable walk. */ 7525 /* Lookup l1 descriptor. */ 7526 if (!get_level1_table_address(env, mmu_idx, &table, address)) { 7527 /* Section translation fault if page walk is disabled by PD0 or PD1 */ 7528 code = 5; 7529 goto do_fault; 7530 } 7531 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), 7532 mmu_idx, fsr, fi); 7533 type = (desc & 3); 7534 domain = (desc >> 5) & 0x0f; 7535 if (regime_el(env, mmu_idx) == 1) { 7536 dacr = env->cp15.dacr_ns; 7537 } else { 7538 dacr = env->cp15.dacr_s; 7539 } 7540 domain_prot = (dacr >> (domain * 2)) & 3; 7541 if (type == 0) { 7542 /* Section translation fault. */ 7543 code = 5; 7544 goto do_fault; 7545 } 7546 if (domain_prot == 0 || domain_prot == 2) { 7547 if (type == 2) 7548 code = 9; /* Section domain fault. */ 7549 else 7550 code = 11; /* Page domain fault. */ 7551 goto do_fault; 7552 } 7553 if (type == 2) { 7554 /* 1Mb section. */ 7555 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); 7556 ap = (desc >> 10) & 3; 7557 code = 13; 7558 *page_size = 1024 * 1024; 7559 } else { 7560 /* Lookup l2 entry. */ 7561 if (type == 1) { 7562 /* Coarse pagetable. */ 7563 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); 7564 } else { 7565 /* Fine pagetable. */ 7566 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc); 7567 } 7568 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), 7569 mmu_idx, fsr, fi); 7570 switch (desc & 3) { 7571 case 0: /* Page translation fault. */ 7572 code = 7; 7573 goto do_fault; 7574 case 1: /* 64k page. */ 7575 phys_addr = (desc & 0xffff0000) | (address & 0xffff); 7576 ap = (desc >> (4 + ((address >> 13) & 6))) & 3; 7577 *page_size = 0x10000; 7578 break; 7579 case 2: /* 4k page. */ 7580 phys_addr = (desc & 0xfffff000) | (address & 0xfff); 7581 ap = (desc >> (4 + ((address >> 9) & 6))) & 3; 7582 *page_size = 0x1000; 7583 break; 7584 case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */ 7585 if (type == 1) { 7586 /* ARMv6/XScale extended small page format */ 7587 if (arm_feature(env, ARM_FEATURE_XSCALE) 7588 || arm_feature(env, ARM_FEATURE_V6)) { 7589 phys_addr = (desc & 0xfffff000) | (address & 0xfff); 7590 *page_size = 0x1000; 7591 } else { 7592 /* UNPREDICTABLE in ARMv5; we choose to take a 7593 * page translation fault. 7594 */ 7595 code = 7; 7596 goto do_fault; 7597 } 7598 } else { 7599 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff); 7600 *page_size = 0x400; 7601 } 7602 ap = (desc >> 4) & 3; 7603 break; 7604 default: 7605 /* Never happens, but compiler isn't smart enough to tell. */ 7606 abort(); 7607 } 7608 code = 15; 7609 } 7610 *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot); 7611 *prot |= *prot ? PAGE_EXEC : 0; 7612 if (!(*prot & (1 << access_type))) { 7613 /* Access permission fault. */ 7614 goto do_fault; 7615 } 7616 *phys_ptr = phys_addr; 7617 return false; 7618 do_fault: 7619 *fsr = code | (domain << 4); 7620 return true; 7621 } 7622 7623 static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, 7624 int access_type, ARMMMUIdx mmu_idx, 7625 hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, 7626 target_ulong *page_size, uint32_t *fsr, 7627 ARMMMUFaultInfo *fi) 7628 { 7629 CPUState *cs = CPU(arm_env_get_cpu(env)); 7630 int code; 7631 uint32_t table; 7632 uint32_t desc; 7633 uint32_t xn; 7634 uint32_t pxn = 0; 7635 int type; 7636 int ap; 7637 int domain = 0; 7638 int domain_prot; 7639 hwaddr phys_addr; 7640 uint32_t dacr; 7641 bool ns; 7642 7643 /* Pagetable walk. */ 7644 /* Lookup l1 descriptor. */ 7645 if (!get_level1_table_address(env, mmu_idx, &table, address)) { 7646 /* Section translation fault if page walk is disabled by PD0 or PD1 */ 7647 code = 5; 7648 goto do_fault; 7649 } 7650 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), 7651 mmu_idx, fsr, fi); 7652 type = (desc & 3); 7653 if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) { 7654 /* Section translation fault, or attempt to use the encoding 7655 * which is Reserved on implementations without PXN. 7656 */ 7657 code = 5; 7658 goto do_fault; 7659 } 7660 if ((type == 1) || !(desc & (1 << 18))) { 7661 /* Page or Section. */ 7662 domain = (desc >> 5) & 0x0f; 7663 } 7664 if (regime_el(env, mmu_idx) == 1) { 7665 dacr = env->cp15.dacr_ns; 7666 } else { 7667 dacr = env->cp15.dacr_s; 7668 } 7669 domain_prot = (dacr >> (domain * 2)) & 3; 7670 if (domain_prot == 0 || domain_prot == 2) { 7671 if (type != 1) { 7672 code = 9; /* Section domain fault. */ 7673 } else { 7674 code = 11; /* Page domain fault. */ 7675 } 7676 goto do_fault; 7677 } 7678 if (type != 1) { 7679 if (desc & (1 << 18)) { 7680 /* Supersection. */ 7681 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff); 7682 phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32; 7683 phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36; 7684 *page_size = 0x1000000; 7685 } else { 7686 /* Section. */ 7687 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); 7688 *page_size = 0x100000; 7689 } 7690 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4); 7691 xn = desc & (1 << 4); 7692 pxn = desc & 1; 7693 code = 13; 7694 ns = extract32(desc, 19, 1); 7695 } else { 7696 if (arm_feature(env, ARM_FEATURE_PXN)) { 7697 pxn = (desc >> 2) & 1; 7698 } 7699 ns = extract32(desc, 3, 1); 7700 /* Lookup l2 entry. */ 7701 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); 7702 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), 7703 mmu_idx, fsr, fi); 7704 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4); 7705 switch (desc & 3) { 7706 case 0: /* Page translation fault. */ 7707 code = 7; 7708 goto do_fault; 7709 case 1: /* 64k page. */ 7710 phys_addr = (desc & 0xffff0000) | (address & 0xffff); 7711 xn = desc & (1 << 15); 7712 *page_size = 0x10000; 7713 break; 7714 case 2: case 3: /* 4k page. */ 7715 phys_addr = (desc & 0xfffff000) | (address & 0xfff); 7716 xn = desc & 1; 7717 *page_size = 0x1000; 7718 break; 7719 default: 7720 /* Never happens, but compiler isn't smart enough to tell. */ 7721 abort(); 7722 } 7723 code = 15; 7724 } 7725 if (domain_prot == 3) { 7726 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 7727 } else { 7728 if (pxn && !regime_is_user(env, mmu_idx)) { 7729 xn = 1; 7730 } 7731 if (xn && access_type == 2) 7732 goto do_fault; 7733 7734 if (arm_feature(env, ARM_FEATURE_V6K) && 7735 (regime_sctlr(env, mmu_idx) & SCTLR_AFE)) { 7736 /* The simplified model uses AP[0] as an access control bit. */ 7737 if ((ap & 1) == 0) { 7738 /* Access flag fault. */ 7739 code = (code == 15) ? 6 : 3; 7740 goto do_fault; 7741 } 7742 *prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1); 7743 } else { 7744 *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot); 7745 } 7746 if (*prot && !xn) { 7747 *prot |= PAGE_EXEC; 7748 } 7749 if (!(*prot & (1 << access_type))) { 7750 /* Access permission fault. */ 7751 goto do_fault; 7752 } 7753 } 7754 if (ns) { 7755 /* The NS bit will (as required by the architecture) have no effect if 7756 * the CPU doesn't support TZ or this is a non-secure translation 7757 * regime, because the attribute will already be non-secure. 7758 */ 7759 attrs->secure = false; 7760 } 7761 *phys_ptr = phys_addr; 7762 return false; 7763 do_fault: 7764 *fsr = code | (domain << 4); 7765 return true; 7766 } 7767 7768 /* Fault type for long-descriptor MMU fault reporting; this corresponds 7769 * to bits [5..2] in the STATUS field in long-format DFSR/IFSR. 7770 */ 7771 typedef enum { 7772 translation_fault = 1, 7773 access_fault = 2, 7774 permission_fault = 3, 7775 } MMUFaultType; 7776 7777 /* 7778 * check_s2_mmu_setup 7779 * @cpu: ARMCPU 7780 * @is_aa64: True if the translation regime is in AArch64 state 7781 * @startlevel: Suggested starting level 7782 * @inputsize: Bitsize of IPAs 7783 * @stride: Page-table stride (See the ARM ARM) 7784 * 7785 * Returns true if the suggested S2 translation parameters are OK and 7786 * false otherwise. 7787 */ 7788 static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, 7789 int inputsize, int stride) 7790 { 7791 const int grainsize = stride + 3; 7792 int startsizecheck; 7793 7794 /* Negative levels are never allowed. */ 7795 if (level < 0) { 7796 return false; 7797 } 7798 7799 startsizecheck = inputsize - ((3 - level) * stride + grainsize); 7800 if (startsizecheck < 1 || startsizecheck > stride + 4) { 7801 return false; 7802 } 7803 7804 if (is_aa64) { 7805 CPUARMState *env = &cpu->env; 7806 unsigned int pamax = arm_pamax(cpu); 7807 7808 switch (stride) { 7809 case 13: /* 64KB Pages. */ 7810 if (level == 0 || (level == 1 && pamax <= 42)) { 7811 return false; 7812 } 7813 break; 7814 case 11: /* 16KB Pages. */ 7815 if (level == 0 || (level == 1 && pamax <= 40)) { 7816 return false; 7817 } 7818 break; 7819 case 9: /* 4KB Pages. */ 7820 if (level == 0 && pamax <= 42) { 7821 return false; 7822 } 7823 break; 7824 default: 7825 g_assert_not_reached(); 7826 } 7827 7828 /* Inputsize checks. */ 7829 if (inputsize > pamax && 7830 (arm_el_is_aa64(env, 1) || inputsize > 40)) { 7831 /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */ 7832 return false; 7833 } 7834 } else { 7835 /* AArch32 only supports 4KB pages. Assert on that. */ 7836 assert(stride == 9); 7837 7838 if (level == 0) { 7839 return false; 7840 } 7841 } 7842 return true; 7843 } 7844 7845 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, 7846 int access_type, ARMMMUIdx mmu_idx, 7847 hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, 7848 target_ulong *page_size_ptr, uint32_t *fsr, 7849 ARMMMUFaultInfo *fi) 7850 { 7851 ARMCPU *cpu = arm_env_get_cpu(env); 7852 CPUState *cs = CPU(cpu); 7853 /* Read an LPAE long-descriptor translation table. */ 7854 MMUFaultType fault_type = translation_fault; 7855 uint32_t level; 7856 uint32_t epd = 0; 7857 int32_t t0sz, t1sz; 7858 uint32_t tg; 7859 uint64_t ttbr; 7860 int ttbr_select; 7861 hwaddr descaddr, indexmask, indexmask_grainsize; 7862 uint32_t tableattrs; 7863 target_ulong page_size; 7864 uint32_t attrs; 7865 int32_t stride = 9; 7866 int32_t addrsize; 7867 int inputsize; 7868 int32_t tbi = 0; 7869 TCR *tcr = regime_tcr(env, mmu_idx); 7870 int ap, ns, xn, pxn; 7871 uint32_t el = regime_el(env, mmu_idx); 7872 bool ttbr1_valid = true; 7873 uint64_t descaddrmask; 7874 bool aarch64 = arm_el_is_aa64(env, el); 7875 7876 /* TODO: 7877 * This code does not handle the different format TCR for VTCR_EL2. 7878 * This code also does not support shareability levels. 7879 * Attribute and permission bit handling should also be checked when adding 7880 * support for those page table walks. 7881 */ 7882 if (aarch64) { 7883 level = 0; 7884 addrsize = 64; 7885 if (el > 1) { 7886 if (mmu_idx != ARMMMUIdx_S2NS) { 7887 tbi = extract64(tcr->raw_tcr, 20, 1); 7888 } 7889 } else { 7890 if (extract64(address, 55, 1)) { 7891 tbi = extract64(tcr->raw_tcr, 38, 1); 7892 } else { 7893 tbi = extract64(tcr->raw_tcr, 37, 1); 7894 } 7895 } 7896 tbi *= 8; 7897 7898 /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it 7899 * invalid. 7900 */ 7901 if (el > 1) { 7902 ttbr1_valid = false; 7903 } 7904 } else { 7905 level = 1; 7906 addrsize = 32; 7907 /* There is no TTBR1 for EL2 */ 7908 if (el == 2) { 7909 ttbr1_valid = false; 7910 } 7911 } 7912 7913 /* Determine whether this address is in the region controlled by 7914 * TTBR0 or TTBR1 (or if it is in neither region and should fault). 7915 * This is a Non-secure PL0/1 stage 1 translation, so controlled by 7916 * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32: 7917 */ 7918 if (aarch64) { 7919 /* AArch64 translation. */ 7920 t0sz = extract32(tcr->raw_tcr, 0, 6); 7921 t0sz = MIN(t0sz, 39); 7922 t0sz = MAX(t0sz, 16); 7923 } else if (mmu_idx != ARMMMUIdx_S2NS) { 7924 /* AArch32 stage 1 translation. */ 7925 t0sz = extract32(tcr->raw_tcr, 0, 3); 7926 } else { 7927 /* AArch32 stage 2 translation. */ 7928 bool sext = extract32(tcr->raw_tcr, 4, 1); 7929 bool sign = extract32(tcr->raw_tcr, 3, 1); 7930 /* Address size is 40-bit for a stage 2 translation, 7931 * and t0sz can be negative (from -8 to 7), 7932 * so we need to adjust it to use the TTBR selecting logic below. 7933 */ 7934 addrsize = 40; 7935 t0sz = sextract32(tcr->raw_tcr, 0, 4) + 8; 7936 7937 /* If the sign-extend bit is not the same as t0sz[3], the result 7938 * is unpredictable. Flag this as a guest error. */ 7939 if (sign != sext) { 7940 qemu_log_mask(LOG_GUEST_ERROR, 7941 "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n"); 7942 } 7943 } 7944 t1sz = extract32(tcr->raw_tcr, 16, 6); 7945 if (aarch64) { 7946 t1sz = MIN(t1sz, 39); 7947 t1sz = MAX(t1sz, 16); 7948 } 7949 if (t0sz && !extract64(address, addrsize - t0sz, t0sz - tbi)) { 7950 /* there is a ttbr0 region and we are in it (high bits all zero) */ 7951 ttbr_select = 0; 7952 } else if (ttbr1_valid && t1sz && 7953 !extract64(~address, addrsize - t1sz, t1sz - tbi)) { 7954 /* there is a ttbr1 region and we are in it (high bits all one) */ 7955 ttbr_select = 1; 7956 } else if (!t0sz) { 7957 /* ttbr0 region is "everything not in the ttbr1 region" */ 7958 ttbr_select = 0; 7959 } else if (!t1sz && ttbr1_valid) { 7960 /* ttbr1 region is "everything not in the ttbr0 region" */ 7961 ttbr_select = 1; 7962 } else { 7963 /* in the gap between the two regions, this is a Translation fault */ 7964 fault_type = translation_fault; 7965 goto do_fault; 7966 } 7967 7968 /* Note that QEMU ignores shareability and cacheability attributes, 7969 * so we don't need to do anything with the SH, ORGN, IRGN fields 7970 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the 7971 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently 7972 * implement any ASID-like capability so we can ignore it (instead 7973 * we will always flush the TLB any time the ASID is changed). 7974 */ 7975 if (ttbr_select == 0) { 7976 ttbr = regime_ttbr(env, mmu_idx, 0); 7977 if (el < 2) { 7978 epd = extract32(tcr->raw_tcr, 7, 1); 7979 } 7980 inputsize = addrsize - t0sz; 7981 7982 tg = extract32(tcr->raw_tcr, 14, 2); 7983 if (tg == 1) { /* 64KB pages */ 7984 stride = 13; 7985 } 7986 if (tg == 2) { /* 16KB pages */ 7987 stride = 11; 7988 } 7989 } else { 7990 /* We should only be here if TTBR1 is valid */ 7991 assert(ttbr1_valid); 7992 7993 ttbr = regime_ttbr(env, mmu_idx, 1); 7994 epd = extract32(tcr->raw_tcr, 23, 1); 7995 inputsize = addrsize - t1sz; 7996 7997 tg = extract32(tcr->raw_tcr, 30, 2); 7998 if (tg == 3) { /* 64KB pages */ 7999 stride = 13; 8000 } 8001 if (tg == 1) { /* 16KB pages */ 8002 stride = 11; 8003 } 8004 } 8005 8006 /* Here we should have set up all the parameters for the translation: 8007 * inputsize, ttbr, epd, stride, tbi 8008 */ 8009 8010 if (epd) { 8011 /* Translation table walk disabled => Translation fault on TLB miss 8012 * Note: This is always 0 on 64-bit EL2 and EL3. 8013 */ 8014 goto do_fault; 8015 } 8016 8017 if (mmu_idx != ARMMMUIdx_S2NS) { 8018 /* The starting level depends on the virtual address size (which can 8019 * be up to 48 bits) and the translation granule size. It indicates 8020 * the number of strides (stride bits at a time) needed to 8021 * consume the bits of the input address. In the pseudocode this is: 8022 * level = 4 - RoundUp((inputsize - grainsize) / stride) 8023 * where their 'inputsize' is our 'inputsize', 'grainsize' is 8024 * our 'stride + 3' and 'stride' is our 'stride'. 8025 * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying: 8026 * = 4 - (inputsize - stride - 3 + stride - 1) / stride 8027 * = 4 - (inputsize - 4) / stride; 8028 */ 8029 level = 4 - (inputsize - 4) / stride; 8030 } else { 8031 /* For stage 2 translations the starting level is specified by the 8032 * VTCR_EL2.SL0 field (whose interpretation depends on the page size) 8033 */ 8034 uint32_t sl0 = extract32(tcr->raw_tcr, 6, 2); 8035 uint32_t startlevel; 8036 bool ok; 8037 8038 if (!aarch64 || stride == 9) { 8039 /* AArch32 or 4KB pages */ 8040 startlevel = 2 - sl0; 8041 } else { 8042 /* 16KB or 64KB pages */ 8043 startlevel = 3 - sl0; 8044 } 8045 8046 /* Check that the starting level is valid. */ 8047 ok = check_s2_mmu_setup(cpu, aarch64, startlevel, 8048 inputsize, stride); 8049 if (!ok) { 8050 fault_type = translation_fault; 8051 goto do_fault; 8052 } 8053 level = startlevel; 8054 } 8055 8056 indexmask_grainsize = (1ULL << (stride + 3)) - 1; 8057 indexmask = (1ULL << (inputsize - (stride * (4 - level)))) - 1; 8058 8059 /* Now we can extract the actual base address from the TTBR */ 8060 descaddr = extract64(ttbr, 0, 48); 8061 descaddr &= ~indexmask; 8062 8063 /* The address field in the descriptor goes up to bit 39 for ARMv7 8064 * but up to bit 47 for ARMv8, but we use the descaddrmask 8065 * up to bit 39 for AArch32, because we don't need other bits in that case 8066 * to construct next descriptor address (anyway they should be all zeroes). 8067 */ 8068 descaddrmask = ((1ull << (aarch64 ? 48 : 40)) - 1) & 8069 ~indexmask_grainsize; 8070 8071 /* Secure accesses start with the page table in secure memory and 8072 * can be downgraded to non-secure at any step. Non-secure accesses 8073 * remain non-secure. We implement this by just ORing in the NSTable/NS 8074 * bits at each step. 8075 */ 8076 tableattrs = regime_is_secure(env, mmu_idx) ? 0 : (1 << 4); 8077 for (;;) { 8078 uint64_t descriptor; 8079 bool nstable; 8080 8081 descaddr |= (address >> (stride * (4 - level))) & indexmask; 8082 descaddr &= ~7ULL; 8083 nstable = extract32(tableattrs, 4, 1); 8084 descriptor = arm_ldq_ptw(cs, descaddr, !nstable, mmu_idx, fsr, fi); 8085 if (fi->s1ptw) { 8086 goto do_fault; 8087 } 8088 8089 if (!(descriptor & 1) || 8090 (!(descriptor & 2) && (level == 3))) { 8091 /* Invalid, or the Reserved level 3 encoding */ 8092 goto do_fault; 8093 } 8094 descaddr = descriptor & descaddrmask; 8095 8096 if ((descriptor & 2) && (level < 3)) { 8097 /* Table entry. The top five bits are attributes which may 8098 * propagate down through lower levels of the table (and 8099 * which are all arranged so that 0 means "no effect", so 8100 * we can gather them up by ORing in the bits at each level). 8101 */ 8102 tableattrs |= extract64(descriptor, 59, 5); 8103 level++; 8104 indexmask = indexmask_grainsize; 8105 continue; 8106 } 8107 /* Block entry at level 1 or 2, or page entry at level 3. 8108 * These are basically the same thing, although the number 8109 * of bits we pull in from the vaddr varies. 8110 */ 8111 page_size = (1ULL << ((stride * (4 - level)) + 3)); 8112 descaddr |= (address & (page_size - 1)); 8113 /* Extract attributes from the descriptor */ 8114 attrs = extract64(descriptor, 2, 10) 8115 | (extract64(descriptor, 52, 12) << 10); 8116 8117 if (mmu_idx == ARMMMUIdx_S2NS) { 8118 /* Stage 2 table descriptors do not include any attribute fields */ 8119 break; 8120 } 8121 /* Merge in attributes from table descriptors */ 8122 attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ 8123 attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */ 8124 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1 8125 * means "force PL1 access only", which means forcing AP[1] to 0. 8126 */ 8127 if (extract32(tableattrs, 2, 1)) { 8128 attrs &= ~(1 << 4); 8129 } 8130 attrs |= nstable << 3; /* NS */ 8131 break; 8132 } 8133 /* Here descaddr is the final physical address, and attributes 8134 * are all in attrs. 8135 */ 8136 fault_type = access_fault; 8137 if ((attrs & (1 << 8)) == 0) { 8138 /* Access flag */ 8139 goto do_fault; 8140 } 8141 8142 ap = extract32(attrs, 4, 2); 8143 xn = extract32(attrs, 12, 1); 8144 8145 if (mmu_idx == ARMMMUIdx_S2NS) { 8146 ns = true; 8147 *prot = get_S2prot(env, ap, xn); 8148 } else { 8149 ns = extract32(attrs, 3, 1); 8150 pxn = extract32(attrs, 11, 1); 8151 *prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn); 8152 } 8153 8154 fault_type = permission_fault; 8155 if (!(*prot & (1 << access_type))) { 8156 goto do_fault; 8157 } 8158 8159 if (ns) { 8160 /* The NS bit will (as required by the architecture) have no effect if 8161 * the CPU doesn't support TZ or this is a non-secure translation 8162 * regime, because the attribute will already be non-secure. 8163 */ 8164 txattrs->secure = false; 8165 } 8166 *phys_ptr = descaddr; 8167 *page_size_ptr = page_size; 8168 return false; 8169 8170 do_fault: 8171 /* Long-descriptor format IFSR/DFSR value */ 8172 *fsr = (1 << 9) | (fault_type << 2) | level; 8173 /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */ 8174 fi->stage2 = fi->s1ptw || (mmu_idx == ARMMMUIdx_S2NS); 8175 return true; 8176 } 8177 8178 static inline void get_phys_addr_pmsav7_default(CPUARMState *env, 8179 ARMMMUIdx mmu_idx, 8180 int32_t address, int *prot) 8181 { 8182 if (!arm_feature(env, ARM_FEATURE_M)) { 8183 *prot = PAGE_READ | PAGE_WRITE; 8184 switch (address) { 8185 case 0xF0000000 ... 0xFFFFFFFF: 8186 if (regime_sctlr(env, mmu_idx) & SCTLR_V) { 8187 /* hivecs execing is ok */ 8188 *prot |= PAGE_EXEC; 8189 } 8190 break; 8191 case 0x00000000 ... 0x7FFFFFFF: 8192 *prot |= PAGE_EXEC; 8193 break; 8194 } 8195 } else { 8196 /* Default system address map for M profile cores. 8197 * The architecture specifies which regions are execute-never; 8198 * at the MPU level no other checks are defined. 8199 */ 8200 switch (address) { 8201 case 0x00000000 ... 0x1fffffff: /* ROM */ 8202 case 0x20000000 ... 0x3fffffff: /* SRAM */ 8203 case 0x60000000 ... 0x7fffffff: /* RAM */ 8204 case 0x80000000 ... 0x9fffffff: /* RAM */ 8205 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 8206 break; 8207 case 0x40000000 ... 0x5fffffff: /* Peripheral */ 8208 case 0xa0000000 ... 0xbfffffff: /* Device */ 8209 case 0xc0000000 ... 0xdfffffff: /* Device */ 8210 case 0xe0000000 ... 0xffffffff: /* System */ 8211 *prot = PAGE_READ | PAGE_WRITE; 8212 break; 8213 default: 8214 g_assert_not_reached(); 8215 } 8216 } 8217 } 8218 8219 static bool pmsav7_use_background_region(ARMCPU *cpu, 8220 ARMMMUIdx mmu_idx, bool is_user) 8221 { 8222 /* Return true if we should use the default memory map as a 8223 * "background" region if there are no hits against any MPU regions. 8224 */ 8225 CPUARMState *env = &cpu->env; 8226 8227 if (is_user) { 8228 return false; 8229 } 8230 8231 if (arm_feature(env, ARM_FEATURE_M)) { 8232 return env->v7m.mpu_ctrl & R_V7M_MPU_CTRL_PRIVDEFENA_MASK; 8233 } else { 8234 return regime_sctlr(env, mmu_idx) & SCTLR_BR; 8235 } 8236 } 8237 8238 static inline bool m_is_ppb_region(CPUARMState *env, uint32_t address) 8239 { 8240 /* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */ 8241 return arm_feature(env, ARM_FEATURE_M) && 8242 extract32(address, 20, 12) == 0xe00; 8243 } 8244 8245 static inline bool m_is_system_region(CPUARMState *env, uint32_t address) 8246 { 8247 /* True if address is in the M profile system region 8248 * 0xe0000000 - 0xffffffff 8249 */ 8250 return arm_feature(env, ARM_FEATURE_M) && extract32(address, 29, 3) == 0x7; 8251 } 8252 8253 static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, 8254 int access_type, ARMMMUIdx mmu_idx, 8255 hwaddr *phys_ptr, int *prot, uint32_t *fsr) 8256 { 8257 ARMCPU *cpu = arm_env_get_cpu(env); 8258 int n; 8259 bool is_user = regime_is_user(env, mmu_idx); 8260 8261 *phys_ptr = address; 8262 *prot = 0; 8263 8264 if (regime_translation_disabled(env, mmu_idx) || 8265 m_is_ppb_region(env, address)) { 8266 /* MPU disabled or M profile PPB access: use default memory map. 8267 * The other case which uses the default memory map in the 8268 * v7M ARM ARM pseudocode is exception vector reads from the vector 8269 * table. In QEMU those accesses are done in arm_v7m_load_vector(), 8270 * which always does a direct read using address_space_ldl(), rather 8271 * than going via this function, so we don't need to check that here. 8272 */ 8273 get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); 8274 } else { /* MPU enabled */ 8275 for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) { 8276 /* region search */ 8277 uint32_t base = env->pmsav7.drbar[n]; 8278 uint32_t rsize = extract32(env->pmsav7.drsr[n], 1, 5); 8279 uint32_t rmask; 8280 bool srdis = false; 8281 8282 if (!(env->pmsav7.drsr[n] & 0x1)) { 8283 continue; 8284 } 8285 8286 if (!rsize) { 8287 qemu_log_mask(LOG_GUEST_ERROR, 8288 "DRSR[%d]: Rsize field cannot be 0\n", n); 8289 continue; 8290 } 8291 rsize++; 8292 rmask = (1ull << rsize) - 1; 8293 8294 if (base & rmask) { 8295 qemu_log_mask(LOG_GUEST_ERROR, 8296 "DRBAR[%d]: 0x%" PRIx32 " misaligned " 8297 "to DRSR region size, mask = 0x%" PRIx32 "\n", 8298 n, base, rmask); 8299 continue; 8300 } 8301 8302 if (address < base || address > base + rmask) { 8303 continue; 8304 } 8305 8306 /* Region matched */ 8307 8308 if (rsize >= 8) { /* no subregions for regions < 256 bytes */ 8309 int i, snd; 8310 uint32_t srdis_mask; 8311 8312 rsize -= 3; /* sub region size (power of 2) */ 8313 snd = ((address - base) >> rsize) & 0x7; 8314 srdis = extract32(env->pmsav7.drsr[n], snd + 8, 1); 8315 8316 srdis_mask = srdis ? 0x3 : 0x0; 8317 for (i = 2; i <= 8 && rsize < TARGET_PAGE_BITS; i *= 2) { 8318 /* This will check in groups of 2, 4 and then 8, whether 8319 * the subregion bits are consistent. rsize is incremented 8320 * back up to give the region size, considering consistent 8321 * adjacent subregions as one region. Stop testing if rsize 8322 * is already big enough for an entire QEMU page. 8323 */ 8324 int snd_rounded = snd & ~(i - 1); 8325 uint32_t srdis_multi = extract32(env->pmsav7.drsr[n], 8326 snd_rounded + 8, i); 8327 if (srdis_mask ^ srdis_multi) { 8328 break; 8329 } 8330 srdis_mask = (srdis_mask << i) | srdis_mask; 8331 rsize++; 8332 } 8333 } 8334 if (rsize < TARGET_PAGE_BITS) { 8335 qemu_log_mask(LOG_UNIMP, 8336 "DRSR[%d]: No support for MPU (sub)region " 8337 "alignment of %" PRIu32 " bits. Minimum is %d\n", 8338 n, rsize, TARGET_PAGE_BITS); 8339 continue; 8340 } 8341 if (srdis) { 8342 continue; 8343 } 8344 break; 8345 } 8346 8347 if (n == -1) { /* no hits */ 8348 if (!pmsav7_use_background_region(cpu, mmu_idx, is_user)) { 8349 /* background fault */ 8350 *fsr = 0; 8351 return true; 8352 } 8353 get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); 8354 } else { /* a MPU hit! */ 8355 uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3); 8356 uint32_t xn = extract32(env->pmsav7.dracr[n], 12, 1); 8357 8358 if (m_is_system_region(env, address)) { 8359 /* System space is always execute never */ 8360 xn = 1; 8361 } 8362 8363 if (is_user) { /* User mode AP bit decoding */ 8364 switch (ap) { 8365 case 0: 8366 case 1: 8367 case 5: 8368 break; /* no access */ 8369 case 3: 8370 *prot |= PAGE_WRITE; 8371 /* fall through */ 8372 case 2: 8373 case 6: 8374 *prot |= PAGE_READ | PAGE_EXEC; 8375 break; 8376 default: 8377 qemu_log_mask(LOG_GUEST_ERROR, 8378 "DRACR[%d]: Bad value for AP bits: 0x%" 8379 PRIx32 "\n", n, ap); 8380 } 8381 } else { /* Priv. mode AP bits decoding */ 8382 switch (ap) { 8383 case 0: 8384 break; /* no access */ 8385 case 1: 8386 case 2: 8387 case 3: 8388 *prot |= PAGE_WRITE; 8389 /* fall through */ 8390 case 5: 8391 case 6: 8392 *prot |= PAGE_READ | PAGE_EXEC; 8393 break; 8394 default: 8395 qemu_log_mask(LOG_GUEST_ERROR, 8396 "DRACR[%d]: Bad value for AP bits: 0x%" 8397 PRIx32 "\n", n, ap); 8398 } 8399 } 8400 8401 /* execute never */ 8402 if (xn) { 8403 *prot &= ~PAGE_EXEC; 8404 } 8405 } 8406 } 8407 8408 *fsr = 0x00d; /* Permission fault */ 8409 return !(*prot & (1 << access_type)); 8410 } 8411 8412 static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, 8413 int access_type, ARMMMUIdx mmu_idx, 8414 hwaddr *phys_ptr, int *prot, uint32_t *fsr) 8415 { 8416 int n; 8417 uint32_t mask; 8418 uint32_t base; 8419 bool is_user = regime_is_user(env, mmu_idx); 8420 8421 *phys_ptr = address; 8422 for (n = 7; n >= 0; n--) { 8423 base = env->cp15.c6_region[n]; 8424 if ((base & 1) == 0) { 8425 continue; 8426 } 8427 mask = 1 << ((base >> 1) & 0x1f); 8428 /* Keep this shift separate from the above to avoid an 8429 (undefined) << 32. */ 8430 mask = (mask << 1) - 1; 8431 if (((base ^ address) & ~mask) == 0) { 8432 break; 8433 } 8434 } 8435 if (n < 0) { 8436 *fsr = 2; 8437 return true; 8438 } 8439 8440 if (access_type == 2) { 8441 mask = env->cp15.pmsav5_insn_ap; 8442 } else { 8443 mask = env->cp15.pmsav5_data_ap; 8444 } 8445 mask = (mask >> (n * 4)) & 0xf; 8446 switch (mask) { 8447 case 0: 8448 *fsr = 1; 8449 return true; 8450 case 1: 8451 if (is_user) { 8452 *fsr = 1; 8453 return true; 8454 } 8455 *prot = PAGE_READ | PAGE_WRITE; 8456 break; 8457 case 2: 8458 *prot = PAGE_READ; 8459 if (!is_user) { 8460 *prot |= PAGE_WRITE; 8461 } 8462 break; 8463 case 3: 8464 *prot = PAGE_READ | PAGE_WRITE; 8465 break; 8466 case 5: 8467 if (is_user) { 8468 *fsr = 1; 8469 return true; 8470 } 8471 *prot = PAGE_READ; 8472 break; 8473 case 6: 8474 *prot = PAGE_READ; 8475 break; 8476 default: 8477 /* Bad permission. */ 8478 *fsr = 1; 8479 return true; 8480 } 8481 *prot |= PAGE_EXEC; 8482 return false; 8483 } 8484 8485 /* get_phys_addr - get the physical address for this virtual address 8486 * 8487 * Find the physical address corresponding to the given virtual address, 8488 * by doing a translation table walk on MMU based systems or using the 8489 * MPU state on MPU based systems. 8490 * 8491 * Returns false if the translation was successful. Otherwise, phys_ptr, attrs, 8492 * prot and page_size may not be filled in, and the populated fsr value provides 8493 * information on why the translation aborted, in the format of a 8494 * DFSR/IFSR fault register, with the following caveats: 8495 * * we honour the short vs long DFSR format differences. 8496 * * the WnR bit is never set (the caller must do this). 8497 * * for PSMAv5 based systems we don't bother to return a full FSR format 8498 * value. 8499 * 8500 * @env: CPUARMState 8501 * @address: virtual address to get physical address for 8502 * @access_type: 0 for read, 1 for write, 2 for execute 8503 * @mmu_idx: MMU index indicating required translation regime 8504 * @phys_ptr: set to the physical address corresponding to the virtual address 8505 * @attrs: set to the memory transaction attributes to use 8506 * @prot: set to the permissions for the page containing phys_ptr 8507 * @page_size: set to the size of the page containing phys_ptr 8508 * @fsr: set to the DFSR/IFSR value on failure 8509 */ 8510 static bool get_phys_addr(CPUARMState *env, target_ulong address, 8511 int access_type, ARMMMUIdx mmu_idx, 8512 hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, 8513 target_ulong *page_size, uint32_t *fsr, 8514 ARMMMUFaultInfo *fi) 8515 { 8516 if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { 8517 /* Call ourselves recursively to do the stage 1 and then stage 2 8518 * translations. 8519 */ 8520 if (arm_feature(env, ARM_FEATURE_EL2)) { 8521 hwaddr ipa; 8522 int s2_prot; 8523 int ret; 8524 8525 ret = get_phys_addr(env, address, access_type, 8526 stage_1_mmu_idx(mmu_idx), &ipa, attrs, 8527 prot, page_size, fsr, fi); 8528 8529 /* If S1 fails or S2 is disabled, return early. */ 8530 if (ret || regime_translation_disabled(env, ARMMMUIdx_S2NS)) { 8531 *phys_ptr = ipa; 8532 return ret; 8533 } 8534 8535 /* S1 is done. Now do S2 translation. */ 8536 ret = get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_S2NS, 8537 phys_ptr, attrs, &s2_prot, 8538 page_size, fsr, fi); 8539 fi->s2addr = ipa; 8540 /* Combine the S1 and S2 perms. */ 8541 *prot &= s2_prot; 8542 return ret; 8543 } else { 8544 /* 8545 * For non-EL2 CPUs a stage1+stage2 translation is just stage 1. 8546 */ 8547 mmu_idx = stage_1_mmu_idx(mmu_idx); 8548 } 8549 } 8550 8551 /* The page table entries may downgrade secure to non-secure, but 8552 * cannot upgrade an non-secure translation regime's attributes 8553 * to secure. 8554 */ 8555 attrs->secure = regime_is_secure(env, mmu_idx); 8556 attrs->user = regime_is_user(env, mmu_idx); 8557 8558 /* Fast Context Switch Extension. This doesn't exist at all in v8. 8559 * In v7 and earlier it affects all stage 1 translations. 8560 */ 8561 if (address < 0x02000000 && mmu_idx != ARMMMUIdx_S2NS 8562 && !arm_feature(env, ARM_FEATURE_V8)) { 8563 if (regime_el(env, mmu_idx) == 3) { 8564 address += env->cp15.fcseidr_s; 8565 } else { 8566 address += env->cp15.fcseidr_ns; 8567 } 8568 } 8569 8570 /* pmsav7 has special handling for when MPU is disabled so call it before 8571 * the common MMU/MPU disabled check below. 8572 */ 8573 if (arm_feature(env, ARM_FEATURE_PMSA) && 8574 arm_feature(env, ARM_FEATURE_V7)) { 8575 bool ret; 8576 *page_size = TARGET_PAGE_SIZE; 8577 ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx, 8578 phys_ptr, prot, fsr); 8579 qemu_log_mask(CPU_LOG_MMU, "PMSAv7 MPU lookup for %s at 0x%08" PRIx32 8580 " mmu_idx %u -> %s (prot %c%c%c)\n", 8581 access_type == MMU_DATA_LOAD ? "reading" : 8582 (access_type == MMU_DATA_STORE ? "writing" : "execute"), 8583 (uint32_t)address, mmu_idx, 8584 ret ? "Miss" : "Hit", 8585 *prot & PAGE_READ ? 'r' : '-', 8586 *prot & PAGE_WRITE ? 'w' : '-', 8587 *prot & PAGE_EXEC ? 'x' : '-'); 8588 8589 return ret; 8590 } 8591 8592 if (regime_translation_disabled(env, mmu_idx)) { 8593 /* MMU/MPU disabled. */ 8594 *phys_ptr = address; 8595 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 8596 *page_size = TARGET_PAGE_SIZE; 8597 return 0; 8598 } 8599 8600 if (arm_feature(env, ARM_FEATURE_PMSA)) { 8601 /* Pre-v7 MPU */ 8602 *page_size = TARGET_PAGE_SIZE; 8603 return get_phys_addr_pmsav5(env, address, access_type, mmu_idx, 8604 phys_ptr, prot, fsr); 8605 } 8606 8607 if (regime_using_lpae_format(env, mmu_idx)) { 8608 return get_phys_addr_lpae(env, address, access_type, mmu_idx, phys_ptr, 8609 attrs, prot, page_size, fsr, fi); 8610 } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { 8611 return get_phys_addr_v6(env, address, access_type, mmu_idx, phys_ptr, 8612 attrs, prot, page_size, fsr, fi); 8613 } else { 8614 return get_phys_addr_v5(env, address, access_type, mmu_idx, phys_ptr, 8615 prot, page_size, fsr, fi); 8616 } 8617 } 8618 8619 /* Walk the page table and (if the mapping exists) add the page 8620 * to the TLB. Return false on success, or true on failure. Populate 8621 * fsr with ARM DFSR/IFSR fault register format value on failure. 8622 */ 8623 bool arm_tlb_fill(CPUState *cs, vaddr address, 8624 int access_type, int mmu_idx, uint32_t *fsr, 8625 ARMMMUFaultInfo *fi) 8626 { 8627 ARMCPU *cpu = ARM_CPU(cs); 8628 CPUARMState *env = &cpu->env; 8629 hwaddr phys_addr; 8630 target_ulong page_size; 8631 int prot; 8632 int ret; 8633 MemTxAttrs attrs = {}; 8634 8635 ret = get_phys_addr(env, address, access_type, 8636 core_to_arm_mmu_idx(env, mmu_idx), &phys_addr, 8637 &attrs, &prot, &page_size, fsr, fi); 8638 if (!ret) { 8639 /* Map a single [sub]page. */ 8640 phys_addr &= TARGET_PAGE_MASK; 8641 address &= TARGET_PAGE_MASK; 8642 tlb_set_page_with_attrs(cs, address, phys_addr, attrs, 8643 prot, mmu_idx, page_size); 8644 return 0; 8645 } 8646 8647 return ret; 8648 } 8649 8650 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, 8651 MemTxAttrs *attrs) 8652 { 8653 ARMCPU *cpu = ARM_CPU(cs); 8654 CPUARMState *env = &cpu->env; 8655 hwaddr phys_addr; 8656 target_ulong page_size; 8657 int prot; 8658 bool ret; 8659 uint32_t fsr; 8660 ARMMMUFaultInfo fi = {}; 8661 ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false)); 8662 8663 *attrs = (MemTxAttrs) {}; 8664 8665 ret = get_phys_addr(env, addr, 0, mmu_idx, &phys_addr, 8666 attrs, &prot, &page_size, &fsr, &fi); 8667 8668 if (ret) { 8669 return -1; 8670 } 8671 return phys_addr; 8672 } 8673 8674 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) 8675 { 8676 uint32_t mask; 8677 unsigned el = arm_current_el(env); 8678 8679 /* First handle registers which unprivileged can read */ 8680 8681 switch (reg) { 8682 case 0 ... 7: /* xPSR sub-fields */ 8683 mask = 0; 8684 if ((reg & 1) && el) { 8685 mask |= 0x000001ff; /* IPSR (unpriv. reads as zero) */ 8686 } 8687 if (!(reg & 4)) { 8688 mask |= 0xf8000000; /* APSR */ 8689 } 8690 /* EPSR reads as zero */ 8691 return xpsr_read(env) & mask; 8692 break; 8693 case 20: /* CONTROL */ 8694 return env->v7m.control; 8695 } 8696 8697 if (el == 0) { 8698 return 0; /* unprivileged reads others as zero */ 8699 } 8700 8701 switch (reg) { 8702 case 8: /* MSP */ 8703 return (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) ? 8704 env->v7m.other_sp : env->regs[13]; 8705 case 9: /* PSP */ 8706 return (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) ? 8707 env->regs[13] : env->v7m.other_sp; 8708 case 16: /* PRIMASK */ 8709 return (env->daif & PSTATE_I) != 0; 8710 case 17: /* BASEPRI */ 8711 case 18: /* BASEPRI_MAX */ 8712 return env->v7m.basepri; 8713 case 19: /* FAULTMASK */ 8714 return (env->daif & PSTATE_F) != 0; 8715 default: 8716 qemu_log_mask(LOG_GUEST_ERROR, "Attempt to read unknown special" 8717 " register %d\n", reg); 8718 return 0; 8719 } 8720 } 8721 8722 void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) 8723 { 8724 /* We're passed bits [11..0] of the instruction; extract 8725 * SYSm and the mask bits. 8726 * Invalid combinations of SYSm and mask are UNPREDICTABLE; 8727 * we choose to treat them as if the mask bits were valid. 8728 * NB that the pseudocode 'mask' variable is bits [11..10], 8729 * whereas ours is [11..8]. 8730 */ 8731 uint32_t mask = extract32(maskreg, 8, 4); 8732 uint32_t reg = extract32(maskreg, 0, 8); 8733 8734 if (arm_current_el(env) == 0 && reg > 7) { 8735 /* only xPSR sub-fields may be written by unprivileged */ 8736 return; 8737 } 8738 8739 switch (reg) { 8740 case 0 ... 7: /* xPSR sub-fields */ 8741 /* only APSR is actually writable */ 8742 if (!(reg & 4)) { 8743 uint32_t apsrmask = 0; 8744 8745 if (mask & 8) { 8746 apsrmask |= 0xf8000000; /* APSR NZCVQ */ 8747 } 8748 if ((mask & 4) && arm_feature(env, ARM_FEATURE_THUMB_DSP)) { 8749 apsrmask |= 0x000f0000; /* APSR GE[3:0] */ 8750 } 8751 xpsr_write(env, val, apsrmask); 8752 } 8753 break; 8754 case 8: /* MSP */ 8755 if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) { 8756 env->v7m.other_sp = val; 8757 } else { 8758 env->regs[13] = val; 8759 } 8760 break; 8761 case 9: /* PSP */ 8762 if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) { 8763 env->regs[13] = val; 8764 } else { 8765 env->v7m.other_sp = val; 8766 } 8767 break; 8768 case 16: /* PRIMASK */ 8769 if (val & 1) { 8770 env->daif |= PSTATE_I; 8771 } else { 8772 env->daif &= ~PSTATE_I; 8773 } 8774 break; 8775 case 17: /* BASEPRI */ 8776 env->v7m.basepri = val & 0xff; 8777 break; 8778 case 18: /* BASEPRI_MAX */ 8779 val &= 0xff; 8780 if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0)) 8781 env->v7m.basepri = val; 8782 break; 8783 case 19: /* FAULTMASK */ 8784 if (val & 1) { 8785 env->daif |= PSTATE_F; 8786 } else { 8787 env->daif &= ~PSTATE_F; 8788 } 8789 break; 8790 case 20: /* CONTROL */ 8791 /* Writing to the SPSEL bit only has an effect if we are in 8792 * thread mode; other bits can be updated by any privileged code. 8793 * switch_v7m_sp() deals with updating the SPSEL bit in 8794 * env->v7m.control, so we only need update the others. 8795 */ 8796 if (env->v7m.exception == 0) { 8797 switch_v7m_sp(env, (val & R_V7M_CONTROL_SPSEL_MASK) != 0); 8798 } 8799 env->v7m.control &= ~R_V7M_CONTROL_NPRIV_MASK; 8800 env->v7m.control |= val & R_V7M_CONTROL_NPRIV_MASK; 8801 break; 8802 default: 8803 qemu_log_mask(LOG_GUEST_ERROR, "Attempt to write unknown special" 8804 " register %d\n", reg); 8805 return; 8806 } 8807 } 8808 8809 #endif 8810 8811 void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in) 8812 { 8813 /* Implement DC ZVA, which zeroes a fixed-length block of memory. 8814 * Note that we do not implement the (architecturally mandated) 8815 * alignment fault for attempts to use this on Device memory 8816 * (which matches the usual QEMU behaviour of not implementing either 8817 * alignment faults or any memory attribute handling). 8818 */ 8819 8820 ARMCPU *cpu = arm_env_get_cpu(env); 8821 uint64_t blocklen = 4 << cpu->dcz_blocksize; 8822 uint64_t vaddr = vaddr_in & ~(blocklen - 1); 8823 8824 #ifndef CONFIG_USER_ONLY 8825 { 8826 /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than 8827 * the block size so we might have to do more than one TLB lookup. 8828 * We know that in fact for any v8 CPU the page size is at least 4K 8829 * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only 8830 * 1K as an artefact of legacy v5 subpage support being present in the 8831 * same QEMU executable. 8832 */ 8833 int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE); 8834 void *hostaddr[maxidx]; 8835 int try, i; 8836 unsigned mmu_idx = cpu_mmu_index(env, false); 8837 TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx); 8838 8839 for (try = 0; try < 2; try++) { 8840 8841 for (i = 0; i < maxidx; i++) { 8842 hostaddr[i] = tlb_vaddr_to_host(env, 8843 vaddr + TARGET_PAGE_SIZE * i, 8844 1, mmu_idx); 8845 if (!hostaddr[i]) { 8846 break; 8847 } 8848 } 8849 if (i == maxidx) { 8850 /* If it's all in the TLB it's fair game for just writing to; 8851 * we know we don't need to update dirty status, etc. 8852 */ 8853 for (i = 0; i < maxidx - 1; i++) { 8854 memset(hostaddr[i], 0, TARGET_PAGE_SIZE); 8855 } 8856 memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE)); 8857 return; 8858 } 8859 /* OK, try a store and see if we can populate the tlb. This 8860 * might cause an exception if the memory isn't writable, 8861 * in which case we will longjmp out of here. We must for 8862 * this purpose use the actual register value passed to us 8863 * so that we get the fault address right. 8864 */ 8865 helper_ret_stb_mmu(env, vaddr_in, 0, oi, GETPC()); 8866 /* Now we can populate the other TLB entries, if any */ 8867 for (i = 0; i < maxidx; i++) { 8868 uint64_t va = vaddr + TARGET_PAGE_SIZE * i; 8869 if (va != (vaddr_in & TARGET_PAGE_MASK)) { 8870 helper_ret_stb_mmu(env, va, 0, oi, GETPC()); 8871 } 8872 } 8873 } 8874 8875 /* Slow path (probably attempt to do this to an I/O device or 8876 * similar, or clearing of a block of code we have translations 8877 * cached for). Just do a series of byte writes as the architecture 8878 * demands. It's not worth trying to use a cpu_physical_memory_map(), 8879 * memset(), unmap() sequence here because: 8880 * + we'd need to account for the blocksize being larger than a page 8881 * + the direct-RAM access case is almost always going to be dealt 8882 * with in the fastpath code above, so there's no speed benefit 8883 * + we would have to deal with the map returning NULL because the 8884 * bounce buffer was in use 8885 */ 8886 for (i = 0; i < blocklen; i++) { 8887 helper_ret_stb_mmu(env, vaddr + i, 0, oi, GETPC()); 8888 } 8889 } 8890 #else 8891 memset(g2h(vaddr), 0, blocklen); 8892 #endif 8893 } 8894 8895 /* Note that signed overflow is undefined in C. The following routines are 8896 careful to use unsigned types where modulo arithmetic is required. 8897 Failure to do so _will_ break on newer gcc. */ 8898 8899 /* Signed saturating arithmetic. */ 8900 8901 /* Perform 16-bit signed saturating addition. */ 8902 static inline uint16_t add16_sat(uint16_t a, uint16_t b) 8903 { 8904 uint16_t res; 8905 8906 res = a + b; 8907 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) { 8908 if (a & 0x8000) 8909 res = 0x8000; 8910 else 8911 res = 0x7fff; 8912 } 8913 return res; 8914 } 8915 8916 /* Perform 8-bit signed saturating addition. */ 8917 static inline uint8_t add8_sat(uint8_t a, uint8_t b) 8918 { 8919 uint8_t res; 8920 8921 res = a + b; 8922 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) { 8923 if (a & 0x80) 8924 res = 0x80; 8925 else 8926 res = 0x7f; 8927 } 8928 return res; 8929 } 8930 8931 /* Perform 16-bit signed saturating subtraction. */ 8932 static inline uint16_t sub16_sat(uint16_t a, uint16_t b) 8933 { 8934 uint16_t res; 8935 8936 res = a - b; 8937 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) { 8938 if (a & 0x8000) 8939 res = 0x8000; 8940 else 8941 res = 0x7fff; 8942 } 8943 return res; 8944 } 8945 8946 /* Perform 8-bit signed saturating subtraction. */ 8947 static inline uint8_t sub8_sat(uint8_t a, uint8_t b) 8948 { 8949 uint8_t res; 8950 8951 res = a - b; 8952 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) { 8953 if (a & 0x80) 8954 res = 0x80; 8955 else 8956 res = 0x7f; 8957 } 8958 return res; 8959 } 8960 8961 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16); 8962 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16); 8963 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8); 8964 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8); 8965 #define PFX q 8966 8967 #include "op_addsub.h" 8968 8969 /* Unsigned saturating arithmetic. */ 8970 static inline uint16_t add16_usat(uint16_t a, uint16_t b) 8971 { 8972 uint16_t res; 8973 res = a + b; 8974 if (res < a) 8975 res = 0xffff; 8976 return res; 8977 } 8978 8979 static inline uint16_t sub16_usat(uint16_t a, uint16_t b) 8980 { 8981 if (a > b) 8982 return a - b; 8983 else 8984 return 0; 8985 } 8986 8987 static inline uint8_t add8_usat(uint8_t a, uint8_t b) 8988 { 8989 uint8_t res; 8990 res = a + b; 8991 if (res < a) 8992 res = 0xff; 8993 return res; 8994 } 8995 8996 static inline uint8_t sub8_usat(uint8_t a, uint8_t b) 8997 { 8998 if (a > b) 8999 return a - b; 9000 else 9001 return 0; 9002 } 9003 9004 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16); 9005 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16); 9006 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8); 9007 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8); 9008 #define PFX uq 9009 9010 #include "op_addsub.h" 9011 9012 /* Signed modulo arithmetic. */ 9013 #define SARITH16(a, b, n, op) do { \ 9014 int32_t sum; \ 9015 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \ 9016 RESULT(sum, n, 16); \ 9017 if (sum >= 0) \ 9018 ge |= 3 << (n * 2); \ 9019 } while(0) 9020 9021 #define SARITH8(a, b, n, op) do { \ 9022 int32_t sum; \ 9023 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \ 9024 RESULT(sum, n, 8); \ 9025 if (sum >= 0) \ 9026 ge |= 1 << n; \ 9027 } while(0) 9028 9029 9030 #define ADD16(a, b, n) SARITH16(a, b, n, +) 9031 #define SUB16(a, b, n) SARITH16(a, b, n, -) 9032 #define ADD8(a, b, n) SARITH8(a, b, n, +) 9033 #define SUB8(a, b, n) SARITH8(a, b, n, -) 9034 #define PFX s 9035 #define ARITH_GE 9036 9037 #include "op_addsub.h" 9038 9039 /* Unsigned modulo arithmetic. */ 9040 #define ADD16(a, b, n) do { \ 9041 uint32_t sum; \ 9042 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \ 9043 RESULT(sum, n, 16); \ 9044 if ((sum >> 16) == 1) \ 9045 ge |= 3 << (n * 2); \ 9046 } while(0) 9047 9048 #define ADD8(a, b, n) do { \ 9049 uint32_t sum; \ 9050 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \ 9051 RESULT(sum, n, 8); \ 9052 if ((sum >> 8) == 1) \ 9053 ge |= 1 << n; \ 9054 } while(0) 9055 9056 #define SUB16(a, b, n) do { \ 9057 uint32_t sum; \ 9058 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \ 9059 RESULT(sum, n, 16); \ 9060 if ((sum >> 16) == 0) \ 9061 ge |= 3 << (n * 2); \ 9062 } while(0) 9063 9064 #define SUB8(a, b, n) do { \ 9065 uint32_t sum; \ 9066 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \ 9067 RESULT(sum, n, 8); \ 9068 if ((sum >> 8) == 0) \ 9069 ge |= 1 << n; \ 9070 } while(0) 9071 9072 #define PFX u 9073 #define ARITH_GE 9074 9075 #include "op_addsub.h" 9076 9077 /* Halved signed arithmetic. */ 9078 #define ADD16(a, b, n) \ 9079 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16) 9080 #define SUB16(a, b, n) \ 9081 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16) 9082 #define ADD8(a, b, n) \ 9083 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8) 9084 #define SUB8(a, b, n) \ 9085 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8) 9086 #define PFX sh 9087 9088 #include "op_addsub.h" 9089 9090 /* Halved unsigned arithmetic. */ 9091 #define ADD16(a, b, n) \ 9092 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16) 9093 #define SUB16(a, b, n) \ 9094 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16) 9095 #define ADD8(a, b, n) \ 9096 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8) 9097 #define SUB8(a, b, n) \ 9098 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8) 9099 #define PFX uh 9100 9101 #include "op_addsub.h" 9102 9103 static inline uint8_t do_usad(uint8_t a, uint8_t b) 9104 { 9105 if (a > b) 9106 return a - b; 9107 else 9108 return b - a; 9109 } 9110 9111 /* Unsigned sum of absolute byte differences. */ 9112 uint32_t HELPER(usad8)(uint32_t a, uint32_t b) 9113 { 9114 uint32_t sum; 9115 sum = do_usad(a, b); 9116 sum += do_usad(a >> 8, b >> 8); 9117 sum += do_usad(a >> 16, b >>16); 9118 sum += do_usad(a >> 24, b >> 24); 9119 return sum; 9120 } 9121 9122 /* For ARMv6 SEL instruction. */ 9123 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b) 9124 { 9125 uint32_t mask; 9126 9127 mask = 0; 9128 if (flags & 1) 9129 mask |= 0xff; 9130 if (flags & 2) 9131 mask |= 0xff00; 9132 if (flags & 4) 9133 mask |= 0xff0000; 9134 if (flags & 8) 9135 mask |= 0xff000000; 9136 return (a & mask) | (b & ~mask); 9137 } 9138 9139 /* VFP support. We follow the convention used for VFP instructions: 9140 Single precision routines have a "s" suffix, double precision a 9141 "d" suffix. */ 9142 9143 /* Convert host exception flags to vfp form. */ 9144 static inline int vfp_exceptbits_from_host(int host_bits) 9145 { 9146 int target_bits = 0; 9147 9148 if (host_bits & float_flag_invalid) 9149 target_bits |= 1; 9150 if (host_bits & float_flag_divbyzero) 9151 target_bits |= 2; 9152 if (host_bits & float_flag_overflow) 9153 target_bits |= 4; 9154 if (host_bits & (float_flag_underflow | float_flag_output_denormal)) 9155 target_bits |= 8; 9156 if (host_bits & float_flag_inexact) 9157 target_bits |= 0x10; 9158 if (host_bits & float_flag_input_denormal) 9159 target_bits |= 0x80; 9160 return target_bits; 9161 } 9162 9163 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env) 9164 { 9165 int i; 9166 uint32_t fpscr; 9167 9168 fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff) 9169 | (env->vfp.vec_len << 16) 9170 | (env->vfp.vec_stride << 20); 9171 i = get_float_exception_flags(&env->vfp.fp_status); 9172 i |= get_float_exception_flags(&env->vfp.standard_fp_status); 9173 fpscr |= vfp_exceptbits_from_host(i); 9174 return fpscr; 9175 } 9176 9177 uint32_t vfp_get_fpscr(CPUARMState *env) 9178 { 9179 return HELPER(vfp_get_fpscr)(env); 9180 } 9181 9182 /* Convert vfp exception flags to target form. */ 9183 static inline int vfp_exceptbits_to_host(int target_bits) 9184 { 9185 int host_bits = 0; 9186 9187 if (target_bits & 1) 9188 host_bits |= float_flag_invalid; 9189 if (target_bits & 2) 9190 host_bits |= float_flag_divbyzero; 9191 if (target_bits & 4) 9192 host_bits |= float_flag_overflow; 9193 if (target_bits & 8) 9194 host_bits |= float_flag_underflow; 9195 if (target_bits & 0x10) 9196 host_bits |= float_flag_inexact; 9197 if (target_bits & 0x80) 9198 host_bits |= float_flag_input_denormal; 9199 return host_bits; 9200 } 9201 9202 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) 9203 { 9204 int i; 9205 uint32_t changed; 9206 9207 changed = env->vfp.xregs[ARM_VFP_FPSCR]; 9208 env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff); 9209 env->vfp.vec_len = (val >> 16) & 7; 9210 env->vfp.vec_stride = (val >> 20) & 3; 9211 9212 changed ^= val; 9213 if (changed & (3 << 22)) { 9214 i = (val >> 22) & 3; 9215 switch (i) { 9216 case FPROUNDING_TIEEVEN: 9217 i = float_round_nearest_even; 9218 break; 9219 case FPROUNDING_POSINF: 9220 i = float_round_up; 9221 break; 9222 case FPROUNDING_NEGINF: 9223 i = float_round_down; 9224 break; 9225 case FPROUNDING_ZERO: 9226 i = float_round_to_zero; 9227 break; 9228 } 9229 set_float_rounding_mode(i, &env->vfp.fp_status); 9230 } 9231 if (changed & (1 << 24)) { 9232 set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status); 9233 set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status); 9234 } 9235 if (changed & (1 << 25)) 9236 set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status); 9237 9238 i = vfp_exceptbits_to_host(val); 9239 set_float_exception_flags(i, &env->vfp.fp_status); 9240 set_float_exception_flags(0, &env->vfp.standard_fp_status); 9241 } 9242 9243 void vfp_set_fpscr(CPUARMState *env, uint32_t val) 9244 { 9245 HELPER(vfp_set_fpscr)(env, val); 9246 } 9247 9248 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p)) 9249 9250 #define VFP_BINOP(name) \ 9251 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \ 9252 { \ 9253 float_status *fpst = fpstp; \ 9254 return float32_ ## name(a, b, fpst); \ 9255 } \ 9256 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \ 9257 { \ 9258 float_status *fpst = fpstp; \ 9259 return float64_ ## name(a, b, fpst); \ 9260 } 9261 VFP_BINOP(add) 9262 VFP_BINOP(sub) 9263 VFP_BINOP(mul) 9264 VFP_BINOP(div) 9265 VFP_BINOP(min) 9266 VFP_BINOP(max) 9267 VFP_BINOP(minnum) 9268 VFP_BINOP(maxnum) 9269 #undef VFP_BINOP 9270 9271 float32 VFP_HELPER(neg, s)(float32 a) 9272 { 9273 return float32_chs(a); 9274 } 9275 9276 float64 VFP_HELPER(neg, d)(float64 a) 9277 { 9278 return float64_chs(a); 9279 } 9280 9281 float32 VFP_HELPER(abs, s)(float32 a) 9282 { 9283 return float32_abs(a); 9284 } 9285 9286 float64 VFP_HELPER(abs, d)(float64 a) 9287 { 9288 return float64_abs(a); 9289 } 9290 9291 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env) 9292 { 9293 return float32_sqrt(a, &env->vfp.fp_status); 9294 } 9295 9296 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env) 9297 { 9298 return float64_sqrt(a, &env->vfp.fp_status); 9299 } 9300 9301 /* XXX: check quiet/signaling case */ 9302 #define DO_VFP_cmp(p, type) \ 9303 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \ 9304 { \ 9305 uint32_t flags; \ 9306 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \ 9307 case 0: flags = 0x6; break; \ 9308 case -1: flags = 0x8; break; \ 9309 case 1: flags = 0x2; break; \ 9310 default: case 2: flags = 0x3; break; \ 9311 } \ 9312 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \ 9313 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \ 9314 } \ 9315 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \ 9316 { \ 9317 uint32_t flags; \ 9318 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \ 9319 case 0: flags = 0x6; break; \ 9320 case -1: flags = 0x8; break; \ 9321 case 1: flags = 0x2; break; \ 9322 default: case 2: flags = 0x3; break; \ 9323 } \ 9324 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \ 9325 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \ 9326 } 9327 DO_VFP_cmp(s, float32) 9328 DO_VFP_cmp(d, float64) 9329 #undef DO_VFP_cmp 9330 9331 /* Integer to float and float to integer conversions */ 9332 9333 #define CONV_ITOF(name, fsz, sign) \ 9334 float##fsz HELPER(name)(uint32_t x, void *fpstp) \ 9335 { \ 9336 float_status *fpst = fpstp; \ 9337 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \ 9338 } 9339 9340 #define CONV_FTOI(name, fsz, sign, round) \ 9341 uint32_t HELPER(name)(float##fsz x, void *fpstp) \ 9342 { \ 9343 float_status *fpst = fpstp; \ 9344 if (float##fsz##_is_any_nan(x)) { \ 9345 float_raise(float_flag_invalid, fpst); \ 9346 return 0; \ 9347 } \ 9348 return float##fsz##_to_##sign##int32##round(x, fpst); \ 9349 } 9350 9351 #define FLOAT_CONVS(name, p, fsz, sign) \ 9352 CONV_ITOF(vfp_##name##to##p, fsz, sign) \ 9353 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \ 9354 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero) 9355 9356 FLOAT_CONVS(si, s, 32, ) 9357 FLOAT_CONVS(si, d, 64, ) 9358 FLOAT_CONVS(ui, s, 32, u) 9359 FLOAT_CONVS(ui, d, 64, u) 9360 9361 #undef CONV_ITOF 9362 #undef CONV_FTOI 9363 #undef FLOAT_CONVS 9364 9365 /* floating point conversion */ 9366 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env) 9367 { 9368 float64 r = float32_to_float64(x, &env->vfp.fp_status); 9369 /* ARM requires that S<->D conversion of any kind of NaN generates 9370 * a quiet NaN by forcing the most significant frac bit to 1. 9371 */ 9372 return float64_maybe_silence_nan(r, &env->vfp.fp_status); 9373 } 9374 9375 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env) 9376 { 9377 float32 r = float64_to_float32(x, &env->vfp.fp_status); 9378 /* ARM requires that S<->D conversion of any kind of NaN generates 9379 * a quiet NaN by forcing the most significant frac bit to 1. 9380 */ 9381 return float32_maybe_silence_nan(r, &env->vfp.fp_status); 9382 } 9383 9384 /* VFP3 fixed point conversion. */ 9385 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ 9386 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \ 9387 void *fpstp) \ 9388 { \ 9389 float_status *fpst = fpstp; \ 9390 float##fsz tmp; \ 9391 tmp = itype##_to_##float##fsz(x, fpst); \ 9392 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \ 9393 } 9394 9395 /* Notice that we want only input-denormal exception flags from the 9396 * scalbn operation: the other possible flags (overflow+inexact if 9397 * we overflow to infinity, output-denormal) aren't correct for the 9398 * complete scale-and-convert operation. 9399 */ 9400 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \ 9401 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \ 9402 uint32_t shift, \ 9403 void *fpstp) \ 9404 { \ 9405 float_status *fpst = fpstp; \ 9406 int old_exc_flags = get_float_exception_flags(fpst); \ 9407 float##fsz tmp; \ 9408 if (float##fsz##_is_any_nan(x)) { \ 9409 float_raise(float_flag_invalid, fpst); \ 9410 return 0; \ 9411 } \ 9412 tmp = float##fsz##_scalbn(x, shift, fpst); \ 9413 old_exc_flags |= get_float_exception_flags(fpst) \ 9414 & float_flag_input_denormal; \ 9415 set_float_exception_flags(old_exc_flags, fpst); \ 9416 return float##fsz##_to_##itype##round(tmp, fpst); \ 9417 } 9418 9419 #define VFP_CONV_FIX(name, p, fsz, isz, itype) \ 9420 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ 9421 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \ 9422 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, ) 9423 9424 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \ 9425 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ 9426 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, ) 9427 9428 VFP_CONV_FIX(sh, d, 64, 64, int16) 9429 VFP_CONV_FIX(sl, d, 64, 64, int32) 9430 VFP_CONV_FIX_A64(sq, d, 64, 64, int64) 9431 VFP_CONV_FIX(uh, d, 64, 64, uint16) 9432 VFP_CONV_FIX(ul, d, 64, 64, uint32) 9433 VFP_CONV_FIX_A64(uq, d, 64, 64, uint64) 9434 VFP_CONV_FIX(sh, s, 32, 32, int16) 9435 VFP_CONV_FIX(sl, s, 32, 32, int32) 9436 VFP_CONV_FIX_A64(sq, s, 32, 64, int64) 9437 VFP_CONV_FIX(uh, s, 32, 32, uint16) 9438 VFP_CONV_FIX(ul, s, 32, 32, uint32) 9439 VFP_CONV_FIX_A64(uq, s, 32, 64, uint64) 9440 #undef VFP_CONV_FIX 9441 #undef VFP_CONV_FIX_FLOAT 9442 #undef VFP_CONV_FLOAT_FIX_ROUND 9443 9444 /* Set the current fp rounding mode and return the old one. 9445 * The argument is a softfloat float_round_ value. 9446 */ 9447 uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env) 9448 { 9449 float_status *fp_status = &env->vfp.fp_status; 9450 9451 uint32_t prev_rmode = get_float_rounding_mode(fp_status); 9452 set_float_rounding_mode(rmode, fp_status); 9453 9454 return prev_rmode; 9455 } 9456 9457 /* Set the current fp rounding mode in the standard fp status and return 9458 * the old one. This is for NEON instructions that need to change the 9459 * rounding mode but wish to use the standard FPSCR values for everything 9460 * else. Always set the rounding mode back to the correct value after 9461 * modifying it. 9462 * The argument is a softfloat float_round_ value. 9463 */ 9464 uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env) 9465 { 9466 float_status *fp_status = &env->vfp.standard_fp_status; 9467 9468 uint32_t prev_rmode = get_float_rounding_mode(fp_status); 9469 set_float_rounding_mode(rmode, fp_status); 9470 9471 return prev_rmode; 9472 } 9473 9474 /* Half precision conversions. */ 9475 static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s) 9476 { 9477 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; 9478 float32 r = float16_to_float32(make_float16(a), ieee, s); 9479 if (ieee) { 9480 return float32_maybe_silence_nan(r, s); 9481 } 9482 return r; 9483 } 9484 9485 static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s) 9486 { 9487 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; 9488 float16 r = float32_to_float16(a, ieee, s); 9489 if (ieee) { 9490 r = float16_maybe_silence_nan(r, s); 9491 } 9492 return float16_val(r); 9493 } 9494 9495 float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env) 9496 { 9497 return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status); 9498 } 9499 9500 uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env) 9501 { 9502 return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status); 9503 } 9504 9505 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env) 9506 { 9507 return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status); 9508 } 9509 9510 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env) 9511 { 9512 return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status); 9513 } 9514 9515 float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env) 9516 { 9517 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; 9518 float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status); 9519 if (ieee) { 9520 return float64_maybe_silence_nan(r, &env->vfp.fp_status); 9521 } 9522 return r; 9523 } 9524 9525 uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env) 9526 { 9527 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; 9528 float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status); 9529 if (ieee) { 9530 r = float16_maybe_silence_nan(r, &env->vfp.fp_status); 9531 } 9532 return float16_val(r); 9533 } 9534 9535 #define float32_two make_float32(0x40000000) 9536 #define float32_three make_float32(0x40400000) 9537 #define float32_one_point_five make_float32(0x3fc00000) 9538 9539 float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env) 9540 { 9541 float_status *s = &env->vfp.standard_fp_status; 9542 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) || 9543 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) { 9544 if (!(float32_is_zero(a) || float32_is_zero(b))) { 9545 float_raise(float_flag_input_denormal, s); 9546 } 9547 return float32_two; 9548 } 9549 return float32_sub(float32_two, float32_mul(a, b, s), s); 9550 } 9551 9552 float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env) 9553 { 9554 float_status *s = &env->vfp.standard_fp_status; 9555 float32 product; 9556 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) || 9557 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) { 9558 if (!(float32_is_zero(a) || float32_is_zero(b))) { 9559 float_raise(float_flag_input_denormal, s); 9560 } 9561 return float32_one_point_five; 9562 } 9563 product = float32_mul(a, b, s); 9564 return float32_div(float32_sub(float32_three, product, s), float32_two, s); 9565 } 9566 9567 /* NEON helpers. */ 9568 9569 /* Constants 256 and 512 are used in some helpers; we avoid relying on 9570 * int->float conversions at run-time. */ 9571 #define float64_256 make_float64(0x4070000000000000LL) 9572 #define float64_512 make_float64(0x4080000000000000LL) 9573 #define float32_maxnorm make_float32(0x7f7fffff) 9574 #define float64_maxnorm make_float64(0x7fefffffffffffffLL) 9575 9576 /* Reciprocal functions 9577 * 9578 * The algorithm that must be used to calculate the estimate 9579 * is specified by the ARM ARM, see FPRecipEstimate() 9580 */ 9581 9582 static float64 recip_estimate(float64 a, float_status *real_fp_status) 9583 { 9584 /* These calculations mustn't set any fp exception flags, 9585 * so we use a local copy of the fp_status. 9586 */ 9587 float_status dummy_status = *real_fp_status; 9588 float_status *s = &dummy_status; 9589 /* q = (int)(a * 512.0) */ 9590 float64 q = float64_mul(float64_512, a, s); 9591 int64_t q_int = float64_to_int64_round_to_zero(q, s); 9592 9593 /* r = 1.0 / (((double)q + 0.5) / 512.0) */ 9594 q = int64_to_float64(q_int, s); 9595 q = float64_add(q, float64_half, s); 9596 q = float64_div(q, float64_512, s); 9597 q = float64_div(float64_one, q, s); 9598 9599 /* s = (int)(256.0 * r + 0.5) */ 9600 q = float64_mul(q, float64_256, s); 9601 q = float64_add(q, float64_half, s); 9602 q_int = float64_to_int64_round_to_zero(q, s); 9603 9604 /* return (double)s / 256.0 */ 9605 return float64_div(int64_to_float64(q_int, s), float64_256, s); 9606 } 9607 9608 /* Common wrapper to call recip_estimate */ 9609 static float64 call_recip_estimate(float64 num, int off, float_status *fpst) 9610 { 9611 uint64_t val64 = float64_val(num); 9612 uint64_t frac = extract64(val64, 0, 52); 9613 int64_t exp = extract64(val64, 52, 11); 9614 uint64_t sbit; 9615 float64 scaled, estimate; 9616 9617 /* Generate the scaled number for the estimate function */ 9618 if (exp == 0) { 9619 if (extract64(frac, 51, 1) == 0) { 9620 exp = -1; 9621 frac = extract64(frac, 0, 50) << 2; 9622 } else { 9623 frac = extract64(frac, 0, 51) << 1; 9624 } 9625 } 9626 9627 /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */ 9628 scaled = make_float64((0x3feULL << 52) 9629 | extract64(frac, 44, 8) << 44); 9630 9631 estimate = recip_estimate(scaled, fpst); 9632 9633 /* Build new result */ 9634 val64 = float64_val(estimate); 9635 sbit = 0x8000000000000000ULL & val64; 9636 exp = off - exp; 9637 frac = extract64(val64, 0, 52); 9638 9639 if (exp == 0) { 9640 frac = 1ULL << 51 | extract64(frac, 1, 51); 9641 } else if (exp == -1) { 9642 frac = 1ULL << 50 | extract64(frac, 2, 50); 9643 exp = 0; 9644 } 9645 9646 return make_float64(sbit | (exp << 52) | frac); 9647 } 9648 9649 static bool round_to_inf(float_status *fpst, bool sign_bit) 9650 { 9651 switch (fpst->float_rounding_mode) { 9652 case float_round_nearest_even: /* Round to Nearest */ 9653 return true; 9654 case float_round_up: /* Round to +Inf */ 9655 return !sign_bit; 9656 case float_round_down: /* Round to -Inf */ 9657 return sign_bit; 9658 case float_round_to_zero: /* Round to Zero */ 9659 return false; 9660 } 9661 9662 g_assert_not_reached(); 9663 } 9664 9665 float32 HELPER(recpe_f32)(float32 input, void *fpstp) 9666 { 9667 float_status *fpst = fpstp; 9668 float32 f32 = float32_squash_input_denormal(input, fpst); 9669 uint32_t f32_val = float32_val(f32); 9670 uint32_t f32_sbit = 0x80000000ULL & f32_val; 9671 int32_t f32_exp = extract32(f32_val, 23, 8); 9672 uint32_t f32_frac = extract32(f32_val, 0, 23); 9673 float64 f64, r64; 9674 uint64_t r64_val; 9675 int64_t r64_exp; 9676 uint64_t r64_frac; 9677 9678 if (float32_is_any_nan(f32)) { 9679 float32 nan = f32; 9680 if (float32_is_signaling_nan(f32, fpst)) { 9681 float_raise(float_flag_invalid, fpst); 9682 nan = float32_maybe_silence_nan(f32, fpst); 9683 } 9684 if (fpst->default_nan_mode) { 9685 nan = float32_default_nan(fpst); 9686 } 9687 return nan; 9688 } else if (float32_is_infinity(f32)) { 9689 return float32_set_sign(float32_zero, float32_is_neg(f32)); 9690 } else if (float32_is_zero(f32)) { 9691 float_raise(float_flag_divbyzero, fpst); 9692 return float32_set_sign(float32_infinity, float32_is_neg(f32)); 9693 } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) { 9694 /* Abs(value) < 2.0^-128 */ 9695 float_raise(float_flag_overflow | float_flag_inexact, fpst); 9696 if (round_to_inf(fpst, f32_sbit)) { 9697 return float32_set_sign(float32_infinity, float32_is_neg(f32)); 9698 } else { 9699 return float32_set_sign(float32_maxnorm, float32_is_neg(f32)); 9700 } 9701 } else if (f32_exp >= 253 && fpst->flush_to_zero) { 9702 float_raise(float_flag_underflow, fpst); 9703 return float32_set_sign(float32_zero, float32_is_neg(f32)); 9704 } 9705 9706 9707 f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29); 9708 r64 = call_recip_estimate(f64, 253, fpst); 9709 r64_val = float64_val(r64); 9710 r64_exp = extract64(r64_val, 52, 11); 9711 r64_frac = extract64(r64_val, 0, 52); 9712 9713 /* result = sign : result_exp<7:0> : fraction<51:29>; */ 9714 return make_float32(f32_sbit | 9715 (r64_exp & 0xff) << 23 | 9716 extract64(r64_frac, 29, 24)); 9717 } 9718 9719 float64 HELPER(recpe_f64)(float64 input, void *fpstp) 9720 { 9721 float_status *fpst = fpstp; 9722 float64 f64 = float64_squash_input_denormal(input, fpst); 9723 uint64_t f64_val = float64_val(f64); 9724 uint64_t f64_sbit = 0x8000000000000000ULL & f64_val; 9725 int64_t f64_exp = extract64(f64_val, 52, 11); 9726 float64 r64; 9727 uint64_t r64_val; 9728 int64_t r64_exp; 9729 uint64_t r64_frac; 9730 9731 /* Deal with any special cases */ 9732 if (float64_is_any_nan(f64)) { 9733 float64 nan = f64; 9734 if (float64_is_signaling_nan(f64, fpst)) { 9735 float_raise(float_flag_invalid, fpst); 9736 nan = float64_maybe_silence_nan(f64, fpst); 9737 } 9738 if (fpst->default_nan_mode) { 9739 nan = float64_default_nan(fpst); 9740 } 9741 return nan; 9742 } else if (float64_is_infinity(f64)) { 9743 return float64_set_sign(float64_zero, float64_is_neg(f64)); 9744 } else if (float64_is_zero(f64)) { 9745 float_raise(float_flag_divbyzero, fpst); 9746 return float64_set_sign(float64_infinity, float64_is_neg(f64)); 9747 } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) { 9748 /* Abs(value) < 2.0^-1024 */ 9749 float_raise(float_flag_overflow | float_flag_inexact, fpst); 9750 if (round_to_inf(fpst, f64_sbit)) { 9751 return float64_set_sign(float64_infinity, float64_is_neg(f64)); 9752 } else { 9753 return float64_set_sign(float64_maxnorm, float64_is_neg(f64)); 9754 } 9755 } else if (f64_exp >= 2045 && fpst->flush_to_zero) { 9756 float_raise(float_flag_underflow, fpst); 9757 return float64_set_sign(float64_zero, float64_is_neg(f64)); 9758 } 9759 9760 r64 = call_recip_estimate(f64, 2045, fpst); 9761 r64_val = float64_val(r64); 9762 r64_exp = extract64(r64_val, 52, 11); 9763 r64_frac = extract64(r64_val, 0, 52); 9764 9765 /* result = sign : result_exp<10:0> : fraction<51:0> */ 9766 return make_float64(f64_sbit | 9767 ((r64_exp & 0x7ff) << 52) | 9768 r64_frac); 9769 } 9770 9771 /* The algorithm that must be used to calculate the estimate 9772 * is specified by the ARM ARM. 9773 */ 9774 static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status) 9775 { 9776 /* These calculations mustn't set any fp exception flags, 9777 * so we use a local copy of the fp_status. 9778 */ 9779 float_status dummy_status = *real_fp_status; 9780 float_status *s = &dummy_status; 9781 float64 q; 9782 int64_t q_int; 9783 9784 if (float64_lt(a, float64_half, s)) { 9785 /* range 0.25 <= a < 0.5 */ 9786 9787 /* a in units of 1/512 rounded down */ 9788 /* q0 = (int)(a * 512.0); */ 9789 q = float64_mul(float64_512, a, s); 9790 q_int = float64_to_int64_round_to_zero(q, s); 9791 9792 /* reciprocal root r */ 9793 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */ 9794 q = int64_to_float64(q_int, s); 9795 q = float64_add(q, float64_half, s); 9796 q = float64_div(q, float64_512, s); 9797 q = float64_sqrt(q, s); 9798 q = float64_div(float64_one, q, s); 9799 } else { 9800 /* range 0.5 <= a < 1.0 */ 9801 9802 /* a in units of 1/256 rounded down */ 9803 /* q1 = (int)(a * 256.0); */ 9804 q = float64_mul(float64_256, a, s); 9805 int64_t q_int = float64_to_int64_round_to_zero(q, s); 9806 9807 /* reciprocal root r */ 9808 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */ 9809 q = int64_to_float64(q_int, s); 9810 q = float64_add(q, float64_half, s); 9811 q = float64_div(q, float64_256, s); 9812 q = float64_sqrt(q, s); 9813 q = float64_div(float64_one, q, s); 9814 } 9815 /* r in units of 1/256 rounded to nearest */ 9816 /* s = (int)(256.0 * r + 0.5); */ 9817 9818 q = float64_mul(q, float64_256,s ); 9819 q = float64_add(q, float64_half, s); 9820 q_int = float64_to_int64_round_to_zero(q, s); 9821 9822 /* return (double)s / 256.0;*/ 9823 return float64_div(int64_to_float64(q_int, s), float64_256, s); 9824 } 9825 9826 float32 HELPER(rsqrte_f32)(float32 input, void *fpstp) 9827 { 9828 float_status *s = fpstp; 9829 float32 f32 = float32_squash_input_denormal(input, s); 9830 uint32_t val = float32_val(f32); 9831 uint32_t f32_sbit = 0x80000000 & val; 9832 int32_t f32_exp = extract32(val, 23, 8); 9833 uint32_t f32_frac = extract32(val, 0, 23); 9834 uint64_t f64_frac; 9835 uint64_t val64; 9836 int result_exp; 9837 float64 f64; 9838 9839 if (float32_is_any_nan(f32)) { 9840 float32 nan = f32; 9841 if (float32_is_signaling_nan(f32, s)) { 9842 float_raise(float_flag_invalid, s); 9843 nan = float32_maybe_silence_nan(f32, s); 9844 } 9845 if (s->default_nan_mode) { 9846 nan = float32_default_nan(s); 9847 } 9848 return nan; 9849 } else if (float32_is_zero(f32)) { 9850 float_raise(float_flag_divbyzero, s); 9851 return float32_set_sign(float32_infinity, float32_is_neg(f32)); 9852 } else if (float32_is_neg(f32)) { 9853 float_raise(float_flag_invalid, s); 9854 return float32_default_nan(s); 9855 } else if (float32_is_infinity(f32)) { 9856 return float32_zero; 9857 } 9858 9859 /* Scale and normalize to a double-precision value between 0.25 and 1.0, 9860 * preserving the parity of the exponent. */ 9861 9862 f64_frac = ((uint64_t) f32_frac) << 29; 9863 if (f32_exp == 0) { 9864 while (extract64(f64_frac, 51, 1) == 0) { 9865 f64_frac = f64_frac << 1; 9866 f32_exp = f32_exp-1; 9867 } 9868 f64_frac = extract64(f64_frac, 0, 51) << 1; 9869 } 9870 9871 if (extract64(f32_exp, 0, 1) == 0) { 9872 f64 = make_float64(((uint64_t) f32_sbit) << 32 9873 | (0x3feULL << 52) 9874 | f64_frac); 9875 } else { 9876 f64 = make_float64(((uint64_t) f32_sbit) << 32 9877 | (0x3fdULL << 52) 9878 | f64_frac); 9879 } 9880 9881 result_exp = (380 - f32_exp) / 2; 9882 9883 f64 = recip_sqrt_estimate(f64, s); 9884 9885 val64 = float64_val(f64); 9886 9887 val = ((result_exp & 0xff) << 23) 9888 | ((val64 >> 29) & 0x7fffff); 9889 return make_float32(val); 9890 } 9891 9892 float64 HELPER(rsqrte_f64)(float64 input, void *fpstp) 9893 { 9894 float_status *s = fpstp; 9895 float64 f64 = float64_squash_input_denormal(input, s); 9896 uint64_t val = float64_val(f64); 9897 uint64_t f64_sbit = 0x8000000000000000ULL & val; 9898 int64_t f64_exp = extract64(val, 52, 11); 9899 uint64_t f64_frac = extract64(val, 0, 52); 9900 int64_t result_exp; 9901 uint64_t result_frac; 9902 9903 if (float64_is_any_nan(f64)) { 9904 float64 nan = f64; 9905 if (float64_is_signaling_nan(f64, s)) { 9906 float_raise(float_flag_invalid, s); 9907 nan = float64_maybe_silence_nan(f64, s); 9908 } 9909 if (s->default_nan_mode) { 9910 nan = float64_default_nan(s); 9911 } 9912 return nan; 9913 } else if (float64_is_zero(f64)) { 9914 float_raise(float_flag_divbyzero, s); 9915 return float64_set_sign(float64_infinity, float64_is_neg(f64)); 9916 } else if (float64_is_neg(f64)) { 9917 float_raise(float_flag_invalid, s); 9918 return float64_default_nan(s); 9919 } else if (float64_is_infinity(f64)) { 9920 return float64_zero; 9921 } 9922 9923 /* Scale and normalize to a double-precision value between 0.25 and 1.0, 9924 * preserving the parity of the exponent. */ 9925 9926 if (f64_exp == 0) { 9927 while (extract64(f64_frac, 51, 1) == 0) { 9928 f64_frac = f64_frac << 1; 9929 f64_exp = f64_exp - 1; 9930 } 9931 f64_frac = extract64(f64_frac, 0, 51) << 1; 9932 } 9933 9934 if (extract64(f64_exp, 0, 1) == 0) { 9935 f64 = make_float64(f64_sbit 9936 | (0x3feULL << 52) 9937 | f64_frac); 9938 } else { 9939 f64 = make_float64(f64_sbit 9940 | (0x3fdULL << 52) 9941 | f64_frac); 9942 } 9943 9944 result_exp = (3068 - f64_exp) / 2; 9945 9946 f64 = recip_sqrt_estimate(f64, s); 9947 9948 result_frac = extract64(float64_val(f64), 0, 52); 9949 9950 return make_float64(f64_sbit | 9951 ((result_exp & 0x7ff) << 52) | 9952 result_frac); 9953 } 9954 9955 uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp) 9956 { 9957 float_status *s = fpstp; 9958 float64 f64; 9959 9960 if ((a & 0x80000000) == 0) { 9961 return 0xffffffff; 9962 } 9963 9964 f64 = make_float64((0x3feULL << 52) 9965 | ((int64_t)(a & 0x7fffffff) << 21)); 9966 9967 f64 = recip_estimate(f64, s); 9968 9969 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff); 9970 } 9971 9972 uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp) 9973 { 9974 float_status *fpst = fpstp; 9975 float64 f64; 9976 9977 if ((a & 0xc0000000) == 0) { 9978 return 0xffffffff; 9979 } 9980 9981 if (a & 0x80000000) { 9982 f64 = make_float64((0x3feULL << 52) 9983 | ((uint64_t)(a & 0x7fffffff) << 21)); 9984 } else { /* bits 31-30 == '01' */ 9985 f64 = make_float64((0x3fdULL << 52) 9986 | ((uint64_t)(a & 0x3fffffff) << 22)); 9987 } 9988 9989 f64 = recip_sqrt_estimate(f64, fpst); 9990 9991 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff); 9992 } 9993 9994 /* VFPv4 fused multiply-accumulate */ 9995 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp) 9996 { 9997 float_status *fpst = fpstp; 9998 return float32_muladd(a, b, c, 0, fpst); 9999 } 10000 10001 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp) 10002 { 10003 float_status *fpst = fpstp; 10004 return float64_muladd(a, b, c, 0, fpst); 10005 } 10006 10007 /* ARMv8 round to integral */ 10008 float32 HELPER(rints_exact)(float32 x, void *fp_status) 10009 { 10010 return float32_round_to_int(x, fp_status); 10011 } 10012 10013 float64 HELPER(rintd_exact)(float64 x, void *fp_status) 10014 { 10015 return float64_round_to_int(x, fp_status); 10016 } 10017 10018 float32 HELPER(rints)(float32 x, void *fp_status) 10019 { 10020 int old_flags = get_float_exception_flags(fp_status), new_flags; 10021 float32 ret; 10022 10023 ret = float32_round_to_int(x, fp_status); 10024 10025 /* Suppress any inexact exceptions the conversion produced */ 10026 if (!(old_flags & float_flag_inexact)) { 10027 new_flags = get_float_exception_flags(fp_status); 10028 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); 10029 } 10030 10031 return ret; 10032 } 10033 10034 float64 HELPER(rintd)(float64 x, void *fp_status) 10035 { 10036 int old_flags = get_float_exception_flags(fp_status), new_flags; 10037 float64 ret; 10038 10039 ret = float64_round_to_int(x, fp_status); 10040 10041 new_flags = get_float_exception_flags(fp_status); 10042 10043 /* Suppress any inexact exceptions the conversion produced */ 10044 if (!(old_flags & float_flag_inexact)) { 10045 new_flags = get_float_exception_flags(fp_status); 10046 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); 10047 } 10048 10049 return ret; 10050 } 10051 10052 /* Convert ARM rounding mode to softfloat */ 10053 int arm_rmode_to_sf(int rmode) 10054 { 10055 switch (rmode) { 10056 case FPROUNDING_TIEAWAY: 10057 rmode = float_round_ties_away; 10058 break; 10059 case FPROUNDING_ODD: 10060 /* FIXME: add support for TIEAWAY and ODD */ 10061 qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n", 10062 rmode); 10063 case FPROUNDING_TIEEVEN: 10064 default: 10065 rmode = float_round_nearest_even; 10066 break; 10067 case FPROUNDING_POSINF: 10068 rmode = float_round_up; 10069 break; 10070 case FPROUNDING_NEGINF: 10071 rmode = float_round_down; 10072 break; 10073 case FPROUNDING_ZERO: 10074 rmode = float_round_to_zero; 10075 break; 10076 } 10077 return rmode; 10078 } 10079 10080 /* CRC helpers. 10081 * The upper bytes of val (above the number specified by 'bytes') must have 10082 * been zeroed out by the caller. 10083 */ 10084 uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes) 10085 { 10086 uint8_t buf[4]; 10087 10088 stl_le_p(buf, val); 10089 10090 /* zlib crc32 converts the accumulator and output to one's complement. */ 10091 return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff; 10092 } 10093 10094 uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes) 10095 { 10096 uint8_t buf[4]; 10097 10098 stl_le_p(buf, val); 10099 10100 /* Linux crc32c converts the output to one's complement. */ 10101 return crc32c(acc, buf, bytes) ^ 0xffffffff; 10102 } 10103