1a1477da3SAlexander Graf /* 2a1477da3SAlexander Graf * QEMU Hypervisor.framework support for Apple Silicon 3a1477da3SAlexander Graf 4a1477da3SAlexander Graf * Copyright 2020 Alexander Graf <agraf@csgraf.de> 5219c101fSPeter Collingbourne * Copyright 2020 Google LLC 6a1477da3SAlexander Graf * 7a1477da3SAlexander Graf * This work is licensed under the terms of the GNU GPL, version 2 or later. 8a1477da3SAlexander Graf * See the COPYING file in the top-level directory. 9a1477da3SAlexander Graf * 10a1477da3SAlexander Graf */ 11a1477da3SAlexander Graf 12a1477da3SAlexander Graf #include "qemu/osdep.h" 13a1477da3SAlexander Graf #include "qemu/error-report.h" 14a1477da3SAlexander Graf 15a1477da3SAlexander Graf #include "sysemu/runstate.h" 16a1477da3SAlexander Graf #include "sysemu/hvf.h" 17a1477da3SAlexander Graf #include "sysemu/hvf_int.h" 18a1477da3SAlexander Graf #include "sysemu/hw_accel.h" 19585df85eSPeter Maydell #include "hvf_arm.h" 20b5fb359cSPhilippe Mathieu-Daudé #include "cpregs.h" 21a1477da3SAlexander Graf 22a1477da3SAlexander Graf #include <mach/mach_time.h> 23a1477da3SAlexander Graf 24a1477da3SAlexander Graf #include "exec/address-spaces.h" 25a1477da3SAlexander Graf #include "hw/irq.h" 26a1477da3SAlexander Graf #include "qemu/main-loop.h" 27a1477da3SAlexander Graf #include "sysemu/cpus.h" 282c9c0bf9SAlexander Graf #include "arm-powerctl.h" 29a1477da3SAlexander Graf #include "target/arm/cpu.h" 30a1477da3SAlexander Graf #include "target/arm/internals.h" 31e2d8cf9bSPhilippe Mathieu-Daudé #include "target/arm/multiprocessing.h" 32f4f318b4SPhilippe Mathieu-Daudé #include "target/arm/gtimer.h" 33a1477da3SAlexander Graf #include "trace/trace-target_arm_hvf.h" 34a1477da3SAlexander Graf #include "migration/vmstate.h" 35a1477da3SAlexander Graf 36f4152040SFrancesco Cagnin #include "exec/gdbstub.h" 37f4152040SFrancesco Cagnin 38eb2edc42SFrancesco Cagnin #define MDSCR_EL1_SS_SHIFT 0 39eb2edc42SFrancesco Cagnin #define MDSCR_EL1_MDE_SHIFT 15 40eb2edc42SFrancesco Cagnin 41f49986aeSRichard Henderson static const uint16_t dbgbcr_regs[] = { 42eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGBCR0_EL1, 43eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGBCR1_EL1, 44eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGBCR2_EL1, 45eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGBCR3_EL1, 46eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGBCR4_EL1, 47eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGBCR5_EL1, 48eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGBCR6_EL1, 49eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGBCR7_EL1, 50eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGBCR8_EL1, 51eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGBCR9_EL1, 52eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGBCR10_EL1, 53eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGBCR11_EL1, 54eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGBCR12_EL1, 55eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGBCR13_EL1, 56eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGBCR14_EL1, 57eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGBCR15_EL1, 58eb2edc42SFrancesco Cagnin }; 59f49986aeSRichard Henderson 60f49986aeSRichard Henderson static const uint16_t dbgbvr_regs[] = { 61eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGBVR0_EL1, 62eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGBVR1_EL1, 63eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGBVR2_EL1, 64eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGBVR3_EL1, 65eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGBVR4_EL1, 66eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGBVR5_EL1, 67eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGBVR6_EL1, 68eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGBVR7_EL1, 69eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGBVR8_EL1, 70eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGBVR9_EL1, 71eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGBVR10_EL1, 72eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGBVR11_EL1, 73eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGBVR12_EL1, 74eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGBVR13_EL1, 75eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGBVR14_EL1, 76eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGBVR15_EL1, 77eb2edc42SFrancesco Cagnin }; 78f49986aeSRichard Henderson 79f49986aeSRichard Henderson static const uint16_t dbgwcr_regs[] = { 80eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGWCR0_EL1, 81eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGWCR1_EL1, 82eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGWCR2_EL1, 83eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGWCR3_EL1, 84eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGWCR4_EL1, 85eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGWCR5_EL1, 86eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGWCR6_EL1, 87eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGWCR7_EL1, 88eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGWCR8_EL1, 89eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGWCR9_EL1, 90eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGWCR10_EL1, 91eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGWCR11_EL1, 92eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGWCR12_EL1, 93eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGWCR13_EL1, 94eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGWCR14_EL1, 95eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGWCR15_EL1, 96eb2edc42SFrancesco Cagnin }; 97f49986aeSRichard Henderson 98f49986aeSRichard Henderson static const uint16_t dbgwvr_regs[] = { 99eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGWVR0_EL1, 100eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGWVR1_EL1, 101eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGWVR2_EL1, 102eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGWVR3_EL1, 103eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGWVR4_EL1, 104eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGWVR5_EL1, 105eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGWVR6_EL1, 106eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGWVR7_EL1, 107eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGWVR8_EL1, 108eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGWVR9_EL1, 109eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGWVR10_EL1, 110eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGWVR11_EL1, 111eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGWVR12_EL1, 112eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGWVR13_EL1, 113eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGWVR14_EL1, 114eb2edc42SFrancesco Cagnin HV_SYS_REG_DBGWVR15_EL1, 115eb2edc42SFrancesco Cagnin }; 116eb2edc42SFrancesco Cagnin 117eb2edc42SFrancesco Cagnin static inline int hvf_arm_num_brps(hv_vcpu_config_t config) 118eb2edc42SFrancesco Cagnin { 119eb2edc42SFrancesco Cagnin uint64_t val; 120eb2edc42SFrancesco Cagnin hv_return_t ret; 121eb2edc42SFrancesco Cagnin ret = hv_vcpu_config_get_feature_reg(config, HV_FEATURE_REG_ID_AA64DFR0_EL1, 122eb2edc42SFrancesco Cagnin &val); 123eb2edc42SFrancesco Cagnin assert_hvf_ok(ret); 124eb2edc42SFrancesco Cagnin return FIELD_EX64(val, ID_AA64DFR0, BRPS) + 1; 125eb2edc42SFrancesco Cagnin } 126eb2edc42SFrancesco Cagnin 127eb2edc42SFrancesco Cagnin static inline int hvf_arm_num_wrps(hv_vcpu_config_t config) 128eb2edc42SFrancesco Cagnin { 129eb2edc42SFrancesco Cagnin uint64_t val; 130eb2edc42SFrancesco Cagnin hv_return_t ret; 131eb2edc42SFrancesco Cagnin ret = hv_vcpu_config_get_feature_reg(config, HV_FEATURE_REG_ID_AA64DFR0_EL1, 132eb2edc42SFrancesco Cagnin &val); 133eb2edc42SFrancesco Cagnin assert_hvf_ok(ret); 134eb2edc42SFrancesco Cagnin return FIELD_EX64(val, ID_AA64DFR0, WRPS) + 1; 135eb2edc42SFrancesco Cagnin } 136eb2edc42SFrancesco Cagnin 137eb2edc42SFrancesco Cagnin void hvf_arm_init_debug(void) 138eb2edc42SFrancesco Cagnin { 139eb2edc42SFrancesco Cagnin hv_vcpu_config_t config; 140eb2edc42SFrancesco Cagnin config = hv_vcpu_config_create(); 141eb2edc42SFrancesco Cagnin 142eb2edc42SFrancesco Cagnin max_hw_bps = hvf_arm_num_brps(config); 143eb2edc42SFrancesco Cagnin hw_breakpoints = 144eb2edc42SFrancesco Cagnin g_array_sized_new(true, true, sizeof(HWBreakpoint), max_hw_bps); 145eb2edc42SFrancesco Cagnin 146eb2edc42SFrancesco Cagnin max_hw_wps = hvf_arm_num_wrps(config); 147eb2edc42SFrancesco Cagnin hw_watchpoints = 148eb2edc42SFrancesco Cagnin g_array_sized_new(true, true, sizeof(HWWatchpoint), max_hw_wps); 149eb2edc42SFrancesco Cagnin } 150eb2edc42SFrancesco Cagnin 151a1477da3SAlexander Graf #define HVF_SYSREG(crn, crm, op0, op1, op2) \ 152a1477da3SAlexander Graf ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2) 153a1477da3SAlexander Graf #define PL1_WRITE_MASK 0x4 154a1477da3SAlexander Graf 155ad99f64fSAlexander Graf #define SYSREG_OP0_SHIFT 20 156ad99f64fSAlexander Graf #define SYSREG_OP0_MASK 0x3 157ad99f64fSAlexander Graf #define SYSREG_OP0(sysreg) ((sysreg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK) 158ad99f64fSAlexander Graf #define SYSREG_OP1_SHIFT 14 159ad99f64fSAlexander Graf #define SYSREG_OP1_MASK 0x7 160ad99f64fSAlexander Graf #define SYSREG_OP1(sysreg) ((sysreg >> SYSREG_OP1_SHIFT) & SYSREG_OP1_MASK) 161ad99f64fSAlexander Graf #define SYSREG_CRN_SHIFT 10 162ad99f64fSAlexander Graf #define SYSREG_CRN_MASK 0xf 163ad99f64fSAlexander Graf #define SYSREG_CRN(sysreg) ((sysreg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK) 164ad99f64fSAlexander Graf #define SYSREG_CRM_SHIFT 1 165ad99f64fSAlexander Graf #define SYSREG_CRM_MASK 0xf 166ad99f64fSAlexander Graf #define SYSREG_CRM(sysreg) ((sysreg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK) 167ad99f64fSAlexander Graf #define SYSREG_OP2_SHIFT 17 168ad99f64fSAlexander Graf #define SYSREG_OP2_MASK 0x7 169ad99f64fSAlexander Graf #define SYSREG_OP2(sysreg) ((sysreg >> SYSREG_OP2_SHIFT) & SYSREG_OP2_MASK) 170ad99f64fSAlexander Graf 171a1477da3SAlexander Graf #define SYSREG(op0, op1, crn, crm, op2) \ 172ad99f64fSAlexander Graf ((op0 << SYSREG_OP0_SHIFT) | \ 173ad99f64fSAlexander Graf (op1 << SYSREG_OP1_SHIFT) | \ 174ad99f64fSAlexander Graf (crn << SYSREG_CRN_SHIFT) | \ 175ad99f64fSAlexander Graf (crm << SYSREG_CRM_SHIFT) | \ 176ad99f64fSAlexander Graf (op2 << SYSREG_OP2_SHIFT)) 177ad99f64fSAlexander Graf #define SYSREG_MASK \ 178ad99f64fSAlexander Graf SYSREG(SYSREG_OP0_MASK, \ 179ad99f64fSAlexander Graf SYSREG_OP1_MASK, \ 180ad99f64fSAlexander Graf SYSREG_CRN_MASK, \ 181ad99f64fSAlexander Graf SYSREG_CRM_MASK, \ 182ad99f64fSAlexander Graf SYSREG_OP2_MASK) 183a1477da3SAlexander Graf #define SYSREG_OSLAR_EL1 SYSREG(2, 0, 1, 0, 4) 184a1477da3SAlexander Graf #define SYSREG_OSLSR_EL1 SYSREG(2, 0, 1, 1, 4) 185a1477da3SAlexander Graf #define SYSREG_OSDLR_EL1 SYSREG(2, 0, 1, 3, 4) 186a1477da3SAlexander Graf #define SYSREG_CNTPCT_EL0 SYSREG(3, 3, 14, 0, 1) 187dd43ac07SAlexander Graf #define SYSREG_PMCR_EL0 SYSREG(3, 3, 9, 12, 0) 188dd43ac07SAlexander Graf #define SYSREG_PMUSERENR_EL0 SYSREG(3, 3, 9, 14, 0) 189dd43ac07SAlexander Graf #define SYSREG_PMCNTENSET_EL0 SYSREG(3, 3, 9, 12, 1) 190dd43ac07SAlexander Graf #define SYSREG_PMCNTENCLR_EL0 SYSREG(3, 3, 9, 12, 2) 191dd43ac07SAlexander Graf #define SYSREG_PMINTENCLR_EL1 SYSREG(3, 0, 9, 14, 2) 192dd43ac07SAlexander Graf #define SYSREG_PMOVSCLR_EL0 SYSREG(3, 3, 9, 12, 3) 193dd43ac07SAlexander Graf #define SYSREG_PMSWINC_EL0 SYSREG(3, 3, 9, 12, 4) 194dd43ac07SAlexander Graf #define SYSREG_PMSELR_EL0 SYSREG(3, 3, 9, 12, 5) 195dd43ac07SAlexander Graf #define SYSREG_PMCEID0_EL0 SYSREG(3, 3, 9, 12, 6) 196dd43ac07SAlexander Graf #define SYSREG_PMCEID1_EL0 SYSREG(3, 3, 9, 12, 7) 197dd43ac07SAlexander Graf #define SYSREG_PMCCNTR_EL0 SYSREG(3, 3, 9, 13, 0) 198dd43ac07SAlexander Graf #define SYSREG_PMCCFILTR_EL0 SYSREG(3, 3, 14, 15, 7) 199a1477da3SAlexander Graf 200a2260983SAlexander Graf #define SYSREG_ICC_AP0R0_EL1 SYSREG(3, 0, 12, 8, 4) 201a2260983SAlexander Graf #define SYSREG_ICC_AP0R1_EL1 SYSREG(3, 0, 12, 8, 5) 202a2260983SAlexander Graf #define SYSREG_ICC_AP0R2_EL1 SYSREG(3, 0, 12, 8, 6) 203a2260983SAlexander Graf #define SYSREG_ICC_AP0R3_EL1 SYSREG(3, 0, 12, 8, 7) 204a2260983SAlexander Graf #define SYSREG_ICC_AP1R0_EL1 SYSREG(3, 0, 12, 9, 0) 205a2260983SAlexander Graf #define SYSREG_ICC_AP1R1_EL1 SYSREG(3, 0, 12, 9, 1) 206a2260983SAlexander Graf #define SYSREG_ICC_AP1R2_EL1 SYSREG(3, 0, 12, 9, 2) 207a2260983SAlexander Graf #define SYSREG_ICC_AP1R3_EL1 SYSREG(3, 0, 12, 9, 3) 208a2260983SAlexander Graf #define SYSREG_ICC_ASGI1R_EL1 SYSREG(3, 0, 12, 11, 6) 209a2260983SAlexander Graf #define SYSREG_ICC_BPR0_EL1 SYSREG(3, 0, 12, 8, 3) 210a2260983SAlexander Graf #define SYSREG_ICC_BPR1_EL1 SYSREG(3, 0, 12, 12, 3) 211a2260983SAlexander Graf #define SYSREG_ICC_CTLR_EL1 SYSREG(3, 0, 12, 12, 4) 212a2260983SAlexander Graf #define SYSREG_ICC_DIR_EL1 SYSREG(3, 0, 12, 11, 1) 213a2260983SAlexander Graf #define SYSREG_ICC_EOIR0_EL1 SYSREG(3, 0, 12, 8, 1) 214a2260983SAlexander Graf #define SYSREG_ICC_EOIR1_EL1 SYSREG(3, 0, 12, 12, 1) 215a2260983SAlexander Graf #define SYSREG_ICC_HPPIR0_EL1 SYSREG(3, 0, 12, 8, 2) 216a2260983SAlexander Graf #define SYSREG_ICC_HPPIR1_EL1 SYSREG(3, 0, 12, 12, 2) 217a2260983SAlexander Graf #define SYSREG_ICC_IAR0_EL1 SYSREG(3, 0, 12, 8, 0) 218a2260983SAlexander Graf #define SYSREG_ICC_IAR1_EL1 SYSREG(3, 0, 12, 12, 0) 219a2260983SAlexander Graf #define SYSREG_ICC_IGRPEN0_EL1 SYSREG(3, 0, 12, 12, 6) 220a2260983SAlexander Graf #define SYSREG_ICC_IGRPEN1_EL1 SYSREG(3, 0, 12, 12, 7) 221a2260983SAlexander Graf #define SYSREG_ICC_PMR_EL1 SYSREG(3, 0, 4, 6, 0) 222a2260983SAlexander Graf #define SYSREG_ICC_RPR_EL1 SYSREG(3, 0, 12, 11, 3) 223a2260983SAlexander Graf #define SYSREG_ICC_SGI0R_EL1 SYSREG(3, 0, 12, 11, 7) 224a2260983SAlexander Graf #define SYSREG_ICC_SGI1R_EL1 SYSREG(3, 0, 12, 11, 5) 225a2260983SAlexander Graf #define SYSREG_ICC_SRE_EL1 SYSREG(3, 0, 12, 12, 5) 226a2260983SAlexander Graf 227ce799a04SFrancesco Cagnin #define SYSREG_MDSCR_EL1 SYSREG(2, 0, 0, 2, 2) 228ce799a04SFrancesco Cagnin #define SYSREG_DBGBVR0_EL1 SYSREG(2, 0, 0, 0, 4) 229ce799a04SFrancesco Cagnin #define SYSREG_DBGBCR0_EL1 SYSREG(2, 0, 0, 0, 5) 230ce799a04SFrancesco Cagnin #define SYSREG_DBGWVR0_EL1 SYSREG(2, 0, 0, 0, 6) 231ce799a04SFrancesco Cagnin #define SYSREG_DBGWCR0_EL1 SYSREG(2, 0, 0, 0, 7) 232ce799a04SFrancesco Cagnin #define SYSREG_DBGBVR1_EL1 SYSREG(2, 0, 0, 1, 4) 233ce799a04SFrancesco Cagnin #define SYSREG_DBGBCR1_EL1 SYSREG(2, 0, 0, 1, 5) 234ce799a04SFrancesco Cagnin #define SYSREG_DBGWVR1_EL1 SYSREG(2, 0, 0, 1, 6) 235ce799a04SFrancesco Cagnin #define SYSREG_DBGWCR1_EL1 SYSREG(2, 0, 0, 1, 7) 236ce799a04SFrancesco Cagnin #define SYSREG_DBGBVR2_EL1 SYSREG(2, 0, 0, 2, 4) 237ce799a04SFrancesco Cagnin #define SYSREG_DBGBCR2_EL1 SYSREG(2, 0, 0, 2, 5) 238ce799a04SFrancesco Cagnin #define SYSREG_DBGWVR2_EL1 SYSREG(2, 0, 0, 2, 6) 239ce799a04SFrancesco Cagnin #define SYSREG_DBGWCR2_EL1 SYSREG(2, 0, 0, 2, 7) 240ce799a04SFrancesco Cagnin #define SYSREG_DBGBVR3_EL1 SYSREG(2, 0, 0, 3, 4) 241ce799a04SFrancesco Cagnin #define SYSREG_DBGBCR3_EL1 SYSREG(2, 0, 0, 3, 5) 242ce799a04SFrancesco Cagnin #define SYSREG_DBGWVR3_EL1 SYSREG(2, 0, 0, 3, 6) 243ce799a04SFrancesco Cagnin #define SYSREG_DBGWCR3_EL1 SYSREG(2, 0, 0, 3, 7) 244ce799a04SFrancesco Cagnin #define SYSREG_DBGBVR4_EL1 SYSREG(2, 0, 0, 4, 4) 245ce799a04SFrancesco Cagnin #define SYSREG_DBGBCR4_EL1 SYSREG(2, 0, 0, 4, 5) 246ce799a04SFrancesco Cagnin #define SYSREG_DBGWVR4_EL1 SYSREG(2, 0, 0, 4, 6) 247ce799a04SFrancesco Cagnin #define SYSREG_DBGWCR4_EL1 SYSREG(2, 0, 0, 4, 7) 248ce799a04SFrancesco Cagnin #define SYSREG_DBGBVR5_EL1 SYSREG(2, 0, 0, 5, 4) 249ce799a04SFrancesco Cagnin #define SYSREG_DBGBCR5_EL1 SYSREG(2, 0, 0, 5, 5) 250ce799a04SFrancesco Cagnin #define SYSREG_DBGWVR5_EL1 SYSREG(2, 0, 0, 5, 6) 251ce799a04SFrancesco Cagnin #define SYSREG_DBGWCR5_EL1 SYSREG(2, 0, 0, 5, 7) 252ce799a04SFrancesco Cagnin #define SYSREG_DBGBVR6_EL1 SYSREG(2, 0, 0, 6, 4) 253ce799a04SFrancesco Cagnin #define SYSREG_DBGBCR6_EL1 SYSREG(2, 0, 0, 6, 5) 254ce799a04SFrancesco Cagnin #define SYSREG_DBGWVR6_EL1 SYSREG(2, 0, 0, 6, 6) 255ce799a04SFrancesco Cagnin #define SYSREG_DBGWCR6_EL1 SYSREG(2, 0, 0, 6, 7) 256ce799a04SFrancesco Cagnin #define SYSREG_DBGBVR7_EL1 SYSREG(2, 0, 0, 7, 4) 257ce799a04SFrancesco Cagnin #define SYSREG_DBGBCR7_EL1 SYSREG(2, 0, 0, 7, 5) 258ce799a04SFrancesco Cagnin #define SYSREG_DBGWVR7_EL1 SYSREG(2, 0, 0, 7, 6) 259ce799a04SFrancesco Cagnin #define SYSREG_DBGWCR7_EL1 SYSREG(2, 0, 0, 7, 7) 260ce799a04SFrancesco Cagnin #define SYSREG_DBGBVR8_EL1 SYSREG(2, 0, 0, 8, 4) 261ce799a04SFrancesco Cagnin #define SYSREG_DBGBCR8_EL1 SYSREG(2, 0, 0, 8, 5) 262ce799a04SFrancesco Cagnin #define SYSREG_DBGWVR8_EL1 SYSREG(2, 0, 0, 8, 6) 263ce799a04SFrancesco Cagnin #define SYSREG_DBGWCR8_EL1 SYSREG(2, 0, 0, 8, 7) 264ce799a04SFrancesco Cagnin #define SYSREG_DBGBVR9_EL1 SYSREG(2, 0, 0, 9, 4) 265ce799a04SFrancesco Cagnin #define SYSREG_DBGBCR9_EL1 SYSREG(2, 0, 0, 9, 5) 266ce799a04SFrancesco Cagnin #define SYSREG_DBGWVR9_EL1 SYSREG(2, 0, 0, 9, 6) 267ce799a04SFrancesco Cagnin #define SYSREG_DBGWCR9_EL1 SYSREG(2, 0, 0, 9, 7) 268ce799a04SFrancesco Cagnin #define SYSREG_DBGBVR10_EL1 SYSREG(2, 0, 0, 10, 4) 269ce799a04SFrancesco Cagnin #define SYSREG_DBGBCR10_EL1 SYSREG(2, 0, 0, 10, 5) 270ce799a04SFrancesco Cagnin #define SYSREG_DBGWVR10_EL1 SYSREG(2, 0, 0, 10, 6) 271ce799a04SFrancesco Cagnin #define SYSREG_DBGWCR10_EL1 SYSREG(2, 0, 0, 10, 7) 272ce799a04SFrancesco Cagnin #define SYSREG_DBGBVR11_EL1 SYSREG(2, 0, 0, 11, 4) 273ce799a04SFrancesco Cagnin #define SYSREG_DBGBCR11_EL1 SYSREG(2, 0, 0, 11, 5) 274ce799a04SFrancesco Cagnin #define SYSREG_DBGWVR11_EL1 SYSREG(2, 0, 0, 11, 6) 275ce799a04SFrancesco Cagnin #define SYSREG_DBGWCR11_EL1 SYSREG(2, 0, 0, 11, 7) 276ce799a04SFrancesco Cagnin #define SYSREG_DBGBVR12_EL1 SYSREG(2, 0, 0, 12, 4) 277ce799a04SFrancesco Cagnin #define SYSREG_DBGBCR12_EL1 SYSREG(2, 0, 0, 12, 5) 278ce799a04SFrancesco Cagnin #define SYSREG_DBGWVR12_EL1 SYSREG(2, 0, 0, 12, 6) 279ce799a04SFrancesco Cagnin #define SYSREG_DBGWCR12_EL1 SYSREG(2, 0, 0, 12, 7) 280ce799a04SFrancesco Cagnin #define SYSREG_DBGBVR13_EL1 SYSREG(2, 0, 0, 13, 4) 281ce799a04SFrancesco Cagnin #define SYSREG_DBGBCR13_EL1 SYSREG(2, 0, 0, 13, 5) 282ce799a04SFrancesco Cagnin #define SYSREG_DBGWVR13_EL1 SYSREG(2, 0, 0, 13, 6) 283ce799a04SFrancesco Cagnin #define SYSREG_DBGWCR13_EL1 SYSREG(2, 0, 0, 13, 7) 284ce799a04SFrancesco Cagnin #define SYSREG_DBGBVR14_EL1 SYSREG(2, 0, 0, 14, 4) 285ce799a04SFrancesco Cagnin #define SYSREG_DBGBCR14_EL1 SYSREG(2, 0, 0, 14, 5) 286ce799a04SFrancesco Cagnin #define SYSREG_DBGWVR14_EL1 SYSREG(2, 0, 0, 14, 6) 287ce799a04SFrancesco Cagnin #define SYSREG_DBGWCR14_EL1 SYSREG(2, 0, 0, 14, 7) 288ce799a04SFrancesco Cagnin #define SYSREG_DBGBVR15_EL1 SYSREG(2, 0, 0, 15, 4) 289ce799a04SFrancesco Cagnin #define SYSREG_DBGBCR15_EL1 SYSREG(2, 0, 0, 15, 5) 290ce799a04SFrancesco Cagnin #define SYSREG_DBGWVR15_EL1 SYSREG(2, 0, 0, 15, 6) 291ce799a04SFrancesco Cagnin #define SYSREG_DBGWCR15_EL1 SYSREG(2, 0, 0, 15, 7) 292ce799a04SFrancesco Cagnin 293a1477da3SAlexander Graf #define WFX_IS_WFE (1 << 0) 294a1477da3SAlexander Graf 295a1477da3SAlexander Graf #define TMR_CTL_ENABLE (1 << 0) 296a1477da3SAlexander Graf #define TMR_CTL_IMASK (1 << 1) 297a1477da3SAlexander Graf #define TMR_CTL_ISTATUS (1 << 2) 298a1477da3SAlexander Graf 2992c9c0bf9SAlexander Graf static void hvf_wfi(CPUState *cpu); 3002c9c0bf9SAlexander Graf 301a1477da3SAlexander Graf typedef struct HVFVTimer { 302a1477da3SAlexander Graf /* Vtimer value during migration and paused state */ 303a1477da3SAlexander Graf uint64_t vtimer_val; 304a1477da3SAlexander Graf } HVFVTimer; 305a1477da3SAlexander Graf 306a1477da3SAlexander Graf static HVFVTimer vtimer; 307a1477da3SAlexander Graf 308585df85eSPeter Maydell typedef struct ARMHostCPUFeatures { 309585df85eSPeter Maydell ARMISARegisters isar; 310585df85eSPeter Maydell uint64_t features; 311585df85eSPeter Maydell uint64_t midr; 312585df85eSPeter Maydell uint32_t reset_sctlr; 313585df85eSPeter Maydell const char *dtb_compatible; 314585df85eSPeter Maydell } ARMHostCPUFeatures; 315585df85eSPeter Maydell 316585df85eSPeter Maydell static ARMHostCPUFeatures arm_host_cpu_features; 317585df85eSPeter Maydell 318a1477da3SAlexander Graf struct hvf_reg_match { 319a1477da3SAlexander Graf int reg; 320a1477da3SAlexander Graf uint64_t offset; 321a1477da3SAlexander Graf }; 322a1477da3SAlexander Graf 323a1477da3SAlexander Graf static const struct hvf_reg_match hvf_reg_match[] = { 324a1477da3SAlexander Graf { HV_REG_X0, offsetof(CPUARMState, xregs[0]) }, 325a1477da3SAlexander Graf { HV_REG_X1, offsetof(CPUARMState, xregs[1]) }, 326a1477da3SAlexander Graf { HV_REG_X2, offsetof(CPUARMState, xregs[2]) }, 327a1477da3SAlexander Graf { HV_REG_X3, offsetof(CPUARMState, xregs[3]) }, 328a1477da3SAlexander Graf { HV_REG_X4, offsetof(CPUARMState, xregs[4]) }, 329a1477da3SAlexander Graf { HV_REG_X5, offsetof(CPUARMState, xregs[5]) }, 330a1477da3SAlexander Graf { HV_REG_X6, offsetof(CPUARMState, xregs[6]) }, 331a1477da3SAlexander Graf { HV_REG_X7, offsetof(CPUARMState, xregs[7]) }, 332a1477da3SAlexander Graf { HV_REG_X8, offsetof(CPUARMState, xregs[8]) }, 333a1477da3SAlexander Graf { HV_REG_X9, offsetof(CPUARMState, xregs[9]) }, 334a1477da3SAlexander Graf { HV_REG_X10, offsetof(CPUARMState, xregs[10]) }, 335a1477da3SAlexander Graf { HV_REG_X11, offsetof(CPUARMState, xregs[11]) }, 336a1477da3SAlexander Graf { HV_REG_X12, offsetof(CPUARMState, xregs[12]) }, 337a1477da3SAlexander Graf { HV_REG_X13, offsetof(CPUARMState, xregs[13]) }, 338a1477da3SAlexander Graf { HV_REG_X14, offsetof(CPUARMState, xregs[14]) }, 339a1477da3SAlexander Graf { HV_REG_X15, offsetof(CPUARMState, xregs[15]) }, 340a1477da3SAlexander Graf { HV_REG_X16, offsetof(CPUARMState, xregs[16]) }, 341a1477da3SAlexander Graf { HV_REG_X17, offsetof(CPUARMState, xregs[17]) }, 342a1477da3SAlexander Graf { HV_REG_X18, offsetof(CPUARMState, xregs[18]) }, 343a1477da3SAlexander Graf { HV_REG_X19, offsetof(CPUARMState, xregs[19]) }, 344a1477da3SAlexander Graf { HV_REG_X20, offsetof(CPUARMState, xregs[20]) }, 345a1477da3SAlexander Graf { HV_REG_X21, offsetof(CPUARMState, xregs[21]) }, 346a1477da3SAlexander Graf { HV_REG_X22, offsetof(CPUARMState, xregs[22]) }, 347a1477da3SAlexander Graf { HV_REG_X23, offsetof(CPUARMState, xregs[23]) }, 348a1477da3SAlexander Graf { HV_REG_X24, offsetof(CPUARMState, xregs[24]) }, 349a1477da3SAlexander Graf { HV_REG_X25, offsetof(CPUARMState, xregs[25]) }, 350a1477da3SAlexander Graf { HV_REG_X26, offsetof(CPUARMState, xregs[26]) }, 351a1477da3SAlexander Graf { HV_REG_X27, offsetof(CPUARMState, xregs[27]) }, 352a1477da3SAlexander Graf { HV_REG_X28, offsetof(CPUARMState, xregs[28]) }, 353a1477da3SAlexander Graf { HV_REG_X29, offsetof(CPUARMState, xregs[29]) }, 354a1477da3SAlexander Graf { HV_REG_X30, offsetof(CPUARMState, xregs[30]) }, 355a1477da3SAlexander Graf { HV_REG_PC, offsetof(CPUARMState, pc) }, 356a1477da3SAlexander Graf }; 357a1477da3SAlexander Graf 358a1477da3SAlexander Graf static const struct hvf_reg_match hvf_fpreg_match[] = { 359a1477da3SAlexander Graf { HV_SIMD_FP_REG_Q0, offsetof(CPUARMState, vfp.zregs[0]) }, 360a1477da3SAlexander Graf { HV_SIMD_FP_REG_Q1, offsetof(CPUARMState, vfp.zregs[1]) }, 361a1477da3SAlexander Graf { HV_SIMD_FP_REG_Q2, offsetof(CPUARMState, vfp.zregs[2]) }, 362a1477da3SAlexander Graf { HV_SIMD_FP_REG_Q3, offsetof(CPUARMState, vfp.zregs[3]) }, 363a1477da3SAlexander Graf { HV_SIMD_FP_REG_Q4, offsetof(CPUARMState, vfp.zregs[4]) }, 364a1477da3SAlexander Graf { HV_SIMD_FP_REG_Q5, offsetof(CPUARMState, vfp.zregs[5]) }, 365a1477da3SAlexander Graf { HV_SIMD_FP_REG_Q6, offsetof(CPUARMState, vfp.zregs[6]) }, 366a1477da3SAlexander Graf { HV_SIMD_FP_REG_Q7, offsetof(CPUARMState, vfp.zregs[7]) }, 367a1477da3SAlexander Graf { HV_SIMD_FP_REG_Q8, offsetof(CPUARMState, vfp.zregs[8]) }, 368a1477da3SAlexander Graf { HV_SIMD_FP_REG_Q9, offsetof(CPUARMState, vfp.zregs[9]) }, 369a1477da3SAlexander Graf { HV_SIMD_FP_REG_Q10, offsetof(CPUARMState, vfp.zregs[10]) }, 370a1477da3SAlexander Graf { HV_SIMD_FP_REG_Q11, offsetof(CPUARMState, vfp.zregs[11]) }, 371a1477da3SAlexander Graf { HV_SIMD_FP_REG_Q12, offsetof(CPUARMState, vfp.zregs[12]) }, 372a1477da3SAlexander Graf { HV_SIMD_FP_REG_Q13, offsetof(CPUARMState, vfp.zregs[13]) }, 373a1477da3SAlexander Graf { HV_SIMD_FP_REG_Q14, offsetof(CPUARMState, vfp.zregs[14]) }, 374a1477da3SAlexander Graf { HV_SIMD_FP_REG_Q15, offsetof(CPUARMState, vfp.zregs[15]) }, 375a1477da3SAlexander Graf { HV_SIMD_FP_REG_Q16, offsetof(CPUARMState, vfp.zregs[16]) }, 376a1477da3SAlexander Graf { HV_SIMD_FP_REG_Q17, offsetof(CPUARMState, vfp.zregs[17]) }, 377a1477da3SAlexander Graf { HV_SIMD_FP_REG_Q18, offsetof(CPUARMState, vfp.zregs[18]) }, 378a1477da3SAlexander Graf { HV_SIMD_FP_REG_Q19, offsetof(CPUARMState, vfp.zregs[19]) }, 379a1477da3SAlexander Graf { HV_SIMD_FP_REG_Q20, offsetof(CPUARMState, vfp.zregs[20]) }, 380a1477da3SAlexander Graf { HV_SIMD_FP_REG_Q21, offsetof(CPUARMState, vfp.zregs[21]) }, 381a1477da3SAlexander Graf { HV_SIMD_FP_REG_Q22, offsetof(CPUARMState, vfp.zregs[22]) }, 382a1477da3SAlexander Graf { HV_SIMD_FP_REG_Q23, offsetof(CPUARMState, vfp.zregs[23]) }, 383a1477da3SAlexander Graf { HV_SIMD_FP_REG_Q24, offsetof(CPUARMState, vfp.zregs[24]) }, 384a1477da3SAlexander Graf { HV_SIMD_FP_REG_Q25, offsetof(CPUARMState, vfp.zregs[25]) }, 385a1477da3SAlexander Graf { HV_SIMD_FP_REG_Q26, offsetof(CPUARMState, vfp.zregs[26]) }, 386a1477da3SAlexander Graf { HV_SIMD_FP_REG_Q27, offsetof(CPUARMState, vfp.zregs[27]) }, 387a1477da3SAlexander Graf { HV_SIMD_FP_REG_Q28, offsetof(CPUARMState, vfp.zregs[28]) }, 388a1477da3SAlexander Graf { HV_SIMD_FP_REG_Q29, offsetof(CPUARMState, vfp.zregs[29]) }, 389a1477da3SAlexander Graf { HV_SIMD_FP_REG_Q30, offsetof(CPUARMState, vfp.zregs[30]) }, 390a1477da3SAlexander Graf { HV_SIMD_FP_REG_Q31, offsetof(CPUARMState, vfp.zregs[31]) }, 391a1477da3SAlexander Graf }; 392a1477da3SAlexander Graf 393a1477da3SAlexander Graf struct hvf_sreg_match { 394a1477da3SAlexander Graf int reg; 395a1477da3SAlexander Graf uint32_t key; 396a1477da3SAlexander Graf uint32_t cp_idx; 397a1477da3SAlexander Graf }; 398a1477da3SAlexander Graf 399a1477da3SAlexander Graf static struct hvf_sreg_match hvf_sreg_match[] = { 400a1477da3SAlexander Graf { HV_SYS_REG_DBGBVR0_EL1, HVF_SYSREG(0, 0, 14, 0, 4) }, 401a1477da3SAlexander Graf { HV_SYS_REG_DBGBCR0_EL1, HVF_SYSREG(0, 0, 14, 0, 5) }, 402a1477da3SAlexander Graf { HV_SYS_REG_DBGWVR0_EL1, HVF_SYSREG(0, 0, 14, 0, 6) }, 403a1477da3SAlexander Graf { HV_SYS_REG_DBGWCR0_EL1, HVF_SYSREG(0, 0, 14, 0, 7) }, 404a1477da3SAlexander Graf 405a1477da3SAlexander Graf { HV_SYS_REG_DBGBVR1_EL1, HVF_SYSREG(0, 1, 14, 0, 4) }, 406a1477da3SAlexander Graf { HV_SYS_REG_DBGBCR1_EL1, HVF_SYSREG(0, 1, 14, 0, 5) }, 407a1477da3SAlexander Graf { HV_SYS_REG_DBGWVR1_EL1, HVF_SYSREG(0, 1, 14, 0, 6) }, 408a1477da3SAlexander Graf { HV_SYS_REG_DBGWCR1_EL1, HVF_SYSREG(0, 1, 14, 0, 7) }, 409a1477da3SAlexander Graf 410a1477da3SAlexander Graf { HV_SYS_REG_DBGBVR2_EL1, HVF_SYSREG(0, 2, 14, 0, 4) }, 411a1477da3SAlexander Graf { HV_SYS_REG_DBGBCR2_EL1, HVF_SYSREG(0, 2, 14, 0, 5) }, 412a1477da3SAlexander Graf { HV_SYS_REG_DBGWVR2_EL1, HVF_SYSREG(0, 2, 14, 0, 6) }, 413a1477da3SAlexander Graf { HV_SYS_REG_DBGWCR2_EL1, HVF_SYSREG(0, 2, 14, 0, 7) }, 414a1477da3SAlexander Graf 415a1477da3SAlexander Graf { HV_SYS_REG_DBGBVR3_EL1, HVF_SYSREG(0, 3, 14, 0, 4) }, 416a1477da3SAlexander Graf { HV_SYS_REG_DBGBCR3_EL1, HVF_SYSREG(0, 3, 14, 0, 5) }, 417a1477da3SAlexander Graf { HV_SYS_REG_DBGWVR3_EL1, HVF_SYSREG(0, 3, 14, 0, 6) }, 418a1477da3SAlexander Graf { HV_SYS_REG_DBGWCR3_EL1, HVF_SYSREG(0, 3, 14, 0, 7) }, 419a1477da3SAlexander Graf 420a1477da3SAlexander Graf { HV_SYS_REG_DBGBVR4_EL1, HVF_SYSREG(0, 4, 14, 0, 4) }, 421a1477da3SAlexander Graf { HV_SYS_REG_DBGBCR4_EL1, HVF_SYSREG(0, 4, 14, 0, 5) }, 422a1477da3SAlexander Graf { HV_SYS_REG_DBGWVR4_EL1, HVF_SYSREG(0, 4, 14, 0, 6) }, 423a1477da3SAlexander Graf { HV_SYS_REG_DBGWCR4_EL1, HVF_SYSREG(0, 4, 14, 0, 7) }, 424a1477da3SAlexander Graf 425a1477da3SAlexander Graf { HV_SYS_REG_DBGBVR5_EL1, HVF_SYSREG(0, 5, 14, 0, 4) }, 426a1477da3SAlexander Graf { HV_SYS_REG_DBGBCR5_EL1, HVF_SYSREG(0, 5, 14, 0, 5) }, 427a1477da3SAlexander Graf { HV_SYS_REG_DBGWVR5_EL1, HVF_SYSREG(0, 5, 14, 0, 6) }, 428a1477da3SAlexander Graf { HV_SYS_REG_DBGWCR5_EL1, HVF_SYSREG(0, 5, 14, 0, 7) }, 429a1477da3SAlexander Graf 430a1477da3SAlexander Graf { HV_SYS_REG_DBGBVR6_EL1, HVF_SYSREG(0, 6, 14, 0, 4) }, 431a1477da3SAlexander Graf { HV_SYS_REG_DBGBCR6_EL1, HVF_SYSREG(0, 6, 14, 0, 5) }, 432a1477da3SAlexander Graf { HV_SYS_REG_DBGWVR6_EL1, HVF_SYSREG(0, 6, 14, 0, 6) }, 433a1477da3SAlexander Graf { HV_SYS_REG_DBGWCR6_EL1, HVF_SYSREG(0, 6, 14, 0, 7) }, 434a1477da3SAlexander Graf 435a1477da3SAlexander Graf { HV_SYS_REG_DBGBVR7_EL1, HVF_SYSREG(0, 7, 14, 0, 4) }, 436a1477da3SAlexander Graf { HV_SYS_REG_DBGBCR7_EL1, HVF_SYSREG(0, 7, 14, 0, 5) }, 437a1477da3SAlexander Graf { HV_SYS_REG_DBGWVR7_EL1, HVF_SYSREG(0, 7, 14, 0, 6) }, 438a1477da3SAlexander Graf { HV_SYS_REG_DBGWCR7_EL1, HVF_SYSREG(0, 7, 14, 0, 7) }, 439a1477da3SAlexander Graf 440a1477da3SAlexander Graf { HV_SYS_REG_DBGBVR8_EL1, HVF_SYSREG(0, 8, 14, 0, 4) }, 441a1477da3SAlexander Graf { HV_SYS_REG_DBGBCR8_EL1, HVF_SYSREG(0, 8, 14, 0, 5) }, 442a1477da3SAlexander Graf { HV_SYS_REG_DBGWVR8_EL1, HVF_SYSREG(0, 8, 14, 0, 6) }, 443a1477da3SAlexander Graf { HV_SYS_REG_DBGWCR8_EL1, HVF_SYSREG(0, 8, 14, 0, 7) }, 444a1477da3SAlexander Graf 445a1477da3SAlexander Graf { HV_SYS_REG_DBGBVR9_EL1, HVF_SYSREG(0, 9, 14, 0, 4) }, 446a1477da3SAlexander Graf { HV_SYS_REG_DBGBCR9_EL1, HVF_SYSREG(0, 9, 14, 0, 5) }, 447a1477da3SAlexander Graf { HV_SYS_REG_DBGWVR9_EL1, HVF_SYSREG(0, 9, 14, 0, 6) }, 448a1477da3SAlexander Graf { HV_SYS_REG_DBGWCR9_EL1, HVF_SYSREG(0, 9, 14, 0, 7) }, 449a1477da3SAlexander Graf 450a1477da3SAlexander Graf { HV_SYS_REG_DBGBVR10_EL1, HVF_SYSREG(0, 10, 14, 0, 4) }, 451a1477da3SAlexander Graf { HV_SYS_REG_DBGBCR10_EL1, HVF_SYSREG(0, 10, 14, 0, 5) }, 452a1477da3SAlexander Graf { HV_SYS_REG_DBGWVR10_EL1, HVF_SYSREG(0, 10, 14, 0, 6) }, 453a1477da3SAlexander Graf { HV_SYS_REG_DBGWCR10_EL1, HVF_SYSREG(0, 10, 14, 0, 7) }, 454a1477da3SAlexander Graf 455a1477da3SAlexander Graf { HV_SYS_REG_DBGBVR11_EL1, HVF_SYSREG(0, 11, 14, 0, 4) }, 456a1477da3SAlexander Graf { HV_SYS_REG_DBGBCR11_EL1, HVF_SYSREG(0, 11, 14, 0, 5) }, 457a1477da3SAlexander Graf { HV_SYS_REG_DBGWVR11_EL1, HVF_SYSREG(0, 11, 14, 0, 6) }, 458a1477da3SAlexander Graf { HV_SYS_REG_DBGWCR11_EL1, HVF_SYSREG(0, 11, 14, 0, 7) }, 459a1477da3SAlexander Graf 460a1477da3SAlexander Graf { HV_SYS_REG_DBGBVR12_EL1, HVF_SYSREG(0, 12, 14, 0, 4) }, 461a1477da3SAlexander Graf { HV_SYS_REG_DBGBCR12_EL1, HVF_SYSREG(0, 12, 14, 0, 5) }, 462a1477da3SAlexander Graf { HV_SYS_REG_DBGWVR12_EL1, HVF_SYSREG(0, 12, 14, 0, 6) }, 463a1477da3SAlexander Graf { HV_SYS_REG_DBGWCR12_EL1, HVF_SYSREG(0, 12, 14, 0, 7) }, 464a1477da3SAlexander Graf 465a1477da3SAlexander Graf { HV_SYS_REG_DBGBVR13_EL1, HVF_SYSREG(0, 13, 14, 0, 4) }, 466a1477da3SAlexander Graf { HV_SYS_REG_DBGBCR13_EL1, HVF_SYSREG(0, 13, 14, 0, 5) }, 467a1477da3SAlexander Graf { HV_SYS_REG_DBGWVR13_EL1, HVF_SYSREG(0, 13, 14, 0, 6) }, 468a1477da3SAlexander Graf { HV_SYS_REG_DBGWCR13_EL1, HVF_SYSREG(0, 13, 14, 0, 7) }, 469a1477da3SAlexander Graf 470a1477da3SAlexander Graf { HV_SYS_REG_DBGBVR14_EL1, HVF_SYSREG(0, 14, 14, 0, 4) }, 471a1477da3SAlexander Graf { HV_SYS_REG_DBGBCR14_EL1, HVF_SYSREG(0, 14, 14, 0, 5) }, 472a1477da3SAlexander Graf { HV_SYS_REG_DBGWVR14_EL1, HVF_SYSREG(0, 14, 14, 0, 6) }, 473a1477da3SAlexander Graf { HV_SYS_REG_DBGWCR14_EL1, HVF_SYSREG(0, 14, 14, 0, 7) }, 474a1477da3SAlexander Graf 475a1477da3SAlexander Graf { HV_SYS_REG_DBGBVR15_EL1, HVF_SYSREG(0, 15, 14, 0, 4) }, 476a1477da3SAlexander Graf { HV_SYS_REG_DBGBCR15_EL1, HVF_SYSREG(0, 15, 14, 0, 5) }, 477a1477da3SAlexander Graf { HV_SYS_REG_DBGWVR15_EL1, HVF_SYSREG(0, 15, 14, 0, 6) }, 478a1477da3SAlexander Graf { HV_SYS_REG_DBGWCR15_EL1, HVF_SYSREG(0, 15, 14, 0, 7) }, 479a1477da3SAlexander Graf 480a1477da3SAlexander Graf #ifdef SYNC_NO_RAW_REGS 481a1477da3SAlexander Graf /* 482a1477da3SAlexander Graf * The registers below are manually synced on init because they are 483a1477da3SAlexander Graf * marked as NO_RAW. We still list them to make number space sync easier. 484a1477da3SAlexander Graf */ 485a1477da3SAlexander Graf { HV_SYS_REG_MDCCINT_EL1, HVF_SYSREG(0, 2, 2, 0, 0) }, 486a1477da3SAlexander Graf { HV_SYS_REG_MIDR_EL1, HVF_SYSREG(0, 0, 3, 0, 0) }, 487a1477da3SAlexander Graf { HV_SYS_REG_MPIDR_EL1, HVF_SYSREG(0, 0, 3, 0, 5) }, 488a1477da3SAlexander Graf { HV_SYS_REG_ID_AA64PFR0_EL1, HVF_SYSREG(0, 4, 3, 0, 0) }, 489a1477da3SAlexander Graf #endif 490a1477da3SAlexander Graf { HV_SYS_REG_ID_AA64PFR1_EL1, HVF_SYSREG(0, 4, 3, 0, 2) }, 491a1477da3SAlexander Graf { HV_SYS_REG_ID_AA64DFR0_EL1, HVF_SYSREG(0, 5, 3, 0, 0) }, 492a1477da3SAlexander Graf { HV_SYS_REG_ID_AA64DFR1_EL1, HVF_SYSREG(0, 5, 3, 0, 1) }, 493a1477da3SAlexander Graf { HV_SYS_REG_ID_AA64ISAR0_EL1, HVF_SYSREG(0, 6, 3, 0, 0) }, 494a1477da3SAlexander Graf { HV_SYS_REG_ID_AA64ISAR1_EL1, HVF_SYSREG(0, 6, 3, 0, 1) }, 495a1477da3SAlexander Graf #ifdef SYNC_NO_MMFR0 496a1477da3SAlexander Graf /* We keep the hardware MMFR0 around. HW limits are there anyway */ 497a1477da3SAlexander Graf { HV_SYS_REG_ID_AA64MMFR0_EL1, HVF_SYSREG(0, 7, 3, 0, 0) }, 498a1477da3SAlexander Graf #endif 499a1477da3SAlexander Graf { HV_SYS_REG_ID_AA64MMFR1_EL1, HVF_SYSREG(0, 7, 3, 0, 1) }, 500a1477da3SAlexander Graf { HV_SYS_REG_ID_AA64MMFR2_EL1, HVF_SYSREG(0, 7, 3, 0, 2) }, 501a1477da3SAlexander Graf 502a1477da3SAlexander Graf { HV_SYS_REG_MDSCR_EL1, HVF_SYSREG(0, 2, 2, 0, 2) }, 503a1477da3SAlexander Graf { HV_SYS_REG_SCTLR_EL1, HVF_SYSREG(1, 0, 3, 0, 0) }, 504a1477da3SAlexander Graf { HV_SYS_REG_CPACR_EL1, HVF_SYSREG(1, 0, 3, 0, 2) }, 505a1477da3SAlexander Graf { HV_SYS_REG_TTBR0_EL1, HVF_SYSREG(2, 0, 3, 0, 0) }, 506a1477da3SAlexander Graf { HV_SYS_REG_TTBR1_EL1, HVF_SYSREG(2, 0, 3, 0, 1) }, 507a1477da3SAlexander Graf { HV_SYS_REG_TCR_EL1, HVF_SYSREG(2, 0, 3, 0, 2) }, 508a1477da3SAlexander Graf 509a1477da3SAlexander Graf { HV_SYS_REG_APIAKEYLO_EL1, HVF_SYSREG(2, 1, 3, 0, 0) }, 510a1477da3SAlexander Graf { HV_SYS_REG_APIAKEYHI_EL1, HVF_SYSREG(2, 1, 3, 0, 1) }, 511a1477da3SAlexander Graf { HV_SYS_REG_APIBKEYLO_EL1, HVF_SYSREG(2, 1, 3, 0, 2) }, 512a1477da3SAlexander Graf { HV_SYS_REG_APIBKEYHI_EL1, HVF_SYSREG(2, 1, 3, 0, 3) }, 513a1477da3SAlexander Graf { HV_SYS_REG_APDAKEYLO_EL1, HVF_SYSREG(2, 2, 3, 0, 0) }, 514a1477da3SAlexander Graf { HV_SYS_REG_APDAKEYHI_EL1, HVF_SYSREG(2, 2, 3, 0, 1) }, 515a1477da3SAlexander Graf { HV_SYS_REG_APDBKEYLO_EL1, HVF_SYSREG(2, 2, 3, 0, 2) }, 516a1477da3SAlexander Graf { HV_SYS_REG_APDBKEYHI_EL1, HVF_SYSREG(2, 2, 3, 0, 3) }, 517a1477da3SAlexander Graf { HV_SYS_REG_APGAKEYLO_EL1, HVF_SYSREG(2, 3, 3, 0, 0) }, 518a1477da3SAlexander Graf { HV_SYS_REG_APGAKEYHI_EL1, HVF_SYSREG(2, 3, 3, 0, 1) }, 519a1477da3SAlexander Graf 520a1477da3SAlexander Graf { HV_SYS_REG_SPSR_EL1, HVF_SYSREG(4, 0, 3, 0, 0) }, 521a1477da3SAlexander Graf { HV_SYS_REG_ELR_EL1, HVF_SYSREG(4, 0, 3, 0, 1) }, 522a1477da3SAlexander Graf { HV_SYS_REG_SP_EL0, HVF_SYSREG(4, 1, 3, 0, 0) }, 523a1477da3SAlexander Graf { HV_SYS_REG_AFSR0_EL1, HVF_SYSREG(5, 1, 3, 0, 0) }, 524a1477da3SAlexander Graf { HV_SYS_REG_AFSR1_EL1, HVF_SYSREG(5, 1, 3, 0, 1) }, 525a1477da3SAlexander Graf { HV_SYS_REG_ESR_EL1, HVF_SYSREG(5, 2, 3, 0, 0) }, 526a1477da3SAlexander Graf { HV_SYS_REG_FAR_EL1, HVF_SYSREG(6, 0, 3, 0, 0) }, 527a1477da3SAlexander Graf { HV_SYS_REG_PAR_EL1, HVF_SYSREG(7, 4, 3, 0, 0) }, 528a1477da3SAlexander Graf { HV_SYS_REG_MAIR_EL1, HVF_SYSREG(10, 2, 3, 0, 0) }, 529a1477da3SAlexander Graf { HV_SYS_REG_AMAIR_EL1, HVF_SYSREG(10, 3, 3, 0, 0) }, 530a1477da3SAlexander Graf { HV_SYS_REG_VBAR_EL1, HVF_SYSREG(12, 0, 3, 0, 0) }, 531a1477da3SAlexander Graf { HV_SYS_REG_CONTEXTIDR_EL1, HVF_SYSREG(13, 0, 3, 0, 1) }, 532a1477da3SAlexander Graf { HV_SYS_REG_TPIDR_EL1, HVF_SYSREG(13, 0, 3, 0, 4) }, 533a1477da3SAlexander Graf { HV_SYS_REG_CNTKCTL_EL1, HVF_SYSREG(14, 1, 3, 0, 0) }, 534a1477da3SAlexander Graf { HV_SYS_REG_CSSELR_EL1, HVF_SYSREG(0, 0, 3, 2, 0) }, 535a1477da3SAlexander Graf { HV_SYS_REG_TPIDR_EL0, HVF_SYSREG(13, 0, 3, 3, 2) }, 536a1477da3SAlexander Graf { HV_SYS_REG_TPIDRRO_EL0, HVF_SYSREG(13, 0, 3, 3, 3) }, 537a1477da3SAlexander Graf { HV_SYS_REG_CNTV_CTL_EL0, HVF_SYSREG(14, 3, 3, 3, 1) }, 538a1477da3SAlexander Graf { HV_SYS_REG_CNTV_CVAL_EL0, HVF_SYSREG(14, 3, 3, 3, 2) }, 539a1477da3SAlexander Graf { HV_SYS_REG_SP_EL1, HVF_SYSREG(4, 1, 3, 4, 0) }, 540a1477da3SAlexander Graf }; 541a1477da3SAlexander Graf 542a1477da3SAlexander Graf int hvf_get_registers(CPUState *cpu) 543a1477da3SAlexander Graf { 544a1477da3SAlexander Graf ARMCPU *arm_cpu = ARM_CPU(cpu); 545a1477da3SAlexander Graf CPUARMState *env = &arm_cpu->env; 546a1477da3SAlexander Graf hv_return_t ret; 547a1477da3SAlexander Graf uint64_t val; 548a1477da3SAlexander Graf hv_simd_fp_uchar16_t fpval; 549a1477da3SAlexander Graf int i; 550a1477da3SAlexander Graf 551a1477da3SAlexander Graf for (i = 0; i < ARRAY_SIZE(hvf_reg_match); i++) { 5523b295bcbSPhilippe Mathieu-Daudé ret = hv_vcpu_get_reg(cpu->accel->fd, hvf_reg_match[i].reg, &val); 553a1477da3SAlexander Graf *(uint64_t *)((void *)env + hvf_reg_match[i].offset) = val; 554a1477da3SAlexander Graf assert_hvf_ok(ret); 555a1477da3SAlexander Graf } 556a1477da3SAlexander Graf 557a1477da3SAlexander Graf for (i = 0; i < ARRAY_SIZE(hvf_fpreg_match); i++) { 5583b295bcbSPhilippe Mathieu-Daudé ret = hv_vcpu_get_simd_fp_reg(cpu->accel->fd, hvf_fpreg_match[i].reg, 559a1477da3SAlexander Graf &fpval); 560a1477da3SAlexander Graf memcpy((void *)env + hvf_fpreg_match[i].offset, &fpval, sizeof(fpval)); 561a1477da3SAlexander Graf assert_hvf_ok(ret); 562a1477da3SAlexander Graf } 563a1477da3SAlexander Graf 564a1477da3SAlexander Graf val = 0; 5653b295bcbSPhilippe Mathieu-Daudé ret = hv_vcpu_get_reg(cpu->accel->fd, HV_REG_FPCR, &val); 566a1477da3SAlexander Graf assert_hvf_ok(ret); 567a1477da3SAlexander Graf vfp_set_fpcr(env, val); 568a1477da3SAlexander Graf 569a1477da3SAlexander Graf val = 0; 5703b295bcbSPhilippe Mathieu-Daudé ret = hv_vcpu_get_reg(cpu->accel->fd, HV_REG_FPSR, &val); 571a1477da3SAlexander Graf assert_hvf_ok(ret); 572a1477da3SAlexander Graf vfp_set_fpsr(env, val); 573a1477da3SAlexander Graf 5743b295bcbSPhilippe Mathieu-Daudé ret = hv_vcpu_get_reg(cpu->accel->fd, HV_REG_CPSR, &val); 575a1477da3SAlexander Graf assert_hvf_ok(ret); 576a1477da3SAlexander Graf pstate_write(env, val); 577a1477da3SAlexander Graf 578a1477da3SAlexander Graf for (i = 0; i < ARRAY_SIZE(hvf_sreg_match); i++) { 579a1477da3SAlexander Graf if (hvf_sreg_match[i].cp_idx == -1) { 580a1477da3SAlexander Graf continue; 581a1477da3SAlexander Graf } 582a1477da3SAlexander Graf 5833b295bcbSPhilippe Mathieu-Daudé if (cpu->accel->guest_debug_enabled) { 584eb2edc42SFrancesco Cagnin /* Handle debug registers */ 585eb2edc42SFrancesco Cagnin switch (hvf_sreg_match[i].reg) { 586eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBVR0_EL1: 587eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBCR0_EL1: 588eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWVR0_EL1: 589eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWCR0_EL1: 590eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBVR1_EL1: 591eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBCR1_EL1: 592eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWVR1_EL1: 593eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWCR1_EL1: 594eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBVR2_EL1: 595eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBCR2_EL1: 596eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWVR2_EL1: 597eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWCR2_EL1: 598eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBVR3_EL1: 599eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBCR3_EL1: 600eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWVR3_EL1: 601eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWCR3_EL1: 602eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBVR4_EL1: 603eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBCR4_EL1: 604eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWVR4_EL1: 605eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWCR4_EL1: 606eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBVR5_EL1: 607eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBCR5_EL1: 608eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWVR5_EL1: 609eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWCR5_EL1: 610eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBVR6_EL1: 611eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBCR6_EL1: 612eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWVR6_EL1: 613eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWCR6_EL1: 614eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBVR7_EL1: 615eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBCR7_EL1: 616eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWVR7_EL1: 617eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWCR7_EL1: 618eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBVR8_EL1: 619eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBCR8_EL1: 620eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWVR8_EL1: 621eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWCR8_EL1: 622eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBVR9_EL1: 623eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBCR9_EL1: 624eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWVR9_EL1: 625eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWCR9_EL1: 626eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBVR10_EL1: 627eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBCR10_EL1: 628eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWVR10_EL1: 629eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWCR10_EL1: 630eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBVR11_EL1: 631eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBCR11_EL1: 632eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWVR11_EL1: 633eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWCR11_EL1: 634eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBVR12_EL1: 635eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBCR12_EL1: 636eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWVR12_EL1: 637eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWCR12_EL1: 638eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBVR13_EL1: 639eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBCR13_EL1: 640eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWVR13_EL1: 641eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWCR13_EL1: 642eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBVR14_EL1: 643eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBCR14_EL1: 644eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWVR14_EL1: 645eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWCR14_EL1: 646eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBVR15_EL1: 647eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBCR15_EL1: 648eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWVR15_EL1: 649eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWCR15_EL1: { 650eb2edc42SFrancesco Cagnin /* 651eb2edc42SFrancesco Cagnin * If the guest is being debugged, the vCPU's debug registers 652eb2edc42SFrancesco Cagnin * are holding the gdbstub's view of the registers (set in 653eb2edc42SFrancesco Cagnin * hvf_arch_update_guest_debug()). 654eb2edc42SFrancesco Cagnin * Since the environment is used to store only the guest's view 655eb2edc42SFrancesco Cagnin * of the registers, don't update it with the values from the 656eb2edc42SFrancesco Cagnin * vCPU but simply keep the values from the previous 657eb2edc42SFrancesco Cagnin * environment. 658eb2edc42SFrancesco Cagnin */ 659eb2edc42SFrancesco Cagnin const ARMCPRegInfo *ri; 660eb2edc42SFrancesco Cagnin ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_sreg_match[i].key); 661eb2edc42SFrancesco Cagnin val = read_raw_cp_reg(env, ri); 662eb2edc42SFrancesco Cagnin 663eb2edc42SFrancesco Cagnin arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx] = val; 664eb2edc42SFrancesco Cagnin continue; 665eb2edc42SFrancesco Cagnin } 666eb2edc42SFrancesco Cagnin } 667eb2edc42SFrancesco Cagnin } 668eb2edc42SFrancesco Cagnin 6693b295bcbSPhilippe Mathieu-Daudé ret = hv_vcpu_get_sys_reg(cpu->accel->fd, hvf_sreg_match[i].reg, &val); 670a1477da3SAlexander Graf assert_hvf_ok(ret); 671a1477da3SAlexander Graf 672a1477da3SAlexander Graf arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx] = val; 673a1477da3SAlexander Graf } 674a1477da3SAlexander Graf assert(write_list_to_cpustate(arm_cpu)); 675a1477da3SAlexander Graf 676a1477da3SAlexander Graf aarch64_restore_sp(env, arm_current_el(env)); 677a1477da3SAlexander Graf 678a1477da3SAlexander Graf return 0; 679a1477da3SAlexander Graf } 680a1477da3SAlexander Graf 681a1477da3SAlexander Graf int hvf_put_registers(CPUState *cpu) 682a1477da3SAlexander Graf { 683a1477da3SAlexander Graf ARMCPU *arm_cpu = ARM_CPU(cpu); 684a1477da3SAlexander Graf CPUARMState *env = &arm_cpu->env; 685a1477da3SAlexander Graf hv_return_t ret; 686a1477da3SAlexander Graf uint64_t val; 687a1477da3SAlexander Graf hv_simd_fp_uchar16_t fpval; 688a1477da3SAlexander Graf int i; 689a1477da3SAlexander Graf 690a1477da3SAlexander Graf for (i = 0; i < ARRAY_SIZE(hvf_reg_match); i++) { 691a1477da3SAlexander Graf val = *(uint64_t *)((void *)env + hvf_reg_match[i].offset); 6923b295bcbSPhilippe Mathieu-Daudé ret = hv_vcpu_set_reg(cpu->accel->fd, hvf_reg_match[i].reg, val); 693a1477da3SAlexander Graf assert_hvf_ok(ret); 694a1477da3SAlexander Graf } 695a1477da3SAlexander Graf 696a1477da3SAlexander Graf for (i = 0; i < ARRAY_SIZE(hvf_fpreg_match); i++) { 697a1477da3SAlexander Graf memcpy(&fpval, (void *)env + hvf_fpreg_match[i].offset, sizeof(fpval)); 6983b295bcbSPhilippe Mathieu-Daudé ret = hv_vcpu_set_simd_fp_reg(cpu->accel->fd, hvf_fpreg_match[i].reg, 699a1477da3SAlexander Graf fpval); 700a1477da3SAlexander Graf assert_hvf_ok(ret); 701a1477da3SAlexander Graf } 702a1477da3SAlexander Graf 7033b295bcbSPhilippe Mathieu-Daudé ret = hv_vcpu_set_reg(cpu->accel->fd, HV_REG_FPCR, vfp_get_fpcr(env)); 704a1477da3SAlexander Graf assert_hvf_ok(ret); 705a1477da3SAlexander Graf 7063b295bcbSPhilippe Mathieu-Daudé ret = hv_vcpu_set_reg(cpu->accel->fd, HV_REG_FPSR, vfp_get_fpsr(env)); 707a1477da3SAlexander Graf assert_hvf_ok(ret); 708a1477da3SAlexander Graf 7093b295bcbSPhilippe Mathieu-Daudé ret = hv_vcpu_set_reg(cpu->accel->fd, HV_REG_CPSR, pstate_read(env)); 710a1477da3SAlexander Graf assert_hvf_ok(ret); 711a1477da3SAlexander Graf 712a1477da3SAlexander Graf aarch64_save_sp(env, arm_current_el(env)); 713a1477da3SAlexander Graf 714a1477da3SAlexander Graf assert(write_cpustate_to_list(arm_cpu, false)); 715a1477da3SAlexander Graf for (i = 0; i < ARRAY_SIZE(hvf_sreg_match); i++) { 716a1477da3SAlexander Graf if (hvf_sreg_match[i].cp_idx == -1) { 717a1477da3SAlexander Graf continue; 718a1477da3SAlexander Graf } 719a1477da3SAlexander Graf 7203b295bcbSPhilippe Mathieu-Daudé if (cpu->accel->guest_debug_enabled) { 721eb2edc42SFrancesco Cagnin /* Handle debug registers */ 722eb2edc42SFrancesco Cagnin switch (hvf_sreg_match[i].reg) { 723eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBVR0_EL1: 724eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBCR0_EL1: 725eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWVR0_EL1: 726eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWCR0_EL1: 727eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBVR1_EL1: 728eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBCR1_EL1: 729eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWVR1_EL1: 730eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWCR1_EL1: 731eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBVR2_EL1: 732eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBCR2_EL1: 733eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWVR2_EL1: 734eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWCR2_EL1: 735eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBVR3_EL1: 736eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBCR3_EL1: 737eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWVR3_EL1: 738eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWCR3_EL1: 739eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBVR4_EL1: 740eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBCR4_EL1: 741eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWVR4_EL1: 742eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWCR4_EL1: 743eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBVR5_EL1: 744eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBCR5_EL1: 745eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWVR5_EL1: 746eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWCR5_EL1: 747eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBVR6_EL1: 748eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBCR6_EL1: 749eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWVR6_EL1: 750eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWCR6_EL1: 751eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBVR7_EL1: 752eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBCR7_EL1: 753eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWVR7_EL1: 754eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWCR7_EL1: 755eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBVR8_EL1: 756eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBCR8_EL1: 757eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWVR8_EL1: 758eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWCR8_EL1: 759eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBVR9_EL1: 760eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBCR9_EL1: 761eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWVR9_EL1: 762eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWCR9_EL1: 763eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBVR10_EL1: 764eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBCR10_EL1: 765eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWVR10_EL1: 766eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWCR10_EL1: 767eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBVR11_EL1: 768eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBCR11_EL1: 769eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWVR11_EL1: 770eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWCR11_EL1: 771eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBVR12_EL1: 772eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBCR12_EL1: 773eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWVR12_EL1: 774eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWCR12_EL1: 775eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBVR13_EL1: 776eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBCR13_EL1: 777eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWVR13_EL1: 778eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWCR13_EL1: 779eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBVR14_EL1: 780eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBCR14_EL1: 781eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWVR14_EL1: 782eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWCR14_EL1: 783eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBVR15_EL1: 784eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGBCR15_EL1: 785eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWVR15_EL1: 786eb2edc42SFrancesco Cagnin case HV_SYS_REG_DBGWCR15_EL1: 787eb2edc42SFrancesco Cagnin /* 788eb2edc42SFrancesco Cagnin * If the guest is being debugged, the vCPU's debug registers 789eb2edc42SFrancesco Cagnin * are already holding the gdbstub's view of the registers (set 790eb2edc42SFrancesco Cagnin * in hvf_arch_update_guest_debug()). 791eb2edc42SFrancesco Cagnin */ 792eb2edc42SFrancesco Cagnin continue; 793eb2edc42SFrancesco Cagnin } 794eb2edc42SFrancesco Cagnin } 795eb2edc42SFrancesco Cagnin 796a1477da3SAlexander Graf val = arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx]; 7973b295bcbSPhilippe Mathieu-Daudé ret = hv_vcpu_set_sys_reg(cpu->accel->fd, hvf_sreg_match[i].reg, val); 798a1477da3SAlexander Graf assert_hvf_ok(ret); 799a1477da3SAlexander Graf } 800a1477da3SAlexander Graf 8013b295bcbSPhilippe Mathieu-Daudé ret = hv_vcpu_set_vtimer_offset(cpu->accel->fd, hvf_state->vtimer_offset); 802a1477da3SAlexander Graf assert_hvf_ok(ret); 803a1477da3SAlexander Graf 804a1477da3SAlexander Graf return 0; 805a1477da3SAlexander Graf } 806a1477da3SAlexander Graf 807a1477da3SAlexander Graf static void flush_cpu_state(CPUState *cpu) 808a1477da3SAlexander Graf { 809e6203636SPhilippe Mathieu-Daudé if (cpu->accel->dirty) { 810a1477da3SAlexander Graf hvf_put_registers(cpu); 811e6203636SPhilippe Mathieu-Daudé cpu->accel->dirty = false; 812a1477da3SAlexander Graf } 813a1477da3SAlexander Graf } 814a1477da3SAlexander Graf 815a1477da3SAlexander Graf static void hvf_set_reg(CPUState *cpu, int rt, uint64_t val) 816a1477da3SAlexander Graf { 817a1477da3SAlexander Graf hv_return_t r; 818a1477da3SAlexander Graf 819a1477da3SAlexander Graf flush_cpu_state(cpu); 820a1477da3SAlexander Graf 821a1477da3SAlexander Graf if (rt < 31) { 8223b295bcbSPhilippe Mathieu-Daudé r = hv_vcpu_set_reg(cpu->accel->fd, HV_REG_X0 + rt, val); 823a1477da3SAlexander Graf assert_hvf_ok(r); 824a1477da3SAlexander Graf } 825a1477da3SAlexander Graf } 826a1477da3SAlexander Graf 827a1477da3SAlexander Graf static uint64_t hvf_get_reg(CPUState *cpu, int rt) 828a1477da3SAlexander Graf { 829a1477da3SAlexander Graf uint64_t val = 0; 830a1477da3SAlexander Graf hv_return_t r; 831a1477da3SAlexander Graf 832a1477da3SAlexander Graf flush_cpu_state(cpu); 833a1477da3SAlexander Graf 834a1477da3SAlexander Graf if (rt < 31) { 8353b295bcbSPhilippe Mathieu-Daudé r = hv_vcpu_get_reg(cpu->accel->fd, HV_REG_X0 + rt, &val); 836a1477da3SAlexander Graf assert_hvf_ok(r); 837a1477da3SAlexander Graf } 838a1477da3SAlexander Graf 839a1477da3SAlexander Graf return val; 840a1477da3SAlexander Graf } 841a1477da3SAlexander Graf 842585df85eSPeter Maydell static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) 843585df85eSPeter Maydell { 844585df85eSPeter Maydell ARMISARegisters host_isar = {}; 845585df85eSPeter Maydell const struct isar_regs { 846585df85eSPeter Maydell int reg; 847585df85eSPeter Maydell uint64_t *val; 848585df85eSPeter Maydell } regs[] = { 849585df85eSPeter Maydell { HV_SYS_REG_ID_AA64PFR0_EL1, &host_isar.id_aa64pfr0 }, 850585df85eSPeter Maydell { HV_SYS_REG_ID_AA64PFR1_EL1, &host_isar.id_aa64pfr1 }, 851585df85eSPeter Maydell { HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.id_aa64dfr0 }, 852585df85eSPeter Maydell { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.id_aa64dfr1 }, 853585df85eSPeter Maydell { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.id_aa64isar0 }, 854585df85eSPeter Maydell { HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.id_aa64isar1 }, 855a969fe97SAaron Lindsay /* Add ID_AA64ISAR2_EL1 here when HVF supports it */ 856585df85eSPeter Maydell { HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.id_aa64mmfr0 }, 857585df85eSPeter Maydell { HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.id_aa64mmfr1 }, 858585df85eSPeter Maydell { HV_SYS_REG_ID_AA64MMFR2_EL1, &host_isar.id_aa64mmfr2 }, 859585df85eSPeter Maydell }; 860585df85eSPeter Maydell hv_vcpu_t fd; 861585df85eSPeter Maydell hv_return_t r = HV_SUCCESS; 862585df85eSPeter Maydell hv_vcpu_exit_t *exit; 863585df85eSPeter Maydell int i; 864585df85eSPeter Maydell 865585df85eSPeter Maydell ahcf->dtb_compatible = "arm,arm-v8"; 866585df85eSPeter Maydell ahcf->features = (1ULL << ARM_FEATURE_V8) | 867585df85eSPeter Maydell (1ULL << ARM_FEATURE_NEON) | 868585df85eSPeter Maydell (1ULL << ARM_FEATURE_AARCH64) | 869585df85eSPeter Maydell (1ULL << ARM_FEATURE_PMU) | 870585df85eSPeter Maydell (1ULL << ARM_FEATURE_GENERIC_TIMER); 871585df85eSPeter Maydell 872585df85eSPeter Maydell /* We set up a small vcpu to extract host registers */ 873585df85eSPeter Maydell 874585df85eSPeter Maydell if (hv_vcpu_create(&fd, &exit, NULL) != HV_SUCCESS) { 875585df85eSPeter Maydell return false; 876585df85eSPeter Maydell } 877585df85eSPeter Maydell 878585df85eSPeter Maydell for (i = 0; i < ARRAY_SIZE(regs); i++) { 879585df85eSPeter Maydell r |= hv_vcpu_get_sys_reg(fd, regs[i].reg, regs[i].val); 880585df85eSPeter Maydell } 881585df85eSPeter Maydell r |= hv_vcpu_get_sys_reg(fd, HV_SYS_REG_MIDR_EL1, &ahcf->midr); 882585df85eSPeter Maydell r |= hv_vcpu_destroy(fd); 883585df85eSPeter Maydell 884585df85eSPeter Maydell ahcf->isar = host_isar; 885585df85eSPeter Maydell 886585df85eSPeter Maydell /* 887585df85eSPeter Maydell * A scratch vCPU returns SCTLR 0, so let's fill our default with the M1 888585df85eSPeter Maydell * boot SCTLR from https://github.com/AsahiLinux/m1n1/issues/97 889585df85eSPeter Maydell */ 890585df85eSPeter Maydell ahcf->reset_sctlr = 0x30100180; 891585df85eSPeter Maydell /* 892585df85eSPeter Maydell * SPAN is disabled by default when SCTLR.SPAN=1. To improve compatibility, 893585df85eSPeter Maydell * let's disable it on boot and then allow guest software to turn it on by 894585df85eSPeter Maydell * setting it to 0. 895585df85eSPeter Maydell */ 896585df85eSPeter Maydell ahcf->reset_sctlr |= 0x00800000; 897585df85eSPeter Maydell 898585df85eSPeter Maydell /* Make sure we don't advertise AArch32 support for EL0/EL1 */ 899585df85eSPeter Maydell if ((host_isar.id_aa64pfr0 & 0xff) != 0x11) { 900585df85eSPeter Maydell return false; 901585df85eSPeter Maydell } 902585df85eSPeter Maydell 903585df85eSPeter Maydell return r == HV_SUCCESS; 904585df85eSPeter Maydell } 905585df85eSPeter Maydell 906585df85eSPeter Maydell void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu) 907585df85eSPeter Maydell { 908585df85eSPeter Maydell if (!arm_host_cpu_features.dtb_compatible) { 909585df85eSPeter Maydell if (!hvf_enabled() || 910585df85eSPeter Maydell !hvf_arm_get_host_cpu_features(&arm_host_cpu_features)) { 911585df85eSPeter Maydell /* 912585df85eSPeter Maydell * We can't report this error yet, so flag that we need to 913585df85eSPeter Maydell * in arm_cpu_realizefn(). 914585df85eSPeter Maydell */ 915585df85eSPeter Maydell cpu->host_cpu_probe_failed = true; 916585df85eSPeter Maydell return; 917585df85eSPeter Maydell } 918585df85eSPeter Maydell } 919585df85eSPeter Maydell 920585df85eSPeter Maydell cpu->dtb_compatible = arm_host_cpu_features.dtb_compatible; 921585df85eSPeter Maydell cpu->isar = arm_host_cpu_features.isar; 922585df85eSPeter Maydell cpu->env.features = arm_host_cpu_features.features; 923585df85eSPeter Maydell cpu->midr = arm_host_cpu_features.midr; 924585df85eSPeter Maydell cpu->reset_sctlr = arm_host_cpu_features.reset_sctlr; 925585df85eSPeter Maydell } 926585df85eSPeter Maydell 927a1477da3SAlexander Graf void hvf_arch_vcpu_destroy(CPUState *cpu) 928a1477da3SAlexander Graf { 929a1477da3SAlexander Graf } 930a1477da3SAlexander Graf 931a1477da3SAlexander Graf int hvf_arch_init_vcpu(CPUState *cpu) 932a1477da3SAlexander Graf { 933a1477da3SAlexander Graf ARMCPU *arm_cpu = ARM_CPU(cpu); 934a1477da3SAlexander Graf CPUARMState *env = &arm_cpu->env; 935a1477da3SAlexander Graf uint32_t sregs_match_len = ARRAY_SIZE(hvf_sreg_match); 936a1477da3SAlexander Graf uint32_t sregs_cnt = 0; 937a1477da3SAlexander Graf uint64_t pfr; 938a1477da3SAlexander Graf hv_return_t ret; 939a1477da3SAlexander Graf int i; 940a1477da3SAlexander Graf 94153221552SRichard Henderson env->aarch64 = true; 942a1477da3SAlexander Graf asm volatile("mrs %0, cntfrq_el0" : "=r"(arm_cpu->gt_cntfrq_hz)); 943a1477da3SAlexander Graf 944a1477da3SAlexander Graf /* Allocate enough space for our sysreg sync */ 945a1477da3SAlexander Graf arm_cpu->cpreg_indexes = g_renew(uint64_t, arm_cpu->cpreg_indexes, 946a1477da3SAlexander Graf sregs_match_len); 947a1477da3SAlexander Graf arm_cpu->cpreg_values = g_renew(uint64_t, arm_cpu->cpreg_values, 948a1477da3SAlexander Graf sregs_match_len); 949a1477da3SAlexander Graf arm_cpu->cpreg_vmstate_indexes = g_renew(uint64_t, 950a1477da3SAlexander Graf arm_cpu->cpreg_vmstate_indexes, 951a1477da3SAlexander Graf sregs_match_len); 952a1477da3SAlexander Graf arm_cpu->cpreg_vmstate_values = g_renew(uint64_t, 953a1477da3SAlexander Graf arm_cpu->cpreg_vmstate_values, 954a1477da3SAlexander Graf sregs_match_len); 955a1477da3SAlexander Graf 956a1477da3SAlexander Graf memset(arm_cpu->cpreg_values, 0, sregs_match_len * sizeof(uint64_t)); 957a1477da3SAlexander Graf 958a1477da3SAlexander Graf /* Populate cp list for all known sysregs */ 959a1477da3SAlexander Graf for (i = 0; i < sregs_match_len; i++) { 960a1477da3SAlexander Graf const ARMCPRegInfo *ri; 961a1477da3SAlexander Graf uint32_t key = hvf_sreg_match[i].key; 962a1477da3SAlexander Graf 963a1477da3SAlexander Graf ri = get_arm_cp_reginfo(arm_cpu->cp_regs, key); 964a1477da3SAlexander Graf if (ri) { 965a1477da3SAlexander Graf assert(!(ri->type & ARM_CP_NO_RAW)); 966a1477da3SAlexander Graf hvf_sreg_match[i].cp_idx = sregs_cnt; 967a1477da3SAlexander Graf arm_cpu->cpreg_indexes[sregs_cnt++] = cpreg_to_kvm_id(key); 968a1477da3SAlexander Graf } else { 969a1477da3SAlexander Graf hvf_sreg_match[i].cp_idx = -1; 970a1477da3SAlexander Graf } 971a1477da3SAlexander Graf } 972a1477da3SAlexander Graf arm_cpu->cpreg_array_len = sregs_cnt; 973a1477da3SAlexander Graf arm_cpu->cpreg_vmstate_array_len = sregs_cnt; 974a1477da3SAlexander Graf 975a1477da3SAlexander Graf assert(write_cpustate_to_list(arm_cpu, false)); 976a1477da3SAlexander Graf 977a1477da3SAlexander Graf /* Set CP_NO_RAW system registers on init */ 9783b295bcbSPhilippe Mathieu-Daudé ret = hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_MIDR_EL1, 979a1477da3SAlexander Graf arm_cpu->midr); 980a1477da3SAlexander Graf assert_hvf_ok(ret); 981a1477da3SAlexander Graf 9823b295bcbSPhilippe Mathieu-Daudé ret = hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_MPIDR_EL1, 983a1477da3SAlexander Graf arm_cpu->mp_affinity); 984a1477da3SAlexander Graf assert_hvf_ok(ret); 985a1477da3SAlexander Graf 9863b295bcbSPhilippe Mathieu-Daudé ret = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64PFR0_EL1, &pfr); 987a1477da3SAlexander Graf assert_hvf_ok(ret); 988a1477da3SAlexander Graf pfr |= env->gicv3state ? (1 << 24) : 0; 9893b295bcbSPhilippe Mathieu-Daudé ret = hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64PFR0_EL1, pfr); 990a1477da3SAlexander Graf assert_hvf_ok(ret); 991a1477da3SAlexander Graf 992a1477da3SAlexander Graf /* We're limited to underlying hardware caps, override internal versions */ 9933b295bcbSPhilippe Mathieu-Daudé ret = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64MMFR0_EL1, 994a1477da3SAlexander Graf &arm_cpu->isar.id_aa64mmfr0); 995a1477da3SAlexander Graf assert_hvf_ok(ret); 996a1477da3SAlexander Graf 997a1477da3SAlexander Graf return 0; 998a1477da3SAlexander Graf } 999a1477da3SAlexander Graf 1000a1477da3SAlexander Graf void hvf_kick_vcpu_thread(CPUState *cpu) 1001a1477da3SAlexander Graf { 1002219c101fSPeter Collingbourne cpus_kick_thread(cpu); 10033b295bcbSPhilippe Mathieu-Daudé hv_vcpus_exit(&cpu->accel->fd, 1); 1004a1477da3SAlexander Graf } 1005a1477da3SAlexander Graf 1006a1477da3SAlexander Graf static void hvf_raise_exception(CPUState *cpu, uint32_t excp, 1007a1477da3SAlexander Graf uint32_t syndrome) 1008a1477da3SAlexander Graf { 1009a1477da3SAlexander Graf ARMCPU *arm_cpu = ARM_CPU(cpu); 1010a1477da3SAlexander Graf CPUARMState *env = &arm_cpu->env; 1011a1477da3SAlexander Graf 1012a1477da3SAlexander Graf cpu->exception_index = excp; 1013a1477da3SAlexander Graf env->exception.target_el = 1; 1014a1477da3SAlexander Graf env->exception.syndrome = syndrome; 1015a1477da3SAlexander Graf 1016a1477da3SAlexander Graf arm_cpu_do_interrupt(cpu); 1017a1477da3SAlexander Graf } 1018a1477da3SAlexander Graf 10192c9c0bf9SAlexander Graf static void hvf_psci_cpu_off(ARMCPU *arm_cpu) 10202c9c0bf9SAlexander Graf { 1021c4380f7bSRichard Henderson int32_t ret = arm_set_cpu_off(arm_cpu_mp_affinity(arm_cpu)); 10222c9c0bf9SAlexander Graf assert(ret == QEMU_ARM_POWERCTL_RET_SUCCESS); 10232c9c0bf9SAlexander Graf } 10242c9c0bf9SAlexander Graf 10252c9c0bf9SAlexander Graf /* 10262c9c0bf9SAlexander Graf * Handle a PSCI call. 10272c9c0bf9SAlexander Graf * 10282c9c0bf9SAlexander Graf * Returns 0 on success 10292c9c0bf9SAlexander Graf * -1 when the PSCI call is unknown, 10302c9c0bf9SAlexander Graf */ 10312c9c0bf9SAlexander Graf static bool hvf_handle_psci_call(CPUState *cpu) 10322c9c0bf9SAlexander Graf { 10332c9c0bf9SAlexander Graf ARMCPU *arm_cpu = ARM_CPU(cpu); 10342c9c0bf9SAlexander Graf CPUARMState *env = &arm_cpu->env; 10352c9c0bf9SAlexander Graf uint64_t param[4] = { 10362c9c0bf9SAlexander Graf env->xregs[0], 10372c9c0bf9SAlexander Graf env->xregs[1], 10382c9c0bf9SAlexander Graf env->xregs[2], 10392c9c0bf9SAlexander Graf env->xregs[3] 10402c9c0bf9SAlexander Graf }; 10412c9c0bf9SAlexander Graf uint64_t context_id, mpidr; 10422c9c0bf9SAlexander Graf bool target_aarch64 = true; 10432c9c0bf9SAlexander Graf CPUState *target_cpu_state; 10442c9c0bf9SAlexander Graf ARMCPU *target_cpu; 10452c9c0bf9SAlexander Graf target_ulong entry; 10462c9c0bf9SAlexander Graf int target_el = 1; 10472c9c0bf9SAlexander Graf int32_t ret = 0; 10482c9c0bf9SAlexander Graf 10492c9c0bf9SAlexander Graf trace_hvf_psci_call(param[0], param[1], param[2], param[3], 1050c4380f7bSRichard Henderson arm_cpu_mp_affinity(arm_cpu)); 10512c9c0bf9SAlexander Graf 10522c9c0bf9SAlexander Graf switch (param[0]) { 10532c9c0bf9SAlexander Graf case QEMU_PSCI_0_2_FN_PSCI_VERSION: 10540dc71c70SAkihiko Odaki ret = QEMU_PSCI_VERSION_1_1; 10552c9c0bf9SAlexander Graf break; 10562c9c0bf9SAlexander Graf case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE: 10572c9c0bf9SAlexander Graf ret = QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED; /* No trusted OS */ 10582c9c0bf9SAlexander Graf break; 10592c9c0bf9SAlexander Graf case QEMU_PSCI_0_2_FN_AFFINITY_INFO: 10602c9c0bf9SAlexander Graf case QEMU_PSCI_0_2_FN64_AFFINITY_INFO: 10612c9c0bf9SAlexander Graf mpidr = param[1]; 10622c9c0bf9SAlexander Graf 10632c9c0bf9SAlexander Graf switch (param[2]) { 10642c9c0bf9SAlexander Graf case 0: 10652c9c0bf9SAlexander Graf target_cpu_state = arm_get_cpu_by_id(mpidr); 10662c9c0bf9SAlexander Graf if (!target_cpu_state) { 10672c9c0bf9SAlexander Graf ret = QEMU_PSCI_RET_INVALID_PARAMS; 10682c9c0bf9SAlexander Graf break; 10692c9c0bf9SAlexander Graf } 10702c9c0bf9SAlexander Graf target_cpu = ARM_CPU(target_cpu_state); 10712c9c0bf9SAlexander Graf 10722c9c0bf9SAlexander Graf ret = target_cpu->power_state; 10732c9c0bf9SAlexander Graf break; 10742c9c0bf9SAlexander Graf default: 10752c9c0bf9SAlexander Graf /* Everything above affinity level 0 is always on. */ 10762c9c0bf9SAlexander Graf ret = 0; 10772c9c0bf9SAlexander Graf } 10782c9c0bf9SAlexander Graf break; 10792c9c0bf9SAlexander Graf case QEMU_PSCI_0_2_FN_SYSTEM_RESET: 10802c9c0bf9SAlexander Graf qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 10812c9c0bf9SAlexander Graf /* 10822c9c0bf9SAlexander Graf * QEMU reset and shutdown are async requests, but PSCI 10832c9c0bf9SAlexander Graf * mandates that we never return from the reset/shutdown 10842c9c0bf9SAlexander Graf * call, so power the CPU off now so it doesn't execute 10852c9c0bf9SAlexander Graf * anything further. 10862c9c0bf9SAlexander Graf */ 10872c9c0bf9SAlexander Graf hvf_psci_cpu_off(arm_cpu); 10882c9c0bf9SAlexander Graf break; 10892c9c0bf9SAlexander Graf case QEMU_PSCI_0_2_FN_SYSTEM_OFF: 10902c9c0bf9SAlexander Graf qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 10912c9c0bf9SAlexander Graf hvf_psci_cpu_off(arm_cpu); 10922c9c0bf9SAlexander Graf break; 10932c9c0bf9SAlexander Graf case QEMU_PSCI_0_1_FN_CPU_ON: 10942c9c0bf9SAlexander Graf case QEMU_PSCI_0_2_FN_CPU_ON: 10952c9c0bf9SAlexander Graf case QEMU_PSCI_0_2_FN64_CPU_ON: 10962c9c0bf9SAlexander Graf mpidr = param[1]; 10972c9c0bf9SAlexander Graf entry = param[2]; 10982c9c0bf9SAlexander Graf context_id = param[3]; 10992c9c0bf9SAlexander Graf ret = arm_set_cpu_on(mpidr, entry, context_id, 11002c9c0bf9SAlexander Graf target_el, target_aarch64); 11012c9c0bf9SAlexander Graf break; 11022c9c0bf9SAlexander Graf case QEMU_PSCI_0_1_FN_CPU_OFF: 11032c9c0bf9SAlexander Graf case QEMU_PSCI_0_2_FN_CPU_OFF: 11042c9c0bf9SAlexander Graf hvf_psci_cpu_off(arm_cpu); 11052c9c0bf9SAlexander Graf break; 11062c9c0bf9SAlexander Graf case QEMU_PSCI_0_1_FN_CPU_SUSPEND: 11072c9c0bf9SAlexander Graf case QEMU_PSCI_0_2_FN_CPU_SUSPEND: 11082c9c0bf9SAlexander Graf case QEMU_PSCI_0_2_FN64_CPU_SUSPEND: 11092c9c0bf9SAlexander Graf /* Affinity levels are not supported in QEMU */ 11102c9c0bf9SAlexander Graf if (param[1] & 0xfffe0000) { 11112c9c0bf9SAlexander Graf ret = QEMU_PSCI_RET_INVALID_PARAMS; 11122c9c0bf9SAlexander Graf break; 11132c9c0bf9SAlexander Graf } 11142c9c0bf9SAlexander Graf /* Powerdown is not supported, we always go into WFI */ 11152c9c0bf9SAlexander Graf env->xregs[0] = 0; 11162c9c0bf9SAlexander Graf hvf_wfi(cpu); 11172c9c0bf9SAlexander Graf break; 11182c9c0bf9SAlexander Graf case QEMU_PSCI_0_1_FN_MIGRATE: 11192c9c0bf9SAlexander Graf case QEMU_PSCI_0_2_FN_MIGRATE: 11202c9c0bf9SAlexander Graf ret = QEMU_PSCI_RET_NOT_SUPPORTED; 11212c9c0bf9SAlexander Graf break; 11220dc71c70SAkihiko Odaki case QEMU_PSCI_1_0_FN_PSCI_FEATURES: 11230dc71c70SAkihiko Odaki switch (param[1]) { 11240dc71c70SAkihiko Odaki case QEMU_PSCI_0_2_FN_PSCI_VERSION: 11250dc71c70SAkihiko Odaki case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE: 11260dc71c70SAkihiko Odaki case QEMU_PSCI_0_2_FN_AFFINITY_INFO: 11270dc71c70SAkihiko Odaki case QEMU_PSCI_0_2_FN64_AFFINITY_INFO: 11280dc71c70SAkihiko Odaki case QEMU_PSCI_0_2_FN_SYSTEM_RESET: 11290dc71c70SAkihiko Odaki case QEMU_PSCI_0_2_FN_SYSTEM_OFF: 11300dc71c70SAkihiko Odaki case QEMU_PSCI_0_1_FN_CPU_ON: 11310dc71c70SAkihiko Odaki case QEMU_PSCI_0_2_FN_CPU_ON: 11320dc71c70SAkihiko Odaki case QEMU_PSCI_0_2_FN64_CPU_ON: 11330dc71c70SAkihiko Odaki case QEMU_PSCI_0_1_FN_CPU_OFF: 11340dc71c70SAkihiko Odaki case QEMU_PSCI_0_2_FN_CPU_OFF: 11350dc71c70SAkihiko Odaki case QEMU_PSCI_0_1_FN_CPU_SUSPEND: 11360dc71c70SAkihiko Odaki case QEMU_PSCI_0_2_FN_CPU_SUSPEND: 11370dc71c70SAkihiko Odaki case QEMU_PSCI_0_2_FN64_CPU_SUSPEND: 11380dc71c70SAkihiko Odaki case QEMU_PSCI_1_0_FN_PSCI_FEATURES: 11390dc71c70SAkihiko Odaki ret = 0; 11400dc71c70SAkihiko Odaki break; 11410dc71c70SAkihiko Odaki case QEMU_PSCI_0_1_FN_MIGRATE: 11420dc71c70SAkihiko Odaki case QEMU_PSCI_0_2_FN_MIGRATE: 11430dc71c70SAkihiko Odaki default: 11440dc71c70SAkihiko Odaki ret = QEMU_PSCI_RET_NOT_SUPPORTED; 11450dc71c70SAkihiko Odaki } 11460dc71c70SAkihiko Odaki break; 11472c9c0bf9SAlexander Graf default: 11482c9c0bf9SAlexander Graf return false; 11492c9c0bf9SAlexander Graf } 11502c9c0bf9SAlexander Graf 11512c9c0bf9SAlexander Graf env->xregs[0] = ret; 11522c9c0bf9SAlexander Graf return true; 11532c9c0bf9SAlexander Graf } 11542c9c0bf9SAlexander Graf 11557f6c295cSAlexander Graf static bool is_id_sysreg(uint32_t reg) 11567f6c295cSAlexander Graf { 11577f6c295cSAlexander Graf return SYSREG_OP0(reg) == 3 && 11587f6c295cSAlexander Graf SYSREG_OP1(reg) == 0 && 11597f6c295cSAlexander Graf SYSREG_CRN(reg) == 0 && 11607f6c295cSAlexander Graf SYSREG_CRM(reg) >= 1 && 11617f6c295cSAlexander Graf SYSREG_CRM(reg) < 8; 11627f6c295cSAlexander Graf } 11637f6c295cSAlexander Graf 1164a2260983SAlexander Graf static uint32_t hvf_reg2cp_reg(uint32_t reg) 1165a2260983SAlexander Graf { 1166a2260983SAlexander Graf return ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, 1167a2260983SAlexander Graf (reg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK, 1168a2260983SAlexander Graf (reg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK, 1169a2260983SAlexander Graf (reg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK, 1170a2260983SAlexander Graf (reg >> SYSREG_OP1_SHIFT) & SYSREG_OP1_MASK, 1171a2260983SAlexander Graf (reg >> SYSREG_OP2_SHIFT) & SYSREG_OP2_MASK); 1172a2260983SAlexander Graf } 1173a2260983SAlexander Graf 1174a2260983SAlexander Graf static bool hvf_sysreg_read_cp(CPUState *cpu, uint32_t reg, uint64_t *val) 1175a2260983SAlexander Graf { 1176a2260983SAlexander Graf ARMCPU *arm_cpu = ARM_CPU(cpu); 1177a2260983SAlexander Graf CPUARMState *env = &arm_cpu->env; 1178a2260983SAlexander Graf const ARMCPRegInfo *ri; 1179a2260983SAlexander Graf 1180a2260983SAlexander Graf ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg)); 1181a2260983SAlexander Graf if (ri) { 1182a2260983SAlexander Graf if (ri->accessfn) { 1183a2260983SAlexander Graf if (ri->accessfn(env, ri, true) != CP_ACCESS_OK) { 1184a2260983SAlexander Graf return false; 1185a2260983SAlexander Graf } 1186a2260983SAlexander Graf } 1187a2260983SAlexander Graf if (ri->type & ARM_CP_CONST) { 1188a2260983SAlexander Graf *val = ri->resetvalue; 1189a2260983SAlexander Graf } else if (ri->readfn) { 1190a2260983SAlexander Graf *val = ri->readfn(env, ri); 1191a2260983SAlexander Graf } else { 1192a2260983SAlexander Graf *val = CPREG_FIELD64(env, ri); 1193a2260983SAlexander Graf } 1194a2260983SAlexander Graf trace_hvf_vgic_read(ri->name, *val); 1195a2260983SAlexander Graf return true; 1196a2260983SAlexander Graf } 1197a2260983SAlexander Graf 1198a2260983SAlexander Graf return false; 1199a2260983SAlexander Graf } 1200a2260983SAlexander Graf 1201a1477da3SAlexander Graf static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt) 1202a1477da3SAlexander Graf { 1203a1477da3SAlexander Graf ARMCPU *arm_cpu = ARM_CPU(cpu); 1204a1477da3SAlexander Graf CPUARMState *env = &arm_cpu->env; 1205a1477da3SAlexander Graf uint64_t val = 0; 1206a1477da3SAlexander Graf 1207a1477da3SAlexander Graf switch (reg) { 1208a1477da3SAlexander Graf case SYSREG_CNTPCT_EL0: 1209a1477da3SAlexander Graf val = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / 1210a1477da3SAlexander Graf gt_cntfrq_period_ns(arm_cpu); 1211a1477da3SAlexander Graf break; 1212dd43ac07SAlexander Graf case SYSREG_PMCR_EL0: 1213dd43ac07SAlexander Graf val = env->cp15.c9_pmcr; 1214dd43ac07SAlexander Graf break; 1215dd43ac07SAlexander Graf case SYSREG_PMCCNTR_EL0: 1216dd43ac07SAlexander Graf pmu_op_start(env); 1217dd43ac07SAlexander Graf val = env->cp15.c15_ccnt; 1218dd43ac07SAlexander Graf pmu_op_finish(env); 1219dd43ac07SAlexander Graf break; 1220dd43ac07SAlexander Graf case SYSREG_PMCNTENCLR_EL0: 1221dd43ac07SAlexander Graf val = env->cp15.c9_pmcnten; 1222dd43ac07SAlexander Graf break; 1223dd43ac07SAlexander Graf case SYSREG_PMOVSCLR_EL0: 1224dd43ac07SAlexander Graf val = env->cp15.c9_pmovsr; 1225dd43ac07SAlexander Graf break; 1226dd43ac07SAlexander Graf case SYSREG_PMSELR_EL0: 1227dd43ac07SAlexander Graf val = env->cp15.c9_pmselr; 1228dd43ac07SAlexander Graf break; 1229dd43ac07SAlexander Graf case SYSREG_PMINTENCLR_EL1: 1230dd43ac07SAlexander Graf val = env->cp15.c9_pminten; 1231dd43ac07SAlexander Graf break; 1232dd43ac07SAlexander Graf case SYSREG_PMCCFILTR_EL0: 1233dd43ac07SAlexander Graf val = env->cp15.pmccfiltr_el0; 1234dd43ac07SAlexander Graf break; 1235dd43ac07SAlexander Graf case SYSREG_PMCNTENSET_EL0: 1236dd43ac07SAlexander Graf val = env->cp15.c9_pmcnten; 1237dd43ac07SAlexander Graf break; 1238dd43ac07SAlexander Graf case SYSREG_PMUSERENR_EL0: 1239dd43ac07SAlexander Graf val = env->cp15.c9_pmuserenr; 1240dd43ac07SAlexander Graf break; 1241dd43ac07SAlexander Graf case SYSREG_PMCEID0_EL0: 1242dd43ac07SAlexander Graf case SYSREG_PMCEID1_EL0: 1243dd43ac07SAlexander Graf /* We can't really count anything yet, declare all events invalid */ 1244dd43ac07SAlexander Graf val = 0; 1245dd43ac07SAlexander Graf break; 1246a1477da3SAlexander Graf case SYSREG_OSLSR_EL1: 1247a1477da3SAlexander Graf val = env->cp15.oslsr_el1; 1248a1477da3SAlexander Graf break; 1249a1477da3SAlexander Graf case SYSREG_OSDLR_EL1: 1250a1477da3SAlexander Graf /* Dummy register */ 1251a1477da3SAlexander Graf break; 1252a2260983SAlexander Graf case SYSREG_ICC_AP0R0_EL1: 1253a2260983SAlexander Graf case SYSREG_ICC_AP0R1_EL1: 1254a2260983SAlexander Graf case SYSREG_ICC_AP0R2_EL1: 1255a2260983SAlexander Graf case SYSREG_ICC_AP0R3_EL1: 1256a2260983SAlexander Graf case SYSREG_ICC_AP1R0_EL1: 1257a2260983SAlexander Graf case SYSREG_ICC_AP1R1_EL1: 1258a2260983SAlexander Graf case SYSREG_ICC_AP1R2_EL1: 1259a2260983SAlexander Graf case SYSREG_ICC_AP1R3_EL1: 1260a2260983SAlexander Graf case SYSREG_ICC_ASGI1R_EL1: 1261a2260983SAlexander Graf case SYSREG_ICC_BPR0_EL1: 1262a2260983SAlexander Graf case SYSREG_ICC_BPR1_EL1: 1263a2260983SAlexander Graf case SYSREG_ICC_DIR_EL1: 1264a2260983SAlexander Graf case SYSREG_ICC_EOIR0_EL1: 1265a2260983SAlexander Graf case SYSREG_ICC_EOIR1_EL1: 1266a2260983SAlexander Graf case SYSREG_ICC_HPPIR0_EL1: 1267a2260983SAlexander Graf case SYSREG_ICC_HPPIR1_EL1: 1268a2260983SAlexander Graf case SYSREG_ICC_IAR0_EL1: 1269a2260983SAlexander Graf case SYSREG_ICC_IAR1_EL1: 1270a2260983SAlexander Graf case SYSREG_ICC_IGRPEN0_EL1: 1271a2260983SAlexander Graf case SYSREG_ICC_IGRPEN1_EL1: 1272a2260983SAlexander Graf case SYSREG_ICC_PMR_EL1: 1273a2260983SAlexander Graf case SYSREG_ICC_SGI0R_EL1: 1274a2260983SAlexander Graf case SYSREG_ICC_SGI1R_EL1: 1275a2260983SAlexander Graf case SYSREG_ICC_SRE_EL1: 1276a2260983SAlexander Graf case SYSREG_ICC_CTLR_EL1: 1277a2260983SAlexander Graf /* Call the TCG sysreg handler. This is only safe for GICv3 regs. */ 1278a2260983SAlexander Graf if (!hvf_sysreg_read_cp(cpu, reg, &val)) { 1279a2260983SAlexander Graf hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); 1280a2260983SAlexander Graf } 1281a2260983SAlexander Graf break; 1282ce799a04SFrancesco Cagnin case SYSREG_DBGBVR0_EL1: 1283ce799a04SFrancesco Cagnin case SYSREG_DBGBVR1_EL1: 1284ce799a04SFrancesco Cagnin case SYSREG_DBGBVR2_EL1: 1285ce799a04SFrancesco Cagnin case SYSREG_DBGBVR3_EL1: 1286ce799a04SFrancesco Cagnin case SYSREG_DBGBVR4_EL1: 1287ce799a04SFrancesco Cagnin case SYSREG_DBGBVR5_EL1: 1288ce799a04SFrancesco Cagnin case SYSREG_DBGBVR6_EL1: 1289ce799a04SFrancesco Cagnin case SYSREG_DBGBVR7_EL1: 1290ce799a04SFrancesco Cagnin case SYSREG_DBGBVR8_EL1: 1291ce799a04SFrancesco Cagnin case SYSREG_DBGBVR9_EL1: 1292ce799a04SFrancesco Cagnin case SYSREG_DBGBVR10_EL1: 1293ce799a04SFrancesco Cagnin case SYSREG_DBGBVR11_EL1: 1294ce799a04SFrancesco Cagnin case SYSREG_DBGBVR12_EL1: 1295ce799a04SFrancesco Cagnin case SYSREG_DBGBVR13_EL1: 1296ce799a04SFrancesco Cagnin case SYSREG_DBGBVR14_EL1: 1297ce799a04SFrancesco Cagnin case SYSREG_DBGBVR15_EL1: 1298ce799a04SFrancesco Cagnin val = env->cp15.dbgbvr[SYSREG_CRM(reg)]; 1299ce799a04SFrancesco Cagnin break; 1300ce799a04SFrancesco Cagnin case SYSREG_DBGBCR0_EL1: 1301ce799a04SFrancesco Cagnin case SYSREG_DBGBCR1_EL1: 1302ce799a04SFrancesco Cagnin case SYSREG_DBGBCR2_EL1: 1303ce799a04SFrancesco Cagnin case SYSREG_DBGBCR3_EL1: 1304ce799a04SFrancesco Cagnin case SYSREG_DBGBCR4_EL1: 1305ce799a04SFrancesco Cagnin case SYSREG_DBGBCR5_EL1: 1306ce799a04SFrancesco Cagnin case SYSREG_DBGBCR6_EL1: 1307ce799a04SFrancesco Cagnin case SYSREG_DBGBCR7_EL1: 1308ce799a04SFrancesco Cagnin case SYSREG_DBGBCR8_EL1: 1309ce799a04SFrancesco Cagnin case SYSREG_DBGBCR9_EL1: 1310ce799a04SFrancesco Cagnin case SYSREG_DBGBCR10_EL1: 1311ce799a04SFrancesco Cagnin case SYSREG_DBGBCR11_EL1: 1312ce799a04SFrancesco Cagnin case SYSREG_DBGBCR12_EL1: 1313ce799a04SFrancesco Cagnin case SYSREG_DBGBCR13_EL1: 1314ce799a04SFrancesco Cagnin case SYSREG_DBGBCR14_EL1: 1315ce799a04SFrancesco Cagnin case SYSREG_DBGBCR15_EL1: 1316ce799a04SFrancesco Cagnin val = env->cp15.dbgbcr[SYSREG_CRM(reg)]; 1317ce799a04SFrancesco Cagnin break; 1318ce799a04SFrancesco Cagnin case SYSREG_DBGWVR0_EL1: 1319ce799a04SFrancesco Cagnin case SYSREG_DBGWVR1_EL1: 1320ce799a04SFrancesco Cagnin case SYSREG_DBGWVR2_EL1: 1321ce799a04SFrancesco Cagnin case SYSREG_DBGWVR3_EL1: 1322ce799a04SFrancesco Cagnin case SYSREG_DBGWVR4_EL1: 1323ce799a04SFrancesco Cagnin case SYSREG_DBGWVR5_EL1: 1324ce799a04SFrancesco Cagnin case SYSREG_DBGWVR6_EL1: 1325ce799a04SFrancesco Cagnin case SYSREG_DBGWVR7_EL1: 1326ce799a04SFrancesco Cagnin case SYSREG_DBGWVR8_EL1: 1327ce799a04SFrancesco Cagnin case SYSREG_DBGWVR9_EL1: 1328ce799a04SFrancesco Cagnin case SYSREG_DBGWVR10_EL1: 1329ce799a04SFrancesco Cagnin case SYSREG_DBGWVR11_EL1: 1330ce799a04SFrancesco Cagnin case SYSREG_DBGWVR12_EL1: 1331ce799a04SFrancesco Cagnin case SYSREG_DBGWVR13_EL1: 1332ce799a04SFrancesco Cagnin case SYSREG_DBGWVR14_EL1: 1333ce799a04SFrancesco Cagnin case SYSREG_DBGWVR15_EL1: 1334ce799a04SFrancesco Cagnin val = env->cp15.dbgwvr[SYSREG_CRM(reg)]; 1335ce799a04SFrancesco Cagnin break; 1336ce799a04SFrancesco Cagnin case SYSREG_DBGWCR0_EL1: 1337ce799a04SFrancesco Cagnin case SYSREG_DBGWCR1_EL1: 1338ce799a04SFrancesco Cagnin case SYSREG_DBGWCR2_EL1: 1339ce799a04SFrancesco Cagnin case SYSREG_DBGWCR3_EL1: 1340ce799a04SFrancesco Cagnin case SYSREG_DBGWCR4_EL1: 1341ce799a04SFrancesco Cagnin case SYSREG_DBGWCR5_EL1: 1342ce799a04SFrancesco Cagnin case SYSREG_DBGWCR6_EL1: 1343ce799a04SFrancesco Cagnin case SYSREG_DBGWCR7_EL1: 1344ce799a04SFrancesco Cagnin case SYSREG_DBGWCR8_EL1: 1345ce799a04SFrancesco Cagnin case SYSREG_DBGWCR9_EL1: 1346ce799a04SFrancesco Cagnin case SYSREG_DBGWCR10_EL1: 1347ce799a04SFrancesco Cagnin case SYSREG_DBGWCR11_EL1: 1348ce799a04SFrancesco Cagnin case SYSREG_DBGWCR12_EL1: 1349ce799a04SFrancesco Cagnin case SYSREG_DBGWCR13_EL1: 1350ce799a04SFrancesco Cagnin case SYSREG_DBGWCR14_EL1: 1351ce799a04SFrancesco Cagnin case SYSREG_DBGWCR15_EL1: 1352ce799a04SFrancesco Cagnin val = env->cp15.dbgwcr[SYSREG_CRM(reg)]; 1353ce799a04SFrancesco Cagnin break; 1354a1477da3SAlexander Graf default: 13557f6c295cSAlexander Graf if (is_id_sysreg(reg)) { 13567f6c295cSAlexander Graf /* ID system registers read as RES0 */ 13577f6c295cSAlexander Graf val = 0; 13587f6c295cSAlexander Graf break; 13597f6c295cSAlexander Graf } 1360a1477da3SAlexander Graf cpu_synchronize_state(cpu); 1361a1477da3SAlexander Graf trace_hvf_unhandled_sysreg_read(env->pc, reg, 1362ad99f64fSAlexander Graf SYSREG_OP0(reg), 1363ad99f64fSAlexander Graf SYSREG_OP1(reg), 1364ad99f64fSAlexander Graf SYSREG_CRN(reg), 1365ad99f64fSAlexander Graf SYSREG_CRM(reg), 1366ad99f64fSAlexander Graf SYSREG_OP2(reg)); 1367a1477da3SAlexander Graf hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); 1368a1477da3SAlexander Graf return 1; 1369a1477da3SAlexander Graf } 1370a1477da3SAlexander Graf 1371a1477da3SAlexander Graf trace_hvf_sysreg_read(reg, 1372ad99f64fSAlexander Graf SYSREG_OP0(reg), 1373ad99f64fSAlexander Graf SYSREG_OP1(reg), 1374ad99f64fSAlexander Graf SYSREG_CRN(reg), 1375ad99f64fSAlexander Graf SYSREG_CRM(reg), 1376ad99f64fSAlexander Graf SYSREG_OP2(reg), 1377a1477da3SAlexander Graf val); 1378a1477da3SAlexander Graf hvf_set_reg(cpu, rt, val); 1379a1477da3SAlexander Graf 1380a1477da3SAlexander Graf return 0; 1381a1477da3SAlexander Graf } 1382a1477da3SAlexander Graf 1383dd43ac07SAlexander Graf static void pmu_update_irq(CPUARMState *env) 1384dd43ac07SAlexander Graf { 1385dd43ac07SAlexander Graf ARMCPU *cpu = env_archcpu(env); 1386dd43ac07SAlexander Graf qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) && 1387dd43ac07SAlexander Graf (env->cp15.c9_pminten & env->cp15.c9_pmovsr)); 1388dd43ac07SAlexander Graf } 1389dd43ac07SAlexander Graf 1390dd43ac07SAlexander Graf static bool pmu_event_supported(uint16_t number) 1391dd43ac07SAlexander Graf { 1392dd43ac07SAlexander Graf return false; 1393dd43ac07SAlexander Graf } 1394dd43ac07SAlexander Graf 1395dd43ac07SAlexander Graf /* Returns true if the counter (pass 31 for PMCCNTR) should count events using 1396dd43ac07SAlexander Graf * the current EL, security state, and register configuration. 1397dd43ac07SAlexander Graf */ 1398dd43ac07SAlexander Graf static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter) 1399dd43ac07SAlexander Graf { 1400dd43ac07SAlexander Graf uint64_t filter; 1401dd43ac07SAlexander Graf bool enabled, filtered = true; 1402dd43ac07SAlexander Graf int el = arm_current_el(env); 1403dd43ac07SAlexander Graf 1404dd43ac07SAlexander Graf enabled = (env->cp15.c9_pmcr & PMCRE) && 1405dd43ac07SAlexander Graf (env->cp15.c9_pmcnten & (1 << counter)); 1406dd43ac07SAlexander Graf 1407dd43ac07SAlexander Graf if (counter == 31) { 1408dd43ac07SAlexander Graf filter = env->cp15.pmccfiltr_el0; 1409dd43ac07SAlexander Graf } else { 1410dd43ac07SAlexander Graf filter = env->cp15.c14_pmevtyper[counter]; 1411dd43ac07SAlexander Graf } 1412dd43ac07SAlexander Graf 1413dd43ac07SAlexander Graf if (el == 0) { 1414dd43ac07SAlexander Graf filtered = filter & PMXEVTYPER_U; 1415dd43ac07SAlexander Graf } else if (el == 1) { 1416dd43ac07SAlexander Graf filtered = filter & PMXEVTYPER_P; 1417dd43ac07SAlexander Graf } 1418dd43ac07SAlexander Graf 1419dd43ac07SAlexander Graf if (counter != 31) { 1420dd43ac07SAlexander Graf /* 1421dd43ac07SAlexander Graf * If not checking PMCCNTR, ensure the counter is setup to an event we 1422dd43ac07SAlexander Graf * support 1423dd43ac07SAlexander Graf */ 1424dd43ac07SAlexander Graf uint16_t event = filter & PMXEVTYPER_EVTCOUNT; 1425dd43ac07SAlexander Graf if (!pmu_event_supported(event)) { 1426dd43ac07SAlexander Graf return false; 1427dd43ac07SAlexander Graf } 1428dd43ac07SAlexander Graf } 1429dd43ac07SAlexander Graf 1430dd43ac07SAlexander Graf return enabled && !filtered; 1431dd43ac07SAlexander Graf } 1432dd43ac07SAlexander Graf 1433dd43ac07SAlexander Graf static void pmswinc_write(CPUARMState *env, uint64_t value) 1434dd43ac07SAlexander Graf { 1435dd43ac07SAlexander Graf unsigned int i; 1436dd43ac07SAlexander Graf for (i = 0; i < pmu_num_counters(env); i++) { 1437dd43ac07SAlexander Graf /* Increment a counter's count iff: */ 1438dd43ac07SAlexander Graf if ((value & (1 << i)) && /* counter's bit is set */ 1439dd43ac07SAlexander Graf /* counter is enabled and not filtered */ 1440dd43ac07SAlexander Graf pmu_counter_enabled(env, i) && 1441dd43ac07SAlexander Graf /* counter is SW_INCR */ 1442dd43ac07SAlexander Graf (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) == 0x0) { 1443dd43ac07SAlexander Graf /* 1444dd43ac07SAlexander Graf * Detect if this write causes an overflow since we can't predict 1445dd43ac07SAlexander Graf * PMSWINC overflows like we can for other events 1446dd43ac07SAlexander Graf */ 1447dd43ac07SAlexander Graf uint32_t new_pmswinc = env->cp15.c14_pmevcntr[i] + 1; 1448dd43ac07SAlexander Graf 1449dd43ac07SAlexander Graf if (env->cp15.c14_pmevcntr[i] & ~new_pmswinc & INT32_MIN) { 1450dd43ac07SAlexander Graf env->cp15.c9_pmovsr |= (1 << i); 1451dd43ac07SAlexander Graf pmu_update_irq(env); 1452dd43ac07SAlexander Graf } 1453dd43ac07SAlexander Graf 1454dd43ac07SAlexander Graf env->cp15.c14_pmevcntr[i] = new_pmswinc; 1455dd43ac07SAlexander Graf } 1456dd43ac07SAlexander Graf } 1457dd43ac07SAlexander Graf } 1458dd43ac07SAlexander Graf 1459a2260983SAlexander Graf static bool hvf_sysreg_write_cp(CPUState *cpu, uint32_t reg, uint64_t val) 1460a2260983SAlexander Graf { 1461a2260983SAlexander Graf ARMCPU *arm_cpu = ARM_CPU(cpu); 1462a2260983SAlexander Graf CPUARMState *env = &arm_cpu->env; 1463a2260983SAlexander Graf const ARMCPRegInfo *ri; 1464a2260983SAlexander Graf 1465a2260983SAlexander Graf ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg)); 1466a2260983SAlexander Graf 1467a2260983SAlexander Graf if (ri) { 1468a2260983SAlexander Graf if (ri->accessfn) { 1469a2260983SAlexander Graf if (ri->accessfn(env, ri, false) != CP_ACCESS_OK) { 1470a2260983SAlexander Graf return false; 1471a2260983SAlexander Graf } 1472a2260983SAlexander Graf } 1473a2260983SAlexander Graf if (ri->writefn) { 1474a2260983SAlexander Graf ri->writefn(env, ri, val); 1475a2260983SAlexander Graf } else { 1476a2260983SAlexander Graf CPREG_FIELD64(env, ri) = val; 1477a2260983SAlexander Graf } 1478a2260983SAlexander Graf 1479a2260983SAlexander Graf trace_hvf_vgic_write(ri->name, val); 1480a2260983SAlexander Graf return true; 1481a2260983SAlexander Graf } 1482a2260983SAlexander Graf 1483a2260983SAlexander Graf return false; 1484a2260983SAlexander Graf } 1485a2260983SAlexander Graf 1486a1477da3SAlexander Graf static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) 1487a1477da3SAlexander Graf { 1488a1477da3SAlexander Graf ARMCPU *arm_cpu = ARM_CPU(cpu); 1489a1477da3SAlexander Graf CPUARMState *env = &arm_cpu->env; 1490a1477da3SAlexander Graf 1491a1477da3SAlexander Graf trace_hvf_sysreg_write(reg, 1492ad99f64fSAlexander Graf SYSREG_OP0(reg), 1493ad99f64fSAlexander Graf SYSREG_OP1(reg), 1494ad99f64fSAlexander Graf SYSREG_CRN(reg), 1495ad99f64fSAlexander Graf SYSREG_CRM(reg), 1496ad99f64fSAlexander Graf SYSREG_OP2(reg), 1497a1477da3SAlexander Graf val); 1498a1477da3SAlexander Graf 1499a1477da3SAlexander Graf switch (reg) { 1500dd43ac07SAlexander Graf case SYSREG_PMCCNTR_EL0: 1501dd43ac07SAlexander Graf pmu_op_start(env); 1502dd43ac07SAlexander Graf env->cp15.c15_ccnt = val; 1503dd43ac07SAlexander Graf pmu_op_finish(env); 1504dd43ac07SAlexander Graf break; 1505dd43ac07SAlexander Graf case SYSREG_PMCR_EL0: 1506dd43ac07SAlexander Graf pmu_op_start(env); 1507dd43ac07SAlexander Graf 1508dd43ac07SAlexander Graf if (val & PMCRC) { 1509dd43ac07SAlexander Graf /* The counter has been reset */ 1510dd43ac07SAlexander Graf env->cp15.c15_ccnt = 0; 1511dd43ac07SAlexander Graf } 1512dd43ac07SAlexander Graf 1513dd43ac07SAlexander Graf if (val & PMCRP) { 1514dd43ac07SAlexander Graf unsigned int i; 1515dd43ac07SAlexander Graf for (i = 0; i < pmu_num_counters(env); i++) { 1516dd43ac07SAlexander Graf env->cp15.c14_pmevcntr[i] = 0; 1517dd43ac07SAlexander Graf } 1518dd43ac07SAlexander Graf } 1519dd43ac07SAlexander Graf 15209323e79fSPeter Maydell env->cp15.c9_pmcr &= ~PMCR_WRITABLE_MASK; 15219323e79fSPeter Maydell env->cp15.c9_pmcr |= (val & PMCR_WRITABLE_MASK); 1522dd43ac07SAlexander Graf 1523dd43ac07SAlexander Graf pmu_op_finish(env); 1524dd43ac07SAlexander Graf break; 1525dd43ac07SAlexander Graf case SYSREG_PMUSERENR_EL0: 1526dd43ac07SAlexander Graf env->cp15.c9_pmuserenr = val & 0xf; 1527dd43ac07SAlexander Graf break; 1528dd43ac07SAlexander Graf case SYSREG_PMCNTENSET_EL0: 1529dd43ac07SAlexander Graf env->cp15.c9_pmcnten |= (val & pmu_counter_mask(env)); 1530dd43ac07SAlexander Graf break; 1531dd43ac07SAlexander Graf case SYSREG_PMCNTENCLR_EL0: 1532dd43ac07SAlexander Graf env->cp15.c9_pmcnten &= ~(val & pmu_counter_mask(env)); 1533dd43ac07SAlexander Graf break; 1534dd43ac07SAlexander Graf case SYSREG_PMINTENCLR_EL1: 1535dd43ac07SAlexander Graf pmu_op_start(env); 1536dd43ac07SAlexander Graf env->cp15.c9_pminten |= val; 1537dd43ac07SAlexander Graf pmu_op_finish(env); 1538dd43ac07SAlexander Graf break; 1539dd43ac07SAlexander Graf case SYSREG_PMOVSCLR_EL0: 1540dd43ac07SAlexander Graf pmu_op_start(env); 1541dd43ac07SAlexander Graf env->cp15.c9_pmovsr &= ~val; 1542dd43ac07SAlexander Graf pmu_op_finish(env); 1543dd43ac07SAlexander Graf break; 1544dd43ac07SAlexander Graf case SYSREG_PMSWINC_EL0: 1545dd43ac07SAlexander Graf pmu_op_start(env); 1546dd43ac07SAlexander Graf pmswinc_write(env, val); 1547dd43ac07SAlexander Graf pmu_op_finish(env); 1548dd43ac07SAlexander Graf break; 1549dd43ac07SAlexander Graf case SYSREG_PMSELR_EL0: 1550dd43ac07SAlexander Graf env->cp15.c9_pmselr = val & 0x1f; 1551dd43ac07SAlexander Graf break; 1552dd43ac07SAlexander Graf case SYSREG_PMCCFILTR_EL0: 1553dd43ac07SAlexander Graf pmu_op_start(env); 1554dd43ac07SAlexander Graf env->cp15.pmccfiltr_el0 = val & PMCCFILTR_EL0; 1555dd43ac07SAlexander Graf pmu_op_finish(env); 1556dd43ac07SAlexander Graf break; 1557a1477da3SAlexander Graf case SYSREG_OSLAR_EL1: 1558a1477da3SAlexander Graf env->cp15.oslsr_el1 = val & 1; 1559a1477da3SAlexander Graf break; 1560a1477da3SAlexander Graf case SYSREG_OSDLR_EL1: 1561a1477da3SAlexander Graf /* Dummy register */ 1562a1477da3SAlexander Graf break; 1563a2260983SAlexander Graf case SYSREG_ICC_AP0R0_EL1: 1564a2260983SAlexander Graf case SYSREG_ICC_AP0R1_EL1: 1565a2260983SAlexander Graf case SYSREG_ICC_AP0R2_EL1: 1566a2260983SAlexander Graf case SYSREG_ICC_AP0R3_EL1: 1567a2260983SAlexander Graf case SYSREG_ICC_AP1R0_EL1: 1568a2260983SAlexander Graf case SYSREG_ICC_AP1R1_EL1: 1569a2260983SAlexander Graf case SYSREG_ICC_AP1R2_EL1: 1570a2260983SAlexander Graf case SYSREG_ICC_AP1R3_EL1: 1571a2260983SAlexander Graf case SYSREG_ICC_ASGI1R_EL1: 1572a2260983SAlexander Graf case SYSREG_ICC_BPR0_EL1: 1573a2260983SAlexander Graf case SYSREG_ICC_BPR1_EL1: 1574a2260983SAlexander Graf case SYSREG_ICC_CTLR_EL1: 1575a2260983SAlexander Graf case SYSREG_ICC_DIR_EL1: 1576a2260983SAlexander Graf case SYSREG_ICC_EOIR0_EL1: 1577a2260983SAlexander Graf case SYSREG_ICC_EOIR1_EL1: 1578a2260983SAlexander Graf case SYSREG_ICC_HPPIR0_EL1: 1579a2260983SAlexander Graf case SYSREG_ICC_HPPIR1_EL1: 1580a2260983SAlexander Graf case SYSREG_ICC_IAR0_EL1: 1581a2260983SAlexander Graf case SYSREG_ICC_IAR1_EL1: 1582a2260983SAlexander Graf case SYSREG_ICC_IGRPEN0_EL1: 1583a2260983SAlexander Graf case SYSREG_ICC_IGRPEN1_EL1: 1584a2260983SAlexander Graf case SYSREG_ICC_PMR_EL1: 1585a2260983SAlexander Graf case SYSREG_ICC_SGI0R_EL1: 1586a2260983SAlexander Graf case SYSREG_ICC_SGI1R_EL1: 1587a2260983SAlexander Graf case SYSREG_ICC_SRE_EL1: 1588a2260983SAlexander Graf /* Call the TCG sysreg handler. This is only safe for GICv3 regs. */ 1589a2260983SAlexander Graf if (!hvf_sysreg_write_cp(cpu, reg, val)) { 1590a2260983SAlexander Graf hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); 1591a2260983SAlexander Graf } 1592a2260983SAlexander Graf break; 1593ce799a04SFrancesco Cagnin case SYSREG_MDSCR_EL1: 1594ce799a04SFrancesco Cagnin env->cp15.mdscr_el1 = val; 1595ce799a04SFrancesco Cagnin break; 1596ce799a04SFrancesco Cagnin case SYSREG_DBGBVR0_EL1: 1597ce799a04SFrancesco Cagnin case SYSREG_DBGBVR1_EL1: 1598ce799a04SFrancesco Cagnin case SYSREG_DBGBVR2_EL1: 1599ce799a04SFrancesco Cagnin case SYSREG_DBGBVR3_EL1: 1600ce799a04SFrancesco Cagnin case SYSREG_DBGBVR4_EL1: 1601ce799a04SFrancesco Cagnin case SYSREG_DBGBVR5_EL1: 1602ce799a04SFrancesco Cagnin case SYSREG_DBGBVR6_EL1: 1603ce799a04SFrancesco Cagnin case SYSREG_DBGBVR7_EL1: 1604ce799a04SFrancesco Cagnin case SYSREG_DBGBVR8_EL1: 1605ce799a04SFrancesco Cagnin case SYSREG_DBGBVR9_EL1: 1606ce799a04SFrancesco Cagnin case SYSREG_DBGBVR10_EL1: 1607ce799a04SFrancesco Cagnin case SYSREG_DBGBVR11_EL1: 1608ce799a04SFrancesco Cagnin case SYSREG_DBGBVR12_EL1: 1609ce799a04SFrancesco Cagnin case SYSREG_DBGBVR13_EL1: 1610ce799a04SFrancesco Cagnin case SYSREG_DBGBVR14_EL1: 1611ce799a04SFrancesco Cagnin case SYSREG_DBGBVR15_EL1: 1612ce799a04SFrancesco Cagnin env->cp15.dbgbvr[SYSREG_CRM(reg)] = val; 1613ce799a04SFrancesco Cagnin break; 1614ce799a04SFrancesco Cagnin case SYSREG_DBGBCR0_EL1: 1615ce799a04SFrancesco Cagnin case SYSREG_DBGBCR1_EL1: 1616ce799a04SFrancesco Cagnin case SYSREG_DBGBCR2_EL1: 1617ce799a04SFrancesco Cagnin case SYSREG_DBGBCR3_EL1: 1618ce799a04SFrancesco Cagnin case SYSREG_DBGBCR4_EL1: 1619ce799a04SFrancesco Cagnin case SYSREG_DBGBCR5_EL1: 1620ce799a04SFrancesco Cagnin case SYSREG_DBGBCR6_EL1: 1621ce799a04SFrancesco Cagnin case SYSREG_DBGBCR7_EL1: 1622ce799a04SFrancesco Cagnin case SYSREG_DBGBCR8_EL1: 1623ce799a04SFrancesco Cagnin case SYSREG_DBGBCR9_EL1: 1624ce799a04SFrancesco Cagnin case SYSREG_DBGBCR10_EL1: 1625ce799a04SFrancesco Cagnin case SYSREG_DBGBCR11_EL1: 1626ce799a04SFrancesco Cagnin case SYSREG_DBGBCR12_EL1: 1627ce799a04SFrancesco Cagnin case SYSREG_DBGBCR13_EL1: 1628ce799a04SFrancesco Cagnin case SYSREG_DBGBCR14_EL1: 1629ce799a04SFrancesco Cagnin case SYSREG_DBGBCR15_EL1: 1630ce799a04SFrancesco Cagnin env->cp15.dbgbcr[SYSREG_CRM(reg)] = val; 1631ce799a04SFrancesco Cagnin break; 1632ce799a04SFrancesco Cagnin case SYSREG_DBGWVR0_EL1: 1633ce799a04SFrancesco Cagnin case SYSREG_DBGWVR1_EL1: 1634ce799a04SFrancesco Cagnin case SYSREG_DBGWVR2_EL1: 1635ce799a04SFrancesco Cagnin case SYSREG_DBGWVR3_EL1: 1636ce799a04SFrancesco Cagnin case SYSREG_DBGWVR4_EL1: 1637ce799a04SFrancesco Cagnin case SYSREG_DBGWVR5_EL1: 1638ce799a04SFrancesco Cagnin case SYSREG_DBGWVR6_EL1: 1639ce799a04SFrancesco Cagnin case SYSREG_DBGWVR7_EL1: 1640ce799a04SFrancesco Cagnin case SYSREG_DBGWVR8_EL1: 1641ce799a04SFrancesco Cagnin case SYSREG_DBGWVR9_EL1: 1642ce799a04SFrancesco Cagnin case SYSREG_DBGWVR10_EL1: 1643ce799a04SFrancesco Cagnin case SYSREG_DBGWVR11_EL1: 1644ce799a04SFrancesco Cagnin case SYSREG_DBGWVR12_EL1: 1645ce799a04SFrancesco Cagnin case SYSREG_DBGWVR13_EL1: 1646ce799a04SFrancesco Cagnin case SYSREG_DBGWVR14_EL1: 1647ce799a04SFrancesco Cagnin case SYSREG_DBGWVR15_EL1: 1648ce799a04SFrancesco Cagnin env->cp15.dbgwvr[SYSREG_CRM(reg)] = val; 1649ce799a04SFrancesco Cagnin break; 1650ce799a04SFrancesco Cagnin case SYSREG_DBGWCR0_EL1: 1651ce799a04SFrancesco Cagnin case SYSREG_DBGWCR1_EL1: 1652ce799a04SFrancesco Cagnin case SYSREG_DBGWCR2_EL1: 1653ce799a04SFrancesco Cagnin case SYSREG_DBGWCR3_EL1: 1654ce799a04SFrancesco Cagnin case SYSREG_DBGWCR4_EL1: 1655ce799a04SFrancesco Cagnin case SYSREG_DBGWCR5_EL1: 1656ce799a04SFrancesco Cagnin case SYSREG_DBGWCR6_EL1: 1657ce799a04SFrancesco Cagnin case SYSREG_DBGWCR7_EL1: 1658ce799a04SFrancesco Cagnin case SYSREG_DBGWCR8_EL1: 1659ce799a04SFrancesco Cagnin case SYSREG_DBGWCR9_EL1: 1660ce799a04SFrancesco Cagnin case SYSREG_DBGWCR10_EL1: 1661ce799a04SFrancesco Cagnin case SYSREG_DBGWCR11_EL1: 1662ce799a04SFrancesco Cagnin case SYSREG_DBGWCR12_EL1: 1663ce799a04SFrancesco Cagnin case SYSREG_DBGWCR13_EL1: 1664ce799a04SFrancesco Cagnin case SYSREG_DBGWCR14_EL1: 1665ce799a04SFrancesco Cagnin case SYSREG_DBGWCR15_EL1: 1666ce799a04SFrancesco Cagnin env->cp15.dbgwcr[SYSREG_CRM(reg)] = val; 1667ce799a04SFrancesco Cagnin break; 1668a1477da3SAlexander Graf default: 1669a1477da3SAlexander Graf cpu_synchronize_state(cpu); 1670a1477da3SAlexander Graf trace_hvf_unhandled_sysreg_write(env->pc, reg, 1671ad99f64fSAlexander Graf SYSREG_OP0(reg), 1672ad99f64fSAlexander Graf SYSREG_OP1(reg), 1673ad99f64fSAlexander Graf SYSREG_CRN(reg), 1674ad99f64fSAlexander Graf SYSREG_CRM(reg), 1675ad99f64fSAlexander Graf SYSREG_OP2(reg)); 1676a1477da3SAlexander Graf hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); 1677a1477da3SAlexander Graf return 1; 1678a1477da3SAlexander Graf } 1679a1477da3SAlexander Graf 1680a1477da3SAlexander Graf return 0; 1681a1477da3SAlexander Graf } 1682a1477da3SAlexander Graf 1683a1477da3SAlexander Graf static int hvf_inject_interrupts(CPUState *cpu) 1684a1477da3SAlexander Graf { 1685a1477da3SAlexander Graf if (cpu->interrupt_request & CPU_INTERRUPT_FIQ) { 1686a1477da3SAlexander Graf trace_hvf_inject_fiq(); 16873b295bcbSPhilippe Mathieu-Daudé hv_vcpu_set_pending_interrupt(cpu->accel->fd, HV_INTERRUPT_TYPE_FIQ, 1688a1477da3SAlexander Graf true); 1689a1477da3SAlexander Graf } 1690a1477da3SAlexander Graf 1691a1477da3SAlexander Graf if (cpu->interrupt_request & CPU_INTERRUPT_HARD) { 1692a1477da3SAlexander Graf trace_hvf_inject_irq(); 16933b295bcbSPhilippe Mathieu-Daudé hv_vcpu_set_pending_interrupt(cpu->accel->fd, HV_INTERRUPT_TYPE_IRQ, 1694a1477da3SAlexander Graf true); 1695a1477da3SAlexander Graf } 1696a1477da3SAlexander Graf 1697a1477da3SAlexander Graf return 0; 1698a1477da3SAlexander Graf } 1699a1477da3SAlexander Graf 1700a1477da3SAlexander Graf static uint64_t hvf_vtimer_val_raw(void) 1701a1477da3SAlexander Graf { 1702a1477da3SAlexander Graf /* 1703a1477da3SAlexander Graf * mach_absolute_time() returns the vtimer value without the VM 1704a1477da3SAlexander Graf * offset that we define. Add our own offset on top. 1705a1477da3SAlexander Graf */ 1706a1477da3SAlexander Graf return mach_absolute_time() - hvf_state->vtimer_offset; 1707a1477da3SAlexander Graf } 1708a1477da3SAlexander Graf 1709219c101fSPeter Collingbourne static uint64_t hvf_vtimer_val(void) 1710219c101fSPeter Collingbourne { 1711219c101fSPeter Collingbourne if (!runstate_is_running()) { 1712219c101fSPeter Collingbourne /* VM is paused, the vtimer value is in vtimer.vtimer_val */ 1713219c101fSPeter Collingbourne return vtimer.vtimer_val; 1714219c101fSPeter Collingbourne } 1715219c101fSPeter Collingbourne 1716219c101fSPeter Collingbourne return hvf_vtimer_val_raw(); 1717219c101fSPeter Collingbourne } 1718219c101fSPeter Collingbourne 1719219c101fSPeter Collingbourne static void hvf_wait_for_ipi(CPUState *cpu, struct timespec *ts) 1720219c101fSPeter Collingbourne { 1721219c101fSPeter Collingbourne /* 1722219c101fSPeter Collingbourne * Use pselect to sleep so that other threads can IPI us while we're 1723219c101fSPeter Collingbourne * sleeping. 1724219c101fSPeter Collingbourne */ 172506831001SPaolo Bonzini qatomic_set_mb(&cpu->thread_kicked, false); 1726195801d7SStefan Hajnoczi bql_unlock(); 17273b295bcbSPhilippe Mathieu-Daudé pselect(0, 0, 0, 0, ts, &cpu->accel->unblock_ipi_mask); 1728195801d7SStefan Hajnoczi bql_lock(); 1729219c101fSPeter Collingbourne } 1730219c101fSPeter Collingbourne 1731219c101fSPeter Collingbourne static void hvf_wfi(CPUState *cpu) 1732219c101fSPeter Collingbourne { 1733219c101fSPeter Collingbourne ARMCPU *arm_cpu = ARM_CPU(cpu); 1734219c101fSPeter Collingbourne struct timespec ts; 1735219c101fSPeter Collingbourne hv_return_t r; 1736219c101fSPeter Collingbourne uint64_t ctl; 1737219c101fSPeter Collingbourne uint64_t cval; 1738219c101fSPeter Collingbourne int64_t ticks_to_sleep; 1739219c101fSPeter Collingbourne uint64_t seconds; 1740219c101fSPeter Collingbourne uint64_t nanos; 1741219c101fSPeter Collingbourne uint32_t cntfrq; 1742219c101fSPeter Collingbourne 1743219c101fSPeter Collingbourne if (cpu->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIQ)) { 1744219c101fSPeter Collingbourne /* Interrupt pending, no need to wait */ 1745219c101fSPeter Collingbourne return; 1746219c101fSPeter Collingbourne } 1747219c101fSPeter Collingbourne 17483b295bcbSPhilippe Mathieu-Daudé r = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CTL_EL0, &ctl); 1749219c101fSPeter Collingbourne assert_hvf_ok(r); 1750219c101fSPeter Collingbourne 1751219c101fSPeter Collingbourne if (!(ctl & 1) || (ctl & 2)) { 1752219c101fSPeter Collingbourne /* Timer disabled or masked, just wait for an IPI. */ 1753219c101fSPeter Collingbourne hvf_wait_for_ipi(cpu, NULL); 1754219c101fSPeter Collingbourne return; 1755219c101fSPeter Collingbourne } 1756219c101fSPeter Collingbourne 17573b295bcbSPhilippe Mathieu-Daudé r = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CVAL_EL0, &cval); 1758219c101fSPeter Collingbourne assert_hvf_ok(r); 1759219c101fSPeter Collingbourne 1760219c101fSPeter Collingbourne ticks_to_sleep = cval - hvf_vtimer_val(); 1761219c101fSPeter Collingbourne if (ticks_to_sleep < 0) { 1762219c101fSPeter Collingbourne return; 1763219c101fSPeter Collingbourne } 1764219c101fSPeter Collingbourne 1765219c101fSPeter Collingbourne cntfrq = gt_cntfrq_period_ns(arm_cpu); 1766219c101fSPeter Collingbourne seconds = muldiv64(ticks_to_sleep, cntfrq, NANOSECONDS_PER_SECOND); 1767219c101fSPeter Collingbourne ticks_to_sleep -= muldiv64(seconds, NANOSECONDS_PER_SECOND, cntfrq); 1768219c101fSPeter Collingbourne nanos = ticks_to_sleep * cntfrq; 1769219c101fSPeter Collingbourne 1770219c101fSPeter Collingbourne /* 1771219c101fSPeter Collingbourne * Don't sleep for less than the time a context switch would take, 1772219c101fSPeter Collingbourne * so that we can satisfy fast timer requests on the same CPU. 1773219c101fSPeter Collingbourne * Measurements on M1 show the sweet spot to be ~2ms. 1774219c101fSPeter Collingbourne */ 1775219c101fSPeter Collingbourne if (!seconds && nanos < (2 * SCALE_MS)) { 1776219c101fSPeter Collingbourne return; 1777219c101fSPeter Collingbourne } 1778219c101fSPeter Collingbourne 1779219c101fSPeter Collingbourne ts = (struct timespec) { seconds, nanos }; 1780219c101fSPeter Collingbourne hvf_wait_for_ipi(cpu, &ts); 1781219c101fSPeter Collingbourne } 1782219c101fSPeter Collingbourne 1783a1477da3SAlexander Graf static void hvf_sync_vtimer(CPUState *cpu) 1784a1477da3SAlexander Graf { 1785a1477da3SAlexander Graf ARMCPU *arm_cpu = ARM_CPU(cpu); 1786a1477da3SAlexander Graf hv_return_t r; 1787a1477da3SAlexander Graf uint64_t ctl; 1788a1477da3SAlexander Graf bool irq_state; 1789a1477da3SAlexander Graf 17903b295bcbSPhilippe Mathieu-Daudé if (!cpu->accel->vtimer_masked) { 1791a1477da3SAlexander Graf /* We will get notified on vtimer changes by hvf, nothing to do */ 1792a1477da3SAlexander Graf return; 1793a1477da3SAlexander Graf } 1794a1477da3SAlexander Graf 17953b295bcbSPhilippe Mathieu-Daudé r = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CTL_EL0, &ctl); 1796a1477da3SAlexander Graf assert_hvf_ok(r); 1797a1477da3SAlexander Graf 1798a1477da3SAlexander Graf irq_state = (ctl & (TMR_CTL_ENABLE | TMR_CTL_IMASK | TMR_CTL_ISTATUS)) == 1799a1477da3SAlexander Graf (TMR_CTL_ENABLE | TMR_CTL_ISTATUS); 1800a1477da3SAlexander Graf qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], irq_state); 1801a1477da3SAlexander Graf 1802a1477da3SAlexander Graf if (!irq_state) { 1803a1477da3SAlexander Graf /* Timer no longer asserting, we can unmask it */ 18043b295bcbSPhilippe Mathieu-Daudé hv_vcpu_set_vtimer_mask(cpu->accel->fd, false); 18053b295bcbSPhilippe Mathieu-Daudé cpu->accel->vtimer_masked = false; 1806a1477da3SAlexander Graf } 1807a1477da3SAlexander Graf } 1808a1477da3SAlexander Graf 1809a1477da3SAlexander Graf int hvf_vcpu_exec(CPUState *cpu) 1810a1477da3SAlexander Graf { 1811a1477da3SAlexander Graf ARMCPU *arm_cpu = ARM_CPU(cpu); 1812a1477da3SAlexander Graf CPUARMState *env = &arm_cpu->env; 1813eb2edc42SFrancesco Cagnin int ret; 18143b295bcbSPhilippe Mathieu-Daudé hv_vcpu_exit_t *hvf_exit = cpu->accel->exit; 1815a1477da3SAlexander Graf hv_return_t r; 1816a1477da3SAlexander Graf bool advance_pc = false; 1817a1477da3SAlexander Graf 1818eb2edc42SFrancesco Cagnin if (!(cpu->singlestep_enabled & SSTEP_NOIRQ) && 1819eb2edc42SFrancesco Cagnin hvf_inject_interrupts(cpu)) { 1820a1477da3SAlexander Graf return EXCP_INTERRUPT; 1821a1477da3SAlexander Graf } 1822a1477da3SAlexander Graf 1823a1477da3SAlexander Graf if (cpu->halted) { 1824a1477da3SAlexander Graf return EXCP_HLT; 1825a1477da3SAlexander Graf } 1826a1477da3SAlexander Graf 1827a1477da3SAlexander Graf flush_cpu_state(cpu); 1828a1477da3SAlexander Graf 1829195801d7SStefan Hajnoczi bql_unlock(); 18303b295bcbSPhilippe Mathieu-Daudé assert_hvf_ok(hv_vcpu_run(cpu->accel->fd)); 1831a1477da3SAlexander Graf 1832a1477da3SAlexander Graf /* handle VMEXIT */ 1833a1477da3SAlexander Graf uint64_t exit_reason = hvf_exit->reason; 1834a1477da3SAlexander Graf uint64_t syndrome = hvf_exit->exception.syndrome; 1835a1477da3SAlexander Graf uint32_t ec = syn_get_ec(syndrome); 1836a1477da3SAlexander Graf 1837eb2edc42SFrancesco Cagnin ret = 0; 1838195801d7SStefan Hajnoczi bql_lock(); 1839a1477da3SAlexander Graf switch (exit_reason) { 1840a1477da3SAlexander Graf case HV_EXIT_REASON_EXCEPTION: 1841a1477da3SAlexander Graf /* This is the main one, handle below. */ 1842a1477da3SAlexander Graf break; 1843a1477da3SAlexander Graf case HV_EXIT_REASON_VTIMER_ACTIVATED: 1844a1477da3SAlexander Graf qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], 1); 18453b295bcbSPhilippe Mathieu-Daudé cpu->accel->vtimer_masked = true; 1846a1477da3SAlexander Graf return 0; 1847a1477da3SAlexander Graf case HV_EXIT_REASON_CANCELED: 1848a1477da3SAlexander Graf /* we got kicked, no exit to process */ 1849a1477da3SAlexander Graf return 0; 1850a1477da3SAlexander Graf default: 1851d385a605SRichard Henderson g_assert_not_reached(); 1852a1477da3SAlexander Graf } 1853a1477da3SAlexander Graf 1854a1477da3SAlexander Graf hvf_sync_vtimer(cpu); 1855a1477da3SAlexander Graf 1856a1477da3SAlexander Graf switch (ec) { 1857eb2edc42SFrancesco Cagnin case EC_SOFTWARESTEP: { 1858eb2edc42SFrancesco Cagnin ret = EXCP_DEBUG; 1859eb2edc42SFrancesco Cagnin 1860eb2edc42SFrancesco Cagnin if (!cpu->singlestep_enabled) { 1861eb2edc42SFrancesco Cagnin error_report("EC_SOFTWARESTEP but single-stepping not enabled"); 1862eb2edc42SFrancesco Cagnin } 1863eb2edc42SFrancesco Cagnin break; 1864eb2edc42SFrancesco Cagnin } 1865eb2edc42SFrancesco Cagnin case EC_AA64_BKPT: { 1866eb2edc42SFrancesco Cagnin ret = EXCP_DEBUG; 1867eb2edc42SFrancesco Cagnin 1868eb2edc42SFrancesco Cagnin cpu_synchronize_state(cpu); 1869eb2edc42SFrancesco Cagnin 1870eb2edc42SFrancesco Cagnin if (!hvf_find_sw_breakpoint(cpu, env->pc)) { 1871eb2edc42SFrancesco Cagnin /* Re-inject into the guest */ 1872eb2edc42SFrancesco Cagnin ret = 0; 1873eb2edc42SFrancesco Cagnin hvf_raise_exception(cpu, EXCP_BKPT, syn_aa64_bkpt(0)); 1874eb2edc42SFrancesco Cagnin } 1875eb2edc42SFrancesco Cagnin break; 1876eb2edc42SFrancesco Cagnin } 1877eb2edc42SFrancesco Cagnin case EC_BREAKPOINT: { 1878eb2edc42SFrancesco Cagnin ret = EXCP_DEBUG; 1879eb2edc42SFrancesco Cagnin 1880eb2edc42SFrancesco Cagnin cpu_synchronize_state(cpu); 1881eb2edc42SFrancesco Cagnin 1882eb2edc42SFrancesco Cagnin if (!find_hw_breakpoint(cpu, env->pc)) { 1883eb2edc42SFrancesco Cagnin error_report("EC_BREAKPOINT but unknown hw breakpoint"); 1884eb2edc42SFrancesco Cagnin } 1885eb2edc42SFrancesco Cagnin break; 1886eb2edc42SFrancesco Cagnin } 1887eb2edc42SFrancesco Cagnin case EC_WATCHPOINT: { 1888eb2edc42SFrancesco Cagnin ret = EXCP_DEBUG; 1889eb2edc42SFrancesco Cagnin 1890eb2edc42SFrancesco Cagnin cpu_synchronize_state(cpu); 1891eb2edc42SFrancesco Cagnin 1892eb2edc42SFrancesco Cagnin CPUWatchpoint *wp = 1893eb2edc42SFrancesco Cagnin find_hw_watchpoint(cpu, hvf_exit->exception.virtual_address); 1894eb2edc42SFrancesco Cagnin if (!wp) { 1895eb2edc42SFrancesco Cagnin error_report("EXCP_DEBUG but unknown hw watchpoint"); 1896eb2edc42SFrancesco Cagnin } 1897eb2edc42SFrancesco Cagnin cpu->watchpoint_hit = wp; 1898eb2edc42SFrancesco Cagnin break; 1899eb2edc42SFrancesco Cagnin } 1900a1477da3SAlexander Graf case EC_DATAABORT: { 1901a1477da3SAlexander Graf bool isv = syndrome & ARM_EL_ISV; 1902a1477da3SAlexander Graf bool iswrite = (syndrome >> 6) & 1; 1903a1477da3SAlexander Graf bool s1ptw = (syndrome >> 7) & 1; 1904a1477da3SAlexander Graf uint32_t sas = (syndrome >> 22) & 3; 1905a1477da3SAlexander Graf uint32_t len = 1 << sas; 1906a1477da3SAlexander Graf uint32_t srt = (syndrome >> 16) & 0x1f; 19075fd6a3e2SAlexander Graf uint32_t cm = (syndrome >> 8) & 0x1; 1908a1477da3SAlexander Graf uint64_t val = 0; 1909a1477da3SAlexander Graf 1910a1477da3SAlexander Graf trace_hvf_data_abort(env->pc, hvf_exit->exception.virtual_address, 1911a1477da3SAlexander Graf hvf_exit->exception.physical_address, isv, 1912a1477da3SAlexander Graf iswrite, s1ptw, len, srt); 1913a1477da3SAlexander Graf 19145fd6a3e2SAlexander Graf if (cm) { 19155fd6a3e2SAlexander Graf /* We don't cache MMIO regions */ 19165fd6a3e2SAlexander Graf advance_pc = true; 19175fd6a3e2SAlexander Graf break; 19185fd6a3e2SAlexander Graf } 19195fd6a3e2SAlexander Graf 1920a1477da3SAlexander Graf assert(isv); 1921a1477da3SAlexander Graf 1922a1477da3SAlexander Graf if (iswrite) { 1923a1477da3SAlexander Graf val = hvf_get_reg(cpu, srt); 1924a1477da3SAlexander Graf address_space_write(&address_space_memory, 1925a1477da3SAlexander Graf hvf_exit->exception.physical_address, 1926a1477da3SAlexander Graf MEMTXATTRS_UNSPECIFIED, &val, len); 1927a1477da3SAlexander Graf } else { 1928a1477da3SAlexander Graf address_space_read(&address_space_memory, 1929a1477da3SAlexander Graf hvf_exit->exception.physical_address, 1930a1477da3SAlexander Graf MEMTXATTRS_UNSPECIFIED, &val, len); 1931a1477da3SAlexander Graf hvf_set_reg(cpu, srt, val); 1932a1477da3SAlexander Graf } 1933a1477da3SAlexander Graf 1934a1477da3SAlexander Graf advance_pc = true; 1935a1477da3SAlexander Graf break; 1936a1477da3SAlexander Graf } 1937a1477da3SAlexander Graf case EC_SYSTEMREGISTERTRAP: { 1938a1477da3SAlexander Graf bool isread = (syndrome >> 0) & 1; 1939a1477da3SAlexander Graf uint32_t rt = (syndrome >> 5) & 0x1f; 1940a1477da3SAlexander Graf uint32_t reg = syndrome & SYSREG_MASK; 1941a1477da3SAlexander Graf uint64_t val; 19425a3d2c35SPhilippe Mathieu-Daudé int sysreg_ret = 0; 1943a1477da3SAlexander Graf 1944a1477da3SAlexander Graf if (isread) { 19455a3d2c35SPhilippe Mathieu-Daudé sysreg_ret = hvf_sysreg_read(cpu, reg, rt); 1946a1477da3SAlexander Graf } else { 1947a1477da3SAlexander Graf val = hvf_get_reg(cpu, rt); 19485a3d2c35SPhilippe Mathieu-Daudé sysreg_ret = hvf_sysreg_write(cpu, reg, val); 1949a1477da3SAlexander Graf } 1950a1477da3SAlexander Graf 19515a3d2c35SPhilippe Mathieu-Daudé advance_pc = !sysreg_ret; 1952a1477da3SAlexander Graf break; 1953a1477da3SAlexander Graf } 1954a1477da3SAlexander Graf case EC_WFX_TRAP: 1955a1477da3SAlexander Graf advance_pc = true; 1956219c101fSPeter Collingbourne if (!(syndrome & WFX_IS_WFE)) { 1957219c101fSPeter Collingbourne hvf_wfi(cpu); 1958219c101fSPeter Collingbourne } 1959a1477da3SAlexander Graf break; 1960a1477da3SAlexander Graf case EC_AA64_HVC: 1961a1477da3SAlexander Graf cpu_synchronize_state(cpu); 19622c9c0bf9SAlexander Graf if (arm_cpu->psci_conduit == QEMU_PSCI_CONDUIT_HVC) { 19632c9c0bf9SAlexander Graf if (!hvf_handle_psci_call(cpu)) { 1964a1477da3SAlexander Graf trace_hvf_unknown_hvc(env->xregs[0]); 1965a1477da3SAlexander Graf /* SMCCC 1.3 section 5.2 says every unknown SMCCC call returns -1 */ 1966a1477da3SAlexander Graf env->xregs[0] = -1; 19672c9c0bf9SAlexander Graf } 19682c9c0bf9SAlexander Graf } else { 19692c9c0bf9SAlexander Graf trace_hvf_unknown_hvc(env->xregs[0]); 19702c9c0bf9SAlexander Graf hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); 19712c9c0bf9SAlexander Graf } 1972a1477da3SAlexander Graf break; 1973a1477da3SAlexander Graf case EC_AA64_SMC: 1974a1477da3SAlexander Graf cpu_synchronize_state(cpu); 19752c9c0bf9SAlexander Graf if (arm_cpu->psci_conduit == QEMU_PSCI_CONDUIT_SMC) { 19762c9c0bf9SAlexander Graf advance_pc = true; 19772c9c0bf9SAlexander Graf 19782c9c0bf9SAlexander Graf if (!hvf_handle_psci_call(cpu)) { 19792c9c0bf9SAlexander Graf trace_hvf_unknown_smc(env->xregs[0]); 19802c9c0bf9SAlexander Graf /* SMCCC 1.3 section 5.2 says every unknown SMCCC call returns -1 */ 19812c9c0bf9SAlexander Graf env->xregs[0] = -1; 19822c9c0bf9SAlexander Graf } 19832c9c0bf9SAlexander Graf } else { 1984a1477da3SAlexander Graf trace_hvf_unknown_smc(env->xregs[0]); 1985a1477da3SAlexander Graf hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); 19862c9c0bf9SAlexander Graf } 1987a1477da3SAlexander Graf break; 1988a1477da3SAlexander Graf default: 1989a1477da3SAlexander Graf cpu_synchronize_state(cpu); 1990a1477da3SAlexander Graf trace_hvf_exit(syndrome, ec, env->pc); 1991a1477da3SAlexander Graf error_report("0x%llx: unhandled exception ec=0x%x", env->pc, ec); 1992a1477da3SAlexander Graf } 1993a1477da3SAlexander Graf 1994a1477da3SAlexander Graf if (advance_pc) { 1995a1477da3SAlexander Graf uint64_t pc; 1996a1477da3SAlexander Graf 1997a1477da3SAlexander Graf flush_cpu_state(cpu); 1998a1477da3SAlexander Graf 19993b295bcbSPhilippe Mathieu-Daudé r = hv_vcpu_get_reg(cpu->accel->fd, HV_REG_PC, &pc); 2000a1477da3SAlexander Graf assert_hvf_ok(r); 2001a1477da3SAlexander Graf pc += 4; 20023b295bcbSPhilippe Mathieu-Daudé r = hv_vcpu_set_reg(cpu->accel->fd, HV_REG_PC, pc); 2003a1477da3SAlexander Graf assert_hvf_ok(r); 2004eb2edc42SFrancesco Cagnin 2005eb2edc42SFrancesco Cagnin /* Handle single-stepping over instructions which trigger a VM exit */ 2006eb2edc42SFrancesco Cagnin if (cpu->singlestep_enabled) { 2007eb2edc42SFrancesco Cagnin ret = EXCP_DEBUG; 2008eb2edc42SFrancesco Cagnin } 2009a1477da3SAlexander Graf } 2010a1477da3SAlexander Graf 2011eb2edc42SFrancesco Cagnin return ret; 2012a1477da3SAlexander Graf } 2013a1477da3SAlexander Graf 2014a1477da3SAlexander Graf static const VMStateDescription vmstate_hvf_vtimer = { 2015a1477da3SAlexander Graf .name = "hvf-vtimer", 2016a1477da3SAlexander Graf .version_id = 1, 2017a1477da3SAlexander Graf .minimum_version_id = 1, 2018f49986aeSRichard Henderson .fields = (const VMStateField[]) { 2019a1477da3SAlexander Graf VMSTATE_UINT64(vtimer_val, HVFVTimer), 2020a1477da3SAlexander Graf VMSTATE_END_OF_LIST() 2021a1477da3SAlexander Graf }, 2022a1477da3SAlexander Graf }; 2023a1477da3SAlexander Graf 2024a1477da3SAlexander Graf static void hvf_vm_state_change(void *opaque, bool running, RunState state) 2025a1477da3SAlexander Graf { 2026a1477da3SAlexander Graf HVFVTimer *s = opaque; 2027a1477da3SAlexander Graf 2028a1477da3SAlexander Graf if (running) { 2029a1477da3SAlexander Graf /* Update vtimer offset on all CPUs */ 2030a1477da3SAlexander Graf hvf_state->vtimer_offset = mach_absolute_time() - s->vtimer_val; 2031a1477da3SAlexander Graf cpu_synchronize_all_states(); 2032a1477da3SAlexander Graf } else { 2033a1477da3SAlexander Graf /* Remember vtimer value on every pause */ 2034a1477da3SAlexander Graf s->vtimer_val = hvf_vtimer_val_raw(); 2035a1477da3SAlexander Graf } 2036a1477da3SAlexander Graf } 2037a1477da3SAlexander Graf 2038a1477da3SAlexander Graf int hvf_arch_init(void) 2039a1477da3SAlexander Graf { 2040a1477da3SAlexander Graf hvf_state->vtimer_offset = mach_absolute_time(); 2041a1477da3SAlexander Graf vmstate_register(NULL, 0, &vmstate_hvf_vtimer, &vtimer); 2042a1477da3SAlexander Graf qemu_add_vm_change_state_handler(hvf_vm_state_change, &vtimer); 2043eb2edc42SFrancesco Cagnin 2044eb2edc42SFrancesco Cagnin hvf_arm_init_debug(); 2045eb2edc42SFrancesco Cagnin 2046a1477da3SAlexander Graf return 0; 2047a1477da3SAlexander Graf } 2048f4152040SFrancesco Cagnin 2049f4152040SFrancesco Cagnin static const uint32_t brk_insn = 0xd4200000; 2050f4152040SFrancesco Cagnin 2051f4152040SFrancesco Cagnin int hvf_arch_insert_sw_breakpoint(CPUState *cpu, struct hvf_sw_breakpoint *bp) 2052f4152040SFrancesco Cagnin { 2053f4152040SFrancesco Cagnin if (cpu_memory_rw_debug(cpu, bp->pc, (uint8_t *)&bp->saved_insn, 4, 0) || 2054f4152040SFrancesco Cagnin cpu_memory_rw_debug(cpu, bp->pc, (uint8_t *)&brk_insn, 4, 1)) { 2055f4152040SFrancesco Cagnin return -EINVAL; 2056f4152040SFrancesco Cagnin } 2057f4152040SFrancesco Cagnin return 0; 2058f4152040SFrancesco Cagnin } 2059f4152040SFrancesco Cagnin 2060f4152040SFrancesco Cagnin int hvf_arch_remove_sw_breakpoint(CPUState *cpu, struct hvf_sw_breakpoint *bp) 2061f4152040SFrancesco Cagnin { 2062f4152040SFrancesco Cagnin static uint32_t brk; 2063f4152040SFrancesco Cagnin 2064f4152040SFrancesco Cagnin if (cpu_memory_rw_debug(cpu, bp->pc, (uint8_t *)&brk, 4, 0) || 2065f4152040SFrancesco Cagnin brk != brk_insn || 2066f4152040SFrancesco Cagnin cpu_memory_rw_debug(cpu, bp->pc, (uint8_t *)&bp->saved_insn, 4, 1)) { 2067f4152040SFrancesco Cagnin return -EINVAL; 2068f4152040SFrancesco Cagnin } 2069f4152040SFrancesco Cagnin return 0; 2070f4152040SFrancesco Cagnin } 2071f4152040SFrancesco Cagnin 2072d447a624SAnton Johansson int hvf_arch_insert_hw_breakpoint(vaddr addr, vaddr len, int type) 2073f4152040SFrancesco Cagnin { 2074f4152040SFrancesco Cagnin switch (type) { 2075f4152040SFrancesco Cagnin case GDB_BREAKPOINT_HW: 2076f4152040SFrancesco Cagnin return insert_hw_breakpoint(addr); 2077f4152040SFrancesco Cagnin case GDB_WATCHPOINT_READ: 2078f4152040SFrancesco Cagnin case GDB_WATCHPOINT_WRITE: 2079f4152040SFrancesco Cagnin case GDB_WATCHPOINT_ACCESS: 2080f4152040SFrancesco Cagnin return insert_hw_watchpoint(addr, len, type); 2081f4152040SFrancesco Cagnin default: 2082f4152040SFrancesco Cagnin return -ENOSYS; 2083f4152040SFrancesco Cagnin } 2084f4152040SFrancesco Cagnin } 2085f4152040SFrancesco Cagnin 2086d447a624SAnton Johansson int hvf_arch_remove_hw_breakpoint(vaddr addr, vaddr len, int type) 2087f4152040SFrancesco Cagnin { 2088f4152040SFrancesco Cagnin switch (type) { 2089f4152040SFrancesco Cagnin case GDB_BREAKPOINT_HW: 2090f4152040SFrancesco Cagnin return delete_hw_breakpoint(addr); 2091f4152040SFrancesco Cagnin case GDB_WATCHPOINT_READ: 2092f4152040SFrancesco Cagnin case GDB_WATCHPOINT_WRITE: 2093f4152040SFrancesco Cagnin case GDB_WATCHPOINT_ACCESS: 2094f4152040SFrancesco Cagnin return delete_hw_watchpoint(addr, len, type); 2095f4152040SFrancesco Cagnin default: 2096f4152040SFrancesco Cagnin return -ENOSYS; 2097f4152040SFrancesco Cagnin } 2098f4152040SFrancesco Cagnin } 2099f4152040SFrancesco Cagnin 2100f4152040SFrancesco Cagnin void hvf_arch_remove_all_hw_breakpoints(void) 2101f4152040SFrancesco Cagnin { 2102f4152040SFrancesco Cagnin if (cur_hw_wps > 0) { 2103f4152040SFrancesco Cagnin g_array_remove_range(hw_watchpoints, 0, cur_hw_wps); 2104f4152040SFrancesco Cagnin } 2105f4152040SFrancesco Cagnin if (cur_hw_bps > 0) { 2106f4152040SFrancesco Cagnin g_array_remove_range(hw_breakpoints, 0, cur_hw_bps); 2107f4152040SFrancesco Cagnin } 2108f4152040SFrancesco Cagnin } 2109eb2edc42SFrancesco Cagnin 2110eb2edc42SFrancesco Cagnin /* 2111eb2edc42SFrancesco Cagnin * Update the vCPU with the gdbstub's view of debug registers. This view 2112eb2edc42SFrancesco Cagnin * consists of all hardware breakpoints and watchpoints inserted so far while 2113eb2edc42SFrancesco Cagnin * debugging the guest. 2114eb2edc42SFrancesco Cagnin */ 2115eb2edc42SFrancesco Cagnin static void hvf_put_gdbstub_debug_registers(CPUState *cpu) 2116eb2edc42SFrancesco Cagnin { 2117eb2edc42SFrancesco Cagnin hv_return_t r = HV_SUCCESS; 2118eb2edc42SFrancesco Cagnin int i; 2119eb2edc42SFrancesco Cagnin 2120eb2edc42SFrancesco Cagnin for (i = 0; i < cur_hw_bps; i++) { 2121eb2edc42SFrancesco Cagnin HWBreakpoint *bp = get_hw_bp(i); 21223b295bcbSPhilippe Mathieu-Daudé r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbcr_regs[i], bp->bcr); 2123eb2edc42SFrancesco Cagnin assert_hvf_ok(r); 21243b295bcbSPhilippe Mathieu-Daudé r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbvr_regs[i], bp->bvr); 2125eb2edc42SFrancesco Cagnin assert_hvf_ok(r); 2126eb2edc42SFrancesco Cagnin } 2127eb2edc42SFrancesco Cagnin for (i = cur_hw_bps; i < max_hw_bps; i++) { 21283b295bcbSPhilippe Mathieu-Daudé r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbcr_regs[i], 0); 2129eb2edc42SFrancesco Cagnin assert_hvf_ok(r); 21303b295bcbSPhilippe Mathieu-Daudé r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbvr_regs[i], 0); 2131eb2edc42SFrancesco Cagnin assert_hvf_ok(r); 2132eb2edc42SFrancesco Cagnin } 2133eb2edc42SFrancesco Cagnin 2134eb2edc42SFrancesco Cagnin for (i = 0; i < cur_hw_wps; i++) { 2135eb2edc42SFrancesco Cagnin HWWatchpoint *wp = get_hw_wp(i); 21363b295bcbSPhilippe Mathieu-Daudé r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwcr_regs[i], wp->wcr); 2137eb2edc42SFrancesco Cagnin assert_hvf_ok(r); 21383b295bcbSPhilippe Mathieu-Daudé r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwvr_regs[i], wp->wvr); 2139eb2edc42SFrancesco Cagnin assert_hvf_ok(r); 2140eb2edc42SFrancesco Cagnin } 2141eb2edc42SFrancesco Cagnin for (i = cur_hw_wps; i < max_hw_wps; i++) { 21423b295bcbSPhilippe Mathieu-Daudé r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwcr_regs[i], 0); 2143eb2edc42SFrancesco Cagnin assert_hvf_ok(r); 21443b295bcbSPhilippe Mathieu-Daudé r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwvr_regs[i], 0); 2145eb2edc42SFrancesco Cagnin assert_hvf_ok(r); 2146eb2edc42SFrancesco Cagnin } 2147eb2edc42SFrancesco Cagnin } 2148eb2edc42SFrancesco Cagnin 2149eb2edc42SFrancesco Cagnin /* 2150eb2edc42SFrancesco Cagnin * Update the vCPU with the guest's view of debug registers. This view is kept 2151eb2edc42SFrancesco Cagnin * in the environment at all times. 2152eb2edc42SFrancesco Cagnin */ 2153eb2edc42SFrancesco Cagnin static void hvf_put_guest_debug_registers(CPUState *cpu) 2154eb2edc42SFrancesco Cagnin { 2155eb2edc42SFrancesco Cagnin ARMCPU *arm_cpu = ARM_CPU(cpu); 2156eb2edc42SFrancesco Cagnin CPUARMState *env = &arm_cpu->env; 2157eb2edc42SFrancesco Cagnin hv_return_t r = HV_SUCCESS; 2158eb2edc42SFrancesco Cagnin int i; 2159eb2edc42SFrancesco Cagnin 2160eb2edc42SFrancesco Cagnin for (i = 0; i < max_hw_bps; i++) { 21613b295bcbSPhilippe Mathieu-Daudé r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbcr_regs[i], 2162eb2edc42SFrancesco Cagnin env->cp15.dbgbcr[i]); 2163eb2edc42SFrancesco Cagnin assert_hvf_ok(r); 21643b295bcbSPhilippe Mathieu-Daudé r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbvr_regs[i], 2165eb2edc42SFrancesco Cagnin env->cp15.dbgbvr[i]); 2166eb2edc42SFrancesco Cagnin assert_hvf_ok(r); 2167eb2edc42SFrancesco Cagnin } 2168eb2edc42SFrancesco Cagnin 2169eb2edc42SFrancesco Cagnin for (i = 0; i < max_hw_wps; i++) { 21703b295bcbSPhilippe Mathieu-Daudé r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwcr_regs[i], 2171eb2edc42SFrancesco Cagnin env->cp15.dbgwcr[i]); 2172eb2edc42SFrancesco Cagnin assert_hvf_ok(r); 21733b295bcbSPhilippe Mathieu-Daudé r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwvr_regs[i], 2174eb2edc42SFrancesco Cagnin env->cp15.dbgwvr[i]); 2175eb2edc42SFrancesco Cagnin assert_hvf_ok(r); 2176eb2edc42SFrancesco Cagnin } 2177eb2edc42SFrancesco Cagnin } 2178eb2edc42SFrancesco Cagnin 2179eb2edc42SFrancesco Cagnin static inline bool hvf_arm_hw_debug_active(CPUState *cpu) 2180eb2edc42SFrancesco Cagnin { 2181eb2edc42SFrancesco Cagnin return ((cur_hw_wps > 0) || (cur_hw_bps > 0)); 2182eb2edc42SFrancesco Cagnin } 2183eb2edc42SFrancesco Cagnin 2184eb2edc42SFrancesco Cagnin static void hvf_arch_set_traps(void) 2185eb2edc42SFrancesco Cagnin { 2186eb2edc42SFrancesco Cagnin CPUState *cpu; 2187eb2edc42SFrancesco Cagnin bool should_enable_traps = false; 2188eb2edc42SFrancesco Cagnin hv_return_t r = HV_SUCCESS; 2189eb2edc42SFrancesco Cagnin 2190eb2edc42SFrancesco Cagnin /* Check whether guest debugging is enabled for at least one vCPU; if it 2191eb2edc42SFrancesco Cagnin * is, enable exiting the guest on all vCPUs */ 2192eb2edc42SFrancesco Cagnin CPU_FOREACH(cpu) { 21933b295bcbSPhilippe Mathieu-Daudé should_enable_traps |= cpu->accel->guest_debug_enabled; 2194eb2edc42SFrancesco Cagnin } 2195eb2edc42SFrancesco Cagnin CPU_FOREACH(cpu) { 2196eb2edc42SFrancesco Cagnin /* Set whether debug exceptions exit the guest */ 21973b295bcbSPhilippe Mathieu-Daudé r = hv_vcpu_set_trap_debug_exceptions(cpu->accel->fd, 2198eb2edc42SFrancesco Cagnin should_enable_traps); 2199eb2edc42SFrancesco Cagnin assert_hvf_ok(r); 2200eb2edc42SFrancesco Cagnin 2201eb2edc42SFrancesco Cagnin /* Set whether accesses to debug registers exit the guest */ 22023b295bcbSPhilippe Mathieu-Daudé r = hv_vcpu_set_trap_debug_reg_accesses(cpu->accel->fd, 2203eb2edc42SFrancesco Cagnin should_enable_traps); 2204eb2edc42SFrancesco Cagnin assert_hvf_ok(r); 2205eb2edc42SFrancesco Cagnin } 2206eb2edc42SFrancesco Cagnin } 2207eb2edc42SFrancesco Cagnin 2208eb2edc42SFrancesco Cagnin void hvf_arch_update_guest_debug(CPUState *cpu) 2209eb2edc42SFrancesco Cagnin { 2210eb2edc42SFrancesco Cagnin ARMCPU *arm_cpu = ARM_CPU(cpu); 2211eb2edc42SFrancesco Cagnin CPUARMState *env = &arm_cpu->env; 2212eb2edc42SFrancesco Cagnin 2213eb2edc42SFrancesco Cagnin /* Check whether guest debugging is enabled */ 22143b295bcbSPhilippe Mathieu-Daudé cpu->accel->guest_debug_enabled = cpu->singlestep_enabled || 2215eb2edc42SFrancesco Cagnin hvf_sw_breakpoints_active(cpu) || 2216eb2edc42SFrancesco Cagnin hvf_arm_hw_debug_active(cpu); 2217eb2edc42SFrancesco Cagnin 2218eb2edc42SFrancesco Cagnin /* Update debug registers */ 22193b295bcbSPhilippe Mathieu-Daudé if (cpu->accel->guest_debug_enabled) { 2220eb2edc42SFrancesco Cagnin hvf_put_gdbstub_debug_registers(cpu); 2221eb2edc42SFrancesco Cagnin } else { 2222eb2edc42SFrancesco Cagnin hvf_put_guest_debug_registers(cpu); 2223eb2edc42SFrancesco Cagnin } 2224eb2edc42SFrancesco Cagnin 2225eb2edc42SFrancesco Cagnin cpu_synchronize_state(cpu); 2226eb2edc42SFrancesco Cagnin 2227eb2edc42SFrancesco Cagnin /* Enable/disable single-stepping */ 2228eb2edc42SFrancesco Cagnin if (cpu->singlestep_enabled) { 2229eb2edc42SFrancesco Cagnin env->cp15.mdscr_el1 = 2230eb2edc42SFrancesco Cagnin deposit64(env->cp15.mdscr_el1, MDSCR_EL1_SS_SHIFT, 1, 1); 2231eb2edc42SFrancesco Cagnin pstate_write(env, pstate_read(env) | PSTATE_SS); 2232eb2edc42SFrancesco Cagnin } else { 2233eb2edc42SFrancesco Cagnin env->cp15.mdscr_el1 = 2234eb2edc42SFrancesco Cagnin deposit64(env->cp15.mdscr_el1, MDSCR_EL1_SS_SHIFT, 1, 0); 2235eb2edc42SFrancesco Cagnin } 2236eb2edc42SFrancesco Cagnin 2237eb2edc42SFrancesco Cagnin /* Enable/disable Breakpoint exceptions */ 2238eb2edc42SFrancesco Cagnin if (hvf_arm_hw_debug_active(cpu)) { 2239eb2edc42SFrancesco Cagnin env->cp15.mdscr_el1 = 2240eb2edc42SFrancesco Cagnin deposit64(env->cp15.mdscr_el1, MDSCR_EL1_MDE_SHIFT, 1, 1); 2241eb2edc42SFrancesco Cagnin } else { 2242eb2edc42SFrancesco Cagnin env->cp15.mdscr_el1 = 2243eb2edc42SFrancesco Cagnin deposit64(env->cp15.mdscr_el1, MDSCR_EL1_MDE_SHIFT, 1, 0); 2244eb2edc42SFrancesco Cagnin } 2245eb2edc42SFrancesco Cagnin 2246eb2edc42SFrancesco Cagnin hvf_arch_set_traps(); 2247eb2edc42SFrancesco Cagnin } 2248eb2edc42SFrancesco Cagnin 2249d6fd5d83SPhilippe Mathieu-Daudé bool hvf_arch_supports_guest_debug(void) 2250eb2edc42SFrancesco Cagnin { 2251eb2edc42SFrancesco Cagnin return true; 2252eb2edc42SFrancesco Cagnin } 2253