1 /* 2 * QEMU ARM CPU -- internal functions and types 3 * 4 * Copyright (c) 2014 Linaro Ltd 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 * 20 * This header defines functions, types, etc which need to be shared 21 * between different source files within target/arm/ but which are 22 * private to it and not required by the rest of QEMU. 23 */ 24 25 #ifndef TARGET_ARM_INTERNALS_H 26 #define TARGET_ARM_INTERNALS_H 27 28 #include "hw/registerfields.h" 29 #include "tcg/tcg-gvec-desc.h" 30 #include "syndrome.h" 31 32 /* register banks for CPU modes */ 33 #define BANK_USRSYS 0 34 #define BANK_SVC 1 35 #define BANK_ABT 2 36 #define BANK_UND 3 37 #define BANK_IRQ 4 38 #define BANK_FIQ 5 39 #define BANK_HYP 6 40 #define BANK_MON 7 41 42 static inline bool excp_is_internal(int excp) 43 { 44 /* Return true if this exception number represents a QEMU-internal 45 * exception that will not be passed to the guest. 46 */ 47 return excp == EXCP_INTERRUPT 48 || excp == EXCP_HLT 49 || excp == EXCP_DEBUG 50 || excp == EXCP_HALTED 51 || excp == EXCP_EXCEPTION_EXIT 52 || excp == EXCP_KERNEL_TRAP 53 || excp == EXCP_SEMIHOST; 54 } 55 56 /* Scale factor for generic timers, ie number of ns per tick. 57 * This gives a 62.5MHz timer. 58 */ 59 #define GTIMER_SCALE 16 60 61 /* Bit definitions for the v7M CONTROL register */ 62 FIELD(V7M_CONTROL, NPRIV, 0, 1) 63 FIELD(V7M_CONTROL, SPSEL, 1, 1) 64 FIELD(V7M_CONTROL, FPCA, 2, 1) 65 FIELD(V7M_CONTROL, SFPA, 3, 1) 66 67 /* Bit definitions for v7M exception return payload */ 68 FIELD(V7M_EXCRET, ES, 0, 1) 69 FIELD(V7M_EXCRET, RES0, 1, 1) 70 FIELD(V7M_EXCRET, SPSEL, 2, 1) 71 FIELD(V7M_EXCRET, MODE, 3, 1) 72 FIELD(V7M_EXCRET, FTYPE, 4, 1) 73 FIELD(V7M_EXCRET, DCRS, 5, 1) 74 FIELD(V7M_EXCRET, S, 6, 1) 75 FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */ 76 77 /* Minimum value which is a magic number for exception return */ 78 #define EXC_RETURN_MIN_MAGIC 0xff000000 79 /* Minimum number which is a magic number for function or exception return 80 * when using v8M security extension 81 */ 82 #define FNC_RETURN_MIN_MAGIC 0xfefffffe 83 84 /* Bit definitions for DBGWCRn and DBGWCRn_EL1 */ 85 FIELD(DBGWCR, E, 0, 1) 86 FIELD(DBGWCR, PAC, 1, 2) 87 FIELD(DBGWCR, LSC, 3, 2) 88 FIELD(DBGWCR, BAS, 5, 8) 89 FIELD(DBGWCR, HMC, 13, 1) 90 FIELD(DBGWCR, SSC, 14, 2) 91 FIELD(DBGWCR, LBN, 16, 4) 92 FIELD(DBGWCR, WT, 20, 1) 93 FIELD(DBGWCR, MASK, 24, 5) 94 FIELD(DBGWCR, SSCE, 29, 1) 95 96 /* We use a few fake FSR values for internal purposes in M profile. 97 * M profile cores don't have A/R format FSRs, but currently our 98 * get_phys_addr() code assumes A/R profile and reports failures via 99 * an A/R format FSR value. We then translate that into the proper 100 * M profile exception and FSR status bit in arm_v7m_cpu_do_interrupt(). 101 * Mostly the FSR values we use for this are those defined for v7PMSA, 102 * since we share some of that codepath. A few kinds of fault are 103 * only for M profile and have no A/R equivalent, though, so we have 104 * to pick a value from the reserved range (which we never otherwise 105 * generate) to use for these. 106 * These values will never be visible to the guest. 107 */ 108 #define M_FAKE_FSR_NSC_EXEC 0xf /* NS executing in S&NSC memory */ 109 #define M_FAKE_FSR_SFAULT 0xe /* SecureFault INVTRAN, INVEP or AUVIOL */ 110 111 /** 112 * raise_exception: Raise the specified exception. 113 * Raise a guest exception with the specified value, syndrome register 114 * and target exception level. This should be called from helper functions, 115 * and never returns because we will longjump back up to the CPU main loop. 116 */ 117 G_NORETURN void raise_exception(CPUARMState *env, uint32_t excp, 118 uint32_t syndrome, uint32_t target_el); 119 120 /* 121 * Similarly, but also use unwinding to restore cpu state. 122 */ 123 G_NORETURN void raise_exception_ra(CPUARMState *env, uint32_t excp, 124 uint32_t syndrome, uint32_t target_el, 125 uintptr_t ra); 126 127 /* 128 * For AArch64, map a given EL to an index in the banked_spsr array. 129 * Note that this mapping and the AArch32 mapping defined in bank_number() 130 * must agree such that the AArch64<->AArch32 SPSRs have the architecturally 131 * mandated mapping between each other. 132 */ 133 static inline unsigned int aarch64_banked_spsr_index(unsigned int el) 134 { 135 static const unsigned int map[4] = { 136 [1] = BANK_SVC, /* EL1. */ 137 [2] = BANK_HYP, /* EL2. */ 138 [3] = BANK_MON, /* EL3. */ 139 }; 140 assert(el >= 1 && el <= 3); 141 return map[el]; 142 } 143 144 /* Map CPU modes onto saved register banks. */ 145 static inline int bank_number(int mode) 146 { 147 switch (mode) { 148 case ARM_CPU_MODE_USR: 149 case ARM_CPU_MODE_SYS: 150 return BANK_USRSYS; 151 case ARM_CPU_MODE_SVC: 152 return BANK_SVC; 153 case ARM_CPU_MODE_ABT: 154 return BANK_ABT; 155 case ARM_CPU_MODE_UND: 156 return BANK_UND; 157 case ARM_CPU_MODE_IRQ: 158 return BANK_IRQ; 159 case ARM_CPU_MODE_FIQ: 160 return BANK_FIQ; 161 case ARM_CPU_MODE_HYP: 162 return BANK_HYP; 163 case ARM_CPU_MODE_MON: 164 return BANK_MON; 165 } 166 g_assert_not_reached(); 167 } 168 169 /** 170 * r14_bank_number: Map CPU mode onto register bank for r14 171 * 172 * Given an AArch32 CPU mode, return the index into the saved register 173 * banks to use for the R14 (LR) in that mode. This is the same as 174 * bank_number(), except for the special case of Hyp mode, where 175 * R14 is shared with USR and SYS, unlike its R13 and SPSR. 176 * This should be used as the index into env->banked_r14[], and 177 * bank_number() used for the index into env->banked_r13[] and 178 * env->banked_spsr[]. 179 */ 180 static inline int r14_bank_number(int mode) 181 { 182 return (mode == ARM_CPU_MODE_HYP) ? BANK_USRSYS : bank_number(mode); 183 } 184 185 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu); 186 void arm_translate_init(void); 187 188 #ifdef CONFIG_TCG 189 void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); 190 #endif /* CONFIG_TCG */ 191 192 enum arm_fprounding { 193 FPROUNDING_TIEEVEN, 194 FPROUNDING_POSINF, 195 FPROUNDING_NEGINF, 196 FPROUNDING_ZERO, 197 FPROUNDING_TIEAWAY, 198 FPROUNDING_ODD 199 }; 200 201 int arm_rmode_to_sf(int rmode); 202 203 static inline void aarch64_save_sp(CPUARMState *env, int el) 204 { 205 if (env->pstate & PSTATE_SP) { 206 env->sp_el[el] = env->xregs[31]; 207 } else { 208 env->sp_el[0] = env->xregs[31]; 209 } 210 } 211 212 static inline void aarch64_restore_sp(CPUARMState *env, int el) 213 { 214 if (env->pstate & PSTATE_SP) { 215 env->xregs[31] = env->sp_el[el]; 216 } else { 217 env->xregs[31] = env->sp_el[0]; 218 } 219 } 220 221 static inline void update_spsel(CPUARMState *env, uint32_t imm) 222 { 223 unsigned int cur_el = arm_current_el(env); 224 /* Update PSTATE SPSel bit; this requires us to update the 225 * working stack pointer in xregs[31]. 226 */ 227 if (!((imm ^ env->pstate) & PSTATE_SP)) { 228 return; 229 } 230 aarch64_save_sp(env, cur_el); 231 env->pstate = deposit32(env->pstate, 0, 1, imm); 232 233 /* We rely on illegal updates to SPsel from EL0 to get trapped 234 * at translation time. 235 */ 236 assert(cur_el >= 1 && cur_el <= 3); 237 aarch64_restore_sp(env, cur_el); 238 } 239 240 /* 241 * arm_pamax 242 * @cpu: ARMCPU 243 * 244 * Returns the implementation defined bit-width of physical addresses. 245 * The ARMv8 reference manuals refer to this as PAMax(). 246 */ 247 unsigned int arm_pamax(ARMCPU *cpu); 248 249 /* Return true if extended addresses are enabled. 250 * This is always the case if our translation regime is 64 bit, 251 * but depends on TTBCR.EAE for 32 bit. 252 */ 253 static inline bool extended_addresses_enabled(CPUARMState *env) 254 { 255 TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1]; 256 return arm_el_is_aa64(env, 1) || 257 (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE)); 258 } 259 260 /* Update a QEMU watchpoint based on the information the guest has set in the 261 * DBGWCR<n>_EL1 and DBGWVR<n>_EL1 registers. 262 */ 263 void hw_watchpoint_update(ARMCPU *cpu, int n); 264 /* Update the QEMU watchpoints for every guest watchpoint. This does a 265 * complete delete-and-reinstate of the QEMU watchpoint list and so is 266 * suitable for use after migration or on reset. 267 */ 268 void hw_watchpoint_update_all(ARMCPU *cpu); 269 /* Update a QEMU breakpoint based on the information the guest has set in the 270 * DBGBCR<n>_EL1 and DBGBVR<n>_EL1 registers. 271 */ 272 void hw_breakpoint_update(ARMCPU *cpu, int n); 273 /* Update the QEMU breakpoints for every guest breakpoint. This does a 274 * complete delete-and-reinstate of the QEMU breakpoint list and so is 275 * suitable for use after migration or on reset. 276 */ 277 void hw_breakpoint_update_all(ARMCPU *cpu); 278 279 /* Callback function for checking if a breakpoint should trigger. */ 280 bool arm_debug_check_breakpoint(CPUState *cs); 281 282 /* Callback function for checking if a watchpoint should trigger. */ 283 bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); 284 285 /* Adjust addresses (in BE32 mode) before testing against watchpoint 286 * addresses. 287 */ 288 vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len); 289 290 /* Callback function for when a watchpoint or breakpoint triggers. */ 291 void arm_debug_excp_handler(CPUState *cs); 292 293 #if defined(CONFIG_USER_ONLY) || !defined(CONFIG_TCG) 294 static inline bool arm_is_psci_call(ARMCPU *cpu, int excp_type) 295 { 296 return false; 297 } 298 static inline void arm_handle_psci_call(ARMCPU *cpu) 299 { 300 g_assert_not_reached(); 301 } 302 #else 303 /* Return true if the r0/x0 value indicates that this SMC/HVC is a PSCI call. */ 304 bool arm_is_psci_call(ARMCPU *cpu, int excp_type); 305 /* Actually handle a PSCI call */ 306 void arm_handle_psci_call(ARMCPU *cpu); 307 #endif 308 309 /** 310 * arm_clear_exclusive: clear the exclusive monitor 311 * @env: CPU env 312 * Clear the CPU's exclusive monitor, like the guest CLREX instruction. 313 */ 314 static inline void arm_clear_exclusive(CPUARMState *env) 315 { 316 env->exclusive_addr = -1; 317 } 318 319 /** 320 * ARMFaultType: type of an ARM MMU fault 321 * This corresponds to the v8A pseudocode's Fault enumeration, 322 * with extensions for QEMU internal conditions. 323 */ 324 typedef enum ARMFaultType { 325 ARMFault_None, 326 ARMFault_AccessFlag, 327 ARMFault_Alignment, 328 ARMFault_Background, 329 ARMFault_Domain, 330 ARMFault_Permission, 331 ARMFault_Translation, 332 ARMFault_AddressSize, 333 ARMFault_SyncExternal, 334 ARMFault_SyncExternalOnWalk, 335 ARMFault_SyncParity, 336 ARMFault_SyncParityOnWalk, 337 ARMFault_AsyncParity, 338 ARMFault_AsyncExternal, 339 ARMFault_Debug, 340 ARMFault_TLBConflict, 341 ARMFault_Lockdown, 342 ARMFault_Exclusive, 343 ARMFault_ICacheMaint, 344 ARMFault_QEMU_NSCExec, /* v8M: NS executing in S&NSC memory */ 345 ARMFault_QEMU_SFault, /* v8M: SecureFault INVTRAN, INVEP or AUVIOL */ 346 } ARMFaultType; 347 348 /** 349 * ARMMMUFaultInfo: Information describing an ARM MMU Fault 350 * @type: Type of fault 351 * @level: Table walk level (for translation, access flag and permission faults) 352 * @domain: Domain of the fault address (for non-LPAE CPUs only) 353 * @s2addr: Address that caused a fault at stage 2 354 * @stage2: True if we faulted at stage 2 355 * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table walk 356 * @s1ns: True if we faulted on a non-secure IPA while in secure state 357 * @ea: True if we should set the EA (external abort type) bit in syndrome 358 */ 359 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; 360 struct ARMMMUFaultInfo { 361 ARMFaultType type; 362 target_ulong s2addr; 363 int level; 364 int domain; 365 bool stage2; 366 bool s1ptw; 367 bool s1ns; 368 bool ea; 369 }; 370 371 /** 372 * arm_fi_to_sfsc: Convert fault info struct to short-format FSC 373 * Compare pseudocode EncodeSDFSC(), though unlike that function 374 * we set up a whole FSR-format code including domain field and 375 * putting the high bit of the FSC into bit 10. 376 */ 377 static inline uint32_t arm_fi_to_sfsc(ARMMMUFaultInfo *fi) 378 { 379 uint32_t fsc; 380 381 switch (fi->type) { 382 case ARMFault_None: 383 return 0; 384 case ARMFault_AccessFlag: 385 fsc = fi->level == 1 ? 0x3 : 0x6; 386 break; 387 case ARMFault_Alignment: 388 fsc = 0x1; 389 break; 390 case ARMFault_Permission: 391 fsc = fi->level == 1 ? 0xd : 0xf; 392 break; 393 case ARMFault_Domain: 394 fsc = fi->level == 1 ? 0x9 : 0xb; 395 break; 396 case ARMFault_Translation: 397 fsc = fi->level == 1 ? 0x5 : 0x7; 398 break; 399 case ARMFault_SyncExternal: 400 fsc = 0x8 | (fi->ea << 12); 401 break; 402 case ARMFault_SyncExternalOnWalk: 403 fsc = fi->level == 1 ? 0xc : 0xe; 404 fsc |= (fi->ea << 12); 405 break; 406 case ARMFault_SyncParity: 407 fsc = 0x409; 408 break; 409 case ARMFault_SyncParityOnWalk: 410 fsc = fi->level == 1 ? 0x40c : 0x40e; 411 break; 412 case ARMFault_AsyncParity: 413 fsc = 0x408; 414 break; 415 case ARMFault_AsyncExternal: 416 fsc = 0x406 | (fi->ea << 12); 417 break; 418 case ARMFault_Debug: 419 fsc = 0x2; 420 break; 421 case ARMFault_TLBConflict: 422 fsc = 0x400; 423 break; 424 case ARMFault_Lockdown: 425 fsc = 0x404; 426 break; 427 case ARMFault_Exclusive: 428 fsc = 0x405; 429 break; 430 case ARMFault_ICacheMaint: 431 fsc = 0x4; 432 break; 433 case ARMFault_Background: 434 fsc = 0x0; 435 break; 436 case ARMFault_QEMU_NSCExec: 437 fsc = M_FAKE_FSR_NSC_EXEC; 438 break; 439 case ARMFault_QEMU_SFault: 440 fsc = M_FAKE_FSR_SFAULT; 441 break; 442 default: 443 /* Other faults can't occur in a context that requires a 444 * short-format status code. 445 */ 446 g_assert_not_reached(); 447 } 448 449 fsc |= (fi->domain << 4); 450 return fsc; 451 } 452 453 /** 454 * arm_fi_to_lfsc: Convert fault info struct to long-format FSC 455 * Compare pseudocode EncodeLDFSC(), though unlike that function 456 * we fill in also the LPAE bit 9 of a DFSR format. 457 */ 458 static inline uint32_t arm_fi_to_lfsc(ARMMMUFaultInfo *fi) 459 { 460 uint32_t fsc; 461 462 switch (fi->type) { 463 case ARMFault_None: 464 return 0; 465 case ARMFault_AddressSize: 466 assert(fi->level >= -1 && fi->level <= 3); 467 if (fi->level < 0) { 468 fsc = 0b101001; 469 } else { 470 fsc = fi->level; 471 } 472 break; 473 case ARMFault_AccessFlag: 474 assert(fi->level >= 0 && fi->level <= 3); 475 fsc = 0b001000 | fi->level; 476 break; 477 case ARMFault_Permission: 478 assert(fi->level >= 0 && fi->level <= 3); 479 fsc = 0b001100 | fi->level; 480 break; 481 case ARMFault_Translation: 482 assert(fi->level >= -1 && fi->level <= 3); 483 if (fi->level < 0) { 484 fsc = 0b101011; 485 } else { 486 fsc = 0b000100 | fi->level; 487 } 488 break; 489 case ARMFault_SyncExternal: 490 fsc = 0x10 | (fi->ea << 12); 491 break; 492 case ARMFault_SyncExternalOnWalk: 493 assert(fi->level >= -1 && fi->level <= 3); 494 if (fi->level < 0) { 495 fsc = 0b010011; 496 } else { 497 fsc = 0b010100 | fi->level; 498 } 499 fsc |= fi->ea << 12; 500 break; 501 case ARMFault_SyncParity: 502 fsc = 0x18; 503 break; 504 case ARMFault_SyncParityOnWalk: 505 assert(fi->level >= -1 && fi->level <= 3); 506 if (fi->level < 0) { 507 fsc = 0b011011; 508 } else { 509 fsc = 0b011100 | fi->level; 510 } 511 break; 512 case ARMFault_AsyncParity: 513 fsc = 0x19; 514 break; 515 case ARMFault_AsyncExternal: 516 fsc = 0x11 | (fi->ea << 12); 517 break; 518 case ARMFault_Alignment: 519 fsc = 0x21; 520 break; 521 case ARMFault_Debug: 522 fsc = 0x22; 523 break; 524 case ARMFault_TLBConflict: 525 fsc = 0x30; 526 break; 527 case ARMFault_Lockdown: 528 fsc = 0x34; 529 break; 530 case ARMFault_Exclusive: 531 fsc = 0x35; 532 break; 533 default: 534 /* Other faults can't occur in a context that requires a 535 * long-format status code. 536 */ 537 g_assert_not_reached(); 538 } 539 540 fsc |= 1 << 9; 541 return fsc; 542 } 543 544 static inline bool arm_extabort_type(MemTxResult result) 545 { 546 /* The EA bit in syndromes and fault status registers is an 547 * IMPDEF classification of external aborts. ARM implementations 548 * usually use this to indicate AXI bus Decode error (0) or 549 * Slave error (1); in QEMU we follow that. 550 */ 551 return result != MEMTX_DECODE_ERROR; 552 } 553 554 #ifdef CONFIG_USER_ONLY 555 void arm_cpu_record_sigsegv(CPUState *cpu, vaddr addr, 556 MMUAccessType access_type, 557 bool maperr, uintptr_t ra); 558 void arm_cpu_record_sigbus(CPUState *cpu, vaddr addr, 559 MMUAccessType access_type, uintptr_t ra); 560 #else 561 bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 562 MMUAccessType access_type, int mmu_idx, 563 bool probe, uintptr_t retaddr); 564 #endif 565 566 static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) 567 { 568 return mmu_idx & ARM_MMU_IDX_COREIDX_MASK; 569 } 570 571 static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx) 572 { 573 if (arm_feature(env, ARM_FEATURE_M)) { 574 return mmu_idx | ARM_MMU_IDX_M; 575 } else { 576 return mmu_idx | ARM_MMU_IDX_A; 577 } 578 } 579 580 static inline ARMMMUIdx core_to_aa64_mmu_idx(int mmu_idx) 581 { 582 /* AArch64 is always a-profile. */ 583 return mmu_idx | ARM_MMU_IDX_A; 584 } 585 586 int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx); 587 588 /* 589 * Return the MMU index for a v7M CPU with all relevant information 590 * manually specified. 591 */ 592 ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, 593 bool secstate, bool priv, bool negpri); 594 595 /* 596 * Return the MMU index for a v7M CPU in the specified security and 597 * privilege state. 598 */ 599 ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, 600 bool secstate, bool priv); 601 602 /* Return the MMU index for a v7M CPU in the specified security state */ 603 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); 604 605 /* Return true if the translation regime is using LPAE format page tables */ 606 bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx); 607 608 /* 609 * Return true if the stage 1 translation regime is using LPAE 610 * format page tables 611 */ 612 bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx); 613 614 /* Raise a data fault alignment exception for the specified virtual address */ 615 G_NORETURN void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, 616 MMUAccessType access_type, 617 int mmu_idx, uintptr_t retaddr); 618 619 /* arm_cpu_do_transaction_failed: handle a memory system error response 620 * (eg "no device/memory present at address") by raising an external abort 621 * exception 622 */ 623 void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 624 vaddr addr, unsigned size, 625 MMUAccessType access_type, 626 int mmu_idx, MemTxAttrs attrs, 627 MemTxResult response, uintptr_t retaddr); 628 629 /* Call any registered EL change hooks */ 630 static inline void arm_call_pre_el_change_hook(ARMCPU *cpu) 631 { 632 ARMELChangeHook *hook, *next; 633 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 634 hook->hook(cpu, hook->opaque); 635 } 636 } 637 static inline void arm_call_el_change_hook(ARMCPU *cpu) 638 { 639 ARMELChangeHook *hook, *next; 640 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 641 hook->hook(cpu, hook->opaque); 642 } 643 } 644 645 /* Return true if this address translation regime has two ranges. */ 646 static inline bool regime_has_2_ranges(ARMMMUIdx mmu_idx) 647 { 648 switch (mmu_idx) { 649 case ARMMMUIdx_Stage1_E0: 650 case ARMMMUIdx_Stage1_E1: 651 case ARMMMUIdx_Stage1_E1_PAN: 652 case ARMMMUIdx_Stage1_SE0: 653 case ARMMMUIdx_Stage1_SE1: 654 case ARMMMUIdx_Stage1_SE1_PAN: 655 case ARMMMUIdx_E10_0: 656 case ARMMMUIdx_E10_1: 657 case ARMMMUIdx_E10_1_PAN: 658 case ARMMMUIdx_E20_0: 659 case ARMMMUIdx_E20_2: 660 case ARMMMUIdx_E20_2_PAN: 661 case ARMMMUIdx_SE10_0: 662 case ARMMMUIdx_SE10_1: 663 case ARMMMUIdx_SE10_1_PAN: 664 case ARMMMUIdx_SE20_0: 665 case ARMMMUIdx_SE20_2: 666 case ARMMMUIdx_SE20_2_PAN: 667 return true; 668 default: 669 return false; 670 } 671 } 672 673 /* Return true if this address translation regime is secure */ 674 static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) 675 { 676 switch (mmu_idx) { 677 case ARMMMUIdx_E10_0: 678 case ARMMMUIdx_E10_1: 679 case ARMMMUIdx_E10_1_PAN: 680 case ARMMMUIdx_E20_0: 681 case ARMMMUIdx_E20_2: 682 case ARMMMUIdx_E20_2_PAN: 683 case ARMMMUIdx_Stage1_E0: 684 case ARMMMUIdx_Stage1_E1: 685 case ARMMMUIdx_Stage1_E1_PAN: 686 case ARMMMUIdx_E2: 687 case ARMMMUIdx_Stage2: 688 case ARMMMUIdx_MPrivNegPri: 689 case ARMMMUIdx_MUserNegPri: 690 case ARMMMUIdx_MPriv: 691 case ARMMMUIdx_MUser: 692 return false; 693 case ARMMMUIdx_SE3: 694 case ARMMMUIdx_SE10_0: 695 case ARMMMUIdx_SE10_1: 696 case ARMMMUIdx_SE10_1_PAN: 697 case ARMMMUIdx_SE20_0: 698 case ARMMMUIdx_SE20_2: 699 case ARMMMUIdx_SE20_2_PAN: 700 case ARMMMUIdx_Stage1_SE0: 701 case ARMMMUIdx_Stage1_SE1: 702 case ARMMMUIdx_Stage1_SE1_PAN: 703 case ARMMMUIdx_SE2: 704 case ARMMMUIdx_Stage2_S: 705 case ARMMMUIdx_MSPrivNegPri: 706 case ARMMMUIdx_MSUserNegPri: 707 case ARMMMUIdx_MSPriv: 708 case ARMMMUIdx_MSUser: 709 return true; 710 default: 711 g_assert_not_reached(); 712 } 713 } 714 715 static inline bool regime_is_pan(CPUARMState *env, ARMMMUIdx mmu_idx) 716 { 717 switch (mmu_idx) { 718 case ARMMMUIdx_Stage1_E1_PAN: 719 case ARMMMUIdx_Stage1_SE1_PAN: 720 case ARMMMUIdx_E10_1_PAN: 721 case ARMMMUIdx_E20_2_PAN: 722 case ARMMMUIdx_SE10_1_PAN: 723 case ARMMMUIdx_SE20_2_PAN: 724 return true; 725 default: 726 return false; 727 } 728 } 729 730 /* Return the exception level which controls this address translation regime */ 731 static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) 732 { 733 switch (mmu_idx) { 734 case ARMMMUIdx_SE20_0: 735 case ARMMMUIdx_SE20_2: 736 case ARMMMUIdx_SE20_2_PAN: 737 case ARMMMUIdx_E20_0: 738 case ARMMMUIdx_E20_2: 739 case ARMMMUIdx_E20_2_PAN: 740 case ARMMMUIdx_Stage2: 741 case ARMMMUIdx_Stage2_S: 742 case ARMMMUIdx_SE2: 743 case ARMMMUIdx_E2: 744 return 2; 745 case ARMMMUIdx_SE3: 746 return 3; 747 case ARMMMUIdx_SE10_0: 748 case ARMMMUIdx_Stage1_SE0: 749 return arm_el_is_aa64(env, 3) ? 1 : 3; 750 case ARMMMUIdx_SE10_1: 751 case ARMMMUIdx_SE10_1_PAN: 752 case ARMMMUIdx_Stage1_E0: 753 case ARMMMUIdx_Stage1_E1: 754 case ARMMMUIdx_Stage1_E1_PAN: 755 case ARMMMUIdx_Stage1_SE1: 756 case ARMMMUIdx_Stage1_SE1_PAN: 757 case ARMMMUIdx_E10_0: 758 case ARMMMUIdx_E10_1: 759 case ARMMMUIdx_E10_1_PAN: 760 case ARMMMUIdx_MPrivNegPri: 761 case ARMMMUIdx_MUserNegPri: 762 case ARMMMUIdx_MPriv: 763 case ARMMMUIdx_MUser: 764 case ARMMMUIdx_MSPrivNegPri: 765 case ARMMMUIdx_MSUserNegPri: 766 case ARMMMUIdx_MSPriv: 767 case ARMMMUIdx_MSUser: 768 return 1; 769 default: 770 g_assert_not_reached(); 771 } 772 } 773 774 /* Return the SCTLR value which controls this address translation regime */ 775 static inline uint64_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) 776 { 777 return env->cp15.sctlr_el[regime_el(env, mmu_idx)]; 778 } 779 780 /* Return the TCR controlling this translation regime */ 781 static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) 782 { 783 if (mmu_idx == ARMMMUIdx_Stage2) { 784 return &env->cp15.vtcr_el2; 785 } 786 if (mmu_idx == ARMMMUIdx_Stage2_S) { 787 /* 788 * Note: Secure stage 2 nominally shares fields from VTCR_EL2, but 789 * those are not currently used by QEMU, so just return VSTCR_EL2. 790 */ 791 return &env->cp15.vstcr_el2; 792 } 793 return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; 794 } 795 796 /** 797 * arm_num_brps: Return number of implemented breakpoints. 798 * Note that the ID register BRPS field is "number of bps - 1", 799 * and we return the actual number of breakpoints. 800 */ 801 static inline int arm_num_brps(ARMCPU *cpu) 802 { 803 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 804 return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, BRPS) + 1; 805 } else { 806 return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, BRPS) + 1; 807 } 808 } 809 810 /** 811 * arm_num_wrps: Return number of implemented watchpoints. 812 * Note that the ID register WRPS field is "number of wps - 1", 813 * and we return the actual number of watchpoints. 814 */ 815 static inline int arm_num_wrps(ARMCPU *cpu) 816 { 817 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 818 return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, WRPS) + 1; 819 } else { 820 return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, WRPS) + 1; 821 } 822 } 823 824 /** 825 * arm_num_ctx_cmps: Return number of implemented context comparators. 826 * Note that the ID register CTX_CMPS field is "number of cmps - 1", 827 * and we return the actual number of comparators. 828 */ 829 static inline int arm_num_ctx_cmps(ARMCPU *cpu) 830 { 831 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 832 return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) + 1; 833 } else { 834 return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, CTX_CMPS) + 1; 835 } 836 } 837 838 /** 839 * v7m_using_psp: Return true if using process stack pointer 840 * Return true if the CPU is currently using the process stack 841 * pointer, or false if it is using the main stack pointer. 842 */ 843 static inline bool v7m_using_psp(CPUARMState *env) 844 { 845 /* Handler mode always uses the main stack; for thread mode 846 * the CONTROL.SPSEL bit determines the answer. 847 * Note that in v7M it is not possible to be in Handler mode with 848 * CONTROL.SPSEL non-zero, but in v8M it is, so we must check both. 849 */ 850 return !arm_v7m_is_handler_mode(env) && 851 env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK; 852 } 853 854 /** 855 * v7m_sp_limit: Return SP limit for current CPU state 856 * Return the SP limit value for the current CPU security state 857 * and stack pointer. 858 */ 859 static inline uint32_t v7m_sp_limit(CPUARMState *env) 860 { 861 if (v7m_using_psp(env)) { 862 return env->v7m.psplim[env->v7m.secure]; 863 } else { 864 return env->v7m.msplim[env->v7m.secure]; 865 } 866 } 867 868 /** 869 * v7m_cpacr_pass: 870 * Return true if the v7M CPACR permits access to the FPU for the specified 871 * security state and privilege level. 872 */ 873 static inline bool v7m_cpacr_pass(CPUARMState *env, 874 bool is_secure, bool is_priv) 875 { 876 switch (extract32(env->v7m.cpacr[is_secure], 20, 2)) { 877 case 0: 878 case 2: /* UNPREDICTABLE: we treat like 0 */ 879 return false; 880 case 1: 881 return is_priv; 882 case 3: 883 return true; 884 default: 885 g_assert_not_reached(); 886 } 887 } 888 889 /** 890 * aarch32_mode_name(): Return name of the AArch32 CPU mode 891 * @psr: Program Status Register indicating CPU mode 892 * 893 * Returns, for debug logging purposes, a printable representation 894 * of the AArch32 CPU mode ("svc", "usr", etc) as indicated by 895 * the low bits of the specified PSR. 896 */ 897 static inline const char *aarch32_mode_name(uint32_t psr) 898 { 899 static const char cpu_mode_names[16][4] = { 900 "usr", "fiq", "irq", "svc", "???", "???", "mon", "abt", 901 "???", "???", "hyp", "und", "???", "???", "???", "sys" 902 }; 903 904 return cpu_mode_names[psr & 0xf]; 905 } 906 907 /** 908 * arm_cpu_update_virq: Update CPU_INTERRUPT_VIRQ bit in cs->interrupt_request 909 * 910 * Update the CPU_INTERRUPT_VIRQ bit in cs->interrupt_request, following 911 * a change to either the input VIRQ line from the GIC or the HCR_EL2.VI bit. 912 * Must be called with the iothread lock held. 913 */ 914 void arm_cpu_update_virq(ARMCPU *cpu); 915 916 /** 917 * arm_cpu_update_vfiq: Update CPU_INTERRUPT_VFIQ bit in cs->interrupt_request 918 * 919 * Update the CPU_INTERRUPT_VFIQ bit in cs->interrupt_request, following 920 * a change to either the input VFIQ line from the GIC or the HCR_EL2.VF bit. 921 * Must be called with the iothread lock held. 922 */ 923 void arm_cpu_update_vfiq(ARMCPU *cpu); 924 925 /** 926 * arm_cpu_update_vserr: Update CPU_INTERRUPT_VSERR bit 927 * 928 * Update the CPU_INTERRUPT_VSERR bit in cs->interrupt_request, 929 * following a change to the HCR_EL2.VSE bit. 930 */ 931 void arm_cpu_update_vserr(ARMCPU *cpu); 932 933 /** 934 * arm_mmu_idx_el: 935 * @env: The cpu environment 936 * @el: The EL to use. 937 * 938 * Return the full ARMMMUIdx for the translation regime for EL. 939 */ 940 ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el); 941 942 /** 943 * arm_mmu_idx: 944 * @env: The cpu environment 945 * 946 * Return the full ARMMMUIdx for the current translation regime. 947 */ 948 ARMMMUIdx arm_mmu_idx(CPUARMState *env); 949 950 /** 951 * arm_stage1_mmu_idx: 952 * @env: The cpu environment 953 * 954 * Return the ARMMMUIdx for the stage1 traversal for the current regime. 955 */ 956 #ifdef CONFIG_USER_ONLY 957 static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) 958 { 959 return ARMMMUIdx_Stage1_E0; 960 } 961 static inline ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) 962 { 963 return ARMMMUIdx_Stage1_E0; 964 } 965 #else 966 ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx); 967 ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env); 968 #endif 969 970 /** 971 * arm_mmu_idx_is_stage1_of_2: 972 * @mmu_idx: The ARMMMUIdx to test 973 * 974 * Return true if @mmu_idx is a NOTLB mmu_idx that is the 975 * first stage of a two stage regime. 976 */ 977 static inline bool arm_mmu_idx_is_stage1_of_2(ARMMMUIdx mmu_idx) 978 { 979 switch (mmu_idx) { 980 case ARMMMUIdx_Stage1_E0: 981 case ARMMMUIdx_Stage1_E1: 982 case ARMMMUIdx_Stage1_E1_PAN: 983 case ARMMMUIdx_Stage1_SE0: 984 case ARMMMUIdx_Stage1_SE1: 985 case ARMMMUIdx_Stage1_SE1_PAN: 986 return true; 987 default: 988 return false; 989 } 990 } 991 992 static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features, 993 const ARMISARegisters *id) 994 { 995 uint32_t valid = CPSR_M | CPSR_AIF | CPSR_IL | CPSR_NZCV; 996 997 if ((features >> ARM_FEATURE_V4T) & 1) { 998 valid |= CPSR_T; 999 } 1000 if ((features >> ARM_FEATURE_V5) & 1) { 1001 valid |= CPSR_Q; /* V5TE in reality*/ 1002 } 1003 if ((features >> ARM_FEATURE_V6) & 1) { 1004 valid |= CPSR_E | CPSR_GE; 1005 } 1006 if ((features >> ARM_FEATURE_THUMB2) & 1) { 1007 valid |= CPSR_IT; 1008 } 1009 if (isar_feature_aa32_jazelle(id)) { 1010 valid |= CPSR_J; 1011 } 1012 if (isar_feature_aa32_pan(id)) { 1013 valid |= CPSR_PAN; 1014 } 1015 if (isar_feature_aa32_dit(id)) { 1016 valid |= CPSR_DIT; 1017 } 1018 if (isar_feature_aa32_ssbs(id)) { 1019 valid |= CPSR_SSBS; 1020 } 1021 1022 return valid; 1023 } 1024 1025 static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id) 1026 { 1027 uint32_t valid; 1028 1029 valid = PSTATE_M | PSTATE_DAIF | PSTATE_IL | PSTATE_SS | PSTATE_NZCV; 1030 if (isar_feature_aa64_bti(id)) { 1031 valid |= PSTATE_BTYPE; 1032 } 1033 if (isar_feature_aa64_pan(id)) { 1034 valid |= PSTATE_PAN; 1035 } 1036 if (isar_feature_aa64_uao(id)) { 1037 valid |= PSTATE_UAO; 1038 } 1039 if (isar_feature_aa64_dit(id)) { 1040 valid |= PSTATE_DIT; 1041 } 1042 if (isar_feature_aa64_ssbs(id)) { 1043 valid |= PSTATE_SSBS; 1044 } 1045 if (isar_feature_aa64_mte(id)) { 1046 valid |= PSTATE_TCO; 1047 } 1048 1049 return valid; 1050 } 1051 1052 /* 1053 * Parameters of a given virtual address, as extracted from the 1054 * translation control register (TCR) for a given regime. 1055 */ 1056 typedef struct ARMVAParameters { 1057 unsigned tsz : 8; 1058 unsigned ps : 3; 1059 unsigned sh : 2; 1060 unsigned select : 1; 1061 bool tbi : 1; 1062 bool epd : 1; 1063 bool hpd : 1; 1064 bool using16k : 1; 1065 bool using64k : 1; 1066 bool tsz_oob : 1; /* tsz has been clamped to legal range */ 1067 bool ds : 1; 1068 } ARMVAParameters; 1069 1070 ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, 1071 ARMMMUIdx mmu_idx, bool data); 1072 1073 int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx); 1074 int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx); 1075 1076 /* Determine if allocation tags are available. */ 1077 static inline bool allocation_tag_access_enabled(CPUARMState *env, int el, 1078 uint64_t sctlr) 1079 { 1080 if (el < 3 1081 && arm_feature(env, ARM_FEATURE_EL3) 1082 && !(env->cp15.scr_el3 & SCR_ATA)) { 1083 return false; 1084 } 1085 if (el < 2 && arm_is_el2_enabled(env)) { 1086 uint64_t hcr = arm_hcr_el2_eff(env); 1087 if (!(hcr & HCR_ATA) && (!(hcr & HCR_E2H) || !(hcr & HCR_TGE))) { 1088 return false; 1089 } 1090 } 1091 sctlr &= (el == 0 ? SCTLR_ATA0 : SCTLR_ATA); 1092 return sctlr != 0; 1093 } 1094 1095 #ifndef CONFIG_USER_ONLY 1096 1097 /* Security attributes for an address, as returned by v8m_security_lookup. */ 1098 typedef struct V8M_SAttributes { 1099 bool subpage; /* true if these attrs don't cover the whole TARGET_PAGE */ 1100 bool ns; 1101 bool nsc; 1102 uint8_t sregion; 1103 bool srvalid; 1104 uint8_t iregion; 1105 bool irvalid; 1106 } V8M_SAttributes; 1107 1108 void v8m_security_lookup(CPUARMState *env, uint32_t address, 1109 MMUAccessType access_type, ARMMMUIdx mmu_idx, 1110 V8M_SAttributes *sattrs); 1111 1112 bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, 1113 MMUAccessType access_type, ARMMMUIdx mmu_idx, 1114 hwaddr *phys_ptr, MemTxAttrs *txattrs, 1115 int *prot, bool *is_subpage, 1116 ARMMMUFaultInfo *fi, uint32_t *mregion); 1117 1118 /* Cacheability and shareability attributes for a memory access */ 1119 typedef struct ARMCacheAttrs { 1120 /* 1121 * If is_s2_format is true, attrs is the S2 descriptor bits [5:2] 1122 * Otherwise, attrs is the same as the MAIR_EL1 8-bit format 1123 */ 1124 unsigned int attrs:8; 1125 unsigned int shareability:2; /* as in the SH field of the VMSAv8-64 PTEs */ 1126 bool is_s2_format:1; 1127 } ARMCacheAttrs; 1128 1129 bool get_phys_addr(CPUARMState *env, target_ulong address, 1130 MMUAccessType access_type, ARMMMUIdx mmu_idx, 1131 hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, 1132 target_ulong *page_size, 1133 ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) 1134 __attribute__((nonnull)); 1135 1136 void arm_log_exception(CPUState *cs); 1137 1138 #endif /* !CONFIG_USER_ONLY */ 1139 1140 /* 1141 * The log2 of the words in the tag block, for GMID_EL1.BS. 1142 * The is the maximum, 256 bytes, which manipulates 64-bits of tags. 1143 */ 1144 #define GMID_EL1_BS 6 1145 1146 /* We associate one allocation tag per 16 bytes, the minimum. */ 1147 #define LOG2_TAG_GRANULE 4 1148 #define TAG_GRANULE (1 << LOG2_TAG_GRANULE) 1149 1150 /* 1151 * SVE predicates are 1/8 the size of SVE vectors, and cannot use 1152 * the same simd_desc() encoding due to restrictions on size. 1153 * Use these instead. 1154 */ 1155 FIELD(PREDDESC, OPRSZ, 0, 6) 1156 FIELD(PREDDESC, ESZ, 6, 2) 1157 FIELD(PREDDESC, DATA, 8, 24) 1158 1159 /* 1160 * The SVE simd_data field, for memory ops, contains either 1161 * rd (5 bits) or a shift count (2 bits). 1162 */ 1163 #define SVE_MTEDESC_SHIFT 5 1164 1165 /* Bits within a descriptor passed to the helper_mte_check* functions. */ 1166 FIELD(MTEDESC, MIDX, 0, 4) 1167 FIELD(MTEDESC, TBI, 4, 2) 1168 FIELD(MTEDESC, TCMA, 6, 2) 1169 FIELD(MTEDESC, WRITE, 8, 1) 1170 FIELD(MTEDESC, SIZEM1, 9, SIMD_DATA_BITS - 9) /* size - 1 */ 1171 1172 bool mte_probe(CPUARMState *env, uint32_t desc, uint64_t ptr); 1173 uint64_t mte_check(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_t ra); 1174 1175 static inline int allocation_tag_from_addr(uint64_t ptr) 1176 { 1177 return extract64(ptr, 56, 4); 1178 } 1179 1180 static inline uint64_t address_with_allocation_tag(uint64_t ptr, int rtag) 1181 { 1182 return deposit64(ptr, 56, 4, rtag); 1183 } 1184 1185 /* Return true if tbi bits mean that the access is checked. */ 1186 static inline bool tbi_check(uint32_t desc, int bit55) 1187 { 1188 return (desc >> (R_MTEDESC_TBI_SHIFT + bit55)) & 1; 1189 } 1190 1191 /* Return true if tcma bits mean that the access is unchecked. */ 1192 static inline bool tcma_check(uint32_t desc, int bit55, int ptr_tag) 1193 { 1194 /* 1195 * We had extracted bit55 and ptr_tag for other reasons, so fold 1196 * (ptr<59:55> == 00000 || ptr<59:55> == 11111) into a single test. 1197 */ 1198 bool match = ((ptr_tag + bit55) & 0xf) == 0; 1199 bool tcma = (desc >> (R_MTEDESC_TCMA_SHIFT + bit55)) & 1; 1200 return tcma && match; 1201 } 1202 1203 /* 1204 * For TBI, ideally, we would do nothing. Proper behaviour on fault is 1205 * for the tag to be present in the FAR_ELx register. But for user-only 1206 * mode, we do not have a TLB with which to implement this, so we must 1207 * remove the top byte. 1208 */ 1209 static inline uint64_t useronly_clean_ptr(uint64_t ptr) 1210 { 1211 #ifdef CONFIG_USER_ONLY 1212 /* TBI0 is known to be enabled, while TBI1 is disabled. */ 1213 ptr &= sextract64(ptr, 0, 56); 1214 #endif 1215 return ptr; 1216 } 1217 1218 static inline uint64_t useronly_maybe_clean_ptr(uint32_t desc, uint64_t ptr) 1219 { 1220 #ifdef CONFIG_USER_ONLY 1221 int64_t clean_ptr = sextract64(ptr, 0, 56); 1222 if (tbi_check(desc, clean_ptr < 0)) { 1223 ptr = clean_ptr; 1224 } 1225 #endif 1226 return ptr; 1227 } 1228 1229 /* Values for M-profile PSR.ECI for MVE insns */ 1230 enum MVEECIState { 1231 ECI_NONE = 0, /* No completed beats */ 1232 ECI_A0 = 1, /* Completed: A0 */ 1233 ECI_A0A1 = 2, /* Completed: A0, A1 */ 1234 /* 3 is reserved */ 1235 ECI_A0A1A2 = 4, /* Completed: A0, A1, A2 */ 1236 ECI_A0A1A2B0 = 5, /* Completed: A0, A1, A2, B0 */ 1237 /* All other values reserved */ 1238 }; 1239 1240 /* Definitions for the PMU registers */ 1241 #define PMCRN_MASK 0xf800 1242 #define PMCRN_SHIFT 11 1243 #define PMCRLC 0x40 1244 #define PMCRDP 0x20 1245 #define PMCRX 0x10 1246 #define PMCRD 0x8 1247 #define PMCRC 0x4 1248 #define PMCRP 0x2 1249 #define PMCRE 0x1 1250 /* 1251 * Mask of PMCR bits writable by guest (not including WO bits like C, P, 1252 * which can be written as 1 to trigger behaviour but which stay RAZ). 1253 */ 1254 #define PMCR_WRITABLE_MASK (PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE) 1255 1256 #define PMXEVTYPER_P 0x80000000 1257 #define PMXEVTYPER_U 0x40000000 1258 #define PMXEVTYPER_NSK 0x20000000 1259 #define PMXEVTYPER_NSU 0x10000000 1260 #define PMXEVTYPER_NSH 0x08000000 1261 #define PMXEVTYPER_M 0x04000000 1262 #define PMXEVTYPER_MT 0x02000000 1263 #define PMXEVTYPER_EVTCOUNT 0x0000ffff 1264 #define PMXEVTYPER_MASK (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NSK | \ 1265 PMXEVTYPER_NSU | PMXEVTYPER_NSH | \ 1266 PMXEVTYPER_M | PMXEVTYPER_MT | \ 1267 PMXEVTYPER_EVTCOUNT) 1268 1269 #define PMCCFILTR 0xf8000000 1270 #define PMCCFILTR_M PMXEVTYPER_M 1271 #define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M) 1272 1273 static inline uint32_t pmu_num_counters(CPUARMState *env) 1274 { 1275 ARMCPU *cpu = env_archcpu(env); 1276 1277 return (cpu->isar.reset_pmcr_el0 & PMCRN_MASK) >> PMCRN_SHIFT; 1278 } 1279 1280 /* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */ 1281 static inline uint64_t pmu_counter_mask(CPUARMState *env) 1282 { 1283 return (1 << 31) | ((1 << pmu_num_counters(env)) - 1); 1284 } 1285 1286 #ifdef TARGET_AARCH64 1287 int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg); 1288 int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg); 1289 int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg); 1290 int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg); 1291 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); 1292 void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp); 1293 void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); 1294 void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp); 1295 #endif 1296 1297 #ifdef CONFIG_USER_ONLY 1298 static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { } 1299 #else 1300 void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); 1301 #endif 1302 1303 bool el_is_in_host(CPUARMState *env, int el); 1304 1305 void aa32_max_features(ARMCPU *cpu); 1306 int exception_target_el(CPUARMState *env); 1307 bool arm_singlestep_active(CPUARMState *env); 1308 bool arm_generate_debug_exceptions(CPUARMState *env); 1309 1310 /* Powers of 2 for sve_vq_map et al. */ 1311 #define SVE_VQ_POW2_MAP \ 1312 ((1 << (1 - 1)) | (1 << (2 - 1)) | \ 1313 (1 << (4 - 1)) | (1 << (8 - 1)) | (1 << (16 - 1))) 1314 1315 #endif 1316