1 /* 2 * QEMU ARM CPU -- internal functions and types 3 * 4 * Copyright (c) 2014 Linaro Ltd 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 * 20 * This header defines functions, types, etc which need to be shared 21 * between different source files within target/arm/ but which are 22 * private to it and not required by the rest of QEMU. 23 */ 24 25 #ifndef TARGET_ARM_INTERNALS_H 26 #define TARGET_ARM_INTERNALS_H 27 28 #include "hw/registerfields.h" 29 30 /* register banks for CPU modes */ 31 #define BANK_USRSYS 0 32 #define BANK_SVC 1 33 #define BANK_ABT 2 34 #define BANK_UND 3 35 #define BANK_IRQ 4 36 #define BANK_FIQ 5 37 #define BANK_HYP 6 38 #define BANK_MON 7 39 40 static inline bool excp_is_internal(int excp) 41 { 42 /* Return true if this exception number represents a QEMU-internal 43 * exception that will not be passed to the guest. 44 */ 45 return excp == EXCP_INTERRUPT 46 || excp == EXCP_HLT 47 || excp == EXCP_DEBUG 48 || excp == EXCP_HALTED 49 || excp == EXCP_EXCEPTION_EXIT 50 || excp == EXCP_KERNEL_TRAP 51 || excp == EXCP_SEMIHOST; 52 } 53 54 /* Exception names for debug logging; note that not all of these 55 * precisely correspond to architectural exceptions. 56 */ 57 static const char * const excnames[] = { 58 [EXCP_UDEF] = "Undefined Instruction", 59 [EXCP_SWI] = "SVC", 60 [EXCP_PREFETCH_ABORT] = "Prefetch Abort", 61 [EXCP_DATA_ABORT] = "Data Abort", 62 [EXCP_IRQ] = "IRQ", 63 [EXCP_FIQ] = "FIQ", 64 [EXCP_BKPT] = "Breakpoint", 65 [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit", 66 [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage", 67 [EXCP_HVC] = "Hypervisor Call", 68 [EXCP_HYP_TRAP] = "Hypervisor Trap", 69 [EXCP_SMC] = "Secure Monitor Call", 70 [EXCP_VIRQ] = "Virtual IRQ", 71 [EXCP_VFIQ] = "Virtual FIQ", 72 [EXCP_SEMIHOST] = "Semihosting call", 73 }; 74 75 /* Scale factor for generic timers, ie number of ns per tick. 76 * This gives a 62.5MHz timer. 77 */ 78 #define GTIMER_SCALE 16 79 80 /* Bit definitions for the v7M CONTROL register */ 81 FIELD(V7M_CONTROL, NPRIV, 0, 1) 82 FIELD(V7M_CONTROL, SPSEL, 1, 1) 83 FIELD(V7M_CONTROL, FPCA, 2, 1) 84 85 /* 86 * For AArch64, map a given EL to an index in the banked_spsr array. 87 * Note that this mapping and the AArch32 mapping defined in bank_number() 88 * must agree such that the AArch64<->AArch32 SPSRs have the architecturally 89 * mandated mapping between each other. 90 */ 91 static inline unsigned int aarch64_banked_spsr_index(unsigned int el) 92 { 93 static const unsigned int map[4] = { 94 [1] = BANK_SVC, /* EL1. */ 95 [2] = BANK_HYP, /* EL2. */ 96 [3] = BANK_MON, /* EL3. */ 97 }; 98 assert(el >= 1 && el <= 3); 99 return map[el]; 100 } 101 102 /* Map CPU modes onto saved register banks. */ 103 static inline int bank_number(int mode) 104 { 105 switch (mode) { 106 case ARM_CPU_MODE_USR: 107 case ARM_CPU_MODE_SYS: 108 return BANK_USRSYS; 109 case ARM_CPU_MODE_SVC: 110 return BANK_SVC; 111 case ARM_CPU_MODE_ABT: 112 return BANK_ABT; 113 case ARM_CPU_MODE_UND: 114 return BANK_UND; 115 case ARM_CPU_MODE_IRQ: 116 return BANK_IRQ; 117 case ARM_CPU_MODE_FIQ: 118 return BANK_FIQ; 119 case ARM_CPU_MODE_HYP: 120 return BANK_HYP; 121 case ARM_CPU_MODE_MON: 122 return BANK_MON; 123 } 124 g_assert_not_reached(); 125 } 126 127 void switch_mode(CPUARMState *, int); 128 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu); 129 void arm_translate_init(void); 130 131 enum arm_fprounding { 132 FPROUNDING_TIEEVEN, 133 FPROUNDING_POSINF, 134 FPROUNDING_NEGINF, 135 FPROUNDING_ZERO, 136 FPROUNDING_TIEAWAY, 137 FPROUNDING_ODD 138 }; 139 140 int arm_rmode_to_sf(int rmode); 141 142 static inline void aarch64_save_sp(CPUARMState *env, int el) 143 { 144 if (env->pstate & PSTATE_SP) { 145 env->sp_el[el] = env->xregs[31]; 146 } else { 147 env->sp_el[0] = env->xregs[31]; 148 } 149 } 150 151 static inline void aarch64_restore_sp(CPUARMState *env, int el) 152 { 153 if (env->pstate & PSTATE_SP) { 154 env->xregs[31] = env->sp_el[el]; 155 } else { 156 env->xregs[31] = env->sp_el[0]; 157 } 158 } 159 160 static inline void update_spsel(CPUARMState *env, uint32_t imm) 161 { 162 unsigned int cur_el = arm_current_el(env); 163 /* Update PSTATE SPSel bit; this requires us to update the 164 * working stack pointer in xregs[31]. 165 */ 166 if (!((imm ^ env->pstate) & PSTATE_SP)) { 167 return; 168 } 169 aarch64_save_sp(env, cur_el); 170 env->pstate = deposit32(env->pstate, 0, 1, imm); 171 172 /* We rely on illegal updates to SPsel from EL0 to get trapped 173 * at translation time. 174 */ 175 assert(cur_el >= 1 && cur_el <= 3); 176 aarch64_restore_sp(env, cur_el); 177 } 178 179 /* 180 * arm_pamax 181 * @cpu: ARMCPU 182 * 183 * Returns the implementation defined bit-width of physical addresses. 184 * The ARMv8 reference manuals refer to this as PAMax(). 185 */ 186 static inline unsigned int arm_pamax(ARMCPU *cpu) 187 { 188 static const unsigned int pamax_map[] = { 189 [0] = 32, 190 [1] = 36, 191 [2] = 40, 192 [3] = 42, 193 [4] = 44, 194 [5] = 48, 195 }; 196 unsigned int parange = extract32(cpu->id_aa64mmfr0, 0, 4); 197 198 /* id_aa64mmfr0 is a read-only register so values outside of the 199 * supported mappings can be considered an implementation error. */ 200 assert(parange < ARRAY_SIZE(pamax_map)); 201 return pamax_map[parange]; 202 } 203 204 /* Return true if extended addresses are enabled. 205 * This is always the case if our translation regime is 64 bit, 206 * but depends on TTBCR.EAE for 32 bit. 207 */ 208 static inline bool extended_addresses_enabled(CPUARMState *env) 209 { 210 TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1]; 211 return arm_el_is_aa64(env, 1) || 212 (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE)); 213 } 214 215 /* Valid Syndrome Register EC field values */ 216 enum arm_exception_class { 217 EC_UNCATEGORIZED = 0x00, 218 EC_WFX_TRAP = 0x01, 219 EC_CP15RTTRAP = 0x03, 220 EC_CP15RRTTRAP = 0x04, 221 EC_CP14RTTRAP = 0x05, 222 EC_CP14DTTRAP = 0x06, 223 EC_ADVSIMDFPACCESSTRAP = 0x07, 224 EC_FPIDTRAP = 0x08, 225 EC_CP14RRTTRAP = 0x0c, 226 EC_ILLEGALSTATE = 0x0e, 227 EC_AA32_SVC = 0x11, 228 EC_AA32_HVC = 0x12, 229 EC_AA32_SMC = 0x13, 230 EC_AA64_SVC = 0x15, 231 EC_AA64_HVC = 0x16, 232 EC_AA64_SMC = 0x17, 233 EC_SYSTEMREGISTERTRAP = 0x18, 234 EC_INSNABORT = 0x20, 235 EC_INSNABORT_SAME_EL = 0x21, 236 EC_PCALIGNMENT = 0x22, 237 EC_DATAABORT = 0x24, 238 EC_DATAABORT_SAME_EL = 0x25, 239 EC_SPALIGNMENT = 0x26, 240 EC_AA32_FPTRAP = 0x28, 241 EC_AA64_FPTRAP = 0x2c, 242 EC_SERROR = 0x2f, 243 EC_BREAKPOINT = 0x30, 244 EC_BREAKPOINT_SAME_EL = 0x31, 245 EC_SOFTWARESTEP = 0x32, 246 EC_SOFTWARESTEP_SAME_EL = 0x33, 247 EC_WATCHPOINT = 0x34, 248 EC_WATCHPOINT_SAME_EL = 0x35, 249 EC_AA32_BKPT = 0x38, 250 EC_VECTORCATCH = 0x3a, 251 EC_AA64_BKPT = 0x3c, 252 }; 253 254 #define ARM_EL_EC_SHIFT 26 255 #define ARM_EL_IL_SHIFT 25 256 #define ARM_EL_ISV_SHIFT 24 257 #define ARM_EL_IL (1 << ARM_EL_IL_SHIFT) 258 #define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT) 259 260 /* Utility functions for constructing various kinds of syndrome value. 261 * Note that in general we follow the AArch64 syndrome values; in a 262 * few cases the value in HSR for exceptions taken to AArch32 Hyp 263 * mode differs slightly, so if we ever implemented Hyp mode then the 264 * syndrome value would need some massaging on exception entry. 265 * (One example of this is that AArch64 defaults to IL bit set for 266 * exceptions which don't specifically indicate information about the 267 * trapping instruction, whereas AArch32 defaults to IL bit clear.) 268 */ 269 static inline uint32_t syn_uncategorized(void) 270 { 271 return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL; 272 } 273 274 static inline uint32_t syn_aa64_svc(uint32_t imm16) 275 { 276 return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 277 } 278 279 static inline uint32_t syn_aa64_hvc(uint32_t imm16) 280 { 281 return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 282 } 283 284 static inline uint32_t syn_aa64_smc(uint32_t imm16) 285 { 286 return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 287 } 288 289 static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit) 290 { 291 return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) 292 | (is_16bit ? 0 : ARM_EL_IL); 293 } 294 295 static inline uint32_t syn_aa32_hvc(uint32_t imm16) 296 { 297 return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 298 } 299 300 static inline uint32_t syn_aa32_smc(void) 301 { 302 return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL; 303 } 304 305 static inline uint32_t syn_aa64_bkpt(uint32_t imm16) 306 { 307 return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 308 } 309 310 static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit) 311 { 312 return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) 313 | (is_16bit ? 0 : ARM_EL_IL); 314 } 315 316 static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2, 317 int crn, int crm, int rt, 318 int isread) 319 { 320 return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL 321 | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5) 322 | (crm << 1) | isread; 323 } 324 325 static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2, 326 int crn, int crm, int rt, int isread, 327 bool is_16bit) 328 { 329 return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT) 330 | (is_16bit ? 0 : ARM_EL_IL) 331 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) 332 | (crn << 10) | (rt << 5) | (crm << 1) | isread; 333 } 334 335 static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2, 336 int crn, int crm, int rt, int isread, 337 bool is_16bit) 338 { 339 return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT) 340 | (is_16bit ? 0 : ARM_EL_IL) 341 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) 342 | (crn << 10) | (rt << 5) | (crm << 1) | isread; 343 } 344 345 static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm, 346 int rt, int rt2, int isread, 347 bool is_16bit) 348 { 349 return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT) 350 | (is_16bit ? 0 : ARM_EL_IL) 351 | (cv << 24) | (cond << 20) | (opc1 << 16) 352 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; 353 } 354 355 static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm, 356 int rt, int rt2, int isread, 357 bool is_16bit) 358 { 359 return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT) 360 | (is_16bit ? 0 : ARM_EL_IL) 361 | (cv << 24) | (cond << 20) | (opc1 << 16) 362 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; 363 } 364 365 static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit) 366 { 367 return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) 368 | (is_16bit ? 0 : ARM_EL_IL) 369 | (cv << 24) | (cond << 20); 370 } 371 372 static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc) 373 { 374 return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 375 | ARM_EL_IL | (ea << 9) | (s1ptw << 7) | fsc; 376 } 377 378 static inline uint32_t syn_data_abort_no_iss(int same_el, 379 int ea, int cm, int s1ptw, 380 int wnr, int fsc) 381 { 382 return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 383 | ARM_EL_IL 384 | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc; 385 } 386 387 static inline uint32_t syn_data_abort_with_iss(int same_el, 388 int sas, int sse, int srt, 389 int sf, int ar, 390 int ea, int cm, int s1ptw, 391 int wnr, int fsc, 392 bool is_16bit) 393 { 394 return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 395 | (is_16bit ? 0 : ARM_EL_IL) 396 | ARM_EL_ISV | (sas << 22) | (sse << 21) | (srt << 16) 397 | (sf << 15) | (ar << 14) 398 | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc; 399 } 400 401 static inline uint32_t syn_swstep(int same_el, int isv, int ex) 402 { 403 return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 404 | ARM_EL_IL | (isv << 24) | (ex << 6) | 0x22; 405 } 406 407 static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr) 408 { 409 return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 410 | ARM_EL_IL | (cm << 8) | (wnr << 6) | 0x22; 411 } 412 413 static inline uint32_t syn_breakpoint(int same_el) 414 { 415 return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 416 | ARM_EL_IL | 0x22; 417 } 418 419 static inline uint32_t syn_wfx(int cv, int cond, int ti) 420 { 421 return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) | 422 (cv << 24) | (cond << 20) | ti; 423 } 424 425 /* Update a QEMU watchpoint based on the information the guest has set in the 426 * DBGWCR<n>_EL1 and DBGWVR<n>_EL1 registers. 427 */ 428 void hw_watchpoint_update(ARMCPU *cpu, int n); 429 /* Update the QEMU watchpoints for every guest watchpoint. This does a 430 * complete delete-and-reinstate of the QEMU watchpoint list and so is 431 * suitable for use after migration or on reset. 432 */ 433 void hw_watchpoint_update_all(ARMCPU *cpu); 434 /* Update a QEMU breakpoint based on the information the guest has set in the 435 * DBGBCR<n>_EL1 and DBGBVR<n>_EL1 registers. 436 */ 437 void hw_breakpoint_update(ARMCPU *cpu, int n); 438 /* Update the QEMU breakpoints for every guest breakpoint. This does a 439 * complete delete-and-reinstate of the QEMU breakpoint list and so is 440 * suitable for use after migration or on reset. 441 */ 442 void hw_breakpoint_update_all(ARMCPU *cpu); 443 444 /* Callback function for checking if a watchpoint should trigger. */ 445 bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); 446 447 /* Callback function for when a watchpoint or breakpoint triggers. */ 448 void arm_debug_excp_handler(CPUState *cs); 449 450 #ifdef CONFIG_USER_ONLY 451 static inline bool arm_is_psci_call(ARMCPU *cpu, int excp_type) 452 { 453 return false; 454 } 455 #else 456 /* Return true if the r0/x0 value indicates that this SMC/HVC is a PSCI call. */ 457 bool arm_is_psci_call(ARMCPU *cpu, int excp_type); 458 /* Actually handle a PSCI call */ 459 void arm_handle_psci_call(ARMCPU *cpu); 460 #endif 461 462 /** 463 * ARMMMUFaultInfo: Information describing an ARM MMU Fault 464 * @s2addr: Address that caused a fault at stage 2 465 * @stage2: True if we faulted at stage 2 466 * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table walk 467 */ 468 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; 469 struct ARMMMUFaultInfo { 470 target_ulong s2addr; 471 bool stage2; 472 bool s1ptw; 473 }; 474 475 /* Do a page table walk and add page to TLB if possible */ 476 bool arm_tlb_fill(CPUState *cpu, vaddr address, int rw, int mmu_idx, 477 uint32_t *fsr, ARMMMUFaultInfo *fi); 478 479 /* Return true if the stage 1 translation regime is using LPAE format page 480 * tables */ 481 bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx); 482 483 /* Raise a data fault alignment exception for the specified virtual address */ 484 void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, 485 MMUAccessType access_type, 486 int mmu_idx, uintptr_t retaddr); 487 488 /* Call the EL change hook if one has been registered */ 489 static inline void arm_call_el_change_hook(ARMCPU *cpu) 490 { 491 if (cpu->el_change_hook) { 492 cpu->el_change_hook(cpu, cpu->el_change_hook_opaque); 493 } 494 } 495 496 #endif 497