1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * ARM implementation of KVM hooks 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright Christoffer Dall 2009-2010 5de3c9601SRichard Henderson * Copyright Mian-M. Hamayun 2013, Virtual Open Systems 6de3c9601SRichard Henderson * Copyright Alex Bennée 2014, Linaro 7fcf5ef2aSThomas Huth * 8fcf5ef2aSThomas Huth * This work is licensed under the terms of the GNU GPL, version 2 or later. 9fcf5ef2aSThomas Huth * See the COPYING file in the top-level directory. 10fcf5ef2aSThomas Huth * 11fcf5ef2aSThomas Huth */ 12fcf5ef2aSThomas Huth 13fcf5ef2aSThomas Huth #include "qemu/osdep.h" 14fcf5ef2aSThomas Huth #include <sys/ioctl.h> 15fcf5ef2aSThomas Huth 16fcf5ef2aSThomas Huth #include <linux/kvm.h> 17fcf5ef2aSThomas Huth 18fcf5ef2aSThomas Huth #include "qemu/timer.h" 19fcf5ef2aSThomas Huth #include "qemu/error-report.h" 20db725815SMarkus Armbruster #include "qemu/main-loop.h" 21dea101a1SAndrew Jones #include "qom/object.h" 22dea101a1SAndrew Jones #include "qapi/error.h" 23fcf5ef2aSThomas Huth #include "sysemu/sysemu.h" 24de3c9601SRichard Henderson #include "sysemu/runstate.h" 25fcf5ef2aSThomas Huth #include "sysemu/kvm.h" 26a27382e2SEric Auger #include "sysemu/kvm_int.h" 27fcf5ef2aSThomas Huth #include "kvm_arm.h" 28fcf5ef2aSThomas Huth #include "cpu.h" 29b05c81d2SEric Auger #include "trace.h" 30fcf5ef2aSThomas Huth #include "internals.h" 31b05c81d2SEric Auger #include "hw/pci/pci.h" 32fcf5ef2aSThomas Huth #include "exec/memattrs.h" 33fcf5ef2aSThomas Huth #include "exec/address-spaces.h" 34de3c9601SRichard Henderson #include "exec/gdbstub.h" 35fcf5ef2aSThomas Huth #include "hw/boards.h" 3664552b6bSMarkus Armbruster #include "hw/irq.h" 37c8f2eb5dSShameer Kolothum #include "qapi/visitor.h" 38fcf5ef2aSThomas Huth #include "qemu/log.h" 39de3c9601SRichard Henderson #include "hw/acpi/acpi.h" 40de3c9601SRichard Henderson #include "hw/acpi/ghes.h" 41fcf5ef2aSThomas Huth 42fcf5ef2aSThomas Huth const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 43fcf5ef2aSThomas Huth KVM_CAP_LAST_INFO 44fcf5ef2aSThomas Huth }; 45fcf5ef2aSThomas Huth 46fcf5ef2aSThomas Huth static bool cap_has_mp_state; 47202ccb6bSDongjiu Geng static bool cap_has_inject_serror_esr; 48694bcaa8SBeata Michalska static bool cap_has_inject_ext_dabt; 49fcf5ef2aSThomas Huth 50dc40d45eSRichard Henderson /** 51dc40d45eSRichard Henderson * ARMHostCPUFeatures: information about the host CPU (identified 52dc40d45eSRichard Henderson * by asking the host kernel) 53dc40d45eSRichard Henderson */ 54dc40d45eSRichard Henderson typedef struct ARMHostCPUFeatures { 55dc40d45eSRichard Henderson ARMISARegisters isar; 56dc40d45eSRichard Henderson uint64_t features; 57dc40d45eSRichard Henderson uint32_t target; 58dc40d45eSRichard Henderson const char *dtb_compatible; 59dc40d45eSRichard Henderson } ARMHostCPUFeatures; 60dc40d45eSRichard Henderson 61c4487d76SPeter Maydell static ARMHostCPUFeatures arm_host_cpu_features; 62c4487d76SPeter Maydell 635a8a6013SRichard Henderson /** 645a8a6013SRichard Henderson * kvm_arm_vcpu_init: 655a8a6013SRichard Henderson * @cs: CPUState 665a8a6013SRichard Henderson * 675a8a6013SRichard Henderson * Initialize (or reinitialize) the VCPU by invoking the 685a8a6013SRichard Henderson * KVM_ARM_VCPU_INIT ioctl with the CPU type and feature 695a8a6013SRichard Henderson * bitmask specified in the CPUState. 705a8a6013SRichard Henderson * 715a8a6013SRichard Henderson * Returns: 0 if success else < 0 error code 725a8a6013SRichard Henderson */ 735a8a6013SRichard Henderson static int kvm_arm_vcpu_init(CPUState *cs) 74fcf5ef2aSThomas Huth { 75fcf5ef2aSThomas Huth ARMCPU *cpu = ARM_CPU(cs); 76fcf5ef2aSThomas Huth struct kvm_vcpu_init init; 77fcf5ef2aSThomas Huth 78fcf5ef2aSThomas Huth init.target = cpu->kvm_target; 79fcf5ef2aSThomas Huth memcpy(init.features, cpu->kvm_init_features, sizeof(init.features)); 80fcf5ef2aSThomas Huth 81fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_INIT, &init); 82fcf5ef2aSThomas Huth } 83fcf5ef2aSThomas Huth 84c223c67aSRichard Henderson /** 85c223c67aSRichard Henderson * kvm_arm_vcpu_finalize: 86c223c67aSRichard Henderson * @cs: CPUState 87c223c67aSRichard Henderson * @feature: feature to finalize 88c223c67aSRichard Henderson * 89c223c67aSRichard Henderson * Finalizes the configuration of the specified VCPU feature by 90c223c67aSRichard Henderson * invoking the KVM_ARM_VCPU_FINALIZE ioctl. Features requiring 91c223c67aSRichard Henderson * this are documented in the "KVM_ARM_VCPU_FINALIZE" section of 92c223c67aSRichard Henderson * KVM's API documentation. 93c223c67aSRichard Henderson * 94c223c67aSRichard Henderson * Returns: 0 if success else < 0 error code 95c223c67aSRichard Henderson */ 96c223c67aSRichard Henderson static int kvm_arm_vcpu_finalize(CPUState *cs, int feature) 9714e99e0fSAndrew Jones { 9814e99e0fSAndrew Jones return kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_FINALIZE, &feature); 9914e99e0fSAndrew Jones } 10014e99e0fSAndrew Jones 101fcf5ef2aSThomas Huth bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try, 102fcf5ef2aSThomas Huth int *fdarray, 103fcf5ef2aSThomas Huth struct kvm_vcpu_init *init) 104fcf5ef2aSThomas Huth { 1050cdb4020SAndrew Jones int ret = 0, kvmfd = -1, vmfd = -1, cpufd = -1; 106d26f2f93SMarc Zyngier int max_vm_pa_size; 107fcf5ef2aSThomas Huth 108448058aaSDaniel P. Berrangé kvmfd = qemu_open_old("/dev/kvm", O_RDWR); 109fcf5ef2aSThomas Huth if (kvmfd < 0) { 110fcf5ef2aSThomas Huth goto err; 111fcf5ef2aSThomas Huth } 112d26f2f93SMarc Zyngier max_vm_pa_size = ioctl(kvmfd, KVM_CHECK_EXTENSION, KVM_CAP_ARM_VM_IPA_SIZE); 113d26f2f93SMarc Zyngier if (max_vm_pa_size < 0) { 114d26f2f93SMarc Zyngier max_vm_pa_size = 0; 115d26f2f93SMarc Zyngier } 116bbde13cdSPeter Maydell do { 117d26f2f93SMarc Zyngier vmfd = ioctl(kvmfd, KVM_CREATE_VM, max_vm_pa_size); 118bbde13cdSPeter Maydell } while (vmfd == -1 && errno == EINTR); 119fcf5ef2aSThomas Huth if (vmfd < 0) { 120fcf5ef2aSThomas Huth goto err; 121fcf5ef2aSThomas Huth } 122fcf5ef2aSThomas Huth cpufd = ioctl(vmfd, KVM_CREATE_VCPU, 0); 123fcf5ef2aSThomas Huth if (cpufd < 0) { 124fcf5ef2aSThomas Huth goto err; 125fcf5ef2aSThomas Huth } 126fcf5ef2aSThomas Huth 127fcf5ef2aSThomas Huth if (!init) { 128fcf5ef2aSThomas Huth /* Caller doesn't want the VCPU to be initialized, so skip it */ 129fcf5ef2aSThomas Huth goto finish; 130fcf5ef2aSThomas Huth } 131fcf5ef2aSThomas Huth 1320cdb4020SAndrew Jones if (init->target == -1) { 1330cdb4020SAndrew Jones struct kvm_vcpu_init preferred; 1340cdb4020SAndrew Jones 1350cdb4020SAndrew Jones ret = ioctl(vmfd, KVM_ARM_PREFERRED_TARGET, &preferred); 1360cdb4020SAndrew Jones if (!ret) { 1370cdb4020SAndrew Jones init->target = preferred.target; 1380cdb4020SAndrew Jones } 1390cdb4020SAndrew Jones } 140fcf5ef2aSThomas Huth if (ret >= 0) { 141fcf5ef2aSThomas Huth ret = ioctl(cpufd, KVM_ARM_VCPU_INIT, init); 142fcf5ef2aSThomas Huth if (ret < 0) { 143fcf5ef2aSThomas Huth goto err; 144fcf5ef2aSThomas Huth } 145fcf5ef2aSThomas Huth } else if (cpus_to_try) { 146fcf5ef2aSThomas Huth /* Old kernel which doesn't know about the 147fcf5ef2aSThomas Huth * PREFERRED_TARGET ioctl: we know it will only support 148fcf5ef2aSThomas Huth * creating one kind of guest CPU which is its preferred 149fcf5ef2aSThomas Huth * CPU type. 150fcf5ef2aSThomas Huth */ 1510cdb4020SAndrew Jones struct kvm_vcpu_init try; 1520cdb4020SAndrew Jones 153fcf5ef2aSThomas Huth while (*cpus_to_try != QEMU_KVM_ARM_TARGET_NONE) { 1540cdb4020SAndrew Jones try.target = *cpus_to_try++; 1550cdb4020SAndrew Jones memcpy(try.features, init->features, sizeof(init->features)); 1560cdb4020SAndrew Jones ret = ioctl(cpufd, KVM_ARM_VCPU_INIT, &try); 157fcf5ef2aSThomas Huth if (ret >= 0) { 158fcf5ef2aSThomas Huth break; 159fcf5ef2aSThomas Huth } 160fcf5ef2aSThomas Huth } 161fcf5ef2aSThomas Huth if (ret < 0) { 162fcf5ef2aSThomas Huth goto err; 163fcf5ef2aSThomas Huth } 1640cdb4020SAndrew Jones init->target = try.target; 165fcf5ef2aSThomas Huth } else { 166fcf5ef2aSThomas Huth /* Treat a NULL cpus_to_try argument the same as an empty 167fcf5ef2aSThomas Huth * list, which means we will fail the call since this must 168fcf5ef2aSThomas Huth * be an old kernel which doesn't support PREFERRED_TARGET. 169fcf5ef2aSThomas Huth */ 170fcf5ef2aSThomas Huth goto err; 171fcf5ef2aSThomas Huth } 172fcf5ef2aSThomas Huth 173fcf5ef2aSThomas Huth finish: 174fcf5ef2aSThomas Huth fdarray[0] = kvmfd; 175fcf5ef2aSThomas Huth fdarray[1] = vmfd; 176fcf5ef2aSThomas Huth fdarray[2] = cpufd; 177fcf5ef2aSThomas Huth 178fcf5ef2aSThomas Huth return true; 179fcf5ef2aSThomas Huth 180fcf5ef2aSThomas Huth err: 181fcf5ef2aSThomas Huth if (cpufd >= 0) { 182fcf5ef2aSThomas Huth close(cpufd); 183fcf5ef2aSThomas Huth } 184fcf5ef2aSThomas Huth if (vmfd >= 0) { 185fcf5ef2aSThomas Huth close(vmfd); 186fcf5ef2aSThomas Huth } 187fcf5ef2aSThomas Huth if (kvmfd >= 0) { 188fcf5ef2aSThomas Huth close(kvmfd); 189fcf5ef2aSThomas Huth } 190fcf5ef2aSThomas Huth 191fcf5ef2aSThomas Huth return false; 192fcf5ef2aSThomas Huth } 193fcf5ef2aSThomas Huth 194fcf5ef2aSThomas Huth void kvm_arm_destroy_scratch_host_vcpu(int *fdarray) 195fcf5ef2aSThomas Huth { 196fcf5ef2aSThomas Huth int i; 197fcf5ef2aSThomas Huth 198fcf5ef2aSThomas Huth for (i = 2; i >= 0; i--) { 199fcf5ef2aSThomas Huth close(fdarray[i]); 200fcf5ef2aSThomas Huth } 201fcf5ef2aSThomas Huth } 202fcf5ef2aSThomas Huth 203dc40d45eSRichard Henderson static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id) 204dc40d45eSRichard Henderson { 205dc40d45eSRichard Henderson uint64_t ret; 206dc40d45eSRichard Henderson struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)&ret }; 207dc40d45eSRichard Henderson int err; 208dc40d45eSRichard Henderson 209dc40d45eSRichard Henderson assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64); 210dc40d45eSRichard Henderson err = ioctl(fd, KVM_GET_ONE_REG, &idreg); 211dc40d45eSRichard Henderson if (err < 0) { 212dc40d45eSRichard Henderson return -1; 213dc40d45eSRichard Henderson } 214dc40d45eSRichard Henderson *pret = ret; 215dc40d45eSRichard Henderson return 0; 216dc40d45eSRichard Henderson } 217dc40d45eSRichard Henderson 218dc40d45eSRichard Henderson static int read_sys_reg64(int fd, uint64_t *pret, uint64_t id) 219dc40d45eSRichard Henderson { 220dc40d45eSRichard Henderson struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)pret }; 221dc40d45eSRichard Henderson 222dc40d45eSRichard Henderson assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64); 223dc40d45eSRichard Henderson return ioctl(fd, KVM_GET_ONE_REG, &idreg); 224dc40d45eSRichard Henderson } 225dc40d45eSRichard Henderson 226dc40d45eSRichard Henderson static bool kvm_arm_pauth_supported(void) 227dc40d45eSRichard Henderson { 228dc40d45eSRichard Henderson return (kvm_check_extension(kvm_state, KVM_CAP_ARM_PTRAUTH_ADDRESS) && 229dc40d45eSRichard Henderson kvm_check_extension(kvm_state, KVM_CAP_ARM_PTRAUTH_GENERIC)); 230dc40d45eSRichard Henderson } 231dc40d45eSRichard Henderson 232dc40d45eSRichard Henderson static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) 233dc40d45eSRichard Henderson { 234dc40d45eSRichard Henderson /* Identify the feature bits corresponding to the host CPU, and 235dc40d45eSRichard Henderson * fill out the ARMHostCPUClass fields accordingly. To do this 236dc40d45eSRichard Henderson * we have to create a scratch VM, create a single CPU inside it, 237dc40d45eSRichard Henderson * and then query that CPU for the relevant ID registers. 238dc40d45eSRichard Henderson */ 239dc40d45eSRichard Henderson int fdarray[3]; 240dc40d45eSRichard Henderson bool sve_supported; 241dc40d45eSRichard Henderson bool pmu_supported = false; 242dc40d45eSRichard Henderson uint64_t features = 0; 243dc40d45eSRichard Henderson int err; 244dc40d45eSRichard Henderson 245dc40d45eSRichard Henderson /* Old kernels may not know about the PREFERRED_TARGET ioctl: however 246dc40d45eSRichard Henderson * we know these will only support creating one kind of guest CPU, 247dc40d45eSRichard Henderson * which is its preferred CPU type. Fortunately these old kernels 248dc40d45eSRichard Henderson * support only a very limited number of CPUs. 249dc40d45eSRichard Henderson */ 250dc40d45eSRichard Henderson static const uint32_t cpus_to_try[] = { 251dc40d45eSRichard Henderson KVM_ARM_TARGET_AEM_V8, 252dc40d45eSRichard Henderson KVM_ARM_TARGET_FOUNDATION_V8, 253dc40d45eSRichard Henderson KVM_ARM_TARGET_CORTEX_A57, 254dc40d45eSRichard Henderson QEMU_KVM_ARM_TARGET_NONE 255dc40d45eSRichard Henderson }; 256dc40d45eSRichard Henderson /* 257dc40d45eSRichard Henderson * target = -1 informs kvm_arm_create_scratch_host_vcpu() 258dc40d45eSRichard Henderson * to use the preferred target 259dc40d45eSRichard Henderson */ 260dc40d45eSRichard Henderson struct kvm_vcpu_init init = { .target = -1, }; 261dc40d45eSRichard Henderson 262dc40d45eSRichard Henderson /* 263dc40d45eSRichard Henderson * Ask for SVE if supported, so that we can query ID_AA64ZFR0, 264dc40d45eSRichard Henderson * which is otherwise RAZ. 265dc40d45eSRichard Henderson */ 266dc40d45eSRichard Henderson sve_supported = kvm_arm_sve_supported(); 267dc40d45eSRichard Henderson if (sve_supported) { 268dc40d45eSRichard Henderson init.features[0] |= 1 << KVM_ARM_VCPU_SVE; 269dc40d45eSRichard Henderson } 270dc40d45eSRichard Henderson 271dc40d45eSRichard Henderson /* 272dc40d45eSRichard Henderson * Ask for Pointer Authentication if supported, so that we get 273dc40d45eSRichard Henderson * the unsanitized field values for AA64ISAR1_EL1. 274dc40d45eSRichard Henderson */ 275dc40d45eSRichard Henderson if (kvm_arm_pauth_supported()) { 276dc40d45eSRichard Henderson init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | 277dc40d45eSRichard Henderson 1 << KVM_ARM_VCPU_PTRAUTH_GENERIC); 278dc40d45eSRichard Henderson } 279dc40d45eSRichard Henderson 280dc40d45eSRichard Henderson if (kvm_arm_pmu_supported()) { 281dc40d45eSRichard Henderson init.features[0] |= 1 << KVM_ARM_VCPU_PMU_V3; 282dc40d45eSRichard Henderson pmu_supported = true; 283dc40d45eSRichard Henderson } 284dc40d45eSRichard Henderson 285dc40d45eSRichard Henderson if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) { 286dc40d45eSRichard Henderson return false; 287dc40d45eSRichard Henderson } 288dc40d45eSRichard Henderson 289dc40d45eSRichard Henderson ahcf->target = init.target; 290dc40d45eSRichard Henderson ahcf->dtb_compatible = "arm,arm-v8"; 291dc40d45eSRichard Henderson 292dc40d45eSRichard Henderson err = read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr0, 293dc40d45eSRichard Henderson ARM64_SYS_REG(3, 0, 0, 4, 0)); 294dc40d45eSRichard Henderson if (unlikely(err < 0)) { 295dc40d45eSRichard Henderson /* 296dc40d45eSRichard Henderson * Before v4.15, the kernel only exposed a limited number of system 297dc40d45eSRichard Henderson * registers, not including any of the interesting AArch64 ID regs. 298dc40d45eSRichard Henderson * For the most part we could leave these fields as zero with minimal 299dc40d45eSRichard Henderson * effect, since this does not affect the values seen by the guest. 300dc40d45eSRichard Henderson * 301dc40d45eSRichard Henderson * However, it could cause problems down the line for QEMU, 302dc40d45eSRichard Henderson * so provide a minimal v8.0 default. 303dc40d45eSRichard Henderson * 304dc40d45eSRichard Henderson * ??? Could read MIDR and use knowledge from cpu64.c. 305dc40d45eSRichard Henderson * ??? Could map a page of memory into our temp guest and 306dc40d45eSRichard Henderson * run the tiniest of hand-crafted kernels to extract 307dc40d45eSRichard Henderson * the values seen by the guest. 308dc40d45eSRichard Henderson * ??? Either of these sounds like too much effort just 309dc40d45eSRichard Henderson * to work around running a modern host kernel. 310dc40d45eSRichard Henderson */ 311dc40d45eSRichard Henderson ahcf->isar.id_aa64pfr0 = 0x00000011; /* EL1&0, AArch64 only */ 312dc40d45eSRichard Henderson err = 0; 313dc40d45eSRichard Henderson } else { 314dc40d45eSRichard Henderson err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr1, 315dc40d45eSRichard Henderson ARM64_SYS_REG(3, 0, 0, 4, 1)); 316dc40d45eSRichard Henderson err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64smfr0, 317dc40d45eSRichard Henderson ARM64_SYS_REG(3, 0, 0, 4, 5)); 318dc40d45eSRichard Henderson err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr0, 319dc40d45eSRichard Henderson ARM64_SYS_REG(3, 0, 0, 5, 0)); 320dc40d45eSRichard Henderson err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr1, 321dc40d45eSRichard Henderson ARM64_SYS_REG(3, 0, 0, 5, 1)); 322dc40d45eSRichard Henderson err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar0, 323dc40d45eSRichard Henderson ARM64_SYS_REG(3, 0, 0, 6, 0)); 324dc40d45eSRichard Henderson err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1, 325dc40d45eSRichard Henderson ARM64_SYS_REG(3, 0, 0, 6, 1)); 326dc40d45eSRichard Henderson err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar2, 327dc40d45eSRichard Henderson ARM64_SYS_REG(3, 0, 0, 6, 2)); 328dc40d45eSRichard Henderson err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr0, 329dc40d45eSRichard Henderson ARM64_SYS_REG(3, 0, 0, 7, 0)); 330dc40d45eSRichard Henderson err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1, 331dc40d45eSRichard Henderson ARM64_SYS_REG(3, 0, 0, 7, 1)); 332dc40d45eSRichard Henderson err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2, 333dc40d45eSRichard Henderson ARM64_SYS_REG(3, 0, 0, 7, 2)); 334dc40d45eSRichard Henderson 335dc40d45eSRichard Henderson /* 336dc40d45eSRichard Henderson * Note that if AArch32 support is not present in the host, 337dc40d45eSRichard Henderson * the AArch32 sysregs are present to be read, but will 338dc40d45eSRichard Henderson * return UNKNOWN values. This is neither better nor worse 339dc40d45eSRichard Henderson * than skipping the reads and leaving 0, as we must avoid 340dc40d45eSRichard Henderson * considering the values in every case. 341dc40d45eSRichard Henderson */ 342dc40d45eSRichard Henderson err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr0, 343dc40d45eSRichard Henderson ARM64_SYS_REG(3, 0, 0, 1, 0)); 344dc40d45eSRichard Henderson err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr1, 345dc40d45eSRichard Henderson ARM64_SYS_REG(3, 0, 0, 1, 1)); 346dc40d45eSRichard Henderson err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0, 347dc40d45eSRichard Henderson ARM64_SYS_REG(3, 0, 0, 1, 2)); 348dc40d45eSRichard Henderson err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0, 349dc40d45eSRichard Henderson ARM64_SYS_REG(3, 0, 0, 1, 4)); 350dc40d45eSRichard Henderson err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr1, 351dc40d45eSRichard Henderson ARM64_SYS_REG(3, 0, 0, 1, 5)); 352dc40d45eSRichard Henderson err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr2, 353dc40d45eSRichard Henderson ARM64_SYS_REG(3, 0, 0, 1, 6)); 354dc40d45eSRichard Henderson err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr3, 355dc40d45eSRichard Henderson ARM64_SYS_REG(3, 0, 0, 1, 7)); 356dc40d45eSRichard Henderson err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0, 357dc40d45eSRichard Henderson ARM64_SYS_REG(3, 0, 0, 2, 0)); 358dc40d45eSRichard Henderson err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1, 359dc40d45eSRichard Henderson ARM64_SYS_REG(3, 0, 0, 2, 1)); 360dc40d45eSRichard Henderson err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2, 361dc40d45eSRichard Henderson ARM64_SYS_REG(3, 0, 0, 2, 2)); 362dc40d45eSRichard Henderson err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3, 363dc40d45eSRichard Henderson ARM64_SYS_REG(3, 0, 0, 2, 3)); 364dc40d45eSRichard Henderson err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4, 365dc40d45eSRichard Henderson ARM64_SYS_REG(3, 0, 0, 2, 4)); 366dc40d45eSRichard Henderson err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5, 367dc40d45eSRichard Henderson ARM64_SYS_REG(3, 0, 0, 2, 5)); 368dc40d45eSRichard Henderson err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr4, 369dc40d45eSRichard Henderson ARM64_SYS_REG(3, 0, 0, 2, 6)); 370dc40d45eSRichard Henderson err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6, 371dc40d45eSRichard Henderson ARM64_SYS_REG(3, 0, 0, 2, 7)); 372dc40d45eSRichard Henderson 373dc40d45eSRichard Henderson err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0, 374dc40d45eSRichard Henderson ARM64_SYS_REG(3, 0, 0, 3, 0)); 375dc40d45eSRichard Henderson err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1, 376dc40d45eSRichard Henderson ARM64_SYS_REG(3, 0, 0, 3, 1)); 377dc40d45eSRichard Henderson err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2, 378dc40d45eSRichard Henderson ARM64_SYS_REG(3, 0, 0, 3, 2)); 379dc40d45eSRichard Henderson err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr2, 380dc40d45eSRichard Henderson ARM64_SYS_REG(3, 0, 0, 3, 4)); 381dc40d45eSRichard Henderson err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr1, 382dc40d45eSRichard Henderson ARM64_SYS_REG(3, 0, 0, 3, 5)); 383dc40d45eSRichard Henderson err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr5, 384dc40d45eSRichard Henderson ARM64_SYS_REG(3, 0, 0, 3, 6)); 385dc40d45eSRichard Henderson 386dc40d45eSRichard Henderson /* 387dc40d45eSRichard Henderson * DBGDIDR is a bit complicated because the kernel doesn't 388dc40d45eSRichard Henderson * provide an accessor for it in 64-bit mode, which is what this 389dc40d45eSRichard Henderson * scratch VM is in, and there's no architected "64-bit sysreg 390dc40d45eSRichard Henderson * which reads the same as the 32-bit register" the way there is 391dc40d45eSRichard Henderson * for other ID registers. Instead we synthesize a value from the 392dc40d45eSRichard Henderson * AArch64 ID_AA64DFR0, the same way the kernel code in 393dc40d45eSRichard Henderson * arch/arm64/kvm/sys_regs.c:trap_dbgidr() does. 394dc40d45eSRichard Henderson * We only do this if the CPU supports AArch32 at EL1. 395dc40d45eSRichard Henderson */ 396dc40d45eSRichard Henderson if (FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL1) >= 2) { 397dc40d45eSRichard Henderson int wrps = FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, WRPS); 398dc40d45eSRichard Henderson int brps = FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, BRPS); 399dc40d45eSRichard Henderson int ctx_cmps = 400dc40d45eSRichard Henderson FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS); 401dc40d45eSRichard Henderson int version = 6; /* ARMv8 debug architecture */ 402dc40d45eSRichard Henderson bool has_el3 = 403dc40d45eSRichard Henderson !!FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL3); 404dc40d45eSRichard Henderson uint32_t dbgdidr = 0; 405dc40d45eSRichard Henderson 406dc40d45eSRichard Henderson dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, WRPS, wrps); 407dc40d45eSRichard Henderson dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, BRPS, brps); 408dc40d45eSRichard Henderson dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, CTX_CMPS, ctx_cmps); 409dc40d45eSRichard Henderson dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, VERSION, version); 410dc40d45eSRichard Henderson dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, NSUHD_IMP, has_el3); 411dc40d45eSRichard Henderson dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, SE_IMP, has_el3); 412dc40d45eSRichard Henderson dbgdidr |= (1 << 15); /* RES1 bit */ 413dc40d45eSRichard Henderson ahcf->isar.dbgdidr = dbgdidr; 414dc40d45eSRichard Henderson } 415dc40d45eSRichard Henderson 416dc40d45eSRichard Henderson if (pmu_supported) { 417dc40d45eSRichard Henderson /* PMCR_EL0 is only accessible if the vCPU has feature PMU_V3 */ 418dc40d45eSRichard Henderson err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0, 419dc40d45eSRichard Henderson ARM64_SYS_REG(3, 3, 9, 12, 0)); 420dc40d45eSRichard Henderson } 421dc40d45eSRichard Henderson 422dc40d45eSRichard Henderson if (sve_supported) { 423dc40d45eSRichard Henderson /* 424dc40d45eSRichard Henderson * There is a range of kernels between kernel commit 73433762fcae 425dc40d45eSRichard Henderson * and f81cb2c3ad41 which have a bug where the kernel doesn't 426dc40d45eSRichard Henderson * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has 427dc40d45eSRichard Henderson * enabled SVE support, which resulted in an error rather than RAZ. 428dc40d45eSRichard Henderson * So only read the register if we set KVM_ARM_VCPU_SVE above. 429dc40d45eSRichard Henderson */ 430dc40d45eSRichard Henderson err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, 431dc40d45eSRichard Henderson ARM64_SYS_REG(3, 0, 0, 4, 4)); 432dc40d45eSRichard Henderson } 433dc40d45eSRichard Henderson } 434dc40d45eSRichard Henderson 435dc40d45eSRichard Henderson kvm_arm_destroy_scratch_host_vcpu(fdarray); 436dc40d45eSRichard Henderson 437dc40d45eSRichard Henderson if (err < 0) { 438dc40d45eSRichard Henderson return false; 439dc40d45eSRichard Henderson } 440dc40d45eSRichard Henderson 441dc40d45eSRichard Henderson /* 442dc40d45eSRichard Henderson * We can assume any KVM supporting CPU is at least a v8 443dc40d45eSRichard Henderson * with VFPv4+Neon; this in turn implies most of the other 444dc40d45eSRichard Henderson * feature bits. 445dc40d45eSRichard Henderson */ 446dc40d45eSRichard Henderson features |= 1ULL << ARM_FEATURE_V8; 447dc40d45eSRichard Henderson features |= 1ULL << ARM_FEATURE_NEON; 448dc40d45eSRichard Henderson features |= 1ULL << ARM_FEATURE_AARCH64; 449dc40d45eSRichard Henderson features |= 1ULL << ARM_FEATURE_PMU; 450dc40d45eSRichard Henderson features |= 1ULL << ARM_FEATURE_GENERIC_TIMER; 451dc40d45eSRichard Henderson 452dc40d45eSRichard Henderson ahcf->features = features; 453dc40d45eSRichard Henderson 454dc40d45eSRichard Henderson return true; 455dc40d45eSRichard Henderson } 456dc40d45eSRichard Henderson 457c4487d76SPeter Maydell void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) 458fcf5ef2aSThomas Huth { 459c4487d76SPeter Maydell CPUARMState *env = &cpu->env; 460fcf5ef2aSThomas Huth 461c4487d76SPeter Maydell if (!arm_host_cpu_features.dtb_compatible) { 462c4487d76SPeter Maydell if (!kvm_enabled() || 463c4487d76SPeter Maydell !kvm_arm_get_host_cpu_features(&arm_host_cpu_features)) { 464c4487d76SPeter Maydell /* We can't report this error yet, so flag that we need to 465c4487d76SPeter Maydell * in arm_cpu_realizefn(). 466fcf5ef2aSThomas Huth */ 467c4487d76SPeter Maydell cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 468c4487d76SPeter Maydell cpu->host_cpu_probe_failed = true; 469c4487d76SPeter Maydell return; 470fcf5ef2aSThomas Huth } 471fcf5ef2aSThomas Huth } 472fcf5ef2aSThomas Huth 473c4487d76SPeter Maydell cpu->kvm_target = arm_host_cpu_features.target; 474c4487d76SPeter Maydell cpu->dtb_compatible = arm_host_cpu_features.dtb_compatible; 4754674097cSRichard Henderson cpu->isar = arm_host_cpu_features.isar; 476c4487d76SPeter Maydell env->features = arm_host_cpu_features.features; 477c4487d76SPeter Maydell } 478c4487d76SPeter Maydell 479dea101a1SAndrew Jones static bool kvm_no_adjvtime_get(Object *obj, Error **errp) 480dea101a1SAndrew Jones { 481dea101a1SAndrew Jones return !ARM_CPU(obj)->kvm_adjvtime; 482dea101a1SAndrew Jones } 483dea101a1SAndrew Jones 484dea101a1SAndrew Jones static void kvm_no_adjvtime_set(Object *obj, bool value, Error **errp) 485dea101a1SAndrew Jones { 486dea101a1SAndrew Jones ARM_CPU(obj)->kvm_adjvtime = !value; 487dea101a1SAndrew Jones } 488dea101a1SAndrew Jones 48968970d1eSAndrew Jones static bool kvm_steal_time_get(Object *obj, Error **errp) 49068970d1eSAndrew Jones { 49168970d1eSAndrew Jones return ARM_CPU(obj)->kvm_steal_time != ON_OFF_AUTO_OFF; 49268970d1eSAndrew Jones } 49368970d1eSAndrew Jones 49468970d1eSAndrew Jones static void kvm_steal_time_set(Object *obj, bool value, Error **errp) 49568970d1eSAndrew Jones { 49668970d1eSAndrew Jones ARM_CPU(obj)->kvm_steal_time = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; 49768970d1eSAndrew Jones } 49868970d1eSAndrew Jones 499dea101a1SAndrew Jones /* KVM VCPU properties should be prefixed with "kvm-". */ 500cac675b5SPhilippe Mathieu-Daudé void kvm_arm_add_vcpu_properties(ARMCPU *cpu) 501dea101a1SAndrew Jones { 5029e6f8d8aSfangying CPUARMState *env = &cpu->env; 503cac675b5SPhilippe Mathieu-Daudé Object *obj = OBJECT(cpu); 504dea101a1SAndrew Jones 5059e6f8d8aSfangying if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { 5069e6f8d8aSfangying cpu->kvm_adjvtime = true; 507dea101a1SAndrew Jones object_property_add_bool(obj, "kvm-no-adjvtime", kvm_no_adjvtime_get, 508d2623129SMarkus Armbruster kvm_no_adjvtime_set); 509dea101a1SAndrew Jones object_property_set_description(obj, "kvm-no-adjvtime", 510dea101a1SAndrew Jones "Set on to disable the adjustment of " 511dea101a1SAndrew Jones "the virtual counter. VM stopped time " 5127eecec7dSMarkus Armbruster "will be counted."); 513dea101a1SAndrew Jones } 51468970d1eSAndrew Jones 51568970d1eSAndrew Jones cpu->kvm_steal_time = ON_OFF_AUTO_AUTO; 51668970d1eSAndrew Jones object_property_add_bool(obj, "kvm-steal-time", kvm_steal_time_get, 51768970d1eSAndrew Jones kvm_steal_time_set); 51868970d1eSAndrew Jones object_property_set_description(obj, "kvm-steal-time", 51968970d1eSAndrew Jones "Set off to disable KVM steal time."); 5209e6f8d8aSfangying } 521dea101a1SAndrew Jones 5227d20e681SPhilippe Mathieu-Daudé bool kvm_arm_pmu_supported(void) 523ae502508SAndrew Jones { 5247d20e681SPhilippe Mathieu-Daudé return kvm_check_extension(kvm_state, KVM_CAP_ARM_PMU_V3); 525ae502508SAndrew Jones } 526ae502508SAndrew Jones 527bcb902a1SAndrew Jones int kvm_arm_get_max_vm_ipa_size(MachineState *ms, bool *fixed_ipa) 528a27382e2SEric Auger { 529a27382e2SEric Auger KVMState *s = KVM_STATE(ms->accelerator); 530a27382e2SEric Auger int ret; 531a27382e2SEric Auger 532a27382e2SEric Auger ret = kvm_check_extension(s, KVM_CAP_ARM_VM_IPA_SIZE); 533bcb902a1SAndrew Jones *fixed_ipa = ret <= 0; 534bcb902a1SAndrew Jones 535a27382e2SEric Auger return ret > 0 ? ret : 40; 536a27382e2SEric Auger } 537a27382e2SEric Auger 5385e0d6590SAkihiko Odaki int kvm_arch_get_default_type(MachineState *ms) 5395e0d6590SAkihiko Odaki { 5401ab445afSAkihiko Odaki bool fixed_ipa; 5411ab445afSAkihiko Odaki int size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa); 5421ab445afSAkihiko Odaki return fixed_ipa ? 0 : size; 5435e0d6590SAkihiko Odaki } 5445e0d6590SAkihiko Odaki 545fcf5ef2aSThomas Huth int kvm_arch_init(MachineState *ms, KVMState *s) 546fcf5ef2aSThomas Huth { 547fff9f555SEric Auger int ret = 0; 548fcf5ef2aSThomas Huth /* For ARM interrupt delivery is always asynchronous, 549fcf5ef2aSThomas Huth * whether we are using an in-kernel VGIC or not. 550fcf5ef2aSThomas Huth */ 551fcf5ef2aSThomas Huth kvm_async_interrupts_allowed = true; 552fcf5ef2aSThomas Huth 5535d721b78SAlexander Graf /* 5545d721b78SAlexander Graf * PSCI wakes up secondary cores, so we always need to 5555d721b78SAlexander Graf * have vCPUs waiting in kernel space 5565d721b78SAlexander Graf */ 5575d721b78SAlexander Graf kvm_halt_in_kernel_allowed = true; 5585d721b78SAlexander Graf 559fcf5ef2aSThomas Huth cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE); 560fcf5ef2aSThomas Huth 56151641de4SRichard Henderson /* Check whether user space can specify guest syndrome value */ 56251641de4SRichard Henderson cap_has_inject_serror_esr = 56351641de4SRichard Henderson kvm_check_extension(s, KVM_CAP_ARM_INJECT_SERROR_ESR); 56451641de4SRichard Henderson 565fff9f555SEric Auger if (ms->smp.cpus > 256 && 566fff9f555SEric Auger !kvm_check_extension(s, KVM_CAP_ARM_IRQ_LINE_LAYOUT_2)) { 567fff9f555SEric Auger error_report("Using more than 256 vcpus requires a host kernel " 568fff9f555SEric Auger "with KVM_CAP_ARM_IRQ_LINE_LAYOUT_2"); 569fff9f555SEric Auger ret = -EINVAL; 570fff9f555SEric Auger } 571fff9f555SEric Auger 572694bcaa8SBeata Michalska if (kvm_check_extension(s, KVM_CAP_ARM_NISV_TO_USER)) { 573694bcaa8SBeata Michalska if (kvm_vm_enable_cap(s, KVM_CAP_ARM_NISV_TO_USER, 0)) { 574694bcaa8SBeata Michalska error_report("Failed to enable KVM_CAP_ARM_NISV_TO_USER cap"); 575694bcaa8SBeata Michalska } else { 576694bcaa8SBeata Michalska /* Set status for supporting the external dabt injection */ 577694bcaa8SBeata Michalska cap_has_inject_ext_dabt = kvm_check_extension(s, 578694bcaa8SBeata Michalska KVM_CAP_ARM_INJECT_EXT_DABT); 579694bcaa8SBeata Michalska } 580694bcaa8SBeata Michalska } 581694bcaa8SBeata Michalska 582c8f2eb5dSShameer Kolothum if (s->kvm_eager_split_size) { 583c8f2eb5dSShameer Kolothum uint32_t sizes; 584c8f2eb5dSShameer Kolothum 585c8f2eb5dSShameer Kolothum sizes = kvm_vm_check_extension(s, KVM_CAP_ARM_SUPPORTED_BLOCK_SIZES); 586c8f2eb5dSShameer Kolothum if (!sizes) { 587c8f2eb5dSShameer Kolothum s->kvm_eager_split_size = 0; 588c8f2eb5dSShameer Kolothum warn_report("Eager Page Split support not available"); 589c8f2eb5dSShameer Kolothum } else if (!(s->kvm_eager_split_size & sizes)) { 590c8f2eb5dSShameer Kolothum error_report("Eager Page Split requested chunk size not valid"); 591c8f2eb5dSShameer Kolothum ret = -EINVAL; 592c8f2eb5dSShameer Kolothum } else { 593c8f2eb5dSShameer Kolothum ret = kvm_vm_enable_cap(s, KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE, 0, 594c8f2eb5dSShameer Kolothum s->kvm_eager_split_size); 595c8f2eb5dSShameer Kolothum if (ret < 0) { 596c8f2eb5dSShameer Kolothum error_report("Enabling of Eager Page Split failed: %s", 597c8f2eb5dSShameer Kolothum strerror(-ret)); 598c8f2eb5dSShameer Kolothum } 599c8f2eb5dSShameer Kolothum } 600c8f2eb5dSShameer Kolothum } 601c8f2eb5dSShameer Kolothum 602dd2157d2SRichard Henderson max_hw_wps = kvm_check_extension(s, KVM_CAP_GUEST_DEBUG_HW_WPS); 603dd2157d2SRichard Henderson hw_watchpoints = g_array_sized_new(true, true, 604dd2157d2SRichard Henderson sizeof(HWWatchpoint), max_hw_wps); 605dd2157d2SRichard Henderson 606dd2157d2SRichard Henderson max_hw_bps = kvm_check_extension(s, KVM_CAP_GUEST_DEBUG_HW_BPS); 607dd2157d2SRichard Henderson hw_breakpoints = g_array_sized_new(true, true, 608dd2157d2SRichard Henderson sizeof(HWBreakpoint), max_hw_bps); 609ad5c6ddeSAkihiko Odaki 610fff9f555SEric Auger return ret; 611fcf5ef2aSThomas Huth } 612fcf5ef2aSThomas Huth 613fcf5ef2aSThomas Huth unsigned long kvm_arch_vcpu_id(CPUState *cpu) 614fcf5ef2aSThomas Huth { 615fcf5ef2aSThomas Huth return cpu->cpu_index; 616fcf5ef2aSThomas Huth } 617fcf5ef2aSThomas Huth 618fcf5ef2aSThomas Huth /* We track all the KVM devices which need their memory addresses 619fcf5ef2aSThomas Huth * passing to the kernel in a list of these structures. 620fcf5ef2aSThomas Huth * When board init is complete we run through the list and 621fcf5ef2aSThomas Huth * tell the kernel the base addresses of the memory regions. 622fcf5ef2aSThomas Huth * We use a MemoryListener to track mapping and unmapping of 623fcf5ef2aSThomas Huth * the regions during board creation, so the board models don't 624fcf5ef2aSThomas Huth * need to do anything special for the KVM case. 62519d1bd0bSEric Auger * 62619d1bd0bSEric Auger * Sometimes the address must be OR'ed with some other fields 62719d1bd0bSEric Auger * (for example for KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION). 62819d1bd0bSEric Auger * @kda_addr_ormask aims at storing the value of those fields. 629fcf5ef2aSThomas Huth */ 630fcf5ef2aSThomas Huth typedef struct KVMDevice { 631fcf5ef2aSThomas Huth struct kvm_arm_device_addr kda; 632fcf5ef2aSThomas Huth struct kvm_device_attr kdattr; 63319d1bd0bSEric Auger uint64_t kda_addr_ormask; 634fcf5ef2aSThomas Huth MemoryRegion *mr; 635fcf5ef2aSThomas Huth QSLIST_ENTRY(KVMDevice) entries; 636fcf5ef2aSThomas Huth int dev_fd; 637fcf5ef2aSThomas Huth } KVMDevice; 638fcf5ef2aSThomas Huth 639b58deb34SPaolo Bonzini static QSLIST_HEAD(, KVMDevice) kvm_devices_head; 640fcf5ef2aSThomas Huth 641fcf5ef2aSThomas Huth static void kvm_arm_devlistener_add(MemoryListener *listener, 642fcf5ef2aSThomas Huth MemoryRegionSection *section) 643fcf5ef2aSThomas Huth { 644fcf5ef2aSThomas Huth KVMDevice *kd; 645fcf5ef2aSThomas Huth 646fcf5ef2aSThomas Huth QSLIST_FOREACH(kd, &kvm_devices_head, entries) { 647fcf5ef2aSThomas Huth if (section->mr == kd->mr) { 648fcf5ef2aSThomas Huth kd->kda.addr = section->offset_within_address_space; 649fcf5ef2aSThomas Huth } 650fcf5ef2aSThomas Huth } 651fcf5ef2aSThomas Huth } 652fcf5ef2aSThomas Huth 653fcf5ef2aSThomas Huth static void kvm_arm_devlistener_del(MemoryListener *listener, 654fcf5ef2aSThomas Huth MemoryRegionSection *section) 655fcf5ef2aSThomas Huth { 656fcf5ef2aSThomas Huth KVMDevice *kd; 657fcf5ef2aSThomas Huth 658fcf5ef2aSThomas Huth QSLIST_FOREACH(kd, &kvm_devices_head, entries) { 659fcf5ef2aSThomas Huth if (section->mr == kd->mr) { 660fcf5ef2aSThomas Huth kd->kda.addr = -1; 661fcf5ef2aSThomas Huth } 662fcf5ef2aSThomas Huth } 663fcf5ef2aSThomas Huth } 664fcf5ef2aSThomas Huth 665fcf5ef2aSThomas Huth static MemoryListener devlistener = { 666142518bdSPeter Xu .name = "kvm-arm", 667fcf5ef2aSThomas Huth .region_add = kvm_arm_devlistener_add, 668fcf5ef2aSThomas Huth .region_del = kvm_arm_devlistener_del, 66914a868c6SIsaku Yamahata .priority = MEMORY_LISTENER_PRIORITY_MIN, 670fcf5ef2aSThomas Huth }; 671fcf5ef2aSThomas Huth 672fcf5ef2aSThomas Huth static void kvm_arm_set_device_addr(KVMDevice *kd) 673fcf5ef2aSThomas Huth { 674fcf5ef2aSThomas Huth struct kvm_device_attr *attr = &kd->kdattr; 675fcf5ef2aSThomas Huth int ret; 676fcf5ef2aSThomas Huth 677fcf5ef2aSThomas Huth /* If the device control API is available and we have a device fd on the 678fcf5ef2aSThomas Huth * KVMDevice struct, let's use the newer API 679fcf5ef2aSThomas Huth */ 680fcf5ef2aSThomas Huth if (kd->dev_fd >= 0) { 681fcf5ef2aSThomas Huth uint64_t addr = kd->kda.addr; 68219d1bd0bSEric Auger 68319d1bd0bSEric Auger addr |= kd->kda_addr_ormask; 684fcf5ef2aSThomas Huth attr->addr = (uintptr_t)&addr; 685fcf5ef2aSThomas Huth ret = kvm_device_ioctl(kd->dev_fd, KVM_SET_DEVICE_ATTR, attr); 686fcf5ef2aSThomas Huth } else { 687fcf5ef2aSThomas Huth ret = kvm_vm_ioctl(kvm_state, KVM_ARM_SET_DEVICE_ADDR, &kd->kda); 688fcf5ef2aSThomas Huth } 689fcf5ef2aSThomas Huth 690fcf5ef2aSThomas Huth if (ret < 0) { 691fcf5ef2aSThomas Huth fprintf(stderr, "Failed to set device address: %s\n", 692fcf5ef2aSThomas Huth strerror(-ret)); 693fcf5ef2aSThomas Huth abort(); 694fcf5ef2aSThomas Huth } 695fcf5ef2aSThomas Huth } 696fcf5ef2aSThomas Huth 697fcf5ef2aSThomas Huth static void kvm_arm_machine_init_done(Notifier *notifier, void *data) 698fcf5ef2aSThomas Huth { 699fcf5ef2aSThomas Huth KVMDevice *kd, *tkd; 700fcf5ef2aSThomas Huth 701fcf5ef2aSThomas Huth QSLIST_FOREACH_SAFE(kd, &kvm_devices_head, entries, tkd) { 702fcf5ef2aSThomas Huth if (kd->kda.addr != -1) { 703fcf5ef2aSThomas Huth kvm_arm_set_device_addr(kd); 704fcf5ef2aSThomas Huth } 705fcf5ef2aSThomas Huth memory_region_unref(kd->mr); 7065ff9aaabSZheng Xiang QSLIST_REMOVE_HEAD(&kvm_devices_head, entries); 707fcf5ef2aSThomas Huth g_free(kd); 708fcf5ef2aSThomas Huth } 7090bbe4354SPeter Xu memory_listener_unregister(&devlistener); 710fcf5ef2aSThomas Huth } 711fcf5ef2aSThomas Huth 712fcf5ef2aSThomas Huth static Notifier notify = { 713fcf5ef2aSThomas Huth .notify = kvm_arm_machine_init_done, 714fcf5ef2aSThomas Huth }; 715fcf5ef2aSThomas Huth 716fcf5ef2aSThomas Huth void kvm_arm_register_device(MemoryRegion *mr, uint64_t devid, uint64_t group, 71719d1bd0bSEric Auger uint64_t attr, int dev_fd, uint64_t addr_ormask) 718fcf5ef2aSThomas Huth { 719fcf5ef2aSThomas Huth KVMDevice *kd; 720fcf5ef2aSThomas Huth 721fcf5ef2aSThomas Huth if (!kvm_irqchip_in_kernel()) { 722fcf5ef2aSThomas Huth return; 723fcf5ef2aSThomas Huth } 724fcf5ef2aSThomas Huth 725fcf5ef2aSThomas Huth if (QSLIST_EMPTY(&kvm_devices_head)) { 726fcf5ef2aSThomas Huth memory_listener_register(&devlistener, &address_space_memory); 727fcf5ef2aSThomas Huth qemu_add_machine_init_done_notifier(¬ify); 728fcf5ef2aSThomas Huth } 729fcf5ef2aSThomas Huth kd = g_new0(KVMDevice, 1); 730fcf5ef2aSThomas Huth kd->mr = mr; 731fcf5ef2aSThomas Huth kd->kda.id = devid; 732fcf5ef2aSThomas Huth kd->kda.addr = -1; 733fcf5ef2aSThomas Huth kd->kdattr.flags = 0; 734fcf5ef2aSThomas Huth kd->kdattr.group = group; 735fcf5ef2aSThomas Huth kd->kdattr.attr = attr; 736fcf5ef2aSThomas Huth kd->dev_fd = dev_fd; 73719d1bd0bSEric Auger kd->kda_addr_ormask = addr_ormask; 738fcf5ef2aSThomas Huth QSLIST_INSERT_HEAD(&kvm_devices_head, kd, entries); 739fcf5ef2aSThomas Huth memory_region_ref(kd->mr); 740fcf5ef2aSThomas Huth } 741fcf5ef2aSThomas Huth 742fcf5ef2aSThomas Huth static int compare_u64(const void *a, const void *b) 743fcf5ef2aSThomas Huth { 744fcf5ef2aSThomas Huth if (*(uint64_t *)a > *(uint64_t *)b) { 745fcf5ef2aSThomas Huth return 1; 746fcf5ef2aSThomas Huth } 747fcf5ef2aSThomas Huth if (*(uint64_t *)a < *(uint64_t *)b) { 748fcf5ef2aSThomas Huth return -1; 749fcf5ef2aSThomas Huth } 750fcf5ef2aSThomas Huth return 0; 751fcf5ef2aSThomas Huth } 752fcf5ef2aSThomas Huth 753e5ac4200SAndrew Jones /* 754e5ac4200SAndrew Jones * cpreg_values are sorted in ascending order by KVM register ID 755e5ac4200SAndrew Jones * (see kvm_arm_init_cpreg_list). This allows us to cheaply find 756e5ac4200SAndrew Jones * the storage for a KVM register by ID with a binary search. 757e5ac4200SAndrew Jones */ 758e5ac4200SAndrew Jones static uint64_t *kvm_arm_get_cpreg_ptr(ARMCPU *cpu, uint64_t regidx) 759e5ac4200SAndrew Jones { 760e5ac4200SAndrew Jones uint64_t *res; 761e5ac4200SAndrew Jones 762e5ac4200SAndrew Jones res = bsearch(®idx, cpu->cpreg_indexes, cpu->cpreg_array_len, 763e5ac4200SAndrew Jones sizeof(uint64_t), compare_u64); 764e5ac4200SAndrew Jones assert(res); 765e5ac4200SAndrew Jones 766e5ac4200SAndrew Jones return &cpu->cpreg_values[res - cpu->cpreg_indexes]; 767e5ac4200SAndrew Jones } 768e5ac4200SAndrew Jones 769f38ce925SRichard Henderson /** 770f38ce925SRichard Henderson * kvm_arm_reg_syncs_via_cpreg_list: 771f38ce925SRichard Henderson * @regidx: KVM register index 772f38ce925SRichard Henderson * 773f38ce925SRichard Henderson * Return true if this KVM register should be synchronized via the 774f38ce925SRichard Henderson * cpreg list of arbitrary system registers, false if it is synchronized 775f38ce925SRichard Henderson * by hand using code in kvm_arch_get/put_registers(). 776f38ce925SRichard Henderson */ 777f38ce925SRichard Henderson static bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx) 778f38ce925SRichard Henderson { 779f38ce925SRichard Henderson switch (regidx & KVM_REG_ARM_COPROC_MASK) { 780f38ce925SRichard Henderson case KVM_REG_ARM_CORE: 781f38ce925SRichard Henderson case KVM_REG_ARM64_SVE: 782f38ce925SRichard Henderson return false; 783f38ce925SRichard Henderson default: 784f38ce925SRichard Henderson return true; 785f38ce925SRichard Henderson } 786f38ce925SRichard Henderson } 787f38ce925SRichard Henderson 78809ddc012SRichard Henderson /** 78909ddc012SRichard Henderson * kvm_arm_init_cpreg_list: 79009ddc012SRichard Henderson * @cpu: ARMCPU 79109ddc012SRichard Henderson * 79209ddc012SRichard Henderson * Initialize the ARMCPU cpreg list according to the kernel's 793fcf5ef2aSThomas Huth * definition of what CPU registers it knows about (and throw away 794fcf5ef2aSThomas Huth * the previous TCG-created cpreg list). 79509ddc012SRichard Henderson * 79609ddc012SRichard Henderson * Returns: 0 if success, else < 0 error code 797fcf5ef2aSThomas Huth */ 79809ddc012SRichard Henderson static int kvm_arm_init_cpreg_list(ARMCPU *cpu) 799fcf5ef2aSThomas Huth { 800fcf5ef2aSThomas Huth struct kvm_reg_list rl; 801fcf5ef2aSThomas Huth struct kvm_reg_list *rlp; 802fcf5ef2aSThomas Huth int i, ret, arraylen; 803fcf5ef2aSThomas Huth CPUState *cs = CPU(cpu); 804fcf5ef2aSThomas Huth 805fcf5ef2aSThomas Huth rl.n = 0; 806fcf5ef2aSThomas Huth ret = kvm_vcpu_ioctl(cs, KVM_GET_REG_LIST, &rl); 807fcf5ef2aSThomas Huth if (ret != -E2BIG) { 808fcf5ef2aSThomas Huth return ret; 809fcf5ef2aSThomas Huth } 810fcf5ef2aSThomas Huth rlp = g_malloc(sizeof(struct kvm_reg_list) + rl.n * sizeof(uint64_t)); 811fcf5ef2aSThomas Huth rlp->n = rl.n; 812fcf5ef2aSThomas Huth ret = kvm_vcpu_ioctl(cs, KVM_GET_REG_LIST, rlp); 813fcf5ef2aSThomas Huth if (ret) { 814fcf5ef2aSThomas Huth goto out; 815fcf5ef2aSThomas Huth } 816fcf5ef2aSThomas Huth /* Sort the list we get back from the kernel, since cpreg_tuples 817fcf5ef2aSThomas Huth * must be in strictly ascending order. 818fcf5ef2aSThomas Huth */ 819fcf5ef2aSThomas Huth qsort(&rlp->reg, rlp->n, sizeof(rlp->reg[0]), compare_u64); 820fcf5ef2aSThomas Huth 821fcf5ef2aSThomas Huth for (i = 0, arraylen = 0; i < rlp->n; i++) { 822fcf5ef2aSThomas Huth if (!kvm_arm_reg_syncs_via_cpreg_list(rlp->reg[i])) { 823fcf5ef2aSThomas Huth continue; 824fcf5ef2aSThomas Huth } 825fcf5ef2aSThomas Huth switch (rlp->reg[i] & KVM_REG_SIZE_MASK) { 826fcf5ef2aSThomas Huth case KVM_REG_SIZE_U32: 827fcf5ef2aSThomas Huth case KVM_REG_SIZE_U64: 828fcf5ef2aSThomas Huth break; 829fcf5ef2aSThomas Huth default: 830fcf5ef2aSThomas Huth fprintf(stderr, "Can't handle size of register in kernel list\n"); 831fcf5ef2aSThomas Huth ret = -EINVAL; 832fcf5ef2aSThomas Huth goto out; 833fcf5ef2aSThomas Huth } 834fcf5ef2aSThomas Huth 835fcf5ef2aSThomas Huth arraylen++; 836fcf5ef2aSThomas Huth } 837fcf5ef2aSThomas Huth 838fcf5ef2aSThomas Huth cpu->cpreg_indexes = g_renew(uint64_t, cpu->cpreg_indexes, arraylen); 839fcf5ef2aSThomas Huth cpu->cpreg_values = g_renew(uint64_t, cpu->cpreg_values, arraylen); 840fcf5ef2aSThomas Huth cpu->cpreg_vmstate_indexes = g_renew(uint64_t, cpu->cpreg_vmstate_indexes, 841fcf5ef2aSThomas Huth arraylen); 842fcf5ef2aSThomas Huth cpu->cpreg_vmstate_values = g_renew(uint64_t, cpu->cpreg_vmstate_values, 843fcf5ef2aSThomas Huth arraylen); 844fcf5ef2aSThomas Huth cpu->cpreg_array_len = arraylen; 845fcf5ef2aSThomas Huth cpu->cpreg_vmstate_array_len = arraylen; 846fcf5ef2aSThomas Huth 847fcf5ef2aSThomas Huth for (i = 0, arraylen = 0; i < rlp->n; i++) { 848fcf5ef2aSThomas Huth uint64_t regidx = rlp->reg[i]; 849fcf5ef2aSThomas Huth if (!kvm_arm_reg_syncs_via_cpreg_list(regidx)) { 850fcf5ef2aSThomas Huth continue; 851fcf5ef2aSThomas Huth } 852fcf5ef2aSThomas Huth cpu->cpreg_indexes[arraylen] = regidx; 853fcf5ef2aSThomas Huth arraylen++; 854fcf5ef2aSThomas Huth } 855fcf5ef2aSThomas Huth assert(cpu->cpreg_array_len == arraylen); 856fcf5ef2aSThomas Huth 857fcf5ef2aSThomas Huth if (!write_kvmstate_to_list(cpu)) { 858fcf5ef2aSThomas Huth /* Shouldn't happen unless kernel is inconsistent about 859fcf5ef2aSThomas Huth * what registers exist. 860fcf5ef2aSThomas Huth */ 861fcf5ef2aSThomas Huth fprintf(stderr, "Initial read of kernel register state failed\n"); 862fcf5ef2aSThomas Huth ret = -EINVAL; 863fcf5ef2aSThomas Huth goto out; 864fcf5ef2aSThomas Huth } 865fcf5ef2aSThomas Huth 866fcf5ef2aSThomas Huth out: 867fcf5ef2aSThomas Huth g_free(rlp); 868fcf5ef2aSThomas Huth return ret; 869fcf5ef2aSThomas Huth } 870fcf5ef2aSThomas Huth 871676fe684SRichard Henderson /** 872676fe684SRichard Henderson * kvm_arm_cpreg_level: 873676fe684SRichard Henderson * @regidx: KVM register index 874676fe684SRichard Henderson * 875676fe684SRichard Henderson * Return the level of this coprocessor/system register. Return value is 876676fe684SRichard Henderson * either KVM_PUT_RUNTIME_STATE, KVM_PUT_RESET_STATE, or KVM_PUT_FULL_STATE. 877676fe684SRichard Henderson */ 878676fe684SRichard Henderson static int kvm_arm_cpreg_level(uint64_t regidx) 879676fe684SRichard Henderson { 880676fe684SRichard Henderson /* 881676fe684SRichard Henderson * All system registers are assumed to be level KVM_PUT_RUNTIME_STATE. 882676fe684SRichard Henderson * If a register should be written less often, you must add it here 883676fe684SRichard Henderson * with a state of either KVM_PUT_RESET_STATE or KVM_PUT_FULL_STATE. 884676fe684SRichard Henderson */ 885676fe684SRichard Henderson switch (regidx) { 886676fe684SRichard Henderson case KVM_REG_ARM_TIMER_CNT: 887676fe684SRichard Henderson case KVM_REG_ARM_PTIMER_CNT: 888676fe684SRichard Henderson return KVM_PUT_FULL_STATE; 889676fe684SRichard Henderson } 890676fe684SRichard Henderson return KVM_PUT_RUNTIME_STATE; 891676fe684SRichard Henderson } 892676fe684SRichard Henderson 893fcf5ef2aSThomas Huth bool write_kvmstate_to_list(ARMCPU *cpu) 894fcf5ef2aSThomas Huth { 895fcf5ef2aSThomas Huth CPUState *cs = CPU(cpu); 896fcf5ef2aSThomas Huth int i; 897fcf5ef2aSThomas Huth bool ok = true; 898fcf5ef2aSThomas Huth 899fcf5ef2aSThomas Huth for (i = 0; i < cpu->cpreg_array_len; i++) { 900fcf5ef2aSThomas Huth uint64_t regidx = cpu->cpreg_indexes[i]; 901fcf5ef2aSThomas Huth uint32_t v32; 902fcf5ef2aSThomas Huth int ret; 903fcf5ef2aSThomas Huth 904fcf5ef2aSThomas Huth switch (regidx & KVM_REG_SIZE_MASK) { 905fcf5ef2aSThomas Huth case KVM_REG_SIZE_U32: 90640d45b85SCornelia Huck ret = kvm_get_one_reg(cs, regidx, &v32); 907fcf5ef2aSThomas Huth if (!ret) { 908fcf5ef2aSThomas Huth cpu->cpreg_values[i] = v32; 909fcf5ef2aSThomas Huth } 910fcf5ef2aSThomas Huth break; 911fcf5ef2aSThomas Huth case KVM_REG_SIZE_U64: 91240d45b85SCornelia Huck ret = kvm_get_one_reg(cs, regidx, cpu->cpreg_values + i); 913fcf5ef2aSThomas Huth break; 914fcf5ef2aSThomas Huth default: 915d385a605SRichard Henderson g_assert_not_reached(); 916fcf5ef2aSThomas Huth } 917fcf5ef2aSThomas Huth if (ret) { 918fcf5ef2aSThomas Huth ok = false; 919fcf5ef2aSThomas Huth } 920fcf5ef2aSThomas Huth } 921fcf5ef2aSThomas Huth return ok; 922fcf5ef2aSThomas Huth } 923fcf5ef2aSThomas Huth 924fcf5ef2aSThomas Huth bool write_list_to_kvmstate(ARMCPU *cpu, int level) 925fcf5ef2aSThomas Huth { 926fcf5ef2aSThomas Huth CPUState *cs = CPU(cpu); 927fcf5ef2aSThomas Huth int i; 928fcf5ef2aSThomas Huth bool ok = true; 929fcf5ef2aSThomas Huth 930fcf5ef2aSThomas Huth for (i = 0; i < cpu->cpreg_array_len; i++) { 931fcf5ef2aSThomas Huth uint64_t regidx = cpu->cpreg_indexes[i]; 932fcf5ef2aSThomas Huth uint32_t v32; 933fcf5ef2aSThomas Huth int ret; 934fcf5ef2aSThomas Huth 935fcf5ef2aSThomas Huth if (kvm_arm_cpreg_level(regidx) > level) { 936fcf5ef2aSThomas Huth continue; 937fcf5ef2aSThomas Huth } 938fcf5ef2aSThomas Huth 939fcf5ef2aSThomas Huth switch (regidx & KVM_REG_SIZE_MASK) { 940fcf5ef2aSThomas Huth case KVM_REG_SIZE_U32: 941fcf5ef2aSThomas Huth v32 = cpu->cpreg_values[i]; 9426c8b9a74SCornelia Huck ret = kvm_set_one_reg(cs, regidx, &v32); 943fcf5ef2aSThomas Huth break; 944fcf5ef2aSThomas Huth case KVM_REG_SIZE_U64: 9456c8b9a74SCornelia Huck ret = kvm_set_one_reg(cs, regidx, cpu->cpreg_values + i); 946fcf5ef2aSThomas Huth break; 947fcf5ef2aSThomas Huth default: 948d385a605SRichard Henderson g_assert_not_reached(); 949fcf5ef2aSThomas Huth } 950fcf5ef2aSThomas Huth if (ret) { 951fcf5ef2aSThomas Huth /* We might fail for "unknown register" and also for 952fcf5ef2aSThomas Huth * "you tried to set a register which is constant with 953fcf5ef2aSThomas Huth * a different value from what it actually contains". 954fcf5ef2aSThomas Huth */ 955fcf5ef2aSThomas Huth ok = false; 956fcf5ef2aSThomas Huth } 957fcf5ef2aSThomas Huth } 958fcf5ef2aSThomas Huth return ok; 959fcf5ef2aSThomas Huth } 960fcf5ef2aSThomas Huth 961e5ac4200SAndrew Jones void kvm_arm_cpu_pre_save(ARMCPU *cpu) 962e5ac4200SAndrew Jones { 963e5ac4200SAndrew Jones /* KVM virtual time adjustment */ 964e5ac4200SAndrew Jones if (cpu->kvm_vtime_dirty) { 965e5ac4200SAndrew Jones *kvm_arm_get_cpreg_ptr(cpu, KVM_REG_ARM_TIMER_CNT) = cpu->kvm_vtime; 966e5ac4200SAndrew Jones } 967e5ac4200SAndrew Jones } 968e5ac4200SAndrew Jones 969e5ac4200SAndrew Jones void kvm_arm_cpu_post_load(ARMCPU *cpu) 970e5ac4200SAndrew Jones { 971e5ac4200SAndrew Jones /* KVM virtual time adjustment */ 972e5ac4200SAndrew Jones if (cpu->kvm_adjvtime) { 973e5ac4200SAndrew Jones cpu->kvm_vtime = *kvm_arm_get_cpreg_ptr(cpu, KVM_REG_ARM_TIMER_CNT); 974e5ac4200SAndrew Jones cpu->kvm_vtime_dirty = true; 975e5ac4200SAndrew Jones } 976e5ac4200SAndrew Jones } 977e5ac4200SAndrew Jones 978fcf5ef2aSThomas Huth void kvm_arm_reset_vcpu(ARMCPU *cpu) 979fcf5ef2aSThomas Huth { 980fcf5ef2aSThomas Huth int ret; 981fcf5ef2aSThomas Huth 982fcf5ef2aSThomas Huth /* Re-init VCPU so that all registers are set to 983fcf5ef2aSThomas Huth * their respective reset values. 984fcf5ef2aSThomas Huth */ 985fcf5ef2aSThomas Huth ret = kvm_arm_vcpu_init(CPU(cpu)); 986fcf5ef2aSThomas Huth if (ret < 0) { 987fcf5ef2aSThomas Huth fprintf(stderr, "kvm_arm_vcpu_init failed: %s\n", strerror(-ret)); 988fcf5ef2aSThomas Huth abort(); 989fcf5ef2aSThomas Huth } 990fcf5ef2aSThomas Huth if (!write_kvmstate_to_list(cpu)) { 991fcf5ef2aSThomas Huth fprintf(stderr, "write_kvmstate_to_list failed\n"); 992fcf5ef2aSThomas Huth abort(); 993fcf5ef2aSThomas Huth } 994b698e4eeSPeter Maydell /* 995b698e4eeSPeter Maydell * Sync the reset values also into the CPUState. This is necessary 996b698e4eeSPeter Maydell * because the next thing we do will be a kvm_arch_put_registers() 997b698e4eeSPeter Maydell * which will update the list values from the CPUState before copying 998b698e4eeSPeter Maydell * the list values back to KVM. It's OK to ignore failure returns here 999b698e4eeSPeter Maydell * for the same reason we do so in kvm_arch_get_registers(). 1000b698e4eeSPeter Maydell */ 1001b698e4eeSPeter Maydell write_list_to_cpustate(cpu); 1002fcf5ef2aSThomas Huth } 1003fcf5ef2aSThomas Huth 1004fcf5ef2aSThomas Huth /* 1005fcf5ef2aSThomas Huth * Update KVM's MP_STATE based on what QEMU thinks it is 1006fcf5ef2aSThomas Huth */ 100771c34911SRichard Henderson static int kvm_arm_sync_mpstate_to_kvm(ARMCPU *cpu) 1008fcf5ef2aSThomas Huth { 1009fcf5ef2aSThomas Huth if (cap_has_mp_state) { 1010fcf5ef2aSThomas Huth struct kvm_mp_state mp_state = { 1011062ba099SAlex Bennée .mp_state = (cpu->power_state == PSCI_OFF) ? 1012062ba099SAlex Bennée KVM_MP_STATE_STOPPED : KVM_MP_STATE_RUNNABLE 1013fcf5ef2aSThomas Huth }; 101471c34911SRichard Henderson return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state); 1015fcf5ef2aSThomas Huth } 1016fcf5ef2aSThomas Huth return 0; 1017fcf5ef2aSThomas Huth } 1018fcf5ef2aSThomas Huth 1019fcf5ef2aSThomas Huth /* 1020fcf5ef2aSThomas Huth * Sync the KVM MP_STATE into QEMU 1021fcf5ef2aSThomas Huth */ 102271c34911SRichard Henderson static int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu) 1023fcf5ef2aSThomas Huth { 1024fcf5ef2aSThomas Huth if (cap_has_mp_state) { 1025fcf5ef2aSThomas Huth struct kvm_mp_state mp_state; 1026fcf5ef2aSThomas Huth int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MP_STATE, &mp_state); 1027fcf5ef2aSThomas Huth if (ret) { 102871c34911SRichard Henderson return ret; 1029fcf5ef2aSThomas Huth } 1030062ba099SAlex Bennée cpu->power_state = (mp_state.mp_state == KVM_MP_STATE_STOPPED) ? 1031062ba099SAlex Bennée PSCI_OFF : PSCI_ON; 1032fcf5ef2aSThomas Huth } 1033fcf5ef2aSThomas Huth return 0; 1034fcf5ef2aSThomas Huth } 1035fcf5ef2aSThomas Huth 103646512471SRichard Henderson /** 103746512471SRichard Henderson * kvm_arm_get_virtual_time: 103846512471SRichard Henderson * @cs: CPUState 103946512471SRichard Henderson * 104046512471SRichard Henderson * Gets the VCPU's virtual counter and stores it in the KVM CPU state. 104146512471SRichard Henderson */ 104246512471SRichard Henderson static void kvm_arm_get_virtual_time(CPUState *cs) 1043e5ac4200SAndrew Jones { 1044e5ac4200SAndrew Jones ARMCPU *cpu = ARM_CPU(cs); 1045e5ac4200SAndrew Jones int ret; 1046e5ac4200SAndrew Jones 1047e5ac4200SAndrew Jones if (cpu->kvm_vtime_dirty) { 1048e5ac4200SAndrew Jones return; 1049e5ac4200SAndrew Jones } 1050e5ac4200SAndrew Jones 105140d45b85SCornelia Huck ret = kvm_get_one_reg(cs, KVM_REG_ARM_TIMER_CNT, &cpu->kvm_vtime); 1052e5ac4200SAndrew Jones if (ret) { 1053e5ac4200SAndrew Jones error_report("Failed to get KVM_REG_ARM_TIMER_CNT"); 1054e5ac4200SAndrew Jones abort(); 1055e5ac4200SAndrew Jones } 1056e5ac4200SAndrew Jones 1057e5ac4200SAndrew Jones cpu->kvm_vtime_dirty = true; 1058e5ac4200SAndrew Jones } 1059e5ac4200SAndrew Jones 106046512471SRichard Henderson /** 106146512471SRichard Henderson * kvm_arm_put_virtual_time: 106246512471SRichard Henderson * @cs: CPUState 106346512471SRichard Henderson * 106446512471SRichard Henderson * Sets the VCPU's virtual counter to the value stored in the KVM CPU state. 106546512471SRichard Henderson */ 106646512471SRichard Henderson static void kvm_arm_put_virtual_time(CPUState *cs) 1067e5ac4200SAndrew Jones { 1068e5ac4200SAndrew Jones ARMCPU *cpu = ARM_CPU(cs); 1069e5ac4200SAndrew Jones int ret; 1070e5ac4200SAndrew Jones 1071e5ac4200SAndrew Jones if (!cpu->kvm_vtime_dirty) { 1072e5ac4200SAndrew Jones return; 1073e5ac4200SAndrew Jones } 1074e5ac4200SAndrew Jones 10756c8b9a74SCornelia Huck ret = kvm_set_one_reg(cs, KVM_REG_ARM_TIMER_CNT, &cpu->kvm_vtime); 1076e5ac4200SAndrew Jones if (ret) { 1077e5ac4200SAndrew Jones error_report("Failed to set KVM_REG_ARM_TIMER_CNT"); 1078e5ac4200SAndrew Jones abort(); 1079e5ac4200SAndrew Jones } 1080e5ac4200SAndrew Jones 1081e5ac4200SAndrew Jones cpu->kvm_vtime_dirty = false; 1082e5ac4200SAndrew Jones } 1083e5ac4200SAndrew Jones 1084353e03cdSRichard Henderson /** 1085353e03cdSRichard Henderson * kvm_put_vcpu_events: 1086353e03cdSRichard Henderson * @cpu: ARMCPU 1087353e03cdSRichard Henderson * 1088353e03cdSRichard Henderson * Put VCPU related state to kvm. 1089353e03cdSRichard Henderson * 1090353e03cdSRichard Henderson * Returns: 0 if success else < 0 error code 1091353e03cdSRichard Henderson */ 1092353e03cdSRichard Henderson static int kvm_put_vcpu_events(ARMCPU *cpu) 1093202ccb6bSDongjiu Geng { 1094202ccb6bSDongjiu Geng CPUARMState *env = &cpu->env; 1095202ccb6bSDongjiu Geng struct kvm_vcpu_events events; 1096202ccb6bSDongjiu Geng int ret; 1097202ccb6bSDongjiu Geng 1098202ccb6bSDongjiu Geng if (!kvm_has_vcpu_events()) { 1099202ccb6bSDongjiu Geng return 0; 1100202ccb6bSDongjiu Geng } 1101202ccb6bSDongjiu Geng 1102202ccb6bSDongjiu Geng memset(&events, 0, sizeof(events)); 1103202ccb6bSDongjiu Geng events.exception.serror_pending = env->serror.pending; 1104202ccb6bSDongjiu Geng 1105202ccb6bSDongjiu Geng /* Inject SError to guest with specified syndrome if host kernel 1106202ccb6bSDongjiu Geng * supports it, otherwise inject SError without syndrome. 1107202ccb6bSDongjiu Geng */ 1108202ccb6bSDongjiu Geng if (cap_has_inject_serror_esr) { 1109202ccb6bSDongjiu Geng events.exception.serror_has_esr = env->serror.has_esr; 1110202ccb6bSDongjiu Geng events.exception.serror_esr = env->serror.esr; 1111202ccb6bSDongjiu Geng } 1112202ccb6bSDongjiu Geng 1113202ccb6bSDongjiu Geng ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events); 1114202ccb6bSDongjiu Geng if (ret) { 1115202ccb6bSDongjiu Geng error_report("failed to put vcpu events"); 1116202ccb6bSDongjiu Geng } 1117202ccb6bSDongjiu Geng 1118202ccb6bSDongjiu Geng return ret; 1119202ccb6bSDongjiu Geng } 1120202ccb6bSDongjiu Geng 1121353e03cdSRichard Henderson /** 1122353e03cdSRichard Henderson * kvm_get_vcpu_events: 1123353e03cdSRichard Henderson * @cpu: ARMCPU 1124353e03cdSRichard Henderson * 1125353e03cdSRichard Henderson * Get VCPU related state from kvm. 1126353e03cdSRichard Henderson * 1127353e03cdSRichard Henderson * Returns: 0 if success else < 0 error code 1128353e03cdSRichard Henderson */ 1129353e03cdSRichard Henderson static int kvm_get_vcpu_events(ARMCPU *cpu) 1130202ccb6bSDongjiu Geng { 1131202ccb6bSDongjiu Geng CPUARMState *env = &cpu->env; 1132202ccb6bSDongjiu Geng struct kvm_vcpu_events events; 1133202ccb6bSDongjiu Geng int ret; 1134202ccb6bSDongjiu Geng 1135202ccb6bSDongjiu Geng if (!kvm_has_vcpu_events()) { 1136202ccb6bSDongjiu Geng return 0; 1137202ccb6bSDongjiu Geng } 1138202ccb6bSDongjiu Geng 1139202ccb6bSDongjiu Geng memset(&events, 0, sizeof(events)); 1140202ccb6bSDongjiu Geng ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events); 1141202ccb6bSDongjiu Geng if (ret) { 1142202ccb6bSDongjiu Geng error_report("failed to get vcpu events"); 1143202ccb6bSDongjiu Geng return ret; 1144202ccb6bSDongjiu Geng } 1145202ccb6bSDongjiu Geng 1146202ccb6bSDongjiu Geng env->serror.pending = events.exception.serror_pending; 1147202ccb6bSDongjiu Geng env->serror.has_esr = events.exception.serror_has_esr; 1148202ccb6bSDongjiu Geng env->serror.esr = events.exception.serror_esr; 1149202ccb6bSDongjiu Geng 1150202ccb6bSDongjiu Geng return 0; 1151202ccb6bSDongjiu Geng } 1152202ccb6bSDongjiu Geng 115320c83dc9SRichard Henderson #define ARM64_REG_ESR_EL1 ARM64_SYS_REG(3, 0, 5, 2, 0) 115420c83dc9SRichard Henderson #define ARM64_REG_TCR_EL1 ARM64_SYS_REG(3, 0, 2, 0, 2) 115520c83dc9SRichard Henderson 115620c83dc9SRichard Henderson /* 115720c83dc9SRichard Henderson * ESR_EL1 115820c83dc9SRichard Henderson * ISS encoding 115920c83dc9SRichard Henderson * AARCH64: DFSC, bits [5:0] 116020c83dc9SRichard Henderson * AARCH32: 116120c83dc9SRichard Henderson * TTBCR.EAE == 0 116220c83dc9SRichard Henderson * FS[4] - DFSR[10] 116320c83dc9SRichard Henderson * FS[3:0] - DFSR[3:0] 116420c83dc9SRichard Henderson * TTBCR.EAE == 1 116520c83dc9SRichard Henderson * FS, bits [5:0] 116620c83dc9SRichard Henderson */ 116720c83dc9SRichard Henderson #define ESR_DFSC(aarch64, lpae, v) \ 116820c83dc9SRichard Henderson ((aarch64 || (lpae)) ? ((v) & 0x3F) \ 116920c83dc9SRichard Henderson : (((v) >> 6) | ((v) & 0x1F))) 117020c83dc9SRichard Henderson 117120c83dc9SRichard Henderson #define ESR_DFSC_EXTABT(aarch64, lpae) \ 117220c83dc9SRichard Henderson ((aarch64) ? 0x10 : (lpae) ? 0x10 : 0x8) 117320c83dc9SRichard Henderson 117420c83dc9SRichard Henderson /** 117520c83dc9SRichard Henderson * kvm_arm_verify_ext_dabt_pending: 117620c83dc9SRichard Henderson * @cs: CPUState 117720c83dc9SRichard Henderson * 117820c83dc9SRichard Henderson * Verify the fault status code wrt the Ext DABT injection 117920c83dc9SRichard Henderson * 118020c83dc9SRichard Henderson * Returns: true if the fault status code is as expected, false otherwise 118120c83dc9SRichard Henderson */ 118220c83dc9SRichard Henderson static bool kvm_arm_verify_ext_dabt_pending(CPUState *cs) 118320c83dc9SRichard Henderson { 118420c83dc9SRichard Henderson uint64_t dfsr_val; 118520c83dc9SRichard Henderson 118620c83dc9SRichard Henderson if (!kvm_get_one_reg(cs, ARM64_REG_ESR_EL1, &dfsr_val)) { 118720c83dc9SRichard Henderson ARMCPU *cpu = ARM_CPU(cs); 118820c83dc9SRichard Henderson CPUARMState *env = &cpu->env; 118920c83dc9SRichard Henderson int aarch64_mode = arm_feature(env, ARM_FEATURE_AARCH64); 119020c83dc9SRichard Henderson int lpae = 0; 119120c83dc9SRichard Henderson 119220c83dc9SRichard Henderson if (!aarch64_mode) { 119320c83dc9SRichard Henderson uint64_t ttbcr; 119420c83dc9SRichard Henderson 119520c83dc9SRichard Henderson if (!kvm_get_one_reg(cs, ARM64_REG_TCR_EL1, &ttbcr)) { 119620c83dc9SRichard Henderson lpae = arm_feature(env, ARM_FEATURE_LPAE) 119720c83dc9SRichard Henderson && (ttbcr & TTBCR_EAE); 119820c83dc9SRichard Henderson } 119920c83dc9SRichard Henderson } 120020c83dc9SRichard Henderson /* 120120c83dc9SRichard Henderson * The verification here is based on the DFSC bits 120220c83dc9SRichard Henderson * of the ESR_EL1 reg only 120320c83dc9SRichard Henderson */ 120420c83dc9SRichard Henderson return (ESR_DFSC(aarch64_mode, lpae, dfsr_val) == 120520c83dc9SRichard Henderson ESR_DFSC_EXTABT(aarch64_mode, lpae)); 120620c83dc9SRichard Henderson } 120720c83dc9SRichard Henderson return false; 120820c83dc9SRichard Henderson } 120920c83dc9SRichard Henderson 1210fcf5ef2aSThomas Huth void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) 1211fcf5ef2aSThomas Huth { 12121711bfa5SBeata Michalska ARMCPU *cpu = ARM_CPU(cs); 12131711bfa5SBeata Michalska CPUARMState *env = &cpu->env; 12141711bfa5SBeata Michalska 12151711bfa5SBeata Michalska if (unlikely(env->ext_dabt_raised)) { 12161711bfa5SBeata Michalska /* 12171711bfa5SBeata Michalska * Verifying that the ext DABT has been properly injected, 12181711bfa5SBeata Michalska * otherwise risking indefinitely re-running the faulting instruction 12191711bfa5SBeata Michalska * Covering a very narrow case for kernels 5.5..5.5.4 12201711bfa5SBeata Michalska * when injected abort was misconfigured to be 12211711bfa5SBeata Michalska * an IMPLEMENTATION DEFINED exception (for 32-bit EL1) 12221711bfa5SBeata Michalska */ 12231711bfa5SBeata Michalska if (!arm_feature(env, ARM_FEATURE_AARCH64) && 12241711bfa5SBeata Michalska unlikely(!kvm_arm_verify_ext_dabt_pending(cs))) { 12251711bfa5SBeata Michalska 12261711bfa5SBeata Michalska error_report("Data abort exception with no valid ISS generated by " 12271711bfa5SBeata Michalska "guest memory access. KVM unable to emulate faulting " 12281711bfa5SBeata Michalska "instruction. Failed to inject an external data abort " 12291711bfa5SBeata Michalska "into the guest."); 12301711bfa5SBeata Michalska abort(); 12311711bfa5SBeata Michalska } 12321711bfa5SBeata Michalska /* Clear the status */ 12331711bfa5SBeata Michalska env->ext_dabt_raised = 0; 12341711bfa5SBeata Michalska } 1235fcf5ef2aSThomas Huth } 1236fcf5ef2aSThomas Huth 1237fcf5ef2aSThomas Huth MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) 1238fcf5ef2aSThomas Huth { 12395d721b78SAlexander Graf ARMCPU *cpu; 12405d721b78SAlexander Graf uint32_t switched_level; 12415d721b78SAlexander Graf 12425d721b78SAlexander Graf if (kvm_irqchip_in_kernel()) { 12435d721b78SAlexander Graf /* 12445d721b78SAlexander Graf * We only need to sync timer states with user-space interrupt 12455d721b78SAlexander Graf * controllers, so return early and save cycles if we don't. 12465d721b78SAlexander Graf */ 12475d721b78SAlexander Graf return MEMTXATTRS_UNSPECIFIED; 12485d721b78SAlexander Graf } 12495d721b78SAlexander Graf 12505d721b78SAlexander Graf cpu = ARM_CPU(cs); 12515d721b78SAlexander Graf 12525d721b78SAlexander Graf /* Synchronize our shadowed in-kernel device irq lines with the kvm ones */ 12535d721b78SAlexander Graf if (run->s.regs.device_irq_level != cpu->device_irq_level) { 12545d721b78SAlexander Graf switched_level = cpu->device_irq_level ^ run->s.regs.device_irq_level; 12555d721b78SAlexander Graf 12565d721b78SAlexander Graf qemu_mutex_lock_iothread(); 12575d721b78SAlexander Graf 12585d721b78SAlexander Graf if (switched_level & KVM_ARM_DEV_EL1_VTIMER) { 12595d721b78SAlexander Graf qemu_set_irq(cpu->gt_timer_outputs[GTIMER_VIRT], 12605d721b78SAlexander Graf !!(run->s.regs.device_irq_level & 12615d721b78SAlexander Graf KVM_ARM_DEV_EL1_VTIMER)); 12625d721b78SAlexander Graf switched_level &= ~KVM_ARM_DEV_EL1_VTIMER; 12635d721b78SAlexander Graf } 12645d721b78SAlexander Graf 12655d721b78SAlexander Graf if (switched_level & KVM_ARM_DEV_EL1_PTIMER) { 12665d721b78SAlexander Graf qemu_set_irq(cpu->gt_timer_outputs[GTIMER_PHYS], 12675d721b78SAlexander Graf !!(run->s.regs.device_irq_level & 12685d721b78SAlexander Graf KVM_ARM_DEV_EL1_PTIMER)); 12695d721b78SAlexander Graf switched_level &= ~KVM_ARM_DEV_EL1_PTIMER; 12705d721b78SAlexander Graf } 12715d721b78SAlexander Graf 1272b1659527SAndrew Jones if (switched_level & KVM_ARM_DEV_PMU) { 1273b1659527SAndrew Jones qemu_set_irq(cpu->pmu_interrupt, 1274b1659527SAndrew Jones !!(run->s.regs.device_irq_level & KVM_ARM_DEV_PMU)); 1275b1659527SAndrew Jones switched_level &= ~KVM_ARM_DEV_PMU; 1276b1659527SAndrew Jones } 12775d721b78SAlexander Graf 12785d721b78SAlexander Graf if (switched_level) { 12795d721b78SAlexander Graf qemu_log_mask(LOG_UNIMP, "%s: unhandled in-kernel device IRQ %x\n", 12805d721b78SAlexander Graf __func__, switched_level); 12815d721b78SAlexander Graf } 12825d721b78SAlexander Graf 12835d721b78SAlexander Graf /* We also mark unknown levels as processed to not waste cycles */ 12845d721b78SAlexander Graf cpu->device_irq_level = run->s.regs.device_irq_level; 12855d721b78SAlexander Graf qemu_mutex_unlock_iothread(); 12865d721b78SAlexander Graf } 12875d721b78SAlexander Graf 1288fcf5ef2aSThomas Huth return MEMTXATTRS_UNSPECIFIED; 1289fcf5ef2aSThomas Huth } 1290fcf5ef2aSThomas Huth 1291396b6c50SRichard Henderson static void kvm_arm_vm_state_change(void *opaque, bool running, RunState state) 1292e5ac4200SAndrew Jones { 1293e5ac4200SAndrew Jones CPUState *cs = opaque; 1294e5ac4200SAndrew Jones ARMCPU *cpu = ARM_CPU(cs); 1295e5ac4200SAndrew Jones 1296e5ac4200SAndrew Jones if (running) { 1297e5ac4200SAndrew Jones if (cpu->kvm_adjvtime) { 1298e5ac4200SAndrew Jones kvm_arm_put_virtual_time(cs); 1299e5ac4200SAndrew Jones } 1300e5ac4200SAndrew Jones } else { 1301e5ac4200SAndrew Jones if (cpu->kvm_adjvtime) { 1302e5ac4200SAndrew Jones kvm_arm_get_virtual_time(cs); 1303e5ac4200SAndrew Jones } 1304e5ac4200SAndrew Jones } 1305e5ac4200SAndrew Jones } 1306fcf5ef2aSThomas Huth 1307694bcaa8SBeata Michalska /** 1308694bcaa8SBeata Michalska * kvm_arm_handle_dabt_nisv: 1309694bcaa8SBeata Michalska * @cs: CPUState 1310694bcaa8SBeata Michalska * @esr_iss: ISS encoding (limited) for the exception from Data Abort 1311694bcaa8SBeata Michalska * ISV bit set to '0b0' -> no valid instruction syndrome 1312694bcaa8SBeata Michalska * @fault_ipa: faulting address for the synchronous data abort 1313694bcaa8SBeata Michalska * 1314694bcaa8SBeata Michalska * Returns: 0 if the exception has been handled, < 0 otherwise 1315694bcaa8SBeata Michalska */ 1316694bcaa8SBeata Michalska static int kvm_arm_handle_dabt_nisv(CPUState *cs, uint64_t esr_iss, 1317694bcaa8SBeata Michalska uint64_t fault_ipa) 1318694bcaa8SBeata Michalska { 13191711bfa5SBeata Michalska ARMCPU *cpu = ARM_CPU(cs); 13201711bfa5SBeata Michalska CPUARMState *env = &cpu->env; 1321694bcaa8SBeata Michalska /* 1322694bcaa8SBeata Michalska * Request KVM to inject the external data abort into the guest 1323694bcaa8SBeata Michalska */ 1324694bcaa8SBeata Michalska if (cap_has_inject_ext_dabt) { 1325694bcaa8SBeata Michalska struct kvm_vcpu_events events = { }; 1326694bcaa8SBeata Michalska /* 1327694bcaa8SBeata Michalska * The external data abort event will be handled immediately by KVM 1328694bcaa8SBeata Michalska * using the address fault that triggered the exit on given VCPU. 1329694bcaa8SBeata Michalska * Requesting injection of the external data abort does not rely 1330694bcaa8SBeata Michalska * on any other VCPU state. Therefore, in this particular case, the VCPU 1331694bcaa8SBeata Michalska * synchronization can be exceptionally skipped. 1332694bcaa8SBeata Michalska */ 1333694bcaa8SBeata Michalska events.exception.ext_dabt_pending = 1; 1334694bcaa8SBeata Michalska /* KVM_CAP_ARM_INJECT_EXT_DABT implies KVM_CAP_VCPU_EVENTS */ 13351711bfa5SBeata Michalska if (!kvm_vcpu_ioctl(cs, KVM_SET_VCPU_EVENTS, &events)) { 13361711bfa5SBeata Michalska env->ext_dabt_raised = 1; 13371711bfa5SBeata Michalska return 0; 13381711bfa5SBeata Michalska } 1339694bcaa8SBeata Michalska } else { 1340694bcaa8SBeata Michalska error_report("Data abort exception triggered by guest memory access " 1341694bcaa8SBeata Michalska "at physical address: 0x" TARGET_FMT_lx, 1342694bcaa8SBeata Michalska (target_ulong)fault_ipa); 1343694bcaa8SBeata Michalska error_printf("KVM unable to emulate faulting instruction.\n"); 1344694bcaa8SBeata Michalska } 1345694bcaa8SBeata Michalska return -1; 1346694bcaa8SBeata Michalska } 1347694bcaa8SBeata Michalska 13485cba8f26SRichard Henderson /** 13495cba8f26SRichard Henderson * kvm_arm_handle_debug: 13505cba8f26SRichard Henderson * @cs: CPUState 13515cba8f26SRichard Henderson * @debug_exit: debug part of the KVM exit structure 13525cba8f26SRichard Henderson * 13535cba8f26SRichard Henderson * Returns: TRUE if the debug exception was handled. 13545cba8f26SRichard Henderson * 13555cba8f26SRichard Henderson * See v8 ARM ARM D7.2.27 ESR_ELx, Exception Syndrome Register 13565cba8f26SRichard Henderson * 13575cba8f26SRichard Henderson * To minimise translating between kernel and user-space the kernel 13585cba8f26SRichard Henderson * ABI just provides user-space with the full exception syndrome 13595cba8f26SRichard Henderson * register value to be decoded in QEMU. 13605cba8f26SRichard Henderson */ 13615cba8f26SRichard Henderson static bool kvm_arm_handle_debug(CPUState *cs, 13625cba8f26SRichard Henderson struct kvm_debug_exit_arch *debug_exit) 13635cba8f26SRichard Henderson { 13645cba8f26SRichard Henderson int hsr_ec = syn_get_ec(debug_exit->hsr); 13655cba8f26SRichard Henderson ARMCPU *cpu = ARM_CPU(cs); 13665cba8f26SRichard Henderson CPUARMState *env = &cpu->env; 13675cba8f26SRichard Henderson 13685cba8f26SRichard Henderson /* Ensure PC is synchronised */ 13695cba8f26SRichard Henderson kvm_cpu_synchronize_state(cs); 13705cba8f26SRichard Henderson 13715cba8f26SRichard Henderson switch (hsr_ec) { 13725cba8f26SRichard Henderson case EC_SOFTWARESTEP: 13735cba8f26SRichard Henderson if (cs->singlestep_enabled) { 13745cba8f26SRichard Henderson return true; 13755cba8f26SRichard Henderson } else { 13765cba8f26SRichard Henderson /* 13775cba8f26SRichard Henderson * The kernel should have suppressed the guest's ability to 13785cba8f26SRichard Henderson * single step at this point so something has gone wrong. 13795cba8f26SRichard Henderson */ 13805cba8f26SRichard Henderson error_report("%s: guest single-step while debugging unsupported" 13815cba8f26SRichard Henderson " (%"PRIx64", %"PRIx32")", 13825cba8f26SRichard Henderson __func__, env->pc, debug_exit->hsr); 13835cba8f26SRichard Henderson return false; 13845cba8f26SRichard Henderson } 13855cba8f26SRichard Henderson break; 13865cba8f26SRichard Henderson case EC_AA64_BKPT: 13875cba8f26SRichard Henderson if (kvm_find_sw_breakpoint(cs, env->pc)) { 13885cba8f26SRichard Henderson return true; 13895cba8f26SRichard Henderson } 13905cba8f26SRichard Henderson break; 13915cba8f26SRichard Henderson case EC_BREAKPOINT: 13925cba8f26SRichard Henderson if (find_hw_breakpoint(cs, env->pc)) { 13935cba8f26SRichard Henderson return true; 13945cba8f26SRichard Henderson } 13955cba8f26SRichard Henderson break; 13965cba8f26SRichard Henderson case EC_WATCHPOINT: 13975cba8f26SRichard Henderson { 13985cba8f26SRichard Henderson CPUWatchpoint *wp = find_hw_watchpoint(cs, debug_exit->far); 13995cba8f26SRichard Henderson if (wp) { 14005cba8f26SRichard Henderson cs->watchpoint_hit = wp; 14015cba8f26SRichard Henderson return true; 14025cba8f26SRichard Henderson } 14035cba8f26SRichard Henderson break; 14045cba8f26SRichard Henderson } 14055cba8f26SRichard Henderson default: 14065cba8f26SRichard Henderson error_report("%s: unhandled debug exit (%"PRIx32", %"PRIx64")", 14075cba8f26SRichard Henderson __func__, debug_exit->hsr, env->pc); 14085cba8f26SRichard Henderson } 14095cba8f26SRichard Henderson 14105cba8f26SRichard Henderson /* If we are not handling the debug exception it must belong to 14115cba8f26SRichard Henderson * the guest. Let's re-use the existing TCG interrupt code to set 14125cba8f26SRichard Henderson * everything up properly. 14135cba8f26SRichard Henderson */ 14145cba8f26SRichard Henderson cs->exception_index = EXCP_BKPT; 14155cba8f26SRichard Henderson env->exception.syndrome = debug_exit->hsr; 14165cba8f26SRichard Henderson env->exception.vaddress = debug_exit->far; 14175cba8f26SRichard Henderson env->exception.target_el = 1; 14185cba8f26SRichard Henderson qemu_mutex_lock_iothread(); 14195cba8f26SRichard Henderson arm_cpu_do_interrupt(cs); 14205cba8f26SRichard Henderson qemu_mutex_unlock_iothread(); 14215cba8f26SRichard Henderson 14225cba8f26SRichard Henderson return false; 14235cba8f26SRichard Henderson } 14245cba8f26SRichard Henderson 1425fcf5ef2aSThomas Huth int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 1426fcf5ef2aSThomas Huth { 1427fcf5ef2aSThomas Huth int ret = 0; 1428fcf5ef2aSThomas Huth 1429fcf5ef2aSThomas Huth switch (run->exit_reason) { 1430fcf5ef2aSThomas Huth case KVM_EXIT_DEBUG: 1431fcf5ef2aSThomas Huth if (kvm_arm_handle_debug(cs, &run->debug.arch)) { 1432fcf5ef2aSThomas Huth ret = EXCP_DEBUG; 1433fcf5ef2aSThomas Huth } /* otherwise return to guest */ 1434fcf5ef2aSThomas Huth break; 1435694bcaa8SBeata Michalska case KVM_EXIT_ARM_NISV: 1436694bcaa8SBeata Michalska /* External DABT with no valid iss to decode */ 1437694bcaa8SBeata Michalska ret = kvm_arm_handle_dabt_nisv(cs, run->arm_nisv.esr_iss, 1438694bcaa8SBeata Michalska run->arm_nisv.fault_ipa); 1439694bcaa8SBeata Michalska break; 1440fcf5ef2aSThomas Huth default: 1441fcf5ef2aSThomas Huth qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n", 1442fcf5ef2aSThomas Huth __func__, run->exit_reason); 1443fcf5ef2aSThomas Huth break; 1444fcf5ef2aSThomas Huth } 1445fcf5ef2aSThomas Huth return ret; 1446fcf5ef2aSThomas Huth } 1447fcf5ef2aSThomas Huth 1448fcf5ef2aSThomas Huth bool kvm_arch_stop_on_emulation_error(CPUState *cs) 1449fcf5ef2aSThomas Huth { 1450fcf5ef2aSThomas Huth return true; 1451fcf5ef2aSThomas Huth } 1452fcf5ef2aSThomas Huth 1453fcf5ef2aSThomas Huth int kvm_arch_process_async_events(CPUState *cs) 1454fcf5ef2aSThomas Huth { 1455fcf5ef2aSThomas Huth return 0; 1456fcf5ef2aSThomas Huth } 1457fcf5ef2aSThomas Huth 1458ec4145f7SRichard Henderson /** 1459ea79c599SRichard Henderson * kvm_arm_hw_debug_active: 1460ea79c599SRichard Henderson * @cs: CPU State 1461ea79c599SRichard Henderson * 1462ea79c599SRichard Henderson * Return: TRUE if any hardware breakpoints in use. 1463ea79c599SRichard Henderson */ 1464ea79c599SRichard Henderson static bool kvm_arm_hw_debug_active(CPUState *cs) 1465ea79c599SRichard Henderson { 1466ea79c599SRichard Henderson return ((cur_hw_wps > 0) || (cur_hw_bps > 0)); 1467ea79c599SRichard Henderson } 1468ea79c599SRichard Henderson 1469ea79c599SRichard Henderson /** 1470ec4145f7SRichard Henderson * kvm_arm_copy_hw_debug_data: 1471ec4145f7SRichard Henderson * @ptr: kvm_guest_debug_arch structure 1472ec4145f7SRichard Henderson * 1473ec4145f7SRichard Henderson * Copy the architecture specific debug registers into the 1474ec4145f7SRichard Henderson * kvm_guest_debug ioctl structure. 1475ec4145f7SRichard Henderson */ 1476ec4145f7SRichard Henderson static void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr) 1477ec4145f7SRichard Henderson { 1478ec4145f7SRichard Henderson int i; 1479ec4145f7SRichard Henderson memset(ptr, 0, sizeof(struct kvm_guest_debug_arch)); 1480ec4145f7SRichard Henderson 1481ec4145f7SRichard Henderson for (i = 0; i < max_hw_wps; i++) { 1482ec4145f7SRichard Henderson HWWatchpoint *wp = get_hw_wp(i); 1483ec4145f7SRichard Henderson ptr->dbg_wcr[i] = wp->wcr; 1484ec4145f7SRichard Henderson ptr->dbg_wvr[i] = wp->wvr; 1485ec4145f7SRichard Henderson } 1486ec4145f7SRichard Henderson for (i = 0; i < max_hw_bps; i++) { 1487ec4145f7SRichard Henderson HWBreakpoint *bp = get_hw_bp(i); 1488ec4145f7SRichard Henderson ptr->dbg_bcr[i] = bp->bcr; 1489ec4145f7SRichard Henderson ptr->dbg_bvr[i] = bp->bvr; 1490ec4145f7SRichard Henderson } 1491ec4145f7SRichard Henderson } 1492ec4145f7SRichard Henderson 1493fcf5ef2aSThomas Huth void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg) 1494fcf5ef2aSThomas Huth { 1495fcf5ef2aSThomas Huth if (kvm_sw_breakpoints_active(cs)) { 1496fcf5ef2aSThomas Huth dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP; 1497fcf5ef2aSThomas Huth } 1498fcf5ef2aSThomas Huth if (kvm_arm_hw_debug_active(cs)) { 1499fcf5ef2aSThomas Huth dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW; 1500fcf5ef2aSThomas Huth kvm_arm_copy_hw_debug_data(&dbg->arch); 1501fcf5ef2aSThomas Huth } 1502fcf5ef2aSThomas Huth } 1503fcf5ef2aSThomas Huth 1504fcf5ef2aSThomas Huth void kvm_arch_init_irq_routing(KVMState *s) 1505fcf5ef2aSThomas Huth { 1506fcf5ef2aSThomas Huth } 1507fcf5ef2aSThomas Huth 15084376c40dSPaolo Bonzini int kvm_arch_irqchip_create(KVMState *s) 1509fcf5ef2aSThomas Huth { 15104376c40dSPaolo Bonzini if (kvm_kernel_irqchip_split()) { 151147c182feSCornelia Huck error_report("-machine kernel_irqchip=split is not supported on ARM."); 1512fcf5ef2aSThomas Huth exit(1); 1513fcf5ef2aSThomas Huth } 1514fcf5ef2aSThomas Huth 1515fcf5ef2aSThomas Huth /* If we can create the VGIC using the newer device control API, we 1516fcf5ef2aSThomas Huth * let the device do this when it initializes itself, otherwise we 1517fcf5ef2aSThomas Huth * fall back to the old API */ 1518fcf5ef2aSThomas Huth return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL); 1519fcf5ef2aSThomas Huth } 1520fcf5ef2aSThomas Huth 1521fcf5ef2aSThomas Huth int kvm_arm_vgic_probe(void) 1522fcf5ef2aSThomas Huth { 1523d45efe47SEric Auger int val = 0; 1524d45efe47SEric Auger 1525fcf5ef2aSThomas Huth if (kvm_create_device(kvm_state, 1526fcf5ef2aSThomas Huth KVM_DEV_TYPE_ARM_VGIC_V3, true) == 0) { 1527d45efe47SEric Auger val |= KVM_ARM_VGIC_V3; 1528fcf5ef2aSThomas Huth } 1529d45efe47SEric Auger if (kvm_create_device(kvm_state, 1530d45efe47SEric Auger KVM_DEV_TYPE_ARM_VGIC_V2, true) == 0) { 1531d45efe47SEric Auger val |= KVM_ARM_VGIC_V2; 1532d45efe47SEric Auger } 1533d45efe47SEric Auger return val; 1534fcf5ef2aSThomas Huth } 1535fcf5ef2aSThomas Huth 1536f6530926SEric Auger int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level) 1537f6530926SEric Auger { 1538f6530926SEric Auger int kvm_irq = (irqtype << KVM_ARM_IRQ_TYPE_SHIFT) | irq; 1539f6530926SEric Auger int cpu_idx1 = cpu % 256; 1540f6530926SEric Auger int cpu_idx2 = cpu / 256; 1541f6530926SEric Auger 1542f6530926SEric Auger kvm_irq |= (cpu_idx1 << KVM_ARM_IRQ_VCPU_SHIFT) | 1543f6530926SEric Auger (cpu_idx2 << KVM_ARM_IRQ_VCPU2_SHIFT); 1544f6530926SEric Auger 1545f6530926SEric Auger return kvm_set_irq(kvm_state, kvm_irq, !!level); 1546f6530926SEric Auger } 1547f6530926SEric Auger 1548fcf5ef2aSThomas Huth int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 1549fcf5ef2aSThomas Huth uint64_t address, uint32_t data, PCIDevice *dev) 1550fcf5ef2aSThomas Huth { 1551b05c81d2SEric Auger AddressSpace *as = pci_device_iommu_address_space(dev); 1552b05c81d2SEric Auger hwaddr xlat, len, doorbell_gpa; 1553b05c81d2SEric Auger MemoryRegionSection mrs; 1554b05c81d2SEric Auger MemoryRegion *mr; 1555b05c81d2SEric Auger 1556b05c81d2SEric Auger if (as == &address_space_memory) { 1557fcf5ef2aSThomas Huth return 0; 1558fcf5ef2aSThomas Huth } 1559fcf5ef2aSThomas Huth 1560b05c81d2SEric Auger /* MSI doorbell address is translated by an IOMMU */ 1561b05c81d2SEric Auger 1562dfa0d9b8SHamza Mahfooz RCU_READ_LOCK_GUARD(); 1563dfa0d9b8SHamza Mahfooz 1564bc6b1cecSPeter Maydell mr = address_space_translate(as, address, &xlat, &len, true, 1565bc6b1cecSPeter Maydell MEMTXATTRS_UNSPECIFIED); 1566dfa0d9b8SHamza Mahfooz 1567b05c81d2SEric Auger if (!mr) { 1568dfa0d9b8SHamza Mahfooz return 1; 1569b05c81d2SEric Auger } 1570dfa0d9b8SHamza Mahfooz 1571b05c81d2SEric Auger mrs = memory_region_find(mr, xlat, 1); 1572dfa0d9b8SHamza Mahfooz 1573b05c81d2SEric Auger if (!mrs.mr) { 1574dfa0d9b8SHamza Mahfooz return 1; 1575b05c81d2SEric Auger } 1576b05c81d2SEric Auger 1577b05c81d2SEric Auger doorbell_gpa = mrs.offset_within_address_space; 1578b05c81d2SEric Auger memory_region_unref(mrs.mr); 1579b05c81d2SEric Auger 1580b05c81d2SEric Auger route->u.msi.address_lo = doorbell_gpa; 1581b05c81d2SEric Auger route->u.msi.address_hi = doorbell_gpa >> 32; 1582b05c81d2SEric Auger 1583b05c81d2SEric Auger trace_kvm_arm_fixup_msi_route(address, doorbell_gpa); 1584b05c81d2SEric Auger 1585dfa0d9b8SHamza Mahfooz return 0; 1586b05c81d2SEric Auger } 1587b05c81d2SEric Auger 1588fcf5ef2aSThomas Huth int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 1589fcf5ef2aSThomas Huth int vector, PCIDevice *dev) 1590fcf5ef2aSThomas Huth { 1591fcf5ef2aSThomas Huth return 0; 1592fcf5ef2aSThomas Huth } 1593fcf5ef2aSThomas Huth 1594fcf5ef2aSThomas Huth int kvm_arch_release_virq_post(int virq) 1595fcf5ef2aSThomas Huth { 1596fcf5ef2aSThomas Huth return 0; 1597fcf5ef2aSThomas Huth } 1598fcf5ef2aSThomas Huth 1599fcf5ef2aSThomas Huth int kvm_arch_msi_data_to_gsi(uint32_t data) 1600fcf5ef2aSThomas Huth { 1601fcf5ef2aSThomas Huth return (data - 32) & 0xffff; 1602fcf5ef2aSThomas Huth } 160392a5199bSTom Lendacky 160492a5199bSTom Lendacky bool kvm_arch_cpu_check_are_resettable(void) 160592a5199bSTom Lendacky { 160692a5199bSTom Lendacky return true; 160792a5199bSTom Lendacky } 16083dba0a33SPaolo Bonzini 1609c8f2eb5dSShameer Kolothum static void kvm_arch_get_eager_split_size(Object *obj, Visitor *v, 1610c8f2eb5dSShameer Kolothum const char *name, void *opaque, 1611c8f2eb5dSShameer Kolothum Error **errp) 1612c8f2eb5dSShameer Kolothum { 1613c8f2eb5dSShameer Kolothum KVMState *s = KVM_STATE(obj); 1614c8f2eb5dSShameer Kolothum uint64_t value = s->kvm_eager_split_size; 1615c8f2eb5dSShameer Kolothum 1616c8f2eb5dSShameer Kolothum visit_type_size(v, name, &value, errp); 1617c8f2eb5dSShameer Kolothum } 1618c8f2eb5dSShameer Kolothum 1619c8f2eb5dSShameer Kolothum static void kvm_arch_set_eager_split_size(Object *obj, Visitor *v, 1620c8f2eb5dSShameer Kolothum const char *name, void *opaque, 1621c8f2eb5dSShameer Kolothum Error **errp) 1622c8f2eb5dSShameer Kolothum { 1623c8f2eb5dSShameer Kolothum KVMState *s = KVM_STATE(obj); 1624c8f2eb5dSShameer Kolothum uint64_t value; 1625c8f2eb5dSShameer Kolothum 1626c8f2eb5dSShameer Kolothum if (s->fd != -1) { 1627c8f2eb5dSShameer Kolothum error_setg(errp, "Unable to set early-split-size after KVM has been initialized"); 1628c8f2eb5dSShameer Kolothum return; 1629c8f2eb5dSShameer Kolothum } 1630c8f2eb5dSShameer Kolothum 1631c8f2eb5dSShameer Kolothum if (!visit_type_size(v, name, &value, errp)) { 1632c8f2eb5dSShameer Kolothum return; 1633c8f2eb5dSShameer Kolothum } 1634c8f2eb5dSShameer Kolothum 1635c8f2eb5dSShameer Kolothum if (value && !is_power_of_2(value)) { 1636c8f2eb5dSShameer Kolothum error_setg(errp, "early-split-size must be a power of two"); 1637c8f2eb5dSShameer Kolothum return; 1638c8f2eb5dSShameer Kolothum } 1639c8f2eb5dSShameer Kolothum 1640c8f2eb5dSShameer Kolothum s->kvm_eager_split_size = value; 1641c8f2eb5dSShameer Kolothum } 1642c8f2eb5dSShameer Kolothum 16433dba0a33SPaolo Bonzini void kvm_arch_accel_class_init(ObjectClass *oc) 16443dba0a33SPaolo Bonzini { 1645c8f2eb5dSShameer Kolothum object_class_property_add(oc, "eager-split-size", "size", 1646c8f2eb5dSShameer Kolothum kvm_arch_get_eager_split_size, 1647c8f2eb5dSShameer Kolothum kvm_arch_set_eager_split_size, NULL, NULL); 1648c8f2eb5dSShameer Kolothum 1649c8f2eb5dSShameer Kolothum object_class_property_set_description(oc, "eager-split-size", 1650c8f2eb5dSShameer Kolothum "Eager Page Split chunk size for hugepages. (default: 0, disabled)"); 16513dba0a33SPaolo Bonzini } 1652de3c9601SRichard Henderson 1653de3c9601SRichard Henderson int kvm_arch_insert_hw_breakpoint(vaddr addr, vaddr len, int type) 1654de3c9601SRichard Henderson { 1655de3c9601SRichard Henderson switch (type) { 1656de3c9601SRichard Henderson case GDB_BREAKPOINT_HW: 1657de3c9601SRichard Henderson return insert_hw_breakpoint(addr); 1658de3c9601SRichard Henderson break; 1659de3c9601SRichard Henderson case GDB_WATCHPOINT_READ: 1660de3c9601SRichard Henderson case GDB_WATCHPOINT_WRITE: 1661de3c9601SRichard Henderson case GDB_WATCHPOINT_ACCESS: 1662de3c9601SRichard Henderson return insert_hw_watchpoint(addr, len, type); 1663de3c9601SRichard Henderson default: 1664de3c9601SRichard Henderson return -ENOSYS; 1665de3c9601SRichard Henderson } 1666de3c9601SRichard Henderson } 1667de3c9601SRichard Henderson 1668de3c9601SRichard Henderson int kvm_arch_remove_hw_breakpoint(vaddr addr, vaddr len, int type) 1669de3c9601SRichard Henderson { 1670de3c9601SRichard Henderson switch (type) { 1671de3c9601SRichard Henderson case GDB_BREAKPOINT_HW: 1672de3c9601SRichard Henderson return delete_hw_breakpoint(addr); 1673de3c9601SRichard Henderson case GDB_WATCHPOINT_READ: 1674de3c9601SRichard Henderson case GDB_WATCHPOINT_WRITE: 1675de3c9601SRichard Henderson case GDB_WATCHPOINT_ACCESS: 1676de3c9601SRichard Henderson return delete_hw_watchpoint(addr, len, type); 1677de3c9601SRichard Henderson default: 1678de3c9601SRichard Henderson return -ENOSYS; 1679de3c9601SRichard Henderson } 1680de3c9601SRichard Henderson } 1681de3c9601SRichard Henderson 1682de3c9601SRichard Henderson void kvm_arch_remove_all_hw_breakpoints(void) 1683de3c9601SRichard Henderson { 1684de3c9601SRichard Henderson if (cur_hw_wps > 0) { 1685de3c9601SRichard Henderson g_array_remove_range(hw_watchpoints, 0, cur_hw_wps); 1686de3c9601SRichard Henderson } 1687de3c9601SRichard Henderson if (cur_hw_bps > 0) { 1688de3c9601SRichard Henderson g_array_remove_range(hw_breakpoints, 0, cur_hw_bps); 1689de3c9601SRichard Henderson } 1690de3c9601SRichard Henderson } 1691de3c9601SRichard Henderson 1692de3c9601SRichard Henderson static bool kvm_arm_set_device_attr(CPUState *cs, struct kvm_device_attr *attr, 1693de3c9601SRichard Henderson const char *name) 1694de3c9601SRichard Henderson { 1695de3c9601SRichard Henderson int err; 1696de3c9601SRichard Henderson 1697de3c9601SRichard Henderson err = kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, attr); 1698de3c9601SRichard Henderson if (err != 0) { 1699de3c9601SRichard Henderson error_report("%s: KVM_HAS_DEVICE_ATTR: %s", name, strerror(-err)); 1700de3c9601SRichard Henderson return false; 1701de3c9601SRichard Henderson } 1702de3c9601SRichard Henderson 1703de3c9601SRichard Henderson err = kvm_vcpu_ioctl(cs, KVM_SET_DEVICE_ATTR, attr); 1704de3c9601SRichard Henderson if (err != 0) { 1705de3c9601SRichard Henderson error_report("%s: KVM_SET_DEVICE_ATTR: %s", name, strerror(-err)); 1706de3c9601SRichard Henderson return false; 1707de3c9601SRichard Henderson } 1708de3c9601SRichard Henderson 1709de3c9601SRichard Henderson return true; 1710de3c9601SRichard Henderson } 1711de3c9601SRichard Henderson 1712de3c9601SRichard Henderson void kvm_arm_pmu_init(CPUState *cs) 1713de3c9601SRichard Henderson { 1714de3c9601SRichard Henderson struct kvm_device_attr attr = { 1715de3c9601SRichard Henderson .group = KVM_ARM_VCPU_PMU_V3_CTRL, 1716de3c9601SRichard Henderson .attr = KVM_ARM_VCPU_PMU_V3_INIT, 1717de3c9601SRichard Henderson }; 1718de3c9601SRichard Henderson 1719de3c9601SRichard Henderson if (!ARM_CPU(cs)->has_pmu) { 1720de3c9601SRichard Henderson return; 1721de3c9601SRichard Henderson } 1722de3c9601SRichard Henderson if (!kvm_arm_set_device_attr(cs, &attr, "PMU")) { 1723de3c9601SRichard Henderson error_report("failed to init PMU"); 1724de3c9601SRichard Henderson abort(); 1725de3c9601SRichard Henderson } 1726de3c9601SRichard Henderson } 1727de3c9601SRichard Henderson 1728de3c9601SRichard Henderson void kvm_arm_pmu_set_irq(CPUState *cs, int irq) 1729de3c9601SRichard Henderson { 1730de3c9601SRichard Henderson struct kvm_device_attr attr = { 1731de3c9601SRichard Henderson .group = KVM_ARM_VCPU_PMU_V3_CTRL, 1732de3c9601SRichard Henderson .addr = (intptr_t)&irq, 1733de3c9601SRichard Henderson .attr = KVM_ARM_VCPU_PMU_V3_IRQ, 1734de3c9601SRichard Henderson }; 1735de3c9601SRichard Henderson 1736de3c9601SRichard Henderson if (!ARM_CPU(cs)->has_pmu) { 1737de3c9601SRichard Henderson return; 1738de3c9601SRichard Henderson } 1739de3c9601SRichard Henderson if (!kvm_arm_set_device_attr(cs, &attr, "PMU")) { 1740de3c9601SRichard Henderson error_report("failed to set irq for PMU"); 1741de3c9601SRichard Henderson abort(); 1742de3c9601SRichard Henderson } 1743de3c9601SRichard Henderson } 1744de3c9601SRichard Henderson 1745de3c9601SRichard Henderson void kvm_arm_pvtime_init(CPUState *cs, uint64_t ipa) 1746de3c9601SRichard Henderson { 1747de3c9601SRichard Henderson struct kvm_device_attr attr = { 1748de3c9601SRichard Henderson .group = KVM_ARM_VCPU_PVTIME_CTRL, 1749de3c9601SRichard Henderson .attr = KVM_ARM_VCPU_PVTIME_IPA, 1750de3c9601SRichard Henderson .addr = (uint64_t)&ipa, 1751de3c9601SRichard Henderson }; 1752de3c9601SRichard Henderson 1753de3c9601SRichard Henderson if (ARM_CPU(cs)->kvm_steal_time == ON_OFF_AUTO_OFF) { 1754de3c9601SRichard Henderson return; 1755de3c9601SRichard Henderson } 1756de3c9601SRichard Henderson if (!kvm_arm_set_device_attr(cs, &attr, "PVTIME IPA")) { 1757de3c9601SRichard Henderson error_report("failed to init PVTIME IPA"); 1758de3c9601SRichard Henderson abort(); 1759de3c9601SRichard Henderson } 1760de3c9601SRichard Henderson } 1761de3c9601SRichard Henderson 1762de3c9601SRichard Henderson void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp) 1763de3c9601SRichard Henderson { 1764de3c9601SRichard Henderson bool has_steal_time = kvm_check_extension(kvm_state, KVM_CAP_STEAL_TIME); 1765de3c9601SRichard Henderson 1766de3c9601SRichard Henderson if (cpu->kvm_steal_time == ON_OFF_AUTO_AUTO) { 1767de3c9601SRichard Henderson if (!has_steal_time || !arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1768de3c9601SRichard Henderson cpu->kvm_steal_time = ON_OFF_AUTO_OFF; 1769de3c9601SRichard Henderson } else { 1770de3c9601SRichard Henderson cpu->kvm_steal_time = ON_OFF_AUTO_ON; 1771de3c9601SRichard Henderson } 1772de3c9601SRichard Henderson } else if (cpu->kvm_steal_time == ON_OFF_AUTO_ON) { 1773de3c9601SRichard Henderson if (!has_steal_time) { 1774de3c9601SRichard Henderson error_setg(errp, "'kvm-steal-time' cannot be enabled " 1775de3c9601SRichard Henderson "on this host"); 1776de3c9601SRichard Henderson return; 1777de3c9601SRichard Henderson } else if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1778de3c9601SRichard Henderson /* 1779de3c9601SRichard Henderson * DEN0057A chapter 2 says "This specification only covers 1780de3c9601SRichard Henderson * systems in which the Execution state of the hypervisor 1781de3c9601SRichard Henderson * as well as EL1 of virtual machines is AArch64.". And, 1782de3c9601SRichard Henderson * to ensure that, the smc/hvc calls are only specified as 1783de3c9601SRichard Henderson * smc64/hvc64. 1784de3c9601SRichard Henderson */ 1785de3c9601SRichard Henderson error_setg(errp, "'kvm-steal-time' cannot be enabled " 1786de3c9601SRichard Henderson "for AArch32 guests"); 1787de3c9601SRichard Henderson return; 1788de3c9601SRichard Henderson } 1789de3c9601SRichard Henderson } 1790de3c9601SRichard Henderson } 1791de3c9601SRichard Henderson 1792de3c9601SRichard Henderson bool kvm_arm_aarch32_supported(void) 1793de3c9601SRichard Henderson { 1794de3c9601SRichard Henderson return kvm_check_extension(kvm_state, KVM_CAP_ARM_EL1_32BIT); 1795de3c9601SRichard Henderson } 1796de3c9601SRichard Henderson 1797de3c9601SRichard Henderson bool kvm_arm_sve_supported(void) 1798de3c9601SRichard Henderson { 1799de3c9601SRichard Henderson return kvm_check_extension(kvm_state, KVM_CAP_ARM_SVE); 1800de3c9601SRichard Henderson } 1801de3c9601SRichard Henderson 1802de3c9601SRichard Henderson QEMU_BUILD_BUG_ON(KVM_ARM64_SVE_VQ_MIN != 1); 1803de3c9601SRichard Henderson 1804*d6339282SPhilippe Mathieu-Daudé uint32_t kvm_arm_sve_get_vls(ARMCPU *cpu) 1805de3c9601SRichard Henderson { 1806de3c9601SRichard Henderson /* Only call this function if kvm_arm_sve_supported() returns true. */ 1807de3c9601SRichard Henderson static uint64_t vls[KVM_ARM64_SVE_VLS_WORDS]; 1808de3c9601SRichard Henderson static bool probed; 1809de3c9601SRichard Henderson uint32_t vq = 0; 1810de3c9601SRichard Henderson int i; 1811de3c9601SRichard Henderson 1812de3c9601SRichard Henderson /* 1813de3c9601SRichard Henderson * KVM ensures all host CPUs support the same set of vector lengths. 1814de3c9601SRichard Henderson * So we only need to create the scratch VCPUs once and then cache 1815de3c9601SRichard Henderson * the results. 1816de3c9601SRichard Henderson */ 1817de3c9601SRichard Henderson if (!probed) { 1818de3c9601SRichard Henderson struct kvm_vcpu_init init = { 1819de3c9601SRichard Henderson .target = -1, 1820de3c9601SRichard Henderson .features[0] = (1 << KVM_ARM_VCPU_SVE), 1821de3c9601SRichard Henderson }; 1822de3c9601SRichard Henderson struct kvm_one_reg reg = { 1823de3c9601SRichard Henderson .id = KVM_REG_ARM64_SVE_VLS, 1824de3c9601SRichard Henderson .addr = (uint64_t)&vls[0], 1825de3c9601SRichard Henderson }; 1826de3c9601SRichard Henderson int fdarray[3], ret; 1827de3c9601SRichard Henderson 1828de3c9601SRichard Henderson probed = true; 1829de3c9601SRichard Henderson 1830de3c9601SRichard Henderson if (!kvm_arm_create_scratch_host_vcpu(NULL, fdarray, &init)) { 1831de3c9601SRichard Henderson error_report("failed to create scratch VCPU with SVE enabled"); 1832de3c9601SRichard Henderson abort(); 1833de3c9601SRichard Henderson } 1834de3c9601SRichard Henderson ret = ioctl(fdarray[2], KVM_GET_ONE_REG, ®); 1835de3c9601SRichard Henderson kvm_arm_destroy_scratch_host_vcpu(fdarray); 1836de3c9601SRichard Henderson if (ret) { 1837de3c9601SRichard Henderson error_report("failed to get KVM_REG_ARM64_SVE_VLS: %s", 1838de3c9601SRichard Henderson strerror(errno)); 1839de3c9601SRichard Henderson abort(); 1840de3c9601SRichard Henderson } 1841de3c9601SRichard Henderson 1842de3c9601SRichard Henderson for (i = KVM_ARM64_SVE_VLS_WORDS - 1; i >= 0; --i) { 1843de3c9601SRichard Henderson if (vls[i]) { 1844de3c9601SRichard Henderson vq = 64 - clz64(vls[i]) + i * 64; 1845de3c9601SRichard Henderson break; 1846de3c9601SRichard Henderson } 1847de3c9601SRichard Henderson } 1848de3c9601SRichard Henderson if (vq > ARM_MAX_VQ) { 1849de3c9601SRichard Henderson warn_report("KVM supports vector lengths larger than " 1850de3c9601SRichard Henderson "QEMU can enable"); 1851de3c9601SRichard Henderson vls[0] &= MAKE_64BIT_MASK(0, ARM_MAX_VQ); 1852de3c9601SRichard Henderson } 1853de3c9601SRichard Henderson } 1854de3c9601SRichard Henderson 1855de3c9601SRichard Henderson return vls[0]; 1856de3c9601SRichard Henderson } 1857de3c9601SRichard Henderson 1858bc1b09b3SPhilippe Mathieu-Daudé static int kvm_arm_sve_set_vls(ARMCPU *cpu) 1859de3c9601SRichard Henderson { 1860de3c9601SRichard Henderson uint64_t vls[KVM_ARM64_SVE_VLS_WORDS] = { cpu->sve_vq.map }; 1861de3c9601SRichard Henderson 1862de3c9601SRichard Henderson assert(cpu->sve_max_vq <= KVM_ARM64_SVE_VQ_MAX); 1863de3c9601SRichard Henderson 1864bc1b09b3SPhilippe Mathieu-Daudé return kvm_set_one_reg(CPU(cpu), KVM_REG_ARM64_SVE_VLS, &vls[0]); 1865de3c9601SRichard Henderson } 1866de3c9601SRichard Henderson 1867de3c9601SRichard Henderson #define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5 1868de3c9601SRichard Henderson 1869de3c9601SRichard Henderson int kvm_arch_init_vcpu(CPUState *cs) 1870de3c9601SRichard Henderson { 1871de3c9601SRichard Henderson int ret; 1872de3c9601SRichard Henderson uint64_t mpidr; 1873de3c9601SRichard Henderson ARMCPU *cpu = ARM_CPU(cs); 1874de3c9601SRichard Henderson CPUARMState *env = &cpu->env; 1875de3c9601SRichard Henderson uint64_t psciver; 1876de3c9601SRichard Henderson 1877de3c9601SRichard Henderson if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE || 1878de3c9601SRichard Henderson !object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU)) { 1879de3c9601SRichard Henderson error_report("KVM is not supported for this guest CPU type"); 1880de3c9601SRichard Henderson return -EINVAL; 1881de3c9601SRichard Henderson } 1882de3c9601SRichard Henderson 1883de3c9601SRichard Henderson qemu_add_vm_change_state_handler(kvm_arm_vm_state_change, cs); 1884de3c9601SRichard Henderson 1885de3c9601SRichard Henderson /* Determine init features for this CPU */ 1886de3c9601SRichard Henderson memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features)); 1887de3c9601SRichard Henderson if (cs->start_powered_off) { 1888de3c9601SRichard Henderson cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_POWER_OFF; 1889de3c9601SRichard Henderson } 1890de3c9601SRichard Henderson if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PSCI_0_2)) { 1891de3c9601SRichard Henderson cpu->psci_version = QEMU_PSCI_VERSION_0_2; 1892de3c9601SRichard Henderson cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2; 1893de3c9601SRichard Henderson } 1894de3c9601SRichard Henderson if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1895de3c9601SRichard Henderson cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_EL1_32BIT; 1896de3c9601SRichard Henderson } 1897de3c9601SRichard Henderson if (!kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PMU_V3)) { 1898de3c9601SRichard Henderson cpu->has_pmu = false; 1899de3c9601SRichard Henderson } 1900de3c9601SRichard Henderson if (cpu->has_pmu) { 1901de3c9601SRichard Henderson cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PMU_V3; 1902de3c9601SRichard Henderson } else { 1903de3c9601SRichard Henderson env->features &= ~(1ULL << ARM_FEATURE_PMU); 1904de3c9601SRichard Henderson } 1905de3c9601SRichard Henderson if (cpu_isar_feature(aa64_sve, cpu)) { 1906de3c9601SRichard Henderson assert(kvm_arm_sve_supported()); 1907de3c9601SRichard Henderson cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_SVE; 1908de3c9601SRichard Henderson } 1909de3c9601SRichard Henderson if (cpu_isar_feature(aa64_pauth, cpu)) { 1910de3c9601SRichard Henderson cpu->kvm_init_features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | 1911de3c9601SRichard Henderson 1 << KVM_ARM_VCPU_PTRAUTH_GENERIC); 1912de3c9601SRichard Henderson } 1913de3c9601SRichard Henderson 1914de3c9601SRichard Henderson /* Do KVM_ARM_VCPU_INIT ioctl */ 1915de3c9601SRichard Henderson ret = kvm_arm_vcpu_init(cs); 1916de3c9601SRichard Henderson if (ret) { 1917de3c9601SRichard Henderson return ret; 1918de3c9601SRichard Henderson } 1919de3c9601SRichard Henderson 1920de3c9601SRichard Henderson if (cpu_isar_feature(aa64_sve, cpu)) { 1921bc1b09b3SPhilippe Mathieu-Daudé ret = kvm_arm_sve_set_vls(cpu); 1922de3c9601SRichard Henderson if (ret) { 1923de3c9601SRichard Henderson return ret; 1924de3c9601SRichard Henderson } 1925de3c9601SRichard Henderson ret = kvm_arm_vcpu_finalize(cs, KVM_ARM_VCPU_SVE); 1926de3c9601SRichard Henderson if (ret) { 1927de3c9601SRichard Henderson return ret; 1928de3c9601SRichard Henderson } 1929de3c9601SRichard Henderson } 1930de3c9601SRichard Henderson 1931de3c9601SRichard Henderson /* 1932de3c9601SRichard Henderson * KVM reports the exact PSCI version it is implementing via a 1933de3c9601SRichard Henderson * special sysreg. If it is present, use its contents to determine 1934de3c9601SRichard Henderson * what to report to the guest in the dtb (it is the PSCI version, 1935de3c9601SRichard Henderson * in the same 15-bits major 16-bits minor format that PSCI_VERSION 1936de3c9601SRichard Henderson * returns). 1937de3c9601SRichard Henderson */ 1938de3c9601SRichard Henderson if (!kvm_get_one_reg(cs, KVM_REG_ARM_PSCI_VERSION, &psciver)) { 1939de3c9601SRichard Henderson cpu->psci_version = psciver; 1940de3c9601SRichard Henderson } 1941de3c9601SRichard Henderson 1942de3c9601SRichard Henderson /* 1943de3c9601SRichard Henderson * When KVM is in use, PSCI is emulated in-kernel and not by qemu. 1944de3c9601SRichard Henderson * Currently KVM has its own idea about MPIDR assignment, so we 1945de3c9601SRichard Henderson * override our defaults with what we get from KVM. 1946de3c9601SRichard Henderson */ 1947de3c9601SRichard Henderson ret = kvm_get_one_reg(cs, ARM64_SYS_REG(ARM_CPU_ID_MPIDR), &mpidr); 1948de3c9601SRichard Henderson if (ret) { 1949de3c9601SRichard Henderson return ret; 1950de3c9601SRichard Henderson } 1951de3c9601SRichard Henderson cpu->mp_affinity = mpidr & ARM64_AFFINITY_MASK; 1952de3c9601SRichard Henderson 1953de3c9601SRichard Henderson return kvm_arm_init_cpreg_list(cpu); 1954de3c9601SRichard Henderson } 1955de3c9601SRichard Henderson 1956de3c9601SRichard Henderson int kvm_arch_destroy_vcpu(CPUState *cs) 1957de3c9601SRichard Henderson { 1958de3c9601SRichard Henderson return 0; 1959de3c9601SRichard Henderson } 1960de3c9601SRichard Henderson 1961de3c9601SRichard Henderson /* Callers must hold the iothread mutex lock */ 1962de3c9601SRichard Henderson static void kvm_inject_arm_sea(CPUState *c) 1963de3c9601SRichard Henderson { 1964de3c9601SRichard Henderson ARMCPU *cpu = ARM_CPU(c); 1965de3c9601SRichard Henderson CPUARMState *env = &cpu->env; 1966de3c9601SRichard Henderson uint32_t esr; 1967de3c9601SRichard Henderson bool same_el; 1968de3c9601SRichard Henderson 1969de3c9601SRichard Henderson c->exception_index = EXCP_DATA_ABORT; 1970de3c9601SRichard Henderson env->exception.target_el = 1; 1971de3c9601SRichard Henderson 1972de3c9601SRichard Henderson /* 1973de3c9601SRichard Henderson * Set the DFSC to synchronous external abort and set FnV to not valid, 1974de3c9601SRichard Henderson * this will tell guest the FAR_ELx is UNKNOWN for this abort. 1975de3c9601SRichard Henderson */ 1976de3c9601SRichard Henderson same_el = arm_current_el(env) == env->exception.target_el; 1977de3c9601SRichard Henderson esr = syn_data_abort_no_iss(same_el, 1, 0, 0, 0, 0, 0x10); 1978de3c9601SRichard Henderson 1979de3c9601SRichard Henderson env->exception.syndrome = esr; 1980de3c9601SRichard Henderson 1981de3c9601SRichard Henderson arm_cpu_do_interrupt(c); 1982de3c9601SRichard Henderson } 1983de3c9601SRichard Henderson 1984de3c9601SRichard Henderson #define AARCH64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \ 1985de3c9601SRichard Henderson KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x)) 1986de3c9601SRichard Henderson 1987de3c9601SRichard Henderson #define AARCH64_SIMD_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U128 | \ 1988de3c9601SRichard Henderson KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x)) 1989de3c9601SRichard Henderson 1990de3c9601SRichard Henderson #define AARCH64_SIMD_CTRL_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U32 | \ 1991de3c9601SRichard Henderson KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x)) 1992de3c9601SRichard Henderson 1993de3c9601SRichard Henderson static int kvm_arch_put_fpsimd(CPUState *cs) 1994de3c9601SRichard Henderson { 1995de3c9601SRichard Henderson CPUARMState *env = &ARM_CPU(cs)->env; 1996de3c9601SRichard Henderson int i, ret; 1997de3c9601SRichard Henderson 1998de3c9601SRichard Henderson for (i = 0; i < 32; i++) { 1999de3c9601SRichard Henderson uint64_t *q = aa64_vfp_qreg(env, i); 2000de3c9601SRichard Henderson #if HOST_BIG_ENDIAN 2001de3c9601SRichard Henderson uint64_t fp_val[2] = { q[1], q[0] }; 2002de3c9601SRichard Henderson ret = kvm_set_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]), 2003de3c9601SRichard Henderson fp_val); 2004de3c9601SRichard Henderson #else 2005de3c9601SRichard Henderson ret = kvm_set_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]), q); 2006de3c9601SRichard Henderson #endif 2007de3c9601SRichard Henderson if (ret) { 2008de3c9601SRichard Henderson return ret; 2009de3c9601SRichard Henderson } 2010de3c9601SRichard Henderson } 2011de3c9601SRichard Henderson 2012de3c9601SRichard Henderson return 0; 2013de3c9601SRichard Henderson } 2014de3c9601SRichard Henderson 2015de3c9601SRichard Henderson /* 2016de3c9601SRichard Henderson * KVM SVE registers come in slices where ZREGs have a slice size of 2048 bits 2017de3c9601SRichard Henderson * and PREGS and the FFR have a slice size of 256 bits. However we simply hard 2018de3c9601SRichard Henderson * code the slice index to zero for now as it's unlikely we'll need more than 2019de3c9601SRichard Henderson * one slice for quite some time. 2020de3c9601SRichard Henderson */ 2021de3c9601SRichard Henderson static int kvm_arch_put_sve(CPUState *cs) 2022de3c9601SRichard Henderson { 2023de3c9601SRichard Henderson ARMCPU *cpu = ARM_CPU(cs); 2024de3c9601SRichard Henderson CPUARMState *env = &cpu->env; 2025de3c9601SRichard Henderson uint64_t tmp[ARM_MAX_VQ * 2]; 2026de3c9601SRichard Henderson uint64_t *r; 2027de3c9601SRichard Henderson int n, ret; 2028de3c9601SRichard Henderson 2029de3c9601SRichard Henderson for (n = 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) { 2030de3c9601SRichard Henderson r = sve_bswap64(tmp, &env->vfp.zregs[n].d[0], cpu->sve_max_vq * 2); 2031de3c9601SRichard Henderson ret = kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_ZREG(n, 0), r); 2032de3c9601SRichard Henderson if (ret) { 2033de3c9601SRichard Henderson return ret; 2034de3c9601SRichard Henderson } 2035de3c9601SRichard Henderson } 2036de3c9601SRichard Henderson 2037de3c9601SRichard Henderson for (n = 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) { 2038de3c9601SRichard Henderson r = sve_bswap64(tmp, r = &env->vfp.pregs[n].p[0], 2039de3c9601SRichard Henderson DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); 2040de3c9601SRichard Henderson ret = kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_PREG(n, 0), r); 2041de3c9601SRichard Henderson if (ret) { 2042de3c9601SRichard Henderson return ret; 2043de3c9601SRichard Henderson } 2044de3c9601SRichard Henderson } 2045de3c9601SRichard Henderson 2046de3c9601SRichard Henderson r = sve_bswap64(tmp, &env->vfp.pregs[FFR_PRED_NUM].p[0], 2047de3c9601SRichard Henderson DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); 2048de3c9601SRichard Henderson ret = kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_FFR(0), r); 2049de3c9601SRichard Henderson if (ret) { 2050de3c9601SRichard Henderson return ret; 2051de3c9601SRichard Henderson } 2052de3c9601SRichard Henderson 2053de3c9601SRichard Henderson return 0; 2054de3c9601SRichard Henderson } 2055de3c9601SRichard Henderson 2056de3c9601SRichard Henderson int kvm_arch_put_registers(CPUState *cs, int level) 2057de3c9601SRichard Henderson { 2058de3c9601SRichard Henderson uint64_t val; 2059de3c9601SRichard Henderson uint32_t fpr; 2060de3c9601SRichard Henderson int i, ret; 2061de3c9601SRichard Henderson unsigned int el; 2062de3c9601SRichard Henderson 2063de3c9601SRichard Henderson ARMCPU *cpu = ARM_CPU(cs); 2064de3c9601SRichard Henderson CPUARMState *env = &cpu->env; 2065de3c9601SRichard Henderson 2066de3c9601SRichard Henderson /* If we are in AArch32 mode then we need to copy the AArch32 regs to the 2067de3c9601SRichard Henderson * AArch64 registers before pushing them out to 64-bit KVM. 2068de3c9601SRichard Henderson */ 2069de3c9601SRichard Henderson if (!is_a64(env)) { 2070de3c9601SRichard Henderson aarch64_sync_32_to_64(env); 2071de3c9601SRichard Henderson } 2072de3c9601SRichard Henderson 2073de3c9601SRichard Henderson for (i = 0; i < 31; i++) { 2074de3c9601SRichard Henderson ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.regs[i]), 2075de3c9601SRichard Henderson &env->xregs[i]); 2076de3c9601SRichard Henderson if (ret) { 2077de3c9601SRichard Henderson return ret; 2078de3c9601SRichard Henderson } 2079de3c9601SRichard Henderson } 2080de3c9601SRichard Henderson 2081de3c9601SRichard Henderson /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the 2082de3c9601SRichard Henderson * QEMU side we keep the current SP in xregs[31] as well. 2083de3c9601SRichard Henderson */ 2084de3c9601SRichard Henderson aarch64_save_sp(env, 1); 2085de3c9601SRichard Henderson 2086de3c9601SRichard Henderson ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.sp), &env->sp_el[0]); 2087de3c9601SRichard Henderson if (ret) { 2088de3c9601SRichard Henderson return ret; 2089de3c9601SRichard Henderson } 2090de3c9601SRichard Henderson 2091de3c9601SRichard Henderson ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(sp_el1), &env->sp_el[1]); 2092de3c9601SRichard Henderson if (ret) { 2093de3c9601SRichard Henderson return ret; 2094de3c9601SRichard Henderson } 2095de3c9601SRichard Henderson 2096de3c9601SRichard Henderson /* Note that KVM thinks pstate is 64 bit but we use a uint32_t */ 2097de3c9601SRichard Henderson if (is_a64(env)) { 2098de3c9601SRichard Henderson val = pstate_read(env); 2099de3c9601SRichard Henderson } else { 2100de3c9601SRichard Henderson val = cpsr_read(env); 2101de3c9601SRichard Henderson } 2102de3c9601SRichard Henderson ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.pstate), &val); 2103de3c9601SRichard Henderson if (ret) { 2104de3c9601SRichard Henderson return ret; 2105de3c9601SRichard Henderson } 2106de3c9601SRichard Henderson 2107de3c9601SRichard Henderson ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.pc), &env->pc); 2108de3c9601SRichard Henderson if (ret) { 2109de3c9601SRichard Henderson return ret; 2110de3c9601SRichard Henderson } 2111de3c9601SRichard Henderson 2112de3c9601SRichard Henderson ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(elr_el1), &env->elr_el[1]); 2113de3c9601SRichard Henderson if (ret) { 2114de3c9601SRichard Henderson return ret; 2115de3c9601SRichard Henderson } 2116de3c9601SRichard Henderson 2117de3c9601SRichard Henderson /* Saved Program State Registers 2118de3c9601SRichard Henderson * 2119de3c9601SRichard Henderson * Before we restore from the banked_spsr[] array we need to 2120de3c9601SRichard Henderson * ensure that any modifications to env->spsr are correctly 2121de3c9601SRichard Henderson * reflected in the banks. 2122de3c9601SRichard Henderson */ 2123de3c9601SRichard Henderson el = arm_current_el(env); 2124de3c9601SRichard Henderson if (el > 0 && !is_a64(env)) { 2125de3c9601SRichard Henderson i = bank_number(env->uncached_cpsr & CPSR_M); 2126de3c9601SRichard Henderson env->banked_spsr[i] = env->spsr; 2127de3c9601SRichard Henderson } 2128de3c9601SRichard Henderson 2129de3c9601SRichard Henderson /* KVM 0-4 map to QEMU banks 1-5 */ 2130de3c9601SRichard Henderson for (i = 0; i < KVM_NR_SPSR; i++) { 2131de3c9601SRichard Henderson ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(spsr[i]), 2132de3c9601SRichard Henderson &env->banked_spsr[i + 1]); 2133de3c9601SRichard Henderson if (ret) { 2134de3c9601SRichard Henderson return ret; 2135de3c9601SRichard Henderson } 2136de3c9601SRichard Henderson } 2137de3c9601SRichard Henderson 2138de3c9601SRichard Henderson if (cpu_isar_feature(aa64_sve, cpu)) { 2139de3c9601SRichard Henderson ret = kvm_arch_put_sve(cs); 2140de3c9601SRichard Henderson } else { 2141de3c9601SRichard Henderson ret = kvm_arch_put_fpsimd(cs); 2142de3c9601SRichard Henderson } 2143de3c9601SRichard Henderson if (ret) { 2144de3c9601SRichard Henderson return ret; 2145de3c9601SRichard Henderson } 2146de3c9601SRichard Henderson 2147de3c9601SRichard Henderson fpr = vfp_get_fpsr(env); 2148de3c9601SRichard Henderson ret = kvm_set_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpsr), &fpr); 2149de3c9601SRichard Henderson if (ret) { 2150de3c9601SRichard Henderson return ret; 2151de3c9601SRichard Henderson } 2152de3c9601SRichard Henderson 2153de3c9601SRichard Henderson fpr = vfp_get_fpcr(env); 2154de3c9601SRichard Henderson ret = kvm_set_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpcr), &fpr); 2155de3c9601SRichard Henderson if (ret) { 2156de3c9601SRichard Henderson return ret; 2157de3c9601SRichard Henderson } 2158de3c9601SRichard Henderson 2159de3c9601SRichard Henderson write_cpustate_to_list(cpu, true); 2160de3c9601SRichard Henderson 2161de3c9601SRichard Henderson if (!write_list_to_kvmstate(cpu, level)) { 2162de3c9601SRichard Henderson return -EINVAL; 2163de3c9601SRichard Henderson } 2164de3c9601SRichard Henderson 2165de3c9601SRichard Henderson /* 2166de3c9601SRichard Henderson * Setting VCPU events should be triggered after syncing the registers 2167de3c9601SRichard Henderson * to avoid overwriting potential changes made by KVM upon calling 2168de3c9601SRichard Henderson * KVM_SET_VCPU_EVENTS ioctl 2169de3c9601SRichard Henderson */ 2170de3c9601SRichard Henderson ret = kvm_put_vcpu_events(cpu); 2171de3c9601SRichard Henderson if (ret) { 2172de3c9601SRichard Henderson return ret; 2173de3c9601SRichard Henderson } 2174de3c9601SRichard Henderson 217571c34911SRichard Henderson return kvm_arm_sync_mpstate_to_kvm(cpu); 2176de3c9601SRichard Henderson } 2177de3c9601SRichard Henderson 2178de3c9601SRichard Henderson static int kvm_arch_get_fpsimd(CPUState *cs) 2179de3c9601SRichard Henderson { 2180de3c9601SRichard Henderson CPUARMState *env = &ARM_CPU(cs)->env; 2181de3c9601SRichard Henderson int i, ret; 2182de3c9601SRichard Henderson 2183de3c9601SRichard Henderson for (i = 0; i < 32; i++) { 2184de3c9601SRichard Henderson uint64_t *q = aa64_vfp_qreg(env, i); 2185de3c9601SRichard Henderson ret = kvm_get_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]), q); 2186de3c9601SRichard Henderson if (ret) { 2187de3c9601SRichard Henderson return ret; 2188de3c9601SRichard Henderson } else { 2189de3c9601SRichard Henderson #if HOST_BIG_ENDIAN 2190de3c9601SRichard Henderson uint64_t t; 2191de3c9601SRichard Henderson t = q[0], q[0] = q[1], q[1] = t; 2192de3c9601SRichard Henderson #endif 2193de3c9601SRichard Henderson } 2194de3c9601SRichard Henderson } 2195de3c9601SRichard Henderson 2196de3c9601SRichard Henderson return 0; 2197de3c9601SRichard Henderson } 2198de3c9601SRichard Henderson 2199de3c9601SRichard Henderson /* 2200de3c9601SRichard Henderson * KVM SVE registers come in slices where ZREGs have a slice size of 2048 bits 2201de3c9601SRichard Henderson * and PREGS and the FFR have a slice size of 256 bits. However we simply hard 2202de3c9601SRichard Henderson * code the slice index to zero for now as it's unlikely we'll need more than 2203de3c9601SRichard Henderson * one slice for quite some time. 2204de3c9601SRichard Henderson */ 2205de3c9601SRichard Henderson static int kvm_arch_get_sve(CPUState *cs) 2206de3c9601SRichard Henderson { 2207de3c9601SRichard Henderson ARMCPU *cpu = ARM_CPU(cs); 2208de3c9601SRichard Henderson CPUARMState *env = &cpu->env; 2209de3c9601SRichard Henderson uint64_t *r; 2210de3c9601SRichard Henderson int n, ret; 2211de3c9601SRichard Henderson 2212de3c9601SRichard Henderson for (n = 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) { 2213de3c9601SRichard Henderson r = &env->vfp.zregs[n].d[0]; 2214de3c9601SRichard Henderson ret = kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_ZREG(n, 0), r); 2215de3c9601SRichard Henderson if (ret) { 2216de3c9601SRichard Henderson return ret; 2217de3c9601SRichard Henderson } 2218de3c9601SRichard Henderson sve_bswap64(r, r, cpu->sve_max_vq * 2); 2219de3c9601SRichard Henderson } 2220de3c9601SRichard Henderson 2221de3c9601SRichard Henderson for (n = 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) { 2222de3c9601SRichard Henderson r = &env->vfp.pregs[n].p[0]; 2223de3c9601SRichard Henderson ret = kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_PREG(n, 0), r); 2224de3c9601SRichard Henderson if (ret) { 2225de3c9601SRichard Henderson return ret; 2226de3c9601SRichard Henderson } 2227de3c9601SRichard Henderson sve_bswap64(r, r, DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); 2228de3c9601SRichard Henderson } 2229de3c9601SRichard Henderson 2230de3c9601SRichard Henderson r = &env->vfp.pregs[FFR_PRED_NUM].p[0]; 2231de3c9601SRichard Henderson ret = kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_FFR(0), r); 2232de3c9601SRichard Henderson if (ret) { 2233de3c9601SRichard Henderson return ret; 2234de3c9601SRichard Henderson } 2235de3c9601SRichard Henderson sve_bswap64(r, r, DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); 2236de3c9601SRichard Henderson 2237de3c9601SRichard Henderson return 0; 2238de3c9601SRichard Henderson } 2239de3c9601SRichard Henderson 2240de3c9601SRichard Henderson int kvm_arch_get_registers(CPUState *cs) 2241de3c9601SRichard Henderson { 2242de3c9601SRichard Henderson uint64_t val; 2243de3c9601SRichard Henderson unsigned int el; 2244de3c9601SRichard Henderson uint32_t fpr; 2245de3c9601SRichard Henderson int i, ret; 2246de3c9601SRichard Henderson 2247de3c9601SRichard Henderson ARMCPU *cpu = ARM_CPU(cs); 2248de3c9601SRichard Henderson CPUARMState *env = &cpu->env; 2249de3c9601SRichard Henderson 2250de3c9601SRichard Henderson for (i = 0; i < 31; i++) { 2251de3c9601SRichard Henderson ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.regs[i]), 2252de3c9601SRichard Henderson &env->xregs[i]); 2253de3c9601SRichard Henderson if (ret) { 2254de3c9601SRichard Henderson return ret; 2255de3c9601SRichard Henderson } 2256de3c9601SRichard Henderson } 2257de3c9601SRichard Henderson 2258de3c9601SRichard Henderson ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.sp), &env->sp_el[0]); 2259de3c9601SRichard Henderson if (ret) { 2260de3c9601SRichard Henderson return ret; 2261de3c9601SRichard Henderson } 2262de3c9601SRichard Henderson 2263de3c9601SRichard Henderson ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(sp_el1), &env->sp_el[1]); 2264de3c9601SRichard Henderson if (ret) { 2265de3c9601SRichard Henderson return ret; 2266de3c9601SRichard Henderson } 2267de3c9601SRichard Henderson 2268de3c9601SRichard Henderson ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.pstate), &val); 2269de3c9601SRichard Henderson if (ret) { 2270de3c9601SRichard Henderson return ret; 2271de3c9601SRichard Henderson } 2272de3c9601SRichard Henderson 2273de3c9601SRichard Henderson env->aarch64 = ((val & PSTATE_nRW) == 0); 2274de3c9601SRichard Henderson if (is_a64(env)) { 2275de3c9601SRichard Henderson pstate_write(env, val); 2276de3c9601SRichard Henderson } else { 2277de3c9601SRichard Henderson cpsr_write(env, val, 0xffffffff, CPSRWriteRaw); 2278de3c9601SRichard Henderson } 2279de3c9601SRichard Henderson 2280de3c9601SRichard Henderson /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the 2281de3c9601SRichard Henderson * QEMU side we keep the current SP in xregs[31] as well. 2282de3c9601SRichard Henderson */ 2283de3c9601SRichard Henderson aarch64_restore_sp(env, 1); 2284de3c9601SRichard Henderson 2285de3c9601SRichard Henderson ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.pc), &env->pc); 2286de3c9601SRichard Henderson if (ret) { 2287de3c9601SRichard Henderson return ret; 2288de3c9601SRichard Henderson } 2289de3c9601SRichard Henderson 2290de3c9601SRichard Henderson /* If we are in AArch32 mode then we need to sync the AArch32 regs with the 2291de3c9601SRichard Henderson * incoming AArch64 regs received from 64-bit KVM. 2292de3c9601SRichard Henderson * We must perform this after all of the registers have been acquired from 2293de3c9601SRichard Henderson * the kernel. 2294de3c9601SRichard Henderson */ 2295de3c9601SRichard Henderson if (!is_a64(env)) { 2296de3c9601SRichard Henderson aarch64_sync_64_to_32(env); 2297de3c9601SRichard Henderson } 2298de3c9601SRichard Henderson 2299de3c9601SRichard Henderson ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(elr_el1), &env->elr_el[1]); 2300de3c9601SRichard Henderson if (ret) { 2301de3c9601SRichard Henderson return ret; 2302de3c9601SRichard Henderson } 2303de3c9601SRichard Henderson 2304de3c9601SRichard Henderson /* Fetch the SPSR registers 2305de3c9601SRichard Henderson * 2306de3c9601SRichard Henderson * KVM SPSRs 0-4 map to QEMU banks 1-5 2307de3c9601SRichard Henderson */ 2308de3c9601SRichard Henderson for (i = 0; i < KVM_NR_SPSR; i++) { 2309de3c9601SRichard Henderson ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(spsr[i]), 2310de3c9601SRichard Henderson &env->banked_spsr[i + 1]); 2311de3c9601SRichard Henderson if (ret) { 2312de3c9601SRichard Henderson return ret; 2313de3c9601SRichard Henderson } 2314de3c9601SRichard Henderson } 2315de3c9601SRichard Henderson 2316de3c9601SRichard Henderson el = arm_current_el(env); 2317de3c9601SRichard Henderson if (el > 0 && !is_a64(env)) { 2318de3c9601SRichard Henderson i = bank_number(env->uncached_cpsr & CPSR_M); 2319de3c9601SRichard Henderson env->spsr = env->banked_spsr[i]; 2320de3c9601SRichard Henderson } 2321de3c9601SRichard Henderson 2322de3c9601SRichard Henderson if (cpu_isar_feature(aa64_sve, cpu)) { 2323de3c9601SRichard Henderson ret = kvm_arch_get_sve(cs); 2324de3c9601SRichard Henderson } else { 2325de3c9601SRichard Henderson ret = kvm_arch_get_fpsimd(cs); 2326de3c9601SRichard Henderson } 2327de3c9601SRichard Henderson if (ret) { 2328de3c9601SRichard Henderson return ret; 2329de3c9601SRichard Henderson } 2330de3c9601SRichard Henderson 2331de3c9601SRichard Henderson ret = kvm_get_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpsr), &fpr); 2332de3c9601SRichard Henderson if (ret) { 2333de3c9601SRichard Henderson return ret; 2334de3c9601SRichard Henderson } 2335de3c9601SRichard Henderson vfp_set_fpsr(env, fpr); 2336de3c9601SRichard Henderson 2337de3c9601SRichard Henderson ret = kvm_get_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpcr), &fpr); 2338de3c9601SRichard Henderson if (ret) { 2339de3c9601SRichard Henderson return ret; 2340de3c9601SRichard Henderson } 2341de3c9601SRichard Henderson vfp_set_fpcr(env, fpr); 2342de3c9601SRichard Henderson 2343de3c9601SRichard Henderson ret = kvm_get_vcpu_events(cpu); 2344de3c9601SRichard Henderson if (ret) { 2345de3c9601SRichard Henderson return ret; 2346de3c9601SRichard Henderson } 2347de3c9601SRichard Henderson 2348de3c9601SRichard Henderson if (!write_kvmstate_to_list(cpu)) { 2349de3c9601SRichard Henderson return -EINVAL; 2350de3c9601SRichard Henderson } 2351de3c9601SRichard Henderson /* Note that it's OK to have registers which aren't in CPUState, 2352de3c9601SRichard Henderson * so we can ignore a failure return here. 2353de3c9601SRichard Henderson */ 2354de3c9601SRichard Henderson write_list_to_cpustate(cpu); 2355de3c9601SRichard Henderson 235671c34911SRichard Henderson ret = kvm_arm_sync_mpstate_to_qemu(cpu); 2357de3c9601SRichard Henderson 2358de3c9601SRichard Henderson /* TODO: other registers */ 2359de3c9601SRichard Henderson return ret; 2360de3c9601SRichard Henderson } 2361de3c9601SRichard Henderson 2362de3c9601SRichard Henderson void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr) 2363de3c9601SRichard Henderson { 2364de3c9601SRichard Henderson ram_addr_t ram_addr; 2365de3c9601SRichard Henderson hwaddr paddr; 2366de3c9601SRichard Henderson 2367de3c9601SRichard Henderson assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO); 2368de3c9601SRichard Henderson 2369de3c9601SRichard Henderson if (acpi_ghes_present() && addr) { 2370de3c9601SRichard Henderson ram_addr = qemu_ram_addr_from_host(addr); 2371de3c9601SRichard Henderson if (ram_addr != RAM_ADDR_INVALID && 2372de3c9601SRichard Henderson kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) { 2373de3c9601SRichard Henderson kvm_hwpoison_page_add(ram_addr); 2374de3c9601SRichard Henderson /* 2375de3c9601SRichard Henderson * If this is a BUS_MCEERR_AR, we know we have been called 2376de3c9601SRichard Henderson * synchronously from the vCPU thread, so we can easily 2377de3c9601SRichard Henderson * synchronize the state and inject an error. 2378de3c9601SRichard Henderson * 2379de3c9601SRichard Henderson * TODO: we currently don't tell the guest at all about 2380de3c9601SRichard Henderson * BUS_MCEERR_AO. In that case we might either be being 2381de3c9601SRichard Henderson * called synchronously from the vCPU thread, or a bit 2382de3c9601SRichard Henderson * later from the main thread, so doing the injection of 2383de3c9601SRichard Henderson * the error would be more complicated. 2384de3c9601SRichard Henderson */ 2385de3c9601SRichard Henderson if (code == BUS_MCEERR_AR) { 2386de3c9601SRichard Henderson kvm_cpu_synchronize_state(c); 2387de3c9601SRichard Henderson if (!acpi_ghes_record_errors(ACPI_HEST_SRC_ID_SEA, paddr)) { 2388de3c9601SRichard Henderson kvm_inject_arm_sea(c); 2389de3c9601SRichard Henderson } else { 2390de3c9601SRichard Henderson error_report("failed to record the error"); 2391de3c9601SRichard Henderson abort(); 2392de3c9601SRichard Henderson } 2393de3c9601SRichard Henderson } 2394de3c9601SRichard Henderson return; 2395de3c9601SRichard Henderson } 2396de3c9601SRichard Henderson if (code == BUS_MCEERR_AO) { 2397de3c9601SRichard Henderson error_report("Hardware memory error at addr %p for memory used by " 2398de3c9601SRichard Henderson "QEMU itself instead of guest system!", addr); 2399de3c9601SRichard Henderson } 2400de3c9601SRichard Henderson } 2401de3c9601SRichard Henderson 2402de3c9601SRichard Henderson if (code == BUS_MCEERR_AR) { 2403de3c9601SRichard Henderson error_report("Hardware memory error!"); 2404de3c9601SRichard Henderson exit(1); 2405de3c9601SRichard Henderson } 2406de3c9601SRichard Henderson } 2407de3c9601SRichard Henderson 2408de3c9601SRichard Henderson /* C6.6.29 BRK instruction */ 2409de3c9601SRichard Henderson static const uint32_t brk_insn = 0xd4200000; 2410de3c9601SRichard Henderson 2411de3c9601SRichard Henderson int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 2412de3c9601SRichard Henderson { 2413de3c9601SRichard Henderson if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 0) || 2414de3c9601SRichard Henderson cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk_insn, 4, 1)) { 2415de3c9601SRichard Henderson return -EINVAL; 2416de3c9601SRichard Henderson } 2417de3c9601SRichard Henderson return 0; 2418de3c9601SRichard Henderson } 2419de3c9601SRichard Henderson 2420de3c9601SRichard Henderson int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 2421de3c9601SRichard Henderson { 2422de3c9601SRichard Henderson static uint32_t brk; 2423de3c9601SRichard Henderson 2424de3c9601SRichard Henderson if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk, 4, 0) || 2425de3c9601SRichard Henderson brk != brk_insn || 2426de3c9601SRichard Henderson cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 1)) { 2427de3c9601SRichard Henderson return -EINVAL; 2428de3c9601SRichard Henderson } 2429de3c9601SRichard Henderson return 0; 2430de3c9601SRichard Henderson } 2431