1 /* 2 * ARM implementation of KVM hooks 3 * 4 * Copyright Christoffer Dall 2009-2010 5 * Copyright Mian-M. Hamayun 2013, Virtual Open Systems 6 * Copyright Alex Bennée 2014, Linaro 7 * 8 * This work is licensed under the terms of the GNU GPL, version 2 or later. 9 * See the COPYING file in the top-level directory. 10 * 11 */ 12 13 #include "qemu/osdep.h" 14 #include <sys/ioctl.h> 15 16 #include <linux/kvm.h> 17 18 #include "qemu/timer.h" 19 #include "qemu/error-report.h" 20 #include "qemu/main-loop.h" 21 #include "qom/object.h" 22 #include "qapi/error.h" 23 #include "sysemu/sysemu.h" 24 #include "sysemu/runstate.h" 25 #include "sysemu/kvm.h" 26 #include "sysemu/kvm_int.h" 27 #include "kvm_arm.h" 28 #include "cpu.h" 29 #include "trace.h" 30 #include "internals.h" 31 #include "hw/pci/pci.h" 32 #include "exec/memattrs.h" 33 #include "exec/address-spaces.h" 34 #include "exec/gdbstub.h" 35 #include "hw/boards.h" 36 #include "hw/irq.h" 37 #include "qapi/visitor.h" 38 #include "qemu/log.h" 39 #include "hw/acpi/acpi.h" 40 #include "hw/acpi/ghes.h" 41 42 const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 43 KVM_CAP_LAST_INFO 44 }; 45 46 static bool cap_has_mp_state; 47 static bool cap_has_inject_serror_esr; 48 static bool cap_has_inject_ext_dabt; 49 50 /** 51 * ARMHostCPUFeatures: information about the host CPU (identified 52 * by asking the host kernel) 53 */ 54 typedef struct ARMHostCPUFeatures { 55 ARMISARegisters isar; 56 uint64_t features; 57 uint32_t target; 58 const char *dtb_compatible; 59 } ARMHostCPUFeatures; 60 61 static ARMHostCPUFeatures arm_host_cpu_features; 62 63 /** 64 * kvm_arm_vcpu_init: 65 * @cpu: ARMCPU 66 * 67 * Initialize (or reinitialize) the VCPU by invoking the 68 * KVM_ARM_VCPU_INIT ioctl with the CPU type and feature 69 * bitmask specified in the CPUState. 70 * 71 * Returns: 0 if success else < 0 error code 72 */ 73 static int kvm_arm_vcpu_init(ARMCPU *cpu) 74 { 75 struct kvm_vcpu_init init; 76 77 init.target = cpu->kvm_target; 78 memcpy(init.features, cpu->kvm_init_features, sizeof(init.features)); 79 80 return kvm_vcpu_ioctl(CPU(cpu), KVM_ARM_VCPU_INIT, &init); 81 } 82 83 /** 84 * kvm_arm_vcpu_finalize: 85 * @cpu: ARMCPU 86 * @feature: feature to finalize 87 * 88 * Finalizes the configuration of the specified VCPU feature by 89 * invoking the KVM_ARM_VCPU_FINALIZE ioctl. Features requiring 90 * this are documented in the "KVM_ARM_VCPU_FINALIZE" section of 91 * KVM's API documentation. 92 * 93 * Returns: 0 if success else < 0 error code 94 */ 95 static int kvm_arm_vcpu_finalize(ARMCPU *cpu, int feature) 96 { 97 return kvm_vcpu_ioctl(CPU(cpu), KVM_ARM_VCPU_FINALIZE, &feature); 98 } 99 100 bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try, 101 int *fdarray, 102 struct kvm_vcpu_init *init) 103 { 104 int ret = 0, kvmfd = -1, vmfd = -1, cpufd = -1; 105 int max_vm_pa_size; 106 107 kvmfd = qemu_open_old("/dev/kvm", O_RDWR); 108 if (kvmfd < 0) { 109 goto err; 110 } 111 max_vm_pa_size = ioctl(kvmfd, KVM_CHECK_EXTENSION, KVM_CAP_ARM_VM_IPA_SIZE); 112 if (max_vm_pa_size < 0) { 113 max_vm_pa_size = 0; 114 } 115 do { 116 vmfd = ioctl(kvmfd, KVM_CREATE_VM, max_vm_pa_size); 117 } while (vmfd == -1 && errno == EINTR); 118 if (vmfd < 0) { 119 goto err; 120 } 121 cpufd = ioctl(vmfd, KVM_CREATE_VCPU, 0); 122 if (cpufd < 0) { 123 goto err; 124 } 125 126 if (!init) { 127 /* Caller doesn't want the VCPU to be initialized, so skip it */ 128 goto finish; 129 } 130 131 if (init->target == -1) { 132 struct kvm_vcpu_init preferred; 133 134 ret = ioctl(vmfd, KVM_ARM_PREFERRED_TARGET, &preferred); 135 if (!ret) { 136 init->target = preferred.target; 137 } 138 } 139 if (ret >= 0) { 140 ret = ioctl(cpufd, KVM_ARM_VCPU_INIT, init); 141 if (ret < 0) { 142 goto err; 143 } 144 } else if (cpus_to_try) { 145 /* Old kernel which doesn't know about the 146 * PREFERRED_TARGET ioctl: we know it will only support 147 * creating one kind of guest CPU which is its preferred 148 * CPU type. 149 */ 150 struct kvm_vcpu_init try; 151 152 while (*cpus_to_try != QEMU_KVM_ARM_TARGET_NONE) { 153 try.target = *cpus_to_try++; 154 memcpy(try.features, init->features, sizeof(init->features)); 155 ret = ioctl(cpufd, KVM_ARM_VCPU_INIT, &try); 156 if (ret >= 0) { 157 break; 158 } 159 } 160 if (ret < 0) { 161 goto err; 162 } 163 init->target = try.target; 164 } else { 165 /* Treat a NULL cpus_to_try argument the same as an empty 166 * list, which means we will fail the call since this must 167 * be an old kernel which doesn't support PREFERRED_TARGET. 168 */ 169 goto err; 170 } 171 172 finish: 173 fdarray[0] = kvmfd; 174 fdarray[1] = vmfd; 175 fdarray[2] = cpufd; 176 177 return true; 178 179 err: 180 if (cpufd >= 0) { 181 close(cpufd); 182 } 183 if (vmfd >= 0) { 184 close(vmfd); 185 } 186 if (kvmfd >= 0) { 187 close(kvmfd); 188 } 189 190 return false; 191 } 192 193 void kvm_arm_destroy_scratch_host_vcpu(int *fdarray) 194 { 195 int i; 196 197 for (i = 2; i >= 0; i--) { 198 close(fdarray[i]); 199 } 200 } 201 202 static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id) 203 { 204 uint64_t ret; 205 struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)&ret }; 206 int err; 207 208 assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64); 209 err = ioctl(fd, KVM_GET_ONE_REG, &idreg); 210 if (err < 0) { 211 return -1; 212 } 213 *pret = ret; 214 return 0; 215 } 216 217 static int read_sys_reg64(int fd, uint64_t *pret, uint64_t id) 218 { 219 struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)pret }; 220 221 assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64); 222 return ioctl(fd, KVM_GET_ONE_REG, &idreg); 223 } 224 225 static bool kvm_arm_pauth_supported(void) 226 { 227 return (kvm_check_extension(kvm_state, KVM_CAP_ARM_PTRAUTH_ADDRESS) && 228 kvm_check_extension(kvm_state, KVM_CAP_ARM_PTRAUTH_GENERIC)); 229 } 230 231 static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) 232 { 233 /* Identify the feature bits corresponding to the host CPU, and 234 * fill out the ARMHostCPUClass fields accordingly. To do this 235 * we have to create a scratch VM, create a single CPU inside it, 236 * and then query that CPU for the relevant ID registers. 237 */ 238 int fdarray[3]; 239 bool sve_supported; 240 bool pmu_supported = false; 241 uint64_t features = 0; 242 int err; 243 244 /* Old kernels may not know about the PREFERRED_TARGET ioctl: however 245 * we know these will only support creating one kind of guest CPU, 246 * which is its preferred CPU type. Fortunately these old kernels 247 * support only a very limited number of CPUs. 248 */ 249 static const uint32_t cpus_to_try[] = { 250 KVM_ARM_TARGET_AEM_V8, 251 KVM_ARM_TARGET_FOUNDATION_V8, 252 KVM_ARM_TARGET_CORTEX_A57, 253 QEMU_KVM_ARM_TARGET_NONE 254 }; 255 /* 256 * target = -1 informs kvm_arm_create_scratch_host_vcpu() 257 * to use the preferred target 258 */ 259 struct kvm_vcpu_init init = { .target = -1, }; 260 261 /* 262 * Ask for SVE if supported, so that we can query ID_AA64ZFR0, 263 * which is otherwise RAZ. 264 */ 265 sve_supported = kvm_arm_sve_supported(); 266 if (sve_supported) { 267 init.features[0] |= 1 << KVM_ARM_VCPU_SVE; 268 } 269 270 /* 271 * Ask for Pointer Authentication if supported, so that we get 272 * the unsanitized field values for AA64ISAR1_EL1. 273 */ 274 if (kvm_arm_pauth_supported()) { 275 init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | 276 1 << KVM_ARM_VCPU_PTRAUTH_GENERIC); 277 } 278 279 if (kvm_arm_pmu_supported()) { 280 init.features[0] |= 1 << KVM_ARM_VCPU_PMU_V3; 281 pmu_supported = true; 282 } 283 284 if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) { 285 return false; 286 } 287 288 ahcf->target = init.target; 289 ahcf->dtb_compatible = "arm,arm-v8"; 290 291 err = read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr0, 292 ARM64_SYS_REG(3, 0, 0, 4, 0)); 293 if (unlikely(err < 0)) { 294 /* 295 * Before v4.15, the kernel only exposed a limited number of system 296 * registers, not including any of the interesting AArch64 ID regs. 297 * For the most part we could leave these fields as zero with minimal 298 * effect, since this does not affect the values seen by the guest. 299 * 300 * However, it could cause problems down the line for QEMU, 301 * so provide a minimal v8.0 default. 302 * 303 * ??? Could read MIDR and use knowledge from cpu64.c. 304 * ??? Could map a page of memory into our temp guest and 305 * run the tiniest of hand-crafted kernels to extract 306 * the values seen by the guest. 307 * ??? Either of these sounds like too much effort just 308 * to work around running a modern host kernel. 309 */ 310 ahcf->isar.id_aa64pfr0 = 0x00000011; /* EL1&0, AArch64 only */ 311 err = 0; 312 } else { 313 err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr1, 314 ARM64_SYS_REG(3, 0, 0, 4, 1)); 315 err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64smfr0, 316 ARM64_SYS_REG(3, 0, 0, 4, 5)); 317 err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr0, 318 ARM64_SYS_REG(3, 0, 0, 5, 0)); 319 err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr1, 320 ARM64_SYS_REG(3, 0, 0, 5, 1)); 321 err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar0, 322 ARM64_SYS_REG(3, 0, 0, 6, 0)); 323 err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1, 324 ARM64_SYS_REG(3, 0, 0, 6, 1)); 325 err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar2, 326 ARM64_SYS_REG(3, 0, 0, 6, 2)); 327 err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr0, 328 ARM64_SYS_REG(3, 0, 0, 7, 0)); 329 err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1, 330 ARM64_SYS_REG(3, 0, 0, 7, 1)); 331 err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2, 332 ARM64_SYS_REG(3, 0, 0, 7, 2)); 333 334 /* 335 * Note that if AArch32 support is not present in the host, 336 * the AArch32 sysregs are present to be read, but will 337 * return UNKNOWN values. This is neither better nor worse 338 * than skipping the reads and leaving 0, as we must avoid 339 * considering the values in every case. 340 */ 341 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr0, 342 ARM64_SYS_REG(3, 0, 0, 1, 0)); 343 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr1, 344 ARM64_SYS_REG(3, 0, 0, 1, 1)); 345 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0, 346 ARM64_SYS_REG(3, 0, 0, 1, 2)); 347 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0, 348 ARM64_SYS_REG(3, 0, 0, 1, 4)); 349 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr1, 350 ARM64_SYS_REG(3, 0, 0, 1, 5)); 351 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr2, 352 ARM64_SYS_REG(3, 0, 0, 1, 6)); 353 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr3, 354 ARM64_SYS_REG(3, 0, 0, 1, 7)); 355 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0, 356 ARM64_SYS_REG(3, 0, 0, 2, 0)); 357 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1, 358 ARM64_SYS_REG(3, 0, 0, 2, 1)); 359 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2, 360 ARM64_SYS_REG(3, 0, 0, 2, 2)); 361 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3, 362 ARM64_SYS_REG(3, 0, 0, 2, 3)); 363 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4, 364 ARM64_SYS_REG(3, 0, 0, 2, 4)); 365 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5, 366 ARM64_SYS_REG(3, 0, 0, 2, 5)); 367 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr4, 368 ARM64_SYS_REG(3, 0, 0, 2, 6)); 369 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6, 370 ARM64_SYS_REG(3, 0, 0, 2, 7)); 371 372 err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0, 373 ARM64_SYS_REG(3, 0, 0, 3, 0)); 374 err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1, 375 ARM64_SYS_REG(3, 0, 0, 3, 1)); 376 err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2, 377 ARM64_SYS_REG(3, 0, 0, 3, 2)); 378 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr2, 379 ARM64_SYS_REG(3, 0, 0, 3, 4)); 380 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr1, 381 ARM64_SYS_REG(3, 0, 0, 3, 5)); 382 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr5, 383 ARM64_SYS_REG(3, 0, 0, 3, 6)); 384 385 /* 386 * DBGDIDR is a bit complicated because the kernel doesn't 387 * provide an accessor for it in 64-bit mode, which is what this 388 * scratch VM is in, and there's no architected "64-bit sysreg 389 * which reads the same as the 32-bit register" the way there is 390 * for other ID registers. Instead we synthesize a value from the 391 * AArch64 ID_AA64DFR0, the same way the kernel code in 392 * arch/arm64/kvm/sys_regs.c:trap_dbgidr() does. 393 * We only do this if the CPU supports AArch32 at EL1. 394 */ 395 if (FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL1) >= 2) { 396 int wrps = FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, WRPS); 397 int brps = FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, BRPS); 398 int ctx_cmps = 399 FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS); 400 int version = 6; /* ARMv8 debug architecture */ 401 bool has_el3 = 402 !!FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL3); 403 uint32_t dbgdidr = 0; 404 405 dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, WRPS, wrps); 406 dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, BRPS, brps); 407 dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, CTX_CMPS, ctx_cmps); 408 dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, VERSION, version); 409 dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, NSUHD_IMP, has_el3); 410 dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, SE_IMP, has_el3); 411 dbgdidr |= (1 << 15); /* RES1 bit */ 412 ahcf->isar.dbgdidr = dbgdidr; 413 } 414 415 if (pmu_supported) { 416 /* PMCR_EL0 is only accessible if the vCPU has feature PMU_V3 */ 417 err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0, 418 ARM64_SYS_REG(3, 3, 9, 12, 0)); 419 } 420 421 if (sve_supported) { 422 /* 423 * There is a range of kernels between kernel commit 73433762fcae 424 * and f81cb2c3ad41 which have a bug where the kernel doesn't 425 * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has 426 * enabled SVE support, which resulted in an error rather than RAZ. 427 * So only read the register if we set KVM_ARM_VCPU_SVE above. 428 */ 429 err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, 430 ARM64_SYS_REG(3, 0, 0, 4, 4)); 431 } 432 } 433 434 kvm_arm_destroy_scratch_host_vcpu(fdarray); 435 436 if (err < 0) { 437 return false; 438 } 439 440 /* 441 * We can assume any KVM supporting CPU is at least a v8 442 * with VFPv4+Neon; this in turn implies most of the other 443 * feature bits. 444 */ 445 features |= 1ULL << ARM_FEATURE_V8; 446 features |= 1ULL << ARM_FEATURE_NEON; 447 features |= 1ULL << ARM_FEATURE_AARCH64; 448 features |= 1ULL << ARM_FEATURE_PMU; 449 features |= 1ULL << ARM_FEATURE_GENERIC_TIMER; 450 451 ahcf->features = features; 452 453 return true; 454 } 455 456 void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) 457 { 458 CPUARMState *env = &cpu->env; 459 460 if (!arm_host_cpu_features.dtb_compatible) { 461 if (!kvm_enabled() || 462 !kvm_arm_get_host_cpu_features(&arm_host_cpu_features)) { 463 /* We can't report this error yet, so flag that we need to 464 * in arm_cpu_realizefn(). 465 */ 466 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 467 cpu->host_cpu_probe_failed = true; 468 return; 469 } 470 } 471 472 cpu->kvm_target = arm_host_cpu_features.target; 473 cpu->dtb_compatible = arm_host_cpu_features.dtb_compatible; 474 cpu->isar = arm_host_cpu_features.isar; 475 env->features = arm_host_cpu_features.features; 476 } 477 478 static bool kvm_no_adjvtime_get(Object *obj, Error **errp) 479 { 480 return !ARM_CPU(obj)->kvm_adjvtime; 481 } 482 483 static void kvm_no_adjvtime_set(Object *obj, bool value, Error **errp) 484 { 485 ARM_CPU(obj)->kvm_adjvtime = !value; 486 } 487 488 static bool kvm_steal_time_get(Object *obj, Error **errp) 489 { 490 return ARM_CPU(obj)->kvm_steal_time != ON_OFF_AUTO_OFF; 491 } 492 493 static void kvm_steal_time_set(Object *obj, bool value, Error **errp) 494 { 495 ARM_CPU(obj)->kvm_steal_time = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; 496 } 497 498 /* KVM VCPU properties should be prefixed with "kvm-". */ 499 void kvm_arm_add_vcpu_properties(ARMCPU *cpu) 500 { 501 CPUARMState *env = &cpu->env; 502 Object *obj = OBJECT(cpu); 503 504 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { 505 cpu->kvm_adjvtime = true; 506 object_property_add_bool(obj, "kvm-no-adjvtime", kvm_no_adjvtime_get, 507 kvm_no_adjvtime_set); 508 object_property_set_description(obj, "kvm-no-adjvtime", 509 "Set on to disable the adjustment of " 510 "the virtual counter. VM stopped time " 511 "will be counted."); 512 } 513 514 cpu->kvm_steal_time = ON_OFF_AUTO_AUTO; 515 object_property_add_bool(obj, "kvm-steal-time", kvm_steal_time_get, 516 kvm_steal_time_set); 517 object_property_set_description(obj, "kvm-steal-time", 518 "Set off to disable KVM steal time."); 519 } 520 521 bool kvm_arm_pmu_supported(void) 522 { 523 return kvm_check_extension(kvm_state, KVM_CAP_ARM_PMU_V3); 524 } 525 526 int kvm_arm_get_max_vm_ipa_size(MachineState *ms, bool *fixed_ipa) 527 { 528 KVMState *s = KVM_STATE(ms->accelerator); 529 int ret; 530 531 ret = kvm_check_extension(s, KVM_CAP_ARM_VM_IPA_SIZE); 532 *fixed_ipa = ret <= 0; 533 534 return ret > 0 ? ret : 40; 535 } 536 537 int kvm_arch_get_default_type(MachineState *ms) 538 { 539 bool fixed_ipa; 540 int size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa); 541 return fixed_ipa ? 0 : size; 542 } 543 544 int kvm_arch_init(MachineState *ms, KVMState *s) 545 { 546 int ret = 0; 547 /* For ARM interrupt delivery is always asynchronous, 548 * whether we are using an in-kernel VGIC or not. 549 */ 550 kvm_async_interrupts_allowed = true; 551 552 /* 553 * PSCI wakes up secondary cores, so we always need to 554 * have vCPUs waiting in kernel space 555 */ 556 kvm_halt_in_kernel_allowed = true; 557 558 cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE); 559 560 /* Check whether user space can specify guest syndrome value */ 561 cap_has_inject_serror_esr = 562 kvm_check_extension(s, KVM_CAP_ARM_INJECT_SERROR_ESR); 563 564 if (ms->smp.cpus > 256 && 565 !kvm_check_extension(s, KVM_CAP_ARM_IRQ_LINE_LAYOUT_2)) { 566 error_report("Using more than 256 vcpus requires a host kernel " 567 "with KVM_CAP_ARM_IRQ_LINE_LAYOUT_2"); 568 ret = -EINVAL; 569 } 570 571 if (kvm_check_extension(s, KVM_CAP_ARM_NISV_TO_USER)) { 572 if (kvm_vm_enable_cap(s, KVM_CAP_ARM_NISV_TO_USER, 0)) { 573 error_report("Failed to enable KVM_CAP_ARM_NISV_TO_USER cap"); 574 } else { 575 /* Set status for supporting the external dabt injection */ 576 cap_has_inject_ext_dabt = kvm_check_extension(s, 577 KVM_CAP_ARM_INJECT_EXT_DABT); 578 } 579 } 580 581 if (s->kvm_eager_split_size) { 582 uint32_t sizes; 583 584 sizes = kvm_vm_check_extension(s, KVM_CAP_ARM_SUPPORTED_BLOCK_SIZES); 585 if (!sizes) { 586 s->kvm_eager_split_size = 0; 587 warn_report("Eager Page Split support not available"); 588 } else if (!(s->kvm_eager_split_size & sizes)) { 589 error_report("Eager Page Split requested chunk size not valid"); 590 ret = -EINVAL; 591 } else { 592 ret = kvm_vm_enable_cap(s, KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE, 0, 593 s->kvm_eager_split_size); 594 if (ret < 0) { 595 error_report("Enabling of Eager Page Split failed: %s", 596 strerror(-ret)); 597 } 598 } 599 } 600 601 max_hw_wps = kvm_check_extension(s, KVM_CAP_GUEST_DEBUG_HW_WPS); 602 hw_watchpoints = g_array_sized_new(true, true, 603 sizeof(HWWatchpoint), max_hw_wps); 604 605 max_hw_bps = kvm_check_extension(s, KVM_CAP_GUEST_DEBUG_HW_BPS); 606 hw_breakpoints = g_array_sized_new(true, true, 607 sizeof(HWBreakpoint), max_hw_bps); 608 609 return ret; 610 } 611 612 unsigned long kvm_arch_vcpu_id(CPUState *cpu) 613 { 614 return cpu->cpu_index; 615 } 616 617 /* We track all the KVM devices which need their memory addresses 618 * passing to the kernel in a list of these structures. 619 * When board init is complete we run through the list and 620 * tell the kernel the base addresses of the memory regions. 621 * We use a MemoryListener to track mapping and unmapping of 622 * the regions during board creation, so the board models don't 623 * need to do anything special for the KVM case. 624 * 625 * Sometimes the address must be OR'ed with some other fields 626 * (for example for KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION). 627 * @kda_addr_ormask aims at storing the value of those fields. 628 */ 629 typedef struct KVMDevice { 630 struct kvm_arm_device_addr kda; 631 struct kvm_device_attr kdattr; 632 uint64_t kda_addr_ormask; 633 MemoryRegion *mr; 634 QSLIST_ENTRY(KVMDevice) entries; 635 int dev_fd; 636 } KVMDevice; 637 638 static QSLIST_HEAD(, KVMDevice) kvm_devices_head; 639 640 static void kvm_arm_devlistener_add(MemoryListener *listener, 641 MemoryRegionSection *section) 642 { 643 KVMDevice *kd; 644 645 QSLIST_FOREACH(kd, &kvm_devices_head, entries) { 646 if (section->mr == kd->mr) { 647 kd->kda.addr = section->offset_within_address_space; 648 } 649 } 650 } 651 652 static void kvm_arm_devlistener_del(MemoryListener *listener, 653 MemoryRegionSection *section) 654 { 655 KVMDevice *kd; 656 657 QSLIST_FOREACH(kd, &kvm_devices_head, entries) { 658 if (section->mr == kd->mr) { 659 kd->kda.addr = -1; 660 } 661 } 662 } 663 664 static MemoryListener devlistener = { 665 .name = "kvm-arm", 666 .region_add = kvm_arm_devlistener_add, 667 .region_del = kvm_arm_devlistener_del, 668 .priority = MEMORY_LISTENER_PRIORITY_MIN, 669 }; 670 671 static void kvm_arm_set_device_addr(KVMDevice *kd) 672 { 673 struct kvm_device_attr *attr = &kd->kdattr; 674 int ret; 675 676 /* If the device control API is available and we have a device fd on the 677 * KVMDevice struct, let's use the newer API 678 */ 679 if (kd->dev_fd >= 0) { 680 uint64_t addr = kd->kda.addr; 681 682 addr |= kd->kda_addr_ormask; 683 attr->addr = (uintptr_t)&addr; 684 ret = kvm_device_ioctl(kd->dev_fd, KVM_SET_DEVICE_ATTR, attr); 685 } else { 686 ret = kvm_vm_ioctl(kvm_state, KVM_ARM_SET_DEVICE_ADDR, &kd->kda); 687 } 688 689 if (ret < 0) { 690 fprintf(stderr, "Failed to set device address: %s\n", 691 strerror(-ret)); 692 abort(); 693 } 694 } 695 696 static void kvm_arm_machine_init_done(Notifier *notifier, void *data) 697 { 698 KVMDevice *kd, *tkd; 699 700 QSLIST_FOREACH_SAFE(kd, &kvm_devices_head, entries, tkd) { 701 if (kd->kda.addr != -1) { 702 kvm_arm_set_device_addr(kd); 703 } 704 memory_region_unref(kd->mr); 705 QSLIST_REMOVE_HEAD(&kvm_devices_head, entries); 706 g_free(kd); 707 } 708 memory_listener_unregister(&devlistener); 709 } 710 711 static Notifier notify = { 712 .notify = kvm_arm_machine_init_done, 713 }; 714 715 void kvm_arm_register_device(MemoryRegion *mr, uint64_t devid, uint64_t group, 716 uint64_t attr, int dev_fd, uint64_t addr_ormask) 717 { 718 KVMDevice *kd; 719 720 if (!kvm_irqchip_in_kernel()) { 721 return; 722 } 723 724 if (QSLIST_EMPTY(&kvm_devices_head)) { 725 memory_listener_register(&devlistener, &address_space_memory); 726 qemu_add_machine_init_done_notifier(¬ify); 727 } 728 kd = g_new0(KVMDevice, 1); 729 kd->mr = mr; 730 kd->kda.id = devid; 731 kd->kda.addr = -1; 732 kd->kdattr.flags = 0; 733 kd->kdattr.group = group; 734 kd->kdattr.attr = attr; 735 kd->dev_fd = dev_fd; 736 kd->kda_addr_ormask = addr_ormask; 737 QSLIST_INSERT_HEAD(&kvm_devices_head, kd, entries); 738 memory_region_ref(kd->mr); 739 } 740 741 static int compare_u64(const void *a, const void *b) 742 { 743 if (*(uint64_t *)a > *(uint64_t *)b) { 744 return 1; 745 } 746 if (*(uint64_t *)a < *(uint64_t *)b) { 747 return -1; 748 } 749 return 0; 750 } 751 752 /* 753 * cpreg_values are sorted in ascending order by KVM register ID 754 * (see kvm_arm_init_cpreg_list). This allows us to cheaply find 755 * the storage for a KVM register by ID with a binary search. 756 */ 757 static uint64_t *kvm_arm_get_cpreg_ptr(ARMCPU *cpu, uint64_t regidx) 758 { 759 uint64_t *res; 760 761 res = bsearch(®idx, cpu->cpreg_indexes, cpu->cpreg_array_len, 762 sizeof(uint64_t), compare_u64); 763 assert(res); 764 765 return &cpu->cpreg_values[res - cpu->cpreg_indexes]; 766 } 767 768 /** 769 * kvm_arm_reg_syncs_via_cpreg_list: 770 * @regidx: KVM register index 771 * 772 * Return true if this KVM register should be synchronized via the 773 * cpreg list of arbitrary system registers, false if it is synchronized 774 * by hand using code in kvm_arch_get/put_registers(). 775 */ 776 static bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx) 777 { 778 switch (regidx & KVM_REG_ARM_COPROC_MASK) { 779 case KVM_REG_ARM_CORE: 780 case KVM_REG_ARM64_SVE: 781 return false; 782 default: 783 return true; 784 } 785 } 786 787 /** 788 * kvm_arm_init_cpreg_list: 789 * @cpu: ARMCPU 790 * 791 * Initialize the ARMCPU cpreg list according to the kernel's 792 * definition of what CPU registers it knows about (and throw away 793 * the previous TCG-created cpreg list). 794 * 795 * Returns: 0 if success, else < 0 error code 796 */ 797 static int kvm_arm_init_cpreg_list(ARMCPU *cpu) 798 { 799 struct kvm_reg_list rl; 800 struct kvm_reg_list *rlp; 801 int i, ret, arraylen; 802 CPUState *cs = CPU(cpu); 803 804 rl.n = 0; 805 ret = kvm_vcpu_ioctl(cs, KVM_GET_REG_LIST, &rl); 806 if (ret != -E2BIG) { 807 return ret; 808 } 809 rlp = g_malloc(sizeof(struct kvm_reg_list) + rl.n * sizeof(uint64_t)); 810 rlp->n = rl.n; 811 ret = kvm_vcpu_ioctl(cs, KVM_GET_REG_LIST, rlp); 812 if (ret) { 813 goto out; 814 } 815 /* Sort the list we get back from the kernel, since cpreg_tuples 816 * must be in strictly ascending order. 817 */ 818 qsort(&rlp->reg, rlp->n, sizeof(rlp->reg[0]), compare_u64); 819 820 for (i = 0, arraylen = 0; i < rlp->n; i++) { 821 if (!kvm_arm_reg_syncs_via_cpreg_list(rlp->reg[i])) { 822 continue; 823 } 824 switch (rlp->reg[i] & KVM_REG_SIZE_MASK) { 825 case KVM_REG_SIZE_U32: 826 case KVM_REG_SIZE_U64: 827 break; 828 default: 829 fprintf(stderr, "Can't handle size of register in kernel list\n"); 830 ret = -EINVAL; 831 goto out; 832 } 833 834 arraylen++; 835 } 836 837 cpu->cpreg_indexes = g_renew(uint64_t, cpu->cpreg_indexes, arraylen); 838 cpu->cpreg_values = g_renew(uint64_t, cpu->cpreg_values, arraylen); 839 cpu->cpreg_vmstate_indexes = g_renew(uint64_t, cpu->cpreg_vmstate_indexes, 840 arraylen); 841 cpu->cpreg_vmstate_values = g_renew(uint64_t, cpu->cpreg_vmstate_values, 842 arraylen); 843 cpu->cpreg_array_len = arraylen; 844 cpu->cpreg_vmstate_array_len = arraylen; 845 846 for (i = 0, arraylen = 0; i < rlp->n; i++) { 847 uint64_t regidx = rlp->reg[i]; 848 if (!kvm_arm_reg_syncs_via_cpreg_list(regidx)) { 849 continue; 850 } 851 cpu->cpreg_indexes[arraylen] = regidx; 852 arraylen++; 853 } 854 assert(cpu->cpreg_array_len == arraylen); 855 856 if (!write_kvmstate_to_list(cpu)) { 857 /* Shouldn't happen unless kernel is inconsistent about 858 * what registers exist. 859 */ 860 fprintf(stderr, "Initial read of kernel register state failed\n"); 861 ret = -EINVAL; 862 goto out; 863 } 864 865 out: 866 g_free(rlp); 867 return ret; 868 } 869 870 /** 871 * kvm_arm_cpreg_level: 872 * @regidx: KVM register index 873 * 874 * Return the level of this coprocessor/system register. Return value is 875 * either KVM_PUT_RUNTIME_STATE, KVM_PUT_RESET_STATE, or KVM_PUT_FULL_STATE. 876 */ 877 static int kvm_arm_cpreg_level(uint64_t regidx) 878 { 879 /* 880 * All system registers are assumed to be level KVM_PUT_RUNTIME_STATE. 881 * If a register should be written less often, you must add it here 882 * with a state of either KVM_PUT_RESET_STATE or KVM_PUT_FULL_STATE. 883 */ 884 switch (regidx) { 885 case KVM_REG_ARM_TIMER_CNT: 886 case KVM_REG_ARM_PTIMER_CNT: 887 return KVM_PUT_FULL_STATE; 888 } 889 return KVM_PUT_RUNTIME_STATE; 890 } 891 892 bool write_kvmstate_to_list(ARMCPU *cpu) 893 { 894 CPUState *cs = CPU(cpu); 895 int i; 896 bool ok = true; 897 898 for (i = 0; i < cpu->cpreg_array_len; i++) { 899 uint64_t regidx = cpu->cpreg_indexes[i]; 900 uint32_t v32; 901 int ret; 902 903 switch (regidx & KVM_REG_SIZE_MASK) { 904 case KVM_REG_SIZE_U32: 905 ret = kvm_get_one_reg(cs, regidx, &v32); 906 if (!ret) { 907 cpu->cpreg_values[i] = v32; 908 } 909 break; 910 case KVM_REG_SIZE_U64: 911 ret = kvm_get_one_reg(cs, regidx, cpu->cpreg_values + i); 912 break; 913 default: 914 g_assert_not_reached(); 915 } 916 if (ret) { 917 ok = false; 918 } 919 } 920 return ok; 921 } 922 923 bool write_list_to_kvmstate(ARMCPU *cpu, int level) 924 { 925 CPUState *cs = CPU(cpu); 926 int i; 927 bool ok = true; 928 929 for (i = 0; i < cpu->cpreg_array_len; i++) { 930 uint64_t regidx = cpu->cpreg_indexes[i]; 931 uint32_t v32; 932 int ret; 933 934 if (kvm_arm_cpreg_level(regidx) > level) { 935 continue; 936 } 937 938 switch (regidx & KVM_REG_SIZE_MASK) { 939 case KVM_REG_SIZE_U32: 940 v32 = cpu->cpreg_values[i]; 941 ret = kvm_set_one_reg(cs, regidx, &v32); 942 break; 943 case KVM_REG_SIZE_U64: 944 ret = kvm_set_one_reg(cs, regidx, cpu->cpreg_values + i); 945 break; 946 default: 947 g_assert_not_reached(); 948 } 949 if (ret) { 950 /* We might fail for "unknown register" and also for 951 * "you tried to set a register which is constant with 952 * a different value from what it actually contains". 953 */ 954 ok = false; 955 } 956 } 957 return ok; 958 } 959 960 void kvm_arm_cpu_pre_save(ARMCPU *cpu) 961 { 962 /* KVM virtual time adjustment */ 963 if (cpu->kvm_vtime_dirty) { 964 *kvm_arm_get_cpreg_ptr(cpu, KVM_REG_ARM_TIMER_CNT) = cpu->kvm_vtime; 965 } 966 } 967 968 void kvm_arm_cpu_post_load(ARMCPU *cpu) 969 { 970 /* KVM virtual time adjustment */ 971 if (cpu->kvm_adjvtime) { 972 cpu->kvm_vtime = *kvm_arm_get_cpreg_ptr(cpu, KVM_REG_ARM_TIMER_CNT); 973 cpu->kvm_vtime_dirty = true; 974 } 975 } 976 977 void kvm_arm_reset_vcpu(ARMCPU *cpu) 978 { 979 int ret; 980 981 /* Re-init VCPU so that all registers are set to 982 * their respective reset values. 983 */ 984 ret = kvm_arm_vcpu_init(cpu); 985 if (ret < 0) { 986 fprintf(stderr, "kvm_arm_vcpu_init failed: %s\n", strerror(-ret)); 987 abort(); 988 } 989 if (!write_kvmstate_to_list(cpu)) { 990 fprintf(stderr, "write_kvmstate_to_list failed\n"); 991 abort(); 992 } 993 /* 994 * Sync the reset values also into the CPUState. This is necessary 995 * because the next thing we do will be a kvm_arch_put_registers() 996 * which will update the list values from the CPUState before copying 997 * the list values back to KVM. It's OK to ignore failure returns here 998 * for the same reason we do so in kvm_arch_get_registers(). 999 */ 1000 write_list_to_cpustate(cpu); 1001 } 1002 1003 /* 1004 * Update KVM's MP_STATE based on what QEMU thinks it is 1005 */ 1006 static int kvm_arm_sync_mpstate_to_kvm(ARMCPU *cpu) 1007 { 1008 if (cap_has_mp_state) { 1009 struct kvm_mp_state mp_state = { 1010 .mp_state = (cpu->power_state == PSCI_OFF) ? 1011 KVM_MP_STATE_STOPPED : KVM_MP_STATE_RUNNABLE 1012 }; 1013 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state); 1014 } 1015 return 0; 1016 } 1017 1018 /* 1019 * Sync the KVM MP_STATE into QEMU 1020 */ 1021 static int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu) 1022 { 1023 if (cap_has_mp_state) { 1024 struct kvm_mp_state mp_state; 1025 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MP_STATE, &mp_state); 1026 if (ret) { 1027 return ret; 1028 } 1029 cpu->power_state = (mp_state.mp_state == KVM_MP_STATE_STOPPED) ? 1030 PSCI_OFF : PSCI_ON; 1031 } 1032 return 0; 1033 } 1034 1035 /** 1036 * kvm_arm_get_virtual_time: 1037 * @cs: CPUState 1038 * 1039 * Gets the VCPU's virtual counter and stores it in the KVM CPU state. 1040 */ 1041 static void kvm_arm_get_virtual_time(CPUState *cs) 1042 { 1043 ARMCPU *cpu = ARM_CPU(cs); 1044 int ret; 1045 1046 if (cpu->kvm_vtime_dirty) { 1047 return; 1048 } 1049 1050 ret = kvm_get_one_reg(cs, KVM_REG_ARM_TIMER_CNT, &cpu->kvm_vtime); 1051 if (ret) { 1052 error_report("Failed to get KVM_REG_ARM_TIMER_CNT"); 1053 abort(); 1054 } 1055 1056 cpu->kvm_vtime_dirty = true; 1057 } 1058 1059 /** 1060 * kvm_arm_put_virtual_time: 1061 * @cs: CPUState 1062 * 1063 * Sets the VCPU's virtual counter to the value stored in the KVM CPU state. 1064 */ 1065 static void kvm_arm_put_virtual_time(CPUState *cs) 1066 { 1067 ARMCPU *cpu = ARM_CPU(cs); 1068 int ret; 1069 1070 if (!cpu->kvm_vtime_dirty) { 1071 return; 1072 } 1073 1074 ret = kvm_set_one_reg(cs, KVM_REG_ARM_TIMER_CNT, &cpu->kvm_vtime); 1075 if (ret) { 1076 error_report("Failed to set KVM_REG_ARM_TIMER_CNT"); 1077 abort(); 1078 } 1079 1080 cpu->kvm_vtime_dirty = false; 1081 } 1082 1083 /** 1084 * kvm_put_vcpu_events: 1085 * @cpu: ARMCPU 1086 * 1087 * Put VCPU related state to kvm. 1088 * 1089 * Returns: 0 if success else < 0 error code 1090 */ 1091 static int kvm_put_vcpu_events(ARMCPU *cpu) 1092 { 1093 CPUARMState *env = &cpu->env; 1094 struct kvm_vcpu_events events; 1095 int ret; 1096 1097 if (!kvm_has_vcpu_events()) { 1098 return 0; 1099 } 1100 1101 memset(&events, 0, sizeof(events)); 1102 events.exception.serror_pending = env->serror.pending; 1103 1104 /* Inject SError to guest with specified syndrome if host kernel 1105 * supports it, otherwise inject SError without syndrome. 1106 */ 1107 if (cap_has_inject_serror_esr) { 1108 events.exception.serror_has_esr = env->serror.has_esr; 1109 events.exception.serror_esr = env->serror.esr; 1110 } 1111 1112 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events); 1113 if (ret) { 1114 error_report("failed to put vcpu events"); 1115 } 1116 1117 return ret; 1118 } 1119 1120 /** 1121 * kvm_get_vcpu_events: 1122 * @cpu: ARMCPU 1123 * 1124 * Get VCPU related state from kvm. 1125 * 1126 * Returns: 0 if success else < 0 error code 1127 */ 1128 static int kvm_get_vcpu_events(ARMCPU *cpu) 1129 { 1130 CPUARMState *env = &cpu->env; 1131 struct kvm_vcpu_events events; 1132 int ret; 1133 1134 if (!kvm_has_vcpu_events()) { 1135 return 0; 1136 } 1137 1138 memset(&events, 0, sizeof(events)); 1139 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events); 1140 if (ret) { 1141 error_report("failed to get vcpu events"); 1142 return ret; 1143 } 1144 1145 env->serror.pending = events.exception.serror_pending; 1146 env->serror.has_esr = events.exception.serror_has_esr; 1147 env->serror.esr = events.exception.serror_esr; 1148 1149 return 0; 1150 } 1151 1152 #define ARM64_REG_ESR_EL1 ARM64_SYS_REG(3, 0, 5, 2, 0) 1153 #define ARM64_REG_TCR_EL1 ARM64_SYS_REG(3, 0, 2, 0, 2) 1154 1155 /* 1156 * ESR_EL1 1157 * ISS encoding 1158 * AARCH64: DFSC, bits [5:0] 1159 * AARCH32: 1160 * TTBCR.EAE == 0 1161 * FS[4] - DFSR[10] 1162 * FS[3:0] - DFSR[3:0] 1163 * TTBCR.EAE == 1 1164 * FS, bits [5:0] 1165 */ 1166 #define ESR_DFSC(aarch64, lpae, v) \ 1167 ((aarch64 || (lpae)) ? ((v) & 0x3F) \ 1168 : (((v) >> 6) | ((v) & 0x1F))) 1169 1170 #define ESR_DFSC_EXTABT(aarch64, lpae) \ 1171 ((aarch64) ? 0x10 : (lpae) ? 0x10 : 0x8) 1172 1173 /** 1174 * kvm_arm_verify_ext_dabt_pending: 1175 * @cs: CPUState 1176 * 1177 * Verify the fault status code wrt the Ext DABT injection 1178 * 1179 * Returns: true if the fault status code is as expected, false otherwise 1180 */ 1181 static bool kvm_arm_verify_ext_dabt_pending(CPUState *cs) 1182 { 1183 uint64_t dfsr_val; 1184 1185 if (!kvm_get_one_reg(cs, ARM64_REG_ESR_EL1, &dfsr_val)) { 1186 ARMCPU *cpu = ARM_CPU(cs); 1187 CPUARMState *env = &cpu->env; 1188 int aarch64_mode = arm_feature(env, ARM_FEATURE_AARCH64); 1189 int lpae = 0; 1190 1191 if (!aarch64_mode) { 1192 uint64_t ttbcr; 1193 1194 if (!kvm_get_one_reg(cs, ARM64_REG_TCR_EL1, &ttbcr)) { 1195 lpae = arm_feature(env, ARM_FEATURE_LPAE) 1196 && (ttbcr & TTBCR_EAE); 1197 } 1198 } 1199 /* 1200 * The verification here is based on the DFSC bits 1201 * of the ESR_EL1 reg only 1202 */ 1203 return (ESR_DFSC(aarch64_mode, lpae, dfsr_val) == 1204 ESR_DFSC_EXTABT(aarch64_mode, lpae)); 1205 } 1206 return false; 1207 } 1208 1209 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) 1210 { 1211 ARMCPU *cpu = ARM_CPU(cs); 1212 CPUARMState *env = &cpu->env; 1213 1214 if (unlikely(env->ext_dabt_raised)) { 1215 /* 1216 * Verifying that the ext DABT has been properly injected, 1217 * otherwise risking indefinitely re-running the faulting instruction 1218 * Covering a very narrow case for kernels 5.5..5.5.4 1219 * when injected abort was misconfigured to be 1220 * an IMPLEMENTATION DEFINED exception (for 32-bit EL1) 1221 */ 1222 if (!arm_feature(env, ARM_FEATURE_AARCH64) && 1223 unlikely(!kvm_arm_verify_ext_dabt_pending(cs))) { 1224 1225 error_report("Data abort exception with no valid ISS generated by " 1226 "guest memory access. KVM unable to emulate faulting " 1227 "instruction. Failed to inject an external data abort " 1228 "into the guest."); 1229 abort(); 1230 } 1231 /* Clear the status */ 1232 env->ext_dabt_raised = 0; 1233 } 1234 } 1235 1236 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) 1237 { 1238 ARMCPU *cpu; 1239 uint32_t switched_level; 1240 1241 if (kvm_irqchip_in_kernel()) { 1242 /* 1243 * We only need to sync timer states with user-space interrupt 1244 * controllers, so return early and save cycles if we don't. 1245 */ 1246 return MEMTXATTRS_UNSPECIFIED; 1247 } 1248 1249 cpu = ARM_CPU(cs); 1250 1251 /* Synchronize our shadowed in-kernel device irq lines with the kvm ones */ 1252 if (run->s.regs.device_irq_level != cpu->device_irq_level) { 1253 switched_level = cpu->device_irq_level ^ run->s.regs.device_irq_level; 1254 1255 qemu_mutex_lock_iothread(); 1256 1257 if (switched_level & KVM_ARM_DEV_EL1_VTIMER) { 1258 qemu_set_irq(cpu->gt_timer_outputs[GTIMER_VIRT], 1259 !!(run->s.regs.device_irq_level & 1260 KVM_ARM_DEV_EL1_VTIMER)); 1261 switched_level &= ~KVM_ARM_DEV_EL1_VTIMER; 1262 } 1263 1264 if (switched_level & KVM_ARM_DEV_EL1_PTIMER) { 1265 qemu_set_irq(cpu->gt_timer_outputs[GTIMER_PHYS], 1266 !!(run->s.regs.device_irq_level & 1267 KVM_ARM_DEV_EL1_PTIMER)); 1268 switched_level &= ~KVM_ARM_DEV_EL1_PTIMER; 1269 } 1270 1271 if (switched_level & KVM_ARM_DEV_PMU) { 1272 qemu_set_irq(cpu->pmu_interrupt, 1273 !!(run->s.regs.device_irq_level & KVM_ARM_DEV_PMU)); 1274 switched_level &= ~KVM_ARM_DEV_PMU; 1275 } 1276 1277 if (switched_level) { 1278 qemu_log_mask(LOG_UNIMP, "%s: unhandled in-kernel device IRQ %x\n", 1279 __func__, switched_level); 1280 } 1281 1282 /* We also mark unknown levels as processed to not waste cycles */ 1283 cpu->device_irq_level = run->s.regs.device_irq_level; 1284 qemu_mutex_unlock_iothread(); 1285 } 1286 1287 return MEMTXATTRS_UNSPECIFIED; 1288 } 1289 1290 static void kvm_arm_vm_state_change(void *opaque, bool running, RunState state) 1291 { 1292 CPUState *cs = opaque; 1293 ARMCPU *cpu = ARM_CPU(cs); 1294 1295 if (running) { 1296 if (cpu->kvm_adjvtime) { 1297 kvm_arm_put_virtual_time(cs); 1298 } 1299 } else { 1300 if (cpu->kvm_adjvtime) { 1301 kvm_arm_get_virtual_time(cs); 1302 } 1303 } 1304 } 1305 1306 /** 1307 * kvm_arm_handle_dabt_nisv: 1308 * @cs: CPUState 1309 * @esr_iss: ISS encoding (limited) for the exception from Data Abort 1310 * ISV bit set to '0b0' -> no valid instruction syndrome 1311 * @fault_ipa: faulting address for the synchronous data abort 1312 * 1313 * Returns: 0 if the exception has been handled, < 0 otherwise 1314 */ 1315 static int kvm_arm_handle_dabt_nisv(CPUState *cs, uint64_t esr_iss, 1316 uint64_t fault_ipa) 1317 { 1318 ARMCPU *cpu = ARM_CPU(cs); 1319 CPUARMState *env = &cpu->env; 1320 /* 1321 * Request KVM to inject the external data abort into the guest 1322 */ 1323 if (cap_has_inject_ext_dabt) { 1324 struct kvm_vcpu_events events = { }; 1325 /* 1326 * The external data abort event will be handled immediately by KVM 1327 * using the address fault that triggered the exit on given VCPU. 1328 * Requesting injection of the external data abort does not rely 1329 * on any other VCPU state. Therefore, in this particular case, the VCPU 1330 * synchronization can be exceptionally skipped. 1331 */ 1332 events.exception.ext_dabt_pending = 1; 1333 /* KVM_CAP_ARM_INJECT_EXT_DABT implies KVM_CAP_VCPU_EVENTS */ 1334 if (!kvm_vcpu_ioctl(cs, KVM_SET_VCPU_EVENTS, &events)) { 1335 env->ext_dabt_raised = 1; 1336 return 0; 1337 } 1338 } else { 1339 error_report("Data abort exception triggered by guest memory access " 1340 "at physical address: 0x" TARGET_FMT_lx, 1341 (target_ulong)fault_ipa); 1342 error_printf("KVM unable to emulate faulting instruction.\n"); 1343 } 1344 return -1; 1345 } 1346 1347 /** 1348 * kvm_arm_handle_debug: 1349 * @cs: CPUState 1350 * @debug_exit: debug part of the KVM exit structure 1351 * 1352 * Returns: TRUE if the debug exception was handled. 1353 * 1354 * See v8 ARM ARM D7.2.27 ESR_ELx, Exception Syndrome Register 1355 * 1356 * To minimise translating between kernel and user-space the kernel 1357 * ABI just provides user-space with the full exception syndrome 1358 * register value to be decoded in QEMU. 1359 */ 1360 static bool kvm_arm_handle_debug(CPUState *cs, 1361 struct kvm_debug_exit_arch *debug_exit) 1362 { 1363 int hsr_ec = syn_get_ec(debug_exit->hsr); 1364 ARMCPU *cpu = ARM_CPU(cs); 1365 CPUARMState *env = &cpu->env; 1366 1367 /* Ensure PC is synchronised */ 1368 kvm_cpu_synchronize_state(cs); 1369 1370 switch (hsr_ec) { 1371 case EC_SOFTWARESTEP: 1372 if (cs->singlestep_enabled) { 1373 return true; 1374 } else { 1375 /* 1376 * The kernel should have suppressed the guest's ability to 1377 * single step at this point so something has gone wrong. 1378 */ 1379 error_report("%s: guest single-step while debugging unsupported" 1380 " (%"PRIx64", %"PRIx32")", 1381 __func__, env->pc, debug_exit->hsr); 1382 return false; 1383 } 1384 break; 1385 case EC_AA64_BKPT: 1386 if (kvm_find_sw_breakpoint(cs, env->pc)) { 1387 return true; 1388 } 1389 break; 1390 case EC_BREAKPOINT: 1391 if (find_hw_breakpoint(cs, env->pc)) { 1392 return true; 1393 } 1394 break; 1395 case EC_WATCHPOINT: 1396 { 1397 CPUWatchpoint *wp = find_hw_watchpoint(cs, debug_exit->far); 1398 if (wp) { 1399 cs->watchpoint_hit = wp; 1400 return true; 1401 } 1402 break; 1403 } 1404 default: 1405 error_report("%s: unhandled debug exit (%"PRIx32", %"PRIx64")", 1406 __func__, debug_exit->hsr, env->pc); 1407 } 1408 1409 /* If we are not handling the debug exception it must belong to 1410 * the guest. Let's re-use the existing TCG interrupt code to set 1411 * everything up properly. 1412 */ 1413 cs->exception_index = EXCP_BKPT; 1414 env->exception.syndrome = debug_exit->hsr; 1415 env->exception.vaddress = debug_exit->far; 1416 env->exception.target_el = 1; 1417 qemu_mutex_lock_iothread(); 1418 arm_cpu_do_interrupt(cs); 1419 qemu_mutex_unlock_iothread(); 1420 1421 return false; 1422 } 1423 1424 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 1425 { 1426 int ret = 0; 1427 1428 switch (run->exit_reason) { 1429 case KVM_EXIT_DEBUG: 1430 if (kvm_arm_handle_debug(cs, &run->debug.arch)) { 1431 ret = EXCP_DEBUG; 1432 } /* otherwise return to guest */ 1433 break; 1434 case KVM_EXIT_ARM_NISV: 1435 /* External DABT with no valid iss to decode */ 1436 ret = kvm_arm_handle_dabt_nisv(cs, run->arm_nisv.esr_iss, 1437 run->arm_nisv.fault_ipa); 1438 break; 1439 default: 1440 qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n", 1441 __func__, run->exit_reason); 1442 break; 1443 } 1444 return ret; 1445 } 1446 1447 bool kvm_arch_stop_on_emulation_error(CPUState *cs) 1448 { 1449 return true; 1450 } 1451 1452 int kvm_arch_process_async_events(CPUState *cs) 1453 { 1454 return 0; 1455 } 1456 1457 /** 1458 * kvm_arm_hw_debug_active: 1459 * @cs: CPU State 1460 * 1461 * Return: TRUE if any hardware breakpoints in use. 1462 */ 1463 static bool kvm_arm_hw_debug_active(CPUState *cs) 1464 { 1465 return ((cur_hw_wps > 0) || (cur_hw_bps > 0)); 1466 } 1467 1468 /** 1469 * kvm_arm_copy_hw_debug_data: 1470 * @ptr: kvm_guest_debug_arch structure 1471 * 1472 * Copy the architecture specific debug registers into the 1473 * kvm_guest_debug ioctl structure. 1474 */ 1475 static void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr) 1476 { 1477 int i; 1478 memset(ptr, 0, sizeof(struct kvm_guest_debug_arch)); 1479 1480 for (i = 0; i < max_hw_wps; i++) { 1481 HWWatchpoint *wp = get_hw_wp(i); 1482 ptr->dbg_wcr[i] = wp->wcr; 1483 ptr->dbg_wvr[i] = wp->wvr; 1484 } 1485 for (i = 0; i < max_hw_bps; i++) { 1486 HWBreakpoint *bp = get_hw_bp(i); 1487 ptr->dbg_bcr[i] = bp->bcr; 1488 ptr->dbg_bvr[i] = bp->bvr; 1489 } 1490 } 1491 1492 void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg) 1493 { 1494 if (kvm_sw_breakpoints_active(cs)) { 1495 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP; 1496 } 1497 if (kvm_arm_hw_debug_active(cs)) { 1498 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW; 1499 kvm_arm_copy_hw_debug_data(&dbg->arch); 1500 } 1501 } 1502 1503 void kvm_arch_init_irq_routing(KVMState *s) 1504 { 1505 } 1506 1507 int kvm_arch_irqchip_create(KVMState *s) 1508 { 1509 if (kvm_kernel_irqchip_split()) { 1510 error_report("-machine kernel_irqchip=split is not supported on ARM."); 1511 exit(1); 1512 } 1513 1514 /* If we can create the VGIC using the newer device control API, we 1515 * let the device do this when it initializes itself, otherwise we 1516 * fall back to the old API */ 1517 return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL); 1518 } 1519 1520 int kvm_arm_vgic_probe(void) 1521 { 1522 int val = 0; 1523 1524 if (kvm_create_device(kvm_state, 1525 KVM_DEV_TYPE_ARM_VGIC_V3, true) == 0) { 1526 val |= KVM_ARM_VGIC_V3; 1527 } 1528 if (kvm_create_device(kvm_state, 1529 KVM_DEV_TYPE_ARM_VGIC_V2, true) == 0) { 1530 val |= KVM_ARM_VGIC_V2; 1531 } 1532 return val; 1533 } 1534 1535 int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level) 1536 { 1537 int kvm_irq = (irqtype << KVM_ARM_IRQ_TYPE_SHIFT) | irq; 1538 int cpu_idx1 = cpu % 256; 1539 int cpu_idx2 = cpu / 256; 1540 1541 kvm_irq |= (cpu_idx1 << KVM_ARM_IRQ_VCPU_SHIFT) | 1542 (cpu_idx2 << KVM_ARM_IRQ_VCPU2_SHIFT); 1543 1544 return kvm_set_irq(kvm_state, kvm_irq, !!level); 1545 } 1546 1547 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 1548 uint64_t address, uint32_t data, PCIDevice *dev) 1549 { 1550 AddressSpace *as = pci_device_iommu_address_space(dev); 1551 hwaddr xlat, len, doorbell_gpa; 1552 MemoryRegionSection mrs; 1553 MemoryRegion *mr; 1554 1555 if (as == &address_space_memory) { 1556 return 0; 1557 } 1558 1559 /* MSI doorbell address is translated by an IOMMU */ 1560 1561 RCU_READ_LOCK_GUARD(); 1562 1563 mr = address_space_translate(as, address, &xlat, &len, true, 1564 MEMTXATTRS_UNSPECIFIED); 1565 1566 if (!mr) { 1567 return 1; 1568 } 1569 1570 mrs = memory_region_find(mr, xlat, 1); 1571 1572 if (!mrs.mr) { 1573 return 1; 1574 } 1575 1576 doorbell_gpa = mrs.offset_within_address_space; 1577 memory_region_unref(mrs.mr); 1578 1579 route->u.msi.address_lo = doorbell_gpa; 1580 route->u.msi.address_hi = doorbell_gpa >> 32; 1581 1582 trace_kvm_arm_fixup_msi_route(address, doorbell_gpa); 1583 1584 return 0; 1585 } 1586 1587 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 1588 int vector, PCIDevice *dev) 1589 { 1590 return 0; 1591 } 1592 1593 int kvm_arch_release_virq_post(int virq) 1594 { 1595 return 0; 1596 } 1597 1598 int kvm_arch_msi_data_to_gsi(uint32_t data) 1599 { 1600 return (data - 32) & 0xffff; 1601 } 1602 1603 bool kvm_arch_cpu_check_are_resettable(void) 1604 { 1605 return true; 1606 } 1607 1608 static void kvm_arch_get_eager_split_size(Object *obj, Visitor *v, 1609 const char *name, void *opaque, 1610 Error **errp) 1611 { 1612 KVMState *s = KVM_STATE(obj); 1613 uint64_t value = s->kvm_eager_split_size; 1614 1615 visit_type_size(v, name, &value, errp); 1616 } 1617 1618 static void kvm_arch_set_eager_split_size(Object *obj, Visitor *v, 1619 const char *name, void *opaque, 1620 Error **errp) 1621 { 1622 KVMState *s = KVM_STATE(obj); 1623 uint64_t value; 1624 1625 if (s->fd != -1) { 1626 error_setg(errp, "Unable to set early-split-size after KVM has been initialized"); 1627 return; 1628 } 1629 1630 if (!visit_type_size(v, name, &value, errp)) { 1631 return; 1632 } 1633 1634 if (value && !is_power_of_2(value)) { 1635 error_setg(errp, "early-split-size must be a power of two"); 1636 return; 1637 } 1638 1639 s->kvm_eager_split_size = value; 1640 } 1641 1642 void kvm_arch_accel_class_init(ObjectClass *oc) 1643 { 1644 object_class_property_add(oc, "eager-split-size", "size", 1645 kvm_arch_get_eager_split_size, 1646 kvm_arch_set_eager_split_size, NULL, NULL); 1647 1648 object_class_property_set_description(oc, "eager-split-size", 1649 "Eager Page Split chunk size for hugepages. (default: 0, disabled)"); 1650 } 1651 1652 int kvm_arch_insert_hw_breakpoint(vaddr addr, vaddr len, int type) 1653 { 1654 switch (type) { 1655 case GDB_BREAKPOINT_HW: 1656 return insert_hw_breakpoint(addr); 1657 break; 1658 case GDB_WATCHPOINT_READ: 1659 case GDB_WATCHPOINT_WRITE: 1660 case GDB_WATCHPOINT_ACCESS: 1661 return insert_hw_watchpoint(addr, len, type); 1662 default: 1663 return -ENOSYS; 1664 } 1665 } 1666 1667 int kvm_arch_remove_hw_breakpoint(vaddr addr, vaddr len, int type) 1668 { 1669 switch (type) { 1670 case GDB_BREAKPOINT_HW: 1671 return delete_hw_breakpoint(addr); 1672 case GDB_WATCHPOINT_READ: 1673 case GDB_WATCHPOINT_WRITE: 1674 case GDB_WATCHPOINT_ACCESS: 1675 return delete_hw_watchpoint(addr, len, type); 1676 default: 1677 return -ENOSYS; 1678 } 1679 } 1680 1681 void kvm_arch_remove_all_hw_breakpoints(void) 1682 { 1683 if (cur_hw_wps > 0) { 1684 g_array_remove_range(hw_watchpoints, 0, cur_hw_wps); 1685 } 1686 if (cur_hw_bps > 0) { 1687 g_array_remove_range(hw_breakpoints, 0, cur_hw_bps); 1688 } 1689 } 1690 1691 static bool kvm_arm_set_device_attr(ARMCPU *cpu, struct kvm_device_attr *attr, 1692 const char *name) 1693 { 1694 int err; 1695 1696 err = kvm_vcpu_ioctl(CPU(cpu), KVM_HAS_DEVICE_ATTR, attr); 1697 if (err != 0) { 1698 error_report("%s: KVM_HAS_DEVICE_ATTR: %s", name, strerror(-err)); 1699 return false; 1700 } 1701 1702 err = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEVICE_ATTR, attr); 1703 if (err != 0) { 1704 error_report("%s: KVM_SET_DEVICE_ATTR: %s", name, strerror(-err)); 1705 return false; 1706 } 1707 1708 return true; 1709 } 1710 1711 void kvm_arm_pmu_init(ARMCPU *cpu) 1712 { 1713 struct kvm_device_attr attr = { 1714 .group = KVM_ARM_VCPU_PMU_V3_CTRL, 1715 .attr = KVM_ARM_VCPU_PMU_V3_INIT, 1716 }; 1717 1718 if (!cpu->has_pmu) { 1719 return; 1720 } 1721 if (!kvm_arm_set_device_attr(cpu, &attr, "PMU")) { 1722 error_report("failed to init PMU"); 1723 abort(); 1724 } 1725 } 1726 1727 void kvm_arm_pmu_set_irq(ARMCPU *cpu, int irq) 1728 { 1729 struct kvm_device_attr attr = { 1730 .group = KVM_ARM_VCPU_PMU_V3_CTRL, 1731 .addr = (intptr_t)&irq, 1732 .attr = KVM_ARM_VCPU_PMU_V3_IRQ, 1733 }; 1734 1735 if (!cpu->has_pmu) { 1736 return; 1737 } 1738 if (!kvm_arm_set_device_attr(cpu, &attr, "PMU")) { 1739 error_report("failed to set irq for PMU"); 1740 abort(); 1741 } 1742 } 1743 1744 void kvm_arm_pvtime_init(ARMCPU *cpu, uint64_t ipa) 1745 { 1746 struct kvm_device_attr attr = { 1747 .group = KVM_ARM_VCPU_PVTIME_CTRL, 1748 .attr = KVM_ARM_VCPU_PVTIME_IPA, 1749 .addr = (uint64_t)&ipa, 1750 }; 1751 1752 if (cpu->kvm_steal_time == ON_OFF_AUTO_OFF) { 1753 return; 1754 } 1755 if (!kvm_arm_set_device_attr(cpu, &attr, "PVTIME IPA")) { 1756 error_report("failed to init PVTIME IPA"); 1757 abort(); 1758 } 1759 } 1760 1761 void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp) 1762 { 1763 bool has_steal_time = kvm_check_extension(kvm_state, KVM_CAP_STEAL_TIME); 1764 1765 if (cpu->kvm_steal_time == ON_OFF_AUTO_AUTO) { 1766 if (!has_steal_time || !arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1767 cpu->kvm_steal_time = ON_OFF_AUTO_OFF; 1768 } else { 1769 cpu->kvm_steal_time = ON_OFF_AUTO_ON; 1770 } 1771 } else if (cpu->kvm_steal_time == ON_OFF_AUTO_ON) { 1772 if (!has_steal_time) { 1773 error_setg(errp, "'kvm-steal-time' cannot be enabled " 1774 "on this host"); 1775 return; 1776 } else if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1777 /* 1778 * DEN0057A chapter 2 says "This specification only covers 1779 * systems in which the Execution state of the hypervisor 1780 * as well as EL1 of virtual machines is AArch64.". And, 1781 * to ensure that, the smc/hvc calls are only specified as 1782 * smc64/hvc64. 1783 */ 1784 error_setg(errp, "'kvm-steal-time' cannot be enabled " 1785 "for AArch32 guests"); 1786 return; 1787 } 1788 } 1789 } 1790 1791 bool kvm_arm_aarch32_supported(void) 1792 { 1793 return kvm_check_extension(kvm_state, KVM_CAP_ARM_EL1_32BIT); 1794 } 1795 1796 bool kvm_arm_sve_supported(void) 1797 { 1798 return kvm_check_extension(kvm_state, KVM_CAP_ARM_SVE); 1799 } 1800 1801 QEMU_BUILD_BUG_ON(KVM_ARM64_SVE_VQ_MIN != 1); 1802 1803 uint32_t kvm_arm_sve_get_vls(ARMCPU *cpu) 1804 { 1805 /* Only call this function if kvm_arm_sve_supported() returns true. */ 1806 static uint64_t vls[KVM_ARM64_SVE_VLS_WORDS]; 1807 static bool probed; 1808 uint32_t vq = 0; 1809 int i; 1810 1811 /* 1812 * KVM ensures all host CPUs support the same set of vector lengths. 1813 * So we only need to create the scratch VCPUs once and then cache 1814 * the results. 1815 */ 1816 if (!probed) { 1817 struct kvm_vcpu_init init = { 1818 .target = -1, 1819 .features[0] = (1 << KVM_ARM_VCPU_SVE), 1820 }; 1821 struct kvm_one_reg reg = { 1822 .id = KVM_REG_ARM64_SVE_VLS, 1823 .addr = (uint64_t)&vls[0], 1824 }; 1825 int fdarray[3], ret; 1826 1827 probed = true; 1828 1829 if (!kvm_arm_create_scratch_host_vcpu(NULL, fdarray, &init)) { 1830 error_report("failed to create scratch VCPU with SVE enabled"); 1831 abort(); 1832 } 1833 ret = ioctl(fdarray[2], KVM_GET_ONE_REG, ®); 1834 kvm_arm_destroy_scratch_host_vcpu(fdarray); 1835 if (ret) { 1836 error_report("failed to get KVM_REG_ARM64_SVE_VLS: %s", 1837 strerror(errno)); 1838 abort(); 1839 } 1840 1841 for (i = KVM_ARM64_SVE_VLS_WORDS - 1; i >= 0; --i) { 1842 if (vls[i]) { 1843 vq = 64 - clz64(vls[i]) + i * 64; 1844 break; 1845 } 1846 } 1847 if (vq > ARM_MAX_VQ) { 1848 warn_report("KVM supports vector lengths larger than " 1849 "QEMU can enable"); 1850 vls[0] &= MAKE_64BIT_MASK(0, ARM_MAX_VQ); 1851 } 1852 } 1853 1854 return vls[0]; 1855 } 1856 1857 static int kvm_arm_sve_set_vls(ARMCPU *cpu) 1858 { 1859 uint64_t vls[KVM_ARM64_SVE_VLS_WORDS] = { cpu->sve_vq.map }; 1860 1861 assert(cpu->sve_max_vq <= KVM_ARM64_SVE_VQ_MAX); 1862 1863 return kvm_set_one_reg(CPU(cpu), KVM_REG_ARM64_SVE_VLS, &vls[0]); 1864 } 1865 1866 #define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5 1867 1868 int kvm_arch_init_vcpu(CPUState *cs) 1869 { 1870 int ret; 1871 uint64_t mpidr; 1872 ARMCPU *cpu = ARM_CPU(cs); 1873 CPUARMState *env = &cpu->env; 1874 uint64_t psciver; 1875 1876 if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE || 1877 !object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU)) { 1878 error_report("KVM is not supported for this guest CPU type"); 1879 return -EINVAL; 1880 } 1881 1882 qemu_add_vm_change_state_handler(kvm_arm_vm_state_change, cs); 1883 1884 /* Determine init features for this CPU */ 1885 memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features)); 1886 if (cs->start_powered_off) { 1887 cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_POWER_OFF; 1888 } 1889 if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PSCI_0_2)) { 1890 cpu->psci_version = QEMU_PSCI_VERSION_0_2; 1891 cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2; 1892 } 1893 if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1894 cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_EL1_32BIT; 1895 } 1896 if (!kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PMU_V3)) { 1897 cpu->has_pmu = false; 1898 } 1899 if (cpu->has_pmu) { 1900 cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PMU_V3; 1901 } else { 1902 env->features &= ~(1ULL << ARM_FEATURE_PMU); 1903 } 1904 if (cpu_isar_feature(aa64_sve, cpu)) { 1905 assert(kvm_arm_sve_supported()); 1906 cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_SVE; 1907 } 1908 if (cpu_isar_feature(aa64_pauth, cpu)) { 1909 cpu->kvm_init_features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | 1910 1 << KVM_ARM_VCPU_PTRAUTH_GENERIC); 1911 } 1912 1913 /* Do KVM_ARM_VCPU_INIT ioctl */ 1914 ret = kvm_arm_vcpu_init(cpu); 1915 if (ret) { 1916 return ret; 1917 } 1918 1919 if (cpu_isar_feature(aa64_sve, cpu)) { 1920 ret = kvm_arm_sve_set_vls(cpu); 1921 if (ret) { 1922 return ret; 1923 } 1924 ret = kvm_arm_vcpu_finalize(cpu, KVM_ARM_VCPU_SVE); 1925 if (ret) { 1926 return ret; 1927 } 1928 } 1929 1930 /* 1931 * KVM reports the exact PSCI version it is implementing via a 1932 * special sysreg. If it is present, use its contents to determine 1933 * what to report to the guest in the dtb (it is the PSCI version, 1934 * in the same 15-bits major 16-bits minor format that PSCI_VERSION 1935 * returns). 1936 */ 1937 if (!kvm_get_one_reg(cs, KVM_REG_ARM_PSCI_VERSION, &psciver)) { 1938 cpu->psci_version = psciver; 1939 } 1940 1941 /* 1942 * When KVM is in use, PSCI is emulated in-kernel and not by qemu. 1943 * Currently KVM has its own idea about MPIDR assignment, so we 1944 * override our defaults with what we get from KVM. 1945 */ 1946 ret = kvm_get_one_reg(cs, ARM64_SYS_REG(ARM_CPU_ID_MPIDR), &mpidr); 1947 if (ret) { 1948 return ret; 1949 } 1950 cpu->mp_affinity = mpidr & ARM64_AFFINITY_MASK; 1951 1952 return kvm_arm_init_cpreg_list(cpu); 1953 } 1954 1955 int kvm_arch_destroy_vcpu(CPUState *cs) 1956 { 1957 return 0; 1958 } 1959 1960 /* Callers must hold the iothread mutex lock */ 1961 static void kvm_inject_arm_sea(CPUState *c) 1962 { 1963 ARMCPU *cpu = ARM_CPU(c); 1964 CPUARMState *env = &cpu->env; 1965 uint32_t esr; 1966 bool same_el; 1967 1968 c->exception_index = EXCP_DATA_ABORT; 1969 env->exception.target_el = 1; 1970 1971 /* 1972 * Set the DFSC to synchronous external abort and set FnV to not valid, 1973 * this will tell guest the FAR_ELx is UNKNOWN for this abort. 1974 */ 1975 same_el = arm_current_el(env) == env->exception.target_el; 1976 esr = syn_data_abort_no_iss(same_el, 1, 0, 0, 0, 0, 0x10); 1977 1978 env->exception.syndrome = esr; 1979 1980 arm_cpu_do_interrupt(c); 1981 } 1982 1983 #define AARCH64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \ 1984 KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x)) 1985 1986 #define AARCH64_SIMD_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U128 | \ 1987 KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x)) 1988 1989 #define AARCH64_SIMD_CTRL_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U32 | \ 1990 KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x)) 1991 1992 static int kvm_arch_put_fpsimd(CPUState *cs) 1993 { 1994 CPUARMState *env = &ARM_CPU(cs)->env; 1995 int i, ret; 1996 1997 for (i = 0; i < 32; i++) { 1998 uint64_t *q = aa64_vfp_qreg(env, i); 1999 #if HOST_BIG_ENDIAN 2000 uint64_t fp_val[2] = { q[1], q[0] }; 2001 ret = kvm_set_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]), 2002 fp_val); 2003 #else 2004 ret = kvm_set_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]), q); 2005 #endif 2006 if (ret) { 2007 return ret; 2008 } 2009 } 2010 2011 return 0; 2012 } 2013 2014 /* 2015 * KVM SVE registers come in slices where ZREGs have a slice size of 2048 bits 2016 * and PREGS and the FFR have a slice size of 256 bits. However we simply hard 2017 * code the slice index to zero for now as it's unlikely we'll need more than 2018 * one slice for quite some time. 2019 */ 2020 static int kvm_arch_put_sve(CPUState *cs) 2021 { 2022 ARMCPU *cpu = ARM_CPU(cs); 2023 CPUARMState *env = &cpu->env; 2024 uint64_t tmp[ARM_MAX_VQ * 2]; 2025 uint64_t *r; 2026 int n, ret; 2027 2028 for (n = 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) { 2029 r = sve_bswap64(tmp, &env->vfp.zregs[n].d[0], cpu->sve_max_vq * 2); 2030 ret = kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_ZREG(n, 0), r); 2031 if (ret) { 2032 return ret; 2033 } 2034 } 2035 2036 for (n = 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) { 2037 r = sve_bswap64(tmp, r = &env->vfp.pregs[n].p[0], 2038 DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); 2039 ret = kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_PREG(n, 0), r); 2040 if (ret) { 2041 return ret; 2042 } 2043 } 2044 2045 r = sve_bswap64(tmp, &env->vfp.pregs[FFR_PRED_NUM].p[0], 2046 DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); 2047 ret = kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_FFR(0), r); 2048 if (ret) { 2049 return ret; 2050 } 2051 2052 return 0; 2053 } 2054 2055 int kvm_arch_put_registers(CPUState *cs, int level) 2056 { 2057 uint64_t val; 2058 uint32_t fpr; 2059 int i, ret; 2060 unsigned int el; 2061 2062 ARMCPU *cpu = ARM_CPU(cs); 2063 CPUARMState *env = &cpu->env; 2064 2065 /* If we are in AArch32 mode then we need to copy the AArch32 regs to the 2066 * AArch64 registers before pushing them out to 64-bit KVM. 2067 */ 2068 if (!is_a64(env)) { 2069 aarch64_sync_32_to_64(env); 2070 } 2071 2072 for (i = 0; i < 31; i++) { 2073 ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.regs[i]), 2074 &env->xregs[i]); 2075 if (ret) { 2076 return ret; 2077 } 2078 } 2079 2080 /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the 2081 * QEMU side we keep the current SP in xregs[31] as well. 2082 */ 2083 aarch64_save_sp(env, 1); 2084 2085 ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.sp), &env->sp_el[0]); 2086 if (ret) { 2087 return ret; 2088 } 2089 2090 ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(sp_el1), &env->sp_el[1]); 2091 if (ret) { 2092 return ret; 2093 } 2094 2095 /* Note that KVM thinks pstate is 64 bit but we use a uint32_t */ 2096 if (is_a64(env)) { 2097 val = pstate_read(env); 2098 } else { 2099 val = cpsr_read(env); 2100 } 2101 ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.pstate), &val); 2102 if (ret) { 2103 return ret; 2104 } 2105 2106 ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.pc), &env->pc); 2107 if (ret) { 2108 return ret; 2109 } 2110 2111 ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(elr_el1), &env->elr_el[1]); 2112 if (ret) { 2113 return ret; 2114 } 2115 2116 /* Saved Program State Registers 2117 * 2118 * Before we restore from the banked_spsr[] array we need to 2119 * ensure that any modifications to env->spsr are correctly 2120 * reflected in the banks. 2121 */ 2122 el = arm_current_el(env); 2123 if (el > 0 && !is_a64(env)) { 2124 i = bank_number(env->uncached_cpsr & CPSR_M); 2125 env->banked_spsr[i] = env->spsr; 2126 } 2127 2128 /* KVM 0-4 map to QEMU banks 1-5 */ 2129 for (i = 0; i < KVM_NR_SPSR; i++) { 2130 ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(spsr[i]), 2131 &env->banked_spsr[i + 1]); 2132 if (ret) { 2133 return ret; 2134 } 2135 } 2136 2137 if (cpu_isar_feature(aa64_sve, cpu)) { 2138 ret = kvm_arch_put_sve(cs); 2139 } else { 2140 ret = kvm_arch_put_fpsimd(cs); 2141 } 2142 if (ret) { 2143 return ret; 2144 } 2145 2146 fpr = vfp_get_fpsr(env); 2147 ret = kvm_set_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpsr), &fpr); 2148 if (ret) { 2149 return ret; 2150 } 2151 2152 fpr = vfp_get_fpcr(env); 2153 ret = kvm_set_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpcr), &fpr); 2154 if (ret) { 2155 return ret; 2156 } 2157 2158 write_cpustate_to_list(cpu, true); 2159 2160 if (!write_list_to_kvmstate(cpu, level)) { 2161 return -EINVAL; 2162 } 2163 2164 /* 2165 * Setting VCPU events should be triggered after syncing the registers 2166 * to avoid overwriting potential changes made by KVM upon calling 2167 * KVM_SET_VCPU_EVENTS ioctl 2168 */ 2169 ret = kvm_put_vcpu_events(cpu); 2170 if (ret) { 2171 return ret; 2172 } 2173 2174 return kvm_arm_sync_mpstate_to_kvm(cpu); 2175 } 2176 2177 static int kvm_arch_get_fpsimd(CPUState *cs) 2178 { 2179 CPUARMState *env = &ARM_CPU(cs)->env; 2180 int i, ret; 2181 2182 for (i = 0; i < 32; i++) { 2183 uint64_t *q = aa64_vfp_qreg(env, i); 2184 ret = kvm_get_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]), q); 2185 if (ret) { 2186 return ret; 2187 } else { 2188 #if HOST_BIG_ENDIAN 2189 uint64_t t; 2190 t = q[0], q[0] = q[1], q[1] = t; 2191 #endif 2192 } 2193 } 2194 2195 return 0; 2196 } 2197 2198 /* 2199 * KVM SVE registers come in slices where ZREGs have a slice size of 2048 bits 2200 * and PREGS and the FFR have a slice size of 256 bits. However we simply hard 2201 * code the slice index to zero for now as it's unlikely we'll need more than 2202 * one slice for quite some time. 2203 */ 2204 static int kvm_arch_get_sve(CPUState *cs) 2205 { 2206 ARMCPU *cpu = ARM_CPU(cs); 2207 CPUARMState *env = &cpu->env; 2208 uint64_t *r; 2209 int n, ret; 2210 2211 for (n = 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) { 2212 r = &env->vfp.zregs[n].d[0]; 2213 ret = kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_ZREG(n, 0), r); 2214 if (ret) { 2215 return ret; 2216 } 2217 sve_bswap64(r, r, cpu->sve_max_vq * 2); 2218 } 2219 2220 for (n = 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) { 2221 r = &env->vfp.pregs[n].p[0]; 2222 ret = kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_PREG(n, 0), r); 2223 if (ret) { 2224 return ret; 2225 } 2226 sve_bswap64(r, r, DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); 2227 } 2228 2229 r = &env->vfp.pregs[FFR_PRED_NUM].p[0]; 2230 ret = kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_FFR(0), r); 2231 if (ret) { 2232 return ret; 2233 } 2234 sve_bswap64(r, r, DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); 2235 2236 return 0; 2237 } 2238 2239 int kvm_arch_get_registers(CPUState *cs) 2240 { 2241 uint64_t val; 2242 unsigned int el; 2243 uint32_t fpr; 2244 int i, ret; 2245 2246 ARMCPU *cpu = ARM_CPU(cs); 2247 CPUARMState *env = &cpu->env; 2248 2249 for (i = 0; i < 31; i++) { 2250 ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.regs[i]), 2251 &env->xregs[i]); 2252 if (ret) { 2253 return ret; 2254 } 2255 } 2256 2257 ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.sp), &env->sp_el[0]); 2258 if (ret) { 2259 return ret; 2260 } 2261 2262 ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(sp_el1), &env->sp_el[1]); 2263 if (ret) { 2264 return ret; 2265 } 2266 2267 ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.pstate), &val); 2268 if (ret) { 2269 return ret; 2270 } 2271 2272 env->aarch64 = ((val & PSTATE_nRW) == 0); 2273 if (is_a64(env)) { 2274 pstate_write(env, val); 2275 } else { 2276 cpsr_write(env, val, 0xffffffff, CPSRWriteRaw); 2277 } 2278 2279 /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the 2280 * QEMU side we keep the current SP in xregs[31] as well. 2281 */ 2282 aarch64_restore_sp(env, 1); 2283 2284 ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.pc), &env->pc); 2285 if (ret) { 2286 return ret; 2287 } 2288 2289 /* If we are in AArch32 mode then we need to sync the AArch32 regs with the 2290 * incoming AArch64 regs received from 64-bit KVM. 2291 * We must perform this after all of the registers have been acquired from 2292 * the kernel. 2293 */ 2294 if (!is_a64(env)) { 2295 aarch64_sync_64_to_32(env); 2296 } 2297 2298 ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(elr_el1), &env->elr_el[1]); 2299 if (ret) { 2300 return ret; 2301 } 2302 2303 /* Fetch the SPSR registers 2304 * 2305 * KVM SPSRs 0-4 map to QEMU banks 1-5 2306 */ 2307 for (i = 0; i < KVM_NR_SPSR; i++) { 2308 ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(spsr[i]), 2309 &env->banked_spsr[i + 1]); 2310 if (ret) { 2311 return ret; 2312 } 2313 } 2314 2315 el = arm_current_el(env); 2316 if (el > 0 && !is_a64(env)) { 2317 i = bank_number(env->uncached_cpsr & CPSR_M); 2318 env->spsr = env->banked_spsr[i]; 2319 } 2320 2321 if (cpu_isar_feature(aa64_sve, cpu)) { 2322 ret = kvm_arch_get_sve(cs); 2323 } else { 2324 ret = kvm_arch_get_fpsimd(cs); 2325 } 2326 if (ret) { 2327 return ret; 2328 } 2329 2330 ret = kvm_get_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpsr), &fpr); 2331 if (ret) { 2332 return ret; 2333 } 2334 vfp_set_fpsr(env, fpr); 2335 2336 ret = kvm_get_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpcr), &fpr); 2337 if (ret) { 2338 return ret; 2339 } 2340 vfp_set_fpcr(env, fpr); 2341 2342 ret = kvm_get_vcpu_events(cpu); 2343 if (ret) { 2344 return ret; 2345 } 2346 2347 if (!write_kvmstate_to_list(cpu)) { 2348 return -EINVAL; 2349 } 2350 /* Note that it's OK to have registers which aren't in CPUState, 2351 * so we can ignore a failure return here. 2352 */ 2353 write_list_to_cpustate(cpu); 2354 2355 ret = kvm_arm_sync_mpstate_to_qemu(cpu); 2356 2357 /* TODO: other registers */ 2358 return ret; 2359 } 2360 2361 void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr) 2362 { 2363 ram_addr_t ram_addr; 2364 hwaddr paddr; 2365 2366 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO); 2367 2368 if (acpi_ghes_present() && addr) { 2369 ram_addr = qemu_ram_addr_from_host(addr); 2370 if (ram_addr != RAM_ADDR_INVALID && 2371 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) { 2372 kvm_hwpoison_page_add(ram_addr); 2373 /* 2374 * If this is a BUS_MCEERR_AR, we know we have been called 2375 * synchronously from the vCPU thread, so we can easily 2376 * synchronize the state and inject an error. 2377 * 2378 * TODO: we currently don't tell the guest at all about 2379 * BUS_MCEERR_AO. In that case we might either be being 2380 * called synchronously from the vCPU thread, or a bit 2381 * later from the main thread, so doing the injection of 2382 * the error would be more complicated. 2383 */ 2384 if (code == BUS_MCEERR_AR) { 2385 kvm_cpu_synchronize_state(c); 2386 if (!acpi_ghes_record_errors(ACPI_HEST_SRC_ID_SEA, paddr)) { 2387 kvm_inject_arm_sea(c); 2388 } else { 2389 error_report("failed to record the error"); 2390 abort(); 2391 } 2392 } 2393 return; 2394 } 2395 if (code == BUS_MCEERR_AO) { 2396 error_report("Hardware memory error at addr %p for memory used by " 2397 "QEMU itself instead of guest system!", addr); 2398 } 2399 } 2400 2401 if (code == BUS_MCEERR_AR) { 2402 error_report("Hardware memory error!"); 2403 exit(1); 2404 } 2405 } 2406 2407 /* C6.6.29 BRK instruction */ 2408 static const uint32_t brk_insn = 0xd4200000; 2409 2410 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 2411 { 2412 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 0) || 2413 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk_insn, 4, 1)) { 2414 return -EINVAL; 2415 } 2416 return 0; 2417 } 2418 2419 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 2420 { 2421 static uint32_t brk; 2422 2423 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk, 4, 0) || 2424 brk != brk_insn || 2425 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 1)) { 2426 return -EINVAL; 2427 } 2428 return 0; 2429 } 2430