1 /* 2 * ARM implementation of KVM hooks 3 * 4 * Copyright Christoffer Dall 2009-2010 5 * Copyright Mian-M. Hamayun 2013, Virtual Open Systems 6 * Copyright Alex Bennée 2014, Linaro 7 * 8 * This work is licensed under the terms of the GNU GPL, version 2 or later. 9 * See the COPYING file in the top-level directory. 10 * 11 */ 12 13 #include "qemu/osdep.h" 14 #include <sys/ioctl.h> 15 16 #include <linux/kvm.h> 17 18 #include "qemu/timer.h" 19 #include "qemu/error-report.h" 20 #include "qemu/main-loop.h" 21 #include "qom/object.h" 22 #include "qapi/error.h" 23 #include "sysemu/sysemu.h" 24 #include "sysemu/runstate.h" 25 #include "sysemu/kvm.h" 26 #include "sysemu/kvm_int.h" 27 #include "kvm_arm.h" 28 #include "cpu.h" 29 #include "trace.h" 30 #include "internals.h" 31 #include "hw/pci/pci.h" 32 #include "exec/memattrs.h" 33 #include "exec/address-spaces.h" 34 #include "exec/gdbstub.h" 35 #include "hw/boards.h" 36 #include "hw/irq.h" 37 #include "qapi/visitor.h" 38 #include "qemu/log.h" 39 #include "hw/acpi/acpi.h" 40 #include "hw/acpi/ghes.h" 41 42 const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 43 KVM_CAP_LAST_INFO 44 }; 45 46 static bool cap_has_mp_state; 47 static bool cap_has_inject_serror_esr; 48 static bool cap_has_inject_ext_dabt; 49 50 /** 51 * ARMHostCPUFeatures: information about the host CPU (identified 52 * by asking the host kernel) 53 */ 54 typedef struct ARMHostCPUFeatures { 55 ARMISARegisters isar; 56 uint64_t features; 57 uint32_t target; 58 const char *dtb_compatible; 59 } ARMHostCPUFeatures; 60 61 static ARMHostCPUFeatures arm_host_cpu_features; 62 63 /** 64 * kvm_arm_vcpu_init: 65 * @cs: CPUState 66 * 67 * Initialize (or reinitialize) the VCPU by invoking the 68 * KVM_ARM_VCPU_INIT ioctl with the CPU type and feature 69 * bitmask specified in the CPUState. 70 * 71 * Returns: 0 if success else < 0 error code 72 */ 73 static int kvm_arm_vcpu_init(CPUState *cs) 74 { 75 ARMCPU *cpu = ARM_CPU(cs); 76 struct kvm_vcpu_init init; 77 78 init.target = cpu->kvm_target; 79 memcpy(init.features, cpu->kvm_init_features, sizeof(init.features)); 80 81 return kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_INIT, &init); 82 } 83 84 /** 85 * kvm_arm_vcpu_finalize: 86 * @cs: CPUState 87 * @feature: feature to finalize 88 * 89 * Finalizes the configuration of the specified VCPU feature by 90 * invoking the KVM_ARM_VCPU_FINALIZE ioctl. Features requiring 91 * this are documented in the "KVM_ARM_VCPU_FINALIZE" section of 92 * KVM's API documentation. 93 * 94 * Returns: 0 if success else < 0 error code 95 */ 96 static int kvm_arm_vcpu_finalize(CPUState *cs, int feature) 97 { 98 return kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_FINALIZE, &feature); 99 } 100 101 bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try, 102 int *fdarray, 103 struct kvm_vcpu_init *init) 104 { 105 int ret = 0, kvmfd = -1, vmfd = -1, cpufd = -1; 106 int max_vm_pa_size; 107 108 kvmfd = qemu_open_old("/dev/kvm", O_RDWR); 109 if (kvmfd < 0) { 110 goto err; 111 } 112 max_vm_pa_size = ioctl(kvmfd, KVM_CHECK_EXTENSION, KVM_CAP_ARM_VM_IPA_SIZE); 113 if (max_vm_pa_size < 0) { 114 max_vm_pa_size = 0; 115 } 116 do { 117 vmfd = ioctl(kvmfd, KVM_CREATE_VM, max_vm_pa_size); 118 } while (vmfd == -1 && errno == EINTR); 119 if (vmfd < 0) { 120 goto err; 121 } 122 cpufd = ioctl(vmfd, KVM_CREATE_VCPU, 0); 123 if (cpufd < 0) { 124 goto err; 125 } 126 127 if (!init) { 128 /* Caller doesn't want the VCPU to be initialized, so skip it */ 129 goto finish; 130 } 131 132 if (init->target == -1) { 133 struct kvm_vcpu_init preferred; 134 135 ret = ioctl(vmfd, KVM_ARM_PREFERRED_TARGET, &preferred); 136 if (!ret) { 137 init->target = preferred.target; 138 } 139 } 140 if (ret >= 0) { 141 ret = ioctl(cpufd, KVM_ARM_VCPU_INIT, init); 142 if (ret < 0) { 143 goto err; 144 } 145 } else if (cpus_to_try) { 146 /* Old kernel which doesn't know about the 147 * PREFERRED_TARGET ioctl: we know it will only support 148 * creating one kind of guest CPU which is its preferred 149 * CPU type. 150 */ 151 struct kvm_vcpu_init try; 152 153 while (*cpus_to_try != QEMU_KVM_ARM_TARGET_NONE) { 154 try.target = *cpus_to_try++; 155 memcpy(try.features, init->features, sizeof(init->features)); 156 ret = ioctl(cpufd, KVM_ARM_VCPU_INIT, &try); 157 if (ret >= 0) { 158 break; 159 } 160 } 161 if (ret < 0) { 162 goto err; 163 } 164 init->target = try.target; 165 } else { 166 /* Treat a NULL cpus_to_try argument the same as an empty 167 * list, which means we will fail the call since this must 168 * be an old kernel which doesn't support PREFERRED_TARGET. 169 */ 170 goto err; 171 } 172 173 finish: 174 fdarray[0] = kvmfd; 175 fdarray[1] = vmfd; 176 fdarray[2] = cpufd; 177 178 return true; 179 180 err: 181 if (cpufd >= 0) { 182 close(cpufd); 183 } 184 if (vmfd >= 0) { 185 close(vmfd); 186 } 187 if (kvmfd >= 0) { 188 close(kvmfd); 189 } 190 191 return false; 192 } 193 194 void kvm_arm_destroy_scratch_host_vcpu(int *fdarray) 195 { 196 int i; 197 198 for (i = 2; i >= 0; i--) { 199 close(fdarray[i]); 200 } 201 } 202 203 static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id) 204 { 205 uint64_t ret; 206 struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)&ret }; 207 int err; 208 209 assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64); 210 err = ioctl(fd, KVM_GET_ONE_REG, &idreg); 211 if (err < 0) { 212 return -1; 213 } 214 *pret = ret; 215 return 0; 216 } 217 218 static int read_sys_reg64(int fd, uint64_t *pret, uint64_t id) 219 { 220 struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)pret }; 221 222 assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64); 223 return ioctl(fd, KVM_GET_ONE_REG, &idreg); 224 } 225 226 static bool kvm_arm_pauth_supported(void) 227 { 228 return (kvm_check_extension(kvm_state, KVM_CAP_ARM_PTRAUTH_ADDRESS) && 229 kvm_check_extension(kvm_state, KVM_CAP_ARM_PTRAUTH_GENERIC)); 230 } 231 232 static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) 233 { 234 /* Identify the feature bits corresponding to the host CPU, and 235 * fill out the ARMHostCPUClass fields accordingly. To do this 236 * we have to create a scratch VM, create a single CPU inside it, 237 * and then query that CPU for the relevant ID registers. 238 */ 239 int fdarray[3]; 240 bool sve_supported; 241 bool pmu_supported = false; 242 uint64_t features = 0; 243 int err; 244 245 /* Old kernels may not know about the PREFERRED_TARGET ioctl: however 246 * we know these will only support creating one kind of guest CPU, 247 * which is its preferred CPU type. Fortunately these old kernels 248 * support only a very limited number of CPUs. 249 */ 250 static const uint32_t cpus_to_try[] = { 251 KVM_ARM_TARGET_AEM_V8, 252 KVM_ARM_TARGET_FOUNDATION_V8, 253 KVM_ARM_TARGET_CORTEX_A57, 254 QEMU_KVM_ARM_TARGET_NONE 255 }; 256 /* 257 * target = -1 informs kvm_arm_create_scratch_host_vcpu() 258 * to use the preferred target 259 */ 260 struct kvm_vcpu_init init = { .target = -1, }; 261 262 /* 263 * Ask for SVE if supported, so that we can query ID_AA64ZFR0, 264 * which is otherwise RAZ. 265 */ 266 sve_supported = kvm_arm_sve_supported(); 267 if (sve_supported) { 268 init.features[0] |= 1 << KVM_ARM_VCPU_SVE; 269 } 270 271 /* 272 * Ask for Pointer Authentication if supported, so that we get 273 * the unsanitized field values for AA64ISAR1_EL1. 274 */ 275 if (kvm_arm_pauth_supported()) { 276 init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | 277 1 << KVM_ARM_VCPU_PTRAUTH_GENERIC); 278 } 279 280 if (kvm_arm_pmu_supported()) { 281 init.features[0] |= 1 << KVM_ARM_VCPU_PMU_V3; 282 pmu_supported = true; 283 } 284 285 if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) { 286 return false; 287 } 288 289 ahcf->target = init.target; 290 ahcf->dtb_compatible = "arm,arm-v8"; 291 292 err = read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr0, 293 ARM64_SYS_REG(3, 0, 0, 4, 0)); 294 if (unlikely(err < 0)) { 295 /* 296 * Before v4.15, the kernel only exposed a limited number of system 297 * registers, not including any of the interesting AArch64 ID regs. 298 * For the most part we could leave these fields as zero with minimal 299 * effect, since this does not affect the values seen by the guest. 300 * 301 * However, it could cause problems down the line for QEMU, 302 * so provide a minimal v8.0 default. 303 * 304 * ??? Could read MIDR and use knowledge from cpu64.c. 305 * ??? Could map a page of memory into our temp guest and 306 * run the tiniest of hand-crafted kernels to extract 307 * the values seen by the guest. 308 * ??? Either of these sounds like too much effort just 309 * to work around running a modern host kernel. 310 */ 311 ahcf->isar.id_aa64pfr0 = 0x00000011; /* EL1&0, AArch64 only */ 312 err = 0; 313 } else { 314 err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr1, 315 ARM64_SYS_REG(3, 0, 0, 4, 1)); 316 err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64smfr0, 317 ARM64_SYS_REG(3, 0, 0, 4, 5)); 318 err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr0, 319 ARM64_SYS_REG(3, 0, 0, 5, 0)); 320 err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr1, 321 ARM64_SYS_REG(3, 0, 0, 5, 1)); 322 err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar0, 323 ARM64_SYS_REG(3, 0, 0, 6, 0)); 324 err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1, 325 ARM64_SYS_REG(3, 0, 0, 6, 1)); 326 err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar2, 327 ARM64_SYS_REG(3, 0, 0, 6, 2)); 328 err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr0, 329 ARM64_SYS_REG(3, 0, 0, 7, 0)); 330 err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1, 331 ARM64_SYS_REG(3, 0, 0, 7, 1)); 332 err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2, 333 ARM64_SYS_REG(3, 0, 0, 7, 2)); 334 335 /* 336 * Note that if AArch32 support is not present in the host, 337 * the AArch32 sysregs are present to be read, but will 338 * return UNKNOWN values. This is neither better nor worse 339 * than skipping the reads and leaving 0, as we must avoid 340 * considering the values in every case. 341 */ 342 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr0, 343 ARM64_SYS_REG(3, 0, 0, 1, 0)); 344 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr1, 345 ARM64_SYS_REG(3, 0, 0, 1, 1)); 346 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0, 347 ARM64_SYS_REG(3, 0, 0, 1, 2)); 348 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0, 349 ARM64_SYS_REG(3, 0, 0, 1, 4)); 350 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr1, 351 ARM64_SYS_REG(3, 0, 0, 1, 5)); 352 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr2, 353 ARM64_SYS_REG(3, 0, 0, 1, 6)); 354 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr3, 355 ARM64_SYS_REG(3, 0, 0, 1, 7)); 356 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0, 357 ARM64_SYS_REG(3, 0, 0, 2, 0)); 358 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1, 359 ARM64_SYS_REG(3, 0, 0, 2, 1)); 360 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2, 361 ARM64_SYS_REG(3, 0, 0, 2, 2)); 362 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3, 363 ARM64_SYS_REG(3, 0, 0, 2, 3)); 364 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4, 365 ARM64_SYS_REG(3, 0, 0, 2, 4)); 366 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5, 367 ARM64_SYS_REG(3, 0, 0, 2, 5)); 368 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr4, 369 ARM64_SYS_REG(3, 0, 0, 2, 6)); 370 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6, 371 ARM64_SYS_REG(3, 0, 0, 2, 7)); 372 373 err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0, 374 ARM64_SYS_REG(3, 0, 0, 3, 0)); 375 err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1, 376 ARM64_SYS_REG(3, 0, 0, 3, 1)); 377 err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2, 378 ARM64_SYS_REG(3, 0, 0, 3, 2)); 379 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr2, 380 ARM64_SYS_REG(3, 0, 0, 3, 4)); 381 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr1, 382 ARM64_SYS_REG(3, 0, 0, 3, 5)); 383 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr5, 384 ARM64_SYS_REG(3, 0, 0, 3, 6)); 385 386 /* 387 * DBGDIDR is a bit complicated because the kernel doesn't 388 * provide an accessor for it in 64-bit mode, which is what this 389 * scratch VM is in, and there's no architected "64-bit sysreg 390 * which reads the same as the 32-bit register" the way there is 391 * for other ID registers. Instead we synthesize a value from the 392 * AArch64 ID_AA64DFR0, the same way the kernel code in 393 * arch/arm64/kvm/sys_regs.c:trap_dbgidr() does. 394 * We only do this if the CPU supports AArch32 at EL1. 395 */ 396 if (FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL1) >= 2) { 397 int wrps = FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, WRPS); 398 int brps = FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, BRPS); 399 int ctx_cmps = 400 FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS); 401 int version = 6; /* ARMv8 debug architecture */ 402 bool has_el3 = 403 !!FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL3); 404 uint32_t dbgdidr = 0; 405 406 dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, WRPS, wrps); 407 dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, BRPS, brps); 408 dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, CTX_CMPS, ctx_cmps); 409 dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, VERSION, version); 410 dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, NSUHD_IMP, has_el3); 411 dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, SE_IMP, has_el3); 412 dbgdidr |= (1 << 15); /* RES1 bit */ 413 ahcf->isar.dbgdidr = dbgdidr; 414 } 415 416 if (pmu_supported) { 417 /* PMCR_EL0 is only accessible if the vCPU has feature PMU_V3 */ 418 err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0, 419 ARM64_SYS_REG(3, 3, 9, 12, 0)); 420 } 421 422 if (sve_supported) { 423 /* 424 * There is a range of kernels between kernel commit 73433762fcae 425 * and f81cb2c3ad41 which have a bug where the kernel doesn't 426 * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has 427 * enabled SVE support, which resulted in an error rather than RAZ. 428 * So only read the register if we set KVM_ARM_VCPU_SVE above. 429 */ 430 err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, 431 ARM64_SYS_REG(3, 0, 0, 4, 4)); 432 } 433 } 434 435 kvm_arm_destroy_scratch_host_vcpu(fdarray); 436 437 if (err < 0) { 438 return false; 439 } 440 441 /* 442 * We can assume any KVM supporting CPU is at least a v8 443 * with VFPv4+Neon; this in turn implies most of the other 444 * feature bits. 445 */ 446 features |= 1ULL << ARM_FEATURE_V8; 447 features |= 1ULL << ARM_FEATURE_NEON; 448 features |= 1ULL << ARM_FEATURE_AARCH64; 449 features |= 1ULL << ARM_FEATURE_PMU; 450 features |= 1ULL << ARM_FEATURE_GENERIC_TIMER; 451 452 ahcf->features = features; 453 454 return true; 455 } 456 457 void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) 458 { 459 CPUARMState *env = &cpu->env; 460 461 if (!arm_host_cpu_features.dtb_compatible) { 462 if (!kvm_enabled() || 463 !kvm_arm_get_host_cpu_features(&arm_host_cpu_features)) { 464 /* We can't report this error yet, so flag that we need to 465 * in arm_cpu_realizefn(). 466 */ 467 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 468 cpu->host_cpu_probe_failed = true; 469 return; 470 } 471 } 472 473 cpu->kvm_target = arm_host_cpu_features.target; 474 cpu->dtb_compatible = arm_host_cpu_features.dtb_compatible; 475 cpu->isar = arm_host_cpu_features.isar; 476 env->features = arm_host_cpu_features.features; 477 } 478 479 static bool kvm_no_adjvtime_get(Object *obj, Error **errp) 480 { 481 return !ARM_CPU(obj)->kvm_adjvtime; 482 } 483 484 static void kvm_no_adjvtime_set(Object *obj, bool value, Error **errp) 485 { 486 ARM_CPU(obj)->kvm_adjvtime = !value; 487 } 488 489 static bool kvm_steal_time_get(Object *obj, Error **errp) 490 { 491 return ARM_CPU(obj)->kvm_steal_time != ON_OFF_AUTO_OFF; 492 } 493 494 static void kvm_steal_time_set(Object *obj, bool value, Error **errp) 495 { 496 ARM_CPU(obj)->kvm_steal_time = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; 497 } 498 499 /* KVM VCPU properties should be prefixed with "kvm-". */ 500 void kvm_arm_add_vcpu_properties(ARMCPU *cpu) 501 { 502 CPUARMState *env = &cpu->env; 503 Object *obj = OBJECT(cpu); 504 505 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { 506 cpu->kvm_adjvtime = true; 507 object_property_add_bool(obj, "kvm-no-adjvtime", kvm_no_adjvtime_get, 508 kvm_no_adjvtime_set); 509 object_property_set_description(obj, "kvm-no-adjvtime", 510 "Set on to disable the adjustment of " 511 "the virtual counter. VM stopped time " 512 "will be counted."); 513 } 514 515 cpu->kvm_steal_time = ON_OFF_AUTO_AUTO; 516 object_property_add_bool(obj, "kvm-steal-time", kvm_steal_time_get, 517 kvm_steal_time_set); 518 object_property_set_description(obj, "kvm-steal-time", 519 "Set off to disable KVM steal time."); 520 } 521 522 bool kvm_arm_pmu_supported(void) 523 { 524 return kvm_check_extension(kvm_state, KVM_CAP_ARM_PMU_V3); 525 } 526 527 int kvm_arm_get_max_vm_ipa_size(MachineState *ms, bool *fixed_ipa) 528 { 529 KVMState *s = KVM_STATE(ms->accelerator); 530 int ret; 531 532 ret = kvm_check_extension(s, KVM_CAP_ARM_VM_IPA_SIZE); 533 *fixed_ipa = ret <= 0; 534 535 return ret > 0 ? ret : 40; 536 } 537 538 int kvm_arch_get_default_type(MachineState *ms) 539 { 540 bool fixed_ipa; 541 int size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa); 542 return fixed_ipa ? 0 : size; 543 } 544 545 int kvm_arch_init(MachineState *ms, KVMState *s) 546 { 547 int ret = 0; 548 /* For ARM interrupt delivery is always asynchronous, 549 * whether we are using an in-kernel VGIC or not. 550 */ 551 kvm_async_interrupts_allowed = true; 552 553 /* 554 * PSCI wakes up secondary cores, so we always need to 555 * have vCPUs waiting in kernel space 556 */ 557 kvm_halt_in_kernel_allowed = true; 558 559 cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE); 560 561 /* Check whether user space can specify guest syndrome value */ 562 cap_has_inject_serror_esr = 563 kvm_check_extension(s, KVM_CAP_ARM_INJECT_SERROR_ESR); 564 565 if (ms->smp.cpus > 256 && 566 !kvm_check_extension(s, KVM_CAP_ARM_IRQ_LINE_LAYOUT_2)) { 567 error_report("Using more than 256 vcpus requires a host kernel " 568 "with KVM_CAP_ARM_IRQ_LINE_LAYOUT_2"); 569 ret = -EINVAL; 570 } 571 572 if (kvm_check_extension(s, KVM_CAP_ARM_NISV_TO_USER)) { 573 if (kvm_vm_enable_cap(s, KVM_CAP_ARM_NISV_TO_USER, 0)) { 574 error_report("Failed to enable KVM_CAP_ARM_NISV_TO_USER cap"); 575 } else { 576 /* Set status for supporting the external dabt injection */ 577 cap_has_inject_ext_dabt = kvm_check_extension(s, 578 KVM_CAP_ARM_INJECT_EXT_DABT); 579 } 580 } 581 582 if (s->kvm_eager_split_size) { 583 uint32_t sizes; 584 585 sizes = kvm_vm_check_extension(s, KVM_CAP_ARM_SUPPORTED_BLOCK_SIZES); 586 if (!sizes) { 587 s->kvm_eager_split_size = 0; 588 warn_report("Eager Page Split support not available"); 589 } else if (!(s->kvm_eager_split_size & sizes)) { 590 error_report("Eager Page Split requested chunk size not valid"); 591 ret = -EINVAL; 592 } else { 593 ret = kvm_vm_enable_cap(s, KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE, 0, 594 s->kvm_eager_split_size); 595 if (ret < 0) { 596 error_report("Enabling of Eager Page Split failed: %s", 597 strerror(-ret)); 598 } 599 } 600 } 601 602 max_hw_wps = kvm_check_extension(s, KVM_CAP_GUEST_DEBUG_HW_WPS); 603 hw_watchpoints = g_array_sized_new(true, true, 604 sizeof(HWWatchpoint), max_hw_wps); 605 606 max_hw_bps = kvm_check_extension(s, KVM_CAP_GUEST_DEBUG_HW_BPS); 607 hw_breakpoints = g_array_sized_new(true, true, 608 sizeof(HWBreakpoint), max_hw_bps); 609 610 return ret; 611 } 612 613 unsigned long kvm_arch_vcpu_id(CPUState *cpu) 614 { 615 return cpu->cpu_index; 616 } 617 618 /* We track all the KVM devices which need their memory addresses 619 * passing to the kernel in a list of these structures. 620 * When board init is complete we run through the list and 621 * tell the kernel the base addresses of the memory regions. 622 * We use a MemoryListener to track mapping and unmapping of 623 * the regions during board creation, so the board models don't 624 * need to do anything special for the KVM case. 625 * 626 * Sometimes the address must be OR'ed with some other fields 627 * (for example for KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION). 628 * @kda_addr_ormask aims at storing the value of those fields. 629 */ 630 typedef struct KVMDevice { 631 struct kvm_arm_device_addr kda; 632 struct kvm_device_attr kdattr; 633 uint64_t kda_addr_ormask; 634 MemoryRegion *mr; 635 QSLIST_ENTRY(KVMDevice) entries; 636 int dev_fd; 637 } KVMDevice; 638 639 static QSLIST_HEAD(, KVMDevice) kvm_devices_head; 640 641 static void kvm_arm_devlistener_add(MemoryListener *listener, 642 MemoryRegionSection *section) 643 { 644 KVMDevice *kd; 645 646 QSLIST_FOREACH(kd, &kvm_devices_head, entries) { 647 if (section->mr == kd->mr) { 648 kd->kda.addr = section->offset_within_address_space; 649 } 650 } 651 } 652 653 static void kvm_arm_devlistener_del(MemoryListener *listener, 654 MemoryRegionSection *section) 655 { 656 KVMDevice *kd; 657 658 QSLIST_FOREACH(kd, &kvm_devices_head, entries) { 659 if (section->mr == kd->mr) { 660 kd->kda.addr = -1; 661 } 662 } 663 } 664 665 static MemoryListener devlistener = { 666 .name = "kvm-arm", 667 .region_add = kvm_arm_devlistener_add, 668 .region_del = kvm_arm_devlistener_del, 669 .priority = MEMORY_LISTENER_PRIORITY_MIN, 670 }; 671 672 static void kvm_arm_set_device_addr(KVMDevice *kd) 673 { 674 struct kvm_device_attr *attr = &kd->kdattr; 675 int ret; 676 677 /* If the device control API is available and we have a device fd on the 678 * KVMDevice struct, let's use the newer API 679 */ 680 if (kd->dev_fd >= 0) { 681 uint64_t addr = kd->kda.addr; 682 683 addr |= kd->kda_addr_ormask; 684 attr->addr = (uintptr_t)&addr; 685 ret = kvm_device_ioctl(kd->dev_fd, KVM_SET_DEVICE_ATTR, attr); 686 } else { 687 ret = kvm_vm_ioctl(kvm_state, KVM_ARM_SET_DEVICE_ADDR, &kd->kda); 688 } 689 690 if (ret < 0) { 691 fprintf(stderr, "Failed to set device address: %s\n", 692 strerror(-ret)); 693 abort(); 694 } 695 } 696 697 static void kvm_arm_machine_init_done(Notifier *notifier, void *data) 698 { 699 KVMDevice *kd, *tkd; 700 701 QSLIST_FOREACH_SAFE(kd, &kvm_devices_head, entries, tkd) { 702 if (kd->kda.addr != -1) { 703 kvm_arm_set_device_addr(kd); 704 } 705 memory_region_unref(kd->mr); 706 QSLIST_REMOVE_HEAD(&kvm_devices_head, entries); 707 g_free(kd); 708 } 709 memory_listener_unregister(&devlistener); 710 } 711 712 static Notifier notify = { 713 .notify = kvm_arm_machine_init_done, 714 }; 715 716 void kvm_arm_register_device(MemoryRegion *mr, uint64_t devid, uint64_t group, 717 uint64_t attr, int dev_fd, uint64_t addr_ormask) 718 { 719 KVMDevice *kd; 720 721 if (!kvm_irqchip_in_kernel()) { 722 return; 723 } 724 725 if (QSLIST_EMPTY(&kvm_devices_head)) { 726 memory_listener_register(&devlistener, &address_space_memory); 727 qemu_add_machine_init_done_notifier(¬ify); 728 } 729 kd = g_new0(KVMDevice, 1); 730 kd->mr = mr; 731 kd->kda.id = devid; 732 kd->kda.addr = -1; 733 kd->kdattr.flags = 0; 734 kd->kdattr.group = group; 735 kd->kdattr.attr = attr; 736 kd->dev_fd = dev_fd; 737 kd->kda_addr_ormask = addr_ormask; 738 QSLIST_INSERT_HEAD(&kvm_devices_head, kd, entries); 739 memory_region_ref(kd->mr); 740 } 741 742 static int compare_u64(const void *a, const void *b) 743 { 744 if (*(uint64_t *)a > *(uint64_t *)b) { 745 return 1; 746 } 747 if (*(uint64_t *)a < *(uint64_t *)b) { 748 return -1; 749 } 750 return 0; 751 } 752 753 /* 754 * cpreg_values are sorted in ascending order by KVM register ID 755 * (see kvm_arm_init_cpreg_list). This allows us to cheaply find 756 * the storage for a KVM register by ID with a binary search. 757 */ 758 static uint64_t *kvm_arm_get_cpreg_ptr(ARMCPU *cpu, uint64_t regidx) 759 { 760 uint64_t *res; 761 762 res = bsearch(®idx, cpu->cpreg_indexes, cpu->cpreg_array_len, 763 sizeof(uint64_t), compare_u64); 764 assert(res); 765 766 return &cpu->cpreg_values[res - cpu->cpreg_indexes]; 767 } 768 769 /** 770 * kvm_arm_reg_syncs_via_cpreg_list: 771 * @regidx: KVM register index 772 * 773 * Return true if this KVM register should be synchronized via the 774 * cpreg list of arbitrary system registers, false if it is synchronized 775 * by hand using code in kvm_arch_get/put_registers(). 776 */ 777 static bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx) 778 { 779 switch (regidx & KVM_REG_ARM_COPROC_MASK) { 780 case KVM_REG_ARM_CORE: 781 case KVM_REG_ARM64_SVE: 782 return false; 783 default: 784 return true; 785 } 786 } 787 788 /** 789 * kvm_arm_init_cpreg_list: 790 * @cpu: ARMCPU 791 * 792 * Initialize the ARMCPU cpreg list according to the kernel's 793 * definition of what CPU registers it knows about (and throw away 794 * the previous TCG-created cpreg list). 795 * 796 * Returns: 0 if success, else < 0 error code 797 */ 798 static int kvm_arm_init_cpreg_list(ARMCPU *cpu) 799 { 800 struct kvm_reg_list rl; 801 struct kvm_reg_list *rlp; 802 int i, ret, arraylen; 803 CPUState *cs = CPU(cpu); 804 805 rl.n = 0; 806 ret = kvm_vcpu_ioctl(cs, KVM_GET_REG_LIST, &rl); 807 if (ret != -E2BIG) { 808 return ret; 809 } 810 rlp = g_malloc(sizeof(struct kvm_reg_list) + rl.n * sizeof(uint64_t)); 811 rlp->n = rl.n; 812 ret = kvm_vcpu_ioctl(cs, KVM_GET_REG_LIST, rlp); 813 if (ret) { 814 goto out; 815 } 816 /* Sort the list we get back from the kernel, since cpreg_tuples 817 * must be in strictly ascending order. 818 */ 819 qsort(&rlp->reg, rlp->n, sizeof(rlp->reg[0]), compare_u64); 820 821 for (i = 0, arraylen = 0; i < rlp->n; i++) { 822 if (!kvm_arm_reg_syncs_via_cpreg_list(rlp->reg[i])) { 823 continue; 824 } 825 switch (rlp->reg[i] & KVM_REG_SIZE_MASK) { 826 case KVM_REG_SIZE_U32: 827 case KVM_REG_SIZE_U64: 828 break; 829 default: 830 fprintf(stderr, "Can't handle size of register in kernel list\n"); 831 ret = -EINVAL; 832 goto out; 833 } 834 835 arraylen++; 836 } 837 838 cpu->cpreg_indexes = g_renew(uint64_t, cpu->cpreg_indexes, arraylen); 839 cpu->cpreg_values = g_renew(uint64_t, cpu->cpreg_values, arraylen); 840 cpu->cpreg_vmstate_indexes = g_renew(uint64_t, cpu->cpreg_vmstate_indexes, 841 arraylen); 842 cpu->cpreg_vmstate_values = g_renew(uint64_t, cpu->cpreg_vmstate_values, 843 arraylen); 844 cpu->cpreg_array_len = arraylen; 845 cpu->cpreg_vmstate_array_len = arraylen; 846 847 for (i = 0, arraylen = 0; i < rlp->n; i++) { 848 uint64_t regidx = rlp->reg[i]; 849 if (!kvm_arm_reg_syncs_via_cpreg_list(regidx)) { 850 continue; 851 } 852 cpu->cpreg_indexes[arraylen] = regidx; 853 arraylen++; 854 } 855 assert(cpu->cpreg_array_len == arraylen); 856 857 if (!write_kvmstate_to_list(cpu)) { 858 /* Shouldn't happen unless kernel is inconsistent about 859 * what registers exist. 860 */ 861 fprintf(stderr, "Initial read of kernel register state failed\n"); 862 ret = -EINVAL; 863 goto out; 864 } 865 866 out: 867 g_free(rlp); 868 return ret; 869 } 870 871 /** 872 * kvm_arm_cpreg_level: 873 * @regidx: KVM register index 874 * 875 * Return the level of this coprocessor/system register. Return value is 876 * either KVM_PUT_RUNTIME_STATE, KVM_PUT_RESET_STATE, or KVM_PUT_FULL_STATE. 877 */ 878 static int kvm_arm_cpreg_level(uint64_t regidx) 879 { 880 /* 881 * All system registers are assumed to be level KVM_PUT_RUNTIME_STATE. 882 * If a register should be written less often, you must add it here 883 * with a state of either KVM_PUT_RESET_STATE or KVM_PUT_FULL_STATE. 884 */ 885 switch (regidx) { 886 case KVM_REG_ARM_TIMER_CNT: 887 case KVM_REG_ARM_PTIMER_CNT: 888 return KVM_PUT_FULL_STATE; 889 } 890 return KVM_PUT_RUNTIME_STATE; 891 } 892 893 bool write_kvmstate_to_list(ARMCPU *cpu) 894 { 895 CPUState *cs = CPU(cpu); 896 int i; 897 bool ok = true; 898 899 for (i = 0; i < cpu->cpreg_array_len; i++) { 900 uint64_t regidx = cpu->cpreg_indexes[i]; 901 uint32_t v32; 902 int ret; 903 904 switch (regidx & KVM_REG_SIZE_MASK) { 905 case KVM_REG_SIZE_U32: 906 ret = kvm_get_one_reg(cs, regidx, &v32); 907 if (!ret) { 908 cpu->cpreg_values[i] = v32; 909 } 910 break; 911 case KVM_REG_SIZE_U64: 912 ret = kvm_get_one_reg(cs, regidx, cpu->cpreg_values + i); 913 break; 914 default: 915 g_assert_not_reached(); 916 } 917 if (ret) { 918 ok = false; 919 } 920 } 921 return ok; 922 } 923 924 bool write_list_to_kvmstate(ARMCPU *cpu, int level) 925 { 926 CPUState *cs = CPU(cpu); 927 int i; 928 bool ok = true; 929 930 for (i = 0; i < cpu->cpreg_array_len; i++) { 931 uint64_t regidx = cpu->cpreg_indexes[i]; 932 uint32_t v32; 933 int ret; 934 935 if (kvm_arm_cpreg_level(regidx) > level) { 936 continue; 937 } 938 939 switch (regidx & KVM_REG_SIZE_MASK) { 940 case KVM_REG_SIZE_U32: 941 v32 = cpu->cpreg_values[i]; 942 ret = kvm_set_one_reg(cs, regidx, &v32); 943 break; 944 case KVM_REG_SIZE_U64: 945 ret = kvm_set_one_reg(cs, regidx, cpu->cpreg_values + i); 946 break; 947 default: 948 g_assert_not_reached(); 949 } 950 if (ret) { 951 /* We might fail for "unknown register" and also for 952 * "you tried to set a register which is constant with 953 * a different value from what it actually contains". 954 */ 955 ok = false; 956 } 957 } 958 return ok; 959 } 960 961 void kvm_arm_cpu_pre_save(ARMCPU *cpu) 962 { 963 /* KVM virtual time adjustment */ 964 if (cpu->kvm_vtime_dirty) { 965 *kvm_arm_get_cpreg_ptr(cpu, KVM_REG_ARM_TIMER_CNT) = cpu->kvm_vtime; 966 } 967 } 968 969 void kvm_arm_cpu_post_load(ARMCPU *cpu) 970 { 971 /* KVM virtual time adjustment */ 972 if (cpu->kvm_adjvtime) { 973 cpu->kvm_vtime = *kvm_arm_get_cpreg_ptr(cpu, KVM_REG_ARM_TIMER_CNT); 974 cpu->kvm_vtime_dirty = true; 975 } 976 } 977 978 void kvm_arm_reset_vcpu(ARMCPU *cpu) 979 { 980 int ret; 981 982 /* Re-init VCPU so that all registers are set to 983 * their respective reset values. 984 */ 985 ret = kvm_arm_vcpu_init(CPU(cpu)); 986 if (ret < 0) { 987 fprintf(stderr, "kvm_arm_vcpu_init failed: %s\n", strerror(-ret)); 988 abort(); 989 } 990 if (!write_kvmstate_to_list(cpu)) { 991 fprintf(stderr, "write_kvmstate_to_list failed\n"); 992 abort(); 993 } 994 /* 995 * Sync the reset values also into the CPUState. This is necessary 996 * because the next thing we do will be a kvm_arch_put_registers() 997 * which will update the list values from the CPUState before copying 998 * the list values back to KVM. It's OK to ignore failure returns here 999 * for the same reason we do so in kvm_arch_get_registers(). 1000 */ 1001 write_list_to_cpustate(cpu); 1002 } 1003 1004 /* 1005 * Update KVM's MP_STATE based on what QEMU thinks it is 1006 */ 1007 static int kvm_arm_sync_mpstate_to_kvm(ARMCPU *cpu) 1008 { 1009 if (cap_has_mp_state) { 1010 struct kvm_mp_state mp_state = { 1011 .mp_state = (cpu->power_state == PSCI_OFF) ? 1012 KVM_MP_STATE_STOPPED : KVM_MP_STATE_RUNNABLE 1013 }; 1014 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state); 1015 } 1016 return 0; 1017 } 1018 1019 /* 1020 * Sync the KVM MP_STATE into QEMU 1021 */ 1022 static int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu) 1023 { 1024 if (cap_has_mp_state) { 1025 struct kvm_mp_state mp_state; 1026 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MP_STATE, &mp_state); 1027 if (ret) { 1028 return ret; 1029 } 1030 cpu->power_state = (mp_state.mp_state == KVM_MP_STATE_STOPPED) ? 1031 PSCI_OFF : PSCI_ON; 1032 } 1033 return 0; 1034 } 1035 1036 /** 1037 * kvm_arm_get_virtual_time: 1038 * @cs: CPUState 1039 * 1040 * Gets the VCPU's virtual counter and stores it in the KVM CPU state. 1041 */ 1042 static void kvm_arm_get_virtual_time(CPUState *cs) 1043 { 1044 ARMCPU *cpu = ARM_CPU(cs); 1045 int ret; 1046 1047 if (cpu->kvm_vtime_dirty) { 1048 return; 1049 } 1050 1051 ret = kvm_get_one_reg(cs, KVM_REG_ARM_TIMER_CNT, &cpu->kvm_vtime); 1052 if (ret) { 1053 error_report("Failed to get KVM_REG_ARM_TIMER_CNT"); 1054 abort(); 1055 } 1056 1057 cpu->kvm_vtime_dirty = true; 1058 } 1059 1060 /** 1061 * kvm_arm_put_virtual_time: 1062 * @cs: CPUState 1063 * 1064 * Sets the VCPU's virtual counter to the value stored in the KVM CPU state. 1065 */ 1066 static void kvm_arm_put_virtual_time(CPUState *cs) 1067 { 1068 ARMCPU *cpu = ARM_CPU(cs); 1069 int ret; 1070 1071 if (!cpu->kvm_vtime_dirty) { 1072 return; 1073 } 1074 1075 ret = kvm_set_one_reg(cs, KVM_REG_ARM_TIMER_CNT, &cpu->kvm_vtime); 1076 if (ret) { 1077 error_report("Failed to set KVM_REG_ARM_TIMER_CNT"); 1078 abort(); 1079 } 1080 1081 cpu->kvm_vtime_dirty = false; 1082 } 1083 1084 /** 1085 * kvm_put_vcpu_events: 1086 * @cpu: ARMCPU 1087 * 1088 * Put VCPU related state to kvm. 1089 * 1090 * Returns: 0 if success else < 0 error code 1091 */ 1092 static int kvm_put_vcpu_events(ARMCPU *cpu) 1093 { 1094 CPUARMState *env = &cpu->env; 1095 struct kvm_vcpu_events events; 1096 int ret; 1097 1098 if (!kvm_has_vcpu_events()) { 1099 return 0; 1100 } 1101 1102 memset(&events, 0, sizeof(events)); 1103 events.exception.serror_pending = env->serror.pending; 1104 1105 /* Inject SError to guest with specified syndrome if host kernel 1106 * supports it, otherwise inject SError without syndrome. 1107 */ 1108 if (cap_has_inject_serror_esr) { 1109 events.exception.serror_has_esr = env->serror.has_esr; 1110 events.exception.serror_esr = env->serror.esr; 1111 } 1112 1113 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events); 1114 if (ret) { 1115 error_report("failed to put vcpu events"); 1116 } 1117 1118 return ret; 1119 } 1120 1121 /** 1122 * kvm_get_vcpu_events: 1123 * @cpu: ARMCPU 1124 * 1125 * Get VCPU related state from kvm. 1126 * 1127 * Returns: 0 if success else < 0 error code 1128 */ 1129 static int kvm_get_vcpu_events(ARMCPU *cpu) 1130 { 1131 CPUARMState *env = &cpu->env; 1132 struct kvm_vcpu_events events; 1133 int ret; 1134 1135 if (!kvm_has_vcpu_events()) { 1136 return 0; 1137 } 1138 1139 memset(&events, 0, sizeof(events)); 1140 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events); 1141 if (ret) { 1142 error_report("failed to get vcpu events"); 1143 return ret; 1144 } 1145 1146 env->serror.pending = events.exception.serror_pending; 1147 env->serror.has_esr = events.exception.serror_has_esr; 1148 env->serror.esr = events.exception.serror_esr; 1149 1150 return 0; 1151 } 1152 1153 #define ARM64_REG_ESR_EL1 ARM64_SYS_REG(3, 0, 5, 2, 0) 1154 #define ARM64_REG_TCR_EL1 ARM64_SYS_REG(3, 0, 2, 0, 2) 1155 1156 /* 1157 * ESR_EL1 1158 * ISS encoding 1159 * AARCH64: DFSC, bits [5:0] 1160 * AARCH32: 1161 * TTBCR.EAE == 0 1162 * FS[4] - DFSR[10] 1163 * FS[3:0] - DFSR[3:0] 1164 * TTBCR.EAE == 1 1165 * FS, bits [5:0] 1166 */ 1167 #define ESR_DFSC(aarch64, lpae, v) \ 1168 ((aarch64 || (lpae)) ? ((v) & 0x3F) \ 1169 : (((v) >> 6) | ((v) & 0x1F))) 1170 1171 #define ESR_DFSC_EXTABT(aarch64, lpae) \ 1172 ((aarch64) ? 0x10 : (lpae) ? 0x10 : 0x8) 1173 1174 /** 1175 * kvm_arm_verify_ext_dabt_pending: 1176 * @cs: CPUState 1177 * 1178 * Verify the fault status code wrt the Ext DABT injection 1179 * 1180 * Returns: true if the fault status code is as expected, false otherwise 1181 */ 1182 static bool kvm_arm_verify_ext_dabt_pending(CPUState *cs) 1183 { 1184 uint64_t dfsr_val; 1185 1186 if (!kvm_get_one_reg(cs, ARM64_REG_ESR_EL1, &dfsr_val)) { 1187 ARMCPU *cpu = ARM_CPU(cs); 1188 CPUARMState *env = &cpu->env; 1189 int aarch64_mode = arm_feature(env, ARM_FEATURE_AARCH64); 1190 int lpae = 0; 1191 1192 if (!aarch64_mode) { 1193 uint64_t ttbcr; 1194 1195 if (!kvm_get_one_reg(cs, ARM64_REG_TCR_EL1, &ttbcr)) { 1196 lpae = arm_feature(env, ARM_FEATURE_LPAE) 1197 && (ttbcr & TTBCR_EAE); 1198 } 1199 } 1200 /* 1201 * The verification here is based on the DFSC bits 1202 * of the ESR_EL1 reg only 1203 */ 1204 return (ESR_DFSC(aarch64_mode, lpae, dfsr_val) == 1205 ESR_DFSC_EXTABT(aarch64_mode, lpae)); 1206 } 1207 return false; 1208 } 1209 1210 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) 1211 { 1212 ARMCPU *cpu = ARM_CPU(cs); 1213 CPUARMState *env = &cpu->env; 1214 1215 if (unlikely(env->ext_dabt_raised)) { 1216 /* 1217 * Verifying that the ext DABT has been properly injected, 1218 * otherwise risking indefinitely re-running the faulting instruction 1219 * Covering a very narrow case for kernels 5.5..5.5.4 1220 * when injected abort was misconfigured to be 1221 * an IMPLEMENTATION DEFINED exception (for 32-bit EL1) 1222 */ 1223 if (!arm_feature(env, ARM_FEATURE_AARCH64) && 1224 unlikely(!kvm_arm_verify_ext_dabt_pending(cs))) { 1225 1226 error_report("Data abort exception with no valid ISS generated by " 1227 "guest memory access. KVM unable to emulate faulting " 1228 "instruction. Failed to inject an external data abort " 1229 "into the guest."); 1230 abort(); 1231 } 1232 /* Clear the status */ 1233 env->ext_dabt_raised = 0; 1234 } 1235 } 1236 1237 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) 1238 { 1239 ARMCPU *cpu; 1240 uint32_t switched_level; 1241 1242 if (kvm_irqchip_in_kernel()) { 1243 /* 1244 * We only need to sync timer states with user-space interrupt 1245 * controllers, so return early and save cycles if we don't. 1246 */ 1247 return MEMTXATTRS_UNSPECIFIED; 1248 } 1249 1250 cpu = ARM_CPU(cs); 1251 1252 /* Synchronize our shadowed in-kernel device irq lines with the kvm ones */ 1253 if (run->s.regs.device_irq_level != cpu->device_irq_level) { 1254 switched_level = cpu->device_irq_level ^ run->s.regs.device_irq_level; 1255 1256 qemu_mutex_lock_iothread(); 1257 1258 if (switched_level & KVM_ARM_DEV_EL1_VTIMER) { 1259 qemu_set_irq(cpu->gt_timer_outputs[GTIMER_VIRT], 1260 !!(run->s.regs.device_irq_level & 1261 KVM_ARM_DEV_EL1_VTIMER)); 1262 switched_level &= ~KVM_ARM_DEV_EL1_VTIMER; 1263 } 1264 1265 if (switched_level & KVM_ARM_DEV_EL1_PTIMER) { 1266 qemu_set_irq(cpu->gt_timer_outputs[GTIMER_PHYS], 1267 !!(run->s.regs.device_irq_level & 1268 KVM_ARM_DEV_EL1_PTIMER)); 1269 switched_level &= ~KVM_ARM_DEV_EL1_PTIMER; 1270 } 1271 1272 if (switched_level & KVM_ARM_DEV_PMU) { 1273 qemu_set_irq(cpu->pmu_interrupt, 1274 !!(run->s.regs.device_irq_level & KVM_ARM_DEV_PMU)); 1275 switched_level &= ~KVM_ARM_DEV_PMU; 1276 } 1277 1278 if (switched_level) { 1279 qemu_log_mask(LOG_UNIMP, "%s: unhandled in-kernel device IRQ %x\n", 1280 __func__, switched_level); 1281 } 1282 1283 /* We also mark unknown levels as processed to not waste cycles */ 1284 cpu->device_irq_level = run->s.regs.device_irq_level; 1285 qemu_mutex_unlock_iothread(); 1286 } 1287 1288 return MEMTXATTRS_UNSPECIFIED; 1289 } 1290 1291 static void kvm_arm_vm_state_change(void *opaque, bool running, RunState state) 1292 { 1293 CPUState *cs = opaque; 1294 ARMCPU *cpu = ARM_CPU(cs); 1295 1296 if (running) { 1297 if (cpu->kvm_adjvtime) { 1298 kvm_arm_put_virtual_time(cs); 1299 } 1300 } else { 1301 if (cpu->kvm_adjvtime) { 1302 kvm_arm_get_virtual_time(cs); 1303 } 1304 } 1305 } 1306 1307 /** 1308 * kvm_arm_handle_dabt_nisv: 1309 * @cs: CPUState 1310 * @esr_iss: ISS encoding (limited) for the exception from Data Abort 1311 * ISV bit set to '0b0' -> no valid instruction syndrome 1312 * @fault_ipa: faulting address for the synchronous data abort 1313 * 1314 * Returns: 0 if the exception has been handled, < 0 otherwise 1315 */ 1316 static int kvm_arm_handle_dabt_nisv(CPUState *cs, uint64_t esr_iss, 1317 uint64_t fault_ipa) 1318 { 1319 ARMCPU *cpu = ARM_CPU(cs); 1320 CPUARMState *env = &cpu->env; 1321 /* 1322 * Request KVM to inject the external data abort into the guest 1323 */ 1324 if (cap_has_inject_ext_dabt) { 1325 struct kvm_vcpu_events events = { }; 1326 /* 1327 * The external data abort event will be handled immediately by KVM 1328 * using the address fault that triggered the exit on given VCPU. 1329 * Requesting injection of the external data abort does not rely 1330 * on any other VCPU state. Therefore, in this particular case, the VCPU 1331 * synchronization can be exceptionally skipped. 1332 */ 1333 events.exception.ext_dabt_pending = 1; 1334 /* KVM_CAP_ARM_INJECT_EXT_DABT implies KVM_CAP_VCPU_EVENTS */ 1335 if (!kvm_vcpu_ioctl(cs, KVM_SET_VCPU_EVENTS, &events)) { 1336 env->ext_dabt_raised = 1; 1337 return 0; 1338 } 1339 } else { 1340 error_report("Data abort exception triggered by guest memory access " 1341 "at physical address: 0x" TARGET_FMT_lx, 1342 (target_ulong)fault_ipa); 1343 error_printf("KVM unable to emulate faulting instruction.\n"); 1344 } 1345 return -1; 1346 } 1347 1348 /** 1349 * kvm_arm_handle_debug: 1350 * @cs: CPUState 1351 * @debug_exit: debug part of the KVM exit structure 1352 * 1353 * Returns: TRUE if the debug exception was handled. 1354 * 1355 * See v8 ARM ARM D7.2.27 ESR_ELx, Exception Syndrome Register 1356 * 1357 * To minimise translating between kernel and user-space the kernel 1358 * ABI just provides user-space with the full exception syndrome 1359 * register value to be decoded in QEMU. 1360 */ 1361 static bool kvm_arm_handle_debug(CPUState *cs, 1362 struct kvm_debug_exit_arch *debug_exit) 1363 { 1364 int hsr_ec = syn_get_ec(debug_exit->hsr); 1365 ARMCPU *cpu = ARM_CPU(cs); 1366 CPUARMState *env = &cpu->env; 1367 1368 /* Ensure PC is synchronised */ 1369 kvm_cpu_synchronize_state(cs); 1370 1371 switch (hsr_ec) { 1372 case EC_SOFTWARESTEP: 1373 if (cs->singlestep_enabled) { 1374 return true; 1375 } else { 1376 /* 1377 * The kernel should have suppressed the guest's ability to 1378 * single step at this point so something has gone wrong. 1379 */ 1380 error_report("%s: guest single-step while debugging unsupported" 1381 " (%"PRIx64", %"PRIx32")", 1382 __func__, env->pc, debug_exit->hsr); 1383 return false; 1384 } 1385 break; 1386 case EC_AA64_BKPT: 1387 if (kvm_find_sw_breakpoint(cs, env->pc)) { 1388 return true; 1389 } 1390 break; 1391 case EC_BREAKPOINT: 1392 if (find_hw_breakpoint(cs, env->pc)) { 1393 return true; 1394 } 1395 break; 1396 case EC_WATCHPOINT: 1397 { 1398 CPUWatchpoint *wp = find_hw_watchpoint(cs, debug_exit->far); 1399 if (wp) { 1400 cs->watchpoint_hit = wp; 1401 return true; 1402 } 1403 break; 1404 } 1405 default: 1406 error_report("%s: unhandled debug exit (%"PRIx32", %"PRIx64")", 1407 __func__, debug_exit->hsr, env->pc); 1408 } 1409 1410 /* If we are not handling the debug exception it must belong to 1411 * the guest. Let's re-use the existing TCG interrupt code to set 1412 * everything up properly. 1413 */ 1414 cs->exception_index = EXCP_BKPT; 1415 env->exception.syndrome = debug_exit->hsr; 1416 env->exception.vaddress = debug_exit->far; 1417 env->exception.target_el = 1; 1418 qemu_mutex_lock_iothread(); 1419 arm_cpu_do_interrupt(cs); 1420 qemu_mutex_unlock_iothread(); 1421 1422 return false; 1423 } 1424 1425 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 1426 { 1427 int ret = 0; 1428 1429 switch (run->exit_reason) { 1430 case KVM_EXIT_DEBUG: 1431 if (kvm_arm_handle_debug(cs, &run->debug.arch)) { 1432 ret = EXCP_DEBUG; 1433 } /* otherwise return to guest */ 1434 break; 1435 case KVM_EXIT_ARM_NISV: 1436 /* External DABT with no valid iss to decode */ 1437 ret = kvm_arm_handle_dabt_nisv(cs, run->arm_nisv.esr_iss, 1438 run->arm_nisv.fault_ipa); 1439 break; 1440 default: 1441 qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n", 1442 __func__, run->exit_reason); 1443 break; 1444 } 1445 return ret; 1446 } 1447 1448 bool kvm_arch_stop_on_emulation_error(CPUState *cs) 1449 { 1450 return true; 1451 } 1452 1453 int kvm_arch_process_async_events(CPUState *cs) 1454 { 1455 return 0; 1456 } 1457 1458 /** 1459 * kvm_arm_hw_debug_active: 1460 * @cs: CPU State 1461 * 1462 * Return: TRUE if any hardware breakpoints in use. 1463 */ 1464 static bool kvm_arm_hw_debug_active(CPUState *cs) 1465 { 1466 return ((cur_hw_wps > 0) || (cur_hw_bps > 0)); 1467 } 1468 1469 /** 1470 * kvm_arm_copy_hw_debug_data: 1471 * @ptr: kvm_guest_debug_arch structure 1472 * 1473 * Copy the architecture specific debug registers into the 1474 * kvm_guest_debug ioctl structure. 1475 */ 1476 static void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr) 1477 { 1478 int i; 1479 memset(ptr, 0, sizeof(struct kvm_guest_debug_arch)); 1480 1481 for (i = 0; i < max_hw_wps; i++) { 1482 HWWatchpoint *wp = get_hw_wp(i); 1483 ptr->dbg_wcr[i] = wp->wcr; 1484 ptr->dbg_wvr[i] = wp->wvr; 1485 } 1486 for (i = 0; i < max_hw_bps; i++) { 1487 HWBreakpoint *bp = get_hw_bp(i); 1488 ptr->dbg_bcr[i] = bp->bcr; 1489 ptr->dbg_bvr[i] = bp->bvr; 1490 } 1491 } 1492 1493 void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg) 1494 { 1495 if (kvm_sw_breakpoints_active(cs)) { 1496 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP; 1497 } 1498 if (kvm_arm_hw_debug_active(cs)) { 1499 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW; 1500 kvm_arm_copy_hw_debug_data(&dbg->arch); 1501 } 1502 } 1503 1504 void kvm_arch_init_irq_routing(KVMState *s) 1505 { 1506 } 1507 1508 int kvm_arch_irqchip_create(KVMState *s) 1509 { 1510 if (kvm_kernel_irqchip_split()) { 1511 error_report("-machine kernel_irqchip=split is not supported on ARM."); 1512 exit(1); 1513 } 1514 1515 /* If we can create the VGIC using the newer device control API, we 1516 * let the device do this when it initializes itself, otherwise we 1517 * fall back to the old API */ 1518 return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL); 1519 } 1520 1521 int kvm_arm_vgic_probe(void) 1522 { 1523 int val = 0; 1524 1525 if (kvm_create_device(kvm_state, 1526 KVM_DEV_TYPE_ARM_VGIC_V3, true) == 0) { 1527 val |= KVM_ARM_VGIC_V3; 1528 } 1529 if (kvm_create_device(kvm_state, 1530 KVM_DEV_TYPE_ARM_VGIC_V2, true) == 0) { 1531 val |= KVM_ARM_VGIC_V2; 1532 } 1533 return val; 1534 } 1535 1536 int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level) 1537 { 1538 int kvm_irq = (irqtype << KVM_ARM_IRQ_TYPE_SHIFT) | irq; 1539 int cpu_idx1 = cpu % 256; 1540 int cpu_idx2 = cpu / 256; 1541 1542 kvm_irq |= (cpu_idx1 << KVM_ARM_IRQ_VCPU_SHIFT) | 1543 (cpu_idx2 << KVM_ARM_IRQ_VCPU2_SHIFT); 1544 1545 return kvm_set_irq(kvm_state, kvm_irq, !!level); 1546 } 1547 1548 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 1549 uint64_t address, uint32_t data, PCIDevice *dev) 1550 { 1551 AddressSpace *as = pci_device_iommu_address_space(dev); 1552 hwaddr xlat, len, doorbell_gpa; 1553 MemoryRegionSection mrs; 1554 MemoryRegion *mr; 1555 1556 if (as == &address_space_memory) { 1557 return 0; 1558 } 1559 1560 /* MSI doorbell address is translated by an IOMMU */ 1561 1562 RCU_READ_LOCK_GUARD(); 1563 1564 mr = address_space_translate(as, address, &xlat, &len, true, 1565 MEMTXATTRS_UNSPECIFIED); 1566 1567 if (!mr) { 1568 return 1; 1569 } 1570 1571 mrs = memory_region_find(mr, xlat, 1); 1572 1573 if (!mrs.mr) { 1574 return 1; 1575 } 1576 1577 doorbell_gpa = mrs.offset_within_address_space; 1578 memory_region_unref(mrs.mr); 1579 1580 route->u.msi.address_lo = doorbell_gpa; 1581 route->u.msi.address_hi = doorbell_gpa >> 32; 1582 1583 trace_kvm_arm_fixup_msi_route(address, doorbell_gpa); 1584 1585 return 0; 1586 } 1587 1588 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 1589 int vector, PCIDevice *dev) 1590 { 1591 return 0; 1592 } 1593 1594 int kvm_arch_release_virq_post(int virq) 1595 { 1596 return 0; 1597 } 1598 1599 int kvm_arch_msi_data_to_gsi(uint32_t data) 1600 { 1601 return (data - 32) & 0xffff; 1602 } 1603 1604 bool kvm_arch_cpu_check_are_resettable(void) 1605 { 1606 return true; 1607 } 1608 1609 static void kvm_arch_get_eager_split_size(Object *obj, Visitor *v, 1610 const char *name, void *opaque, 1611 Error **errp) 1612 { 1613 KVMState *s = KVM_STATE(obj); 1614 uint64_t value = s->kvm_eager_split_size; 1615 1616 visit_type_size(v, name, &value, errp); 1617 } 1618 1619 static void kvm_arch_set_eager_split_size(Object *obj, Visitor *v, 1620 const char *name, void *opaque, 1621 Error **errp) 1622 { 1623 KVMState *s = KVM_STATE(obj); 1624 uint64_t value; 1625 1626 if (s->fd != -1) { 1627 error_setg(errp, "Unable to set early-split-size after KVM has been initialized"); 1628 return; 1629 } 1630 1631 if (!visit_type_size(v, name, &value, errp)) { 1632 return; 1633 } 1634 1635 if (value && !is_power_of_2(value)) { 1636 error_setg(errp, "early-split-size must be a power of two"); 1637 return; 1638 } 1639 1640 s->kvm_eager_split_size = value; 1641 } 1642 1643 void kvm_arch_accel_class_init(ObjectClass *oc) 1644 { 1645 object_class_property_add(oc, "eager-split-size", "size", 1646 kvm_arch_get_eager_split_size, 1647 kvm_arch_set_eager_split_size, NULL, NULL); 1648 1649 object_class_property_set_description(oc, "eager-split-size", 1650 "Eager Page Split chunk size for hugepages. (default: 0, disabled)"); 1651 } 1652 1653 int kvm_arch_insert_hw_breakpoint(vaddr addr, vaddr len, int type) 1654 { 1655 switch (type) { 1656 case GDB_BREAKPOINT_HW: 1657 return insert_hw_breakpoint(addr); 1658 break; 1659 case GDB_WATCHPOINT_READ: 1660 case GDB_WATCHPOINT_WRITE: 1661 case GDB_WATCHPOINT_ACCESS: 1662 return insert_hw_watchpoint(addr, len, type); 1663 default: 1664 return -ENOSYS; 1665 } 1666 } 1667 1668 int kvm_arch_remove_hw_breakpoint(vaddr addr, vaddr len, int type) 1669 { 1670 switch (type) { 1671 case GDB_BREAKPOINT_HW: 1672 return delete_hw_breakpoint(addr); 1673 case GDB_WATCHPOINT_READ: 1674 case GDB_WATCHPOINT_WRITE: 1675 case GDB_WATCHPOINT_ACCESS: 1676 return delete_hw_watchpoint(addr, len, type); 1677 default: 1678 return -ENOSYS; 1679 } 1680 } 1681 1682 void kvm_arch_remove_all_hw_breakpoints(void) 1683 { 1684 if (cur_hw_wps > 0) { 1685 g_array_remove_range(hw_watchpoints, 0, cur_hw_wps); 1686 } 1687 if (cur_hw_bps > 0) { 1688 g_array_remove_range(hw_breakpoints, 0, cur_hw_bps); 1689 } 1690 } 1691 1692 static bool kvm_arm_set_device_attr(CPUState *cs, struct kvm_device_attr *attr, 1693 const char *name) 1694 { 1695 int err; 1696 1697 err = kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, attr); 1698 if (err != 0) { 1699 error_report("%s: KVM_HAS_DEVICE_ATTR: %s", name, strerror(-err)); 1700 return false; 1701 } 1702 1703 err = kvm_vcpu_ioctl(cs, KVM_SET_DEVICE_ATTR, attr); 1704 if (err != 0) { 1705 error_report("%s: KVM_SET_DEVICE_ATTR: %s", name, strerror(-err)); 1706 return false; 1707 } 1708 1709 return true; 1710 } 1711 1712 void kvm_arm_pmu_init(CPUState *cs) 1713 { 1714 struct kvm_device_attr attr = { 1715 .group = KVM_ARM_VCPU_PMU_V3_CTRL, 1716 .attr = KVM_ARM_VCPU_PMU_V3_INIT, 1717 }; 1718 1719 if (!ARM_CPU(cs)->has_pmu) { 1720 return; 1721 } 1722 if (!kvm_arm_set_device_attr(cs, &attr, "PMU")) { 1723 error_report("failed to init PMU"); 1724 abort(); 1725 } 1726 } 1727 1728 void kvm_arm_pmu_set_irq(CPUState *cs, int irq) 1729 { 1730 struct kvm_device_attr attr = { 1731 .group = KVM_ARM_VCPU_PMU_V3_CTRL, 1732 .addr = (intptr_t)&irq, 1733 .attr = KVM_ARM_VCPU_PMU_V3_IRQ, 1734 }; 1735 1736 if (!ARM_CPU(cs)->has_pmu) { 1737 return; 1738 } 1739 if (!kvm_arm_set_device_attr(cs, &attr, "PMU")) { 1740 error_report("failed to set irq for PMU"); 1741 abort(); 1742 } 1743 } 1744 1745 void kvm_arm_pvtime_init(CPUState *cs, uint64_t ipa) 1746 { 1747 struct kvm_device_attr attr = { 1748 .group = KVM_ARM_VCPU_PVTIME_CTRL, 1749 .attr = KVM_ARM_VCPU_PVTIME_IPA, 1750 .addr = (uint64_t)&ipa, 1751 }; 1752 1753 if (ARM_CPU(cs)->kvm_steal_time == ON_OFF_AUTO_OFF) { 1754 return; 1755 } 1756 if (!kvm_arm_set_device_attr(cs, &attr, "PVTIME IPA")) { 1757 error_report("failed to init PVTIME IPA"); 1758 abort(); 1759 } 1760 } 1761 1762 void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp) 1763 { 1764 bool has_steal_time = kvm_check_extension(kvm_state, KVM_CAP_STEAL_TIME); 1765 1766 if (cpu->kvm_steal_time == ON_OFF_AUTO_AUTO) { 1767 if (!has_steal_time || !arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1768 cpu->kvm_steal_time = ON_OFF_AUTO_OFF; 1769 } else { 1770 cpu->kvm_steal_time = ON_OFF_AUTO_ON; 1771 } 1772 } else if (cpu->kvm_steal_time == ON_OFF_AUTO_ON) { 1773 if (!has_steal_time) { 1774 error_setg(errp, "'kvm-steal-time' cannot be enabled " 1775 "on this host"); 1776 return; 1777 } else if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1778 /* 1779 * DEN0057A chapter 2 says "This specification only covers 1780 * systems in which the Execution state of the hypervisor 1781 * as well as EL1 of virtual machines is AArch64.". And, 1782 * to ensure that, the smc/hvc calls are only specified as 1783 * smc64/hvc64. 1784 */ 1785 error_setg(errp, "'kvm-steal-time' cannot be enabled " 1786 "for AArch32 guests"); 1787 return; 1788 } 1789 } 1790 } 1791 1792 bool kvm_arm_aarch32_supported(void) 1793 { 1794 return kvm_check_extension(kvm_state, KVM_CAP_ARM_EL1_32BIT); 1795 } 1796 1797 bool kvm_arm_sve_supported(void) 1798 { 1799 return kvm_check_extension(kvm_state, KVM_CAP_ARM_SVE); 1800 } 1801 1802 QEMU_BUILD_BUG_ON(KVM_ARM64_SVE_VQ_MIN != 1); 1803 1804 uint32_t kvm_arm_sve_get_vls(CPUState *cs) 1805 { 1806 /* Only call this function if kvm_arm_sve_supported() returns true. */ 1807 static uint64_t vls[KVM_ARM64_SVE_VLS_WORDS]; 1808 static bool probed; 1809 uint32_t vq = 0; 1810 int i; 1811 1812 /* 1813 * KVM ensures all host CPUs support the same set of vector lengths. 1814 * So we only need to create the scratch VCPUs once and then cache 1815 * the results. 1816 */ 1817 if (!probed) { 1818 struct kvm_vcpu_init init = { 1819 .target = -1, 1820 .features[0] = (1 << KVM_ARM_VCPU_SVE), 1821 }; 1822 struct kvm_one_reg reg = { 1823 .id = KVM_REG_ARM64_SVE_VLS, 1824 .addr = (uint64_t)&vls[0], 1825 }; 1826 int fdarray[3], ret; 1827 1828 probed = true; 1829 1830 if (!kvm_arm_create_scratch_host_vcpu(NULL, fdarray, &init)) { 1831 error_report("failed to create scratch VCPU with SVE enabled"); 1832 abort(); 1833 } 1834 ret = ioctl(fdarray[2], KVM_GET_ONE_REG, ®); 1835 kvm_arm_destroy_scratch_host_vcpu(fdarray); 1836 if (ret) { 1837 error_report("failed to get KVM_REG_ARM64_SVE_VLS: %s", 1838 strerror(errno)); 1839 abort(); 1840 } 1841 1842 for (i = KVM_ARM64_SVE_VLS_WORDS - 1; i >= 0; --i) { 1843 if (vls[i]) { 1844 vq = 64 - clz64(vls[i]) + i * 64; 1845 break; 1846 } 1847 } 1848 if (vq > ARM_MAX_VQ) { 1849 warn_report("KVM supports vector lengths larger than " 1850 "QEMU can enable"); 1851 vls[0] &= MAKE_64BIT_MASK(0, ARM_MAX_VQ); 1852 } 1853 } 1854 1855 return vls[0]; 1856 } 1857 1858 static int kvm_arm_sve_set_vls(ARMCPU *cpu) 1859 { 1860 uint64_t vls[KVM_ARM64_SVE_VLS_WORDS] = { cpu->sve_vq.map }; 1861 1862 assert(cpu->sve_max_vq <= KVM_ARM64_SVE_VQ_MAX); 1863 1864 return kvm_set_one_reg(CPU(cpu), KVM_REG_ARM64_SVE_VLS, &vls[0]); 1865 } 1866 1867 #define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5 1868 1869 int kvm_arch_init_vcpu(CPUState *cs) 1870 { 1871 int ret; 1872 uint64_t mpidr; 1873 ARMCPU *cpu = ARM_CPU(cs); 1874 CPUARMState *env = &cpu->env; 1875 uint64_t psciver; 1876 1877 if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE || 1878 !object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU)) { 1879 error_report("KVM is not supported for this guest CPU type"); 1880 return -EINVAL; 1881 } 1882 1883 qemu_add_vm_change_state_handler(kvm_arm_vm_state_change, cs); 1884 1885 /* Determine init features for this CPU */ 1886 memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features)); 1887 if (cs->start_powered_off) { 1888 cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_POWER_OFF; 1889 } 1890 if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PSCI_0_2)) { 1891 cpu->psci_version = QEMU_PSCI_VERSION_0_2; 1892 cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2; 1893 } 1894 if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1895 cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_EL1_32BIT; 1896 } 1897 if (!kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PMU_V3)) { 1898 cpu->has_pmu = false; 1899 } 1900 if (cpu->has_pmu) { 1901 cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PMU_V3; 1902 } else { 1903 env->features &= ~(1ULL << ARM_FEATURE_PMU); 1904 } 1905 if (cpu_isar_feature(aa64_sve, cpu)) { 1906 assert(kvm_arm_sve_supported()); 1907 cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_SVE; 1908 } 1909 if (cpu_isar_feature(aa64_pauth, cpu)) { 1910 cpu->kvm_init_features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | 1911 1 << KVM_ARM_VCPU_PTRAUTH_GENERIC); 1912 } 1913 1914 /* Do KVM_ARM_VCPU_INIT ioctl */ 1915 ret = kvm_arm_vcpu_init(cs); 1916 if (ret) { 1917 return ret; 1918 } 1919 1920 if (cpu_isar_feature(aa64_sve, cpu)) { 1921 ret = kvm_arm_sve_set_vls(cpu); 1922 if (ret) { 1923 return ret; 1924 } 1925 ret = kvm_arm_vcpu_finalize(cs, KVM_ARM_VCPU_SVE); 1926 if (ret) { 1927 return ret; 1928 } 1929 } 1930 1931 /* 1932 * KVM reports the exact PSCI version it is implementing via a 1933 * special sysreg. If it is present, use its contents to determine 1934 * what to report to the guest in the dtb (it is the PSCI version, 1935 * in the same 15-bits major 16-bits minor format that PSCI_VERSION 1936 * returns). 1937 */ 1938 if (!kvm_get_one_reg(cs, KVM_REG_ARM_PSCI_VERSION, &psciver)) { 1939 cpu->psci_version = psciver; 1940 } 1941 1942 /* 1943 * When KVM is in use, PSCI is emulated in-kernel and not by qemu. 1944 * Currently KVM has its own idea about MPIDR assignment, so we 1945 * override our defaults with what we get from KVM. 1946 */ 1947 ret = kvm_get_one_reg(cs, ARM64_SYS_REG(ARM_CPU_ID_MPIDR), &mpidr); 1948 if (ret) { 1949 return ret; 1950 } 1951 cpu->mp_affinity = mpidr & ARM64_AFFINITY_MASK; 1952 1953 return kvm_arm_init_cpreg_list(cpu); 1954 } 1955 1956 int kvm_arch_destroy_vcpu(CPUState *cs) 1957 { 1958 return 0; 1959 } 1960 1961 /* Callers must hold the iothread mutex lock */ 1962 static void kvm_inject_arm_sea(CPUState *c) 1963 { 1964 ARMCPU *cpu = ARM_CPU(c); 1965 CPUARMState *env = &cpu->env; 1966 uint32_t esr; 1967 bool same_el; 1968 1969 c->exception_index = EXCP_DATA_ABORT; 1970 env->exception.target_el = 1; 1971 1972 /* 1973 * Set the DFSC to synchronous external abort and set FnV to not valid, 1974 * this will tell guest the FAR_ELx is UNKNOWN for this abort. 1975 */ 1976 same_el = arm_current_el(env) == env->exception.target_el; 1977 esr = syn_data_abort_no_iss(same_el, 1, 0, 0, 0, 0, 0x10); 1978 1979 env->exception.syndrome = esr; 1980 1981 arm_cpu_do_interrupt(c); 1982 } 1983 1984 #define AARCH64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \ 1985 KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x)) 1986 1987 #define AARCH64_SIMD_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U128 | \ 1988 KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x)) 1989 1990 #define AARCH64_SIMD_CTRL_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U32 | \ 1991 KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x)) 1992 1993 static int kvm_arch_put_fpsimd(CPUState *cs) 1994 { 1995 CPUARMState *env = &ARM_CPU(cs)->env; 1996 int i, ret; 1997 1998 for (i = 0; i < 32; i++) { 1999 uint64_t *q = aa64_vfp_qreg(env, i); 2000 #if HOST_BIG_ENDIAN 2001 uint64_t fp_val[2] = { q[1], q[0] }; 2002 ret = kvm_set_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]), 2003 fp_val); 2004 #else 2005 ret = kvm_set_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]), q); 2006 #endif 2007 if (ret) { 2008 return ret; 2009 } 2010 } 2011 2012 return 0; 2013 } 2014 2015 /* 2016 * KVM SVE registers come in slices where ZREGs have a slice size of 2048 bits 2017 * and PREGS and the FFR have a slice size of 256 bits. However we simply hard 2018 * code the slice index to zero for now as it's unlikely we'll need more than 2019 * one slice for quite some time. 2020 */ 2021 static int kvm_arch_put_sve(CPUState *cs) 2022 { 2023 ARMCPU *cpu = ARM_CPU(cs); 2024 CPUARMState *env = &cpu->env; 2025 uint64_t tmp[ARM_MAX_VQ * 2]; 2026 uint64_t *r; 2027 int n, ret; 2028 2029 for (n = 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) { 2030 r = sve_bswap64(tmp, &env->vfp.zregs[n].d[0], cpu->sve_max_vq * 2); 2031 ret = kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_ZREG(n, 0), r); 2032 if (ret) { 2033 return ret; 2034 } 2035 } 2036 2037 for (n = 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) { 2038 r = sve_bswap64(tmp, r = &env->vfp.pregs[n].p[0], 2039 DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); 2040 ret = kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_PREG(n, 0), r); 2041 if (ret) { 2042 return ret; 2043 } 2044 } 2045 2046 r = sve_bswap64(tmp, &env->vfp.pregs[FFR_PRED_NUM].p[0], 2047 DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); 2048 ret = kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_FFR(0), r); 2049 if (ret) { 2050 return ret; 2051 } 2052 2053 return 0; 2054 } 2055 2056 int kvm_arch_put_registers(CPUState *cs, int level) 2057 { 2058 uint64_t val; 2059 uint32_t fpr; 2060 int i, ret; 2061 unsigned int el; 2062 2063 ARMCPU *cpu = ARM_CPU(cs); 2064 CPUARMState *env = &cpu->env; 2065 2066 /* If we are in AArch32 mode then we need to copy the AArch32 regs to the 2067 * AArch64 registers before pushing them out to 64-bit KVM. 2068 */ 2069 if (!is_a64(env)) { 2070 aarch64_sync_32_to_64(env); 2071 } 2072 2073 for (i = 0; i < 31; i++) { 2074 ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.regs[i]), 2075 &env->xregs[i]); 2076 if (ret) { 2077 return ret; 2078 } 2079 } 2080 2081 /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the 2082 * QEMU side we keep the current SP in xregs[31] as well. 2083 */ 2084 aarch64_save_sp(env, 1); 2085 2086 ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.sp), &env->sp_el[0]); 2087 if (ret) { 2088 return ret; 2089 } 2090 2091 ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(sp_el1), &env->sp_el[1]); 2092 if (ret) { 2093 return ret; 2094 } 2095 2096 /* Note that KVM thinks pstate is 64 bit but we use a uint32_t */ 2097 if (is_a64(env)) { 2098 val = pstate_read(env); 2099 } else { 2100 val = cpsr_read(env); 2101 } 2102 ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.pstate), &val); 2103 if (ret) { 2104 return ret; 2105 } 2106 2107 ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.pc), &env->pc); 2108 if (ret) { 2109 return ret; 2110 } 2111 2112 ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(elr_el1), &env->elr_el[1]); 2113 if (ret) { 2114 return ret; 2115 } 2116 2117 /* Saved Program State Registers 2118 * 2119 * Before we restore from the banked_spsr[] array we need to 2120 * ensure that any modifications to env->spsr are correctly 2121 * reflected in the banks. 2122 */ 2123 el = arm_current_el(env); 2124 if (el > 0 && !is_a64(env)) { 2125 i = bank_number(env->uncached_cpsr & CPSR_M); 2126 env->banked_spsr[i] = env->spsr; 2127 } 2128 2129 /* KVM 0-4 map to QEMU banks 1-5 */ 2130 for (i = 0; i < KVM_NR_SPSR; i++) { 2131 ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(spsr[i]), 2132 &env->banked_spsr[i + 1]); 2133 if (ret) { 2134 return ret; 2135 } 2136 } 2137 2138 if (cpu_isar_feature(aa64_sve, cpu)) { 2139 ret = kvm_arch_put_sve(cs); 2140 } else { 2141 ret = kvm_arch_put_fpsimd(cs); 2142 } 2143 if (ret) { 2144 return ret; 2145 } 2146 2147 fpr = vfp_get_fpsr(env); 2148 ret = kvm_set_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpsr), &fpr); 2149 if (ret) { 2150 return ret; 2151 } 2152 2153 fpr = vfp_get_fpcr(env); 2154 ret = kvm_set_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpcr), &fpr); 2155 if (ret) { 2156 return ret; 2157 } 2158 2159 write_cpustate_to_list(cpu, true); 2160 2161 if (!write_list_to_kvmstate(cpu, level)) { 2162 return -EINVAL; 2163 } 2164 2165 /* 2166 * Setting VCPU events should be triggered after syncing the registers 2167 * to avoid overwriting potential changes made by KVM upon calling 2168 * KVM_SET_VCPU_EVENTS ioctl 2169 */ 2170 ret = kvm_put_vcpu_events(cpu); 2171 if (ret) { 2172 return ret; 2173 } 2174 2175 return kvm_arm_sync_mpstate_to_kvm(cpu); 2176 } 2177 2178 static int kvm_arch_get_fpsimd(CPUState *cs) 2179 { 2180 CPUARMState *env = &ARM_CPU(cs)->env; 2181 int i, ret; 2182 2183 for (i = 0; i < 32; i++) { 2184 uint64_t *q = aa64_vfp_qreg(env, i); 2185 ret = kvm_get_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]), q); 2186 if (ret) { 2187 return ret; 2188 } else { 2189 #if HOST_BIG_ENDIAN 2190 uint64_t t; 2191 t = q[0], q[0] = q[1], q[1] = t; 2192 #endif 2193 } 2194 } 2195 2196 return 0; 2197 } 2198 2199 /* 2200 * KVM SVE registers come in slices where ZREGs have a slice size of 2048 bits 2201 * and PREGS and the FFR have a slice size of 256 bits. However we simply hard 2202 * code the slice index to zero for now as it's unlikely we'll need more than 2203 * one slice for quite some time. 2204 */ 2205 static int kvm_arch_get_sve(CPUState *cs) 2206 { 2207 ARMCPU *cpu = ARM_CPU(cs); 2208 CPUARMState *env = &cpu->env; 2209 uint64_t *r; 2210 int n, ret; 2211 2212 for (n = 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) { 2213 r = &env->vfp.zregs[n].d[0]; 2214 ret = kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_ZREG(n, 0), r); 2215 if (ret) { 2216 return ret; 2217 } 2218 sve_bswap64(r, r, cpu->sve_max_vq * 2); 2219 } 2220 2221 for (n = 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) { 2222 r = &env->vfp.pregs[n].p[0]; 2223 ret = kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_PREG(n, 0), r); 2224 if (ret) { 2225 return ret; 2226 } 2227 sve_bswap64(r, r, DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); 2228 } 2229 2230 r = &env->vfp.pregs[FFR_PRED_NUM].p[0]; 2231 ret = kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_FFR(0), r); 2232 if (ret) { 2233 return ret; 2234 } 2235 sve_bswap64(r, r, DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); 2236 2237 return 0; 2238 } 2239 2240 int kvm_arch_get_registers(CPUState *cs) 2241 { 2242 uint64_t val; 2243 unsigned int el; 2244 uint32_t fpr; 2245 int i, ret; 2246 2247 ARMCPU *cpu = ARM_CPU(cs); 2248 CPUARMState *env = &cpu->env; 2249 2250 for (i = 0; i < 31; i++) { 2251 ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.regs[i]), 2252 &env->xregs[i]); 2253 if (ret) { 2254 return ret; 2255 } 2256 } 2257 2258 ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.sp), &env->sp_el[0]); 2259 if (ret) { 2260 return ret; 2261 } 2262 2263 ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(sp_el1), &env->sp_el[1]); 2264 if (ret) { 2265 return ret; 2266 } 2267 2268 ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.pstate), &val); 2269 if (ret) { 2270 return ret; 2271 } 2272 2273 env->aarch64 = ((val & PSTATE_nRW) == 0); 2274 if (is_a64(env)) { 2275 pstate_write(env, val); 2276 } else { 2277 cpsr_write(env, val, 0xffffffff, CPSRWriteRaw); 2278 } 2279 2280 /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the 2281 * QEMU side we keep the current SP in xregs[31] as well. 2282 */ 2283 aarch64_restore_sp(env, 1); 2284 2285 ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.pc), &env->pc); 2286 if (ret) { 2287 return ret; 2288 } 2289 2290 /* If we are in AArch32 mode then we need to sync the AArch32 regs with the 2291 * incoming AArch64 regs received from 64-bit KVM. 2292 * We must perform this after all of the registers have been acquired from 2293 * the kernel. 2294 */ 2295 if (!is_a64(env)) { 2296 aarch64_sync_64_to_32(env); 2297 } 2298 2299 ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(elr_el1), &env->elr_el[1]); 2300 if (ret) { 2301 return ret; 2302 } 2303 2304 /* Fetch the SPSR registers 2305 * 2306 * KVM SPSRs 0-4 map to QEMU banks 1-5 2307 */ 2308 for (i = 0; i < KVM_NR_SPSR; i++) { 2309 ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(spsr[i]), 2310 &env->banked_spsr[i + 1]); 2311 if (ret) { 2312 return ret; 2313 } 2314 } 2315 2316 el = arm_current_el(env); 2317 if (el > 0 && !is_a64(env)) { 2318 i = bank_number(env->uncached_cpsr & CPSR_M); 2319 env->spsr = env->banked_spsr[i]; 2320 } 2321 2322 if (cpu_isar_feature(aa64_sve, cpu)) { 2323 ret = kvm_arch_get_sve(cs); 2324 } else { 2325 ret = kvm_arch_get_fpsimd(cs); 2326 } 2327 if (ret) { 2328 return ret; 2329 } 2330 2331 ret = kvm_get_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpsr), &fpr); 2332 if (ret) { 2333 return ret; 2334 } 2335 vfp_set_fpsr(env, fpr); 2336 2337 ret = kvm_get_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpcr), &fpr); 2338 if (ret) { 2339 return ret; 2340 } 2341 vfp_set_fpcr(env, fpr); 2342 2343 ret = kvm_get_vcpu_events(cpu); 2344 if (ret) { 2345 return ret; 2346 } 2347 2348 if (!write_kvmstate_to_list(cpu)) { 2349 return -EINVAL; 2350 } 2351 /* Note that it's OK to have registers which aren't in CPUState, 2352 * so we can ignore a failure return here. 2353 */ 2354 write_list_to_cpustate(cpu); 2355 2356 ret = kvm_arm_sync_mpstate_to_qemu(cpu); 2357 2358 /* TODO: other registers */ 2359 return ret; 2360 } 2361 2362 void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr) 2363 { 2364 ram_addr_t ram_addr; 2365 hwaddr paddr; 2366 2367 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO); 2368 2369 if (acpi_ghes_present() && addr) { 2370 ram_addr = qemu_ram_addr_from_host(addr); 2371 if (ram_addr != RAM_ADDR_INVALID && 2372 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) { 2373 kvm_hwpoison_page_add(ram_addr); 2374 /* 2375 * If this is a BUS_MCEERR_AR, we know we have been called 2376 * synchronously from the vCPU thread, so we can easily 2377 * synchronize the state and inject an error. 2378 * 2379 * TODO: we currently don't tell the guest at all about 2380 * BUS_MCEERR_AO. In that case we might either be being 2381 * called synchronously from the vCPU thread, or a bit 2382 * later from the main thread, so doing the injection of 2383 * the error would be more complicated. 2384 */ 2385 if (code == BUS_MCEERR_AR) { 2386 kvm_cpu_synchronize_state(c); 2387 if (!acpi_ghes_record_errors(ACPI_HEST_SRC_ID_SEA, paddr)) { 2388 kvm_inject_arm_sea(c); 2389 } else { 2390 error_report("failed to record the error"); 2391 abort(); 2392 } 2393 } 2394 return; 2395 } 2396 if (code == BUS_MCEERR_AO) { 2397 error_report("Hardware memory error at addr %p for memory used by " 2398 "QEMU itself instead of guest system!", addr); 2399 } 2400 } 2401 2402 if (code == BUS_MCEERR_AR) { 2403 error_report("Hardware memory error!"); 2404 exit(1); 2405 } 2406 } 2407 2408 /* C6.6.29 BRK instruction */ 2409 static const uint32_t brk_insn = 0xd4200000; 2410 2411 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 2412 { 2413 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 0) || 2414 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk_insn, 4, 1)) { 2415 return -EINVAL; 2416 } 2417 return 0; 2418 } 2419 2420 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 2421 { 2422 static uint32_t brk; 2423 2424 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk, 4, 0) || 2425 brk != brk_insn || 2426 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 1)) { 2427 return -EINVAL; 2428 } 2429 return 0; 2430 } 2431