xref: /qemu/target/arm/tcg/translate.h (revision 4642250e)
1f0984d40SFabiano Rosas #ifndef TARGET_ARM_TRANSLATE_H
2f0984d40SFabiano Rosas #define TARGET_ARM_TRANSLATE_H
3f0984d40SFabiano Rosas 
45d05e5a1SRichard Henderson #include "cpu.h"
55d05e5a1SRichard Henderson #include "tcg/tcg-op.h"
65d05e5a1SRichard Henderson #include "tcg/tcg-op-gvec.h"
71f17f91dSRichard Henderson #include "exec/exec-all.h"
8f0984d40SFabiano Rosas #include "exec/translator.h"
9a46f42d9SRichard Henderson #include "exec/helper-gen.h"
10f0984d40SFabiano Rosas #include "internals.h"
115a534314SPeter Maydell #include "cpu-features.h"
12f0984d40SFabiano Rosas 
13f0984d40SFabiano Rosas /* internal defines */
14f0984d40SFabiano Rosas 
15f0984d40SFabiano Rosas /*
16f0984d40SFabiano Rosas  * Save pc_save across a branch, so that we may restore the value from
17f0984d40SFabiano Rosas  * before the branch at the point the label is emitted.
18f0984d40SFabiano Rosas  */
19f0984d40SFabiano Rosas typedef struct DisasLabel {
20f0984d40SFabiano Rosas     TCGLabel *label;
21f0984d40SFabiano Rosas     target_ulong pc_save;
22f0984d40SFabiano Rosas } DisasLabel;
23f0984d40SFabiano Rosas 
24f0984d40SFabiano Rosas typedef struct DisasContext {
25f0984d40SFabiano Rosas     DisasContextBase base;
26f0984d40SFabiano Rosas     const ARMISARegisters *isar;
27f0984d40SFabiano Rosas 
28f0984d40SFabiano Rosas     /* The address of the current instruction being translated. */
29f0984d40SFabiano Rosas     target_ulong pc_curr;
30f0984d40SFabiano Rosas     /*
3103a648c4SAnton Johansson      * For CF_PCREL, the full value of cpu_pc is not known
32f0984d40SFabiano Rosas      * (although the page offset is known).  For convenience, the
33f0984d40SFabiano Rosas      * translation loop uses the full virtual address that triggered
34f0984d40SFabiano Rosas      * the translation, from base.pc_start through pc_curr.
35f0984d40SFabiano Rosas      * For efficiency, we do not update cpu_pc for every instruction.
36f0984d40SFabiano Rosas      * Instead, pc_save has the value of pc_curr at the time of the
37f0984d40SFabiano Rosas      * last update to cpu_pc, which allows us to compute the addend
38f0984d40SFabiano Rosas      * needed to bring cpu_pc current: pc_curr - pc_save.
39f0984d40SFabiano Rosas      * If cpu_pc now contains the destination of an indirect branch,
40f0984d40SFabiano Rosas      * pc_save contains -1 to indicate that relative updates are no
41f0984d40SFabiano Rosas      * longer possible.
42f0984d40SFabiano Rosas      */
43f0984d40SFabiano Rosas     target_ulong pc_save;
44f0984d40SFabiano Rosas     target_ulong page_start;
45f0984d40SFabiano Rosas     uint32_t insn;
46f0984d40SFabiano Rosas     /* Nonzero if this instruction has been conditionally skipped.  */
47f0984d40SFabiano Rosas     int condjmp;
48f0984d40SFabiano Rosas     /* The label that will be jumped to when the instruction is skipped.  */
49f0984d40SFabiano Rosas     DisasLabel condlabel;
50f0984d40SFabiano Rosas     /* Thumb-2 conditional execution bits.  */
51f0984d40SFabiano Rosas     int condexec_mask;
52f0984d40SFabiano Rosas     int condexec_cond;
53f0984d40SFabiano Rosas     /* M-profile ECI/ICI exception-continuable instruction state */
54f0984d40SFabiano Rosas     int eci;
55f0984d40SFabiano Rosas     /*
56f0984d40SFabiano Rosas      * trans_ functions for insns which are continuable should set this true
57f0984d40SFabiano Rosas      * after decode (ie after any UNDEF checks)
58f0984d40SFabiano Rosas      */
59f0984d40SFabiano Rosas     bool eci_handled;
60f0984d40SFabiano Rosas     int sctlr_b;
61f0984d40SFabiano Rosas     MemOp be_data;
62f0984d40SFabiano Rosas #if !defined(CONFIG_USER_ONLY)
63f0984d40SFabiano Rosas     int user;
64f0984d40SFabiano Rosas #endif
65f0984d40SFabiano Rosas     ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */
66f0984d40SFabiano Rosas     uint8_t tbii;      /* TBI1|TBI0 for insns */
67f0984d40SFabiano Rosas     uint8_t tbid;      /* TBI1|TBI0 for data */
68f0984d40SFabiano Rosas     uint8_t tcma;      /* TCMA1|TCMA0 for MTE */
69f0984d40SFabiano Rosas     bool ns;        /* Use non-secure CPREG bank on access */
70f0984d40SFabiano Rosas     int fp_excp_el; /* FP exception EL or 0 if enabled */
71f0984d40SFabiano Rosas     int sve_excp_el; /* SVE exception EL or 0 if enabled */
72f0984d40SFabiano Rosas     int sme_excp_el; /* SME exception EL or 0 if enabled */
73f0984d40SFabiano Rosas     int vl;          /* current vector length in bytes */
74f0984d40SFabiano Rosas     int svl;         /* current streaming vector length in bytes */
75f0984d40SFabiano Rosas     bool vfp_enabled; /* FP enabled via FPSCR.EN */
76f0984d40SFabiano Rosas     int vec_len;
77f0984d40SFabiano Rosas     int vec_stride;
78f0984d40SFabiano Rosas     bool v7m_handler_mode;
79f0984d40SFabiano Rosas     bool v8m_secure; /* true if v8M and we're in Secure mode */
80f0984d40SFabiano Rosas     bool v8m_stackcheck; /* true if we need to perform v8M stack limit checks */
81f0984d40SFabiano Rosas     bool v8m_fpccr_s_wrong; /* true if v8M FPCCR.S != v8m_secure */
82f0984d40SFabiano Rosas     bool v7m_new_fp_ctxt_needed; /* ASPEN set but no active FP context */
83f0984d40SFabiano Rosas     bool v7m_lspact; /* FPCCR.LSPACT set */
84f0984d40SFabiano Rosas     /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI
85f0984d40SFabiano Rosas      * so that top level loop can generate correct syndrome information.
86f0984d40SFabiano Rosas      */
87f0984d40SFabiano Rosas     uint32_t svc_imm;
88f0984d40SFabiano Rosas     int current_el;
89f0984d40SFabiano Rosas     GHashTable *cp_regs;
90f0984d40SFabiano Rosas     uint64_t features; /* CPU features bits */
91f0984d40SFabiano Rosas     bool aarch64;
92f0984d40SFabiano Rosas     bool thumb;
93e452ca5aSRichard Henderson     bool lse2;
94f0984d40SFabiano Rosas     /* Because unallocated encodings generate different exception syndrome
95f0984d40SFabiano Rosas      * information from traps due to FP being disabled, we can't do a single
96f0984d40SFabiano Rosas      * "is fp access disabled" check at a high level in the decode tree.
97f0984d40SFabiano Rosas      * To help in catching bugs where the access check was forgotten in some
98f0984d40SFabiano Rosas      * code path, we set this flag when the access check is done, and assert
99f0984d40SFabiano Rosas      * that it is set at the point where we actually touch the FP regs.
100f0984d40SFabiano Rosas      */
101f0984d40SFabiano Rosas     bool fp_access_checked;
102f0984d40SFabiano Rosas     bool sve_access_checked;
103f0984d40SFabiano Rosas     /* ARMv8 single-step state (this is distinct from the QEMU gdbstub
104f0984d40SFabiano Rosas      * single-step support).
105f0984d40SFabiano Rosas      */
106f0984d40SFabiano Rosas     bool ss_active;
107f0984d40SFabiano Rosas     bool pstate_ss;
108f0984d40SFabiano Rosas     /* True if the insn just emitted was a load-exclusive instruction
109f0984d40SFabiano Rosas      * (necessary for syndrome information for single step exceptions),
110f0984d40SFabiano Rosas      * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*.
111f0984d40SFabiano Rosas      */
112f0984d40SFabiano Rosas     bool is_ldex;
113f0984d40SFabiano Rosas     /* True if AccType_UNPRIV should be used for LDTR et al */
114f0984d40SFabiano Rosas     bool unpriv;
115f0984d40SFabiano Rosas     /* True if v8.3-PAuth is active.  */
116f0984d40SFabiano Rosas     bool pauth_active;
117179e9a3bSPeter Maydell     /* True if v8.5-MTE access to tags is enabled; index with is_unpriv.  */
118179e9a3bSPeter Maydell     bool ata[2];
119f0984d40SFabiano Rosas     /* True if v8.5-MTE tag checks affect the PE; index with is_unpriv.  */
120f0984d40SFabiano Rosas     bool mte_active[2];
121f0984d40SFabiano Rosas     /* True with v8.5-BTI and SCTLR_ELx.BT* set.  */
122f0984d40SFabiano Rosas     bool bt;
123f0984d40SFabiano Rosas     /* True if any CP15 access is trapped by HSTR_EL2 */
124f0984d40SFabiano Rosas     bool hstr_active;
125f0984d40SFabiano Rosas     /* True if memory operations require alignment */
126f0984d40SFabiano Rosas     bool align_mem;
127f0984d40SFabiano Rosas     /* True if PSTATE.IL is set */
128f0984d40SFabiano Rosas     bool pstate_il;
129f0984d40SFabiano Rosas     /* True if PSTATE.SM is set. */
130f0984d40SFabiano Rosas     bool pstate_sm;
131f0984d40SFabiano Rosas     /* True if PSTATE.ZA is set. */
132f0984d40SFabiano Rosas     bool pstate_za;
133f0984d40SFabiano Rosas     /* True if non-streaming insns should raise an SME Streaming exception. */
134f0984d40SFabiano Rosas     bool sme_trap_nonstreaming;
135f0984d40SFabiano Rosas     /* True if the current instruction is non-streaming. */
136f0984d40SFabiano Rosas     bool is_nonstreaming;
137f0984d40SFabiano Rosas     /* True if MVE insns are definitely not predicated by VPR or LTPSIZE */
138f0984d40SFabiano Rosas     bool mve_no_pred;
139f0984d40SFabiano Rosas     /* True if fine-grained traps are active */
140f0984d40SFabiano Rosas     bool fgt_active;
141f0984d40SFabiano Rosas     /* True if fine-grained trap on SVC is enabled */
142f0984d40SFabiano Rosas     bool fgt_svc;
143e37e98b7SPeter Maydell     /* True if a trap on ERET is enabled (FGT or NV) */
144e37e98b7SPeter Maydell     bool trap_eret;
14583f624d9SRichard Henderson     /* True if FEAT_LSE2 SCTLR_ELx.nAA is set */
14683f624d9SRichard Henderson     bool naa;
14767d10fc4SPeter Maydell     /* True if FEAT_NV HCR_EL2.NV is enabled */
14867d10fc4SPeter Maydell     bool nv;
149c35da11dSPeter Maydell     /* True if NV enabled and HCR_EL2.NV1 is set */
150c35da11dSPeter Maydell     bool nv1;
151c35da11dSPeter Maydell     /* True if NV enabled and HCR_EL2.NV2 is set */
152c35da11dSPeter Maydell     bool nv2;
153daf9b4a0SPeter Maydell     /* True if NV2 enabled and NV2 RAM accesses use EL2&0 translation regime */
154daf9b4a0SPeter Maydell     bool nv2_mem_e20;
155daf9b4a0SPeter Maydell     /* True if NV2 enabled and NV2 RAM accesses are big-endian */
156daf9b4a0SPeter Maydell     bool nv2_mem_be;
157f0984d40SFabiano Rosas     /*
158f0984d40SFabiano Rosas      * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI.
159f0984d40SFabiano Rosas      *  < 0, set by the current instruction.
160f0984d40SFabiano Rosas      */
161f0984d40SFabiano Rosas     int8_t btype;
162f0984d40SFabiano Rosas     /* A copy of cpu->dcz_blocksize. */
163f0984d40SFabiano Rosas     uint8_t dcz_blocksize;
164851ec6ebSRichard Henderson     /* A copy of cpu->gm_blocksize. */
165851ec6ebSRichard Henderson     uint8_t gm_blocksize;
166f0984d40SFabiano Rosas     /* True if this page is guarded.  */
167f0984d40SFabiano Rosas     bool guarded_page;
168*4642250eSRichard Henderson     /* True if the current insn_start has been updated. */
169*4642250eSRichard Henderson     bool insn_start_updated;
170f0984d40SFabiano Rosas     /* Bottom two bits of XScale c15_cpar coprocessor access control reg */
171f0984d40SFabiano Rosas     int c15_cpar;
172daf9b4a0SPeter Maydell     /* Offset from VNCR_EL2 when FEAT_NV2 redirects this reg to memory */
173daf9b4a0SPeter Maydell     uint32_t nv2_redirect_offset;
174f0984d40SFabiano Rosas } DisasContext;
175f0984d40SFabiano Rosas 
176f0984d40SFabiano Rosas typedef struct DisasCompare {
177f0984d40SFabiano Rosas     TCGCond cond;
178f0984d40SFabiano Rosas     TCGv_i32 value;
179f0984d40SFabiano Rosas } DisasCompare;
180f0984d40SFabiano Rosas 
181f0984d40SFabiano Rosas /* Share the TCG temporaries common between 32 and 64 bit modes.  */
182f0984d40SFabiano Rosas extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
183f0984d40SFabiano Rosas extern TCGv_i64 cpu_exclusive_addr;
184f0984d40SFabiano Rosas extern TCGv_i64 cpu_exclusive_val;
185f0984d40SFabiano Rosas 
186f0984d40SFabiano Rosas /*
187f0984d40SFabiano Rosas  * Constant expanders for the decoders.
188f0984d40SFabiano Rosas  */
189f0984d40SFabiano Rosas 
negate(DisasContext * s,int x)190f0984d40SFabiano Rosas static inline int negate(DisasContext *s, int x)
191f0984d40SFabiano Rosas {
192f0984d40SFabiano Rosas     return -x;
193f0984d40SFabiano Rosas }
194f0984d40SFabiano Rosas 
plus_1(DisasContext * s,int x)195f0984d40SFabiano Rosas static inline int plus_1(DisasContext *s, int x)
196f0984d40SFabiano Rosas {
197f0984d40SFabiano Rosas     return x + 1;
198f0984d40SFabiano Rosas }
199f0984d40SFabiano Rosas 
plus_2(DisasContext * s,int x)200f0984d40SFabiano Rosas static inline int plus_2(DisasContext *s, int x)
201f0984d40SFabiano Rosas {
202f0984d40SFabiano Rosas     return x + 2;
203f0984d40SFabiano Rosas }
204f0984d40SFabiano Rosas 
plus_12(DisasContext * s,int x)205f0984d40SFabiano Rosas static inline int plus_12(DisasContext *s, int x)
206f0984d40SFabiano Rosas {
207f0984d40SFabiano Rosas     return x + 12;
208f0984d40SFabiano Rosas }
209f0984d40SFabiano Rosas 
times_2(DisasContext * s,int x)210f0984d40SFabiano Rosas static inline int times_2(DisasContext *s, int x)
211f0984d40SFabiano Rosas {
212f0984d40SFabiano Rosas     return x * 2;
213f0984d40SFabiano Rosas }
214f0984d40SFabiano Rosas 
times_4(DisasContext * s,int x)215f0984d40SFabiano Rosas static inline int times_4(DisasContext *s, int x)
216f0984d40SFabiano Rosas {
217f0984d40SFabiano Rosas     return x * 4;
218f0984d40SFabiano Rosas }
219f0984d40SFabiano Rosas 
times_8(DisasContext * s,int x)2205722fc47SPeter Maydell static inline int times_8(DisasContext *s, int x)
2215722fc47SPeter Maydell {
2225722fc47SPeter Maydell     return x * 8;
2235722fc47SPeter Maydell }
2245722fc47SPeter Maydell 
times_2_plus_1(DisasContext * s,int x)225f0984d40SFabiano Rosas static inline int times_2_plus_1(DisasContext *s, int x)
226f0984d40SFabiano Rosas {
227f0984d40SFabiano Rosas     return x * 2 + 1;
228f0984d40SFabiano Rosas }
229f0984d40SFabiano Rosas 
rsub_64(DisasContext * s,int x)230f0984d40SFabiano Rosas static inline int rsub_64(DisasContext *s, int x)
231f0984d40SFabiano Rosas {
232f0984d40SFabiano Rosas     return 64 - x;
233f0984d40SFabiano Rosas }
234f0984d40SFabiano Rosas 
rsub_32(DisasContext * s,int x)235f0984d40SFabiano Rosas static inline int rsub_32(DisasContext *s, int x)
236f0984d40SFabiano Rosas {
237f0984d40SFabiano Rosas     return 32 - x;
238f0984d40SFabiano Rosas }
239f0984d40SFabiano Rosas 
rsub_16(DisasContext * s,int x)240f0984d40SFabiano Rosas static inline int rsub_16(DisasContext *s, int x)
241f0984d40SFabiano Rosas {
242f0984d40SFabiano Rosas     return 16 - x;
243f0984d40SFabiano Rosas }
244f0984d40SFabiano Rosas 
rsub_8(DisasContext * s,int x)245f0984d40SFabiano Rosas static inline int rsub_8(DisasContext *s, int x)
246f0984d40SFabiano Rosas {
247f0984d40SFabiano Rosas     return 8 - x;
248f0984d40SFabiano Rosas }
249f0984d40SFabiano Rosas 
shl_12(DisasContext * s,int x)2503ce7b5eaSRichard Henderson static inline int shl_12(DisasContext *s, int x)
2513ce7b5eaSRichard Henderson {
2523ce7b5eaSRichard Henderson     return x << 12;
2533ce7b5eaSRichard Henderson }
2543ce7b5eaSRichard Henderson 
neon_3same_fp_size(DisasContext * s,int x)255f0984d40SFabiano Rosas static inline int neon_3same_fp_size(DisasContext *s, int x)
256f0984d40SFabiano Rosas {
257f0984d40SFabiano Rosas     /* Convert 0==fp32, 1==fp16 into a MO_* value */
258f0984d40SFabiano Rosas     return MO_32 - x;
259f0984d40SFabiano Rosas }
260f0984d40SFabiano Rosas 
arm_dc_feature(DisasContext * dc,int feature)261f0984d40SFabiano Rosas static inline int arm_dc_feature(DisasContext *dc, int feature)
262f0984d40SFabiano Rosas {
263f0984d40SFabiano Rosas     return (dc->features & (1ULL << feature)) != 0;
264f0984d40SFabiano Rosas }
265f0984d40SFabiano Rosas 
get_mem_index(DisasContext * s)266f0984d40SFabiano Rosas static inline int get_mem_index(DisasContext *s)
267f0984d40SFabiano Rosas {
268f0984d40SFabiano Rosas     return arm_to_core_mmu_idx(s->mmu_idx);
269f0984d40SFabiano Rosas }
270f0984d40SFabiano Rosas 
disas_set_insn_syndrome(DisasContext * s,uint32_t syn)271f0984d40SFabiano Rosas static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
272f0984d40SFabiano Rosas {
273f0984d40SFabiano Rosas     /* We don't need to save all of the syndrome so we mask and shift
274f0984d40SFabiano Rosas      * out unneeded bits to help the sleb128 encoder do a better job.
275f0984d40SFabiano Rosas      */
276f0984d40SFabiano Rosas     syn &= ARM_INSN_START_WORD2_MASK;
277f0984d40SFabiano Rosas     syn >>= ARM_INSN_START_WORD2_SHIFT;
278f0984d40SFabiano Rosas 
279*4642250eSRichard Henderson     /* Check for multiple updates.  */
280*4642250eSRichard Henderson     assert(!s->insn_start_updated);
281*4642250eSRichard Henderson     s->insn_start_updated = true;
282*4642250eSRichard Henderson     tcg_set_insn_start_param(s->base.insn_start, 2, syn);
283f0984d40SFabiano Rosas }
284f0984d40SFabiano Rosas 
curr_insn_len(DisasContext * s)285f0984d40SFabiano Rosas static inline int curr_insn_len(DisasContext *s)
286f0984d40SFabiano Rosas {
287f0984d40SFabiano Rosas     return s->base.pc_next - s->pc_curr;
288f0984d40SFabiano Rosas }
289f0984d40SFabiano Rosas 
290f0984d40SFabiano Rosas /* is_jmp field values */
291f0984d40SFabiano Rosas #define DISAS_JUMP      DISAS_TARGET_0 /* only pc was modified dynamically */
292f0984d40SFabiano Rosas /* CPU state was modified dynamically; exit to main loop for interrupts. */
293f0984d40SFabiano Rosas #define DISAS_UPDATE_EXIT  DISAS_TARGET_1
294f0984d40SFabiano Rosas /* These instructions trap after executing, so the A32/T32 decoder must
295f0984d40SFabiano Rosas  * defer them until after the conditional execution state has been updated.
296f0984d40SFabiano Rosas  * WFI also needs special handling when single-stepping.
297f0984d40SFabiano Rosas  */
298f0984d40SFabiano Rosas #define DISAS_WFI       DISAS_TARGET_2
299f0984d40SFabiano Rosas #define DISAS_SWI       DISAS_TARGET_3
300f0984d40SFabiano Rosas /* WFE */
301f0984d40SFabiano Rosas #define DISAS_WFE       DISAS_TARGET_4
302f0984d40SFabiano Rosas #define DISAS_HVC       DISAS_TARGET_5
303f0984d40SFabiano Rosas #define DISAS_SMC       DISAS_TARGET_6
304f0984d40SFabiano Rosas #define DISAS_YIELD     DISAS_TARGET_7
305f0984d40SFabiano Rosas /* M profile branch which might be an exception return (and so needs
306f0984d40SFabiano Rosas  * custom end-of-TB code)
307f0984d40SFabiano Rosas  */
308f0984d40SFabiano Rosas #define DISAS_BX_EXCRET DISAS_TARGET_8
309f0984d40SFabiano Rosas /*
310f0984d40SFabiano Rosas  * For instructions which want an immediate exit to the main loop, as opposed
311f0984d40SFabiano Rosas  * to attempting to use lookup_and_goto_ptr.  Unlike DISAS_UPDATE_EXIT, this
312f0984d40SFabiano Rosas  * doesn't write the PC on exiting the translation loop so you need to ensure
313f0984d40SFabiano Rosas  * something (gen_a64_update_pc or runtime helper) has done so before we reach
314f0984d40SFabiano Rosas  * return from cpu_tb_exec.
315f0984d40SFabiano Rosas  */
316f0984d40SFabiano Rosas #define DISAS_EXIT      DISAS_TARGET_9
317f0984d40SFabiano Rosas /* CPU state was modified dynamically; no need to exit, but do not chain. */
318f0984d40SFabiano Rosas #define DISAS_UPDATE_NOCHAIN  DISAS_TARGET_10
319f0984d40SFabiano Rosas 
320f0984d40SFabiano Rosas #ifdef TARGET_AARCH64
321f0984d40SFabiano Rosas void a64_translate_init(void);
322f0984d40SFabiano Rosas void gen_a64_update_pc(DisasContext *s, target_long diff);
323f0984d40SFabiano Rosas extern const TranslatorOps aarch64_translator_ops;
324f0984d40SFabiano Rosas #else
a64_translate_init(void)325f0984d40SFabiano Rosas static inline void a64_translate_init(void)
326f0984d40SFabiano Rosas {
327f0984d40SFabiano Rosas }
328f0984d40SFabiano Rosas 
gen_a64_update_pc(DisasContext * s,target_long diff)329f0984d40SFabiano Rosas static inline void gen_a64_update_pc(DisasContext *s, target_long diff)
330f0984d40SFabiano Rosas {
331f0984d40SFabiano Rosas }
332f0984d40SFabiano Rosas #endif
333f0984d40SFabiano Rosas 
334f0984d40SFabiano Rosas void arm_test_cc(DisasCompare *cmp, int cc);
335f0984d40SFabiano Rosas void arm_jump_cc(DisasCompare *cmp, TCGLabel *label);
336f0984d40SFabiano Rosas void arm_gen_test_cc(int cc, TCGLabel *label);
337f0984d40SFabiano Rosas MemOp pow2_align(unsigned i);
338f0984d40SFabiano Rosas void unallocated_encoding(DisasContext *s);
339f0984d40SFabiano Rosas void gen_exception_insn_el(DisasContext *s, target_long pc_diff, int excp,
340f0984d40SFabiano Rosas                            uint32_t syn, uint32_t target_el);
341f0984d40SFabiano Rosas void gen_exception_insn(DisasContext *s, target_long pc_diff,
342f0984d40SFabiano Rosas                         int excp, uint32_t syn);
343f0984d40SFabiano Rosas 
344f0984d40SFabiano Rosas /* Return state of Alternate Half-precision flag, caller frees result */
get_ahp_flag(void)345f0984d40SFabiano Rosas static inline TCGv_i32 get_ahp_flag(void)
346f0984d40SFabiano Rosas {
347f0984d40SFabiano Rosas     TCGv_i32 ret = tcg_temp_new_i32();
348f0984d40SFabiano Rosas 
349ad75a51eSRichard Henderson     tcg_gen_ld_i32(ret, tcg_env,
350f0984d40SFabiano Rosas                    offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPSCR]));
351f0984d40SFabiano Rosas     tcg_gen_extract_i32(ret, ret, 26, 1);
352f0984d40SFabiano Rosas 
353f0984d40SFabiano Rosas     return ret;
354f0984d40SFabiano Rosas }
355f0984d40SFabiano Rosas 
356f0984d40SFabiano Rosas /* Set bits within PSTATE.  */
set_pstate_bits(uint32_t bits)357f0984d40SFabiano Rosas static inline void set_pstate_bits(uint32_t bits)
358f0984d40SFabiano Rosas {
359f0984d40SFabiano Rosas     TCGv_i32 p = tcg_temp_new_i32();
360f0984d40SFabiano Rosas 
361f0984d40SFabiano Rosas     tcg_debug_assert(!(bits & CACHED_PSTATE_BITS));
362f0984d40SFabiano Rosas 
363ad75a51eSRichard Henderson     tcg_gen_ld_i32(p, tcg_env, offsetof(CPUARMState, pstate));
364f0984d40SFabiano Rosas     tcg_gen_ori_i32(p, p, bits);
365ad75a51eSRichard Henderson     tcg_gen_st_i32(p, tcg_env, offsetof(CPUARMState, pstate));
366f0984d40SFabiano Rosas }
367f0984d40SFabiano Rosas 
368f0984d40SFabiano Rosas /* Clear bits within PSTATE.  */
clear_pstate_bits(uint32_t bits)369f0984d40SFabiano Rosas static inline void clear_pstate_bits(uint32_t bits)
370f0984d40SFabiano Rosas {
371f0984d40SFabiano Rosas     TCGv_i32 p = tcg_temp_new_i32();
372f0984d40SFabiano Rosas 
373f0984d40SFabiano Rosas     tcg_debug_assert(!(bits & CACHED_PSTATE_BITS));
374f0984d40SFabiano Rosas 
375ad75a51eSRichard Henderson     tcg_gen_ld_i32(p, tcg_env, offsetof(CPUARMState, pstate));
376f0984d40SFabiano Rosas     tcg_gen_andi_i32(p, p, ~bits);
377ad75a51eSRichard Henderson     tcg_gen_st_i32(p, tcg_env, offsetof(CPUARMState, pstate));
378f0984d40SFabiano Rosas }
379f0984d40SFabiano Rosas 
380f0984d40SFabiano Rosas /* If the singlestep state is Active-not-pending, advance to Active-pending. */
gen_ss_advance(DisasContext * s)381f0984d40SFabiano Rosas static inline void gen_ss_advance(DisasContext *s)
382f0984d40SFabiano Rosas {
383f0984d40SFabiano Rosas     if (s->ss_active) {
384f0984d40SFabiano Rosas         s->pstate_ss = 0;
385f0984d40SFabiano Rosas         clear_pstate_bits(PSTATE_SS);
386f0984d40SFabiano Rosas     }
387f0984d40SFabiano Rosas }
388f0984d40SFabiano Rosas 
389f0984d40SFabiano Rosas /* Generate an architectural singlestep exception */
gen_swstep_exception(DisasContext * s,int isv,int ex)390f0984d40SFabiano Rosas static inline void gen_swstep_exception(DisasContext *s, int isv, int ex)
391f0984d40SFabiano Rosas {
392f0984d40SFabiano Rosas     /* Fill in the same_el field of the syndrome in the helper. */
393f0984d40SFabiano Rosas     uint32_t syn = syn_swstep(false, isv, ex);
394ad75a51eSRichard Henderson     gen_helper_exception_swstep(tcg_env, tcg_constant_i32(syn));
395f0984d40SFabiano Rosas }
396f0984d40SFabiano Rosas 
397f0984d40SFabiano Rosas /*
398f0984d40SFabiano Rosas  * Given a VFP floating point constant encoded into an 8 bit immediate in an
399f0984d40SFabiano Rosas  * instruction, expand it to the actual constant value of the specified
400f0984d40SFabiano Rosas  * size, as per the VFPExpandImm() pseudocode in the Arm ARM.
401f0984d40SFabiano Rosas  */
402f0984d40SFabiano Rosas uint64_t vfp_expand_imm(int size, uint8_t imm8);
403f0984d40SFabiano Rosas 
404f0984d40SFabiano Rosas /* Vector operations shared between ARM and AArch64.  */
405f0984d40SFabiano Rosas void gen_gvec_ceq0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
406f0984d40SFabiano Rosas                    uint32_t opr_sz, uint32_t max_sz);
407f0984d40SFabiano Rosas void gen_gvec_clt0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
408f0984d40SFabiano Rosas                    uint32_t opr_sz, uint32_t max_sz);
409f0984d40SFabiano Rosas void gen_gvec_cgt0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
410f0984d40SFabiano Rosas                    uint32_t opr_sz, uint32_t max_sz);
411f0984d40SFabiano Rosas void gen_gvec_cle0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
412f0984d40SFabiano Rosas                    uint32_t opr_sz, uint32_t max_sz);
413f0984d40SFabiano Rosas void gen_gvec_cge0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
414f0984d40SFabiano Rosas                    uint32_t opr_sz, uint32_t max_sz);
415f0984d40SFabiano Rosas 
416f0984d40SFabiano Rosas void gen_gvec_mla(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
417f0984d40SFabiano Rosas                   uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
418f0984d40SFabiano Rosas void gen_gvec_mls(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
419f0984d40SFabiano Rosas                   uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
420f0984d40SFabiano Rosas 
421f0984d40SFabiano Rosas void gen_gvec_cmtst(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
422f0984d40SFabiano Rosas                     uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
423f0984d40SFabiano Rosas void gen_gvec_sshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
424f0984d40SFabiano Rosas                    uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
425f0984d40SFabiano Rosas void gen_gvec_ushl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
426f0984d40SFabiano Rosas                    uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
427f0984d40SFabiano Rosas 
428f0984d40SFabiano Rosas void gen_cmtst_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
429f0984d40SFabiano Rosas void gen_ushl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b);
430f0984d40SFabiano Rosas void gen_sshl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b);
431f0984d40SFabiano Rosas void gen_ushl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
432f0984d40SFabiano Rosas void gen_sshl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
433f0984d40SFabiano Rosas 
434f0984d40SFabiano Rosas void gen_gvec_uqadd_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
435f0984d40SFabiano Rosas                        uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
436f0984d40SFabiano Rosas void gen_gvec_sqadd_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
437f0984d40SFabiano Rosas                        uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
438f0984d40SFabiano Rosas void gen_gvec_uqsub_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
439f0984d40SFabiano Rosas                        uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
440f0984d40SFabiano Rosas void gen_gvec_sqsub_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
441f0984d40SFabiano Rosas                        uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
442f0984d40SFabiano Rosas 
443f0984d40SFabiano Rosas void gen_gvec_ssra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
444f0984d40SFabiano Rosas                    int64_t shift, uint32_t opr_sz, uint32_t max_sz);
445f0984d40SFabiano Rosas void gen_gvec_usra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
446f0984d40SFabiano Rosas                    int64_t shift, uint32_t opr_sz, uint32_t max_sz);
447f0984d40SFabiano Rosas 
448f0984d40SFabiano Rosas void gen_gvec_srshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
449f0984d40SFabiano Rosas                     int64_t shift, uint32_t opr_sz, uint32_t max_sz);
450f0984d40SFabiano Rosas void gen_gvec_urshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
451f0984d40SFabiano Rosas                     int64_t shift, uint32_t opr_sz, uint32_t max_sz);
452f0984d40SFabiano Rosas void gen_gvec_srsra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
453f0984d40SFabiano Rosas                     int64_t shift, uint32_t opr_sz, uint32_t max_sz);
454f0984d40SFabiano Rosas void gen_gvec_ursra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
455f0984d40SFabiano Rosas                     int64_t shift, uint32_t opr_sz, uint32_t max_sz);
456f0984d40SFabiano Rosas 
457f0984d40SFabiano Rosas void gen_gvec_sri(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
458f0984d40SFabiano Rosas                   int64_t shift, uint32_t opr_sz, uint32_t max_sz);
459f0984d40SFabiano Rosas void gen_gvec_sli(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
460f0984d40SFabiano Rosas                   int64_t shift, uint32_t opr_sz, uint32_t max_sz);
461f0984d40SFabiano Rosas 
462f0984d40SFabiano Rosas void gen_gvec_sqrdmlah_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
463f0984d40SFabiano Rosas                           uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
464f0984d40SFabiano Rosas void gen_gvec_sqrdmlsh_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
465f0984d40SFabiano Rosas                           uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
466f0984d40SFabiano Rosas 
467f0984d40SFabiano Rosas void gen_gvec_sabd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
468f0984d40SFabiano Rosas                    uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
469f0984d40SFabiano Rosas void gen_gvec_uabd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
470f0984d40SFabiano Rosas                    uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
471f0984d40SFabiano Rosas 
472f0984d40SFabiano Rosas void gen_gvec_saba(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
473f0984d40SFabiano Rosas                    uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
474f0984d40SFabiano Rosas void gen_gvec_uaba(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
475f0984d40SFabiano Rosas                    uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
476f0984d40SFabiano Rosas 
477f0984d40SFabiano Rosas /*
478f0984d40SFabiano Rosas  * Forward to the isar_feature_* tests given a DisasContext pointer.
479f0984d40SFabiano Rosas  */
480f0984d40SFabiano Rosas #define dc_isar_feature(name, ctx) \
481f0984d40SFabiano Rosas     ({ DisasContext *ctx_ = (ctx); isar_feature_##name(ctx_->isar); })
482f0984d40SFabiano Rosas 
483f0984d40SFabiano Rosas /* Note that the gvec expanders operate on offsets + sizes.  */
484f0984d40SFabiano Rosas typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t);
485f0984d40SFabiano Rosas typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t,
486f0984d40SFabiano Rosas                          uint32_t, uint32_t);
487f0984d40SFabiano Rosas typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
488f0984d40SFabiano Rosas                         uint32_t, uint32_t, uint32_t);
489f0984d40SFabiano Rosas typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t,
490f0984d40SFabiano Rosas                         uint32_t, uint32_t, uint32_t);
491f0984d40SFabiano Rosas 
492f0984d40SFabiano Rosas /* Function prototype for gen_ functions for calling Neon helpers */
493f0984d40SFabiano Rosas typedef void NeonGenOneOpFn(TCGv_i32, TCGv_i32);
494f0984d40SFabiano Rosas typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32);
495f0984d40SFabiano Rosas typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32);
496f0984d40SFabiano Rosas typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
497f0984d40SFabiano Rosas typedef void NeonGenThreeOpEnvFn(TCGv_i32, TCGv_env, TCGv_i32,
498f0984d40SFabiano Rosas                                  TCGv_i32, TCGv_i32);
499f0984d40SFabiano Rosas typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64);
500f0984d40SFabiano Rosas typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64);
501f0984d40SFabiano Rosas typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64);
502f0984d40SFabiano Rosas typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64);
503f0984d40SFabiano Rosas typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32);
504f0984d40SFabiano Rosas typedef void NeonGenTwoOpWidenFn(TCGv_i64, TCGv_i32, TCGv_i32);
505f0984d40SFabiano Rosas typedef void NeonGenOneSingleOpFn(TCGv_i32, TCGv_i32, TCGv_ptr);
506f0984d40SFabiano Rosas typedef void NeonGenTwoSingleOpFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
507f0984d40SFabiano Rosas typedef void NeonGenTwoDoubleOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);
508f0984d40SFabiano Rosas typedef void NeonGenOne64OpFn(TCGv_i64, TCGv_i64);
509f0984d40SFabiano Rosas typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
510f0984d40SFabiano Rosas typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
511f0984d40SFabiano Rosas typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
512f0984d40SFabiano Rosas typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
513f0984d40SFabiano Rosas typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
514f0984d40SFabiano Rosas typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
515f0984d40SFabiano Rosas typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift);
516f0984d40SFabiano Rosas typedef void ShiftFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
517f0984d40SFabiano Rosas 
518f0984d40SFabiano Rosas /**
519f0984d40SFabiano Rosas  * arm_tbflags_from_tb:
520f0984d40SFabiano Rosas  * @tb: the TranslationBlock
521f0984d40SFabiano Rosas  *
522f0984d40SFabiano Rosas  * Extract the flag values from @tb.
523f0984d40SFabiano Rosas  */
arm_tbflags_from_tb(const TranslationBlock * tb)524f0984d40SFabiano Rosas static inline CPUARMTBFlags arm_tbflags_from_tb(const TranslationBlock *tb)
525f0984d40SFabiano Rosas {
526f0984d40SFabiano Rosas     return (CPUARMTBFlags){ tb->flags, tb->cs_base };
527f0984d40SFabiano Rosas }
528f0984d40SFabiano Rosas 
529f0984d40SFabiano Rosas /*
530f0984d40SFabiano Rosas  * Enum for argument to fpstatus_ptr().
531f0984d40SFabiano Rosas  */
532f0984d40SFabiano Rosas typedef enum ARMFPStatusFlavour {
533f0984d40SFabiano Rosas     FPST_FPCR,
534f0984d40SFabiano Rosas     FPST_FPCR_F16,
535f0984d40SFabiano Rosas     FPST_STD,
536f0984d40SFabiano Rosas     FPST_STD_F16,
537f0984d40SFabiano Rosas } ARMFPStatusFlavour;
538f0984d40SFabiano Rosas 
539f0984d40SFabiano Rosas /**
540f0984d40SFabiano Rosas  * fpstatus_ptr: return TCGv_ptr to the specified fp_status field
541f0984d40SFabiano Rosas  *
542f0984d40SFabiano Rosas  * We have multiple softfloat float_status fields in the Arm CPU state struct
543f0984d40SFabiano Rosas  * (see the comment in cpu.h for details). Return a TCGv_ptr which has
544f0984d40SFabiano Rosas  * been set up to point to the requested field in the CPU state struct.
545f0984d40SFabiano Rosas  * The options are:
546f0984d40SFabiano Rosas  *
547f0984d40SFabiano Rosas  * FPST_FPCR
548f0984d40SFabiano Rosas  *   for non-FP16 operations controlled by the FPCR
549f0984d40SFabiano Rosas  * FPST_FPCR_F16
550f0984d40SFabiano Rosas  *   for operations controlled by the FPCR where FPCR.FZ16 is to be used
551f0984d40SFabiano Rosas  * FPST_STD
552f0984d40SFabiano Rosas  *   for A32/T32 Neon operations using the "standard FPSCR value"
553f0984d40SFabiano Rosas  * FPST_STD_F16
554f0984d40SFabiano Rosas  *   as FPST_STD, but where FPCR.FZ16 is to be used
555f0984d40SFabiano Rosas  */
fpstatus_ptr(ARMFPStatusFlavour flavour)556f0984d40SFabiano Rosas static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour flavour)
557f0984d40SFabiano Rosas {
558f0984d40SFabiano Rosas     TCGv_ptr statusptr = tcg_temp_new_ptr();
559f0984d40SFabiano Rosas     int offset;
560f0984d40SFabiano Rosas 
561f0984d40SFabiano Rosas     switch (flavour) {
562f0984d40SFabiano Rosas     case FPST_FPCR:
563f0984d40SFabiano Rosas         offset = offsetof(CPUARMState, vfp.fp_status);
564f0984d40SFabiano Rosas         break;
565f0984d40SFabiano Rosas     case FPST_FPCR_F16:
566f0984d40SFabiano Rosas         offset = offsetof(CPUARMState, vfp.fp_status_f16);
567f0984d40SFabiano Rosas         break;
568f0984d40SFabiano Rosas     case FPST_STD:
569f0984d40SFabiano Rosas         offset = offsetof(CPUARMState, vfp.standard_fp_status);
570f0984d40SFabiano Rosas         break;
571f0984d40SFabiano Rosas     case FPST_STD_F16:
572f0984d40SFabiano Rosas         offset = offsetof(CPUARMState, vfp.standard_fp_status_f16);
573f0984d40SFabiano Rosas         break;
574f0984d40SFabiano Rosas     default:
575f0984d40SFabiano Rosas         g_assert_not_reached();
576f0984d40SFabiano Rosas     }
577ad75a51eSRichard Henderson     tcg_gen_addi_ptr(statusptr, tcg_env, offset);
578f0984d40SFabiano Rosas     return statusptr;
579f0984d40SFabiano Rosas }
580f0984d40SFabiano Rosas 
581f0984d40SFabiano Rosas /**
582e452ca5aSRichard Henderson  * finalize_memop_atom:
583f0984d40SFabiano Rosas  * @s: DisasContext
584f0984d40SFabiano Rosas  * @opc: size+sign+align of the memory operation
585e452ca5aSRichard Henderson  * @atom: atomicity of the memory operation
586f0984d40SFabiano Rosas  *
587e452ca5aSRichard Henderson  * Build the complete MemOp for a memory operation, including alignment,
588e452ca5aSRichard Henderson  * endianness, and atomicity.
589f0984d40SFabiano Rosas  *
590f0984d40SFabiano Rosas  * If (op & MO_AMASK) then the operation already contains the required
591f0984d40SFabiano Rosas  * alignment, e.g. for AccType_ATOMIC.  Otherwise, this an optionally
592f0984d40SFabiano Rosas  * unaligned operation, e.g. for AccType_NORMAL.
593f0984d40SFabiano Rosas  *
594f0984d40SFabiano Rosas  * In the latter case, there are configuration bits that require alignment,
595f0984d40SFabiano Rosas  * and this is applied here.  Note that there is no way to indicate that
596f0984d40SFabiano Rosas  * no alignment should ever be enforced; this must be handled manually.
597f0984d40SFabiano Rosas  */
finalize_memop_atom(DisasContext * s,MemOp opc,MemOp atom)598e452ca5aSRichard Henderson static inline MemOp finalize_memop_atom(DisasContext *s, MemOp opc, MemOp atom)
599f0984d40SFabiano Rosas {
600f0984d40SFabiano Rosas     if (s->align_mem && !(opc & MO_AMASK)) {
601f0984d40SFabiano Rosas         opc |= MO_ALIGN;
602f0984d40SFabiano Rosas     }
603e452ca5aSRichard Henderson     return opc | atom | s->be_data;
604e452ca5aSRichard Henderson }
605e452ca5aSRichard Henderson 
606e452ca5aSRichard Henderson /**
607e452ca5aSRichard Henderson  * finalize_memop:
608e452ca5aSRichard Henderson  * @s: DisasContext
609e452ca5aSRichard Henderson  * @opc: size+sign+align of the memory operation
610e452ca5aSRichard Henderson  *
611e452ca5aSRichard Henderson  * Like finalize_memop_atom, but with default atomicity.
612e452ca5aSRichard Henderson  */
finalize_memop(DisasContext * s,MemOp opc)613e452ca5aSRichard Henderson static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
614e452ca5aSRichard Henderson {
615e452ca5aSRichard Henderson     MemOp atom = s->lse2 ? MO_ATOM_WITHIN16 : MO_ATOM_IFALIGN;
616e452ca5aSRichard Henderson     return finalize_memop_atom(s, opc, atom);
617e452ca5aSRichard Henderson }
618e452ca5aSRichard Henderson 
619e452ca5aSRichard Henderson /**
620e452ca5aSRichard Henderson  * finalize_memop_pair:
621e452ca5aSRichard Henderson  * @s: DisasContext
622e452ca5aSRichard Henderson  * @opc: size+sign+align of the memory operation
623e452ca5aSRichard Henderson  *
624e452ca5aSRichard Henderson  * Like finalize_memop_atom, but with atomicity for a pair.
625e452ca5aSRichard Henderson  * C.f. Pseudocode for Mem[], operand ispair.
626e452ca5aSRichard Henderson  */
finalize_memop_pair(DisasContext * s,MemOp opc)627e452ca5aSRichard Henderson static inline MemOp finalize_memop_pair(DisasContext *s, MemOp opc)
628e452ca5aSRichard Henderson {
629e452ca5aSRichard Henderson     MemOp atom = s->lse2 ? MO_ATOM_WITHIN16_PAIR : MO_ATOM_IFALIGN_PAIR;
630e452ca5aSRichard Henderson     return finalize_memop_atom(s, opc, atom);
631f0984d40SFabiano Rosas }
632f0984d40SFabiano Rosas 
633f0984d40SFabiano Rosas /**
634d450bd01SRichard Henderson  * finalize_memop_asimd:
635d450bd01SRichard Henderson  * @s: DisasContext
636d450bd01SRichard Henderson  * @opc: size+sign+align of the memory operation
637d450bd01SRichard Henderson  *
638d450bd01SRichard Henderson  * Like finalize_memop_atom, but with atomicity of AccessType_ASIMD.
639d450bd01SRichard Henderson  */
finalize_memop_asimd(DisasContext * s,MemOp opc)640d450bd01SRichard Henderson static inline MemOp finalize_memop_asimd(DisasContext *s, MemOp opc)
641d450bd01SRichard Henderson {
642d450bd01SRichard Henderson     /*
643d450bd01SRichard Henderson      * In the pseudocode for Mem[], with AccessType_ASIMD, size == 16,
644d450bd01SRichard Henderson      * if IsAligned(8), the first case provides separate atomicity for
645d450bd01SRichard Henderson      * the pair of 64-bit accesses.  If !IsAligned(8), the middle cases
646d450bd01SRichard Henderson      * do not apply, and we're left with the final case of no atomicity.
647d450bd01SRichard Henderson      * Thus MO_ATOM_IFALIGN_PAIR.
648d450bd01SRichard Henderson      *
649d450bd01SRichard Henderson      * For other sizes, normal LSE2 rules apply.
650d450bd01SRichard Henderson      */
651d450bd01SRichard Henderson     if ((opc & MO_SIZE) == MO_128) {
652d450bd01SRichard Henderson         return finalize_memop_atom(s, opc, MO_ATOM_IFALIGN_PAIR);
653d450bd01SRichard Henderson     }
654d450bd01SRichard Henderson     return finalize_memop(s, opc);
655d450bd01SRichard Henderson }
656d450bd01SRichard Henderson 
657d450bd01SRichard Henderson /**
658f0984d40SFabiano Rosas  * asimd_imm_const: Expand an encoded SIMD constant value
659f0984d40SFabiano Rosas  *
660f0984d40SFabiano Rosas  * Expand a SIMD constant value. This is essentially the pseudocode
661f0984d40SFabiano Rosas  * AdvSIMDExpandImm, except that we also perform the boolean NOT needed for
662f0984d40SFabiano Rosas  * VMVN and VBIC (when cmode < 14 && op == 1).
663f0984d40SFabiano Rosas  *
664f0984d40SFabiano Rosas  * The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
665f0984d40SFabiano Rosas  * callers must catch this; we return the 64-bit constant value defined
666f0984d40SFabiano Rosas  * for AArch64.
667f0984d40SFabiano Rosas  *
668f0984d40SFabiano Rosas  * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
669f0984d40SFabiano Rosas  * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
670f0984d40SFabiano Rosas  * we produce an immediate constant value of 0 in these cases.
671f0984d40SFabiano Rosas  */
672f0984d40SFabiano Rosas uint64_t asimd_imm_const(uint32_t imm, int cmode, int op);
673f0984d40SFabiano Rosas 
674f0984d40SFabiano Rosas /*
675f0984d40SFabiano Rosas  * gen_disas_label:
676f0984d40SFabiano Rosas  * Create a label and cache a copy of pc_save.
677f0984d40SFabiano Rosas  */
gen_disas_label(DisasContext * s)678f0984d40SFabiano Rosas static inline DisasLabel gen_disas_label(DisasContext *s)
679f0984d40SFabiano Rosas {
680f0984d40SFabiano Rosas     return (DisasLabel){
681f0984d40SFabiano Rosas         .label = gen_new_label(),
682f0984d40SFabiano Rosas         .pc_save = s->pc_save,
683f0984d40SFabiano Rosas     };
684f0984d40SFabiano Rosas }
685f0984d40SFabiano Rosas 
686f0984d40SFabiano Rosas /*
687f0984d40SFabiano Rosas  * set_disas_label:
688f0984d40SFabiano Rosas  * Emit a label and restore the cached copy of pc_save.
689f0984d40SFabiano Rosas  */
set_disas_label(DisasContext * s,DisasLabel l)690f0984d40SFabiano Rosas static inline void set_disas_label(DisasContext *s, DisasLabel l)
691f0984d40SFabiano Rosas {
692f0984d40SFabiano Rosas     gen_set_label(l.label);
693f0984d40SFabiano Rosas     s->pc_save = l.pc_save;
694f0984d40SFabiano Rosas }
695f0984d40SFabiano Rosas 
gen_lookup_cp_reg(uint32_t key)696f0984d40SFabiano Rosas static inline TCGv_ptr gen_lookup_cp_reg(uint32_t key)
697f0984d40SFabiano Rosas {
698f0984d40SFabiano Rosas     TCGv_ptr ret = tcg_temp_new_ptr();
699ad75a51eSRichard Henderson     gen_helper_lookup_cp_reg(ret, tcg_env, tcg_constant_i32(key));
700f0984d40SFabiano Rosas     return ret;
701f0984d40SFabiano Rosas }
702f0984d40SFabiano Rosas 
703f0984d40SFabiano Rosas /*
7048d1b02a6SRichard Henderson  * Set and reset rounding mode around another operation.
7058d1b02a6SRichard Henderson  */
gen_set_rmode(ARMFPRounding rmode,TCGv_ptr fpst)7068d1b02a6SRichard Henderson static inline TCGv_i32 gen_set_rmode(ARMFPRounding rmode, TCGv_ptr fpst)
7078d1b02a6SRichard Henderson {
7088d1b02a6SRichard Henderson     TCGv_i32 new = tcg_constant_i32(arm_rmode_to_sf(rmode));
7098d1b02a6SRichard Henderson     TCGv_i32 old = tcg_temp_new_i32();
7108d1b02a6SRichard Henderson 
7118d1b02a6SRichard Henderson     gen_helper_set_rmode(old, new, fpst);
7128d1b02a6SRichard Henderson     return old;
7138d1b02a6SRichard Henderson }
7148d1b02a6SRichard Henderson 
gen_restore_rmode(TCGv_i32 old,TCGv_ptr fpst)7158d1b02a6SRichard Henderson static inline void gen_restore_rmode(TCGv_i32 old, TCGv_ptr fpst)
7168d1b02a6SRichard Henderson {
7178d1b02a6SRichard Henderson     gen_helper_set_rmode(old, old, fpst);
7188d1b02a6SRichard Henderson }
7198d1b02a6SRichard Henderson 
7208d1b02a6SRichard Henderson /*
721f0984d40SFabiano Rosas  * Helpers for implementing sets of trans_* functions.
722f0984d40SFabiano Rosas  * Defer the implementation of NAME to FUNC, with optional extra arguments.
723f0984d40SFabiano Rosas  */
724f0984d40SFabiano Rosas #define TRANS(NAME, FUNC, ...) \
725f0984d40SFabiano Rosas     static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
726f0984d40SFabiano Rosas     { return FUNC(s, __VA_ARGS__); }
727f0984d40SFabiano Rosas #define TRANS_FEAT(NAME, FEAT, FUNC, ...) \
728f0984d40SFabiano Rosas     static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
729f0984d40SFabiano Rosas     { return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); }
730f0984d40SFabiano Rosas 
731f0984d40SFabiano Rosas #define TRANS_FEAT_NONSTREAMING(NAME, FEAT, FUNC, ...)            \
732f0984d40SFabiano Rosas     static bool trans_##NAME(DisasContext *s, arg_##NAME *a)      \
733f0984d40SFabiano Rosas     {                                                             \
734f0984d40SFabiano Rosas         s->is_nonstreaming = true;                                \
735f0984d40SFabiano Rosas         return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__);  \
736f0984d40SFabiano Rosas     }
737f0984d40SFabiano Rosas 
738f0984d40SFabiano Rosas #endif /* TARGET_ARM_TRANSLATE_H */
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