xref: /qemu/target/cris/cpu.c (revision 75ac231c) 
1 /*
2  * QEMU CRIS CPU
3  *
4  * Copyright (c) 2008 AXIS Communications AB
5  * Written by Edgar E. Iglesias.
6  *
7  * Copyright (c) 2012 SUSE LINUX Products GmbH
8  *
9  * This library is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU Lesser General Public
11  * License as published by the Free Software Foundation; either
12  * version 2.1 of the License, or (at your option) any later version.
13  *
14  * This library is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
17  * Lesser General Public License for more details.
18  *
19  * You should have received a copy of the GNU Lesser General Public
20  * License along with this library; if not, see
21  * <http://www.gnu.org/licenses/lgpl-2.1.html>
22  */
23 
24 #include "qemu/osdep.h"
25 #include "qapi/error.h"
26 #include "qemu/qemu-print.h"
27 #include "cpu.h"
28 #include "mmu.h"
29 
30 
31 static void cris_cpu_set_pc(CPUState *cs, vaddr value)
32 {
33     CRISCPU *cpu = CRIS_CPU(cs);
34 
35     cpu->env.pc = value;
36 }
37 
38 static vaddr cris_cpu_get_pc(CPUState *cs)
39 {
40     CRISCPU *cpu = CRIS_CPU(cs);
41 
42     return cpu->env.pc;
43 }
44 
45 static void cris_restore_state_to_opc(CPUState *cs,
46                                       const TranslationBlock *tb,
47                                       const uint64_t *data)
48 {
49     CRISCPU *cpu = CRIS_CPU(cs);
50 
51     cpu->env.pc = data[0];
52 }
53 
54 static bool cris_cpu_has_work(CPUState *cs)
55 {
56     return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
57 }
58 
59 static void cris_cpu_reset(DeviceState *dev)
60 {
61     CPUState *s = CPU(dev);
62     CRISCPU *cpu = CRIS_CPU(s);
63     CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(cpu);
64     CPUCRISState *env = &cpu->env;
65     uint32_t vr;
66 
67     ccc->parent_reset(dev);
68 
69     vr = env->pregs[PR_VR];
70     memset(env, 0, offsetof(CPUCRISState, end_reset_fields));
71     env->pregs[PR_VR] = vr;
72 
73 #if defined(CONFIG_USER_ONLY)
74     /* start in user mode with interrupts enabled.  */
75     env->pregs[PR_CCS] |= U_FLAG | I_FLAG | P_FLAG;
76 #else
77     cris_mmu_init(env);
78     env->pregs[PR_CCS] = 0;
79 #endif
80 }
81 
82 static ObjectClass *cris_cpu_class_by_name(const char *cpu_model)
83 {
84     ObjectClass *oc;
85     char *typename;
86 
87 #if defined(CONFIG_USER_ONLY)
88     if (strcasecmp(cpu_model, "any") == 0) {
89         return object_class_by_name(CRIS_CPU_TYPE_NAME("crisv32"));
90     }
91 #endif
92 
93     typename = g_strdup_printf(CRIS_CPU_TYPE_NAME("%s"), cpu_model);
94     oc = object_class_by_name(typename);
95     g_free(typename);
96     if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_CRIS_CPU) ||
97                        object_class_is_abstract(oc))) {
98         oc = NULL;
99     }
100     return oc;
101 }
102 
103 /* Sort alphabetically by VR. */
104 static gint cris_cpu_list_compare(gconstpointer a, gconstpointer b)
105 {
106     CRISCPUClass *ccc_a = CRIS_CPU_CLASS(a);
107     CRISCPUClass *ccc_b = CRIS_CPU_CLASS(b);
108 
109     /*  */
110     if (ccc_a->vr > ccc_b->vr) {
111         return 1;
112     } else if (ccc_a->vr < ccc_b->vr) {
113         return -1;
114     } else {
115         return 0;
116     }
117 }
118 
119 static void cris_cpu_list_entry(gpointer data, gpointer user_data)
120 {
121     ObjectClass *oc = data;
122     const char *typename = object_class_get_name(oc);
123     char *name;
124 
125     name = g_strndup(typename, strlen(typename) - strlen(CRIS_CPU_TYPE_SUFFIX));
126     qemu_printf("  %s\n", name);
127     g_free(name);
128 }
129 
130 void cris_cpu_list(void)
131 {
132     GSList *list;
133 
134     list = object_class_get_list(TYPE_CRIS_CPU, false);
135     list = g_slist_sort(list, cris_cpu_list_compare);
136     qemu_printf("Available CPUs:\n");
137     g_slist_foreach(list, cris_cpu_list_entry, NULL);
138     g_slist_free(list);
139 }
140 
141 static void cris_cpu_realizefn(DeviceState *dev, Error **errp)
142 {
143     CPUState *cs = CPU(dev);
144     CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(dev);
145     Error *local_err = NULL;
146 
147     cpu_exec_realizefn(cs, &local_err);
148     if (local_err != NULL) {
149         error_propagate(errp, local_err);
150         return;
151     }
152 
153     cpu_reset(cs);
154     qemu_init_vcpu(cs);
155 
156     ccc->parent_realize(dev, errp);
157 }
158 
159 #ifndef CONFIG_USER_ONLY
160 static void cris_cpu_set_irq(void *opaque, int irq, int level)
161 {
162     CRISCPU *cpu = opaque;
163     CPUState *cs = CPU(cpu);
164     int type = irq == CRIS_CPU_IRQ ? CPU_INTERRUPT_HARD : CPU_INTERRUPT_NMI;
165 
166     if (irq == CRIS_CPU_IRQ) {
167         /*
168          * The PIC passes us the vector for the IRQ as the value it sends
169          * over the qemu_irq line
170          */
171         cpu->env.interrupt_vector = level;
172     }
173 
174     if (level) {
175         cpu_interrupt(cs, type);
176     } else {
177         cpu_reset_interrupt(cs, type);
178     }
179 }
180 #endif
181 
182 static void cris_disas_set_info(CPUState *cpu, disassemble_info *info)
183 {
184     CRISCPU *cc = CRIS_CPU(cpu);
185     CPUCRISState *env = &cc->env;
186 
187     if (env->pregs[PR_VR] != 32) {
188         info->mach = bfd_mach_cris_v0_v10;
189         info->print_insn = print_insn_crisv10;
190     } else {
191         info->mach = bfd_mach_cris_v32;
192         info->print_insn = print_insn_crisv32;
193     }
194 }
195 
196 static void cris_cpu_initfn(Object *obj)
197 {
198     CRISCPU *cpu = CRIS_CPU(obj);
199     CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(obj);
200     CPUCRISState *env = &cpu->env;
201 
202     cpu_set_cpustate_pointers(cpu);
203 
204     env->pregs[PR_VR] = ccc->vr;
205 
206 #ifndef CONFIG_USER_ONLY
207     /* IRQ and NMI lines.  */
208     qdev_init_gpio_in(DEVICE(cpu), cris_cpu_set_irq, 2);
209 #endif
210 }
211 
212 #ifndef CONFIG_USER_ONLY
213 #include "hw/core/sysemu-cpu-ops.h"
214 
215 static const struct SysemuCPUOps cris_sysemu_ops = {
216     .get_phys_page_debug = cris_cpu_get_phys_page_debug,
217 };
218 #endif
219 
220 #include "hw/core/tcg-cpu-ops.h"
221 
222 static const struct TCGCPUOps crisv10_tcg_ops = {
223     .initialize = cris_initialize_crisv10_tcg,
224     .restore_state_to_opc = cris_restore_state_to_opc,
225 
226 #ifndef CONFIG_USER_ONLY
227     .tlb_fill = cris_cpu_tlb_fill,
228     .cpu_exec_interrupt = cris_cpu_exec_interrupt,
229     .do_interrupt = crisv10_cpu_do_interrupt,
230 #endif /* !CONFIG_USER_ONLY */
231 };
232 
233 static const struct TCGCPUOps crisv32_tcg_ops = {
234     .initialize = cris_initialize_tcg,
235     .restore_state_to_opc = cris_restore_state_to_opc,
236 
237 #ifndef CONFIG_USER_ONLY
238     .tlb_fill = cris_cpu_tlb_fill,
239     .cpu_exec_interrupt = cris_cpu_exec_interrupt,
240     .do_interrupt = cris_cpu_do_interrupt,
241 #endif /* !CONFIG_USER_ONLY */
242 };
243 
244 static void crisv8_cpu_class_init(ObjectClass *oc, void *data)
245 {
246     CPUClass *cc = CPU_CLASS(oc);
247     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
248 
249     ccc->vr = 8;
250     cc->gdb_read_register = crisv10_cpu_gdb_read_register;
251     cc->tcg_ops = &crisv10_tcg_ops;
252 }
253 
254 static void crisv9_cpu_class_init(ObjectClass *oc, void *data)
255 {
256     CPUClass *cc = CPU_CLASS(oc);
257     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
258 
259     ccc->vr = 9;
260     cc->gdb_read_register = crisv10_cpu_gdb_read_register;
261     cc->tcg_ops = &crisv10_tcg_ops;
262 }
263 
264 static void crisv10_cpu_class_init(ObjectClass *oc, void *data)
265 {
266     CPUClass *cc = CPU_CLASS(oc);
267     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
268 
269     ccc->vr = 10;
270     cc->gdb_read_register = crisv10_cpu_gdb_read_register;
271     cc->tcg_ops = &crisv10_tcg_ops;
272 }
273 
274 static void crisv11_cpu_class_init(ObjectClass *oc, void *data)
275 {
276     CPUClass *cc = CPU_CLASS(oc);
277     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
278 
279     ccc->vr = 11;
280     cc->gdb_read_register = crisv10_cpu_gdb_read_register;
281     cc->tcg_ops = &crisv10_tcg_ops;
282 }
283 
284 static void crisv17_cpu_class_init(ObjectClass *oc, void *data)
285 {
286     CPUClass *cc = CPU_CLASS(oc);
287     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
288 
289     ccc->vr = 17;
290     cc->gdb_read_register = crisv10_cpu_gdb_read_register;
291     cc->tcg_ops = &crisv10_tcg_ops;
292 }
293 
294 static void crisv32_cpu_class_init(ObjectClass *oc, void *data)
295 {
296     CPUClass *cc = CPU_CLASS(oc);
297     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
298 
299     ccc->vr = 32;
300     cc->tcg_ops = &crisv32_tcg_ops;
301 }
302 
303 static void cris_cpu_class_init(ObjectClass *oc, void *data)
304 {
305     DeviceClass *dc = DEVICE_CLASS(oc);
306     CPUClass *cc = CPU_CLASS(oc);
307     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
308 
309     device_class_set_parent_realize(dc, cris_cpu_realizefn,
310                                     &ccc->parent_realize);
311 
312     device_class_set_parent_reset(dc, cris_cpu_reset, &ccc->parent_reset);
313 
314     cc->class_by_name = cris_cpu_class_by_name;
315     cc->has_work = cris_cpu_has_work;
316     cc->dump_state = cris_cpu_dump_state;
317     cc->set_pc = cris_cpu_set_pc;
318     cc->get_pc = cris_cpu_get_pc;
319     cc->gdb_read_register = cris_cpu_gdb_read_register;
320     cc->gdb_write_register = cris_cpu_gdb_write_register;
321 #ifndef CONFIG_USER_ONLY
322     dc->vmsd = &vmstate_cris_cpu;
323     cc->sysemu_ops = &cris_sysemu_ops;
324 #endif
325 
326     cc->gdb_num_core_regs = 49;
327     cc->gdb_stop_before_watchpoint = true;
328 
329     cc->disas_set_info = cris_disas_set_info;
330 }
331 
332 #define DEFINE_CRIS_CPU_TYPE(cpu_model, initfn) \
333      {                                          \
334          .parent = TYPE_CRIS_CPU,               \
335          .class_init = initfn,                  \
336          .name = CRIS_CPU_TYPE_NAME(cpu_model), \
337      }
338 
339 static const TypeInfo cris_cpu_model_type_infos[] = {
340     {
341         .name = TYPE_CRIS_CPU,
342         .parent = TYPE_CPU,
343         .instance_size = sizeof(CRISCPU),
344         .instance_init = cris_cpu_initfn,
345         .abstract = true,
346         .class_size = sizeof(CRISCPUClass),
347         .class_init = cris_cpu_class_init,
348     },
349     DEFINE_CRIS_CPU_TYPE("crisv8", crisv8_cpu_class_init),
350     DEFINE_CRIS_CPU_TYPE("crisv9", crisv9_cpu_class_init),
351     DEFINE_CRIS_CPU_TYPE("crisv10", crisv10_cpu_class_init),
352     DEFINE_CRIS_CPU_TYPE("crisv11", crisv11_cpu_class_init),
353     DEFINE_CRIS_CPU_TYPE("crisv17", crisv17_cpu_class_init),
354     DEFINE_CRIS_CPU_TYPE("crisv32", crisv32_cpu_class_init),
355 };
356 
357 DEFINE_TYPES(cris_cpu_model_type_infos)
358