1 /* 2 * CRIS virtual CPU header 3 * 4 * Copyright (c) 2007 AXIS Communications AB 5 * Written by Edgar E. Iglesias 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #ifndef CRIS_CPU_H 22 #define CRIS_CPU_H 23 24 #include "qemu-common.h" 25 #include "cpu-qom.h" 26 27 #define TARGET_LONG_BITS 32 28 29 #define CPUArchState struct CPUCRISState 30 31 #include "exec/cpu-defs.h" 32 33 #define EXCP_NMI 1 34 #define EXCP_GURU 2 35 #define EXCP_BUSFAULT 3 36 #define EXCP_IRQ 4 37 #define EXCP_BREAK 5 38 39 /* CRIS-specific interrupt pending bits. */ 40 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 41 42 /* CRUS CPU device objects interrupt lines. */ 43 #define CRIS_CPU_IRQ 0 44 #define CRIS_CPU_NMI 1 45 46 /* Register aliases. R0 - R15 */ 47 #define R_FP 8 48 #define R_SP 14 49 #define R_ACR 15 50 51 /* Support regs, P0 - P15 */ 52 #define PR_BZ 0 53 #define PR_VR 1 54 #define PR_PID 2 55 #define PR_SRS 3 56 #define PR_WZ 4 57 #define PR_EXS 5 58 #define PR_EDA 6 59 #define PR_PREFIX 6 /* On CRISv10 P6 is reserved, we use it as prefix. */ 60 #define PR_MOF 7 61 #define PR_DZ 8 62 #define PR_EBP 9 63 #define PR_ERP 10 64 #define PR_SRP 11 65 #define PR_NRP 12 66 #define PR_CCS 13 67 #define PR_USP 14 68 #define PRV10_BRP 14 69 #define PR_SPC 15 70 71 /* CPU flags. */ 72 #define Q_FLAG 0x80000000 73 #define M_FLAG_V32 0x40000000 74 #define PFIX_FLAG 0x800 /* CRISv10 Only. */ 75 #define F_FLAG_V10 0x400 76 #define P_FLAG_V10 0x200 77 #define S_FLAG 0x200 78 #define R_FLAG 0x100 79 #define P_FLAG 0x80 80 #define M_FLAG_V10 0x80 81 #define U_FLAG 0x40 82 #define I_FLAG 0x20 83 #define X_FLAG 0x10 84 #define N_FLAG 0x08 85 #define Z_FLAG 0x04 86 #define V_FLAG 0x02 87 #define C_FLAG 0x01 88 #define ALU_FLAGS 0x1F 89 90 /* Condition codes. */ 91 #define CC_CC 0 92 #define CC_CS 1 93 #define CC_NE 2 94 #define CC_EQ 3 95 #define CC_VC 4 96 #define CC_VS 5 97 #define CC_PL 6 98 #define CC_MI 7 99 #define CC_LS 8 100 #define CC_HI 9 101 #define CC_GE 10 102 #define CC_LT 11 103 #define CC_GT 12 104 #define CC_LE 13 105 #define CC_A 14 106 #define CC_P 15 107 108 #define NB_MMU_MODES 2 109 110 typedef struct { 111 uint32_t hi; 112 uint32_t lo; 113 } TLBSet; 114 115 typedef struct CPUCRISState { 116 uint32_t regs[16]; 117 /* P0 - P15 are referred to as special registers in the docs. */ 118 uint32_t pregs[16]; 119 120 /* Pseudo register for the PC. Not directly accessible on CRIS. */ 121 uint32_t pc; 122 123 /* Pseudo register for the kernel stack. */ 124 uint32_t ksp; 125 126 /* Branch. */ 127 int dslot; 128 int btaken; 129 uint32_t btarget; 130 131 /* Condition flag tracking. */ 132 uint32_t cc_op; 133 uint32_t cc_mask; 134 uint32_t cc_dest; 135 uint32_t cc_src; 136 uint32_t cc_result; 137 /* size of the operation, 1 = byte, 2 = word, 4 = dword. */ 138 int cc_size; 139 /* X flag at the time of cc snapshot. */ 140 int cc_x; 141 142 /* CRIS has certain insns that lockout interrupts. */ 143 int locked_irq; 144 int interrupt_vector; 145 int fault_vector; 146 int trap_vector; 147 148 /* FIXME: add a check in the translator to avoid writing to support 149 register sets beyond the 4th. The ISA allows up to 256! but in 150 practice there is no core that implements more than 4. 151 152 Support function registers are used to control units close to the 153 core. Accesses do not pass down the normal hierarchy. 154 */ 155 uint32_t sregs[4][16]; 156 157 /* Linear feedback shift reg in the mmu. Used to provide pseudo 158 randomness for the 'hint' the mmu gives to sw for choosing valid 159 sets on TLB refills. */ 160 uint32_t mmu_rand_lfsr; 161 162 /* 163 * We just store the stores to the tlbset here for later evaluation 164 * when the hw needs access to them. 165 * 166 * One for I and another for D. 167 */ 168 TLBSet tlbsets[2][4][16]; 169 170 CPU_COMMON 171 172 /* Members from load_info on are preserved across resets. */ 173 void *load_info; 174 } CPUCRISState; 175 176 /** 177 * CRISCPU: 178 * @env: #CPUCRISState 179 * 180 * A CRIS CPU. 181 */ 182 struct CRISCPU { 183 /*< private >*/ 184 CPUState parent_obj; 185 /*< public >*/ 186 187 CPUCRISState env; 188 }; 189 190 static inline CRISCPU *cris_env_get_cpu(CPUCRISState *env) 191 { 192 return container_of(env, CRISCPU, env); 193 } 194 195 #define ENV_GET_CPU(e) CPU(cris_env_get_cpu(e)) 196 197 #define ENV_OFFSET offsetof(CRISCPU, env) 198 199 #ifndef CONFIG_USER_ONLY 200 extern const struct VMStateDescription vmstate_cris_cpu; 201 #endif 202 203 void cris_cpu_do_interrupt(CPUState *cpu); 204 void crisv10_cpu_do_interrupt(CPUState *cpu); 205 bool cris_cpu_exec_interrupt(CPUState *cpu, int int_req); 206 207 void cris_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 208 int flags); 209 210 hwaddr cris_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 211 212 int crisv10_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 213 int cris_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 214 int cris_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 215 216 CRISCPU *cpu_cris_init(const char *cpu_model); 217 /* you can call this signal handler from your SIGBUS and SIGSEGV 218 signal handlers to inform the virtual CPU of exceptions. non zero 219 is returned if the signal was handled by the virtual CPU. */ 220 int cpu_cris_signal_handler(int host_signum, void *pinfo, 221 void *puc); 222 223 void cris_initialize_tcg(void); 224 void cris_initialize_crisv10_tcg(void); 225 226 /* Instead of computing the condition codes after each CRIS instruction, 227 * QEMU just stores one operand (called CC_SRC), the result 228 * (called CC_DEST) and the type of operation (called CC_OP). When the 229 * condition codes are needed, the condition codes can be calculated 230 * using this information. Condition codes are not generated if they 231 * are only needed for conditional branches. 232 */ 233 enum { 234 CC_OP_DYNAMIC, /* Use env->cc_op */ 235 CC_OP_FLAGS, 236 CC_OP_CMP, 237 CC_OP_MOVE, 238 CC_OP_ADD, 239 CC_OP_ADDC, 240 CC_OP_MCP, 241 CC_OP_ADDU, 242 CC_OP_SUB, 243 CC_OP_SUBU, 244 CC_OP_NEG, 245 CC_OP_BTST, 246 CC_OP_MULS, 247 CC_OP_MULU, 248 CC_OP_DSTEP, 249 CC_OP_MSTEP, 250 CC_OP_BOUND, 251 252 CC_OP_OR, 253 CC_OP_AND, 254 CC_OP_XOR, 255 CC_OP_LSL, 256 CC_OP_LSR, 257 CC_OP_ASR, 258 CC_OP_LZ 259 }; 260 261 /* CRIS uses 8k pages. */ 262 #define TARGET_PAGE_BITS 13 263 #define MMAP_SHIFT TARGET_PAGE_BITS 264 265 #define TARGET_PHYS_ADDR_SPACE_BITS 32 266 #define TARGET_VIRT_ADDR_SPACE_BITS 32 267 268 #define cpu_init(cpu_model) CPU(cpu_cris_init(cpu_model)) 269 270 #define cpu_signal_handler cpu_cris_signal_handler 271 272 /* MMU modes definitions */ 273 #define MMU_MODE0_SUFFIX _kernel 274 #define MMU_MODE1_SUFFIX _user 275 #define MMU_USER_IDX 1 276 static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch) 277 { 278 return !!(env->pregs[PR_CCS] & U_FLAG); 279 } 280 281 int cris_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, 282 int mmu_idx); 283 284 /* Support function regs. */ 285 #define SFR_RW_GC_CFG 0][0 286 #define SFR_RW_MM_CFG env->pregs[PR_SRS]][0 287 #define SFR_RW_MM_KBASE_LO env->pregs[PR_SRS]][1 288 #define SFR_RW_MM_KBASE_HI env->pregs[PR_SRS]][2 289 #define SFR_R_MM_CAUSE env->pregs[PR_SRS]][3 290 #define SFR_RW_MM_TLB_SEL env->pregs[PR_SRS]][4 291 #define SFR_RW_MM_TLB_LO env->pregs[PR_SRS]][5 292 #define SFR_RW_MM_TLB_HI env->pregs[PR_SRS]][6 293 294 #include "exec/cpu-all.h" 295 296 static inline void cpu_get_tb_cpu_state(CPUCRISState *env, target_ulong *pc, 297 target_ulong *cs_base, uint32_t *flags) 298 { 299 *pc = env->pc; 300 *cs_base = 0; 301 *flags = env->dslot | 302 (env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG 303 | X_FLAG | PFIX_FLAG)); 304 } 305 306 #define cpu_list cris_cpu_list 307 void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf); 308 309 #endif 310