1 /* 2 * CRIS emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2008 AXIS Communications AB 5 * Written by Edgar E. Iglesias. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 /* 22 * FIXME: 23 * The condition code translation is in need of attention. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "cpu.h" 28 #include "disas/disas.h" 29 #include "exec/exec-all.h" 30 #include "tcg-op.h" 31 #include "exec/helper-proto.h" 32 #include "mmu.h" 33 #include "exec/cpu_ldst.h" 34 #include "exec/translator.h" 35 #include "crisv32-decode.h" 36 37 #include "exec/helper-gen.h" 38 39 #include "trace-tcg.h" 40 #include "exec/log.h" 41 42 43 #define DISAS_CRIS 0 44 #if DISAS_CRIS 45 # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 46 #else 47 # define LOG_DIS(...) do { } while (0) 48 #endif 49 50 #define D(x) 51 #define BUG() (gen_BUG(dc, __FILE__, __LINE__)) 52 #define BUG_ON(x) ({if (x) BUG();}) 53 54 /* is_jmp field values */ 55 #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ 56 #define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */ 57 #define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ 58 #define DISAS_SWI DISAS_TARGET_3 59 60 /* Used by the decoder. */ 61 #define EXTRACT_FIELD(src, start, end) \ 62 (((src) >> start) & ((1 << (end - start + 1)) - 1)) 63 64 #define CC_MASK_NZ 0xc 65 #define CC_MASK_NZV 0xe 66 #define CC_MASK_NZVC 0xf 67 #define CC_MASK_RNZV 0x10e 68 69 static TCGv cpu_R[16]; 70 static TCGv cpu_PR[16]; 71 static TCGv cc_x; 72 static TCGv cc_src; 73 static TCGv cc_dest; 74 static TCGv cc_result; 75 static TCGv cc_op; 76 static TCGv cc_size; 77 static TCGv cc_mask; 78 79 static TCGv env_btaken; 80 static TCGv env_btarget; 81 static TCGv env_pc; 82 83 #include "exec/gen-icount.h" 84 85 /* This is the state at translation time. */ 86 typedef struct DisasContext { 87 CRISCPU *cpu; 88 target_ulong pc, ppc; 89 90 /* Decoder. */ 91 unsigned int (*decoder)(CPUCRISState *env, struct DisasContext *dc); 92 uint32_t ir; 93 uint32_t opcode; 94 unsigned int op1; 95 unsigned int op2; 96 unsigned int zsize, zzsize; 97 unsigned int mode; 98 unsigned int postinc; 99 100 unsigned int size; 101 unsigned int src; 102 unsigned int dst; 103 unsigned int cond; 104 105 int update_cc; 106 int cc_op; 107 int cc_size; 108 uint32_t cc_mask; 109 110 int cc_size_uptodate; /* -1 invalid or last written value. */ 111 112 int cc_x_uptodate; /* 1 - ccs, 2 - known | X_FLAG. 0 not up-to-date. */ 113 int flags_uptodate; /* Whether or not $ccs is up-to-date. */ 114 int flagx_known; /* Whether or not flags_x has the x flag known at 115 translation time. */ 116 int flags_x; 117 118 int clear_x; /* Clear x after this insn? */ 119 int clear_prefix; /* Clear prefix after this insn? */ 120 int clear_locked_irq; /* Clear the irq lockout. */ 121 int cpustate_changed; 122 unsigned int tb_flags; /* tb dependent flags. */ 123 int is_jmp; 124 125 #define JMP_NOJMP 0 126 #define JMP_DIRECT 1 127 #define JMP_DIRECT_CC 2 128 #define JMP_INDIRECT 3 129 int jmp; /* 0=nojmp, 1=direct, 2=indirect. */ 130 uint32_t jmp_pc; 131 132 int delayed_branch; 133 134 struct TranslationBlock *tb; 135 int singlestep_enabled; 136 } DisasContext; 137 138 static void gen_BUG(DisasContext *dc, const char *file, int line) 139 { 140 fprintf(stderr, "BUG: pc=%x %s %d\n", dc->pc, file, line); 141 if (qemu_log_separate()) { 142 qemu_log("BUG: pc=%x %s %d\n", dc->pc, file, line); 143 } 144 cpu_abort(CPU(dc->cpu), "%s:%d\n", file, line); 145 } 146 147 static const char *regnames_v32[] = 148 { 149 "$r0", "$r1", "$r2", "$r3", 150 "$r4", "$r5", "$r6", "$r7", 151 "$r8", "$r9", "$r10", "$r11", 152 "$r12", "$r13", "$sp", "$acr", 153 }; 154 static const char *pregnames_v32[] = 155 { 156 "$bz", "$vr", "$pid", "$srs", 157 "$wz", "$exs", "$eda", "$mof", 158 "$dz", "$ebp", "$erp", "$srp", 159 "$nrp", "$ccs", "$usp", "$spc", 160 }; 161 162 /* We need this table to handle preg-moves with implicit width. */ 163 static int preg_sizes[] = { 164 1, /* bz. */ 165 1, /* vr. */ 166 4, /* pid. */ 167 1, /* srs. */ 168 2, /* wz. */ 169 4, 4, 4, 170 4, 4, 4, 4, 171 4, 4, 4, 4, 172 }; 173 174 #define t_gen_mov_TN_env(tn, member) \ 175 tcg_gen_ld_tl(tn, cpu_env, offsetof(CPUCRISState, member)) 176 #define t_gen_mov_env_TN(member, tn) \ 177 tcg_gen_st_tl(tn, cpu_env, offsetof(CPUCRISState, member)) 178 179 static inline void t_gen_mov_TN_preg(TCGv tn, int r) 180 { 181 assert(r >= 0 && r <= 15); 182 if (r == PR_BZ || r == PR_WZ || r == PR_DZ) { 183 tcg_gen_mov_tl(tn, tcg_const_tl(0)); 184 } else if (r == PR_VR) { 185 tcg_gen_mov_tl(tn, tcg_const_tl(32)); 186 } else { 187 tcg_gen_mov_tl(tn, cpu_PR[r]); 188 } 189 } 190 static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn) 191 { 192 assert(r >= 0 && r <= 15); 193 if (r == PR_BZ || r == PR_WZ || r == PR_DZ) { 194 return; 195 } else if (r == PR_SRS) { 196 tcg_gen_andi_tl(cpu_PR[r], tn, 3); 197 } else { 198 if (r == PR_PID) { 199 gen_helper_tlb_flush_pid(cpu_env, tn); 200 } 201 if (dc->tb_flags & S_FLAG && r == PR_SPC) { 202 gen_helper_spc_write(cpu_env, tn); 203 } else if (r == PR_CCS) { 204 dc->cpustate_changed = 1; 205 } 206 tcg_gen_mov_tl(cpu_PR[r], tn); 207 } 208 } 209 210 /* Sign extend at translation time. */ 211 static int sign_extend(unsigned int val, unsigned int width) 212 { 213 int sval; 214 215 /* LSL. */ 216 val <<= 31 - width; 217 sval = val; 218 /* ASR. */ 219 sval >>= 31 - width; 220 return sval; 221 } 222 223 static int cris_fetch(CPUCRISState *env, DisasContext *dc, uint32_t addr, 224 unsigned int size, unsigned int sign) 225 { 226 int r; 227 228 switch (size) { 229 case 4: 230 { 231 r = cpu_ldl_code(env, addr); 232 break; 233 } 234 case 2: 235 { 236 if (sign) { 237 r = cpu_ldsw_code(env, addr); 238 } else { 239 r = cpu_lduw_code(env, addr); 240 } 241 break; 242 } 243 case 1: 244 { 245 if (sign) { 246 r = cpu_ldsb_code(env, addr); 247 } else { 248 r = cpu_ldub_code(env, addr); 249 } 250 break; 251 } 252 default: 253 cpu_abort(CPU(dc->cpu), "Invalid fetch size %d\n", size); 254 break; 255 } 256 return r; 257 } 258 259 static void cris_lock_irq(DisasContext *dc) 260 { 261 dc->clear_locked_irq = 0; 262 t_gen_mov_env_TN(locked_irq, tcg_const_tl(1)); 263 } 264 265 static inline void t_gen_raise_exception(uint32_t index) 266 { 267 TCGv_i32 tmp = tcg_const_i32(index); 268 gen_helper_raise_exception(cpu_env, tmp); 269 tcg_temp_free_i32(tmp); 270 } 271 272 static void t_gen_lsl(TCGv d, TCGv a, TCGv b) 273 { 274 TCGv t0, t_31; 275 276 t0 = tcg_temp_new(); 277 t_31 = tcg_const_tl(31); 278 tcg_gen_shl_tl(d, a, b); 279 280 tcg_gen_sub_tl(t0, t_31, b); 281 tcg_gen_sar_tl(t0, t0, t_31); 282 tcg_gen_and_tl(t0, t0, d); 283 tcg_gen_xor_tl(d, d, t0); 284 tcg_temp_free(t0); 285 tcg_temp_free(t_31); 286 } 287 288 static void t_gen_lsr(TCGv d, TCGv a, TCGv b) 289 { 290 TCGv t0, t_31; 291 292 t0 = tcg_temp_new(); 293 t_31 = tcg_temp_new(); 294 tcg_gen_shr_tl(d, a, b); 295 296 tcg_gen_movi_tl(t_31, 31); 297 tcg_gen_sub_tl(t0, t_31, b); 298 tcg_gen_sar_tl(t0, t0, t_31); 299 tcg_gen_and_tl(t0, t0, d); 300 tcg_gen_xor_tl(d, d, t0); 301 tcg_temp_free(t0); 302 tcg_temp_free(t_31); 303 } 304 305 static void t_gen_asr(TCGv d, TCGv a, TCGv b) 306 { 307 TCGv t0, t_31; 308 309 t0 = tcg_temp_new(); 310 t_31 = tcg_temp_new(); 311 tcg_gen_sar_tl(d, a, b); 312 313 tcg_gen_movi_tl(t_31, 31); 314 tcg_gen_sub_tl(t0, t_31, b); 315 tcg_gen_sar_tl(t0, t0, t_31); 316 tcg_gen_or_tl(d, d, t0); 317 tcg_temp_free(t0); 318 tcg_temp_free(t_31); 319 } 320 321 static void t_gen_cris_dstep(TCGv d, TCGv a, TCGv b) 322 { 323 TCGv t = tcg_temp_new(); 324 325 /* 326 * d <<= 1 327 * if (d >= s) 328 * d -= s; 329 */ 330 tcg_gen_shli_tl(d, a, 1); 331 tcg_gen_sub_tl(t, d, b); 332 tcg_gen_movcond_tl(TCG_COND_GEU, d, d, b, t, d); 333 tcg_temp_free(t); 334 } 335 336 static void t_gen_cris_mstep(TCGv d, TCGv a, TCGv b, TCGv ccs) 337 { 338 TCGv t; 339 340 /* 341 * d <<= 1 342 * if (n) 343 * d += s; 344 */ 345 t = tcg_temp_new(); 346 tcg_gen_shli_tl(d, a, 1); 347 tcg_gen_shli_tl(t, ccs, 31 - 3); 348 tcg_gen_sari_tl(t, t, 31); 349 tcg_gen_and_tl(t, t, b); 350 tcg_gen_add_tl(d, d, t); 351 tcg_temp_free(t); 352 } 353 354 /* Extended arithmetics on CRIS. */ 355 static inline void t_gen_add_flag(TCGv d, int flag) 356 { 357 TCGv c; 358 359 c = tcg_temp_new(); 360 t_gen_mov_TN_preg(c, PR_CCS); 361 /* Propagate carry into d. */ 362 tcg_gen_andi_tl(c, c, 1 << flag); 363 if (flag) { 364 tcg_gen_shri_tl(c, c, flag); 365 } 366 tcg_gen_add_tl(d, d, c); 367 tcg_temp_free(c); 368 } 369 370 static inline void t_gen_addx_carry(DisasContext *dc, TCGv d) 371 { 372 if (dc->flagx_known) { 373 if (dc->flags_x) { 374 TCGv c; 375 376 c = tcg_temp_new(); 377 t_gen_mov_TN_preg(c, PR_CCS); 378 /* C flag is already at bit 0. */ 379 tcg_gen_andi_tl(c, c, C_FLAG); 380 tcg_gen_add_tl(d, d, c); 381 tcg_temp_free(c); 382 } 383 } else { 384 TCGv x, c; 385 386 x = tcg_temp_new(); 387 c = tcg_temp_new(); 388 t_gen_mov_TN_preg(x, PR_CCS); 389 tcg_gen_mov_tl(c, x); 390 391 /* Propagate carry into d if X is set. Branch free. */ 392 tcg_gen_andi_tl(c, c, C_FLAG); 393 tcg_gen_andi_tl(x, x, X_FLAG); 394 tcg_gen_shri_tl(x, x, 4); 395 396 tcg_gen_and_tl(x, x, c); 397 tcg_gen_add_tl(d, d, x); 398 tcg_temp_free(x); 399 tcg_temp_free(c); 400 } 401 } 402 403 static inline void t_gen_subx_carry(DisasContext *dc, TCGv d) 404 { 405 if (dc->flagx_known) { 406 if (dc->flags_x) { 407 TCGv c; 408 409 c = tcg_temp_new(); 410 t_gen_mov_TN_preg(c, PR_CCS); 411 /* C flag is already at bit 0. */ 412 tcg_gen_andi_tl(c, c, C_FLAG); 413 tcg_gen_sub_tl(d, d, c); 414 tcg_temp_free(c); 415 } 416 } else { 417 TCGv x, c; 418 419 x = tcg_temp_new(); 420 c = tcg_temp_new(); 421 t_gen_mov_TN_preg(x, PR_CCS); 422 tcg_gen_mov_tl(c, x); 423 424 /* Propagate carry into d if X is set. Branch free. */ 425 tcg_gen_andi_tl(c, c, C_FLAG); 426 tcg_gen_andi_tl(x, x, X_FLAG); 427 tcg_gen_shri_tl(x, x, 4); 428 429 tcg_gen_and_tl(x, x, c); 430 tcg_gen_sub_tl(d, d, x); 431 tcg_temp_free(x); 432 tcg_temp_free(c); 433 } 434 } 435 436 /* Swap the two bytes within each half word of the s operand. 437 T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */ 438 static inline void t_gen_swapb(TCGv d, TCGv s) 439 { 440 TCGv t, org_s; 441 442 t = tcg_temp_new(); 443 org_s = tcg_temp_new(); 444 445 /* d and s may refer to the same object. */ 446 tcg_gen_mov_tl(org_s, s); 447 tcg_gen_shli_tl(t, org_s, 8); 448 tcg_gen_andi_tl(d, t, 0xff00ff00); 449 tcg_gen_shri_tl(t, org_s, 8); 450 tcg_gen_andi_tl(t, t, 0x00ff00ff); 451 tcg_gen_or_tl(d, d, t); 452 tcg_temp_free(t); 453 tcg_temp_free(org_s); 454 } 455 456 /* Swap the halfwords of the s operand. */ 457 static inline void t_gen_swapw(TCGv d, TCGv s) 458 { 459 TCGv t; 460 /* d and s refer the same object. */ 461 t = tcg_temp_new(); 462 tcg_gen_mov_tl(t, s); 463 tcg_gen_shli_tl(d, t, 16); 464 tcg_gen_shri_tl(t, t, 16); 465 tcg_gen_or_tl(d, d, t); 466 tcg_temp_free(t); 467 } 468 469 /* Reverse the within each byte. 470 T0 = (((T0 << 7) & 0x80808080) | 471 ((T0 << 5) & 0x40404040) | 472 ((T0 << 3) & 0x20202020) | 473 ((T0 << 1) & 0x10101010) | 474 ((T0 >> 1) & 0x08080808) | 475 ((T0 >> 3) & 0x04040404) | 476 ((T0 >> 5) & 0x02020202) | 477 ((T0 >> 7) & 0x01010101)); 478 */ 479 static inline void t_gen_swapr(TCGv d, TCGv s) 480 { 481 struct { 482 int shift; /* LSL when positive, LSR when negative. */ 483 uint32_t mask; 484 } bitrev[] = { 485 {7, 0x80808080}, 486 {5, 0x40404040}, 487 {3, 0x20202020}, 488 {1, 0x10101010}, 489 {-1, 0x08080808}, 490 {-3, 0x04040404}, 491 {-5, 0x02020202}, 492 {-7, 0x01010101} 493 }; 494 int i; 495 TCGv t, org_s; 496 497 /* d and s refer the same object. */ 498 t = tcg_temp_new(); 499 org_s = tcg_temp_new(); 500 tcg_gen_mov_tl(org_s, s); 501 502 tcg_gen_shli_tl(t, org_s, bitrev[0].shift); 503 tcg_gen_andi_tl(d, t, bitrev[0].mask); 504 for (i = 1; i < ARRAY_SIZE(bitrev); i++) { 505 if (bitrev[i].shift >= 0) { 506 tcg_gen_shli_tl(t, org_s, bitrev[i].shift); 507 } else { 508 tcg_gen_shri_tl(t, org_s, -bitrev[i].shift); 509 } 510 tcg_gen_andi_tl(t, t, bitrev[i].mask); 511 tcg_gen_or_tl(d, d, t); 512 } 513 tcg_temp_free(t); 514 tcg_temp_free(org_s); 515 } 516 517 static void t_gen_cc_jmp(TCGv pc_true, TCGv pc_false) 518 { 519 TCGLabel *l1 = gen_new_label(); 520 521 /* Conditional jmp. */ 522 tcg_gen_mov_tl(env_pc, pc_false); 523 tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, l1); 524 tcg_gen_mov_tl(env_pc, pc_true); 525 gen_set_label(l1); 526 } 527 528 static inline bool use_goto_tb(DisasContext *dc, target_ulong dest) 529 { 530 #ifndef CONFIG_USER_ONLY 531 return (dc->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) || 532 (dc->ppc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); 533 #else 534 return true; 535 #endif 536 } 537 538 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) 539 { 540 if (use_goto_tb(dc, dest)) { 541 tcg_gen_goto_tb(n); 542 tcg_gen_movi_tl(env_pc, dest); 543 tcg_gen_exit_tb((uintptr_t)dc->tb + n); 544 } else { 545 tcg_gen_movi_tl(env_pc, dest); 546 tcg_gen_exit_tb(0); 547 } 548 } 549 550 static inline void cris_clear_x_flag(DisasContext *dc) 551 { 552 if (dc->flagx_known && dc->flags_x) { 553 dc->flags_uptodate = 0; 554 } 555 556 dc->flagx_known = 1; 557 dc->flags_x = 0; 558 } 559 560 static void cris_flush_cc_state(DisasContext *dc) 561 { 562 if (dc->cc_size_uptodate != dc->cc_size) { 563 tcg_gen_movi_tl(cc_size, dc->cc_size); 564 dc->cc_size_uptodate = dc->cc_size; 565 } 566 tcg_gen_movi_tl(cc_op, dc->cc_op); 567 tcg_gen_movi_tl(cc_mask, dc->cc_mask); 568 } 569 570 static void cris_evaluate_flags(DisasContext *dc) 571 { 572 if (dc->flags_uptodate) { 573 return; 574 } 575 576 cris_flush_cc_state(dc); 577 578 switch (dc->cc_op) { 579 case CC_OP_MCP: 580 gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS], cpu_env, 581 cpu_PR[PR_CCS], cc_src, 582 cc_dest, cc_result); 583 break; 584 case CC_OP_MULS: 585 gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS], cpu_env, 586 cpu_PR[PR_CCS], cc_result, 587 cpu_PR[PR_MOF]); 588 break; 589 case CC_OP_MULU: 590 gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS], cpu_env, 591 cpu_PR[PR_CCS], cc_result, 592 cpu_PR[PR_MOF]); 593 break; 594 case CC_OP_MOVE: 595 case CC_OP_AND: 596 case CC_OP_OR: 597 case CC_OP_XOR: 598 case CC_OP_ASR: 599 case CC_OP_LSR: 600 case CC_OP_LSL: 601 switch (dc->cc_size) { 602 case 4: 603 gen_helper_evaluate_flags_move_4(cpu_PR[PR_CCS], 604 cpu_env, cpu_PR[PR_CCS], cc_result); 605 break; 606 case 2: 607 gen_helper_evaluate_flags_move_2(cpu_PR[PR_CCS], 608 cpu_env, cpu_PR[PR_CCS], cc_result); 609 break; 610 default: 611 gen_helper_evaluate_flags(cpu_env); 612 break; 613 } 614 break; 615 case CC_OP_FLAGS: 616 /* live. */ 617 break; 618 case CC_OP_SUB: 619 case CC_OP_CMP: 620 if (dc->cc_size == 4) { 621 gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS], cpu_env, 622 cpu_PR[PR_CCS], cc_src, cc_dest, cc_result); 623 } else { 624 gen_helper_evaluate_flags(cpu_env); 625 } 626 627 break; 628 default: 629 switch (dc->cc_size) { 630 case 4: 631 gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS], cpu_env, 632 cpu_PR[PR_CCS], cc_src, cc_dest, cc_result); 633 break; 634 default: 635 gen_helper_evaluate_flags(cpu_env); 636 break; 637 } 638 break; 639 } 640 641 if (dc->flagx_known) { 642 if (dc->flags_x) { 643 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], X_FLAG); 644 } else if (dc->cc_op == CC_OP_FLAGS) { 645 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~X_FLAG); 646 } 647 } 648 dc->flags_uptodate = 1; 649 } 650 651 static void cris_cc_mask(DisasContext *dc, unsigned int mask) 652 { 653 uint32_t ovl; 654 655 if (!mask) { 656 dc->update_cc = 0; 657 return; 658 } 659 660 /* Check if we need to evaluate the condition codes due to 661 CC overlaying. */ 662 ovl = (dc->cc_mask ^ mask) & ~mask; 663 if (ovl) { 664 /* TODO: optimize this case. It trigs all the time. */ 665 cris_evaluate_flags(dc); 666 } 667 dc->cc_mask = mask; 668 dc->update_cc = 1; 669 } 670 671 static void cris_update_cc_op(DisasContext *dc, int op, int size) 672 { 673 dc->cc_op = op; 674 dc->cc_size = size; 675 dc->flags_uptodate = 0; 676 } 677 678 static inline void cris_update_cc_x(DisasContext *dc) 679 { 680 /* Save the x flag state at the time of the cc snapshot. */ 681 if (dc->flagx_known) { 682 if (dc->cc_x_uptodate == (2 | dc->flags_x)) { 683 return; 684 } 685 tcg_gen_movi_tl(cc_x, dc->flags_x); 686 dc->cc_x_uptodate = 2 | dc->flags_x; 687 } else { 688 tcg_gen_andi_tl(cc_x, cpu_PR[PR_CCS], X_FLAG); 689 dc->cc_x_uptodate = 1; 690 } 691 } 692 693 /* Update cc prior to executing ALU op. Needs source operands untouched. */ 694 static void cris_pre_alu_update_cc(DisasContext *dc, int op, 695 TCGv dst, TCGv src, int size) 696 { 697 if (dc->update_cc) { 698 cris_update_cc_op(dc, op, size); 699 tcg_gen_mov_tl(cc_src, src); 700 701 if (op != CC_OP_MOVE 702 && op != CC_OP_AND 703 && op != CC_OP_OR 704 && op != CC_OP_XOR 705 && op != CC_OP_ASR 706 && op != CC_OP_LSR 707 && op != CC_OP_LSL) { 708 tcg_gen_mov_tl(cc_dest, dst); 709 } 710 711 cris_update_cc_x(dc); 712 } 713 } 714 715 /* Update cc after executing ALU op. needs the result. */ 716 static inline void cris_update_result(DisasContext *dc, TCGv res) 717 { 718 if (dc->update_cc) { 719 tcg_gen_mov_tl(cc_result, res); 720 } 721 } 722 723 /* Returns one if the write back stage should execute. */ 724 static void cris_alu_op_exec(DisasContext *dc, int op, 725 TCGv dst, TCGv a, TCGv b, int size) 726 { 727 /* Emit the ALU insns. */ 728 switch (op) { 729 case CC_OP_ADD: 730 tcg_gen_add_tl(dst, a, b); 731 /* Extended arithmetics. */ 732 t_gen_addx_carry(dc, dst); 733 break; 734 case CC_OP_ADDC: 735 tcg_gen_add_tl(dst, a, b); 736 t_gen_add_flag(dst, 0); /* C_FLAG. */ 737 break; 738 case CC_OP_MCP: 739 tcg_gen_add_tl(dst, a, b); 740 t_gen_add_flag(dst, 8); /* R_FLAG. */ 741 break; 742 case CC_OP_SUB: 743 tcg_gen_sub_tl(dst, a, b); 744 /* Extended arithmetics. */ 745 t_gen_subx_carry(dc, dst); 746 break; 747 case CC_OP_MOVE: 748 tcg_gen_mov_tl(dst, b); 749 break; 750 case CC_OP_OR: 751 tcg_gen_or_tl(dst, a, b); 752 break; 753 case CC_OP_AND: 754 tcg_gen_and_tl(dst, a, b); 755 break; 756 case CC_OP_XOR: 757 tcg_gen_xor_tl(dst, a, b); 758 break; 759 case CC_OP_LSL: 760 t_gen_lsl(dst, a, b); 761 break; 762 case CC_OP_LSR: 763 t_gen_lsr(dst, a, b); 764 break; 765 case CC_OP_ASR: 766 t_gen_asr(dst, a, b); 767 break; 768 case CC_OP_NEG: 769 tcg_gen_neg_tl(dst, b); 770 /* Extended arithmetics. */ 771 t_gen_subx_carry(dc, dst); 772 break; 773 case CC_OP_LZ: 774 tcg_gen_clzi_tl(dst, b, TARGET_LONG_BITS); 775 break; 776 case CC_OP_MULS: 777 tcg_gen_muls2_tl(dst, cpu_PR[PR_MOF], a, b); 778 break; 779 case CC_OP_MULU: 780 tcg_gen_mulu2_tl(dst, cpu_PR[PR_MOF], a, b); 781 break; 782 case CC_OP_DSTEP: 783 t_gen_cris_dstep(dst, a, b); 784 break; 785 case CC_OP_MSTEP: 786 t_gen_cris_mstep(dst, a, b, cpu_PR[PR_CCS]); 787 break; 788 case CC_OP_BOUND: 789 tcg_gen_movcond_tl(TCG_COND_LEU, dst, a, b, a, b); 790 break; 791 case CC_OP_CMP: 792 tcg_gen_sub_tl(dst, a, b); 793 /* Extended arithmetics. */ 794 t_gen_subx_carry(dc, dst); 795 break; 796 default: 797 qemu_log_mask(LOG_GUEST_ERROR, "illegal ALU op.\n"); 798 BUG(); 799 break; 800 } 801 802 if (size == 1) { 803 tcg_gen_andi_tl(dst, dst, 0xff); 804 } else if (size == 2) { 805 tcg_gen_andi_tl(dst, dst, 0xffff); 806 } 807 } 808 809 static void cris_alu(DisasContext *dc, int op, 810 TCGv d, TCGv op_a, TCGv op_b, int size) 811 { 812 TCGv tmp; 813 int writeback; 814 815 writeback = 1; 816 817 if (op == CC_OP_CMP) { 818 tmp = tcg_temp_new(); 819 writeback = 0; 820 } else if (size == 4) { 821 tmp = d; 822 writeback = 0; 823 } else { 824 tmp = tcg_temp_new(); 825 } 826 827 828 cris_pre_alu_update_cc(dc, op, op_a, op_b, size); 829 cris_alu_op_exec(dc, op, tmp, op_a, op_b, size); 830 cris_update_result(dc, tmp); 831 832 /* Writeback. */ 833 if (writeback) { 834 if (size == 1) { 835 tcg_gen_andi_tl(d, d, ~0xff); 836 } else { 837 tcg_gen_andi_tl(d, d, ~0xffff); 838 } 839 tcg_gen_or_tl(d, d, tmp); 840 } 841 if (tmp != d) { 842 tcg_temp_free(tmp); 843 } 844 } 845 846 static int arith_cc(DisasContext *dc) 847 { 848 if (dc->update_cc) { 849 switch (dc->cc_op) { 850 case CC_OP_ADDC: return 1; 851 case CC_OP_ADD: return 1; 852 case CC_OP_SUB: return 1; 853 case CC_OP_DSTEP: return 1; 854 case CC_OP_LSL: return 1; 855 case CC_OP_LSR: return 1; 856 case CC_OP_ASR: return 1; 857 case CC_OP_CMP: return 1; 858 case CC_OP_NEG: return 1; 859 case CC_OP_OR: return 1; 860 case CC_OP_AND: return 1; 861 case CC_OP_XOR: return 1; 862 case CC_OP_MULU: return 1; 863 case CC_OP_MULS: return 1; 864 default: 865 return 0; 866 } 867 } 868 return 0; 869 } 870 871 static void gen_tst_cc (DisasContext *dc, TCGv cc, int cond) 872 { 873 int arith_opt, move_opt; 874 875 /* TODO: optimize more condition codes. */ 876 877 /* 878 * If the flags are live, we've gotta look into the bits of CCS. 879 * Otherwise, if we just did an arithmetic operation we try to 880 * evaluate the condition code faster. 881 * 882 * When this function is done, T0 should be non-zero if the condition 883 * code is true. 884 */ 885 arith_opt = arith_cc(dc) && !dc->flags_uptodate; 886 move_opt = (dc->cc_op == CC_OP_MOVE); 887 switch (cond) { 888 case CC_EQ: 889 if ((arith_opt || move_opt) 890 && dc->cc_x_uptodate != (2 | X_FLAG)) { 891 tcg_gen_setcond_tl(TCG_COND_EQ, cc, 892 cc_result, tcg_const_tl(0)); 893 } else { 894 cris_evaluate_flags(dc); 895 tcg_gen_andi_tl(cc, 896 cpu_PR[PR_CCS], Z_FLAG); 897 } 898 break; 899 case CC_NE: 900 if ((arith_opt || move_opt) 901 && dc->cc_x_uptodate != (2 | X_FLAG)) { 902 tcg_gen_mov_tl(cc, cc_result); 903 } else { 904 cris_evaluate_flags(dc); 905 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS], 906 Z_FLAG); 907 tcg_gen_andi_tl(cc, cc, Z_FLAG); 908 } 909 break; 910 case CC_CS: 911 cris_evaluate_flags(dc); 912 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], C_FLAG); 913 break; 914 case CC_CC: 915 cris_evaluate_flags(dc); 916 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS], C_FLAG); 917 tcg_gen_andi_tl(cc, cc, C_FLAG); 918 break; 919 case CC_VS: 920 cris_evaluate_flags(dc); 921 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], V_FLAG); 922 break; 923 case CC_VC: 924 cris_evaluate_flags(dc); 925 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS], 926 V_FLAG); 927 tcg_gen_andi_tl(cc, cc, V_FLAG); 928 break; 929 case CC_PL: 930 if (arith_opt || move_opt) { 931 int bits = 31; 932 933 if (dc->cc_size == 1) { 934 bits = 7; 935 } else if (dc->cc_size == 2) { 936 bits = 15; 937 } 938 939 tcg_gen_shri_tl(cc, cc_result, bits); 940 tcg_gen_xori_tl(cc, cc, 1); 941 } else { 942 cris_evaluate_flags(dc); 943 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS], 944 N_FLAG); 945 tcg_gen_andi_tl(cc, cc, N_FLAG); 946 } 947 break; 948 case CC_MI: 949 if (arith_opt || move_opt) { 950 int bits = 31; 951 952 if (dc->cc_size == 1) { 953 bits = 7; 954 } else if (dc->cc_size == 2) { 955 bits = 15; 956 } 957 958 tcg_gen_shri_tl(cc, cc_result, bits); 959 tcg_gen_andi_tl(cc, cc, 1); 960 } else { 961 cris_evaluate_flags(dc); 962 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], 963 N_FLAG); 964 } 965 break; 966 case CC_LS: 967 cris_evaluate_flags(dc); 968 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], 969 C_FLAG | Z_FLAG); 970 break; 971 case CC_HI: 972 cris_evaluate_flags(dc); 973 { 974 TCGv tmp; 975 976 tmp = tcg_temp_new(); 977 tcg_gen_xori_tl(tmp, cpu_PR[PR_CCS], 978 C_FLAG | Z_FLAG); 979 /* Overlay the C flag on top of the Z. */ 980 tcg_gen_shli_tl(cc, tmp, 2); 981 tcg_gen_and_tl(cc, tmp, cc); 982 tcg_gen_andi_tl(cc, cc, Z_FLAG); 983 984 tcg_temp_free(tmp); 985 } 986 break; 987 case CC_GE: 988 cris_evaluate_flags(dc); 989 /* Overlay the V flag on top of the N. */ 990 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2); 991 tcg_gen_xor_tl(cc, 992 cpu_PR[PR_CCS], cc); 993 tcg_gen_andi_tl(cc, cc, N_FLAG); 994 tcg_gen_xori_tl(cc, cc, N_FLAG); 995 break; 996 case CC_LT: 997 cris_evaluate_flags(dc); 998 /* Overlay the V flag on top of the N. */ 999 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2); 1000 tcg_gen_xor_tl(cc, 1001 cpu_PR[PR_CCS], cc); 1002 tcg_gen_andi_tl(cc, cc, N_FLAG); 1003 break; 1004 case CC_GT: 1005 cris_evaluate_flags(dc); 1006 { 1007 TCGv n, z; 1008 1009 n = tcg_temp_new(); 1010 z = tcg_temp_new(); 1011 1012 /* To avoid a shift we overlay everything on 1013 the V flag. */ 1014 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2); 1015 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1); 1016 /* invert Z. */ 1017 tcg_gen_xori_tl(z, z, 2); 1018 1019 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]); 1020 tcg_gen_xori_tl(n, n, 2); 1021 tcg_gen_and_tl(cc, z, n); 1022 tcg_gen_andi_tl(cc, cc, 2); 1023 1024 tcg_temp_free(n); 1025 tcg_temp_free(z); 1026 } 1027 break; 1028 case CC_LE: 1029 cris_evaluate_flags(dc); 1030 { 1031 TCGv n, z; 1032 1033 n = tcg_temp_new(); 1034 z = tcg_temp_new(); 1035 1036 /* To avoid a shift we overlay everything on 1037 the V flag. */ 1038 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2); 1039 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1); 1040 1041 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]); 1042 tcg_gen_or_tl(cc, z, n); 1043 tcg_gen_andi_tl(cc, cc, 2); 1044 1045 tcg_temp_free(n); 1046 tcg_temp_free(z); 1047 } 1048 break; 1049 case CC_P: 1050 cris_evaluate_flags(dc); 1051 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], P_FLAG); 1052 break; 1053 case CC_A: 1054 tcg_gen_movi_tl(cc, 1); 1055 break; 1056 default: 1057 BUG(); 1058 break; 1059 }; 1060 } 1061 1062 static void cris_store_direct_jmp(DisasContext *dc) 1063 { 1064 /* Store the direct jmp state into the cpu-state. */ 1065 if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) { 1066 if (dc->jmp == JMP_DIRECT) { 1067 tcg_gen_movi_tl(env_btaken, 1); 1068 } 1069 tcg_gen_movi_tl(env_btarget, dc->jmp_pc); 1070 dc->jmp = JMP_INDIRECT; 1071 } 1072 } 1073 1074 static void cris_prepare_cc_branch (DisasContext *dc, 1075 int offset, int cond) 1076 { 1077 /* This helps us re-schedule the micro-code to insns in delay-slots 1078 before the actual jump. */ 1079 dc->delayed_branch = 2; 1080 dc->jmp = JMP_DIRECT_CC; 1081 dc->jmp_pc = dc->pc + offset; 1082 1083 gen_tst_cc(dc, env_btaken, cond); 1084 tcg_gen_movi_tl(env_btarget, dc->jmp_pc); 1085 } 1086 1087 1088 /* jumps, when the dest is in a live reg for example. Direct should be set 1089 when the dest addr is constant to allow tb chaining. */ 1090 static inline void cris_prepare_jmp (DisasContext *dc, unsigned int type) 1091 { 1092 /* This helps us re-schedule the micro-code to insns in delay-slots 1093 before the actual jump. */ 1094 dc->delayed_branch = 2; 1095 dc->jmp = type; 1096 if (type == JMP_INDIRECT) { 1097 tcg_gen_movi_tl(env_btaken, 1); 1098 } 1099 } 1100 1101 static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr) 1102 { 1103 int mem_index = cpu_mmu_index(&dc->cpu->env, false); 1104 1105 /* If we get a fault on a delayslot we must keep the jmp state in 1106 the cpu-state to be able to re-execute the jmp. */ 1107 if (dc->delayed_branch == 1) { 1108 cris_store_direct_jmp(dc); 1109 } 1110 1111 tcg_gen_qemu_ld_i64(dst, addr, mem_index, MO_TEQ); 1112 } 1113 1114 static void gen_load(DisasContext *dc, TCGv dst, TCGv addr, 1115 unsigned int size, int sign) 1116 { 1117 int mem_index = cpu_mmu_index(&dc->cpu->env, false); 1118 1119 /* If we get a fault on a delayslot we must keep the jmp state in 1120 the cpu-state to be able to re-execute the jmp. */ 1121 if (dc->delayed_branch == 1) { 1122 cris_store_direct_jmp(dc); 1123 } 1124 1125 tcg_gen_qemu_ld_tl(dst, addr, mem_index, 1126 MO_TE + ctz32(size) + (sign ? MO_SIGN : 0)); 1127 } 1128 1129 static void gen_store (DisasContext *dc, TCGv addr, TCGv val, 1130 unsigned int size) 1131 { 1132 int mem_index = cpu_mmu_index(&dc->cpu->env, false); 1133 1134 /* If we get a fault on a delayslot we must keep the jmp state in 1135 the cpu-state to be able to re-execute the jmp. */ 1136 if (dc->delayed_branch == 1) { 1137 cris_store_direct_jmp(dc); 1138 } 1139 1140 1141 /* Conditional writes. We only support the kind were X and P are known 1142 at translation time. */ 1143 if (dc->flagx_known && dc->flags_x && (dc->tb_flags & P_FLAG)) { 1144 dc->postinc = 0; 1145 cris_evaluate_flags(dc); 1146 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], C_FLAG); 1147 return; 1148 } 1149 1150 tcg_gen_qemu_st_tl(val, addr, mem_index, MO_TE + ctz32(size)); 1151 1152 if (dc->flagx_known && dc->flags_x) { 1153 cris_evaluate_flags(dc); 1154 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~C_FLAG); 1155 } 1156 } 1157 1158 static inline void t_gen_sext(TCGv d, TCGv s, int size) 1159 { 1160 if (size == 1) { 1161 tcg_gen_ext8s_i32(d, s); 1162 } else if (size == 2) { 1163 tcg_gen_ext16s_i32(d, s); 1164 } else { 1165 tcg_gen_mov_tl(d, s); 1166 } 1167 } 1168 1169 static inline void t_gen_zext(TCGv d, TCGv s, int size) 1170 { 1171 if (size == 1) { 1172 tcg_gen_ext8u_i32(d, s); 1173 } else if (size == 2) { 1174 tcg_gen_ext16u_i32(d, s); 1175 } else { 1176 tcg_gen_mov_tl(d, s); 1177 } 1178 } 1179 1180 #if DISAS_CRIS 1181 static char memsize_char(int size) 1182 { 1183 switch (size) { 1184 case 1: return 'b'; break; 1185 case 2: return 'w'; break; 1186 case 4: return 'd'; break; 1187 default: 1188 return 'x'; 1189 break; 1190 } 1191 } 1192 #endif 1193 1194 static inline unsigned int memsize_z(DisasContext *dc) 1195 { 1196 return dc->zsize + 1; 1197 } 1198 1199 static inline unsigned int memsize_zz(DisasContext *dc) 1200 { 1201 switch (dc->zzsize) { 1202 case 0: return 1; 1203 case 1: return 2; 1204 default: 1205 return 4; 1206 } 1207 } 1208 1209 static inline void do_postinc (DisasContext *dc, int size) 1210 { 1211 if (dc->postinc) { 1212 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size); 1213 } 1214 } 1215 1216 static inline void dec_prep_move_r(DisasContext *dc, int rs, int rd, 1217 int size, int s_ext, TCGv dst) 1218 { 1219 if (s_ext) { 1220 t_gen_sext(dst, cpu_R[rs], size); 1221 } else { 1222 t_gen_zext(dst, cpu_R[rs], size); 1223 } 1224 } 1225 1226 /* Prepare T0 and T1 for a register alu operation. 1227 s_ext decides if the operand1 should be sign-extended or zero-extended when 1228 needed. */ 1229 static void dec_prep_alu_r(DisasContext *dc, int rs, int rd, 1230 int size, int s_ext, TCGv dst, TCGv src) 1231 { 1232 dec_prep_move_r(dc, rs, rd, size, s_ext, src); 1233 1234 if (s_ext) { 1235 t_gen_sext(dst, cpu_R[rd], size); 1236 } else { 1237 t_gen_zext(dst, cpu_R[rd], size); 1238 } 1239 } 1240 1241 static int dec_prep_move_m(CPUCRISState *env, DisasContext *dc, 1242 int s_ext, int memsize, TCGv dst) 1243 { 1244 unsigned int rs; 1245 uint32_t imm; 1246 int is_imm; 1247 int insn_len = 2; 1248 1249 rs = dc->op1; 1250 is_imm = rs == 15 && dc->postinc; 1251 1252 /* Load [$rs] onto T1. */ 1253 if (is_imm) { 1254 insn_len = 2 + memsize; 1255 if (memsize == 1) { 1256 insn_len++; 1257 } 1258 1259 imm = cris_fetch(env, dc, dc->pc + 2, memsize, s_ext); 1260 tcg_gen_movi_tl(dst, imm); 1261 dc->postinc = 0; 1262 } else { 1263 cris_flush_cc_state(dc); 1264 gen_load(dc, dst, cpu_R[rs], memsize, 0); 1265 if (s_ext) { 1266 t_gen_sext(dst, dst, memsize); 1267 } else { 1268 t_gen_zext(dst, dst, memsize); 1269 } 1270 } 1271 return insn_len; 1272 } 1273 1274 /* Prepare T0 and T1 for a memory + alu operation. 1275 s_ext decides if the operand1 should be sign-extended or zero-extended when 1276 needed. */ 1277 static int dec_prep_alu_m(CPUCRISState *env, DisasContext *dc, 1278 int s_ext, int memsize, TCGv dst, TCGv src) 1279 { 1280 int insn_len; 1281 1282 insn_len = dec_prep_move_m(env, dc, s_ext, memsize, src); 1283 tcg_gen_mov_tl(dst, cpu_R[dc->op2]); 1284 return insn_len; 1285 } 1286 1287 #if DISAS_CRIS 1288 static const char *cc_name(int cc) 1289 { 1290 static const char *cc_names[16] = { 1291 "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi", 1292 "ls", "hi", "ge", "lt", "gt", "le", "a", "p" 1293 }; 1294 assert(cc < 16); 1295 return cc_names[cc]; 1296 } 1297 #endif 1298 1299 /* Start of insn decoders. */ 1300 1301 static int dec_bccq(CPUCRISState *env, DisasContext *dc) 1302 { 1303 int32_t offset; 1304 int sign; 1305 uint32_t cond = dc->op2; 1306 1307 offset = EXTRACT_FIELD(dc->ir, 1, 7); 1308 sign = EXTRACT_FIELD(dc->ir, 0, 0); 1309 1310 offset *= 2; 1311 offset |= sign << 8; 1312 offset = sign_extend(offset, 8); 1313 1314 LOG_DIS("b%s %x\n", cc_name(cond), dc->pc + offset); 1315 1316 /* op2 holds the condition-code. */ 1317 cris_cc_mask(dc, 0); 1318 cris_prepare_cc_branch(dc, offset, cond); 1319 return 2; 1320 } 1321 static int dec_addoq(CPUCRISState *env, DisasContext *dc) 1322 { 1323 int32_t imm; 1324 1325 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7); 1326 imm = sign_extend(dc->op1, 7); 1327 1328 LOG_DIS("addoq %d, $r%u\n", imm, dc->op2); 1329 cris_cc_mask(dc, 0); 1330 /* Fetch register operand, */ 1331 tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm); 1332 1333 return 2; 1334 } 1335 static int dec_addq(CPUCRISState *env, DisasContext *dc) 1336 { 1337 LOG_DIS("addq %u, $r%u\n", dc->op1, dc->op2); 1338 1339 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); 1340 1341 cris_cc_mask(dc, CC_MASK_NZVC); 1342 1343 cris_alu(dc, CC_OP_ADD, 1344 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4); 1345 return 2; 1346 } 1347 static int dec_moveq(CPUCRISState *env, DisasContext *dc) 1348 { 1349 uint32_t imm; 1350 1351 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); 1352 imm = sign_extend(dc->op1, 5); 1353 LOG_DIS("moveq %d, $r%u\n", imm, dc->op2); 1354 1355 tcg_gen_movi_tl(cpu_R[dc->op2], imm); 1356 return 2; 1357 } 1358 static int dec_subq(CPUCRISState *env, DisasContext *dc) 1359 { 1360 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); 1361 1362 LOG_DIS("subq %u, $r%u\n", dc->op1, dc->op2); 1363 1364 cris_cc_mask(dc, CC_MASK_NZVC); 1365 cris_alu(dc, CC_OP_SUB, 1366 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4); 1367 return 2; 1368 } 1369 static int dec_cmpq(CPUCRISState *env, DisasContext *dc) 1370 { 1371 uint32_t imm; 1372 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); 1373 imm = sign_extend(dc->op1, 5); 1374 1375 LOG_DIS("cmpq %d, $r%d\n", imm, dc->op2); 1376 cris_cc_mask(dc, CC_MASK_NZVC); 1377 1378 cris_alu(dc, CC_OP_CMP, 1379 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4); 1380 return 2; 1381 } 1382 static int dec_andq(CPUCRISState *env, DisasContext *dc) 1383 { 1384 uint32_t imm; 1385 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); 1386 imm = sign_extend(dc->op1, 5); 1387 1388 LOG_DIS("andq %d, $r%d\n", imm, dc->op2); 1389 cris_cc_mask(dc, CC_MASK_NZ); 1390 1391 cris_alu(dc, CC_OP_AND, 1392 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4); 1393 return 2; 1394 } 1395 static int dec_orq(CPUCRISState *env, DisasContext *dc) 1396 { 1397 uint32_t imm; 1398 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); 1399 imm = sign_extend(dc->op1, 5); 1400 LOG_DIS("orq %d, $r%d\n", imm, dc->op2); 1401 cris_cc_mask(dc, CC_MASK_NZ); 1402 1403 cris_alu(dc, CC_OP_OR, 1404 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4); 1405 return 2; 1406 } 1407 static int dec_btstq(CPUCRISState *env, DisasContext *dc) 1408 { 1409 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4); 1410 LOG_DIS("btstq %u, $r%d\n", dc->op1, dc->op2); 1411 1412 cris_cc_mask(dc, CC_MASK_NZ); 1413 cris_evaluate_flags(dc); 1414 gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2], 1415 tcg_const_tl(dc->op1), cpu_PR[PR_CCS]); 1416 cris_alu(dc, CC_OP_MOVE, 1417 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4); 1418 cris_update_cc_op(dc, CC_OP_FLAGS, 4); 1419 dc->flags_uptodate = 1; 1420 return 2; 1421 } 1422 static int dec_asrq(CPUCRISState *env, DisasContext *dc) 1423 { 1424 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4); 1425 LOG_DIS("asrq %u, $r%d\n", dc->op1, dc->op2); 1426 cris_cc_mask(dc, CC_MASK_NZ); 1427 1428 tcg_gen_sari_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1); 1429 cris_alu(dc, CC_OP_MOVE, 1430 cpu_R[dc->op2], 1431 cpu_R[dc->op2], cpu_R[dc->op2], 4); 1432 return 2; 1433 } 1434 static int dec_lslq(CPUCRISState *env, DisasContext *dc) 1435 { 1436 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4); 1437 LOG_DIS("lslq %u, $r%d\n", dc->op1, dc->op2); 1438 1439 cris_cc_mask(dc, CC_MASK_NZ); 1440 1441 tcg_gen_shli_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1); 1442 1443 cris_alu(dc, CC_OP_MOVE, 1444 cpu_R[dc->op2], 1445 cpu_R[dc->op2], cpu_R[dc->op2], 4); 1446 return 2; 1447 } 1448 static int dec_lsrq(CPUCRISState *env, DisasContext *dc) 1449 { 1450 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4); 1451 LOG_DIS("lsrq %u, $r%d\n", dc->op1, dc->op2); 1452 1453 cris_cc_mask(dc, CC_MASK_NZ); 1454 1455 tcg_gen_shri_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1); 1456 cris_alu(dc, CC_OP_MOVE, 1457 cpu_R[dc->op2], 1458 cpu_R[dc->op2], cpu_R[dc->op2], 4); 1459 return 2; 1460 } 1461 1462 static int dec_move_r(CPUCRISState *env, DisasContext *dc) 1463 { 1464 int size = memsize_zz(dc); 1465 1466 LOG_DIS("move.%c $r%u, $r%u\n", 1467 memsize_char(size), dc->op1, dc->op2); 1468 1469 cris_cc_mask(dc, CC_MASK_NZ); 1470 if (size == 4) { 1471 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_R[dc->op2]); 1472 cris_cc_mask(dc, CC_MASK_NZ); 1473 cris_update_cc_op(dc, CC_OP_MOVE, 4); 1474 cris_update_cc_x(dc); 1475 cris_update_result(dc, cpu_R[dc->op2]); 1476 } else { 1477 TCGv t0; 1478 1479 t0 = tcg_temp_new(); 1480 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0); 1481 cris_alu(dc, CC_OP_MOVE, 1482 cpu_R[dc->op2], 1483 cpu_R[dc->op2], t0, size); 1484 tcg_temp_free(t0); 1485 } 1486 return 2; 1487 } 1488 1489 static int dec_scc_r(CPUCRISState *env, DisasContext *dc) 1490 { 1491 int cond = dc->op2; 1492 1493 LOG_DIS("s%s $r%u\n", 1494 cc_name(cond), dc->op1); 1495 1496 gen_tst_cc(dc, cpu_R[dc->op1], cond); 1497 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_R[dc->op1], cpu_R[dc->op1], 0); 1498 1499 cris_cc_mask(dc, 0); 1500 return 2; 1501 } 1502 1503 static inline void cris_alu_alloc_temps(DisasContext *dc, int size, TCGv *t) 1504 { 1505 if (size == 4) { 1506 t[0] = cpu_R[dc->op2]; 1507 t[1] = cpu_R[dc->op1]; 1508 } else { 1509 t[0] = tcg_temp_new(); 1510 t[1] = tcg_temp_new(); 1511 } 1512 } 1513 1514 static inline void cris_alu_free_temps(DisasContext *dc, int size, TCGv *t) 1515 { 1516 if (size != 4) { 1517 tcg_temp_free(t[0]); 1518 tcg_temp_free(t[1]); 1519 } 1520 } 1521 1522 static int dec_and_r(CPUCRISState *env, DisasContext *dc) 1523 { 1524 TCGv t[2]; 1525 int size = memsize_zz(dc); 1526 1527 LOG_DIS("and.%c $r%u, $r%u\n", 1528 memsize_char(size), dc->op1, dc->op2); 1529 1530 cris_cc_mask(dc, CC_MASK_NZ); 1531 1532 cris_alu_alloc_temps(dc, size, t); 1533 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); 1534 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], size); 1535 cris_alu_free_temps(dc, size, t); 1536 return 2; 1537 } 1538 1539 static int dec_lz_r(CPUCRISState *env, DisasContext *dc) 1540 { 1541 TCGv t0; 1542 LOG_DIS("lz $r%u, $r%u\n", 1543 dc->op1, dc->op2); 1544 cris_cc_mask(dc, CC_MASK_NZ); 1545 t0 = tcg_temp_new(); 1546 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0, cpu_R[dc->op2], t0); 1547 cris_alu(dc, CC_OP_LZ, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4); 1548 tcg_temp_free(t0); 1549 return 2; 1550 } 1551 1552 static int dec_lsl_r(CPUCRISState *env, DisasContext *dc) 1553 { 1554 TCGv t[2]; 1555 int size = memsize_zz(dc); 1556 1557 LOG_DIS("lsl.%c $r%u, $r%u\n", 1558 memsize_char(size), dc->op1, dc->op2); 1559 1560 cris_cc_mask(dc, CC_MASK_NZ); 1561 cris_alu_alloc_temps(dc, size, t); 1562 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); 1563 tcg_gen_andi_tl(t[1], t[1], 63); 1564 cris_alu(dc, CC_OP_LSL, cpu_R[dc->op2], t[0], t[1], size); 1565 cris_alu_alloc_temps(dc, size, t); 1566 return 2; 1567 } 1568 1569 static int dec_lsr_r(CPUCRISState *env, DisasContext *dc) 1570 { 1571 TCGv t[2]; 1572 int size = memsize_zz(dc); 1573 1574 LOG_DIS("lsr.%c $r%u, $r%u\n", 1575 memsize_char(size), dc->op1, dc->op2); 1576 1577 cris_cc_mask(dc, CC_MASK_NZ); 1578 cris_alu_alloc_temps(dc, size, t); 1579 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); 1580 tcg_gen_andi_tl(t[1], t[1], 63); 1581 cris_alu(dc, CC_OP_LSR, cpu_R[dc->op2], t[0], t[1], size); 1582 cris_alu_free_temps(dc, size, t); 1583 return 2; 1584 } 1585 1586 static int dec_asr_r(CPUCRISState *env, DisasContext *dc) 1587 { 1588 TCGv t[2]; 1589 int size = memsize_zz(dc); 1590 1591 LOG_DIS("asr.%c $r%u, $r%u\n", 1592 memsize_char(size), dc->op1, dc->op2); 1593 1594 cris_cc_mask(dc, CC_MASK_NZ); 1595 cris_alu_alloc_temps(dc, size, t); 1596 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]); 1597 tcg_gen_andi_tl(t[1], t[1], 63); 1598 cris_alu(dc, CC_OP_ASR, cpu_R[dc->op2], t[0], t[1], size); 1599 cris_alu_free_temps(dc, size, t); 1600 return 2; 1601 } 1602 1603 static int dec_muls_r(CPUCRISState *env, DisasContext *dc) 1604 { 1605 TCGv t[2]; 1606 int size = memsize_zz(dc); 1607 1608 LOG_DIS("muls.%c $r%u, $r%u\n", 1609 memsize_char(size), dc->op1, dc->op2); 1610 cris_cc_mask(dc, CC_MASK_NZV); 1611 cris_alu_alloc_temps(dc, size, t); 1612 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]); 1613 1614 cris_alu(dc, CC_OP_MULS, cpu_R[dc->op2], t[0], t[1], 4); 1615 cris_alu_free_temps(dc, size, t); 1616 return 2; 1617 } 1618 1619 static int dec_mulu_r(CPUCRISState *env, DisasContext *dc) 1620 { 1621 TCGv t[2]; 1622 int size = memsize_zz(dc); 1623 1624 LOG_DIS("mulu.%c $r%u, $r%u\n", 1625 memsize_char(size), dc->op1, dc->op2); 1626 cris_cc_mask(dc, CC_MASK_NZV); 1627 cris_alu_alloc_temps(dc, size, t); 1628 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); 1629 1630 cris_alu(dc, CC_OP_MULU, cpu_R[dc->op2], t[0], t[1], 4); 1631 cris_alu_alloc_temps(dc, size, t); 1632 return 2; 1633 } 1634 1635 1636 static int dec_dstep_r(CPUCRISState *env, DisasContext *dc) 1637 { 1638 LOG_DIS("dstep $r%u, $r%u\n", dc->op1, dc->op2); 1639 cris_cc_mask(dc, CC_MASK_NZ); 1640 cris_alu(dc, CC_OP_DSTEP, 1641 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4); 1642 return 2; 1643 } 1644 1645 static int dec_xor_r(CPUCRISState *env, DisasContext *dc) 1646 { 1647 TCGv t[2]; 1648 int size = memsize_zz(dc); 1649 LOG_DIS("xor.%c $r%u, $r%u\n", 1650 memsize_char(size), dc->op1, dc->op2); 1651 BUG_ON(size != 4); /* xor is dword. */ 1652 cris_cc_mask(dc, CC_MASK_NZ); 1653 cris_alu_alloc_temps(dc, size, t); 1654 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); 1655 1656 cris_alu(dc, CC_OP_XOR, cpu_R[dc->op2], t[0], t[1], 4); 1657 cris_alu_free_temps(dc, size, t); 1658 return 2; 1659 } 1660 1661 static int dec_bound_r(CPUCRISState *env, DisasContext *dc) 1662 { 1663 TCGv l0; 1664 int size = memsize_zz(dc); 1665 LOG_DIS("bound.%c $r%u, $r%u\n", 1666 memsize_char(size), dc->op1, dc->op2); 1667 cris_cc_mask(dc, CC_MASK_NZ); 1668 l0 = tcg_temp_local_new(); 1669 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, l0); 1670 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], cpu_R[dc->op2], l0, 4); 1671 tcg_temp_free(l0); 1672 return 2; 1673 } 1674 1675 static int dec_cmp_r(CPUCRISState *env, DisasContext *dc) 1676 { 1677 TCGv t[2]; 1678 int size = memsize_zz(dc); 1679 LOG_DIS("cmp.%c $r%u, $r%u\n", 1680 memsize_char(size), dc->op1, dc->op2); 1681 cris_cc_mask(dc, CC_MASK_NZVC); 1682 cris_alu_alloc_temps(dc, size, t); 1683 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); 1684 1685 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], t[0], t[1], size); 1686 cris_alu_free_temps(dc, size, t); 1687 return 2; 1688 } 1689 1690 static int dec_abs_r(CPUCRISState *env, DisasContext *dc) 1691 { 1692 TCGv t0; 1693 1694 LOG_DIS("abs $r%u, $r%u\n", 1695 dc->op1, dc->op2); 1696 cris_cc_mask(dc, CC_MASK_NZ); 1697 1698 t0 = tcg_temp_new(); 1699 tcg_gen_sari_tl(t0, cpu_R[dc->op1], 31); 1700 tcg_gen_xor_tl(cpu_R[dc->op2], cpu_R[dc->op1], t0); 1701 tcg_gen_sub_tl(cpu_R[dc->op2], cpu_R[dc->op2], t0); 1702 tcg_temp_free(t0); 1703 1704 cris_alu(dc, CC_OP_MOVE, 1705 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4); 1706 return 2; 1707 } 1708 1709 static int dec_add_r(CPUCRISState *env, DisasContext *dc) 1710 { 1711 TCGv t[2]; 1712 int size = memsize_zz(dc); 1713 LOG_DIS("add.%c $r%u, $r%u\n", 1714 memsize_char(size), dc->op1, dc->op2); 1715 cris_cc_mask(dc, CC_MASK_NZVC); 1716 cris_alu_alloc_temps(dc, size, t); 1717 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); 1718 1719 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], t[0], t[1], size); 1720 cris_alu_free_temps(dc, size, t); 1721 return 2; 1722 } 1723 1724 static int dec_addc_r(CPUCRISState *env, DisasContext *dc) 1725 { 1726 LOG_DIS("addc $r%u, $r%u\n", 1727 dc->op1, dc->op2); 1728 cris_evaluate_flags(dc); 1729 /* Set for this insn. */ 1730 dc->flagx_known = 1; 1731 dc->flags_x = X_FLAG; 1732 1733 cris_cc_mask(dc, CC_MASK_NZVC); 1734 cris_alu(dc, CC_OP_ADDC, 1735 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4); 1736 return 2; 1737 } 1738 1739 static int dec_mcp_r(CPUCRISState *env, DisasContext *dc) 1740 { 1741 LOG_DIS("mcp $p%u, $r%u\n", 1742 dc->op2, dc->op1); 1743 cris_evaluate_flags(dc); 1744 cris_cc_mask(dc, CC_MASK_RNZV); 1745 cris_alu(dc, CC_OP_MCP, 1746 cpu_R[dc->op1], cpu_R[dc->op1], cpu_PR[dc->op2], 4); 1747 return 2; 1748 } 1749 1750 #if DISAS_CRIS 1751 static char * swapmode_name(int mode, char *modename) { 1752 int i = 0; 1753 if (mode & 8) { 1754 modename[i++] = 'n'; 1755 } 1756 if (mode & 4) { 1757 modename[i++] = 'w'; 1758 } 1759 if (mode & 2) { 1760 modename[i++] = 'b'; 1761 } 1762 if (mode & 1) { 1763 modename[i++] = 'r'; 1764 } 1765 modename[i++] = 0; 1766 return modename; 1767 } 1768 #endif 1769 1770 static int dec_swap_r(CPUCRISState *env, DisasContext *dc) 1771 { 1772 TCGv t0; 1773 #if DISAS_CRIS 1774 char modename[4]; 1775 #endif 1776 LOG_DIS("swap%s $r%u\n", 1777 swapmode_name(dc->op2, modename), dc->op1); 1778 1779 cris_cc_mask(dc, CC_MASK_NZ); 1780 t0 = tcg_temp_new(); 1781 tcg_gen_mov_tl(t0, cpu_R[dc->op1]); 1782 if (dc->op2 & 8) { 1783 tcg_gen_not_tl(t0, t0); 1784 } 1785 if (dc->op2 & 4) { 1786 t_gen_swapw(t0, t0); 1787 } 1788 if (dc->op2 & 2) { 1789 t_gen_swapb(t0, t0); 1790 } 1791 if (dc->op2 & 1) { 1792 t_gen_swapr(t0, t0); 1793 } 1794 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op1], cpu_R[dc->op1], t0, 4); 1795 tcg_temp_free(t0); 1796 return 2; 1797 } 1798 1799 static int dec_or_r(CPUCRISState *env, DisasContext *dc) 1800 { 1801 TCGv t[2]; 1802 int size = memsize_zz(dc); 1803 LOG_DIS("or.%c $r%u, $r%u\n", 1804 memsize_char(size), dc->op1, dc->op2); 1805 cris_cc_mask(dc, CC_MASK_NZ); 1806 cris_alu_alloc_temps(dc, size, t); 1807 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); 1808 cris_alu(dc, CC_OP_OR, cpu_R[dc->op2], t[0], t[1], size); 1809 cris_alu_free_temps(dc, size, t); 1810 return 2; 1811 } 1812 1813 static int dec_addi_r(CPUCRISState *env, DisasContext *dc) 1814 { 1815 TCGv t0; 1816 LOG_DIS("addi.%c $r%u, $r%u\n", 1817 memsize_char(memsize_zz(dc)), dc->op2, dc->op1); 1818 cris_cc_mask(dc, 0); 1819 t0 = tcg_temp_new(); 1820 tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize)); 1821 tcg_gen_add_tl(cpu_R[dc->op1], cpu_R[dc->op1], t0); 1822 tcg_temp_free(t0); 1823 return 2; 1824 } 1825 1826 static int dec_addi_acr(CPUCRISState *env, DisasContext *dc) 1827 { 1828 TCGv t0; 1829 LOG_DIS("addi.%c $r%u, $r%u, $acr\n", 1830 memsize_char(memsize_zz(dc)), dc->op2, dc->op1); 1831 cris_cc_mask(dc, 0); 1832 t0 = tcg_temp_new(); 1833 tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize)); 1834 tcg_gen_add_tl(cpu_R[R_ACR], cpu_R[dc->op1], t0); 1835 tcg_temp_free(t0); 1836 return 2; 1837 } 1838 1839 static int dec_neg_r(CPUCRISState *env, DisasContext *dc) 1840 { 1841 TCGv t[2]; 1842 int size = memsize_zz(dc); 1843 LOG_DIS("neg.%c $r%u, $r%u\n", 1844 memsize_char(size), dc->op1, dc->op2); 1845 cris_cc_mask(dc, CC_MASK_NZVC); 1846 cris_alu_alloc_temps(dc, size, t); 1847 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); 1848 1849 cris_alu(dc, CC_OP_NEG, cpu_R[dc->op2], t[0], t[1], size); 1850 cris_alu_free_temps(dc, size, t); 1851 return 2; 1852 } 1853 1854 static int dec_btst_r(CPUCRISState *env, DisasContext *dc) 1855 { 1856 LOG_DIS("btst $r%u, $r%u\n", 1857 dc->op1, dc->op2); 1858 cris_cc_mask(dc, CC_MASK_NZ); 1859 cris_evaluate_flags(dc); 1860 gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2], 1861 cpu_R[dc->op1], cpu_PR[PR_CCS]); 1862 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], 1863 cpu_R[dc->op2], cpu_R[dc->op2], 4); 1864 cris_update_cc_op(dc, CC_OP_FLAGS, 4); 1865 dc->flags_uptodate = 1; 1866 return 2; 1867 } 1868 1869 static int dec_sub_r(CPUCRISState *env, DisasContext *dc) 1870 { 1871 TCGv t[2]; 1872 int size = memsize_zz(dc); 1873 LOG_DIS("sub.%c $r%u, $r%u\n", 1874 memsize_char(size), dc->op1, dc->op2); 1875 cris_cc_mask(dc, CC_MASK_NZVC); 1876 cris_alu_alloc_temps(dc, size, t); 1877 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); 1878 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], size); 1879 cris_alu_free_temps(dc, size, t); 1880 return 2; 1881 } 1882 1883 /* Zero extension. From size to dword. */ 1884 static int dec_movu_r(CPUCRISState *env, DisasContext *dc) 1885 { 1886 TCGv t0; 1887 int size = memsize_z(dc); 1888 LOG_DIS("movu.%c $r%u, $r%u\n", 1889 memsize_char(size), 1890 dc->op1, dc->op2); 1891 1892 cris_cc_mask(dc, CC_MASK_NZ); 1893 t0 = tcg_temp_new(); 1894 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0); 1895 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4); 1896 tcg_temp_free(t0); 1897 return 2; 1898 } 1899 1900 /* Sign extension. From size to dword. */ 1901 static int dec_movs_r(CPUCRISState *env, DisasContext *dc) 1902 { 1903 TCGv t0; 1904 int size = memsize_z(dc); 1905 LOG_DIS("movs.%c $r%u, $r%u\n", 1906 memsize_char(size), 1907 dc->op1, dc->op2); 1908 1909 cris_cc_mask(dc, CC_MASK_NZ); 1910 t0 = tcg_temp_new(); 1911 /* Size can only be qi or hi. */ 1912 t_gen_sext(t0, cpu_R[dc->op1], size); 1913 cris_alu(dc, CC_OP_MOVE, 1914 cpu_R[dc->op2], cpu_R[dc->op1], t0, 4); 1915 tcg_temp_free(t0); 1916 return 2; 1917 } 1918 1919 /* zero extension. From size to dword. */ 1920 static int dec_addu_r(CPUCRISState *env, DisasContext *dc) 1921 { 1922 TCGv t0; 1923 int size = memsize_z(dc); 1924 LOG_DIS("addu.%c $r%u, $r%u\n", 1925 memsize_char(size), 1926 dc->op1, dc->op2); 1927 1928 cris_cc_mask(dc, CC_MASK_NZVC); 1929 t0 = tcg_temp_new(); 1930 /* Size can only be qi or hi. */ 1931 t_gen_zext(t0, cpu_R[dc->op1], size); 1932 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4); 1933 tcg_temp_free(t0); 1934 return 2; 1935 } 1936 1937 /* Sign extension. From size to dword. */ 1938 static int dec_adds_r(CPUCRISState *env, DisasContext *dc) 1939 { 1940 TCGv t0; 1941 int size = memsize_z(dc); 1942 LOG_DIS("adds.%c $r%u, $r%u\n", 1943 memsize_char(size), 1944 dc->op1, dc->op2); 1945 1946 cris_cc_mask(dc, CC_MASK_NZVC); 1947 t0 = tcg_temp_new(); 1948 /* Size can only be qi or hi. */ 1949 t_gen_sext(t0, cpu_R[dc->op1], size); 1950 cris_alu(dc, CC_OP_ADD, 1951 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4); 1952 tcg_temp_free(t0); 1953 return 2; 1954 } 1955 1956 /* Zero extension. From size to dword. */ 1957 static int dec_subu_r(CPUCRISState *env, DisasContext *dc) 1958 { 1959 TCGv t0; 1960 int size = memsize_z(dc); 1961 LOG_DIS("subu.%c $r%u, $r%u\n", 1962 memsize_char(size), 1963 dc->op1, dc->op2); 1964 1965 cris_cc_mask(dc, CC_MASK_NZVC); 1966 t0 = tcg_temp_new(); 1967 /* Size can only be qi or hi. */ 1968 t_gen_zext(t0, cpu_R[dc->op1], size); 1969 cris_alu(dc, CC_OP_SUB, 1970 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4); 1971 tcg_temp_free(t0); 1972 return 2; 1973 } 1974 1975 /* Sign extension. From size to dword. */ 1976 static int dec_subs_r(CPUCRISState *env, DisasContext *dc) 1977 { 1978 TCGv t0; 1979 int size = memsize_z(dc); 1980 LOG_DIS("subs.%c $r%u, $r%u\n", 1981 memsize_char(size), 1982 dc->op1, dc->op2); 1983 1984 cris_cc_mask(dc, CC_MASK_NZVC); 1985 t0 = tcg_temp_new(); 1986 /* Size can only be qi or hi. */ 1987 t_gen_sext(t0, cpu_R[dc->op1], size); 1988 cris_alu(dc, CC_OP_SUB, 1989 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4); 1990 tcg_temp_free(t0); 1991 return 2; 1992 } 1993 1994 static int dec_setclrf(CPUCRISState *env, DisasContext *dc) 1995 { 1996 uint32_t flags; 1997 int set = (~dc->opcode >> 2) & 1; 1998 1999 2000 flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4) 2001 | EXTRACT_FIELD(dc->ir, 0, 3); 2002 if (set && flags == 0) { 2003 LOG_DIS("nop\n"); 2004 return 2; 2005 } else if (!set && (flags & 0x20)) { 2006 LOG_DIS("di\n"); 2007 } else { 2008 LOG_DIS("%sf %x\n", set ? "set" : "clr", flags); 2009 } 2010 2011 /* User space is not allowed to touch these. Silently ignore. */ 2012 if (dc->tb_flags & U_FLAG) { 2013 flags &= ~(S_FLAG | I_FLAG | U_FLAG); 2014 } 2015 2016 if (flags & X_FLAG) { 2017 dc->flagx_known = 1; 2018 if (set) { 2019 dc->flags_x = X_FLAG; 2020 } else { 2021 dc->flags_x = 0; 2022 } 2023 } 2024 2025 /* Break the TB if any of the SPI flag changes. */ 2026 if (flags & (P_FLAG | S_FLAG)) { 2027 tcg_gen_movi_tl(env_pc, dc->pc + 2); 2028 dc->is_jmp = DISAS_UPDATE; 2029 dc->cpustate_changed = 1; 2030 } 2031 2032 /* For the I flag, only act on posedge. */ 2033 if ((flags & I_FLAG)) { 2034 tcg_gen_movi_tl(env_pc, dc->pc + 2); 2035 dc->is_jmp = DISAS_UPDATE; 2036 dc->cpustate_changed = 1; 2037 } 2038 2039 2040 /* Simply decode the flags. */ 2041 cris_evaluate_flags(dc); 2042 cris_update_cc_op(dc, CC_OP_FLAGS, 4); 2043 cris_update_cc_x(dc); 2044 tcg_gen_movi_tl(cc_op, dc->cc_op); 2045 2046 if (set) { 2047 if (!(dc->tb_flags & U_FLAG) && (flags & U_FLAG)) { 2048 /* Enter user mode. */ 2049 t_gen_mov_env_TN(ksp, cpu_R[R_SP]); 2050 tcg_gen_mov_tl(cpu_R[R_SP], cpu_PR[PR_USP]); 2051 dc->cpustate_changed = 1; 2052 } 2053 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags); 2054 } else { 2055 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~flags); 2056 } 2057 2058 dc->flags_uptodate = 1; 2059 dc->clear_x = 0; 2060 return 2; 2061 } 2062 2063 static int dec_move_rs(CPUCRISState *env, DisasContext *dc) 2064 { 2065 LOG_DIS("move $r%u, $s%u\n", dc->op1, dc->op2); 2066 cris_cc_mask(dc, 0); 2067 gen_helper_movl_sreg_reg(cpu_env, tcg_const_tl(dc->op2), 2068 tcg_const_tl(dc->op1)); 2069 return 2; 2070 } 2071 static int dec_move_sr(CPUCRISState *env, DisasContext *dc) 2072 { 2073 LOG_DIS("move $s%u, $r%u\n", dc->op2, dc->op1); 2074 cris_cc_mask(dc, 0); 2075 gen_helper_movl_reg_sreg(cpu_env, tcg_const_tl(dc->op1), 2076 tcg_const_tl(dc->op2)); 2077 return 2; 2078 } 2079 2080 static int dec_move_rp(CPUCRISState *env, DisasContext *dc) 2081 { 2082 TCGv t[2]; 2083 LOG_DIS("move $r%u, $p%u\n", dc->op1, dc->op2); 2084 cris_cc_mask(dc, 0); 2085 2086 t[0] = tcg_temp_new(); 2087 if (dc->op2 == PR_CCS) { 2088 cris_evaluate_flags(dc); 2089 tcg_gen_mov_tl(t[0], cpu_R[dc->op1]); 2090 if (dc->tb_flags & U_FLAG) { 2091 t[1] = tcg_temp_new(); 2092 /* User space is not allowed to touch all flags. */ 2093 tcg_gen_andi_tl(t[0], t[0], 0x39f); 2094 tcg_gen_andi_tl(t[1], cpu_PR[PR_CCS], ~0x39f); 2095 tcg_gen_or_tl(t[0], t[1], t[0]); 2096 tcg_temp_free(t[1]); 2097 } 2098 } else { 2099 tcg_gen_mov_tl(t[0], cpu_R[dc->op1]); 2100 } 2101 2102 t_gen_mov_preg_TN(dc, dc->op2, t[0]); 2103 if (dc->op2 == PR_CCS) { 2104 cris_update_cc_op(dc, CC_OP_FLAGS, 4); 2105 dc->flags_uptodate = 1; 2106 } 2107 tcg_temp_free(t[0]); 2108 return 2; 2109 } 2110 static int dec_move_pr(CPUCRISState *env, DisasContext *dc) 2111 { 2112 TCGv t0; 2113 LOG_DIS("move $p%u, $r%u\n", dc->op2, dc->op1); 2114 cris_cc_mask(dc, 0); 2115 2116 if (dc->op2 == PR_CCS) { 2117 cris_evaluate_flags(dc); 2118 } 2119 2120 if (dc->op2 == PR_DZ) { 2121 tcg_gen_movi_tl(cpu_R[dc->op1], 0); 2122 } else { 2123 t0 = tcg_temp_new(); 2124 t_gen_mov_TN_preg(t0, dc->op2); 2125 cris_alu(dc, CC_OP_MOVE, 2126 cpu_R[dc->op1], cpu_R[dc->op1], t0, 2127 preg_sizes[dc->op2]); 2128 tcg_temp_free(t0); 2129 } 2130 return 2; 2131 } 2132 2133 static int dec_move_mr(CPUCRISState *env, DisasContext *dc) 2134 { 2135 int memsize = memsize_zz(dc); 2136 int insn_len; 2137 LOG_DIS("move.%c [$r%u%s, $r%u\n", 2138 memsize_char(memsize), 2139 dc->op1, dc->postinc ? "+]" : "]", 2140 dc->op2); 2141 2142 if (memsize == 4) { 2143 insn_len = dec_prep_move_m(env, dc, 0, 4, cpu_R[dc->op2]); 2144 cris_cc_mask(dc, CC_MASK_NZ); 2145 cris_update_cc_op(dc, CC_OP_MOVE, 4); 2146 cris_update_cc_x(dc); 2147 cris_update_result(dc, cpu_R[dc->op2]); 2148 } else { 2149 TCGv t0; 2150 2151 t0 = tcg_temp_new(); 2152 insn_len = dec_prep_move_m(env, dc, 0, memsize, t0); 2153 cris_cc_mask(dc, CC_MASK_NZ); 2154 cris_alu(dc, CC_OP_MOVE, 2155 cpu_R[dc->op2], cpu_R[dc->op2], t0, memsize); 2156 tcg_temp_free(t0); 2157 } 2158 do_postinc(dc, memsize); 2159 return insn_len; 2160 } 2161 2162 static inline void cris_alu_m_alloc_temps(TCGv *t) 2163 { 2164 t[0] = tcg_temp_new(); 2165 t[1] = tcg_temp_new(); 2166 } 2167 2168 static inline void cris_alu_m_free_temps(TCGv *t) 2169 { 2170 tcg_temp_free(t[0]); 2171 tcg_temp_free(t[1]); 2172 } 2173 2174 static int dec_movs_m(CPUCRISState *env, DisasContext *dc) 2175 { 2176 TCGv t[2]; 2177 int memsize = memsize_z(dc); 2178 int insn_len; 2179 LOG_DIS("movs.%c [$r%u%s, $r%u\n", 2180 memsize_char(memsize), 2181 dc->op1, dc->postinc ? "+]" : "]", 2182 dc->op2); 2183 2184 cris_alu_m_alloc_temps(t); 2185 /* sign extend. */ 2186 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]); 2187 cris_cc_mask(dc, CC_MASK_NZ); 2188 cris_alu(dc, CC_OP_MOVE, 2189 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4); 2190 do_postinc(dc, memsize); 2191 cris_alu_m_free_temps(t); 2192 return insn_len; 2193 } 2194 2195 static int dec_addu_m(CPUCRISState *env, DisasContext *dc) 2196 { 2197 TCGv t[2]; 2198 int memsize = memsize_z(dc); 2199 int insn_len; 2200 LOG_DIS("addu.%c [$r%u%s, $r%u\n", 2201 memsize_char(memsize), 2202 dc->op1, dc->postinc ? "+]" : "]", 2203 dc->op2); 2204 2205 cris_alu_m_alloc_temps(t); 2206 /* sign extend. */ 2207 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); 2208 cris_cc_mask(dc, CC_MASK_NZVC); 2209 cris_alu(dc, CC_OP_ADD, 2210 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4); 2211 do_postinc(dc, memsize); 2212 cris_alu_m_free_temps(t); 2213 return insn_len; 2214 } 2215 2216 static int dec_adds_m(CPUCRISState *env, DisasContext *dc) 2217 { 2218 TCGv t[2]; 2219 int memsize = memsize_z(dc); 2220 int insn_len; 2221 LOG_DIS("adds.%c [$r%u%s, $r%u\n", 2222 memsize_char(memsize), 2223 dc->op1, dc->postinc ? "+]" : "]", 2224 dc->op2); 2225 2226 cris_alu_m_alloc_temps(t); 2227 /* sign extend. */ 2228 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]); 2229 cris_cc_mask(dc, CC_MASK_NZVC); 2230 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4); 2231 do_postinc(dc, memsize); 2232 cris_alu_m_free_temps(t); 2233 return insn_len; 2234 } 2235 2236 static int dec_subu_m(CPUCRISState *env, DisasContext *dc) 2237 { 2238 TCGv t[2]; 2239 int memsize = memsize_z(dc); 2240 int insn_len; 2241 LOG_DIS("subu.%c [$r%u%s, $r%u\n", 2242 memsize_char(memsize), 2243 dc->op1, dc->postinc ? "+]" : "]", 2244 dc->op2); 2245 2246 cris_alu_m_alloc_temps(t); 2247 /* sign extend. */ 2248 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); 2249 cris_cc_mask(dc, CC_MASK_NZVC); 2250 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4); 2251 do_postinc(dc, memsize); 2252 cris_alu_m_free_temps(t); 2253 return insn_len; 2254 } 2255 2256 static int dec_subs_m(CPUCRISState *env, DisasContext *dc) 2257 { 2258 TCGv t[2]; 2259 int memsize = memsize_z(dc); 2260 int insn_len; 2261 LOG_DIS("subs.%c [$r%u%s, $r%u\n", 2262 memsize_char(memsize), 2263 dc->op1, dc->postinc ? "+]" : "]", 2264 dc->op2); 2265 2266 cris_alu_m_alloc_temps(t); 2267 /* sign extend. */ 2268 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]); 2269 cris_cc_mask(dc, CC_MASK_NZVC); 2270 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4); 2271 do_postinc(dc, memsize); 2272 cris_alu_m_free_temps(t); 2273 return insn_len; 2274 } 2275 2276 static int dec_movu_m(CPUCRISState *env, DisasContext *dc) 2277 { 2278 TCGv t[2]; 2279 int memsize = memsize_z(dc); 2280 int insn_len; 2281 2282 LOG_DIS("movu.%c [$r%u%s, $r%u\n", 2283 memsize_char(memsize), 2284 dc->op1, dc->postinc ? "+]" : "]", 2285 dc->op2); 2286 2287 cris_alu_m_alloc_temps(t); 2288 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); 2289 cris_cc_mask(dc, CC_MASK_NZ); 2290 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4); 2291 do_postinc(dc, memsize); 2292 cris_alu_m_free_temps(t); 2293 return insn_len; 2294 } 2295 2296 static int dec_cmpu_m(CPUCRISState *env, DisasContext *dc) 2297 { 2298 TCGv t[2]; 2299 int memsize = memsize_z(dc); 2300 int insn_len; 2301 LOG_DIS("cmpu.%c [$r%u%s, $r%u\n", 2302 memsize_char(memsize), 2303 dc->op1, dc->postinc ? "+]" : "]", 2304 dc->op2); 2305 2306 cris_alu_m_alloc_temps(t); 2307 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); 2308 cris_cc_mask(dc, CC_MASK_NZVC); 2309 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4); 2310 do_postinc(dc, memsize); 2311 cris_alu_m_free_temps(t); 2312 return insn_len; 2313 } 2314 2315 static int dec_cmps_m(CPUCRISState *env, DisasContext *dc) 2316 { 2317 TCGv t[2]; 2318 int memsize = memsize_z(dc); 2319 int insn_len; 2320 LOG_DIS("cmps.%c [$r%u%s, $r%u\n", 2321 memsize_char(memsize), 2322 dc->op1, dc->postinc ? "+]" : "]", 2323 dc->op2); 2324 2325 cris_alu_m_alloc_temps(t); 2326 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]); 2327 cris_cc_mask(dc, CC_MASK_NZVC); 2328 cris_alu(dc, CC_OP_CMP, 2329 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 2330 memsize_zz(dc)); 2331 do_postinc(dc, memsize); 2332 cris_alu_m_free_temps(t); 2333 return insn_len; 2334 } 2335 2336 static int dec_cmp_m(CPUCRISState *env, DisasContext *dc) 2337 { 2338 TCGv t[2]; 2339 int memsize = memsize_zz(dc); 2340 int insn_len; 2341 LOG_DIS("cmp.%c [$r%u%s, $r%u\n", 2342 memsize_char(memsize), 2343 dc->op1, dc->postinc ? "+]" : "]", 2344 dc->op2); 2345 2346 cris_alu_m_alloc_temps(t); 2347 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); 2348 cris_cc_mask(dc, CC_MASK_NZVC); 2349 cris_alu(dc, CC_OP_CMP, 2350 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 2351 memsize_zz(dc)); 2352 do_postinc(dc, memsize); 2353 cris_alu_m_free_temps(t); 2354 return insn_len; 2355 } 2356 2357 static int dec_test_m(CPUCRISState *env, DisasContext *dc) 2358 { 2359 TCGv t[2]; 2360 int memsize = memsize_zz(dc); 2361 int insn_len; 2362 LOG_DIS("test.%c [$r%u%s] op2=%x\n", 2363 memsize_char(memsize), 2364 dc->op1, dc->postinc ? "+]" : "]", 2365 dc->op2); 2366 2367 cris_evaluate_flags(dc); 2368 2369 cris_alu_m_alloc_temps(t); 2370 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); 2371 cris_cc_mask(dc, CC_MASK_NZ); 2372 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3); 2373 2374 cris_alu(dc, CC_OP_CMP, 2375 cpu_R[dc->op2], t[1], tcg_const_tl(0), memsize_zz(dc)); 2376 do_postinc(dc, memsize); 2377 cris_alu_m_free_temps(t); 2378 return insn_len; 2379 } 2380 2381 static int dec_and_m(CPUCRISState *env, DisasContext *dc) 2382 { 2383 TCGv t[2]; 2384 int memsize = memsize_zz(dc); 2385 int insn_len; 2386 LOG_DIS("and.%c [$r%u%s, $r%u\n", 2387 memsize_char(memsize), 2388 dc->op1, dc->postinc ? "+]" : "]", 2389 dc->op2); 2390 2391 cris_alu_m_alloc_temps(t); 2392 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); 2393 cris_cc_mask(dc, CC_MASK_NZ); 2394 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], memsize_zz(dc)); 2395 do_postinc(dc, memsize); 2396 cris_alu_m_free_temps(t); 2397 return insn_len; 2398 } 2399 2400 static int dec_add_m(CPUCRISState *env, DisasContext *dc) 2401 { 2402 TCGv t[2]; 2403 int memsize = memsize_zz(dc); 2404 int insn_len; 2405 LOG_DIS("add.%c [$r%u%s, $r%u\n", 2406 memsize_char(memsize), 2407 dc->op1, dc->postinc ? "+]" : "]", 2408 dc->op2); 2409 2410 cris_alu_m_alloc_temps(t); 2411 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); 2412 cris_cc_mask(dc, CC_MASK_NZVC); 2413 cris_alu(dc, CC_OP_ADD, 2414 cpu_R[dc->op2], t[0], t[1], memsize_zz(dc)); 2415 do_postinc(dc, memsize); 2416 cris_alu_m_free_temps(t); 2417 return insn_len; 2418 } 2419 2420 static int dec_addo_m(CPUCRISState *env, DisasContext *dc) 2421 { 2422 TCGv t[2]; 2423 int memsize = memsize_zz(dc); 2424 int insn_len; 2425 LOG_DIS("add.%c [$r%u%s, $r%u\n", 2426 memsize_char(memsize), 2427 dc->op1, dc->postinc ? "+]" : "]", 2428 dc->op2); 2429 2430 cris_alu_m_alloc_temps(t); 2431 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]); 2432 cris_cc_mask(dc, 0); 2433 cris_alu(dc, CC_OP_ADD, cpu_R[R_ACR], t[0], t[1], 4); 2434 do_postinc(dc, memsize); 2435 cris_alu_m_free_temps(t); 2436 return insn_len; 2437 } 2438 2439 static int dec_bound_m(CPUCRISState *env, DisasContext *dc) 2440 { 2441 TCGv l[2]; 2442 int memsize = memsize_zz(dc); 2443 int insn_len; 2444 LOG_DIS("bound.%c [$r%u%s, $r%u\n", 2445 memsize_char(memsize), 2446 dc->op1, dc->postinc ? "+]" : "]", 2447 dc->op2); 2448 2449 l[0] = tcg_temp_local_new(); 2450 l[1] = tcg_temp_local_new(); 2451 insn_len = dec_prep_alu_m(env, dc, 0, memsize, l[0], l[1]); 2452 cris_cc_mask(dc, CC_MASK_NZ); 2453 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], l[0], l[1], 4); 2454 do_postinc(dc, memsize); 2455 tcg_temp_free(l[0]); 2456 tcg_temp_free(l[1]); 2457 return insn_len; 2458 } 2459 2460 static int dec_addc_mr(CPUCRISState *env, DisasContext *dc) 2461 { 2462 TCGv t[2]; 2463 int insn_len = 2; 2464 LOG_DIS("addc [$r%u%s, $r%u\n", 2465 dc->op1, dc->postinc ? "+]" : "]", 2466 dc->op2); 2467 2468 cris_evaluate_flags(dc); 2469 2470 /* Set for this insn. */ 2471 dc->flagx_known = 1; 2472 dc->flags_x = X_FLAG; 2473 2474 cris_alu_m_alloc_temps(t); 2475 insn_len = dec_prep_alu_m(env, dc, 0, 4, t[0], t[1]); 2476 cris_cc_mask(dc, CC_MASK_NZVC); 2477 cris_alu(dc, CC_OP_ADDC, cpu_R[dc->op2], t[0], t[1], 4); 2478 do_postinc(dc, 4); 2479 cris_alu_m_free_temps(t); 2480 return insn_len; 2481 } 2482 2483 static int dec_sub_m(CPUCRISState *env, DisasContext *dc) 2484 { 2485 TCGv t[2]; 2486 int memsize = memsize_zz(dc); 2487 int insn_len; 2488 LOG_DIS("sub.%c [$r%u%s, $r%u ir=%x zz=%x\n", 2489 memsize_char(memsize), 2490 dc->op1, dc->postinc ? "+]" : "]", 2491 dc->op2, dc->ir, dc->zzsize); 2492 2493 cris_alu_m_alloc_temps(t); 2494 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); 2495 cris_cc_mask(dc, CC_MASK_NZVC); 2496 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], memsize); 2497 do_postinc(dc, memsize); 2498 cris_alu_m_free_temps(t); 2499 return insn_len; 2500 } 2501 2502 static int dec_or_m(CPUCRISState *env, DisasContext *dc) 2503 { 2504 TCGv t[2]; 2505 int memsize = memsize_zz(dc); 2506 int insn_len; 2507 LOG_DIS("or.%c [$r%u%s, $r%u pc=%x\n", 2508 memsize_char(memsize), 2509 dc->op1, dc->postinc ? "+]" : "]", 2510 dc->op2, dc->pc); 2511 2512 cris_alu_m_alloc_temps(t); 2513 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); 2514 cris_cc_mask(dc, CC_MASK_NZ); 2515 cris_alu(dc, CC_OP_OR, 2516 cpu_R[dc->op2], t[0], t[1], memsize_zz(dc)); 2517 do_postinc(dc, memsize); 2518 cris_alu_m_free_temps(t); 2519 return insn_len; 2520 } 2521 2522 static int dec_move_mp(CPUCRISState *env, DisasContext *dc) 2523 { 2524 TCGv t[2]; 2525 int memsize = memsize_zz(dc); 2526 int insn_len = 2; 2527 2528 LOG_DIS("move.%c [$r%u%s, $p%u\n", 2529 memsize_char(memsize), 2530 dc->op1, 2531 dc->postinc ? "+]" : "]", 2532 dc->op2); 2533 2534 cris_alu_m_alloc_temps(t); 2535 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); 2536 cris_cc_mask(dc, 0); 2537 if (dc->op2 == PR_CCS) { 2538 cris_evaluate_flags(dc); 2539 if (dc->tb_flags & U_FLAG) { 2540 /* User space is not allowed to touch all flags. */ 2541 tcg_gen_andi_tl(t[1], t[1], 0x39f); 2542 tcg_gen_andi_tl(t[0], cpu_PR[PR_CCS], ~0x39f); 2543 tcg_gen_or_tl(t[1], t[0], t[1]); 2544 } 2545 } 2546 2547 t_gen_mov_preg_TN(dc, dc->op2, t[1]); 2548 2549 do_postinc(dc, memsize); 2550 cris_alu_m_free_temps(t); 2551 return insn_len; 2552 } 2553 2554 static int dec_move_pm(CPUCRISState *env, DisasContext *dc) 2555 { 2556 TCGv t0; 2557 int memsize; 2558 2559 memsize = preg_sizes[dc->op2]; 2560 2561 LOG_DIS("move.%c $p%u, [$r%u%s\n", 2562 memsize_char(memsize), 2563 dc->op2, dc->op1, dc->postinc ? "+]" : "]"); 2564 2565 /* prepare store. Address in T0, value in T1. */ 2566 if (dc->op2 == PR_CCS) { 2567 cris_evaluate_flags(dc); 2568 } 2569 t0 = tcg_temp_new(); 2570 t_gen_mov_TN_preg(t0, dc->op2); 2571 cris_flush_cc_state(dc); 2572 gen_store(dc, cpu_R[dc->op1], t0, memsize); 2573 tcg_temp_free(t0); 2574 2575 cris_cc_mask(dc, 0); 2576 if (dc->postinc) { 2577 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize); 2578 } 2579 return 2; 2580 } 2581 2582 static int dec_movem_mr(CPUCRISState *env, DisasContext *dc) 2583 { 2584 TCGv_i64 tmp[16]; 2585 TCGv tmp32; 2586 TCGv addr; 2587 int i; 2588 int nr = dc->op2 + 1; 2589 2590 LOG_DIS("movem [$r%u%s, $r%u\n", dc->op1, 2591 dc->postinc ? "+]" : "]", dc->op2); 2592 2593 addr = tcg_temp_new(); 2594 /* There are probably better ways of doing this. */ 2595 cris_flush_cc_state(dc); 2596 for (i = 0; i < (nr >> 1); i++) { 2597 tmp[i] = tcg_temp_new_i64(); 2598 tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8); 2599 gen_load64(dc, tmp[i], addr); 2600 } 2601 if (nr & 1) { 2602 tmp32 = tcg_temp_new_i32(); 2603 tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8); 2604 gen_load(dc, tmp32, addr, 4, 0); 2605 } else { 2606 TCGV_UNUSED(tmp32); 2607 } 2608 tcg_temp_free(addr); 2609 2610 for (i = 0; i < (nr >> 1); i++) { 2611 tcg_gen_extrl_i64_i32(cpu_R[i * 2], tmp[i]); 2612 tcg_gen_shri_i64(tmp[i], tmp[i], 32); 2613 tcg_gen_extrl_i64_i32(cpu_R[i * 2 + 1], tmp[i]); 2614 tcg_temp_free_i64(tmp[i]); 2615 } 2616 if (nr & 1) { 2617 tcg_gen_mov_tl(cpu_R[dc->op2], tmp32); 2618 tcg_temp_free(tmp32); 2619 } 2620 2621 /* writeback the updated pointer value. */ 2622 if (dc->postinc) { 2623 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], nr * 4); 2624 } 2625 2626 /* gen_load might want to evaluate the previous insns flags. */ 2627 cris_cc_mask(dc, 0); 2628 return 2; 2629 } 2630 2631 static int dec_movem_rm(CPUCRISState *env, DisasContext *dc) 2632 { 2633 TCGv tmp; 2634 TCGv addr; 2635 int i; 2636 2637 LOG_DIS("movem $r%u, [$r%u%s\n", dc->op2, dc->op1, 2638 dc->postinc ? "+]" : "]"); 2639 2640 cris_flush_cc_state(dc); 2641 2642 tmp = tcg_temp_new(); 2643 addr = tcg_temp_new(); 2644 tcg_gen_movi_tl(tmp, 4); 2645 tcg_gen_mov_tl(addr, cpu_R[dc->op1]); 2646 for (i = 0; i <= dc->op2; i++) { 2647 /* Displace addr. */ 2648 /* Perform the store. */ 2649 gen_store(dc, addr, cpu_R[i], 4); 2650 tcg_gen_add_tl(addr, addr, tmp); 2651 } 2652 if (dc->postinc) { 2653 tcg_gen_mov_tl(cpu_R[dc->op1], addr); 2654 } 2655 cris_cc_mask(dc, 0); 2656 tcg_temp_free(tmp); 2657 tcg_temp_free(addr); 2658 return 2; 2659 } 2660 2661 static int dec_move_rm(CPUCRISState *env, DisasContext *dc) 2662 { 2663 int memsize; 2664 2665 memsize = memsize_zz(dc); 2666 2667 LOG_DIS("move.%c $r%u, [$r%u]\n", 2668 memsize_char(memsize), dc->op2, dc->op1); 2669 2670 /* prepare store. */ 2671 cris_flush_cc_state(dc); 2672 gen_store(dc, cpu_R[dc->op1], cpu_R[dc->op2], memsize); 2673 2674 if (dc->postinc) { 2675 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize); 2676 } 2677 cris_cc_mask(dc, 0); 2678 return 2; 2679 } 2680 2681 static int dec_lapcq(CPUCRISState *env, DisasContext *dc) 2682 { 2683 LOG_DIS("lapcq %x, $r%u\n", 2684 dc->pc + dc->op1*2, dc->op2); 2685 cris_cc_mask(dc, 0); 2686 tcg_gen_movi_tl(cpu_R[dc->op2], dc->pc + dc->op1 * 2); 2687 return 2; 2688 } 2689 2690 static int dec_lapc_im(CPUCRISState *env, DisasContext *dc) 2691 { 2692 unsigned int rd; 2693 int32_t imm; 2694 int32_t pc; 2695 2696 rd = dc->op2; 2697 2698 cris_cc_mask(dc, 0); 2699 imm = cris_fetch(env, dc, dc->pc + 2, 4, 0); 2700 LOG_DIS("lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2); 2701 2702 pc = dc->pc; 2703 pc += imm; 2704 tcg_gen_movi_tl(cpu_R[rd], pc); 2705 return 6; 2706 } 2707 2708 /* Jump to special reg. */ 2709 static int dec_jump_p(CPUCRISState *env, DisasContext *dc) 2710 { 2711 LOG_DIS("jump $p%u\n", dc->op2); 2712 2713 if (dc->op2 == PR_CCS) { 2714 cris_evaluate_flags(dc); 2715 } 2716 t_gen_mov_TN_preg(env_btarget, dc->op2); 2717 /* rete will often have low bit set to indicate delayslot. */ 2718 tcg_gen_andi_tl(env_btarget, env_btarget, ~1); 2719 cris_cc_mask(dc, 0); 2720 cris_prepare_jmp(dc, JMP_INDIRECT); 2721 return 2; 2722 } 2723 2724 /* Jump and save. */ 2725 static int dec_jas_r(CPUCRISState *env, DisasContext *dc) 2726 { 2727 LOG_DIS("jas $r%u, $p%u\n", dc->op1, dc->op2); 2728 cris_cc_mask(dc, 0); 2729 /* Store the return address in Pd. */ 2730 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]); 2731 if (dc->op2 > 15) { 2732 abort(); 2733 } 2734 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4)); 2735 2736 cris_prepare_jmp(dc, JMP_INDIRECT); 2737 return 2; 2738 } 2739 2740 static int dec_jas_im(CPUCRISState *env, DisasContext *dc) 2741 { 2742 uint32_t imm; 2743 2744 imm = cris_fetch(env, dc, dc->pc + 2, 4, 0); 2745 2746 LOG_DIS("jas 0x%x\n", imm); 2747 cris_cc_mask(dc, 0); 2748 /* Store the return address in Pd. */ 2749 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8)); 2750 2751 dc->jmp_pc = imm; 2752 cris_prepare_jmp(dc, JMP_DIRECT); 2753 return 6; 2754 } 2755 2756 static int dec_jasc_im(CPUCRISState *env, DisasContext *dc) 2757 { 2758 uint32_t imm; 2759 2760 imm = cris_fetch(env, dc, dc->pc + 2, 4, 0); 2761 2762 LOG_DIS("jasc 0x%x\n", imm); 2763 cris_cc_mask(dc, 0); 2764 /* Store the return address in Pd. */ 2765 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8 + 4)); 2766 2767 dc->jmp_pc = imm; 2768 cris_prepare_jmp(dc, JMP_DIRECT); 2769 return 6; 2770 } 2771 2772 static int dec_jasc_r(CPUCRISState *env, DisasContext *dc) 2773 { 2774 LOG_DIS("jasc_r $r%u, $p%u\n", dc->op1, dc->op2); 2775 cris_cc_mask(dc, 0); 2776 /* Store the return address in Pd. */ 2777 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]); 2778 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4 + 4)); 2779 cris_prepare_jmp(dc, JMP_INDIRECT); 2780 return 2; 2781 } 2782 2783 static int dec_bcc_im(CPUCRISState *env, DisasContext *dc) 2784 { 2785 int32_t offset; 2786 uint32_t cond = dc->op2; 2787 2788 offset = cris_fetch(env, dc, dc->pc + 2, 2, 1); 2789 2790 LOG_DIS("b%s %d pc=%x dst=%x\n", 2791 cc_name(cond), offset, 2792 dc->pc, dc->pc + offset); 2793 2794 cris_cc_mask(dc, 0); 2795 /* op2 holds the condition-code. */ 2796 cris_prepare_cc_branch(dc, offset, cond); 2797 return 4; 2798 } 2799 2800 static int dec_bas_im(CPUCRISState *env, DisasContext *dc) 2801 { 2802 int32_t simm; 2803 2804 simm = cris_fetch(env, dc, dc->pc + 2, 4, 0); 2805 2806 LOG_DIS("bas 0x%x, $p%u\n", dc->pc + simm, dc->op2); 2807 cris_cc_mask(dc, 0); 2808 /* Store the return address in Pd. */ 2809 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8)); 2810 2811 dc->jmp_pc = dc->pc + simm; 2812 cris_prepare_jmp(dc, JMP_DIRECT); 2813 return 6; 2814 } 2815 2816 static int dec_basc_im(CPUCRISState *env, DisasContext *dc) 2817 { 2818 int32_t simm; 2819 simm = cris_fetch(env, dc, dc->pc + 2, 4, 0); 2820 2821 LOG_DIS("basc 0x%x, $p%u\n", dc->pc + simm, dc->op2); 2822 cris_cc_mask(dc, 0); 2823 /* Store the return address in Pd. */ 2824 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 12)); 2825 2826 dc->jmp_pc = dc->pc + simm; 2827 cris_prepare_jmp(dc, JMP_DIRECT); 2828 return 6; 2829 } 2830 2831 static int dec_rfe_etc(CPUCRISState *env, DisasContext *dc) 2832 { 2833 cris_cc_mask(dc, 0); 2834 2835 if (dc->op2 == 15) { 2836 tcg_gen_st_i32(tcg_const_i32(1), cpu_env, 2837 -offsetof(CRISCPU, env) + offsetof(CPUState, halted)); 2838 tcg_gen_movi_tl(env_pc, dc->pc + 2); 2839 t_gen_raise_exception(EXCP_HLT); 2840 return 2; 2841 } 2842 2843 switch (dc->op2 & 7) { 2844 case 2: 2845 /* rfe. */ 2846 LOG_DIS("rfe\n"); 2847 cris_evaluate_flags(dc); 2848 gen_helper_rfe(cpu_env); 2849 dc->is_jmp = DISAS_UPDATE; 2850 break; 2851 case 5: 2852 /* rfn. */ 2853 LOG_DIS("rfn\n"); 2854 cris_evaluate_flags(dc); 2855 gen_helper_rfn(cpu_env); 2856 dc->is_jmp = DISAS_UPDATE; 2857 break; 2858 case 6: 2859 LOG_DIS("break %d\n", dc->op1); 2860 cris_evaluate_flags(dc); 2861 /* break. */ 2862 tcg_gen_movi_tl(env_pc, dc->pc + 2); 2863 2864 /* Breaks start at 16 in the exception vector. */ 2865 t_gen_mov_env_TN(trap_vector, 2866 tcg_const_tl(dc->op1 + 16)); 2867 t_gen_raise_exception(EXCP_BREAK); 2868 dc->is_jmp = DISAS_UPDATE; 2869 break; 2870 default: 2871 printf("op2=%x\n", dc->op2); 2872 BUG(); 2873 break; 2874 2875 } 2876 return 2; 2877 } 2878 2879 static int dec_ftag_fidx_d_m(CPUCRISState *env, DisasContext *dc) 2880 { 2881 return 2; 2882 } 2883 2884 static int dec_ftag_fidx_i_m(CPUCRISState *env, DisasContext *dc) 2885 { 2886 return 2; 2887 } 2888 2889 static int dec_null(CPUCRISState *env, DisasContext *dc) 2890 { 2891 printf("unknown insn pc=%x opc=%x op1=%x op2=%x\n", 2892 dc->pc, dc->opcode, dc->op1, dc->op2); 2893 fflush(NULL); 2894 BUG(); 2895 return 2; 2896 } 2897 2898 static struct decoder_info { 2899 struct { 2900 uint32_t bits; 2901 uint32_t mask; 2902 }; 2903 int (*dec)(CPUCRISState *env, DisasContext *dc); 2904 } decinfo[] = { 2905 /* Order matters here. */ 2906 {DEC_MOVEQ, dec_moveq}, 2907 {DEC_BTSTQ, dec_btstq}, 2908 {DEC_CMPQ, dec_cmpq}, 2909 {DEC_ADDOQ, dec_addoq}, 2910 {DEC_ADDQ, dec_addq}, 2911 {DEC_SUBQ, dec_subq}, 2912 {DEC_ANDQ, dec_andq}, 2913 {DEC_ORQ, dec_orq}, 2914 {DEC_ASRQ, dec_asrq}, 2915 {DEC_LSLQ, dec_lslq}, 2916 {DEC_LSRQ, dec_lsrq}, 2917 {DEC_BCCQ, dec_bccq}, 2918 2919 {DEC_BCC_IM, dec_bcc_im}, 2920 {DEC_JAS_IM, dec_jas_im}, 2921 {DEC_JAS_R, dec_jas_r}, 2922 {DEC_JASC_IM, dec_jasc_im}, 2923 {DEC_JASC_R, dec_jasc_r}, 2924 {DEC_BAS_IM, dec_bas_im}, 2925 {DEC_BASC_IM, dec_basc_im}, 2926 {DEC_JUMP_P, dec_jump_p}, 2927 {DEC_LAPC_IM, dec_lapc_im}, 2928 {DEC_LAPCQ, dec_lapcq}, 2929 2930 {DEC_RFE_ETC, dec_rfe_etc}, 2931 {DEC_ADDC_MR, dec_addc_mr}, 2932 2933 {DEC_MOVE_MP, dec_move_mp}, 2934 {DEC_MOVE_PM, dec_move_pm}, 2935 {DEC_MOVEM_MR, dec_movem_mr}, 2936 {DEC_MOVEM_RM, dec_movem_rm}, 2937 {DEC_MOVE_PR, dec_move_pr}, 2938 {DEC_SCC_R, dec_scc_r}, 2939 {DEC_SETF, dec_setclrf}, 2940 {DEC_CLEARF, dec_setclrf}, 2941 2942 {DEC_MOVE_SR, dec_move_sr}, 2943 {DEC_MOVE_RP, dec_move_rp}, 2944 {DEC_SWAP_R, dec_swap_r}, 2945 {DEC_ABS_R, dec_abs_r}, 2946 {DEC_LZ_R, dec_lz_r}, 2947 {DEC_MOVE_RS, dec_move_rs}, 2948 {DEC_BTST_R, dec_btst_r}, 2949 {DEC_ADDC_R, dec_addc_r}, 2950 2951 {DEC_DSTEP_R, dec_dstep_r}, 2952 {DEC_XOR_R, dec_xor_r}, 2953 {DEC_MCP_R, dec_mcp_r}, 2954 {DEC_CMP_R, dec_cmp_r}, 2955 2956 {DEC_ADDI_R, dec_addi_r}, 2957 {DEC_ADDI_ACR, dec_addi_acr}, 2958 2959 {DEC_ADD_R, dec_add_r}, 2960 {DEC_SUB_R, dec_sub_r}, 2961 2962 {DEC_ADDU_R, dec_addu_r}, 2963 {DEC_ADDS_R, dec_adds_r}, 2964 {DEC_SUBU_R, dec_subu_r}, 2965 {DEC_SUBS_R, dec_subs_r}, 2966 {DEC_LSL_R, dec_lsl_r}, 2967 2968 {DEC_AND_R, dec_and_r}, 2969 {DEC_OR_R, dec_or_r}, 2970 {DEC_BOUND_R, dec_bound_r}, 2971 {DEC_ASR_R, dec_asr_r}, 2972 {DEC_LSR_R, dec_lsr_r}, 2973 2974 {DEC_MOVU_R, dec_movu_r}, 2975 {DEC_MOVS_R, dec_movs_r}, 2976 {DEC_NEG_R, dec_neg_r}, 2977 {DEC_MOVE_R, dec_move_r}, 2978 2979 {DEC_FTAG_FIDX_I_M, dec_ftag_fidx_i_m}, 2980 {DEC_FTAG_FIDX_D_M, dec_ftag_fidx_d_m}, 2981 2982 {DEC_MULS_R, dec_muls_r}, 2983 {DEC_MULU_R, dec_mulu_r}, 2984 2985 {DEC_ADDU_M, dec_addu_m}, 2986 {DEC_ADDS_M, dec_adds_m}, 2987 {DEC_SUBU_M, dec_subu_m}, 2988 {DEC_SUBS_M, dec_subs_m}, 2989 2990 {DEC_CMPU_M, dec_cmpu_m}, 2991 {DEC_CMPS_M, dec_cmps_m}, 2992 {DEC_MOVU_M, dec_movu_m}, 2993 {DEC_MOVS_M, dec_movs_m}, 2994 2995 {DEC_CMP_M, dec_cmp_m}, 2996 {DEC_ADDO_M, dec_addo_m}, 2997 {DEC_BOUND_M, dec_bound_m}, 2998 {DEC_ADD_M, dec_add_m}, 2999 {DEC_SUB_M, dec_sub_m}, 3000 {DEC_AND_M, dec_and_m}, 3001 {DEC_OR_M, dec_or_m}, 3002 {DEC_MOVE_RM, dec_move_rm}, 3003 {DEC_TEST_M, dec_test_m}, 3004 {DEC_MOVE_MR, dec_move_mr}, 3005 3006 {{0, 0}, dec_null} 3007 }; 3008 3009 static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc) 3010 { 3011 int insn_len = 2; 3012 int i; 3013 3014 /* Load a halfword onto the instruction register. */ 3015 dc->ir = cris_fetch(env, dc, dc->pc, 2, 0); 3016 3017 /* Now decode it. */ 3018 dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11); 3019 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 3); 3020 dc->op2 = EXTRACT_FIELD(dc->ir, 12, 15); 3021 dc->zsize = EXTRACT_FIELD(dc->ir, 4, 4); 3022 dc->zzsize = EXTRACT_FIELD(dc->ir, 4, 5); 3023 dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10); 3024 3025 /* Large switch for all insns. */ 3026 for (i = 0; i < ARRAY_SIZE(decinfo); i++) { 3027 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) { 3028 insn_len = decinfo[i].dec(env, dc); 3029 break; 3030 } 3031 } 3032 3033 #if !defined(CONFIG_USER_ONLY) 3034 /* Single-stepping ? */ 3035 if (dc->tb_flags & S_FLAG) { 3036 TCGLabel *l1 = gen_new_label(); 3037 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_PR[PR_SPC], dc->pc, l1); 3038 /* We treat SPC as a break with an odd trap vector. */ 3039 cris_evaluate_flags(dc); 3040 t_gen_mov_env_TN(trap_vector, tcg_const_tl(3)); 3041 tcg_gen_movi_tl(env_pc, dc->pc + insn_len); 3042 tcg_gen_movi_tl(cpu_PR[PR_SPC], dc->pc + insn_len); 3043 t_gen_raise_exception(EXCP_BREAK); 3044 gen_set_label(l1); 3045 } 3046 #endif 3047 return insn_len; 3048 } 3049 3050 #include "translate_v10.c" 3051 3052 /* 3053 * Delay slots on QEMU/CRIS. 3054 * 3055 * If an exception hits on a delayslot, the core will let ERP (the Exception 3056 * Return Pointer) point to the branch (the previous) insn and set the lsb to 3057 * to give SW a hint that the exception actually hit on the dslot. 3058 * 3059 * CRIS expects all PC addresses to be 16-bit aligned. The lsb is ignored by 3060 * the core and any jmp to an odd addresses will mask off that lsb. It is 3061 * simply there to let sw know there was an exception on a dslot. 3062 * 3063 * When the software returns from an exception, the branch will re-execute. 3064 * On QEMU care needs to be taken when a branch+delayslot sequence is broken 3065 * and the branch and delayslot don't share pages. 3066 * 3067 * The TB contaning the branch insn will set up env->btarget and evaluate 3068 * env->btaken. When the translation loop exits we will note that the branch 3069 * sequence is broken and let env->dslot be the size of the branch insn (those 3070 * vary in length). 3071 * 3072 * The TB contaning the delayslot will have the PC of its real insn (i.e no lsb 3073 * set). It will also expect to have env->dslot setup with the size of the 3074 * delay slot so that env->pc - env->dslot point to the branch insn. This TB 3075 * will execute the dslot and take the branch, either to btarget or just one 3076 * insn ahead. 3077 * 3078 * When exceptions occur, we check for env->dslot in do_interrupt to detect 3079 * broken branch sequences and setup $erp accordingly (i.e let it point to the 3080 * branch and set lsb). Then env->dslot gets cleared so that the exception 3081 * handler can enter. When returning from exceptions (jump $erp) the lsb gets 3082 * masked off and we will reexecute the branch insn. 3083 * 3084 */ 3085 3086 /* generate intermediate code for basic block 'tb'. */ 3087 void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) 3088 { 3089 CPUCRISState *env = cs->env_ptr; 3090 uint32_t pc_start; 3091 unsigned int insn_len; 3092 struct DisasContext ctx; 3093 struct DisasContext *dc = &ctx; 3094 uint32_t next_page_start; 3095 target_ulong npc; 3096 int num_insns; 3097 int max_insns; 3098 3099 if (env->pregs[PR_VR] == 32) { 3100 dc->decoder = crisv32_decoder; 3101 dc->clear_locked_irq = 0; 3102 } else { 3103 dc->decoder = crisv10_decoder; 3104 dc->clear_locked_irq = 1; 3105 } 3106 3107 /* Odd PC indicates that branch is rexecuting due to exception in the 3108 * delayslot, like in real hw. 3109 */ 3110 pc_start = tb->pc & ~1; 3111 dc->cpu = cris_env_get_cpu(env); 3112 dc->tb = tb; 3113 3114 dc->is_jmp = DISAS_NEXT; 3115 dc->ppc = pc_start; 3116 dc->pc = pc_start; 3117 dc->singlestep_enabled = cs->singlestep_enabled; 3118 dc->flags_uptodate = 1; 3119 dc->flagx_known = 1; 3120 dc->flags_x = tb->flags & X_FLAG; 3121 dc->cc_x_uptodate = 0; 3122 dc->cc_mask = 0; 3123 dc->update_cc = 0; 3124 dc->clear_prefix = 0; 3125 3126 cris_update_cc_op(dc, CC_OP_FLAGS, 4); 3127 dc->cc_size_uptodate = -1; 3128 3129 /* Decode TB flags. */ 3130 dc->tb_flags = tb->flags & (S_FLAG | P_FLAG | U_FLAG \ 3131 | X_FLAG | PFIX_FLAG); 3132 dc->delayed_branch = !!(tb->flags & 7); 3133 if (dc->delayed_branch) { 3134 dc->jmp = JMP_INDIRECT; 3135 } else { 3136 dc->jmp = JMP_NOJMP; 3137 } 3138 3139 dc->cpustate_changed = 0; 3140 3141 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; 3142 num_insns = 0; 3143 max_insns = tb_cflags(tb) & CF_COUNT_MASK; 3144 if (max_insns == 0) { 3145 max_insns = CF_COUNT_MASK; 3146 } 3147 if (max_insns > TCG_MAX_INSNS) { 3148 max_insns = TCG_MAX_INSNS; 3149 } 3150 3151 gen_tb_start(tb); 3152 do { 3153 tcg_gen_insn_start(dc->delayed_branch == 1 3154 ? dc->ppc | 1 : dc->pc); 3155 num_insns++; 3156 3157 if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { 3158 cris_evaluate_flags(dc); 3159 tcg_gen_movi_tl(env_pc, dc->pc); 3160 t_gen_raise_exception(EXCP_DEBUG); 3161 dc->is_jmp = DISAS_UPDATE; 3162 /* The address covered by the breakpoint must be included in 3163 [tb->pc, tb->pc + tb->size) in order to for it to be 3164 properly cleared -- thus we increment the PC here so that 3165 the logic setting tb->size below does the right thing. */ 3166 dc->pc += 2; 3167 break; 3168 } 3169 3170 /* Pretty disas. */ 3171 LOG_DIS("%8.8x:\t", dc->pc); 3172 3173 if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) { 3174 gen_io_start(); 3175 } 3176 dc->clear_x = 1; 3177 3178 insn_len = dc->decoder(env, dc); 3179 dc->ppc = dc->pc; 3180 dc->pc += insn_len; 3181 if (dc->clear_x) { 3182 cris_clear_x_flag(dc); 3183 } 3184 3185 /* Check for delayed branches here. If we do it before 3186 actually generating any host code, the simulator will just 3187 loop doing nothing for on this program location. */ 3188 if (dc->delayed_branch) { 3189 dc->delayed_branch--; 3190 if (dc->delayed_branch == 0) { 3191 if (tb->flags & 7) { 3192 t_gen_mov_env_TN(dslot, tcg_const_tl(0)); 3193 } 3194 if (dc->cpustate_changed || !dc->flagx_known 3195 || (dc->flags_x != (tb->flags & X_FLAG))) { 3196 cris_store_direct_jmp(dc); 3197 } 3198 3199 if (dc->clear_locked_irq) { 3200 dc->clear_locked_irq = 0; 3201 t_gen_mov_env_TN(locked_irq, tcg_const_tl(0)); 3202 } 3203 3204 if (dc->jmp == JMP_DIRECT_CC) { 3205 TCGLabel *l1 = gen_new_label(); 3206 cris_evaluate_flags(dc); 3207 3208 /* Conditional jmp. */ 3209 tcg_gen_brcondi_tl(TCG_COND_EQ, 3210 env_btaken, 0, l1); 3211 gen_goto_tb(dc, 1, dc->jmp_pc); 3212 gen_set_label(l1); 3213 gen_goto_tb(dc, 0, dc->pc); 3214 dc->is_jmp = DISAS_TB_JUMP; 3215 dc->jmp = JMP_NOJMP; 3216 } else if (dc->jmp == JMP_DIRECT) { 3217 cris_evaluate_flags(dc); 3218 gen_goto_tb(dc, 0, dc->jmp_pc); 3219 dc->is_jmp = DISAS_TB_JUMP; 3220 dc->jmp = JMP_NOJMP; 3221 } else { 3222 t_gen_cc_jmp(env_btarget, tcg_const_tl(dc->pc)); 3223 dc->is_jmp = DISAS_JUMP; 3224 } 3225 break; 3226 } 3227 } 3228 3229 /* If we are rexecuting a branch due to exceptions on 3230 delay slots don't break. */ 3231 if (!(tb->pc & 1) && cs->singlestep_enabled) { 3232 break; 3233 } 3234 } while (!dc->is_jmp && !dc->cpustate_changed 3235 && !tcg_op_buf_full() 3236 && !singlestep 3237 && (dc->pc < next_page_start) 3238 && num_insns < max_insns); 3239 3240 if (dc->clear_locked_irq) { 3241 t_gen_mov_env_TN(locked_irq, tcg_const_tl(0)); 3242 } 3243 3244 npc = dc->pc; 3245 3246 if (tb_cflags(tb) & CF_LAST_IO) 3247 gen_io_end(); 3248 /* Force an update if the per-tb cpu state has changed. */ 3249 if (dc->is_jmp == DISAS_NEXT 3250 && (dc->cpustate_changed || !dc->flagx_known 3251 || (dc->flags_x != (tb->flags & X_FLAG)))) { 3252 dc->is_jmp = DISAS_UPDATE; 3253 tcg_gen_movi_tl(env_pc, npc); 3254 } 3255 /* Broken branch+delayslot sequence. */ 3256 if (dc->delayed_branch == 1) { 3257 /* Set env->dslot to the size of the branch insn. */ 3258 t_gen_mov_env_TN(dslot, tcg_const_tl(dc->pc - dc->ppc)); 3259 cris_store_direct_jmp(dc); 3260 } 3261 3262 cris_evaluate_flags(dc); 3263 3264 if (unlikely(cs->singlestep_enabled)) { 3265 if (dc->is_jmp == DISAS_NEXT) { 3266 tcg_gen_movi_tl(env_pc, npc); 3267 } 3268 t_gen_raise_exception(EXCP_DEBUG); 3269 } else { 3270 switch (dc->is_jmp) { 3271 case DISAS_NEXT: 3272 gen_goto_tb(dc, 1, npc); 3273 break; 3274 default: 3275 case DISAS_JUMP: 3276 case DISAS_UPDATE: 3277 /* indicate that the hash table must be used 3278 to find the next TB */ 3279 tcg_gen_exit_tb(0); 3280 break; 3281 case DISAS_SWI: 3282 case DISAS_TB_JUMP: 3283 /* nothing more to generate */ 3284 break; 3285 } 3286 } 3287 gen_tb_end(tb, num_insns); 3288 3289 tb->size = dc->pc - pc_start; 3290 tb->icount = num_insns; 3291 3292 #ifdef DEBUG_DISAS 3293 #if !DISAS_CRIS 3294 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) 3295 && qemu_log_in_addr_range(pc_start)) { 3296 qemu_log_lock(); 3297 qemu_log("--------------\n"); 3298 qemu_log("IN: %s\n", lookup_symbol(pc_start)); 3299 log_target_disas(cs, pc_start, dc->pc - pc_start); 3300 qemu_log("\nisize=%d osize=%d\n", 3301 dc->pc - pc_start, tcg_op_buf_count()); 3302 qemu_log_unlock(); 3303 } 3304 #endif 3305 #endif 3306 } 3307 3308 void cris_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 3309 int flags) 3310 { 3311 CRISCPU *cpu = CRIS_CPU(cs); 3312 CPUCRISState *env = &cpu->env; 3313 const char **regnames; 3314 const char **pregnames; 3315 int i; 3316 3317 if (!env || !f) { 3318 return; 3319 } 3320 if (env->pregs[PR_VR] < 32) { 3321 pregnames = pregnames_v10; 3322 regnames = regnames_v10; 3323 } else { 3324 pregnames = pregnames_v32; 3325 regnames = regnames_v32; 3326 } 3327 3328 cpu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n" 3329 "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n", 3330 env->pc, env->pregs[PR_CCS], env->btaken, env->btarget, 3331 env->cc_op, 3332 env->cc_src, env->cc_dest, env->cc_result, env->cc_mask); 3333 3334 3335 for (i = 0; i < 16; i++) { 3336 cpu_fprintf(f, "%s=%8.8x ", regnames[i], env->regs[i]); 3337 if ((i + 1) % 4 == 0) { 3338 cpu_fprintf(f, "\n"); 3339 } 3340 } 3341 cpu_fprintf(f, "\nspecial regs:\n"); 3342 for (i = 0; i < 16; i++) { 3343 cpu_fprintf(f, "%s=%8.8x ", pregnames[i], env->pregs[i]); 3344 if ((i + 1) % 4 == 0) { 3345 cpu_fprintf(f, "\n"); 3346 } 3347 } 3348 if (env->pregs[PR_VR] >= 32) { 3349 uint32_t srs = env->pregs[PR_SRS]; 3350 cpu_fprintf(f, "\nsupport function regs bank %x:\n", srs); 3351 if (srs < ARRAY_SIZE(env->sregs)) { 3352 for (i = 0; i < 16; i++) { 3353 cpu_fprintf(f, "s%2.2d=%8.8x ", 3354 i, env->sregs[srs][i]); 3355 if ((i + 1) % 4 == 0) { 3356 cpu_fprintf(f, "\n"); 3357 } 3358 } 3359 } 3360 } 3361 cpu_fprintf(f, "\n\n"); 3362 3363 } 3364 3365 void cris_initialize_tcg(void) 3366 { 3367 int i; 3368 3369 cc_x = tcg_global_mem_new(cpu_env, 3370 offsetof(CPUCRISState, cc_x), "cc_x"); 3371 cc_src = tcg_global_mem_new(cpu_env, 3372 offsetof(CPUCRISState, cc_src), "cc_src"); 3373 cc_dest = tcg_global_mem_new(cpu_env, 3374 offsetof(CPUCRISState, cc_dest), 3375 "cc_dest"); 3376 cc_result = tcg_global_mem_new(cpu_env, 3377 offsetof(CPUCRISState, cc_result), 3378 "cc_result"); 3379 cc_op = tcg_global_mem_new(cpu_env, 3380 offsetof(CPUCRISState, cc_op), "cc_op"); 3381 cc_size = tcg_global_mem_new(cpu_env, 3382 offsetof(CPUCRISState, cc_size), 3383 "cc_size"); 3384 cc_mask = tcg_global_mem_new(cpu_env, 3385 offsetof(CPUCRISState, cc_mask), 3386 "cc_mask"); 3387 3388 env_pc = tcg_global_mem_new(cpu_env, 3389 offsetof(CPUCRISState, pc), 3390 "pc"); 3391 env_btarget = tcg_global_mem_new(cpu_env, 3392 offsetof(CPUCRISState, btarget), 3393 "btarget"); 3394 env_btaken = tcg_global_mem_new(cpu_env, 3395 offsetof(CPUCRISState, btaken), 3396 "btaken"); 3397 for (i = 0; i < 16; i++) { 3398 cpu_R[i] = tcg_global_mem_new(cpu_env, 3399 offsetof(CPUCRISState, regs[i]), 3400 regnames_v32[i]); 3401 } 3402 for (i = 0; i < 16; i++) { 3403 cpu_PR[i] = tcg_global_mem_new(cpu_env, 3404 offsetof(CPUCRISState, pregs[i]), 3405 pregnames_v32[i]); 3406 } 3407 } 3408 3409 void restore_state_to_opc(CPUCRISState *env, TranslationBlock *tb, 3410 target_ulong *data) 3411 { 3412 env->pc = data[0]; 3413 } 3414