1 /* 2 * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qemu/qemu-print.h" 20 #include "cpu.h" 21 #include "internal.h" 22 #include "exec/exec-all.h" 23 #include "qapi/error.h" 24 #include "hw/qdev-properties.h" 25 #include "fpu/softfloat-helpers.h" 26 #include "tcg/tcg.h" 27 28 static void hexagon_v67_cpu_init(Object *obj) { } 29 static void hexagon_v68_cpu_init(Object *obj) { } 30 static void hexagon_v69_cpu_init(Object *obj) { } 31 static void hexagon_v71_cpu_init(Object *obj) { } 32 static void hexagon_v73_cpu_init(Object *obj) { } 33 34 static void hexagon_cpu_list_entry(gpointer data, gpointer user_data) 35 { 36 ObjectClass *oc = data; 37 char *name = g_strdup(object_class_get_name(oc)); 38 if (g_str_has_suffix(name, HEXAGON_CPU_TYPE_SUFFIX)) { 39 name[strlen(name) - strlen(HEXAGON_CPU_TYPE_SUFFIX)] = '\0'; 40 } 41 qemu_printf(" %s\n", name); 42 g_free(name); 43 } 44 45 void hexagon_cpu_list(void) 46 { 47 GSList *list; 48 list = object_class_get_list_sorted(TYPE_HEXAGON_CPU, false); 49 qemu_printf("Available CPUs:\n"); 50 g_slist_foreach(list, hexagon_cpu_list_entry, NULL); 51 g_slist_free(list); 52 } 53 54 static ObjectClass *hexagon_cpu_class_by_name(const char *cpu_model) 55 { 56 ObjectClass *oc; 57 char *typename; 58 char **cpuname; 59 60 cpuname = g_strsplit(cpu_model, ",", 1); 61 typename = g_strdup_printf(HEXAGON_CPU_TYPE_NAME("%s"), cpuname[0]); 62 oc = object_class_by_name(typename); 63 g_strfreev(cpuname); 64 g_free(typename); 65 if (!oc || !object_class_dynamic_cast(oc, TYPE_HEXAGON_CPU) || 66 object_class_is_abstract(oc)) { 67 return NULL; 68 } 69 return oc; 70 } 71 72 static Property hexagon_lldb_compat_property = 73 DEFINE_PROP_BOOL("lldb-compat", HexagonCPU, lldb_compat, false); 74 static Property hexagon_lldb_stack_adjust_property = 75 DEFINE_PROP_UNSIGNED("lldb-stack-adjust", HexagonCPU, lldb_stack_adjust, 76 0, qdev_prop_uint32, target_ulong); 77 static Property hexagon_short_circuit_property = 78 DEFINE_PROP_BOOL("short-circuit", HexagonCPU, short_circuit, true); 79 80 const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS] = { 81 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 82 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 83 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 84 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 85 "sa0", "lc0", "sa1", "lc1", "p3_0", "c5", "m0", "m1", 86 "usr", "pc", "ugp", "gp", "cs0", "cs1", "c14", "c15", 87 "c16", "c17", "c18", "c19", "pkt_cnt", "insn_cnt", "hvx_cnt", "c23", 88 "c24", "c25", "c26", "c27", "c28", "c29", "c30", "c31", 89 }; 90 91 /* 92 * One of the main debugging techniques is to use "-d cpu" and compare against 93 * LLDB output when single stepping. However, the target and qemu put the 94 * stacks at different locations. This is used to compensate so the diff is 95 * cleaner. 96 */ 97 static target_ulong adjust_stack_ptrs(CPUHexagonState *env, target_ulong addr) 98 { 99 HexagonCPU *cpu = env_archcpu(env); 100 target_ulong stack_adjust = cpu->lldb_stack_adjust; 101 target_ulong stack_start = env->stack_start; 102 target_ulong stack_size = 0x10000; 103 104 if (stack_adjust == 0) { 105 return addr; 106 } 107 108 if (stack_start + 0x1000 >= addr && addr >= (stack_start - stack_size)) { 109 return addr - stack_adjust; 110 } 111 return addr; 112 } 113 114 /* HEX_REG_P3_0_ALIASED (aka C4) is an alias for the predicate registers */ 115 static target_ulong read_p3_0(CPUHexagonState *env) 116 { 117 int32_t control_reg = 0; 118 int i; 119 for (i = NUM_PREGS - 1; i >= 0; i--) { 120 control_reg <<= 8; 121 control_reg |= env->pred[i] & 0xff; 122 } 123 return control_reg; 124 } 125 126 static void print_reg(FILE *f, CPUHexagonState *env, int regnum) 127 { 128 target_ulong value; 129 130 if (regnum == HEX_REG_P3_0_ALIASED) { 131 value = read_p3_0(env); 132 } else { 133 value = regnum < 32 ? adjust_stack_ptrs(env, env->gpr[regnum]) 134 : env->gpr[regnum]; 135 } 136 137 qemu_fprintf(f, " %s = 0x" TARGET_FMT_lx "\n", 138 hexagon_regnames[regnum], value); 139 } 140 141 static void print_vreg(FILE *f, CPUHexagonState *env, int regnum, 142 bool skip_if_zero) 143 { 144 if (skip_if_zero) { 145 bool nonzero_found = false; 146 for (int i = 0; i < MAX_VEC_SIZE_BYTES; i++) { 147 if (env->VRegs[regnum].ub[i] != 0) { 148 nonzero_found = true; 149 break; 150 } 151 } 152 if (!nonzero_found) { 153 return; 154 } 155 } 156 157 qemu_fprintf(f, " v%d = ( ", regnum); 158 qemu_fprintf(f, "0x%02x", env->VRegs[regnum].ub[MAX_VEC_SIZE_BYTES - 1]); 159 for (int i = MAX_VEC_SIZE_BYTES - 2; i >= 0; i--) { 160 qemu_fprintf(f, ", 0x%02x", env->VRegs[regnum].ub[i]); 161 } 162 qemu_fprintf(f, " )\n"); 163 } 164 165 void hexagon_debug_vreg(CPUHexagonState *env, int regnum) 166 { 167 print_vreg(stdout, env, regnum, false); 168 } 169 170 static void print_qreg(FILE *f, CPUHexagonState *env, int regnum, 171 bool skip_if_zero) 172 { 173 if (skip_if_zero) { 174 bool nonzero_found = false; 175 for (int i = 0; i < MAX_VEC_SIZE_BYTES / 8; i++) { 176 if (env->QRegs[regnum].ub[i] != 0) { 177 nonzero_found = true; 178 break; 179 } 180 } 181 if (!nonzero_found) { 182 return; 183 } 184 } 185 186 qemu_fprintf(f, " q%d = ( ", regnum); 187 qemu_fprintf(f, "0x%02x", 188 env->QRegs[regnum].ub[MAX_VEC_SIZE_BYTES / 8 - 1]); 189 for (int i = MAX_VEC_SIZE_BYTES / 8 - 2; i >= 0; i--) { 190 qemu_fprintf(f, ", 0x%02x", env->QRegs[regnum].ub[i]); 191 } 192 qemu_fprintf(f, " )\n"); 193 } 194 195 void hexagon_debug_qreg(CPUHexagonState *env, int regnum) 196 { 197 print_qreg(stdout, env, regnum, false); 198 } 199 200 static void hexagon_dump(CPUHexagonState *env, FILE *f, int flags) 201 { 202 HexagonCPU *cpu = env_archcpu(env); 203 204 if (cpu->lldb_compat) { 205 /* 206 * When comparing with LLDB, it doesn't step through single-cycle 207 * hardware loops the same way. So, we just skip them here 208 */ 209 if (env->gpr[HEX_REG_PC] == env->last_pc_dumped) { 210 return; 211 } 212 env->last_pc_dumped = env->gpr[HEX_REG_PC]; 213 } 214 215 qemu_fprintf(f, "General Purpose Registers = {\n"); 216 for (int i = 0; i < 32; i++) { 217 print_reg(f, env, i); 218 } 219 print_reg(f, env, HEX_REG_SA0); 220 print_reg(f, env, HEX_REG_LC0); 221 print_reg(f, env, HEX_REG_SA1); 222 print_reg(f, env, HEX_REG_LC1); 223 print_reg(f, env, HEX_REG_M0); 224 print_reg(f, env, HEX_REG_M1); 225 print_reg(f, env, HEX_REG_USR); 226 print_reg(f, env, HEX_REG_P3_0_ALIASED); 227 print_reg(f, env, HEX_REG_GP); 228 print_reg(f, env, HEX_REG_UGP); 229 print_reg(f, env, HEX_REG_PC); 230 #ifdef CONFIG_USER_ONLY 231 /* 232 * Not modelled in user mode, print junk to minimize the diff's 233 * with LLDB output 234 */ 235 qemu_fprintf(f, " cause = 0x000000db\n"); 236 qemu_fprintf(f, " badva = 0x00000000\n"); 237 qemu_fprintf(f, " cs0 = 0x00000000\n"); 238 qemu_fprintf(f, " cs1 = 0x00000000\n"); 239 #else 240 print_reg(f, env, HEX_REG_CAUSE); 241 print_reg(f, env, HEX_REG_BADVA); 242 print_reg(f, env, HEX_REG_CS0); 243 print_reg(f, env, HEX_REG_CS1); 244 #endif 245 qemu_fprintf(f, "}\n"); 246 247 if (flags & CPU_DUMP_FPU) { 248 qemu_fprintf(f, "Vector Registers = {\n"); 249 for (int i = 0; i < NUM_VREGS; i++) { 250 print_vreg(f, env, i, true); 251 } 252 for (int i = 0; i < NUM_QREGS; i++) { 253 print_qreg(f, env, i, true); 254 } 255 qemu_fprintf(f, "}\n"); 256 } 257 } 258 259 static void hexagon_dump_state(CPUState *cs, FILE *f, int flags) 260 { 261 HexagonCPU *cpu = HEXAGON_CPU(cs); 262 CPUHexagonState *env = &cpu->env; 263 264 hexagon_dump(env, f, flags); 265 } 266 267 void hexagon_debug(CPUHexagonState *env) 268 { 269 hexagon_dump(env, stdout, CPU_DUMP_FPU); 270 } 271 272 static void hexagon_cpu_set_pc(CPUState *cs, vaddr value) 273 { 274 HexagonCPU *cpu = HEXAGON_CPU(cs); 275 CPUHexagonState *env = &cpu->env; 276 env->gpr[HEX_REG_PC] = value; 277 } 278 279 static vaddr hexagon_cpu_get_pc(CPUState *cs) 280 { 281 HexagonCPU *cpu = HEXAGON_CPU(cs); 282 CPUHexagonState *env = &cpu->env; 283 return env->gpr[HEX_REG_PC]; 284 } 285 286 static void hexagon_cpu_synchronize_from_tb(CPUState *cs, 287 const TranslationBlock *tb) 288 { 289 HexagonCPU *cpu = HEXAGON_CPU(cs); 290 CPUHexagonState *env = &cpu->env; 291 tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); 292 env->gpr[HEX_REG_PC] = tb->pc; 293 } 294 295 static bool hexagon_cpu_has_work(CPUState *cs) 296 { 297 return true; 298 } 299 300 static void hexagon_restore_state_to_opc(CPUState *cs, 301 const TranslationBlock *tb, 302 const uint64_t *data) 303 { 304 HexagonCPU *cpu = HEXAGON_CPU(cs); 305 CPUHexagonState *env = &cpu->env; 306 307 env->gpr[HEX_REG_PC] = data[0]; 308 } 309 310 static void hexagon_cpu_reset_hold(Object *obj) 311 { 312 CPUState *cs = CPU(obj); 313 HexagonCPU *cpu = HEXAGON_CPU(cs); 314 HexagonCPUClass *mcc = HEXAGON_CPU_GET_CLASS(cpu); 315 CPUHexagonState *env = &cpu->env; 316 317 if (mcc->parent_phases.hold) { 318 mcc->parent_phases.hold(obj); 319 } 320 321 set_default_nan_mode(1, &env->fp_status); 322 set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status); 323 } 324 325 static void hexagon_cpu_disas_set_info(CPUState *s, disassemble_info *info) 326 { 327 info->print_insn = print_insn_hexagon; 328 } 329 330 static void hexagon_cpu_realize(DeviceState *dev, Error **errp) 331 { 332 CPUState *cs = CPU(dev); 333 HexagonCPUClass *mcc = HEXAGON_CPU_GET_CLASS(dev); 334 Error *local_err = NULL; 335 336 cpu_exec_realizefn(cs, &local_err); 337 if (local_err != NULL) { 338 error_propagate(errp, local_err); 339 return; 340 } 341 342 qemu_init_vcpu(cs); 343 cpu_reset(cs); 344 345 mcc->parent_realize(dev, errp); 346 } 347 348 static void hexagon_cpu_init(Object *obj) 349 { 350 HexagonCPU *cpu = HEXAGON_CPU(obj); 351 352 cpu_set_cpustate_pointers(cpu); 353 qdev_property_add_static(DEVICE(obj), &hexagon_lldb_compat_property); 354 qdev_property_add_static(DEVICE(obj), &hexagon_lldb_stack_adjust_property); 355 qdev_property_add_static(DEVICE(obj), &hexagon_short_circuit_property); 356 } 357 358 #include "hw/core/tcg-cpu-ops.h" 359 360 static const struct TCGCPUOps hexagon_tcg_ops = { 361 .initialize = hexagon_translate_init, 362 .synchronize_from_tb = hexagon_cpu_synchronize_from_tb, 363 .restore_state_to_opc = hexagon_restore_state_to_opc, 364 }; 365 366 static void hexagon_cpu_class_init(ObjectClass *c, void *data) 367 { 368 HexagonCPUClass *mcc = HEXAGON_CPU_CLASS(c); 369 CPUClass *cc = CPU_CLASS(c); 370 DeviceClass *dc = DEVICE_CLASS(c); 371 ResettableClass *rc = RESETTABLE_CLASS(c); 372 373 device_class_set_parent_realize(dc, hexagon_cpu_realize, 374 &mcc->parent_realize); 375 376 resettable_class_set_parent_phases(rc, NULL, hexagon_cpu_reset_hold, NULL, 377 &mcc->parent_phases); 378 379 cc->class_by_name = hexagon_cpu_class_by_name; 380 cc->has_work = hexagon_cpu_has_work; 381 cc->dump_state = hexagon_dump_state; 382 cc->set_pc = hexagon_cpu_set_pc; 383 cc->get_pc = hexagon_cpu_get_pc; 384 cc->gdb_read_register = hexagon_gdb_read_register; 385 cc->gdb_write_register = hexagon_gdb_write_register; 386 cc->gdb_num_core_regs = TOTAL_PER_THREAD_REGS; 387 cc->gdb_stop_before_watchpoint = true; 388 cc->gdb_core_xml_file = "hexagon-core.xml"; 389 cc->disas_set_info = hexagon_cpu_disas_set_info; 390 cc->tcg_ops = &hexagon_tcg_ops; 391 } 392 393 #define DEFINE_CPU(type_name, initfn) \ 394 { \ 395 .name = type_name, \ 396 .parent = TYPE_HEXAGON_CPU, \ 397 .instance_init = initfn \ 398 } 399 400 static const TypeInfo hexagon_cpu_type_infos[] = { 401 { 402 .name = TYPE_HEXAGON_CPU, 403 .parent = TYPE_CPU, 404 .instance_size = sizeof(HexagonCPU), 405 .instance_init = hexagon_cpu_init, 406 .abstract = true, 407 .class_size = sizeof(HexagonCPUClass), 408 .class_init = hexagon_cpu_class_init, 409 }, 410 DEFINE_CPU(TYPE_HEXAGON_CPU_V67, hexagon_v67_cpu_init), 411 DEFINE_CPU(TYPE_HEXAGON_CPU_V68, hexagon_v68_cpu_init), 412 DEFINE_CPU(TYPE_HEXAGON_CPU_V69, hexagon_v69_cpu_init), 413 DEFINE_CPU(TYPE_HEXAGON_CPU_V71, hexagon_v71_cpu_init), 414 DEFINE_CPU(TYPE_HEXAGON_CPU_V73, hexagon_v73_cpu_init), 415 }; 416 417 DEFINE_TYPES(hexagon_cpu_type_infos) 418