1 /* 2 * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "iclass.h" 20 #include "attribs.h" 21 #include "genptr.h" 22 #include "decode.h" 23 #include "insn.h" 24 #include "printinsn.h" 25 #include "mmvec/decode_ext_mmvec.h" 26 27 #define fZXTN(N, M, VAL) ((VAL) & ((1LL << (N)) - 1)) 28 29 enum { 30 EXT_IDX_noext = 0, 31 EXT_IDX_noext_AFTER = 4, 32 EXT_IDX_mmvec = 4, 33 EXT_IDX_mmvec_AFTER = 8, 34 XX_LAST_EXT_IDX 35 }; 36 37 /* 38 * Certain operand types represent a non-contiguous set of values. 39 * For example, the compound compare-and-jump instruction can only access 40 * registers R0-R7 and R16-23. 41 * This table represents the mapping from the encoding to the actual values. 42 */ 43 44 #define DEF_REGMAP(NAME, ELEMENTS, ...) \ 45 static const unsigned int DECODE_REGISTER_##NAME[ELEMENTS] = \ 46 { __VA_ARGS__ }; 47 /* Name Num Table */ 48 DEF_REGMAP(R_16, 16, 0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 23) 49 DEF_REGMAP(R__8, 8, 0, 2, 4, 6, 16, 18, 20, 22) 50 DEF_REGMAP(R_8, 8, 0, 1, 2, 3, 4, 5, 6, 7) 51 52 #define DECODE_MAPPED_REG(OPNUM, NAME) \ 53 insn->regno[OPNUM] = DECODE_REGISTER_##NAME[insn->regno[OPNUM]]; 54 55 /* Helper functions for decode_*_generated.c.inc */ 56 #define DECODE_MAPPED(NAME) \ 57 static int decode_mapped_reg_##NAME(DisasContext *ctx, int x) \ 58 { \ 59 return DECODE_REGISTER_##NAME[x]; \ 60 } 61 DECODE_MAPPED(R_16) 62 DECODE_MAPPED(R_8) 63 DECODE_MAPPED(R__8) 64 65 /* Helper function for decodetree_trans_funcs_generated.c.inc */ 66 static int shift_left(DisasContext *ctx, int x, int n, int immno) 67 { 68 int ret = x; 69 Insn *insn = ctx->insn; 70 if (!insn->extension_valid || 71 insn->which_extended != immno) { 72 ret <<= n; 73 } 74 return ret; 75 } 76 77 /* Include the generated decoder for 32 bit insn */ 78 #include "decode_normal_generated.c.inc" 79 #include "decode_hvx_generated.c.inc" 80 81 /* Include the generated decoder for 16 bit insn */ 82 #include "decode_subinsn_a_generated.c.inc" 83 #include "decode_subinsn_l1_generated.c.inc" 84 #include "decode_subinsn_l2_generated.c.inc" 85 #include "decode_subinsn_s1_generated.c.inc" 86 #include "decode_subinsn_s2_generated.c.inc" 87 88 /* Include the generated helpers for the decoder */ 89 #include "decodetree_trans_funcs_generated.c.inc" 90 91 void decode_send_insn_to(Packet *packet, int start, int newloc) 92 { 93 Insn tmpinsn; 94 int direction; 95 int i; 96 if (start == newloc) { 97 return; 98 } 99 if (start < newloc) { 100 /* Move towards end */ 101 direction = 1; 102 } else { 103 /* move towards beginning */ 104 direction = -1; 105 } 106 for (i = start; i != newloc; i += direction) { 107 tmpinsn = packet->insn[i]; 108 packet->insn[i] = packet->insn[i + direction]; 109 packet->insn[i + direction] = tmpinsn; 110 } 111 } 112 113 /* Fill newvalue registers with the correct regno */ 114 static void 115 decode_fill_newvalue_regno(Packet *packet) 116 { 117 int i, use_regidx, offset, def_idx, dst_idx; 118 uint16_t def_opcode, use_opcode; 119 char *dststr; 120 121 for (i = 1; i < packet->num_insns; i++) { 122 if (GET_ATTRIB(packet->insn[i].opcode, A_DOTNEWVALUE) && 123 !GET_ATTRIB(packet->insn[i].opcode, A_EXTENSION)) { 124 use_opcode = packet->insn[i].opcode; 125 126 /* It's a store, so we're adjusting the Nt field */ 127 if (GET_ATTRIB(use_opcode, A_STORE)) { 128 use_regidx = strchr(opcode_reginfo[use_opcode], 't') - 129 opcode_reginfo[use_opcode]; 130 } else { /* It's a Jump, so we're adjusting the Ns field */ 131 use_regidx = strchr(opcode_reginfo[use_opcode], 's') - 132 opcode_reginfo[use_opcode]; 133 } 134 g_assert(packet->insn[i].new_read_idx != -1 && 135 packet->insn[i].new_read_idx == use_regidx); 136 137 /* 138 * What's encoded at the N-field is the offset to who's producing 139 * the value. Shift off the LSB which indicates odd/even register, 140 * then walk backwards and skip over the constant extenders. 141 */ 142 offset = packet->insn[i].regno[use_regidx] >> 1; 143 def_idx = i - offset; 144 for (int j = 0; j < offset; j++) { 145 if (GET_ATTRIB(packet->insn[i - j - 1].opcode, A_IT_EXTENDER)) { 146 def_idx--; 147 } 148 } 149 150 /* 151 * Check for a badly encoded N-field which points to an instruction 152 * out-of-range 153 */ 154 g_assert(!((def_idx < 0) || (def_idx > (packet->num_insns - 1)))); 155 156 /* 157 * packet->insn[def_idx] is the producer 158 * Figure out which type of destination it produces 159 * and the corresponding index in the reginfo 160 */ 161 def_opcode = packet->insn[def_idx].opcode; 162 dststr = strstr(opcode_wregs[def_opcode], "Rd"); 163 if (dststr) { 164 dststr = strchr(opcode_reginfo[def_opcode], 'd'); 165 } else { 166 dststr = strstr(opcode_wregs[def_opcode], "Rx"); 167 if (dststr) { 168 dststr = strchr(opcode_reginfo[def_opcode], 'x'); 169 } else { 170 dststr = strstr(opcode_wregs[def_opcode], "Re"); 171 if (dststr) { 172 dststr = strchr(opcode_reginfo[def_opcode], 'e'); 173 } else { 174 dststr = strstr(opcode_wregs[def_opcode], "Ry"); 175 if (dststr) { 176 dststr = strchr(opcode_reginfo[def_opcode], 'y'); 177 } else { 178 g_assert_not_reached(); 179 } 180 } 181 } 182 } 183 g_assert(dststr != NULL); 184 185 /* Now patch up the consumer with the register number */ 186 dst_idx = dststr - opcode_reginfo[def_opcode]; 187 g_assert(packet->insn[def_idx].dest_idx != -1 && 188 packet->insn[def_idx].dest_idx == dst_idx); 189 packet->insn[i].regno[use_regidx] = 190 packet->insn[def_idx].regno[dst_idx]; 191 /* 192 * We need to remember who produces this value to later 193 * check if it was dynamically cancelled 194 */ 195 packet->insn[i].new_value_producer_slot = 196 packet->insn[def_idx].slot; 197 } 198 } 199 } 200 201 /* Split CJ into a compare and a jump */ 202 static void decode_split_cmpjump(Packet *pkt) 203 { 204 int last, i; 205 int numinsns = pkt->num_insns; 206 207 /* 208 * First, split all compare-jumps. 209 * The compare is sent to the end as a new instruction. 210 * Do it this way so we don't reorder dual jumps. Those need to stay in 211 * original order. 212 */ 213 for (i = 0; i < numinsns; i++) { 214 /* It's a cmp-jump */ 215 if (GET_ATTRIB(pkt->insn[i].opcode, A_NEWCMPJUMP)) { 216 last = pkt->num_insns; 217 pkt->insn[last] = pkt->insn[i]; /* copy the instruction */ 218 pkt->insn[last].part1 = true; /* last insn does the CMP */ 219 pkt->insn[i].part1 = false; /* existing insn does the JUMP */ 220 pkt->num_insns++; 221 } 222 } 223 224 /* Now re-shuffle all the compares back to the beginning */ 225 for (i = 0; i < pkt->num_insns; i++) { 226 if (pkt->insn[i].part1) { 227 decode_send_insn_to(pkt, i, 0); 228 } 229 } 230 } 231 232 static bool decode_opcode_can_jump(int opcode) 233 { 234 if ((GET_ATTRIB(opcode, A_JUMP)) || 235 (GET_ATTRIB(opcode, A_CALL)) || 236 (opcode == J2_trap0) || 237 (opcode == J2_pause)) { 238 /* Exception to A_JUMP attribute */ 239 if (opcode == J4_hintjumpr) { 240 return false; 241 } 242 return true; 243 } 244 245 return false; 246 } 247 248 static bool decode_opcode_ends_loop(int opcode) 249 { 250 return GET_ATTRIB(opcode, A_HWLOOP0_END) || 251 GET_ATTRIB(opcode, A_HWLOOP1_END); 252 } 253 254 /* Set the is_* fields in each instruction */ 255 static void decode_set_insn_attr_fields(Packet *pkt) 256 { 257 int i; 258 int numinsns = pkt->num_insns; 259 uint16_t opcode; 260 261 pkt->pkt_has_cof = false; 262 pkt->pkt_has_multi_cof = false; 263 pkt->pkt_has_endloop = false; 264 pkt->pkt_has_dczeroa = false; 265 266 for (i = 0; i < numinsns; i++) { 267 opcode = pkt->insn[i].opcode; 268 if (pkt->insn[i].part1) { 269 continue; /* Skip compare of cmp-jumps */ 270 } 271 272 if (GET_ATTRIB(opcode, A_DCZEROA)) { 273 pkt->pkt_has_dczeroa = true; 274 } 275 276 if (GET_ATTRIB(opcode, A_STORE)) { 277 if (GET_ATTRIB(opcode, A_SCALAR_STORE) && 278 !GET_ATTRIB(opcode, A_MEMSIZE_0B)) { 279 if (pkt->insn[i].slot == 0) { 280 pkt->pkt_has_store_s0 = true; 281 } else { 282 pkt->pkt_has_store_s1 = true; 283 } 284 } 285 } 286 287 if (decode_opcode_can_jump(opcode)) { 288 if (pkt->pkt_has_cof) { 289 pkt->pkt_has_multi_cof = true; 290 } 291 pkt->pkt_has_cof = true; 292 } 293 294 pkt->insn[i].is_endloop = decode_opcode_ends_loop(opcode); 295 296 pkt->pkt_has_endloop |= pkt->insn[i].is_endloop; 297 298 if (pkt->pkt_has_endloop) { 299 if (pkt->pkt_has_cof) { 300 pkt->pkt_has_multi_cof = true; 301 } 302 pkt->pkt_has_cof = true; 303 } 304 } 305 } 306 307 /* 308 * Shuffle for execution 309 * Move stores to end (in same order as encoding) 310 * Move compares to beginning (for use by .new insns) 311 */ 312 static void decode_shuffle_for_execution(Packet *packet) 313 { 314 bool changed = false; 315 int i; 316 bool flag; /* flag means we've seen a non-memory instruction */ 317 int n_mems; 318 int last_insn = packet->num_insns - 1; 319 320 /* 321 * Skip end loops, somehow an end loop is getting in and messing 322 * up the order 323 */ 324 if (decode_opcode_ends_loop(packet->insn[last_insn].opcode)) { 325 last_insn--; 326 } 327 328 do { 329 changed = false; 330 /* 331 * Stores go last, must not reorder. 332 * Cannot shuffle stores past loads, either. 333 * Iterate backwards. If we see a non-memory instruction, 334 * then a store, shuffle the store to the front. Don't shuffle 335 * stores wrt each other or a load. 336 */ 337 for (flag = false, n_mems = 0, i = last_insn; i >= 0; i--) { 338 int opcode = packet->insn[i].opcode; 339 340 if (flag && GET_ATTRIB(opcode, A_STORE)) { 341 decode_send_insn_to(packet, i, last_insn - n_mems); 342 n_mems++; 343 changed = true; 344 } else if (GET_ATTRIB(opcode, A_STORE)) { 345 n_mems++; 346 } else if (GET_ATTRIB(opcode, A_LOAD)) { 347 /* 348 * Don't set flag, since we don't want to shuffle a 349 * store past a load 350 */ 351 n_mems++; 352 } else if (GET_ATTRIB(opcode, A_DOTNEWVALUE)) { 353 /* 354 * Don't set flag, since we don't want to shuffle past 355 * a .new value 356 */ 357 } else { 358 flag = true; 359 } 360 } 361 362 if (changed) { 363 continue; 364 } 365 /* Compares go first, may be reordered wrt each other */ 366 for (flag = false, i = 0; i < last_insn + 1; i++) { 367 int opcode = packet->insn[i].opcode; 368 369 g_assert(packet->insn[i].has_pred_dest == 370 (strstr(opcode_wregs[opcode], "Pd4") || 371 strstr(opcode_wregs[opcode], "Pe4"))); 372 if ((strstr(opcode_wregs[opcode], "Pd4") || 373 strstr(opcode_wregs[opcode], "Pe4")) && 374 GET_ATTRIB(opcode, A_STORE) == 0) { 375 /* This should be a compare (not a store conditional) */ 376 if (flag) { 377 decode_send_insn_to(packet, i, 0); 378 changed = true; 379 continue; 380 } 381 } else if (GET_ATTRIB(opcode, A_IMPLICIT_WRITES_P3) && 382 !decode_opcode_ends_loop(packet->insn[i].opcode)) { 383 /* 384 * spNloop instruction 385 * Don't reorder endloops; they are not valid for .new uses, 386 * and we want to match HW 387 */ 388 if (flag) { 389 decode_send_insn_to(packet, i, 0); 390 changed = true; 391 continue; 392 } 393 } else if (GET_ATTRIB(opcode, A_IMPLICIT_WRITES_P0) && 394 !GET_ATTRIB(opcode, A_NEWCMPJUMP)) { 395 if (flag) { 396 decode_send_insn_to(packet, i, 0); 397 changed = true; 398 continue; 399 } 400 } else { 401 flag = true; 402 } 403 } 404 if (changed) { 405 continue; 406 } 407 } while (changed); 408 409 /* 410 * If we have a .new register compare/branch, move that to the very 411 * very end, past stores 412 */ 413 for (i = 0; i < last_insn; i++) { 414 if (GET_ATTRIB(packet->insn[i].opcode, A_DOTNEWVALUE)) { 415 decode_send_insn_to(packet, i, last_insn); 416 break; 417 } 418 } 419 } 420 421 static void 422 apply_extender(Packet *pkt, int i, uint32_t extender) 423 { 424 int immed_num; 425 uint32_t base_immed; 426 427 immed_num = pkt->insn[i].which_extended; 428 base_immed = pkt->insn[i].immed[immed_num]; 429 430 pkt->insn[i].immed[immed_num] = extender | fZXTN(6, 32, base_immed); 431 } 432 433 static void decode_apply_extenders(Packet *packet) 434 { 435 int i; 436 for (i = 0; i < packet->num_insns; i++) { 437 if (GET_ATTRIB(packet->insn[i].opcode, A_IT_EXTENDER)) { 438 packet->insn[i + 1].extension_valid = true; 439 apply_extender(packet, i + 1, packet->insn[i].immed[0]); 440 } 441 } 442 } 443 444 static void decode_remove_extenders(Packet *packet) 445 { 446 int i, j; 447 for (i = 0; i < packet->num_insns; i++) { 448 if (GET_ATTRIB(packet->insn[i].opcode, A_IT_EXTENDER)) { 449 /* Remove this one by moving the remaining instructions down */ 450 for (j = i; 451 (j < packet->num_insns - 1) && (j < INSTRUCTIONS_MAX - 1); 452 j++) { 453 packet->insn[j] = packet->insn[j + 1]; 454 } 455 packet->num_insns--; 456 } 457 } 458 } 459 460 static SlotMask get_valid_slots(const Packet *pkt, unsigned int slot) 461 { 462 if (GET_ATTRIB(pkt->insn[slot].opcode, A_EXTENSION)) { 463 return mmvec_ext_decode_find_iclass_slots(pkt->insn[slot].opcode); 464 } else { 465 return find_iclass_slots(pkt->insn[slot].opcode, 466 pkt->insn[slot].iclass); 467 } 468 } 469 470 /* 471 * Section 10.3 of the Hexagon V73 Programmer's Reference Manual 472 * 473 * A duplex is encoded as a 32-bit instruction with bits [15:14] set to 00. 474 * The sub-instructions that comprise a duplex are encoded as 13-bit fields 475 * in the duplex. 476 * 477 * Per table 10-4, the 4-bit duplex iclass is encoded in bits 31:29, 13 478 */ 479 static uint32_t get_duplex_iclass(uint32_t encoding) 480 { 481 uint32_t iclass = extract32(encoding, 13, 1); 482 iclass = deposit32(iclass, 1, 3, extract32(encoding, 29, 3)); 483 return iclass; 484 } 485 486 /* 487 * Per table 10-5, the duplex ICLASS field values that specify the group of 488 * each sub-instruction in a duplex 489 * 490 * This table points to the decode instruction for each entry in the table 491 */ 492 typedef bool (*subinsn_decode_func)(DisasContext *ctx, uint16_t insn); 493 typedef struct { 494 subinsn_decode_func decode_slot0_subinsn; 495 subinsn_decode_func decode_slot1_subinsn; 496 } subinsn_decode_groups; 497 498 static const subinsn_decode_groups decode_groups[16] = { 499 [0x0] = { decode_subinsn_l1, decode_subinsn_l1 }, 500 [0x1] = { decode_subinsn_l2, decode_subinsn_l1 }, 501 [0x2] = { decode_subinsn_l2, decode_subinsn_l2 }, 502 [0x3] = { decode_subinsn_a, decode_subinsn_a }, 503 [0x4] = { decode_subinsn_l1, decode_subinsn_a }, 504 [0x5] = { decode_subinsn_l2, decode_subinsn_a }, 505 [0x6] = { decode_subinsn_s1, decode_subinsn_a }, 506 [0x7] = { decode_subinsn_s2, decode_subinsn_a }, 507 [0x8] = { decode_subinsn_s1, decode_subinsn_l1 }, 508 [0x9] = { decode_subinsn_s1, decode_subinsn_l2 }, 509 [0xa] = { decode_subinsn_s1, decode_subinsn_s1 }, 510 [0xb] = { decode_subinsn_s2, decode_subinsn_s1 }, 511 [0xc] = { decode_subinsn_s2, decode_subinsn_l1 }, 512 [0xd] = { decode_subinsn_s2, decode_subinsn_l2 }, 513 [0xe] = { decode_subinsn_s2, decode_subinsn_s2 }, 514 [0xf] = { NULL, NULL }, /* Reserved */ 515 }; 516 517 static uint16_t get_slot0_subinsn(uint32_t encoding) 518 { 519 return extract32(encoding, 0, 13); 520 } 521 522 static uint16_t get_slot1_subinsn(uint32_t encoding) 523 { 524 return extract32(encoding, 16, 13); 525 } 526 527 static unsigned int 528 decode_insns(DisasContext *ctx, Insn *insn, uint32_t encoding) 529 { 530 if (parse_bits(encoding) != 0) { 531 if (decode_normal(ctx, encoding) || 532 decode_hvx(ctx, encoding)) { 533 insn->generate = opcode_genptr[insn->opcode]; 534 insn->iclass = iclass_bits(encoding); 535 return 1; 536 } 537 g_assert_not_reached(); 538 } else { 539 uint32_t iclass = get_duplex_iclass(encoding); 540 unsigned int slot0_subinsn = get_slot0_subinsn(encoding); 541 unsigned int slot1_subinsn = get_slot1_subinsn(encoding); 542 subinsn_decode_func decode_slot0_subinsn = 543 decode_groups[iclass].decode_slot0_subinsn; 544 subinsn_decode_func decode_slot1_subinsn = 545 decode_groups[iclass].decode_slot1_subinsn; 546 547 /* The slot1 subinsn needs to be in the packet first */ 548 if (decode_slot1_subinsn(ctx, slot1_subinsn)) { 549 insn->generate = opcode_genptr[insn->opcode]; 550 insn->iclass = iclass_bits(encoding); 551 ctx->insn = ++insn; 552 if (decode_slot0_subinsn(ctx, slot0_subinsn)) { 553 insn->generate = opcode_genptr[insn->opcode]; 554 insn->iclass = iclass_bits(encoding); 555 return 2; 556 } 557 } 558 g_assert_not_reached(); 559 } 560 } 561 562 static void decode_add_endloop_insn(Insn *insn, int loopnum) 563 { 564 if (loopnum == 10) { 565 insn->opcode = J2_endloop01; 566 insn->generate = opcode_genptr[J2_endloop01]; 567 } else if (loopnum == 1) { 568 insn->opcode = J2_endloop1; 569 insn->generate = opcode_genptr[J2_endloop1]; 570 } else if (loopnum == 0) { 571 insn->opcode = J2_endloop0; 572 insn->generate = opcode_genptr[J2_endloop0]; 573 } else { 574 g_assert_not_reached(); 575 } 576 } 577 578 static bool decode_parsebits_is_loopend(uint32_t encoding32) 579 { 580 uint32_t bits = parse_bits(encoding32); 581 return bits == 0x2; 582 } 583 584 static bool has_valid_slot_assignment(Packet *pkt) 585 { 586 int used_slots = 0; 587 for (int i = 0; i < pkt->num_insns; i++) { 588 int slot_mask; 589 Insn *insn = &pkt->insn[i]; 590 if (decode_opcode_ends_loop(insn->opcode)) { 591 /* We overload slot 0 for endloop. */ 592 continue; 593 } 594 slot_mask = 1 << insn->slot; 595 if (used_slots & slot_mask) { 596 return false; 597 } 598 used_slots |= slot_mask; 599 } 600 return true; 601 } 602 603 static bool 604 decode_set_slot_number(Packet *pkt) 605 { 606 int slot; 607 int i; 608 bool hit_mem_insn = false; 609 bool hit_duplex = false; 610 bool slot0_found = false; 611 bool slot1_found = false; 612 int slot1_iidx = 0; 613 614 /* 615 * The slots are encoded in reverse order 616 * For each instruction, count down until you find a suitable slot 617 */ 618 for (i = 0, slot = 3; i < pkt->num_insns; i++) { 619 SlotMask valid_slots = get_valid_slots(pkt, i); 620 621 while (!(valid_slots & (1 << slot))) { 622 slot--; 623 } 624 pkt->insn[i].slot = slot; 625 if (slot) { 626 /* I've assigned the slot, now decrement it for the next insn */ 627 slot--; 628 } 629 } 630 631 /* Fix the exceptions - mem insns to slot 0,1 */ 632 for (i = pkt->num_insns - 1; i >= 0; i--) { 633 /* First memory instruction always goes to slot 0 */ 634 if ((GET_ATTRIB(pkt->insn[i].opcode, A_MEMLIKE) || 635 GET_ATTRIB(pkt->insn[i].opcode, A_MEMLIKE_PACKET_RULES)) && 636 !hit_mem_insn) { 637 hit_mem_insn = true; 638 pkt->insn[i].slot = 0; 639 continue; 640 } 641 642 /* Next memory instruction always goes to slot 1 */ 643 if ((GET_ATTRIB(pkt->insn[i].opcode, A_MEMLIKE) || 644 GET_ATTRIB(pkt->insn[i].opcode, A_MEMLIKE_PACKET_RULES)) && 645 hit_mem_insn) { 646 pkt->insn[i].slot = 1; 647 } 648 } 649 650 /* Fix the exceptions - duplex always slot 0,1 */ 651 for (i = pkt->num_insns - 1; i >= 0; i--) { 652 /* First subinsn always goes to slot 0 */ 653 if (GET_ATTRIB(pkt->insn[i].opcode, A_SUBINSN) && !hit_duplex) { 654 hit_duplex = true; 655 pkt->insn[i].slot = 0; 656 continue; 657 } 658 659 /* Next subinsn always goes to slot 1 */ 660 if (GET_ATTRIB(pkt->insn[i].opcode, A_SUBINSN) && hit_duplex) { 661 pkt->insn[i].slot = 1; 662 } 663 } 664 665 /* Fix the exceptions - slot 1 is never empty, always aligns to slot 0 */ 666 for (i = pkt->num_insns - 1; i >= 0; i--) { 667 /* Is slot0 used? */ 668 if (pkt->insn[i].slot == 0) { 669 bool is_endloop = (pkt->insn[i].opcode == J2_endloop01); 670 is_endloop |= (pkt->insn[i].opcode == J2_endloop0); 671 is_endloop |= (pkt->insn[i].opcode == J2_endloop1); 672 673 /* 674 * Make sure it's not endloop since, we're overloading 675 * slot0 for endloop 676 */ 677 if (!is_endloop) { 678 slot0_found = true; 679 } 680 } 681 /* Is slot1 used? */ 682 if (pkt->insn[i].slot == 1) { 683 slot1_found = true; 684 slot1_iidx = i; 685 } 686 } 687 /* Is slot0 empty and slot1 used? */ 688 if ((!slot0_found) && slot1_found) { 689 /* Then push it to slot0 */ 690 pkt->insn[slot1_iidx].slot = 0; 691 } 692 693 return has_valid_slot_assignment(pkt); 694 } 695 696 /* 697 * decode_packet 698 * Decodes packet with given words 699 * Returns 0 on insufficient words, 700 * or number of words used on success 701 */ 702 703 int decode_packet(DisasContext *ctx, int max_words, const uint32_t *words, 704 Packet *pkt, bool disas_only) 705 { 706 int num_insns = 0; 707 int words_read = 0; 708 bool end_of_packet = false; 709 int new_insns = 0; 710 int i; 711 uint32_t encoding32; 712 713 /* Initialize */ 714 memset(pkt, 0, sizeof(*pkt)); 715 /* Try to build packet */ 716 while (!end_of_packet && (words_read < max_words)) { 717 Insn *insn = &pkt->insn[num_insns]; 718 ctx->insn = insn; 719 encoding32 = words[words_read]; 720 end_of_packet = is_packet_end(encoding32); 721 new_insns = decode_insns(ctx, insn, encoding32); 722 g_assert(new_insns > 0); 723 /* 724 * If we saw an extender, mark next word extended so immediate 725 * decode works 726 */ 727 if (pkt->insn[num_insns].opcode == A4_ext) { 728 pkt->insn[num_insns + 1].extension_valid = true; 729 } 730 num_insns += new_insns; 731 words_read++; 732 } 733 734 pkt->num_insns = num_insns; 735 if (!end_of_packet) { 736 /* Ran out of words! */ 737 return 0; 738 } 739 pkt->encod_pkt_size_in_bytes = words_read * 4; 740 pkt->pkt_has_hvx = false; 741 for (i = 0; i < num_insns; i++) { 742 pkt->pkt_has_hvx |= 743 GET_ATTRIB(pkt->insn[i].opcode, A_CVI); 744 } 745 746 /* 747 * Check for :endloop in the parse bits 748 * Section 10.6 of the Programmer's Reference describes the encoding 749 * The end of hardware loop 0 can be encoded with 2 words 750 * The end of hardware loop 1 needs 3 words 751 */ 752 if ((words_read == 2) && (decode_parsebits_is_loopend(words[0]))) { 753 decode_add_endloop_insn(&pkt->insn[pkt->num_insns++], 0); 754 } 755 if (words_read >= 3) { 756 bool has_loop0, has_loop1; 757 has_loop0 = decode_parsebits_is_loopend(words[0]); 758 has_loop1 = decode_parsebits_is_loopend(words[1]); 759 if (has_loop0 && has_loop1) { 760 decode_add_endloop_insn(&pkt->insn[pkt->num_insns++], 10); 761 } else if (has_loop1) { 762 decode_add_endloop_insn(&pkt->insn[pkt->num_insns++], 1); 763 } else if (has_loop0) { 764 decode_add_endloop_insn(&pkt->insn[pkt->num_insns++], 0); 765 } 766 } 767 768 decode_apply_extenders(pkt); 769 if (!disas_only) { 770 decode_remove_extenders(pkt); 771 if (!decode_set_slot_number(pkt)) { 772 /* Invalid packet */ 773 return 0; 774 } 775 } 776 decode_fill_newvalue_regno(pkt); 777 778 if (pkt->pkt_has_hvx) { 779 mmvec_ext_decode_checks(pkt, disas_only); 780 } 781 782 if (!disas_only) { 783 decode_shuffle_for_execution(pkt); 784 decode_split_cmpjump(pkt); 785 decode_set_insn_attr_fields(pkt); 786 } 787 788 return words_read; 789 } 790 791 /* Used for "-d in_asm" logging */ 792 int disassemble_hexagon(uint32_t *words, int nwords, bfd_vma pc, 793 GString *buf) 794 { 795 DisasContext ctx; 796 Packet pkt; 797 798 memset(&ctx, 0, sizeof(DisasContext)); 799 ctx.pkt = &pkt; 800 801 if (decode_packet(&ctx, nwords, words, &pkt, true) > 0) { 802 snprint_a_pkt_disas(buf, &pkt, words, pc); 803 return pkt.encod_pkt_size_in_bytes; 804 } else { 805 g_string_assign(buf, "<invalid>"); 806 return 0; 807 } 808 } 809