1 /* 2 * Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #define QEMU_GENERATE 19 #include "qemu/osdep.h" 20 #include "cpu.h" 21 #include "tcg/tcg-op.h" 22 #include "tcg/tcg-op-gvec.h" 23 #include "exec/cpu_ldst.h" 24 #include "exec/log.h" 25 #include "internal.h" 26 #include "attribs.h" 27 #include "insn.h" 28 #include "decode.h" 29 #include "translate.h" 30 #include "printinsn.h" 31 32 TCGv hex_gpr[TOTAL_PER_THREAD_REGS]; 33 TCGv hex_pred[NUM_PREGS]; 34 TCGv hex_this_PC; 35 TCGv hex_slot_cancelled; 36 TCGv hex_branch_taken; 37 TCGv hex_new_value[TOTAL_PER_THREAD_REGS]; 38 TCGv hex_reg_written[TOTAL_PER_THREAD_REGS]; 39 TCGv hex_new_pred_value[NUM_PREGS]; 40 TCGv hex_pred_written; 41 TCGv hex_store_addr[STORES_MAX]; 42 TCGv hex_store_width[STORES_MAX]; 43 TCGv hex_store_val32[STORES_MAX]; 44 TCGv_i64 hex_store_val64[STORES_MAX]; 45 TCGv hex_pkt_has_store_s1; 46 TCGv hex_dczero_addr; 47 TCGv hex_llsc_addr; 48 TCGv hex_llsc_val; 49 TCGv_i64 hex_llsc_val_i64; 50 TCGv hex_VRegs_updated; 51 TCGv hex_QRegs_updated; 52 TCGv hex_vstore_addr[VSTORES_MAX]; 53 TCGv hex_vstore_size[VSTORES_MAX]; 54 TCGv hex_vstore_pending[VSTORES_MAX]; 55 56 static const char * const hexagon_prednames[] = { 57 "p0", "p1", "p2", "p3" 58 }; 59 60 intptr_t ctx_future_vreg_off(DisasContext *ctx, int regnum, 61 int num, bool alloc_ok) 62 { 63 intptr_t offset; 64 65 /* See if it is already allocated */ 66 for (int i = 0; i < ctx->future_vregs_idx; i++) { 67 if (ctx->future_vregs_num[i] == regnum) { 68 return offsetof(CPUHexagonState, future_VRegs[i]); 69 } 70 } 71 72 g_assert(alloc_ok); 73 offset = offsetof(CPUHexagonState, future_VRegs[ctx->future_vregs_idx]); 74 for (int i = 0; i < num; i++) { 75 ctx->future_vregs_num[ctx->future_vregs_idx + i] = regnum++; 76 } 77 ctx->future_vregs_idx += num; 78 g_assert(ctx->future_vregs_idx <= VECTOR_TEMPS_MAX); 79 return offset; 80 } 81 82 intptr_t ctx_tmp_vreg_off(DisasContext *ctx, int regnum, 83 int num, bool alloc_ok) 84 { 85 intptr_t offset; 86 87 /* See if it is already allocated */ 88 for (int i = 0; i < ctx->tmp_vregs_idx; i++) { 89 if (ctx->tmp_vregs_num[i] == regnum) { 90 return offsetof(CPUHexagonState, tmp_VRegs[i]); 91 } 92 } 93 94 g_assert(alloc_ok); 95 offset = offsetof(CPUHexagonState, tmp_VRegs[ctx->tmp_vregs_idx]); 96 for (int i = 0; i < num; i++) { 97 ctx->tmp_vregs_num[ctx->tmp_vregs_idx + i] = regnum++; 98 } 99 ctx->tmp_vregs_idx += num; 100 g_assert(ctx->tmp_vregs_idx <= VECTOR_TEMPS_MAX); 101 return offset; 102 } 103 104 static void gen_exception_raw(int excp) 105 { 106 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 107 } 108 109 static void gen_exec_counters(DisasContext *ctx) 110 { 111 tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_PKT_CNT], 112 hex_gpr[HEX_REG_QEMU_PKT_CNT], ctx->num_packets); 113 tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_INSN_CNT], 114 hex_gpr[HEX_REG_QEMU_INSN_CNT], ctx->num_insns); 115 tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_HVX_CNT], 116 hex_gpr[HEX_REG_QEMU_HVX_CNT], ctx->num_hvx_insns); 117 } 118 119 static bool use_goto_tb(DisasContext *ctx, target_ulong dest) 120 { 121 return translator_use_goto_tb(&ctx->base, dest); 122 } 123 124 static void gen_goto_tb(DisasContext *ctx, int idx, target_ulong dest) 125 { 126 if (use_goto_tb(ctx, dest)) { 127 tcg_gen_goto_tb(idx); 128 tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], dest); 129 tcg_gen_exit_tb(ctx->base.tb, idx); 130 } else { 131 tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], dest); 132 tcg_gen_lookup_and_goto_ptr(); 133 } 134 } 135 136 static void gen_end_tb(DisasContext *ctx) 137 { 138 Packet *pkt = ctx->pkt; 139 140 gen_exec_counters(ctx); 141 142 if (ctx->branch_cond != TCG_COND_NEVER) { 143 if (ctx->branch_cond != TCG_COND_ALWAYS) { 144 TCGLabel *skip = gen_new_label(); 145 tcg_gen_brcondi_tl(ctx->branch_cond, hex_branch_taken, 0, skip); 146 gen_goto_tb(ctx, 0, ctx->branch_dest); 147 gen_set_label(skip); 148 gen_goto_tb(ctx, 1, ctx->next_PC); 149 } else { 150 gen_goto_tb(ctx, 0, ctx->branch_dest); 151 } 152 } else if (ctx->is_tight_loop && 153 pkt->insn[pkt->num_insns - 1].opcode == J2_endloop0) { 154 /* 155 * When we're in a tight loop, we defer the endloop0 processing 156 * to take advantage of direct block chaining 157 */ 158 TCGLabel *skip = gen_new_label(); 159 tcg_gen_brcondi_tl(TCG_COND_LEU, hex_gpr[HEX_REG_LC0], 1, skip); 160 tcg_gen_subi_tl(hex_gpr[HEX_REG_LC0], hex_gpr[HEX_REG_LC0], 1); 161 gen_goto_tb(ctx, 0, ctx->base.tb->pc); 162 gen_set_label(skip); 163 gen_goto_tb(ctx, 1, ctx->next_PC); 164 } else { 165 tcg_gen_lookup_and_goto_ptr(); 166 } 167 168 ctx->base.is_jmp = DISAS_NORETURN; 169 } 170 171 static void gen_exception_end_tb(DisasContext *ctx, int excp) 172 { 173 gen_exec_counters(ctx); 174 tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->next_PC); 175 gen_exception_raw(excp); 176 ctx->base.is_jmp = DISAS_NORETURN; 177 178 } 179 180 #define PACKET_BUFFER_LEN 1028 181 static void print_pkt(Packet *pkt) 182 { 183 GString *buf = g_string_sized_new(PACKET_BUFFER_LEN); 184 snprint_a_pkt_debug(buf, pkt); 185 HEX_DEBUG_LOG("%s", buf->str); 186 g_string_free(buf, true); 187 } 188 #define HEX_DEBUG_PRINT_PKT(pkt) \ 189 do { \ 190 if (HEX_DEBUG) { \ 191 print_pkt(pkt); \ 192 } \ 193 } while (0) 194 195 static int read_packet_words(CPUHexagonState *env, DisasContext *ctx, 196 uint32_t words[]) 197 { 198 bool found_end = false; 199 int nwords, max_words; 200 201 memset(words, 0, PACKET_WORDS_MAX * sizeof(uint32_t)); 202 for (nwords = 0; !found_end && nwords < PACKET_WORDS_MAX; nwords++) { 203 words[nwords] = 204 translator_ldl(env, &ctx->base, 205 ctx->base.pc_next + nwords * sizeof(uint32_t)); 206 found_end = is_packet_end(words[nwords]); 207 } 208 if (!found_end) { 209 /* Read too many words without finding the end */ 210 return 0; 211 } 212 213 /* Check for page boundary crossing */ 214 max_words = -(ctx->base.pc_next | TARGET_PAGE_MASK) / sizeof(uint32_t); 215 if (nwords > max_words) { 216 /* We can only cross a page boundary at the beginning of a TB */ 217 g_assert(ctx->base.num_insns == 1); 218 } 219 220 HEX_DEBUG_LOG("decode_packet: pc = 0x%x\n", ctx->base.pc_next); 221 HEX_DEBUG_LOG(" words = { "); 222 for (int i = 0; i < nwords; i++) { 223 HEX_DEBUG_LOG("0x%x, ", words[i]); 224 } 225 HEX_DEBUG_LOG("}\n"); 226 227 return nwords; 228 } 229 230 static bool check_for_attrib(Packet *pkt, int attrib) 231 { 232 for (int i = 0; i < pkt->num_insns; i++) { 233 if (GET_ATTRIB(pkt->insn[i].opcode, attrib)) { 234 return true; 235 } 236 } 237 return false; 238 } 239 240 static bool need_slot_cancelled(Packet *pkt) 241 { 242 return check_for_attrib(pkt, A_CONDEXEC); 243 } 244 245 static bool need_pred_written(Packet *pkt) 246 { 247 return check_for_attrib(pkt, A_WRITES_PRED_REG); 248 } 249 250 static bool need_next_PC(DisasContext *ctx) 251 { 252 Packet *pkt = ctx->pkt; 253 254 /* Check for conditional control flow or HW loop end */ 255 for (int i = 0; i < pkt->num_insns; i++) { 256 uint16_t opcode = pkt->insn[i].opcode; 257 if (GET_ATTRIB(opcode, A_CONDEXEC) && GET_ATTRIB(opcode, A_COF)) { 258 return true; 259 } 260 if (GET_ATTRIB(opcode, A_HWLOOP0_END) || 261 GET_ATTRIB(opcode, A_HWLOOP1_END)) { 262 return true; 263 } 264 } 265 return false; 266 } 267 268 static void gen_start_packet(DisasContext *ctx) 269 { 270 Packet *pkt = ctx->pkt; 271 target_ulong next_PC = ctx->base.pc_next + pkt->encod_pkt_size_in_bytes; 272 int i; 273 274 /* Clear out the disassembly context */ 275 ctx->next_PC = next_PC; 276 ctx->reg_log_idx = 0; 277 bitmap_zero(ctx->regs_written, TOTAL_PER_THREAD_REGS); 278 ctx->preg_log_idx = 0; 279 bitmap_zero(ctx->pregs_written, NUM_PREGS); 280 ctx->future_vregs_idx = 0; 281 ctx->tmp_vregs_idx = 0; 282 ctx->vreg_log_idx = 0; 283 bitmap_zero(ctx->vregs_updated_tmp, NUM_VREGS); 284 bitmap_zero(ctx->vregs_updated, NUM_VREGS); 285 bitmap_zero(ctx->vregs_select, NUM_VREGS); 286 ctx->qreg_log_idx = 0; 287 for (i = 0; i < STORES_MAX; i++) { 288 ctx->store_width[i] = 0; 289 } 290 tcg_gen_movi_tl(hex_pkt_has_store_s1, pkt->pkt_has_store_s1); 291 ctx->s1_store_processed = false; 292 ctx->pre_commit = true; 293 294 if (HEX_DEBUG) { 295 /* Handy place to set a breakpoint before the packet executes */ 296 gen_helper_debug_start_packet(cpu_env); 297 tcg_gen_movi_tl(hex_this_PC, ctx->base.pc_next); 298 } 299 300 /* Initialize the runtime state for packet semantics */ 301 if (need_slot_cancelled(pkt)) { 302 tcg_gen_movi_tl(hex_slot_cancelled, 0); 303 } 304 if (pkt->pkt_has_cof) { 305 if (pkt->pkt_has_multi_cof) { 306 tcg_gen_movi_tl(hex_branch_taken, 0); 307 } 308 if (need_next_PC(ctx)) { 309 tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], next_PC); 310 } 311 } 312 if (need_pred_written(pkt)) { 313 tcg_gen_movi_tl(hex_pred_written, 0); 314 } 315 316 if (pkt->pkt_has_hvx) { 317 tcg_gen_movi_tl(hex_VRegs_updated, 0); 318 tcg_gen_movi_tl(hex_QRegs_updated, 0); 319 } 320 } 321 322 bool is_gather_store_insn(DisasContext *ctx) 323 { 324 Packet *pkt = ctx->pkt; 325 Insn *insn = ctx->insn; 326 if (GET_ATTRIB(insn->opcode, A_CVI_NEW) && 327 insn->new_value_producer_slot == 1) { 328 /* Look for gather instruction */ 329 for (int i = 0; i < pkt->num_insns; i++) { 330 Insn *in = &pkt->insn[i]; 331 if (GET_ATTRIB(in->opcode, A_CVI_GATHER) && in->slot == 1) { 332 return true; 333 } 334 } 335 } 336 return false; 337 } 338 339 /* 340 * The LOG_*_WRITE macros mark most of the writes in a packet 341 * However, there are some implicit writes marked as attributes 342 * of the applicable instructions. 343 */ 344 static void mark_implicit_reg_write(DisasContext *ctx, int attrib, int rnum) 345 { 346 uint16_t opcode = ctx->insn->opcode; 347 if (GET_ATTRIB(opcode, attrib)) { 348 /* 349 * USR is used to set overflow and FP exceptions, 350 * so treat it as conditional 351 */ 352 bool is_predicated = GET_ATTRIB(opcode, A_CONDEXEC) || 353 rnum == HEX_REG_USR; 354 355 /* LC0/LC1 is conditionally written by endloop instructions */ 356 if ((rnum == HEX_REG_LC0 || rnum == HEX_REG_LC1) && 357 (opcode == J2_endloop0 || 358 opcode == J2_endloop1 || 359 opcode == J2_endloop01)) { 360 is_predicated = true; 361 } 362 363 if (is_predicated && !is_preloaded(ctx, rnum)) { 364 tcg_gen_mov_tl(hex_new_value[rnum], hex_gpr[rnum]); 365 } 366 367 ctx_log_reg_write(ctx, rnum); 368 } 369 } 370 371 static void mark_implicit_pred_write(DisasContext *ctx, int attrib, int pnum) 372 { 373 if (GET_ATTRIB(ctx->insn->opcode, attrib)) { 374 ctx_log_pred_write(ctx, pnum); 375 } 376 } 377 378 static void mark_implicit_reg_writes(DisasContext *ctx) 379 { 380 mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_FP, HEX_REG_FP); 381 mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_SP, HEX_REG_SP); 382 mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_LR, HEX_REG_LR); 383 mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_LC0, HEX_REG_LC0); 384 mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_SA0, HEX_REG_SA0); 385 mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_LC1, HEX_REG_LC1); 386 mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_SA1, HEX_REG_SA1); 387 mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_USR, HEX_REG_USR); 388 mark_implicit_reg_write(ctx, A_FPOP, HEX_REG_USR); 389 } 390 391 static void mark_implicit_pred_writes(DisasContext *ctx) 392 { 393 mark_implicit_pred_write(ctx, A_IMPLICIT_WRITES_P0, 0); 394 mark_implicit_pred_write(ctx, A_IMPLICIT_WRITES_P1, 1); 395 mark_implicit_pred_write(ctx, A_IMPLICIT_WRITES_P2, 2); 396 mark_implicit_pred_write(ctx, A_IMPLICIT_WRITES_P3, 3); 397 } 398 399 static void mark_store_width(DisasContext *ctx) 400 { 401 uint16_t opcode = ctx->insn->opcode; 402 uint32_t slot = ctx->insn->slot; 403 uint8_t width = 0; 404 405 if (GET_ATTRIB(opcode, A_SCALAR_STORE)) { 406 if (GET_ATTRIB(opcode, A_MEMSIZE_1B)) { 407 width |= 1; 408 } 409 if (GET_ATTRIB(opcode, A_MEMSIZE_2B)) { 410 width |= 2; 411 } 412 if (GET_ATTRIB(opcode, A_MEMSIZE_4B)) { 413 width |= 4; 414 } 415 if (GET_ATTRIB(opcode, A_MEMSIZE_8B)) { 416 width |= 8; 417 } 418 tcg_debug_assert(is_power_of_2(width)); 419 ctx->store_width[slot] = width; 420 } 421 } 422 423 static void gen_insn(DisasContext *ctx) 424 { 425 if (ctx->insn->generate) { 426 mark_implicit_reg_writes(ctx); 427 ctx->insn->generate(ctx); 428 mark_implicit_pred_writes(ctx); 429 mark_store_width(ctx); 430 } else { 431 gen_exception_end_tb(ctx, HEX_EXCP_INVALID_OPCODE); 432 } 433 } 434 435 /* 436 * Helpers for generating the packet commit 437 */ 438 static void gen_reg_writes(DisasContext *ctx) 439 { 440 int i; 441 442 for (i = 0; i < ctx->reg_log_idx; i++) { 443 int reg_num = ctx->reg_log[i]; 444 445 tcg_gen_mov_tl(hex_gpr[reg_num], hex_new_value[reg_num]); 446 447 /* 448 * ctx->is_tight_loop is set when SA0 points to the beginning of the TB. 449 * If we write to SA0, we have to turn off tight loop handling. 450 */ 451 if (reg_num == HEX_REG_SA0) { 452 ctx->is_tight_loop = false; 453 } 454 } 455 } 456 457 static void gen_pred_writes(DisasContext *ctx) 458 { 459 int i; 460 461 /* Early exit if the log is empty */ 462 if (!ctx->preg_log_idx) { 463 return; 464 } 465 466 /* 467 * Only endloop instructions will conditionally 468 * write a predicate. If there are no endloop 469 * instructions, we can use the non-conditional 470 * write of the predicates. 471 */ 472 if (ctx->pkt->pkt_has_endloop) { 473 TCGv zero = tcg_constant_tl(0); 474 TCGv pred_written = tcg_temp_new(); 475 for (i = 0; i < ctx->preg_log_idx; i++) { 476 int pred_num = ctx->preg_log[i]; 477 478 tcg_gen_andi_tl(pred_written, hex_pred_written, 1 << pred_num); 479 tcg_gen_movcond_tl(TCG_COND_NE, hex_pred[pred_num], 480 pred_written, zero, 481 hex_new_pred_value[pred_num], 482 hex_pred[pred_num]); 483 } 484 } else { 485 for (i = 0; i < ctx->preg_log_idx; i++) { 486 int pred_num = ctx->preg_log[i]; 487 tcg_gen_mov_tl(hex_pred[pred_num], hex_new_pred_value[pred_num]); 488 if (HEX_DEBUG) { 489 /* Do this so HELPER(debug_commit_end) will know */ 490 tcg_gen_ori_tl(hex_pred_written, hex_pred_written, 491 1 << pred_num); 492 } 493 } 494 } 495 } 496 497 static void gen_check_store_width(DisasContext *ctx, int slot_num) 498 { 499 if (HEX_DEBUG) { 500 TCGv slot = tcg_constant_tl(slot_num); 501 TCGv check = tcg_constant_tl(ctx->store_width[slot_num]); 502 gen_helper_debug_check_store_width(cpu_env, slot, check); 503 } 504 } 505 506 static bool slot_is_predicated(Packet *pkt, int slot_num) 507 { 508 for (int i = 0; i < pkt->num_insns; i++) { 509 if (pkt->insn[i].slot == slot_num) { 510 return GET_ATTRIB(pkt->insn[i].opcode, A_CONDEXEC); 511 } 512 } 513 /* If we get to here, we didn't find an instruction in the requested slot */ 514 g_assert_not_reached(); 515 } 516 517 void process_store(DisasContext *ctx, int slot_num) 518 { 519 bool is_predicated = slot_is_predicated(ctx->pkt, slot_num); 520 TCGLabel *label_end = NULL; 521 522 /* 523 * We may have already processed this store 524 * See CHECK_NOSHUF in macros.h 525 */ 526 if (slot_num == 1 && ctx->s1_store_processed) { 527 return; 528 } 529 ctx->s1_store_processed = true; 530 531 if (is_predicated) { 532 TCGv cancelled = tcg_temp_new(); 533 label_end = gen_new_label(); 534 535 /* Don't do anything if the slot was cancelled */ 536 tcg_gen_extract_tl(cancelled, hex_slot_cancelled, slot_num, 1); 537 tcg_gen_brcondi_tl(TCG_COND_NE, cancelled, 0, label_end); 538 } 539 { 540 TCGv address = tcg_temp_new(); 541 tcg_gen_mov_tl(address, hex_store_addr[slot_num]); 542 543 /* 544 * If we know the width from the DisasContext, we can 545 * generate much cleaner code. 546 * Unfortunately, not all instructions execute the fSTORE 547 * macro during code generation. Anything that uses the 548 * generic helper will have this problem. Instructions 549 * that use fWRAP to generate proper TCG code will be OK. 550 */ 551 switch (ctx->store_width[slot_num]) { 552 case 1: 553 gen_check_store_width(ctx, slot_num); 554 tcg_gen_qemu_st8(hex_store_val32[slot_num], 555 hex_store_addr[slot_num], 556 ctx->mem_idx); 557 break; 558 case 2: 559 gen_check_store_width(ctx, slot_num); 560 tcg_gen_qemu_st16(hex_store_val32[slot_num], 561 hex_store_addr[slot_num], 562 ctx->mem_idx); 563 break; 564 case 4: 565 gen_check_store_width(ctx, slot_num); 566 tcg_gen_qemu_st32(hex_store_val32[slot_num], 567 hex_store_addr[slot_num], 568 ctx->mem_idx); 569 break; 570 case 8: 571 gen_check_store_width(ctx, slot_num); 572 tcg_gen_qemu_st64(hex_store_val64[slot_num], 573 hex_store_addr[slot_num], 574 ctx->mem_idx); 575 break; 576 default: 577 { 578 /* 579 * If we get to here, we don't know the width at 580 * TCG generation time, we'll use a helper to 581 * avoid branching based on the width at runtime. 582 */ 583 TCGv slot = tcg_constant_tl(slot_num); 584 gen_helper_commit_store(cpu_env, slot); 585 } 586 } 587 } 588 if (is_predicated) { 589 gen_set_label(label_end); 590 } 591 } 592 593 static void process_store_log(DisasContext *ctx) 594 { 595 /* 596 * When a packet has two stores, the hardware processes 597 * slot 1 and then slot 0. This will be important when 598 * the memory accesses overlap. 599 */ 600 Packet *pkt = ctx->pkt; 601 if (pkt->pkt_has_store_s1) { 602 g_assert(!pkt->pkt_has_dczeroa); 603 process_store(ctx, 1); 604 } 605 if (pkt->pkt_has_store_s0) { 606 g_assert(!pkt->pkt_has_dczeroa); 607 process_store(ctx, 0); 608 } 609 } 610 611 /* Zero out a 32-bit cache line */ 612 static void process_dczeroa(DisasContext *ctx) 613 { 614 if (ctx->pkt->pkt_has_dczeroa) { 615 /* Store 32 bytes of zero starting at (addr & ~0x1f) */ 616 TCGv addr = tcg_temp_new(); 617 TCGv_i64 zero = tcg_constant_i64(0); 618 619 tcg_gen_andi_tl(addr, hex_dczero_addr, ~0x1f); 620 tcg_gen_qemu_st64(zero, addr, ctx->mem_idx); 621 tcg_gen_addi_tl(addr, addr, 8); 622 tcg_gen_qemu_st64(zero, addr, ctx->mem_idx); 623 tcg_gen_addi_tl(addr, addr, 8); 624 tcg_gen_qemu_st64(zero, addr, ctx->mem_idx); 625 tcg_gen_addi_tl(addr, addr, 8); 626 tcg_gen_qemu_st64(zero, addr, ctx->mem_idx); 627 } 628 } 629 630 static bool pkt_has_hvx_store(Packet *pkt) 631 { 632 int i; 633 for (i = 0; i < pkt->num_insns; i++) { 634 int opcode = pkt->insn[i].opcode; 635 if (GET_ATTRIB(opcode, A_CVI) && GET_ATTRIB(opcode, A_STORE)) { 636 return true; 637 } 638 } 639 return false; 640 } 641 642 static void gen_commit_hvx(DisasContext *ctx) 643 { 644 int i; 645 646 /* 647 * for (i = 0; i < ctx->vreg_log_idx; i++) { 648 * int rnum = ctx->vreg_log[i]; 649 * if (ctx->vreg_is_predicated[i]) { 650 * if (env->VRegs_updated & (1 << rnum)) { 651 * env->VRegs[rnum] = env->future_VRegs[rnum]; 652 * } 653 * } else { 654 * env->VRegs[rnum] = env->future_VRegs[rnum]; 655 * } 656 * } 657 */ 658 for (i = 0; i < ctx->vreg_log_idx; i++) { 659 int rnum = ctx->vreg_log[i]; 660 bool is_predicated = ctx->vreg_is_predicated[i]; 661 intptr_t dstoff = offsetof(CPUHexagonState, VRegs[rnum]); 662 intptr_t srcoff = ctx_future_vreg_off(ctx, rnum, 1, false); 663 size_t size = sizeof(MMVector); 664 665 if (is_predicated) { 666 TCGv cmp = tcg_temp_new(); 667 TCGLabel *label_skip = gen_new_label(); 668 669 tcg_gen_andi_tl(cmp, hex_VRegs_updated, 1 << rnum); 670 tcg_gen_brcondi_tl(TCG_COND_EQ, cmp, 0, label_skip); 671 tcg_gen_gvec_mov(MO_64, dstoff, srcoff, size, size); 672 gen_set_label(label_skip); 673 } else { 674 tcg_gen_gvec_mov(MO_64, dstoff, srcoff, size, size); 675 } 676 } 677 678 /* 679 * for (i = 0; i < ctx->qreg_log_idx; i++) { 680 * int rnum = ctx->qreg_log[i]; 681 * if (ctx->qreg_is_predicated[i]) { 682 * if (env->QRegs_updated) & (1 << rnum)) { 683 * env->QRegs[rnum] = env->future_QRegs[rnum]; 684 * } 685 * } else { 686 * env->QRegs[rnum] = env->future_QRegs[rnum]; 687 * } 688 * } 689 */ 690 for (i = 0; i < ctx->qreg_log_idx; i++) { 691 int rnum = ctx->qreg_log[i]; 692 bool is_predicated = ctx->qreg_is_predicated[i]; 693 intptr_t dstoff = offsetof(CPUHexagonState, QRegs[rnum]); 694 intptr_t srcoff = offsetof(CPUHexagonState, future_QRegs[rnum]); 695 size_t size = sizeof(MMQReg); 696 697 if (is_predicated) { 698 TCGv cmp = tcg_temp_new(); 699 TCGLabel *label_skip = gen_new_label(); 700 701 tcg_gen_andi_tl(cmp, hex_QRegs_updated, 1 << rnum); 702 tcg_gen_brcondi_tl(TCG_COND_EQ, cmp, 0, label_skip); 703 tcg_gen_gvec_mov(MO_64, dstoff, srcoff, size, size); 704 gen_set_label(label_skip); 705 } else { 706 tcg_gen_gvec_mov(MO_64, dstoff, srcoff, size, size); 707 } 708 } 709 710 if (pkt_has_hvx_store(ctx->pkt)) { 711 gen_helper_commit_hvx_stores(cpu_env); 712 } 713 } 714 715 static void update_exec_counters(DisasContext *ctx) 716 { 717 Packet *pkt = ctx->pkt; 718 int num_insns = pkt->num_insns; 719 int num_real_insns = 0; 720 int num_hvx_insns = 0; 721 722 for (int i = 0; i < num_insns; i++) { 723 if (!pkt->insn[i].is_endloop && 724 !pkt->insn[i].part1 && 725 !GET_ATTRIB(pkt->insn[i].opcode, A_IT_NOP)) { 726 num_real_insns++; 727 } 728 if (GET_ATTRIB(pkt->insn[i].opcode, A_CVI)) { 729 num_hvx_insns++; 730 } 731 } 732 733 ctx->num_packets++; 734 ctx->num_insns += num_real_insns; 735 ctx->num_hvx_insns += num_hvx_insns; 736 } 737 738 static void gen_commit_packet(DisasContext *ctx) 739 { 740 /* 741 * If there is more than one store in a packet, make sure they are all OK 742 * before proceeding with the rest of the packet commit. 743 * 744 * dczeroa has to be the only store operation in the packet, so we go 745 * ahead and process that first. 746 * 747 * When there is an HVX store, there can also be a scalar store in either 748 * slot 0 or slot1, so we create a mask for the helper to indicate what 749 * work to do. 750 * 751 * When there are two scalar stores, we probe the one in slot 0. 752 * 753 * Note that we don't call the probe helper for packets with only one 754 * store. Therefore, we call process_store_log before anything else 755 * involved in committing the packet. 756 */ 757 Packet *pkt = ctx->pkt; 758 bool has_store_s0 = pkt->pkt_has_store_s0; 759 bool has_store_s1 = (pkt->pkt_has_store_s1 && !ctx->s1_store_processed); 760 bool has_hvx_store = pkt_has_hvx_store(pkt); 761 if (pkt->pkt_has_dczeroa) { 762 /* 763 * The dczeroa will be the store in slot 0, check that we don't have 764 * a store in slot 1 or an HVX store. 765 */ 766 g_assert(!has_store_s1 && !has_hvx_store); 767 process_dczeroa(ctx); 768 } else if (has_hvx_store) { 769 TCGv mem_idx = tcg_constant_tl(ctx->mem_idx); 770 771 if (!has_store_s0 && !has_store_s1) { 772 gen_helper_probe_hvx_stores(cpu_env, mem_idx); 773 } else { 774 int mask = 0; 775 TCGv mask_tcgv; 776 777 if (has_store_s0) { 778 mask |= (1 << 0); 779 } 780 if (has_store_s1) { 781 mask |= (1 << 1); 782 } 783 if (has_hvx_store) { 784 mask |= (1 << 2); 785 } 786 mask_tcgv = tcg_constant_tl(mask); 787 gen_helper_probe_pkt_scalar_hvx_stores(cpu_env, mask_tcgv, mem_idx); 788 } 789 } else if (has_store_s0 && has_store_s1) { 790 /* 791 * process_store_log will execute the slot 1 store first, 792 * so we only have to probe the store in slot 0 793 */ 794 TCGv mem_idx = tcg_constant_tl(ctx->mem_idx); 795 gen_helper_probe_pkt_scalar_store_s0(cpu_env, mem_idx); 796 } 797 798 process_store_log(ctx); 799 800 gen_reg_writes(ctx); 801 gen_pred_writes(ctx); 802 if (pkt->pkt_has_hvx) { 803 gen_commit_hvx(ctx); 804 } 805 update_exec_counters(ctx); 806 if (HEX_DEBUG) { 807 TCGv has_st0 = 808 tcg_constant_tl(pkt->pkt_has_store_s0 && !pkt->pkt_has_dczeroa); 809 TCGv has_st1 = 810 tcg_constant_tl(pkt->pkt_has_store_s1 && !pkt->pkt_has_dczeroa); 811 812 /* Handy place to set a breakpoint at the end of execution */ 813 gen_helper_debug_commit_end(cpu_env, has_st0, has_st1); 814 } 815 816 if (pkt->vhist_insn != NULL) { 817 ctx->pre_commit = false; 818 ctx->insn = pkt->vhist_insn; 819 pkt->vhist_insn->generate(ctx); 820 } 821 822 if (pkt->pkt_has_cof) { 823 gen_end_tb(ctx); 824 } 825 } 826 827 static void decode_and_translate_packet(CPUHexagonState *env, DisasContext *ctx) 828 { 829 uint32_t words[PACKET_WORDS_MAX]; 830 int nwords; 831 Packet pkt; 832 int i; 833 834 nwords = read_packet_words(env, ctx, words); 835 if (!nwords) { 836 gen_exception_end_tb(ctx, HEX_EXCP_INVALID_PACKET); 837 return; 838 } 839 840 if (decode_packet(nwords, words, &pkt, false) > 0) { 841 pkt.pc = ctx->base.pc_next; 842 HEX_DEBUG_PRINT_PKT(&pkt); 843 ctx->pkt = &pkt; 844 gen_start_packet(ctx); 845 for (i = 0; i < pkt.num_insns; i++) { 846 ctx->insn = &pkt.insn[i]; 847 gen_insn(ctx); 848 } 849 gen_commit_packet(ctx); 850 ctx->base.pc_next += pkt.encod_pkt_size_in_bytes; 851 } else { 852 gen_exception_end_tb(ctx, HEX_EXCP_INVALID_PACKET); 853 } 854 } 855 856 static void hexagon_tr_init_disas_context(DisasContextBase *dcbase, 857 CPUState *cs) 858 { 859 DisasContext *ctx = container_of(dcbase, DisasContext, base); 860 uint32_t hex_flags = dcbase->tb->flags; 861 862 ctx->mem_idx = MMU_USER_IDX; 863 ctx->num_packets = 0; 864 ctx->num_insns = 0; 865 ctx->num_hvx_insns = 0; 866 ctx->branch_cond = TCG_COND_NEVER; 867 ctx->is_tight_loop = FIELD_EX32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP); 868 } 869 870 static void hexagon_tr_tb_start(DisasContextBase *db, CPUState *cpu) 871 { 872 } 873 874 static void hexagon_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 875 { 876 DisasContext *ctx = container_of(dcbase, DisasContext, base); 877 878 tcg_gen_insn_start(ctx->base.pc_next); 879 } 880 881 static bool pkt_crosses_page(CPUHexagonState *env, DisasContext *ctx) 882 { 883 target_ulong page_start = ctx->base.pc_first & TARGET_PAGE_MASK; 884 bool found_end = false; 885 int nwords; 886 887 for (nwords = 0; !found_end && nwords < PACKET_WORDS_MAX; nwords++) { 888 uint32_t word = cpu_ldl_code(env, 889 ctx->base.pc_next + nwords * sizeof(uint32_t)); 890 found_end = is_packet_end(word); 891 } 892 uint32_t next_ptr = ctx->base.pc_next + nwords * sizeof(uint32_t); 893 return found_end && next_ptr - page_start >= TARGET_PAGE_SIZE; 894 } 895 896 static void hexagon_tr_translate_packet(DisasContextBase *dcbase, CPUState *cpu) 897 { 898 DisasContext *ctx = container_of(dcbase, DisasContext, base); 899 CPUHexagonState *env = cpu->env_ptr; 900 901 decode_and_translate_packet(env, ctx); 902 903 if (ctx->base.is_jmp == DISAS_NEXT) { 904 target_ulong page_start = ctx->base.pc_first & TARGET_PAGE_MASK; 905 target_ulong bytes_max = PACKET_WORDS_MAX * sizeof(target_ulong); 906 907 if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE || 908 (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE - bytes_max && 909 pkt_crosses_page(env, ctx))) { 910 ctx->base.is_jmp = DISAS_TOO_MANY; 911 } 912 913 /* 914 * The CPU log is used to compare against LLDB single stepping, 915 * so end the TLB after every packet. 916 */ 917 HexagonCPU *hex_cpu = env_archcpu(env); 918 if (hex_cpu->lldb_compat && qemu_loglevel_mask(CPU_LOG_TB_CPU)) { 919 ctx->base.is_jmp = DISAS_TOO_MANY; 920 } 921 } 922 } 923 924 static void hexagon_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 925 { 926 DisasContext *ctx = container_of(dcbase, DisasContext, base); 927 928 switch (ctx->base.is_jmp) { 929 case DISAS_TOO_MANY: 930 gen_exec_counters(ctx); 931 tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->base.pc_next); 932 tcg_gen_exit_tb(NULL, 0); 933 break; 934 case DISAS_NORETURN: 935 break; 936 default: 937 g_assert_not_reached(); 938 } 939 } 940 941 static void hexagon_tr_disas_log(const DisasContextBase *dcbase, 942 CPUState *cpu, FILE *logfile) 943 { 944 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 945 target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size); 946 } 947 948 949 static const TranslatorOps hexagon_tr_ops = { 950 .init_disas_context = hexagon_tr_init_disas_context, 951 .tb_start = hexagon_tr_tb_start, 952 .insn_start = hexagon_tr_insn_start, 953 .translate_insn = hexagon_tr_translate_packet, 954 .tb_stop = hexagon_tr_tb_stop, 955 .disas_log = hexagon_tr_disas_log, 956 }; 957 958 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 959 target_ulong pc, void *host_pc) 960 { 961 DisasContext ctx; 962 963 translator_loop(cs, tb, max_insns, pc, host_pc, 964 &hexagon_tr_ops, &ctx.base); 965 } 966 967 #define NAME_LEN 64 968 static char new_value_names[TOTAL_PER_THREAD_REGS][NAME_LEN]; 969 static char reg_written_names[TOTAL_PER_THREAD_REGS][NAME_LEN]; 970 static char new_pred_value_names[NUM_PREGS][NAME_LEN]; 971 static char store_addr_names[STORES_MAX][NAME_LEN]; 972 static char store_width_names[STORES_MAX][NAME_LEN]; 973 static char store_val32_names[STORES_MAX][NAME_LEN]; 974 static char store_val64_names[STORES_MAX][NAME_LEN]; 975 static char vstore_addr_names[VSTORES_MAX][NAME_LEN]; 976 static char vstore_size_names[VSTORES_MAX][NAME_LEN]; 977 static char vstore_pending_names[VSTORES_MAX][NAME_LEN]; 978 979 void hexagon_translate_init(void) 980 { 981 int i; 982 983 opcode_init(); 984 985 for (i = 0; i < TOTAL_PER_THREAD_REGS; i++) { 986 hex_gpr[i] = tcg_global_mem_new(cpu_env, 987 offsetof(CPUHexagonState, gpr[i]), 988 hexagon_regnames[i]); 989 990 snprintf(new_value_names[i], NAME_LEN, "new_%s", hexagon_regnames[i]); 991 hex_new_value[i] = tcg_global_mem_new(cpu_env, 992 offsetof(CPUHexagonState, new_value[i]), 993 new_value_names[i]); 994 995 if (HEX_DEBUG) { 996 snprintf(reg_written_names[i], NAME_LEN, "reg_written_%s", 997 hexagon_regnames[i]); 998 hex_reg_written[i] = tcg_global_mem_new(cpu_env, 999 offsetof(CPUHexagonState, reg_written[i]), 1000 reg_written_names[i]); 1001 } 1002 } 1003 for (i = 0; i < NUM_PREGS; i++) { 1004 hex_pred[i] = tcg_global_mem_new(cpu_env, 1005 offsetof(CPUHexagonState, pred[i]), 1006 hexagon_prednames[i]); 1007 1008 snprintf(new_pred_value_names[i], NAME_LEN, "new_pred_%s", 1009 hexagon_prednames[i]); 1010 hex_new_pred_value[i] = tcg_global_mem_new(cpu_env, 1011 offsetof(CPUHexagonState, new_pred_value[i]), 1012 new_pred_value_names[i]); 1013 } 1014 hex_pred_written = tcg_global_mem_new(cpu_env, 1015 offsetof(CPUHexagonState, pred_written), "pred_written"); 1016 hex_this_PC = tcg_global_mem_new(cpu_env, 1017 offsetof(CPUHexagonState, this_PC), "this_PC"); 1018 hex_slot_cancelled = tcg_global_mem_new(cpu_env, 1019 offsetof(CPUHexagonState, slot_cancelled), "slot_cancelled"); 1020 hex_branch_taken = tcg_global_mem_new(cpu_env, 1021 offsetof(CPUHexagonState, branch_taken), "branch_taken"); 1022 hex_pkt_has_store_s1 = tcg_global_mem_new(cpu_env, 1023 offsetof(CPUHexagonState, pkt_has_store_s1), "pkt_has_store_s1"); 1024 hex_dczero_addr = tcg_global_mem_new(cpu_env, 1025 offsetof(CPUHexagonState, dczero_addr), "dczero_addr"); 1026 hex_llsc_addr = tcg_global_mem_new(cpu_env, 1027 offsetof(CPUHexagonState, llsc_addr), "llsc_addr"); 1028 hex_llsc_val = tcg_global_mem_new(cpu_env, 1029 offsetof(CPUHexagonState, llsc_val), "llsc_val"); 1030 hex_llsc_val_i64 = tcg_global_mem_new_i64(cpu_env, 1031 offsetof(CPUHexagonState, llsc_val_i64), "llsc_val_i64"); 1032 hex_VRegs_updated = tcg_global_mem_new(cpu_env, 1033 offsetof(CPUHexagonState, VRegs_updated), "VRegs_updated"); 1034 hex_QRegs_updated = tcg_global_mem_new(cpu_env, 1035 offsetof(CPUHexagonState, QRegs_updated), "QRegs_updated"); 1036 for (i = 0; i < STORES_MAX; i++) { 1037 snprintf(store_addr_names[i], NAME_LEN, "store_addr_%d", i); 1038 hex_store_addr[i] = tcg_global_mem_new(cpu_env, 1039 offsetof(CPUHexagonState, mem_log_stores[i].va), 1040 store_addr_names[i]); 1041 1042 snprintf(store_width_names[i], NAME_LEN, "store_width_%d", i); 1043 hex_store_width[i] = tcg_global_mem_new(cpu_env, 1044 offsetof(CPUHexagonState, mem_log_stores[i].width), 1045 store_width_names[i]); 1046 1047 snprintf(store_val32_names[i], NAME_LEN, "store_val32_%d", i); 1048 hex_store_val32[i] = tcg_global_mem_new(cpu_env, 1049 offsetof(CPUHexagonState, mem_log_stores[i].data32), 1050 store_val32_names[i]); 1051 1052 snprintf(store_val64_names[i], NAME_LEN, "store_val64_%d", i); 1053 hex_store_val64[i] = tcg_global_mem_new_i64(cpu_env, 1054 offsetof(CPUHexagonState, mem_log_stores[i].data64), 1055 store_val64_names[i]); 1056 } 1057 for (int i = 0; i < VSTORES_MAX; i++) { 1058 snprintf(vstore_addr_names[i], NAME_LEN, "vstore_addr_%d", i); 1059 hex_vstore_addr[i] = tcg_global_mem_new(cpu_env, 1060 offsetof(CPUHexagonState, vstore[i].va), 1061 vstore_addr_names[i]); 1062 1063 snprintf(vstore_size_names[i], NAME_LEN, "vstore_size_%d", i); 1064 hex_vstore_size[i] = tcg_global_mem_new(cpu_env, 1065 offsetof(CPUHexagonState, vstore[i].size), 1066 vstore_size_names[i]); 1067 1068 snprintf(vstore_pending_names[i], NAME_LEN, "vstore_pending_%d", i); 1069 hex_vstore_pending[i] = tcg_global_mem_new(cpu_env, 1070 offsetof(CPUHexagonState, vstore_pending[i]), 1071 vstore_pending_names[i]); 1072 } 1073 } 1074