xref: /qemu/target/hppa/cpu.c (revision 8e31b744) 
1 /*
2  * QEMU HPPA CPU
3  *
4  * Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2.1 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see
18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
19  */
20 
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
23 #include "qemu/qemu-print.h"
24 #include "qemu/timer.h"
25 #include "cpu.h"
26 #include "qemu/module.h"
27 #include "exec/exec-all.h"
28 #include "fpu/softfloat.h"
29 #include "tcg/tcg.h"
30 
31 static void hppa_cpu_set_pc(CPUState *cs, vaddr value)
32 {
33     HPPACPU *cpu = HPPA_CPU(cs);
34 
35     cpu->env.iaoq_f = value;
36     cpu->env.iaoq_b = value + 4;
37 }
38 
39 static vaddr hppa_cpu_get_pc(CPUState *cs)
40 {
41     HPPACPU *cpu = HPPA_CPU(cs);
42 
43     return cpu->env.iaoq_f;
44 }
45 
46 static void hppa_cpu_synchronize_from_tb(CPUState *cs,
47                                          const TranslationBlock *tb)
48 {
49     HPPACPU *cpu = HPPA_CPU(cs);
50 
51     tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
52 
53 #ifdef CONFIG_USER_ONLY
54     cpu->env.iaoq_f = tb->pc;
55     cpu->env.iaoq_b = tb->cs_base;
56 #else
57     /* Recover the IAOQ values from the GVA + PRIV.  */
58     uint32_t priv = (tb->flags >> TB_FLAG_PRIV_SHIFT) & 3;
59     target_ulong cs_base = tb->cs_base;
60     target_ulong iasq_f = cs_base & ~0xffffffffull;
61     int32_t diff = cs_base;
62 
63     cpu->env.iasq_f = iasq_f;
64     cpu->env.iaoq_f = (tb->pc & ~iasq_f) + priv;
65     if (diff) {
66         cpu->env.iaoq_b = cpu->env.iaoq_f + diff;
67     }
68 #endif
69 
70     cpu->env.psw_n = (tb->flags & PSW_N) != 0;
71 }
72 
73 static void hppa_restore_state_to_opc(CPUState *cs,
74                                       const TranslationBlock *tb,
75                                       const uint64_t *data)
76 {
77     HPPACPU *cpu = HPPA_CPU(cs);
78 
79     cpu->env.iaoq_f = data[0];
80     if (data[1] != (target_ulong)-1) {
81         cpu->env.iaoq_b = data[1];
82     }
83     cpu->env.unwind_breg = data[2];
84     /*
85      * Since we were executing the instruction at IAOQ_F, and took some
86      * sort of action that provoked the cpu_restore_state, we can infer
87      * that the instruction was not nullified.
88      */
89     cpu->env.psw_n = 0;
90 }
91 
92 static bool hppa_cpu_has_work(CPUState *cs)
93 {
94     return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
95 }
96 
97 static int hppa_cpu_mmu_index(CPUState *cs, bool ifetch)
98 {
99     CPUHPPAState *env = cpu_env(cs);
100 
101     if (env->psw & (ifetch ? PSW_C : PSW_D)) {
102         return PRIV_P_TO_MMU_IDX(env->iaoq_f & 3, env->psw & PSW_P);
103     }
104     /* mmu disabled */
105     return env->psw & PSW_W ? MMU_ABS_W_IDX : MMU_ABS_IDX;
106 }
107 
108 static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info)
109 {
110     info->mach = bfd_mach_hppa20;
111     info->print_insn = print_insn_hppa;
112 }
113 
114 #ifndef CONFIG_USER_ONLY
115 static G_NORETURN
116 void hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
117                                   MMUAccessType access_type, int mmu_idx,
118                                   uintptr_t retaddr)
119 {
120     HPPACPU *cpu = HPPA_CPU(cs);
121     CPUHPPAState *env = &cpu->env;
122 
123     cs->exception_index = EXCP_UNALIGN;
124     hppa_set_ior_and_isr(env, addr, MMU_IDX_MMU_DISABLED(mmu_idx));
125 
126     cpu_loop_exit_restore(cs, retaddr);
127 }
128 #endif /* CONFIG_USER_ONLY */
129 
130 static void hppa_cpu_realizefn(DeviceState *dev, Error **errp)
131 {
132     CPUState *cs = CPU(dev);
133     HPPACPUClass *acc = HPPA_CPU_GET_CLASS(dev);
134     Error *local_err = NULL;
135 
136     cpu_exec_realizefn(cs, &local_err);
137     if (local_err != NULL) {
138         error_propagate(errp, local_err);
139         return;
140     }
141 
142     qemu_init_vcpu(cs);
143     acc->parent_realize(dev, errp);
144 
145 #ifndef CONFIG_USER_ONLY
146     {
147         HPPACPU *cpu = HPPA_CPU(cs);
148 
149         cpu->alarm_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
150                                         hppa_cpu_alarm_timer, cpu);
151         hppa_ptlbe(&cpu->env);
152     }
153 #endif
154 }
155 
156 static void hppa_cpu_initfn(Object *obj)
157 {
158     CPUState *cs = CPU(obj);
159     HPPACPU *cpu = HPPA_CPU(obj);
160     CPUHPPAState *env = &cpu->env;
161 
162     cs->exception_index = -1;
163     cpu_hppa_loaded_fr0(env);
164     cpu_hppa_put_psw(env, PSW_W);
165 }
166 
167 static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model)
168 {
169     g_autofree char *typename = g_strconcat(cpu_model, "-cpu", NULL);
170 
171     return object_class_by_name(typename);
172 }
173 
174 #ifndef CONFIG_USER_ONLY
175 #include "hw/core/sysemu-cpu-ops.h"
176 
177 static const struct SysemuCPUOps hppa_sysemu_ops = {
178     .get_phys_page_debug = hppa_cpu_get_phys_page_debug,
179 };
180 #endif
181 
182 #include "hw/core/tcg-cpu-ops.h"
183 
184 static const TCGCPUOps hppa_tcg_ops = {
185     .initialize = hppa_translate_init,
186     .synchronize_from_tb = hppa_cpu_synchronize_from_tb,
187     .restore_state_to_opc = hppa_restore_state_to_opc,
188 
189 #ifndef CONFIG_USER_ONLY
190     .tlb_fill = hppa_cpu_tlb_fill,
191     .cpu_exec_interrupt = hppa_cpu_exec_interrupt,
192     .do_interrupt = hppa_cpu_do_interrupt,
193     .do_unaligned_access = hppa_cpu_do_unaligned_access,
194     .do_transaction_failed = hppa_cpu_do_transaction_failed,
195 #endif /* !CONFIG_USER_ONLY */
196 };
197 
198 static void hppa_cpu_class_init(ObjectClass *oc, void *data)
199 {
200     DeviceClass *dc = DEVICE_CLASS(oc);
201     CPUClass *cc = CPU_CLASS(oc);
202     HPPACPUClass *acc = HPPA_CPU_CLASS(oc);
203 
204     device_class_set_parent_realize(dc, hppa_cpu_realizefn,
205                                     &acc->parent_realize);
206 
207     cc->class_by_name = hppa_cpu_class_by_name;
208     cc->has_work = hppa_cpu_has_work;
209     cc->mmu_index = hppa_cpu_mmu_index;
210     cc->dump_state = hppa_cpu_dump_state;
211     cc->set_pc = hppa_cpu_set_pc;
212     cc->get_pc = hppa_cpu_get_pc;
213     cc->gdb_read_register = hppa_cpu_gdb_read_register;
214     cc->gdb_write_register = hppa_cpu_gdb_write_register;
215 #ifndef CONFIG_USER_ONLY
216     dc->vmsd = &vmstate_hppa_cpu;
217     cc->sysemu_ops = &hppa_sysemu_ops;
218 #endif
219     cc->disas_set_info = hppa_cpu_disas_set_info;
220     cc->gdb_num_core_regs = 128;
221     cc->tcg_ops = &hppa_tcg_ops;
222 }
223 
224 static const TypeInfo hppa_cpu_type_infos[] = {
225     {
226         .name = TYPE_HPPA_CPU,
227         .parent = TYPE_CPU,
228         .instance_size = sizeof(HPPACPU),
229         .instance_align = __alignof(HPPACPU),
230         .instance_init = hppa_cpu_initfn,
231         .abstract = false,
232         .class_size = sizeof(HPPACPUClass),
233         .class_init = hppa_cpu_class_init,
234     },
235     {
236         .name = TYPE_HPPA64_CPU,
237         .parent = TYPE_HPPA_CPU,
238     },
239 };
240 
241 DEFINE_TYPES(hppa_cpu_type_infos)
242