xref: /qemu/target/hppa/cpu.c (revision e995d5cc)
1 /*
2  * QEMU HPPA CPU
3  *
4  * Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2.1 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see
18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
19  */
20 
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
23 #include "qemu/qemu-print.h"
24 #include "qemu/timer.h"
25 #include "cpu.h"
26 #include "qemu/module.h"
27 #include "exec/exec-all.h"
28 #include "fpu/softfloat.h"
29 #include "tcg/tcg.h"
30 
31 static void hppa_cpu_set_pc(CPUState *cs, vaddr value)
32 {
33     HPPACPU *cpu = HPPA_CPU(cs);
34 
35     cpu->env.iaoq_f = value;
36     cpu->env.iaoq_b = value + 4;
37 }
38 
39 static vaddr hppa_cpu_get_pc(CPUState *cs)
40 {
41     HPPACPU *cpu = HPPA_CPU(cs);
42 
43     return cpu->env.iaoq_f;
44 }
45 
46 static void hppa_cpu_synchronize_from_tb(CPUState *cs,
47                                          const TranslationBlock *tb)
48 {
49     HPPACPU *cpu = HPPA_CPU(cs);
50 
51     tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
52 
53 #ifdef CONFIG_USER_ONLY
54     cpu->env.iaoq_f = tb->pc;
55     cpu->env.iaoq_b = tb->cs_base;
56 #else
57     /* Recover the IAOQ values from the GVA + PRIV.  */
58     uint32_t priv = (tb->flags >> TB_FLAG_PRIV_SHIFT) & 3;
59     target_ulong cs_base = tb->cs_base;
60     target_ulong iasq_f = cs_base & ~0xffffffffull;
61     int32_t diff = cs_base;
62 
63     cpu->env.iasq_f = iasq_f;
64     cpu->env.iaoq_f = (tb->pc & ~iasq_f) + priv;
65     if (diff) {
66         cpu->env.iaoq_b = cpu->env.iaoq_f + diff;
67     }
68 #endif
69 
70     cpu->env.psw_n = (tb->flags & PSW_N) != 0;
71 }
72 
73 static void hppa_restore_state_to_opc(CPUState *cs,
74                                       const TranslationBlock *tb,
75                                       const uint64_t *data)
76 {
77     HPPACPU *cpu = HPPA_CPU(cs);
78 
79     cpu->env.iaoq_f = data[0];
80     if (data[1] != (target_ureg)-1) {
81         cpu->env.iaoq_b = data[1];
82     }
83     /*
84      * Since we were executing the instruction at IAOQ_F, and took some
85      * sort of action that provoked the cpu_restore_state, we can infer
86      * that the instruction was not nullified.
87      */
88     cpu->env.psw_n = 0;
89 }
90 
91 static bool hppa_cpu_has_work(CPUState *cs)
92 {
93     return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
94 }
95 
96 static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info)
97 {
98     info->mach = bfd_mach_hppa20;
99     info->print_insn = print_insn_hppa;
100 }
101 
102 #ifndef CONFIG_USER_ONLY
103 static G_NORETURN
104 void hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
105                                   MMUAccessType access_type, int mmu_idx,
106                                   uintptr_t retaddr)
107 {
108     HPPACPU *cpu = HPPA_CPU(cs);
109     CPUHPPAState *env = &cpu->env;
110 
111     cs->exception_index = EXCP_UNALIGN;
112     if (env->psw & PSW_Q) {
113         /* ??? Needs tweaking for hppa64.  */
114         env->cr[CR_IOR] = addr;
115         env->cr[CR_ISR] = addr >> 32;
116     }
117 
118     cpu_loop_exit_restore(cs, retaddr);
119 }
120 #endif /* CONFIG_USER_ONLY */
121 
122 static void hppa_cpu_realizefn(DeviceState *dev, Error **errp)
123 {
124     CPUState *cs = CPU(dev);
125     HPPACPUClass *acc = HPPA_CPU_GET_CLASS(dev);
126     Error *local_err = NULL;
127 
128     cpu_exec_realizefn(cs, &local_err);
129     if (local_err != NULL) {
130         error_propagate(errp, local_err);
131         return;
132     }
133 
134     qemu_init_vcpu(cs);
135     acc->parent_realize(dev, errp);
136 
137 #ifndef CONFIG_USER_ONLY
138     {
139         HPPACPU *cpu = HPPA_CPU(cs);
140         cpu->alarm_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
141                                         hppa_cpu_alarm_timer, cpu);
142     }
143 #endif
144 }
145 
146 static void hppa_cpu_initfn(Object *obj)
147 {
148     CPUState *cs = CPU(obj);
149     HPPACPU *cpu = HPPA_CPU(obj);
150     CPUHPPAState *env = &cpu->env;
151 
152     cpu_set_cpustate_pointers(cpu);
153     cs->exception_index = -1;
154     cpu_hppa_loaded_fr0(env);
155     cpu_hppa_put_psw(env, PSW_W);
156 }
157 
158 static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model)
159 {
160     return object_class_by_name(TYPE_HPPA_CPU);
161 }
162 
163 #ifndef CONFIG_USER_ONLY
164 #include "hw/core/sysemu-cpu-ops.h"
165 
166 static const struct SysemuCPUOps hppa_sysemu_ops = {
167     .get_phys_page_debug = hppa_cpu_get_phys_page_debug,
168 };
169 #endif
170 
171 #include "hw/core/tcg-cpu-ops.h"
172 
173 static const struct TCGCPUOps hppa_tcg_ops = {
174     .initialize = hppa_translate_init,
175     .synchronize_from_tb = hppa_cpu_synchronize_from_tb,
176     .restore_state_to_opc = hppa_restore_state_to_opc,
177 
178 #ifndef CONFIG_USER_ONLY
179     .tlb_fill = hppa_cpu_tlb_fill,
180     .cpu_exec_interrupt = hppa_cpu_exec_interrupt,
181     .do_interrupt = hppa_cpu_do_interrupt,
182     .do_unaligned_access = hppa_cpu_do_unaligned_access,
183 #endif /* !CONFIG_USER_ONLY */
184 };
185 
186 static void hppa_cpu_class_init(ObjectClass *oc, void *data)
187 {
188     DeviceClass *dc = DEVICE_CLASS(oc);
189     CPUClass *cc = CPU_CLASS(oc);
190     HPPACPUClass *acc = HPPA_CPU_CLASS(oc);
191 
192     device_class_set_parent_realize(dc, hppa_cpu_realizefn,
193                                     &acc->parent_realize);
194 
195     cc->class_by_name = hppa_cpu_class_by_name;
196     cc->has_work = hppa_cpu_has_work;
197     cc->dump_state = hppa_cpu_dump_state;
198     cc->set_pc = hppa_cpu_set_pc;
199     cc->get_pc = hppa_cpu_get_pc;
200     cc->gdb_read_register = hppa_cpu_gdb_read_register;
201     cc->gdb_write_register = hppa_cpu_gdb_write_register;
202 #ifndef CONFIG_USER_ONLY
203     dc->vmsd = &vmstate_hppa_cpu;
204     cc->sysemu_ops = &hppa_sysemu_ops;
205 #endif
206     cc->disas_set_info = hppa_cpu_disas_set_info;
207     cc->gdb_num_core_regs = 128;
208     cc->tcg_ops = &hppa_tcg_ops;
209 }
210 
211 static const TypeInfo hppa_cpu_type_info = {
212     .name = TYPE_HPPA_CPU,
213     .parent = TYPE_CPU,
214     .instance_size = sizeof(HPPACPU),
215     .instance_init = hppa_cpu_initfn,
216     .abstract = false,
217     .class_size = sizeof(HPPACPUClass),
218     .class_init = hppa_cpu_class_init,
219 };
220 
221 static void hppa_cpu_register_types(void)
222 {
223     type_register_static(&hppa_cpu_type_info);
224 }
225 
226 type_init(hppa_cpu_register_types)
227