1 /* 2 * PA-RISC emulation cpu definitions for qemu. 3 * 4 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef HPPA_CPU_H 21 #define HPPA_CPU_H 22 23 #include "cpu-qom.h" 24 #include "exec/cpu-defs.h" 25 26 /* PA-RISC 1.x processors have a strong memory model. */ 27 /* ??? While we do not yet implement PA-RISC 2.0, those processors have 28 a weak memory model, but with TLB bits that force ordering on a per-page 29 basis. It's probably easier to fall back to a strong memory model. */ 30 #define TCG_GUEST_DEFAULT_MO TCG_MO_ALL 31 32 #define MMU_KERNEL_IDX 0 33 #define MMU_USER_IDX 3 34 #define MMU_PHYS_IDX 4 35 #define TARGET_INSN_START_EXTRA_WORDS 1 36 37 /* Hardware exceptions, interupts, faults, and traps. */ 38 #define EXCP_HPMC 1 /* high priority machine check */ 39 #define EXCP_POWER_FAIL 2 40 #define EXCP_RC 3 /* recovery counter */ 41 #define EXCP_EXT_INTERRUPT 4 /* external interrupt */ 42 #define EXCP_LPMC 5 /* low priority machine check */ 43 #define EXCP_ITLB_MISS 6 /* itlb miss / instruction page fault */ 44 #define EXCP_IMP 7 /* instruction memory protection trap */ 45 #define EXCP_ILL 8 /* illegal instruction trap */ 46 #define EXCP_BREAK 9 /* break instruction */ 47 #define EXCP_PRIV_OPR 10 /* privileged operation trap */ 48 #define EXCP_PRIV_REG 11 /* privileged register trap */ 49 #define EXCP_OVERFLOW 12 /* signed overflow trap */ 50 #define EXCP_COND 13 /* trap-on-condition */ 51 #define EXCP_ASSIST 14 /* assist exception trap */ 52 #define EXCP_DTLB_MISS 15 /* dtlb miss / data page fault */ 53 #define EXCP_NA_ITLB_MISS 16 /* non-access itlb miss */ 54 #define EXCP_NA_DTLB_MISS 17 /* non-access dtlb miss */ 55 #define EXCP_DMP 18 /* data memory protection trap */ 56 #define EXCP_DMB 19 /* data memory break trap */ 57 #define EXCP_TLB_DIRTY 20 /* tlb dirty bit trap */ 58 #define EXCP_PAGE_REF 21 /* page reference trap */ 59 #define EXCP_ASSIST_EMU 22 /* assist emulation trap */ 60 #define EXCP_HPT 23 /* high-privilege transfer trap */ 61 #define EXCP_LPT 24 /* low-privilege transfer trap */ 62 #define EXCP_TB 25 /* taken branch trap */ 63 #define EXCP_DMAR 26 /* data memory access rights trap */ 64 #define EXCP_DMPI 27 /* data memory protection id trap */ 65 #define EXCP_UNALIGN 28 /* unaligned data reference trap */ 66 #define EXCP_PER_INTERRUPT 29 /* performance monitor interrupt */ 67 68 /* Exceptions for linux-user emulation. */ 69 #define EXCP_SYSCALL 30 70 #define EXCP_SYSCALL_LWS 31 71 72 /* Emulated hardware TOC button */ 73 #define EXCP_TOC 32 /* TOC = Transfer of control (NMI) */ 74 75 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 /* TOC */ 76 77 /* Taken from Linux kernel: arch/parisc/include/asm/psw.h */ 78 #define PSW_I 0x00000001 79 #define PSW_D 0x00000002 80 #define PSW_P 0x00000004 81 #define PSW_Q 0x00000008 82 #define PSW_R 0x00000010 83 #define PSW_F 0x00000020 84 #define PSW_G 0x00000040 /* PA1.x only */ 85 #define PSW_O 0x00000080 /* PA2.0 only */ 86 #define PSW_CB 0x0000ff00 87 #define PSW_M 0x00010000 88 #define PSW_V 0x00020000 89 #define PSW_C 0x00040000 90 #define PSW_B 0x00080000 91 #define PSW_X 0x00100000 92 #define PSW_N 0x00200000 93 #define PSW_L 0x00400000 94 #define PSW_H 0x00800000 95 #define PSW_T 0x01000000 96 #define PSW_S 0x02000000 97 #define PSW_E 0x04000000 98 #ifdef TARGET_HPPA64 99 #define PSW_W 0x08000000 /* PA2.0 only */ 100 #else 101 #define PSW_W 0 102 #endif 103 #define PSW_Z 0x40000000 /* PA1.x only */ 104 #define PSW_Y 0x80000000 /* PA1.x only */ 105 106 #define PSW_SM (PSW_W | PSW_E | PSW_O | PSW_G | PSW_F \ 107 | PSW_R | PSW_Q | PSW_P | PSW_D | PSW_I) 108 109 /* ssm/rsm instructions number PSW_W and PSW_E differently */ 110 #define PSW_SM_I PSW_I /* Enable External Interrupts */ 111 #define PSW_SM_D PSW_D 112 #define PSW_SM_P PSW_P 113 #define PSW_SM_Q PSW_Q /* Enable Interrupt State Collection */ 114 #define PSW_SM_R PSW_R /* Enable Recover Counter Trap */ 115 #ifdef TARGET_HPPA64 116 #define PSW_SM_E 0x100 117 #define PSW_SM_W 0x200 /* PA2.0 only : Enable Wide Mode */ 118 #else 119 #define PSW_SM_E 0 120 #define PSW_SM_W 0 121 #endif 122 123 #define CR_RC 0 124 #define CR_PID1 8 125 #define CR_PID2 9 126 #define CR_PID3 12 127 #define CR_PID4 13 128 #define CR_SCRCCR 10 129 #define CR_SAR 11 130 #define CR_IVA 14 131 #define CR_EIEM 15 132 #define CR_IT 16 133 #define CR_IIASQ 17 134 #define CR_IIAOQ 18 135 #define CR_IIR 19 136 #define CR_ISR 20 137 #define CR_IOR 21 138 #define CR_IPSW 22 139 #define CR_EIRR 23 140 141 typedef struct CPUHPPAState CPUHPPAState; 142 143 #if TARGET_REGISTER_BITS == 32 144 typedef uint32_t target_ureg; 145 typedef int32_t target_sreg; 146 #define TREG_FMT_lx "%08"PRIx32 147 #define TREG_FMT_ld "%"PRId32 148 #else 149 typedef uint64_t target_ureg; 150 typedef int64_t target_sreg; 151 #define TREG_FMT_lx "%016"PRIx64 152 #define TREG_FMT_ld "%"PRId64 153 #endif 154 155 typedef struct { 156 uint64_t va_b; 157 uint64_t va_e; 158 target_ureg pa; 159 unsigned u : 1; 160 unsigned t : 1; 161 unsigned d : 1; 162 unsigned b : 1; 163 unsigned page_size : 4; 164 unsigned ar_type : 3; 165 unsigned ar_pl1 : 2; 166 unsigned ar_pl2 : 2; 167 unsigned entry_valid : 1; 168 unsigned access_id : 16; 169 } hppa_tlb_entry; 170 171 struct CPUHPPAState { 172 target_ureg gr[32]; 173 uint64_t fr[32]; 174 uint64_t sr[8]; /* stored shifted into place for gva */ 175 176 target_ureg psw; /* All psw bits except the following: */ 177 target_ureg psw_n; /* boolean */ 178 target_sreg psw_v; /* in most significant bit */ 179 180 /* Splitting the carry-borrow field into the MSB and "the rest", allows 181 * for "the rest" to be deleted when it is unused, but the MSB is in use. 182 * In addition, it's easier to compute carry-in for bit B+1 than it is to 183 * compute carry-out for bit B (3 vs 4 insns for addition, assuming the 184 * host has the appropriate add-with-carry insn to compute the msb). 185 * Therefore the carry bits are stored as: cb_msb : cb & 0x11111110. 186 */ 187 target_ureg psw_cb; /* in least significant bit of next nibble */ 188 target_ureg psw_cb_msb; /* boolean */ 189 190 target_ureg iaoq_f; /* front */ 191 target_ureg iaoq_b; /* back, aka next instruction */ 192 uint64_t iasq_f; 193 uint64_t iasq_b; 194 195 uint32_t fr0_shadow; /* flags, c, ca/cq, rm, d, enables */ 196 float_status fp_status; 197 198 target_ureg cr[32]; /* control registers */ 199 target_ureg cr_back[2]; /* back of cr17/cr18 */ 200 target_ureg shadow[7]; /* shadow registers */ 201 202 /* ??? The number of entries isn't specified by the architecture. */ 203 #define HPPA_TLB_ENTRIES 256 204 #define HPPA_BTLB_ENTRIES 0 205 206 /* ??? Implement a unified itlb/dtlb for the moment. */ 207 /* ??? We should use a more intelligent data structure. */ 208 hppa_tlb_entry tlb[HPPA_TLB_ENTRIES]; 209 uint32_t tlb_last; 210 }; 211 212 /** 213 * HPPACPU: 214 * @env: #CPUHPPAState 215 * 216 * An HPPA CPU. 217 */ 218 struct HPPACPU { 219 /*< private >*/ 220 CPUState parent_obj; 221 /*< public >*/ 222 223 CPUNegativeOffsetState neg; 224 CPUHPPAState env; 225 QEMUTimer *alarm_timer; 226 }; 227 228 229 typedef CPUHPPAState CPUArchState; 230 typedef HPPACPU ArchCPU; 231 232 #include "exec/cpu-all.h" 233 234 static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch) 235 { 236 #ifdef CONFIG_USER_ONLY 237 return MMU_USER_IDX; 238 #else 239 if (env->psw & (ifetch ? PSW_C : PSW_D)) { 240 return env->iaoq_f & 3; 241 } 242 return MMU_PHYS_IDX; /* mmu disabled */ 243 #endif 244 } 245 246 void hppa_translate_init(void); 247 248 #define CPU_RESOLVING_TYPE TYPE_HPPA_CPU 249 250 static inline target_ulong hppa_form_gva_psw(target_ureg psw, uint64_t spc, 251 target_ureg off) 252 { 253 #ifdef CONFIG_USER_ONLY 254 return off; 255 #else 256 off &= (psw & PSW_W ? 0x3fffffffffffffffull : 0xffffffffull); 257 return spc | off; 258 #endif 259 } 260 261 static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc, 262 target_ureg off) 263 { 264 return hppa_form_gva_psw(env->psw, spc, off); 265 } 266 267 /* 268 * Since PSW_{I,CB} will never need to be in tb->flags, reuse them. 269 * TB_FLAG_SR_SAME indicates that SR4 through SR7 all contain the 270 * same value. 271 */ 272 #define TB_FLAG_SR_SAME PSW_I 273 #define TB_FLAG_PRIV_SHIFT 8 274 #define TB_FLAG_UNALIGN 0x400 275 276 static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *pc, 277 target_ulong *cs_base, 278 uint32_t *pflags) 279 { 280 uint32_t flags = env->psw_n * PSW_N; 281 282 /* TB lookup assumes that PC contains the complete virtual address. 283 If we leave space+offset separate, we'll get ITLB misses to an 284 incomplete virtual address. This also means that we must separate 285 out current cpu priviledge from the low bits of IAOQ_F. */ 286 #ifdef CONFIG_USER_ONLY 287 *pc = env->iaoq_f & -4; 288 *cs_base = env->iaoq_b & -4; 289 flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; 290 #else 291 /* ??? E, T, H, L, B, P bits need to be here, when implemented. */ 292 flags |= env->psw & (PSW_W | PSW_C | PSW_D); 293 flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; 294 295 *pc = (env->psw & PSW_C 296 ? hppa_form_gva_psw(env->psw, env->iasq_f, env->iaoq_f & -4) 297 : env->iaoq_f & -4); 298 *cs_base = env->iasq_f; 299 300 /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero 301 low 32-bits of CS_BASE. This will succeed for all direct branches, 302 which is the primary case we care about -- using goto_tb within a page. 303 Failure is indicated by a zero difference. */ 304 if (env->iasq_f == env->iasq_b) { 305 target_sreg diff = env->iaoq_b - env->iaoq_f; 306 if (TARGET_REGISTER_BITS == 32 || diff == (int32_t)diff) { 307 *cs_base |= (uint32_t)diff; 308 } 309 } 310 if ((env->sr[4] == env->sr[5]) 311 & (env->sr[4] == env->sr[6]) 312 & (env->sr[4] == env->sr[7])) { 313 flags |= TB_FLAG_SR_SAME; 314 } 315 #endif 316 317 *pflags = flags; 318 } 319 320 target_ureg cpu_hppa_get_psw(CPUHPPAState *env); 321 void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg); 322 void cpu_hppa_loaded_fr0(CPUHPPAState *env); 323 324 #ifdef CONFIG_USER_ONLY 325 static inline void cpu_hppa_change_prot_id(CPUHPPAState *env) { } 326 #else 327 void cpu_hppa_change_prot_id(CPUHPPAState *env); 328 #endif 329 330 hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); 331 int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 332 int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 333 void hppa_cpu_dump_state(CPUState *cs, FILE *f, int); 334 #ifndef CONFIG_USER_ONLY 335 bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 336 MMUAccessType access_type, int mmu_idx, 337 bool probe, uintptr_t retaddr); 338 void hppa_cpu_do_interrupt(CPUState *cpu); 339 bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req); 340 int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, 341 int type, hwaddr *pphys, int *pprot); 342 extern const MemoryRegionOps hppa_io_eir_ops; 343 extern const VMStateDescription vmstate_hppa_cpu; 344 void hppa_cpu_alarm_timer(void *); 345 int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr); 346 #endif 347 void QEMU_NORETURN hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra); 348 349 #endif /* HPPA_CPU_H */ 350