1# 2# HPPA instruction decode definitions. 3# 4# Copyright (c) 2018 Richard Henderson <rth@twiddle.net> 5# 6# This library is free software; you can redistribute it and/or 7# modify it under the terms of the GNU Lesser General Public 8# License as published by the Free Software Foundation; either 9# version 2.1 of the License, or (at your option) any later version. 10# 11# This library is distributed in the hope that it will be useful, 12# but WITHOUT ANY WARRANTY; without even the implied warranty of 13# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14# Lesser General Public License for more details. 15# 16# You should have received a copy of the GNU Lesser General Public 17# License along with this library; if not, see <http://www.gnu.org/licenses/>. 18# 19 20#### 21# Field definitions 22#### 23 24%assemble_sr3 13:1 14:2 25%assemble_sr3x 13:1 14:2 !function=expand_sr3x 26 27%assemble_11a 0:s1 4:10 !function=expand_shl3 28%assemble_12 0:s1 2:1 3:10 !function=expand_shl2 29%assemble_12a 0:s1 3:11 !function=expand_shl2 30%assemble_17 0:s1 16:5 2:1 3:10 !function=expand_shl2 31%assemble_22 0:s1 16:10 2:1 3:10 !function=expand_shl2 32 33%assemble_21 0:s1 1:11 14:2 16:5 12:2 !function=expand_shl11 34 35%lowsign_11 0:s1 1:10 36%lowsign_14 0:s1 1:13 37 38%sm_imm 16:10 !function=expand_sm_imm 39 40%rm64 1:1 16:5 41%rt64 6:1 0:5 42%ra64 7:1 21:5 43%rb64 12:1 16:5 44%rc64 8:1 13:3 9:2 45%rc32 13:3 9:2 46 47%im5_0 0:s1 1:4 48%im5_16 16:s1 17:4 49%len5 0:5 !function=assemble_6 50%len6_8 8:1 0:5 !function=assemble_6 51%len6_12 12:1 0:5 !function=assemble_6 52%cpos6_11 11:1 5:5 53%ma_to_m 5:1 13:1 !function=ma_to_m 54%ma2_to_m 2:2 !function=ma_to_m 55%pos_to_m 0:1 !function=pos_to_m 56%neg_to_m 0:1 !function=neg_to_m 57%a_to_m 2:1 !function=neg_to_m 58%cmpbid_c 13:2 !function=cmpbid_c 59 60#### 61# Argument set definitions 62#### 63 64# All insns that need to form a virtual address should use this set. 65&ldst t b x disp sp m scale size 66 67&rr_cf_d t r cf d 68&rrr t r1 r2 69&rrr_cf t r1 r2 cf 70&rrr_cf_d t r1 r2 cf d 71&rrr_sh t r1 r2 sh 72&rrr_cf_d_sh t r1 r2 cf d sh 73&rri t r i 74&rri_cf t r i cf 75&rri_cf_d t r i cf d 76 77&rrb_c_f disp n c f r1 r2 78&rrb_c_d_f disp n c d f r1 r2 79&rib_c_f disp n c f r i 80&rib_c_d_f disp n c d f r i 81 82#### 83# Format definitions 84#### 85 86@rr_cf_d ...... r:5 ..... cf:4 ...... d:1 t:5 &rr_cf_d 87@rrr ...... r2:5 r1:5 .... ....... t:5 &rrr 88@rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf 89@rrr_cf_d ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d 90@rrr_sh ...... r2:5 r1:5 ........ sh:2 . t:5 &rrr_sh 91@rrr_cf_d_sh ...... r2:5 r1:5 cf:4 .... sh:2 d:1 t:5 &rrr_cf_d_sh 92@rrr_cf_d_sh0 ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d_sh sh=0 93@rri_cf ...... r:5 t:5 cf:4 . ........... &rri_cf i=%lowsign_11 94@rri_cf_d ...... r:5 t:5 cf:4 d:1 ........... &rri_cf_d i=%lowsign_11 95 96@rrb_cf ...... r2:5 r1:5 c:3 ........... n:1 . \ 97 &rrb_c_f disp=%assemble_12 98@rrb_cdf ...... r2:5 r1:5 c:3 ........... n:1 . \ 99 &rrb_c_d_f disp=%assemble_12 100@rib_cf ...... r:5 ..... c:3 ........... n:1 . \ 101 &rib_c_f disp=%assemble_12 i=%im5_16 102@rib_cdf ...... r:5 ..... c:3 ........... n:1 . \ 103 &rib_c_d_f disp=%assemble_12 i=%im5_16 104 105#### 106# System 107#### 108 109break 000000 ----- ----- --- 00000000 ----- 110 111mtsp 000000 ----- r:5 ... 11000001 00000 sp=%assemble_sr3 112mtctl 000000 t:5 r:5 --- 11000010 00000 113mtsarcm 000000 01011 r:5 --- 11000110 00000 114mtsm 000000 00000 r:5 000 11000011 00000 115 116mfia 000000 ----- 00000 --- 10100101 t:5 117mfsp 000000 ----- 00000 ... 00100101 t:5 sp=%assemble_sr3 118mfctl 000000 r:5 00000- e:1 -01000101 t:5 119 120sync 000000 ----- ----- 000 00100000 00000 # sync, syncdma 121 122ldsid 000000 b:5 ----- sp:2 0 10000101 t:5 123 124rsm 000000 .......... 000 01110011 t:5 i=%sm_imm 125ssm 000000 .......... 000 01101011 t:5 i=%sm_imm 126 127rfi 000000 ----- ----- --- 01100000 00000 128rfi_r 000000 ----- ----- --- 01100101 00000 129 130# These are artificial instructions used by QEMU firmware. 131# They are allocated from the unassigned instruction space. 132halt 1111 1111 1111 1101 1110 1010 1101 0000 133reset 1111 1111 1111 1101 1110 1010 1101 0001 134getshadowregs 1111 1111 1111 1101 1110 1010 1101 0010 135 136#### 137# Memory Management 138#### 139 140@addrx ...... b:5 x:5 .. ........ m:1 ..... \ 141 &ldst disp=0 scale=0 t=0 sp=0 size=0 142 143nop 000001 ----- ----- -- 11001010 0 ----- # fdc, disp 144nop_addrx 000001 ..... ..... -- 01001010 . ----- @addrx # fdc, index 145nop_addrx 000001 ..... ..... -- 01001011 . ----- @addrx # fdce 146nop_addrx 000001 ..... ..... --- 0001010 . ----- @addrx # fic 0x0a 147nop_addrx 000001 ..... ..... -- 01001111 . 00000 @addrx # fic 0x4f 148nop_addrx 000001 ..... ..... --- 0001011 . ----- @addrx # fice 149nop_addrx 000001 ..... ..... -- 01001110 . 00000 @addrx # pdc 150 151probe 000001 b:5 ri:5 sp:2 imm:1 100011 write:1 0 t:5 152 153# pa1.x tlb insert instructions 154ixtlbx 000001 b:5 r:5 sp:2 0100000 addr:1 0 00000 data=1 155ixtlbx 000001 b:5 r:5 ... 000000 addr:1 0 00000 \ 156 sp=%assemble_sr3x data=0 157 158# pcxl and pcxl2 Fast TLB Insert instructions 159ixtlbxf 000001 00000 r:5 00 0 data:1 01000 addr:1 0 00000 160 161# pa2.0 tlb insert idtlbt and iitlbt instructions 162ixtlbt 000001 r2:5 r1:5 000 data:1 100000 0 00000 # idtlbt 163 164pxtlbx 000001 b:5 x:5 sp:2 0100100 local:1 m:1 ----- data=1 165pxtlbx 000001 b:5 x:5 ... 000100 local:1 m:1 ----- \ 166 sp=%assemble_sr3x data=0 167 168lpa 000001 b:5 x:5 sp:2 01001101 m:1 t:5 \ 169 &ldst disp=0 scale=0 size=0 170 171lci 000001 ----- ----- -- 01001100 0 t:5 172 173#### 174# Arith/Log 175#### 176 177andcm 000010 ..... ..... .... 000000 . ..... @rrr_cf_d 178and 000010 ..... ..... .... 001000 . ..... @rrr_cf_d 179or 000010 ..... ..... .... 001001 . ..... @rrr_cf_d 180xor 000010 ..... ..... .... 001010 . ..... @rrr_cf_d 181uxor 000010 ..... ..... .... 001110 . ..... @rrr_cf_d 182ds 000010 ..... ..... .... 010001 0 ..... @rrr_cf 183cmpclr 000010 ..... ..... .... 100010 . ..... @rrr_cf_d 184uaddcm 000010 ..... ..... .... 100110 . ..... @rrr_cf_d 185uaddcm_tc 000010 ..... ..... .... 100111 . ..... @rrr_cf_d 186dcor 000010 ..... 00000 .... 101110 . ..... @rr_cf_d 187dcor_i 000010 ..... 00000 .... 101111 . ..... @rr_cf_d 188 189add 000010 ..... ..... .... 0110.. . ..... @rrr_cf_d_sh 190add_l 000010 ..... ..... .... 1010.. . ..... @rrr_cf_d_sh 191add_tsv 000010 ..... ..... .... 1110.. . ..... @rrr_cf_d_sh 192{ 193 add_c 000010 ..... ..... .... 011100 . ..... @rrr_cf_d_sh0 194 hshladd 000010 ..... ..... 0000 0111.. 0 ..... @rrr_sh 195} 196add_c_tsv 000010 ..... ..... .... 111100 . ..... @rrr_cf_d_sh0 197 198sub 000010 ..... ..... .... 010000 . ..... @rrr_cf_d 199sub_tsv 000010 ..... ..... .... 110000 . ..... @rrr_cf_d 200sub_tc 000010 ..... ..... .... 010011 . ..... @rrr_cf_d 201sub_tsv_tc 000010 ..... ..... .... 110011 . ..... @rrr_cf_d 202{ 203 sub_b 000010 ..... ..... .... 010100 . ..... @rrr_cf_d 204 hshradd 000010 ..... ..... 0000 0101.. 0 ..... @rrr_sh 205} 206sub_b_tsv 000010 ..... ..... .... 110100 . ..... @rrr_cf_d 207 208ldil 001000 t:5 ..................... i=%assemble_21 209addil 001010 r:5 ..................... i=%assemble_21 210ldo 001101 b:5 t:5 -- .............. i=%lowsign_14 211 212addi 101101 ..... ..... .... 0 ........... @rri_cf 213addi_tsv 101101 ..... ..... .... 1 ........... @rri_cf 214addi_tc 101100 ..... ..... .... 0 ........... @rri_cf 215addi_tc_tsv 101100 ..... ..... .... 1 ........... @rri_cf 216 217subi 100101 ..... ..... .... 0 ........... @rri_cf 218subi_tsv 100101 ..... ..... .... 1 ........... @rri_cf 219 220cmpiclr 100100 ..... ..... .... . ........... @rri_cf_d 221 222hadd 000010 ..... ..... 00000011 11 0 ..... @rrr 223hadd_ss 000010 ..... ..... 00000011 01 0 ..... @rrr 224hadd_us 000010 ..... ..... 00000011 00 0 ..... @rrr 225 226havg 000010 ..... ..... 00000010 11 0 ..... @rrr 227 228hshl 111110 00000 r:5 100010 i:4 0 t:5 &rri 229hshr_s 111110 r:5 00000 110011 i:4 0 t:5 &rri 230hshr_u 111110 r:5 00000 110010 i:4 0 t:5 &rri 231 232hsub 000010 ..... ..... 00000001 11 0 ..... @rrr 233hsub_ss 000010 ..... ..... 00000001 01 0 ..... @rrr 234hsub_us 000010 ..... ..... 00000001 00 0 ..... @rrr 235 236mixh_l 111110 ..... ..... 1 00 00100000 ..... @rrr 237mixh_r 111110 ..... ..... 1 10 00100000 ..... @rrr 238mixw_l 111110 ..... ..... 1 00 00000000 ..... @rrr 239mixw_r 111110 ..... ..... 1 10 00000000 ..... @rrr 240 241permh 111110 r1:5 r2:5 0 c0:2 0 c1:2 c2:2 c3:2 0 t:5 242 243#### 244# Index Mem 245#### 246 247@ldstx ...... b:5 x:5 sp:2 scale:1 ....... m:1 t:5 &ldst disp=0 248@ldim5 ...... b:5 ..... sp:2 ......... t:5 \ 249 &ldst disp=%im5_16 x=0 scale=0 m=%ma_to_m 250@stim5 ...... b:5 t:5 sp:2 ......... ..... \ 251 &ldst disp=%im5_0 x=0 scale=0 m=%ma_to_m 252 253ld 000011 ..... ..... .. . 1 -- 00 size:2 ...... @ldim5 254ld 000011 ..... ..... .. . 0 -- 00 size:2 ...... @ldstx 255st 000011 ..... ..... .. . 1 -- 10 size:2 ...... @stim5 256ldc 000011 ..... ..... .. . 1 -- 0111 ...... @ldim5 size=2 257ldc 000011 ..... ..... .. . 0 -- 0111 ...... @ldstx size=2 258ldc 000011 ..... ..... .. . 1 -- 0101 ...... @ldim5 size=3 259ldc 000011 ..... ..... .. . 0 -- 0101 ...... @ldstx size=3 260lda 000011 ..... ..... .. . 1 -- 0110 ...... @ldim5 size=2 261lda 000011 ..... ..... .. . 0 -- 0110 ...... @ldstx size=2 262lda 000011 ..... ..... .. . 1 -- 0100 ...... @ldim5 size=3 263lda 000011 ..... ..... .. . 0 -- 0100 ...... @ldstx size=3 264sta 000011 ..... ..... .. . 1 -- 1110 ...... @stim5 size=2 265sta 000011 ..... ..... .. . 1 -- 1111 ...... @stim5 size=3 266stby 000011 b:5 r:5 sp:2 a:1 1 -- 1100 m:1 ..... disp=%im5_0 267stdby 000011 b:5 r:5 sp:2 a:1 1 -- 1101 m:1 ..... disp=%im5_0 268 269@fldstwx ...... b:5 x:5 sp:2 scale:1 ....... m:1 ..... \ 270 &ldst t=%rt64 disp=0 size=2 271@fldstwi ...... b:5 ..... sp:2 . ....... . ..... \ 272 &ldst t=%rt64 disp=%im5_16 m=%ma_to_m x=0 scale=0 size=2 273 274fldw 001001 ..... ..... .. . 0 -- 000 . . ..... @fldstwx 275fldw 001001 ..... ..... .. . 1 -- 000 . . ..... @fldstwi 276fstw 001001 ..... ..... .. . 0 -- 100 . . ..... @fldstwx 277fstw 001001 ..... ..... .. . 1 -- 100 . . ..... @fldstwi 278 279@fldstdx ...... b:5 x:5 sp:2 scale:1 ....... m:1 t:5 \ 280 &ldst disp=0 size=3 281@fldstdi ...... b:5 ..... sp:2 . ....... . t:5 \ 282 &ldst disp=%im5_16 m=%ma_to_m x=0 scale=0 size=3 283 284fldd 001011 ..... ..... .. . 0 -- 000 0 . ..... @fldstdx 285fldd 001011 ..... ..... .. . 1 -- 000 0 . ..... @fldstdi 286fstd 001011 ..... ..... .. . 0 -- 100 0 . ..... @fldstdx 287fstd 001011 ..... ..... .. . 1 -- 100 0 . ..... @fldstdi 288 289#### 290# Offset Mem 291#### 292 293@ldstim11 ...... b:5 t:5 sp:2 .............. \ 294 &ldst disp=%assemble_11a m=%ma2_to_m x=0 scale=0 size=3 295@ldstim14 ...... b:5 t:5 sp:2 .............. \ 296 &ldst disp=%lowsign_14 x=0 scale=0 m=0 297@ldstim14m ...... b:5 t:5 sp:2 .............. \ 298 &ldst disp=%lowsign_14 x=0 scale=0 m=%neg_to_m 299@ldstim12m ...... b:5 t:5 sp:2 .............. \ 300 &ldst disp=%assemble_12a x=0 scale=0 m=%pos_to_m 301 302# LDB, LDH, LDW, LDWM 303ld 010000 ..... ..... .. .............. @ldstim14 size=0 304ld 010001 ..... ..... .. .............. @ldstim14 size=1 305ld 010010 ..... ..... .. .............. @ldstim14 size=2 306ld 010011 ..... ..... .. .............. @ldstim14m size=2 307ld 010111 ..... ..... .. ...........10. @ldstim12m size=2 308 309# STB, STH, STW, STWM 310st 011000 ..... ..... .. .............. @ldstim14 size=0 311st 011001 ..... ..... .. .............. @ldstim14 size=1 312st 011010 ..... ..... .. .............. @ldstim14 size=2 313st 011011 ..... ..... .. .............. @ldstim14m size=2 314st 011111 ..... ..... .. ...........10. @ldstim12m size=2 315 316fldw 010110 b:5 ..... sp:2 .............. \ 317 &ldst disp=%assemble_12a t=%rm64 m=%a_to_m x=0 scale=0 size=2 318fldw 010111 b:5 ..... sp:2 ...........0.. \ 319 &ldst disp=%assemble_12a t=%rm64 m=0 x=0 scale=0 size=2 320 321fstw 011110 b:5 ..... sp:2 .............. \ 322 &ldst disp=%assemble_12a t=%rm64 m=%a_to_m x=0 scale=0 size=2 323fstw 011111 b:5 ..... sp:2 ...........0.. \ 324 &ldst disp=%assemble_12a t=%rm64 m=0 x=0 scale=0 size=2 325 326ld 010100 ..... ..... .. ............0. @ldstim11 327fldd 010100 ..... ..... .. ............1. @ldstim11 328 329st 011100 ..... ..... .. ............0. @ldstim11 330fstd 011100 ..... ..... .. ............1. @ldstim11 331 332#### 333# Floating-point Multiply Add 334#### 335 336&mpyadd rm1 rm2 ta ra tm 337@mpyadd ...... rm1:5 rm2:5 ta:5 ra:5 . tm:5 &mpyadd 338 339fmpyadd_f 000110 ..... ..... ..... ..... 0 ..... @mpyadd 340fmpyadd_d 000110 ..... ..... ..... ..... 1 ..... @mpyadd 341fmpysub_f 100110 ..... ..... ..... ..... 0 ..... @mpyadd 342fmpysub_d 100110 ..... ..... ..... ..... 1 ..... @mpyadd 343 344#### 345# Conditional Branches 346#### 347 348bb_sar 110000 00000 r:5 c:1 1 d:1 ........... n:1 . disp=%assemble_12 349bb_imm 110001 p:5 r:5 c:1 1 d:1 ........... n:1 . disp=%assemble_12 350 351movb 110010 ..... ..... ... ........... . . @rrb_cf f=0 352movbi 110011 ..... ..... ... ........... . . @rib_cf f=0 353 354cmpb 100000 ..... ..... ... ........... . . @rrb_cdf d=0 f=0 355cmpb 100010 ..... ..... ... ........... . . @rrb_cdf d=0 f=1 356cmpb 100111 ..... ..... ... ........... . . @rrb_cdf d=1 f=0 357cmpb 101111 ..... ..... ... ........... . . @rrb_cdf d=1 f=1 358cmpbi 100001 ..... ..... ... ........... . . @rib_cdf d=0 f=0 359cmpbi 100011 ..... ..... ... ........... . . @rib_cdf d=0 f=1 360cmpbi 111011 r:5 ..... f:1 .. ........... n:1 . \ 361 &rib_c_d_f d=1 disp=%assemble_12 c=%cmpbid_c i=%im5_16 362 363addb 101000 ..... ..... ... ........... . . @rrb_cf f=0 364addb 101010 ..... ..... ... ........... . . @rrb_cf f=1 365addbi 101001 ..... ..... ... ........... . . @rib_cf f=0 366addbi 101011 ..... ..... ... ........... . . @rib_cf f=1 367 368#### 369# Shift, Extract, Deposit 370#### 371 372shrp_sar 110100 r2:5 r1:5 c:3 00 0 d:1 0000 t:5 373shrp_imm 110100 r2:5 r1:5 c:3 01 0 cpos:5 t:5 d=0 374shrp_imm 110100 r2:5 r1:5 c:3 0. 1 ..... t:5 \ 375 d=1 cpos=%cpos6_11 376 377extr_sar 110100 r:5 t:5 c:3 10 se:1 00 000 ..... d=0 len=%len5 378extr_sar 110100 r:5 t:5 c:3 10 se:1 1. 000 ..... d=1 len=%len6_8 379extr_imm 110100 r:5 t:5 c:3 11 se:1 pos:5 ..... d=0 len=%len5 380extr_imm 110110 r:5 t:5 c:3 .. se:1 ..... ..... \ 381 d=1 len=%len6_12 pos=%cpos6_11 382 383dep_sar 110101 t:5 r:5 c:3 00 nz:1 00 000 ..... d=0 len=%len5 384dep_sar 110101 t:5 r:5 c:3 00 nz:1 1. 000 ..... d=1 len=%len6_8 385dep_imm 110101 t:5 r:5 c:3 01 nz:1 cpos:5 ..... d=0 len=%len5 386dep_imm 111100 t:5 r:5 c:3 .. nz:1 ..... ..... \ 387 d=1 len=%len6_12 cpos=%cpos6_11 388depi_sar 110101 t:5 ..... c:3 10 nz:1 d:1 . 000 ..... \ 389 i=%im5_16 len=%len6_8 390depi_imm 110101 t:5 ..... c:3 11 nz:1 cpos:5 ..... \ 391 d=0 i=%im5_16 len=%len5 392depi_imm 111101 t:5 ..... c:3 .. nz:1 ..... ..... \ 393 d=1 i=%im5_16 len=%len6_12 cpos=%cpos6_11 394 395#### 396# Branch External 397#### 398 399&BE b l n disp sp 400@be ...... b:5 ..... ... ........... n:1 . \ 401 &BE disp=%assemble_17 sp=%assemble_sr3 402 403be 111000 ..... ..... ... ........... . . @be l=0 404be 111001 ..... ..... ... ........... . . @be l=31 405 406#### 407# Branch 408#### 409 410&BL l n disp 411@bl ...... l:5 ..... ... ........... n:1 . &BL disp=%assemble_17 412 413# B,L and B,L,PUSH 414bl 111010 ..... ..... 000 ........... . . @bl 415bl 111010 ..... ..... 100 ........... . . @bl 416# B,L (long displacement) 417bl 111010 ..... ..... 101 ........... n:1 . &BL l=2 \ 418 disp=%assemble_22 419b_gate 111010 ..... ..... 001 ........... . . @bl 420blr 111010 l:5 x:5 010 00000000000 n:1 0 421nopbts 111010 00000 00000 010 0---------1 0 1 # clrbts/popbts 422nopbts 111010 00000 ----- 010 00000000000 0 1 # pushbts/pushnom 423bv 111010 b:5 x:5 110 00000000000 n:1 0 424bve 111010 b:5 00000 110 10000000000 n:1 - l=0 425bve 111010 b:5 00000 111 10000000000 n:1 - l=2 426 427#### 428# FP Fused Multiple-Add 429#### 430 431fmpyfadd_f 101110 ..... ..... ... . 0 ... . . neg:1 ..... \ 432 rm1=%ra64 rm2=%rb64 ra3=%rc64 t=%rt64 433fmpyfadd_d 101110 rm1:5 rm2:5 ... 0 1 ..0 0 0 neg:1 t:5 ra3=%rc32 434 435#### 436# FP operations 437#### 438 439&fclass01 r t 440&fclass2 r1 r2 c y 441&fclass3 r1 r2 t 442 443@f0c_0 ...... r:5 00000 ..... 00 000 0 t:5 &fclass01 444@f0c_1 ...... r:5 000.. ..... 01 000 0 t:5 &fclass01 445@f0c_2 ...... r1:5 r2:5 y:3 .. 10 000 . c:5 &fclass2 446@f0c_3 ...... r1:5 r2:5 ..... 11 000 0 t:5 &fclass3 447 448@f0e_f_0 ...... ..... 00000 ... 0 0 000 .. 0 ..... \ 449 &fclass01 r=%ra64 t=%rt64 450@f0e_d_0 ...... r:5 00000 ... 0 1 000 00 0 t:5 &fclass01 451 452@f0e_ff_1 ...... ..... 000 ... 0000 010 .. 0 ..... \ 453 &fclass01 r=%ra64 t=%rt64 454@f0e_fd_1 ...... ..... 000 ... 0100 010 .0 0 t:5 &fclass01 r=%ra64 455@f0e_df_1 ...... r:5 000 ... 0001 010 0. 0 ..... &fclass01 t=%rt64 456@f0e_dd_1 ...... r:5 000 ... 0101 010 00 0 t:5 &fclass01 457 458@f0e_f_2 ...... ..... ..... y:3 .0 100 .00 c:5 \ 459 &fclass2 r1=%ra64 r2=%rb64 460@f0e_d_2 ...... r1:5 r2:5 y:3 01 100 000 c:5 &fclass2 461 462@f0e_f_3 ...... ..... ..... ... .0 110 ..0 ..... \ 463 &fclass3 r1=%ra64 r2=%rb64 t=%rt64 464@f0e_d_3 ...... r1:5 r2:5 ... 01 110 000 t:5 &fclass3 465 466# Floating point class 0 467 468fid_f 001100 00000 00000 000 00 000000 00000 469 470fcpy_f 001100 ..... ..... 010 00 ...... ..... @f0c_0 471fabs_f 001100 ..... ..... 011 00 ...... ..... @f0c_0 472fsqrt_f 001100 ..... ..... 100 00 ...... ..... @f0c_0 473frnd_f 001100 ..... ..... 101 00 ...... ..... @f0c_0 474fneg_f 001100 ..... ..... 110 00 ...... ..... @f0c_0 475fnegabs_f 001100 ..... ..... 111 00 ...... ..... @f0c_0 476 477fcpy_d 001100 ..... ..... 010 01 ...... ..... @f0c_0 478fabs_d 001100 ..... ..... 011 01 ...... ..... @f0c_0 479fsqrt_d 001100 ..... ..... 100 01 ...... ..... @f0c_0 480frnd_d 001100 ..... ..... 101 01 ...... ..... @f0c_0 481fneg_d 001100 ..... ..... 110 01 ...... ..... @f0c_0 482fnegabs_d 001100 ..... ..... 111 01 ...... ..... @f0c_0 483 484fcpy_f 001110 ..... ..... 010 ........ ..... @f0e_f_0 485fabs_f 001110 ..... ..... 011 ........ ..... @f0e_f_0 486fsqrt_f 001110 ..... ..... 100 ........ ..... @f0e_f_0 487frnd_f 001110 ..... ..... 101 ........ ..... @f0e_f_0 488fneg_f 001110 ..... ..... 110 ........ ..... @f0e_f_0 489fnegabs_f 001110 ..... ..... 111 ........ ..... @f0e_f_0 490 491fcpy_d 001110 ..... ..... 010 ........ ..... @f0e_d_0 492fabs_d 001110 ..... ..... 011 ........ ..... @f0e_d_0 493fsqrt_d 001110 ..... ..... 100 ........ ..... @f0e_d_0 494frnd_d 001110 ..... ..... 101 ........ ..... @f0e_d_0 495fneg_d 001110 ..... ..... 110 ........ ..... @f0e_d_0 496fnegabs_d 001110 ..... ..... 111 ........ ..... @f0e_d_0 497 498# Floating point class 1 499 500# float/float 501fcnv_d_f 001100 ..... ... 000 00 01 ...... ..... @f0c_1 502fcnv_f_d 001100 ..... ... 000 01 00 ...... ..... @f0c_1 503 504fcnv_d_f 001110 ..... ... 000 .......... ..... @f0e_df_1 505fcnv_f_d 001110 ..... ... 000 .......... ..... @f0e_fd_1 506 507# int/float 508fcnv_w_f 001100 ..... ... 001 00 00 ...... ..... @f0c_1 509fcnv_q_f 001100 ..... ... 001 00 01 ...... ..... @f0c_1 510fcnv_w_d 001100 ..... ... 001 01 00 ...... ..... @f0c_1 511fcnv_q_d 001100 ..... ... 001 01 01 ...... ..... @f0c_1 512 513fcnv_w_f 001110 ..... ... 001 .......... ..... @f0e_ff_1 514fcnv_q_f 001110 ..... ... 001 .......... ..... @f0e_df_1 515fcnv_w_d 001110 ..... ... 001 .......... ..... @f0e_fd_1 516fcnv_q_d 001110 ..... ... 001 .......... ..... @f0e_dd_1 517 518# float/int 519fcnv_f_w 001100 ..... ... 010 00 00 ...... ..... @f0c_1 520fcnv_d_w 001100 ..... ... 010 00 01 ...... ..... @f0c_1 521fcnv_f_q 001100 ..... ... 010 01 00 ...... ..... @f0c_1 522fcnv_d_q 001100 ..... ... 010 01 01 ...... ..... @f0c_1 523 524fcnv_f_w 001110 ..... ... 010 .......... ..... @f0e_ff_1 525fcnv_d_w 001110 ..... ... 010 .......... ..... @f0e_df_1 526fcnv_f_q 001110 ..... ... 010 .......... ..... @f0e_fd_1 527fcnv_d_q 001110 ..... ... 010 .......... ..... @f0e_dd_1 528 529# float/int truncate 530fcnv_t_f_w 001100 ..... ... 011 00 00 ...... ..... @f0c_1 531fcnv_t_d_w 001100 ..... ... 011 00 01 ...... ..... @f0c_1 532fcnv_t_f_q 001100 ..... ... 011 01 00 ...... ..... @f0c_1 533fcnv_t_d_q 001100 ..... ... 011 01 01 ...... ..... @f0c_1 534 535fcnv_t_f_w 001110 ..... ... 011 .......... ..... @f0e_ff_1 536fcnv_t_d_w 001110 ..... ... 011 .......... ..... @f0e_df_1 537fcnv_t_f_q 001110 ..... ... 011 .......... ..... @f0e_fd_1 538fcnv_t_d_q 001110 ..... ... 011 .......... ..... @f0e_dd_1 539 540# uint/float 541fcnv_uw_f 001100 ..... ... 101 00 00 ...... ..... @f0c_1 542fcnv_uq_f 001100 ..... ... 101 00 01 ...... ..... @f0c_1 543fcnv_uw_d 001100 ..... ... 101 01 00 ...... ..... @f0c_1 544fcnv_uq_d 001100 ..... ... 101 01 01 ...... ..... @f0c_1 545 546fcnv_uw_f 001110 ..... ... 101 .......... ..... @f0e_ff_1 547fcnv_uq_f 001110 ..... ... 101 .......... ..... @f0e_df_1 548fcnv_uw_d 001110 ..... ... 101 .......... ..... @f0e_fd_1 549fcnv_uq_d 001110 ..... ... 101 .......... ..... @f0e_dd_1 550 551# float/int 552fcnv_f_uw 001100 ..... ... 110 00 00 ...... ..... @f0c_1 553fcnv_d_uw 001100 ..... ... 110 00 01 ...... ..... @f0c_1 554fcnv_f_uq 001100 ..... ... 110 01 00 ...... ..... @f0c_1 555fcnv_d_uq 001100 ..... ... 110 01 01 ...... ..... @f0c_1 556 557fcnv_f_uw 001110 ..... ... 110 .......... ..... @f0e_ff_1 558fcnv_d_uw 001110 ..... ... 110 .......... ..... @f0e_df_1 559fcnv_f_uq 001110 ..... ... 110 .......... ..... @f0e_fd_1 560fcnv_d_uq 001110 ..... ... 110 .......... ..... @f0e_dd_1 561 562# float/int truncate 563fcnv_t_f_uw 001100 ..... ... 111 00 00 ...... ..... @f0c_1 564fcnv_t_d_uw 001100 ..... ... 111 00 01 ...... ..... @f0c_1 565fcnv_t_f_uq 001100 ..... ... 111 01 00 ...... ..... @f0c_1 566fcnv_t_d_uq 001100 ..... ... 111 01 01 ...... ..... @f0c_1 567 568fcnv_t_f_uw 001110 ..... ... 111 .......... ..... @f0e_ff_1 569fcnv_t_d_uw 001110 ..... ... 111 .......... ..... @f0e_df_1 570fcnv_t_f_uq 001110 ..... ... 111 .......... ..... @f0e_fd_1 571fcnv_t_d_uq 001110 ..... ... 111 .......... ..... @f0e_dd_1 572 573# Floating point class 2 574 575ftest 001100 00000 00000 y:3 00 10000 1 c:5 576 577fcmp_f 001100 ..... ..... ... 00 ..... 0 ..... @f0c_2 578fcmp_d 001100 ..... ..... ... 01 ..... 0 ..... @f0c_2 579 580fcmp_f 001110 ..... ..... ... ..... ... ..... @f0e_f_2 581fcmp_d 001110 ..... ..... ... ..... ... ..... @f0e_d_2 582 583# Floating point class 3 584 585fadd_f 001100 ..... ..... 000 00 ...... ..... @f0c_3 586fsub_f 001100 ..... ..... 001 00 ...... ..... @f0c_3 587fmpy_f 001100 ..... ..... 010 00 ...... ..... @f0c_3 588fdiv_f 001100 ..... ..... 011 00 ...... ..... @f0c_3 589 590fadd_d 001100 ..... ..... 000 01 ...... ..... @f0c_3 591fsub_d 001100 ..... ..... 001 01 ...... ..... @f0c_3 592fmpy_d 001100 ..... ..... 010 01 ...... ..... @f0c_3 593fdiv_d 001100 ..... ..... 011 01 ...... ..... @f0c_3 594 595fadd_f 001110 ..... ..... 000 ..... ... ..... @f0e_f_3 596fsub_f 001110 ..... ..... 001 ..... ... ..... @f0e_f_3 597fmpy_f 001110 ..... ..... 010 ..... ... ..... @f0e_f_3 598fdiv_f 001110 ..... ..... 011 ..... ... ..... @f0e_f_3 599 600fadd_d 001110 ..... ..... 000 ..... ... ..... @f0e_d_3 601fsub_d 001110 ..... ..... 001 ..... ... ..... @f0e_d_3 602fmpy_d 001110 ..... ..... 010 ..... ... ..... @f0e_d_3 603fdiv_d 001110 ..... ..... 011 ..... ... ..... @f0e_d_3 604 605xmpyu 001110 ..... ..... 010 .0111 .00 t:5 r1=%ra64 r2=%rb64 606 607# diag 608diag 000101 i:26 609