xref: /qemu/target/hppa/op_helper.c (revision 5b76dd13) 
1 /*
2  * Helpers for HPPA instructions.
3  *
4  * Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #include "qemu/osdep.h"
21 #include "cpu.h"
22 #include "exec/exec-all.h"
23 #include "exec/helper-proto.h"
24 #include "exec/cpu_ldst.h"
25 #include "sysemu/sysemu.h"
26 #include "qemu/timer.h"
27 #include "fpu/softfloat.h"
28 
29 void QEMU_NORETURN HELPER(excp)(CPUHPPAState *env, int excp)
30 {
31     HPPACPU *cpu = hppa_env_get_cpu(env);
32     CPUState *cs = CPU(cpu);
33 
34     cs->exception_index = excp;
35     cpu_loop_exit(cs);
36 }
37 
38 void QEMU_NORETURN hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra)
39 {
40     HPPACPU *cpu = hppa_env_get_cpu(env);
41     CPUState *cs = CPU(cpu);
42 
43     cs->exception_index = excp;
44     cpu_loop_exit_restore(cs, ra);
45 }
46 
47 void HELPER(tsv)(CPUHPPAState *env, target_ureg cond)
48 {
49     if (unlikely((target_sreg)cond < 0)) {
50         hppa_dynamic_excp(env, EXCP_OVERFLOW, GETPC());
51     }
52 }
53 
54 void HELPER(tcond)(CPUHPPAState *env, target_ureg cond)
55 {
56     if (unlikely(cond)) {
57         hppa_dynamic_excp(env, EXCP_COND, GETPC());
58     }
59 }
60 
61 static void atomic_store_3(CPUHPPAState *env, target_ulong addr, uint32_t val,
62                            uint32_t mask, uintptr_t ra)
63 {
64 #ifdef CONFIG_USER_ONLY
65     uint32_t old, new, cmp;
66 
67     uint32_t *haddr = g2h(addr - 1);
68     old = *haddr;
69     while (1) {
70         new = (old & ~mask) | (val & mask);
71         cmp = atomic_cmpxchg(haddr, old, new);
72         if (cmp == old) {
73             return;
74         }
75         old = cmp;
76     }
77 #else
78     /* FIXME -- we can do better.  */
79     cpu_loop_exit_atomic(ENV_GET_CPU(env), ra);
80 #endif
81 }
82 
83 static void do_stby_b(CPUHPPAState *env, target_ulong addr, target_ureg val,
84                       bool parallel, uintptr_t ra)
85 {
86     switch (addr & 3) {
87     case 3:
88         cpu_stb_data_ra(env, addr, val, ra);
89         break;
90     case 2:
91         cpu_stw_data_ra(env, addr, val, ra);
92         break;
93     case 1:
94         /* The 3 byte store must appear atomic.  */
95         if (parallel) {
96             atomic_store_3(env, addr, val, 0x00ffffffu, ra);
97         } else {
98             cpu_stb_data_ra(env, addr, val >> 16, ra);
99             cpu_stw_data_ra(env, addr + 1, val, ra);
100         }
101         break;
102     default:
103         cpu_stl_data_ra(env, addr, val, ra);
104         break;
105     }
106 }
107 
108 void HELPER(stby_b)(CPUHPPAState *env, target_ulong addr, target_ureg val)
109 {
110     do_stby_b(env, addr, val, false, GETPC());
111 }
112 
113 void HELPER(stby_b_parallel)(CPUHPPAState *env, target_ulong addr,
114                              target_ureg val)
115 {
116     do_stby_b(env, addr, val, true, GETPC());
117 }
118 
119 static void do_stby_e(CPUHPPAState *env, target_ulong addr, target_ureg val,
120                       bool parallel, uintptr_t ra)
121 {
122     switch (addr & 3) {
123     case 3:
124         /* The 3 byte store must appear atomic.  */
125         if (parallel) {
126             atomic_store_3(env, addr - 3, val, 0xffffff00u, ra);
127         } else {
128             cpu_stw_data_ra(env, addr - 3, val >> 16, ra);
129             cpu_stb_data_ra(env, addr - 1, val >> 8, ra);
130         }
131         break;
132     case 2:
133         cpu_stw_data_ra(env, addr - 2, val >> 16, ra);
134         break;
135     case 1:
136         cpu_stb_data_ra(env, addr - 1, val >> 24, ra);
137         break;
138     default:
139         /* Nothing is stored, but protection is checked and the
140            cacheline is marked dirty.  */
141 #ifndef CONFIG_USER_ONLY
142         probe_write(env, addr, 0, cpu_mmu_index(env, 0), ra);
143 #endif
144         break;
145     }
146 }
147 
148 void HELPER(stby_e)(CPUHPPAState *env, target_ulong addr, target_ureg val)
149 {
150     do_stby_e(env, addr, val, false, GETPC());
151 }
152 
153 void HELPER(stby_e_parallel)(CPUHPPAState *env, target_ulong addr,
154                              target_ureg val)
155 {
156     do_stby_e(env, addr, val, true, GETPC());
157 }
158 
159 target_ureg HELPER(probe)(CPUHPPAState *env, target_ulong addr,
160                           uint32_t level, uint32_t want)
161 {
162 #ifdef CONFIG_USER_ONLY
163     return page_check_range(addr, 1, want);
164 #else
165     int prot, excp;
166     hwaddr phys;
167 
168     /* Fail if the requested privilege level is higher than current.  */
169     if (level < (env->iaoq_f & 3)) {
170         return 0;
171     }
172 
173     excp = hppa_get_physical_address(env, addr, level, 0, &phys, &prot);
174     if (excp >= 0) {
175         if (env->psw & PSW_Q) {
176             /* ??? Needs tweaking for hppa64.  */
177             env->cr[CR_IOR] = addr;
178             env->cr[CR_ISR] = addr >> 32;
179         }
180         if (excp == EXCP_DTLB_MISS) {
181             excp = EXCP_NA_DTLB_MISS;
182         }
183         hppa_dynamic_excp(env, excp, GETPC());
184     }
185     return (want & prot) != 0;
186 #endif
187 }
188 
189 void HELPER(loaded_fr0)(CPUHPPAState *env)
190 {
191     uint32_t shadow = env->fr[0] >> 32;
192     int rm, d;
193 
194     env->fr0_shadow = shadow;
195 
196     switch (extract32(shadow, 9, 2)) {
197     default:
198         rm = float_round_nearest_even;
199         break;
200     case 1:
201         rm = float_round_to_zero;
202         break;
203     case 2:
204         rm = float_round_up;
205         break;
206     case 3:
207         rm = float_round_down;
208         break;
209     }
210     set_float_rounding_mode(rm, &env->fp_status);
211 
212     d = extract32(shadow, 5, 1);
213     set_flush_to_zero(d, &env->fp_status);
214     set_flush_inputs_to_zero(d, &env->fp_status);
215 }
216 
217 void cpu_hppa_loaded_fr0(CPUHPPAState *env)
218 {
219     helper_loaded_fr0(env);
220 }
221 
222 #define CONVERT_BIT(X, SRC, DST)        \
223     ((SRC) > (DST)                      \
224      ? (X) / ((SRC) / (DST)) & (DST)    \
225      : ((X) & (SRC)) * ((DST) / (SRC)))
226 
227 static void update_fr0_op(CPUHPPAState *env, uintptr_t ra)
228 {
229     uint32_t soft_exp = get_float_exception_flags(&env->fp_status);
230     uint32_t hard_exp = 0;
231     uint32_t shadow = env->fr0_shadow;
232 
233     if (likely(soft_exp == 0)) {
234         env->fr[0] = (uint64_t)shadow << 32;
235         return;
236     }
237     set_float_exception_flags(0, &env->fp_status);
238 
239     hard_exp |= CONVERT_BIT(soft_exp, float_flag_inexact,   1u << 0);
240     hard_exp |= CONVERT_BIT(soft_exp, float_flag_underflow, 1u << 1);
241     hard_exp |= CONVERT_BIT(soft_exp, float_flag_overflow,  1u << 2);
242     hard_exp |= CONVERT_BIT(soft_exp, float_flag_divbyzero, 1u << 3);
243     hard_exp |= CONVERT_BIT(soft_exp, float_flag_invalid,   1u << 4);
244     shadow |= hard_exp << (32 - 5);
245     env->fr0_shadow = shadow;
246     env->fr[0] = (uint64_t)shadow << 32;
247 
248     if (hard_exp & shadow) {
249         hppa_dynamic_excp(env, EXCP_ASSIST, ra);
250     }
251 }
252 
253 float32 HELPER(fsqrt_s)(CPUHPPAState *env, float32 arg)
254 {
255     float32 ret = float32_sqrt(arg, &env->fp_status);
256     update_fr0_op(env, GETPC());
257     return ret;
258 }
259 
260 float32 HELPER(frnd_s)(CPUHPPAState *env, float32 arg)
261 {
262     float32 ret = float32_round_to_int(arg, &env->fp_status);
263     update_fr0_op(env, GETPC());
264     return ret;
265 }
266 
267 float32 HELPER(fadd_s)(CPUHPPAState *env, float32 a, float32 b)
268 {
269     float32 ret = float32_add(a, b, &env->fp_status);
270     update_fr0_op(env, GETPC());
271     return ret;
272 }
273 
274 float32 HELPER(fsub_s)(CPUHPPAState *env, float32 a, float32 b)
275 {
276     float32 ret = float32_sub(a, b, &env->fp_status);
277     update_fr0_op(env, GETPC());
278     return ret;
279 }
280 
281 float32 HELPER(fmpy_s)(CPUHPPAState *env, float32 a, float32 b)
282 {
283     float32 ret = float32_mul(a, b, &env->fp_status);
284     update_fr0_op(env, GETPC());
285     return ret;
286 }
287 
288 float32 HELPER(fdiv_s)(CPUHPPAState *env, float32 a, float32 b)
289 {
290     float32 ret = float32_div(a, b, &env->fp_status);
291     update_fr0_op(env, GETPC());
292     return ret;
293 }
294 
295 float64 HELPER(fsqrt_d)(CPUHPPAState *env, float64 arg)
296 {
297     float64 ret = float64_sqrt(arg, &env->fp_status);
298     update_fr0_op(env, GETPC());
299     return ret;
300 }
301 
302 float64 HELPER(frnd_d)(CPUHPPAState *env, float64 arg)
303 {
304     float64 ret = float64_round_to_int(arg, &env->fp_status);
305     update_fr0_op(env, GETPC());
306     return ret;
307 }
308 
309 float64 HELPER(fadd_d)(CPUHPPAState *env, float64 a, float64 b)
310 {
311     float64 ret = float64_add(a, b, &env->fp_status);
312     update_fr0_op(env, GETPC());
313     return ret;
314 }
315 
316 float64 HELPER(fsub_d)(CPUHPPAState *env, float64 a, float64 b)
317 {
318     float64 ret = float64_sub(a, b, &env->fp_status);
319     update_fr0_op(env, GETPC());
320     return ret;
321 }
322 
323 float64 HELPER(fmpy_d)(CPUHPPAState *env, float64 a, float64 b)
324 {
325     float64 ret = float64_mul(a, b, &env->fp_status);
326     update_fr0_op(env, GETPC());
327     return ret;
328 }
329 
330 float64 HELPER(fdiv_d)(CPUHPPAState *env, float64 a, float64 b)
331 {
332     float64 ret = float64_div(a, b, &env->fp_status);
333     update_fr0_op(env, GETPC());
334     return ret;
335 }
336 
337 float64 HELPER(fcnv_s_d)(CPUHPPAState *env, float32 arg)
338 {
339     float64 ret = float32_to_float64(arg, &env->fp_status);
340     update_fr0_op(env, GETPC());
341     return ret;
342 }
343 
344 float32 HELPER(fcnv_d_s)(CPUHPPAState *env, float64 arg)
345 {
346     float32 ret = float64_to_float32(arg, &env->fp_status);
347     update_fr0_op(env, GETPC());
348     return ret;
349 }
350 
351 float32 HELPER(fcnv_w_s)(CPUHPPAState *env, int32_t arg)
352 {
353     float32 ret = int32_to_float32(arg, &env->fp_status);
354     update_fr0_op(env, GETPC());
355     return ret;
356 }
357 
358 float32 HELPER(fcnv_dw_s)(CPUHPPAState *env, int64_t arg)
359 {
360     float32 ret = int64_to_float32(arg, &env->fp_status);
361     update_fr0_op(env, GETPC());
362     return ret;
363 }
364 
365 float64 HELPER(fcnv_w_d)(CPUHPPAState *env, int32_t arg)
366 {
367     float64 ret = int32_to_float64(arg, &env->fp_status);
368     update_fr0_op(env, GETPC());
369     return ret;
370 }
371 
372 float64 HELPER(fcnv_dw_d)(CPUHPPAState *env, int64_t arg)
373 {
374     float64 ret = int64_to_float64(arg, &env->fp_status);
375     update_fr0_op(env, GETPC());
376     return ret;
377 }
378 
379 int32_t HELPER(fcnv_s_w)(CPUHPPAState *env, float32 arg)
380 {
381     int32_t ret = float32_to_int32(arg, &env->fp_status);
382     update_fr0_op(env, GETPC());
383     return ret;
384 }
385 
386 int32_t HELPER(fcnv_d_w)(CPUHPPAState *env, float64 arg)
387 {
388     int32_t ret = float64_to_int32(arg, &env->fp_status);
389     update_fr0_op(env, GETPC());
390     return ret;
391 }
392 
393 int64_t HELPER(fcnv_s_dw)(CPUHPPAState *env, float32 arg)
394 {
395     int64_t ret = float32_to_int64(arg, &env->fp_status);
396     update_fr0_op(env, GETPC());
397     return ret;
398 }
399 
400 int64_t HELPER(fcnv_d_dw)(CPUHPPAState *env, float64 arg)
401 {
402     int64_t ret = float64_to_int64(arg, &env->fp_status);
403     update_fr0_op(env, GETPC());
404     return ret;
405 }
406 
407 int32_t HELPER(fcnv_t_s_w)(CPUHPPAState *env, float32 arg)
408 {
409     int32_t ret = float32_to_int32_round_to_zero(arg, &env->fp_status);
410     update_fr0_op(env, GETPC());
411     return ret;
412 }
413 
414 int32_t HELPER(fcnv_t_d_w)(CPUHPPAState *env, float64 arg)
415 {
416     int32_t ret = float64_to_int32_round_to_zero(arg, &env->fp_status);
417     update_fr0_op(env, GETPC());
418     return ret;
419 }
420 
421 int64_t HELPER(fcnv_t_s_dw)(CPUHPPAState *env, float32 arg)
422 {
423     int64_t ret = float32_to_int64_round_to_zero(arg, &env->fp_status);
424     update_fr0_op(env, GETPC());
425     return ret;
426 }
427 
428 int64_t HELPER(fcnv_t_d_dw)(CPUHPPAState *env, float64 arg)
429 {
430     int64_t ret = float64_to_int64_round_to_zero(arg, &env->fp_status);
431     update_fr0_op(env, GETPC());
432     return ret;
433 }
434 
435 float32 HELPER(fcnv_uw_s)(CPUHPPAState *env, uint32_t arg)
436 {
437     float32 ret = uint32_to_float32(arg, &env->fp_status);
438     update_fr0_op(env, GETPC());
439     return ret;
440 }
441 
442 float32 HELPER(fcnv_udw_s)(CPUHPPAState *env, uint64_t arg)
443 {
444     float32 ret = uint64_to_float32(arg, &env->fp_status);
445     update_fr0_op(env, GETPC());
446     return ret;
447 }
448 
449 float64 HELPER(fcnv_uw_d)(CPUHPPAState *env, uint32_t arg)
450 {
451     float64 ret = uint32_to_float64(arg, &env->fp_status);
452     update_fr0_op(env, GETPC());
453     return ret;
454 }
455 
456 float64 HELPER(fcnv_udw_d)(CPUHPPAState *env, uint64_t arg)
457 {
458     float64 ret = uint64_to_float64(arg, &env->fp_status);
459     update_fr0_op(env, GETPC());
460     return ret;
461 }
462 
463 uint32_t HELPER(fcnv_s_uw)(CPUHPPAState *env, float32 arg)
464 {
465     uint32_t ret = float32_to_uint32(arg, &env->fp_status);
466     update_fr0_op(env, GETPC());
467     return ret;
468 }
469 
470 uint32_t HELPER(fcnv_d_uw)(CPUHPPAState *env, float64 arg)
471 {
472     uint32_t ret = float64_to_uint32(arg, &env->fp_status);
473     update_fr0_op(env, GETPC());
474     return ret;
475 }
476 
477 uint64_t HELPER(fcnv_s_udw)(CPUHPPAState *env, float32 arg)
478 {
479     uint64_t ret = float32_to_uint64(arg, &env->fp_status);
480     update_fr0_op(env, GETPC());
481     return ret;
482 }
483 
484 uint64_t HELPER(fcnv_d_udw)(CPUHPPAState *env, float64 arg)
485 {
486     uint64_t ret = float64_to_uint64(arg, &env->fp_status);
487     update_fr0_op(env, GETPC());
488     return ret;
489 }
490 
491 uint32_t HELPER(fcnv_t_s_uw)(CPUHPPAState *env, float32 arg)
492 {
493     uint32_t ret = float32_to_uint32_round_to_zero(arg, &env->fp_status);
494     update_fr0_op(env, GETPC());
495     return ret;
496 }
497 
498 uint32_t HELPER(fcnv_t_d_uw)(CPUHPPAState *env, float64 arg)
499 {
500     uint32_t ret = float64_to_uint32_round_to_zero(arg, &env->fp_status);
501     update_fr0_op(env, GETPC());
502     return ret;
503 }
504 
505 uint64_t HELPER(fcnv_t_s_udw)(CPUHPPAState *env, float32 arg)
506 {
507     uint64_t ret = float32_to_uint64_round_to_zero(arg, &env->fp_status);
508     update_fr0_op(env, GETPC());
509     return ret;
510 }
511 
512 uint64_t HELPER(fcnv_t_d_udw)(CPUHPPAState *env, float64 arg)
513 {
514     uint64_t ret = float64_to_uint64_round_to_zero(arg, &env->fp_status);
515     update_fr0_op(env, GETPC());
516     return ret;
517 }
518 
519 static void update_fr0_cmp(CPUHPPAState *env, uint32_t y, uint32_t c, int r)
520 {
521     uint32_t shadow = env->fr0_shadow;
522 
523     switch (r) {
524     case float_relation_greater:
525         c = extract32(c, 4, 1);
526         break;
527     case float_relation_less:
528         c = extract32(c, 3, 1);
529         break;
530     case float_relation_equal:
531         c = extract32(c, 2, 1);
532         break;
533     case float_relation_unordered:
534         c = extract32(c, 1, 1);
535         break;
536     default:
537         g_assert_not_reached();
538     }
539 
540     if (y) {
541         /* targeted comparison */
542         /* set fpsr[ca[y - 1]] to current compare */
543         shadow = deposit32(shadow, 21 - (y - 1), 1, c);
544     } else {
545         /* queued comparison */
546         /* shift cq right by one place */
547         shadow = deposit32(shadow, 11, 10, extract32(shadow, 12, 10));
548         /* move fpsr[c] to fpsr[cq[0]] */
549         shadow = deposit32(shadow, 21, 1, extract32(shadow, 26, 1));
550         /* set fpsr[c] to current compare */
551         shadow = deposit32(shadow, 26, 1, c);
552     }
553 
554     env->fr0_shadow = shadow;
555     env->fr[0] = (uint64_t)shadow << 32;
556 }
557 
558 void HELPER(fcmp_s)(CPUHPPAState *env, float32 a, float32 b,
559                     uint32_t y, uint32_t c)
560 {
561     int r;
562     if (c & 1) {
563         r = float32_compare(a, b, &env->fp_status);
564     } else {
565         r = float32_compare_quiet(a, b, &env->fp_status);
566     }
567     update_fr0_op(env, GETPC());
568     update_fr0_cmp(env, y, c, r);
569 }
570 
571 void HELPER(fcmp_d)(CPUHPPAState *env, float64 a, float64 b,
572                     uint32_t y, uint32_t c)
573 {
574     int r;
575     if (c & 1) {
576         r = float64_compare(a, b, &env->fp_status);
577     } else {
578         r = float64_compare_quiet(a, b, &env->fp_status);
579     }
580     update_fr0_op(env, GETPC());
581     update_fr0_cmp(env, y, c, r);
582 }
583 
584 float32 HELPER(fmpyfadd_s)(CPUHPPAState *env, float32 a, float32 b, float32 c)
585 {
586     float32 ret = float32_muladd(a, b, c, 0, &env->fp_status);
587     update_fr0_op(env, GETPC());
588     return ret;
589 }
590 
591 float32 HELPER(fmpynfadd_s)(CPUHPPAState *env, float32 a, float32 b, float32 c)
592 {
593     float32 ret = float32_muladd(a, b, c, float_muladd_negate_product,
594                                  &env->fp_status);
595     update_fr0_op(env, GETPC());
596     return ret;
597 }
598 
599 float64 HELPER(fmpyfadd_d)(CPUHPPAState *env, float64 a, float64 b, float64 c)
600 {
601     float64 ret = float64_muladd(a, b, c, 0, &env->fp_status);
602     update_fr0_op(env, GETPC());
603     return ret;
604 }
605 
606 float64 HELPER(fmpynfadd_d)(CPUHPPAState *env, float64 a, float64 b, float64 c)
607 {
608     float64 ret = float64_muladd(a, b, c, float_muladd_negate_product,
609                                  &env->fp_status);
610     update_fr0_op(env, GETPC());
611     return ret;
612 }
613 
614 target_ureg HELPER(read_interval_timer)(void)
615 {
616 #ifdef CONFIG_USER_ONLY
617     /* In user-mode, QEMU_CLOCK_VIRTUAL doesn't exist.
618        Just pass through the host cpu clock ticks.  */
619     return cpu_get_host_ticks();
620 #else
621     /* In system mode we have access to a decent high-resolution clock.
622        In order to make OS-level time accounting work with the cr16,
623        present it with a well-timed clock fixed at 250MHz.  */
624     return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) >> 2;
625 #endif
626 }
627 
628 #ifndef CONFIG_USER_ONLY
629 void HELPER(write_interval_timer)(CPUHPPAState *env, target_ureg val)
630 {
631     HPPACPU *cpu = hppa_env_get_cpu(env);
632     uint64_t current = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
633     uint64_t timeout;
634 
635     /* Even in 64-bit mode, the comparator is always 32-bit.  But the
636        value we expose to the guest is 1/4 of the speed of the clock,
637        so moosh in 34 bits.  */
638     timeout = deposit64(current, 0, 34, (uint64_t)val << 2);
639 
640     /* If the mooshing puts the clock in the past, advance to next round.  */
641     if (timeout < current + 1000) {
642         timeout += 1ULL << 34;
643     }
644 
645     cpu->env.cr[CR_IT] = timeout;
646     timer_mod(cpu->alarm_timer, timeout);
647 }
648 
649 void HELPER(halt)(CPUHPPAState *env)
650 {
651     qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
652     helper_excp(env, EXCP_HLT);
653 }
654 
655 void HELPER(reset)(CPUHPPAState *env)
656 {
657     qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
658     helper_excp(env, EXCP_HLT);
659 }
660 
661 target_ureg HELPER(swap_system_mask)(CPUHPPAState *env, target_ureg nsm)
662 {
663     target_ulong psw = env->psw;
664     /*
665      * Setting the PSW Q bit to 1, if it was not already 1, is an
666      * undefined operation.
667      *
668      * However, HP-UX 10.20 does this with the SSM instruction.
669      * Tested this on HP9000/712 and HP9000/785/C3750 and both
670      * machines set the Q bit from 0 to 1 without an exception,
671      * so let this go without comment.
672      */
673     env->psw = (psw & ~PSW_SM) | (nsm & PSW_SM);
674     return psw & PSW_SM;
675 }
676 
677 void HELPER(rfi)(CPUHPPAState *env)
678 {
679     /* ??? On second reading this condition simply seems
680        to be undefined rather than a diagnosed trap.  */
681     if (env->psw & (PSW_I | PSW_R | PSW_Q)) {
682         helper_excp(env, EXCP_ILL);
683     }
684     env->iasq_f = (uint64_t)env->cr[CR_IIASQ] << 32;
685     env->iasq_b = (uint64_t)env->cr_back[0] << 32;
686     env->iaoq_f = env->cr[CR_IIAOQ];
687     env->iaoq_b = env->cr_back[1];
688     cpu_hppa_put_psw(env, env->cr[CR_IPSW]);
689 }
690 
691 void HELPER(rfi_r)(CPUHPPAState *env)
692 {
693     env->gr[1] = env->shadow[0];
694     env->gr[8] = env->shadow[1];
695     env->gr[9] = env->shadow[2];
696     env->gr[16] = env->shadow[3];
697     env->gr[17] = env->shadow[4];
698     env->gr[24] = env->shadow[5];
699     env->gr[25] = env->shadow[6];
700     helper_rfi(env);
701 }
702 #endif
703