1 /* 2 * i386 CPUID, CPU class, definitions, models 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 #include "qemu/cutils.h" 23 #include "qemu/qemu-print.h" 24 #include "cpu.h" 25 #include "tcg/helper-tcg.h" 26 #include "sysemu/reset.h" 27 #include "sysemu/hvf.h" 28 #include "kvm/kvm_i386.h" 29 #include "sev_i386.h" 30 #include "qapi/qapi-visit-machine.h" 31 #include "qapi/qmp/qerror.h" 32 #include "qapi/qapi-commands-machine-target.h" 33 #include "standard-headers/asm-x86/kvm_para.h" 34 #include "hw/qdev-properties.h" 35 #include "hw/i386/topology.h" 36 #ifndef CONFIG_USER_ONLY 37 #include "exec/address-spaces.h" 38 #include "hw/boards.h" 39 #include "hw/i386/sgx-epc.h" 40 #endif 41 42 #include "disas/capstone.h" 43 #include "cpu-internal.h" 44 45 /* Helpers for building CPUID[2] descriptors: */ 46 47 struct CPUID2CacheDescriptorInfo { 48 enum CacheType type; 49 int level; 50 int size; 51 int line_size; 52 int associativity; 53 }; 54 55 /* 56 * Known CPUID 2 cache descriptors. 57 * From Intel SDM Volume 2A, CPUID instruction 58 */ 59 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = { 60 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB, 61 .associativity = 4, .line_size = 32, }, 62 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB, 63 .associativity = 4, .line_size = 32, }, 64 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 65 .associativity = 4, .line_size = 64, }, 66 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 67 .associativity = 2, .line_size = 32, }, 68 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 69 .associativity = 4, .line_size = 32, }, 70 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 71 .associativity = 4, .line_size = 64, }, 72 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB, 73 .associativity = 6, .line_size = 64, }, 74 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 75 .associativity = 2, .line_size = 64, }, 76 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 77 .associativity = 8, .line_size = 64, }, 78 /* lines per sector is not supported cpuid2_cache_descriptor(), 79 * so descriptors 0x22, 0x23 are not included 80 */ 81 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 82 .associativity = 16, .line_size = 64, }, 83 /* lines per sector is not supported cpuid2_cache_descriptor(), 84 * so descriptors 0x25, 0x20 are not included 85 */ 86 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 87 .associativity = 8, .line_size = 64, }, 88 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 89 .associativity = 8, .line_size = 64, }, 90 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 91 .associativity = 4, .line_size = 32, }, 92 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 93 .associativity = 4, .line_size = 32, }, 94 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 95 .associativity = 4, .line_size = 32, }, 96 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 97 .associativity = 4, .line_size = 32, }, 98 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 99 .associativity = 4, .line_size = 32, }, 100 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 101 .associativity = 4, .line_size = 64, }, 102 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 103 .associativity = 8, .line_size = 64, }, 104 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB, 105 .associativity = 12, .line_size = 64, }, 106 /* Descriptor 0x49 depends on CPU family/model, so it is not included */ 107 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 108 .associativity = 12, .line_size = 64, }, 109 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 110 .associativity = 16, .line_size = 64, }, 111 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 112 .associativity = 12, .line_size = 64, }, 113 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB, 114 .associativity = 16, .line_size = 64, }, 115 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB, 116 .associativity = 24, .line_size = 64, }, 117 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 118 .associativity = 8, .line_size = 64, }, 119 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 120 .associativity = 4, .line_size = 64, }, 121 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 122 .associativity = 4, .line_size = 64, }, 123 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 124 .associativity = 4, .line_size = 64, }, 125 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 126 .associativity = 4, .line_size = 64, }, 127 /* lines per sector is not supported cpuid2_cache_descriptor(), 128 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included. 129 */ 130 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 131 .associativity = 8, .line_size = 64, }, 132 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 133 .associativity = 2, .line_size = 64, }, 134 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 135 .associativity = 8, .line_size = 64, }, 136 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 137 .associativity = 8, .line_size = 32, }, 138 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 139 .associativity = 8, .line_size = 32, }, 140 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 141 .associativity = 8, .line_size = 32, }, 142 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 143 .associativity = 8, .line_size = 32, }, 144 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 145 .associativity = 4, .line_size = 64, }, 146 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 147 .associativity = 8, .line_size = 64, }, 148 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB, 149 .associativity = 4, .line_size = 64, }, 150 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 151 .associativity = 4, .line_size = 64, }, 152 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 153 .associativity = 4, .line_size = 64, }, 154 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 155 .associativity = 8, .line_size = 64, }, 156 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 157 .associativity = 8, .line_size = 64, }, 158 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 159 .associativity = 8, .line_size = 64, }, 160 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB, 161 .associativity = 12, .line_size = 64, }, 162 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB, 163 .associativity = 12, .line_size = 64, }, 164 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 165 .associativity = 12, .line_size = 64, }, 166 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 167 .associativity = 16, .line_size = 64, }, 168 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 169 .associativity = 16, .line_size = 64, }, 170 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 171 .associativity = 16, .line_size = 64, }, 172 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 173 .associativity = 24, .line_size = 64, }, 174 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB, 175 .associativity = 24, .line_size = 64, }, 176 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB, 177 .associativity = 24, .line_size = 64, }, 178 }; 179 180 /* 181 * "CPUID leaf 2 does not report cache descriptor information, 182 * use CPUID leaf 4 to query cache parameters" 183 */ 184 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF 185 186 /* 187 * Return a CPUID 2 cache descriptor for a given cache. 188 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE 189 */ 190 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache) 191 { 192 int i; 193 194 assert(cache->size > 0); 195 assert(cache->level > 0); 196 assert(cache->line_size > 0); 197 assert(cache->associativity > 0); 198 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) { 199 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i]; 200 if (d->level == cache->level && d->type == cache->type && 201 d->size == cache->size && d->line_size == cache->line_size && 202 d->associativity == cache->associativity) { 203 return i; 204 } 205 } 206 207 return CACHE_DESCRIPTOR_UNAVAILABLE; 208 } 209 210 /* CPUID Leaf 4 constants: */ 211 212 /* EAX: */ 213 #define CACHE_TYPE_D 1 214 #define CACHE_TYPE_I 2 215 #define CACHE_TYPE_UNIFIED 3 216 217 #define CACHE_LEVEL(l) (l << 5) 218 219 #define CACHE_SELF_INIT_LEVEL (1 << 8) 220 221 /* EDX: */ 222 #define CACHE_NO_INVD_SHARING (1 << 0) 223 #define CACHE_INCLUSIVE (1 << 1) 224 #define CACHE_COMPLEX_IDX (1 << 2) 225 226 /* Encode CacheType for CPUID[4].EAX */ 227 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \ 228 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \ 229 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \ 230 0 /* Invalid value */) 231 232 233 /* Encode cache info for CPUID[4] */ 234 static void encode_cache_cpuid4(CPUCacheInfo *cache, 235 int num_apic_ids, int num_cores, 236 uint32_t *eax, uint32_t *ebx, 237 uint32_t *ecx, uint32_t *edx) 238 { 239 assert(cache->size == cache->line_size * cache->associativity * 240 cache->partitions * cache->sets); 241 242 assert(num_apic_ids > 0); 243 *eax = CACHE_TYPE(cache->type) | 244 CACHE_LEVEL(cache->level) | 245 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | 246 ((num_cores - 1) << 26) | 247 ((num_apic_ids - 1) << 14); 248 249 assert(cache->line_size > 0); 250 assert(cache->partitions > 0); 251 assert(cache->associativity > 0); 252 /* We don't implement fully-associative caches */ 253 assert(cache->associativity < cache->sets); 254 *ebx = (cache->line_size - 1) | 255 ((cache->partitions - 1) << 12) | 256 ((cache->associativity - 1) << 22); 257 258 assert(cache->sets > 0); 259 *ecx = cache->sets - 1; 260 261 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 262 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 263 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 264 } 265 266 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */ 267 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache) 268 { 269 assert(cache->size % 1024 == 0); 270 assert(cache->lines_per_tag > 0); 271 assert(cache->associativity > 0); 272 assert(cache->line_size > 0); 273 return ((cache->size / 1024) << 24) | (cache->associativity << 16) | 274 (cache->lines_per_tag << 8) | (cache->line_size); 275 } 276 277 #define ASSOC_FULL 0xFF 278 279 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */ 280 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \ 281 a == 2 ? 0x2 : \ 282 a == 4 ? 0x4 : \ 283 a == 8 ? 0x6 : \ 284 a == 16 ? 0x8 : \ 285 a == 32 ? 0xA : \ 286 a == 48 ? 0xB : \ 287 a == 64 ? 0xC : \ 288 a == 96 ? 0xD : \ 289 a == 128 ? 0xE : \ 290 a == ASSOC_FULL ? 0xF : \ 291 0 /* invalid value */) 292 293 /* 294 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX 295 * @l3 can be NULL. 296 */ 297 static void encode_cache_cpuid80000006(CPUCacheInfo *l2, 298 CPUCacheInfo *l3, 299 uint32_t *ecx, uint32_t *edx) 300 { 301 assert(l2->size % 1024 == 0); 302 assert(l2->associativity > 0); 303 assert(l2->lines_per_tag > 0); 304 assert(l2->line_size > 0); 305 *ecx = ((l2->size / 1024) << 16) | 306 (AMD_ENC_ASSOC(l2->associativity) << 12) | 307 (l2->lines_per_tag << 8) | (l2->line_size); 308 309 if (l3) { 310 assert(l3->size % (512 * 1024) == 0); 311 assert(l3->associativity > 0); 312 assert(l3->lines_per_tag > 0); 313 assert(l3->line_size > 0); 314 *edx = ((l3->size / (512 * 1024)) << 18) | 315 (AMD_ENC_ASSOC(l3->associativity) << 12) | 316 (l3->lines_per_tag << 8) | (l3->line_size); 317 } else { 318 *edx = 0; 319 } 320 } 321 322 /* Encode cache info for CPUID[8000001D] */ 323 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, 324 X86CPUTopoInfo *topo_info, 325 uint32_t *eax, uint32_t *ebx, 326 uint32_t *ecx, uint32_t *edx) 327 { 328 uint32_t l3_threads; 329 assert(cache->size == cache->line_size * cache->associativity * 330 cache->partitions * cache->sets); 331 332 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | 333 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); 334 335 /* L3 is shared among multiple cores */ 336 if (cache->level == 3) { 337 l3_threads = topo_info->cores_per_die * topo_info->threads_per_core; 338 *eax |= (l3_threads - 1) << 14; 339 } else { 340 *eax |= ((topo_info->threads_per_core - 1) << 14); 341 } 342 343 assert(cache->line_size > 0); 344 assert(cache->partitions > 0); 345 assert(cache->associativity > 0); 346 /* We don't implement fully-associative caches */ 347 assert(cache->associativity < cache->sets); 348 *ebx = (cache->line_size - 1) | 349 ((cache->partitions - 1) << 12) | 350 ((cache->associativity - 1) << 22); 351 352 assert(cache->sets > 0); 353 *ecx = cache->sets - 1; 354 355 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 356 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 357 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 358 } 359 360 /* Encode cache info for CPUID[8000001E] */ 361 static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info, 362 uint32_t *eax, uint32_t *ebx, 363 uint32_t *ecx, uint32_t *edx) 364 { 365 X86CPUTopoIDs topo_ids; 366 367 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids); 368 369 *eax = cpu->apic_id; 370 371 /* 372 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId) 373 * Read-only. Reset: 0000_XXXXh. 374 * See Core::X86::Cpuid::ExtApicId. 375 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0]; 376 * Bits Description 377 * 31:16 Reserved. 378 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh. 379 * The number of threads per core is ThreadsPerCore+1. 380 * 7:0 CoreId: core ID. Read-only. Reset: XXh. 381 * 382 * NOTE: CoreId is already part of apic_id. Just use it. We can 383 * use all the 8 bits to represent the core_id here. 384 */ 385 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF); 386 387 /* 388 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId) 389 * Read-only. Reset: 0000_0XXXh. 390 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0]; 391 * Bits Description 392 * 31:11 Reserved. 393 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb. 394 * ValidValues: 395 * Value Description 396 * 000b 1 node per processor. 397 * 001b 2 nodes per processor. 398 * 010b Reserved. 399 * 011b 4 nodes per processor. 400 * 111b-100b Reserved. 401 * 7:0 NodeId: Node ID. Read-only. Reset: XXh. 402 * 403 * NOTE: Hardware reserves 3 bits for number of nodes per processor. 404 * But users can create more nodes than the actual hardware can 405 * support. To genaralize we can use all the upper 8 bits for nodes. 406 * NodeId is combination of node and socket_id which is already decoded 407 * in apic_id. Just use it by shifting. 408 */ 409 *ecx = ((topo_info->dies_per_pkg - 1) << 8) | 410 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF); 411 412 *edx = 0; 413 } 414 415 /* 416 * Definitions of the hardcoded cache entries we expose: 417 * These are legacy cache values. If there is a need to change any 418 * of these values please use builtin_x86_defs 419 */ 420 421 /* L1 data cache: */ 422 static CPUCacheInfo legacy_l1d_cache = { 423 .type = DATA_CACHE, 424 .level = 1, 425 .size = 32 * KiB, 426 .self_init = 1, 427 .line_size = 64, 428 .associativity = 8, 429 .sets = 64, 430 .partitions = 1, 431 .no_invd_sharing = true, 432 }; 433 434 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 435 static CPUCacheInfo legacy_l1d_cache_amd = { 436 .type = DATA_CACHE, 437 .level = 1, 438 .size = 64 * KiB, 439 .self_init = 1, 440 .line_size = 64, 441 .associativity = 2, 442 .sets = 512, 443 .partitions = 1, 444 .lines_per_tag = 1, 445 .no_invd_sharing = true, 446 }; 447 448 /* L1 instruction cache: */ 449 static CPUCacheInfo legacy_l1i_cache = { 450 .type = INSTRUCTION_CACHE, 451 .level = 1, 452 .size = 32 * KiB, 453 .self_init = 1, 454 .line_size = 64, 455 .associativity = 8, 456 .sets = 64, 457 .partitions = 1, 458 .no_invd_sharing = true, 459 }; 460 461 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 462 static CPUCacheInfo legacy_l1i_cache_amd = { 463 .type = INSTRUCTION_CACHE, 464 .level = 1, 465 .size = 64 * KiB, 466 .self_init = 1, 467 .line_size = 64, 468 .associativity = 2, 469 .sets = 512, 470 .partitions = 1, 471 .lines_per_tag = 1, 472 .no_invd_sharing = true, 473 }; 474 475 /* Level 2 unified cache: */ 476 static CPUCacheInfo legacy_l2_cache = { 477 .type = UNIFIED_CACHE, 478 .level = 2, 479 .size = 4 * MiB, 480 .self_init = 1, 481 .line_size = 64, 482 .associativity = 16, 483 .sets = 4096, 484 .partitions = 1, 485 .no_invd_sharing = true, 486 }; 487 488 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ 489 static CPUCacheInfo legacy_l2_cache_cpuid2 = { 490 .type = UNIFIED_CACHE, 491 .level = 2, 492 .size = 2 * MiB, 493 .line_size = 64, 494 .associativity = 8, 495 }; 496 497 498 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */ 499 static CPUCacheInfo legacy_l2_cache_amd = { 500 .type = UNIFIED_CACHE, 501 .level = 2, 502 .size = 512 * KiB, 503 .line_size = 64, 504 .lines_per_tag = 1, 505 .associativity = 16, 506 .sets = 512, 507 .partitions = 1, 508 }; 509 510 /* Level 3 unified cache: */ 511 static CPUCacheInfo legacy_l3_cache = { 512 .type = UNIFIED_CACHE, 513 .level = 3, 514 .size = 16 * MiB, 515 .line_size = 64, 516 .associativity = 16, 517 .sets = 16384, 518 .partitions = 1, 519 .lines_per_tag = 1, 520 .self_init = true, 521 .inclusive = true, 522 .complex_indexing = true, 523 }; 524 525 /* TLB definitions: */ 526 527 #define L1_DTLB_2M_ASSOC 1 528 #define L1_DTLB_2M_ENTRIES 255 529 #define L1_DTLB_4K_ASSOC 1 530 #define L1_DTLB_4K_ENTRIES 255 531 532 #define L1_ITLB_2M_ASSOC 1 533 #define L1_ITLB_2M_ENTRIES 255 534 #define L1_ITLB_4K_ASSOC 1 535 #define L1_ITLB_4K_ENTRIES 255 536 537 #define L2_DTLB_2M_ASSOC 0 /* disabled */ 538 #define L2_DTLB_2M_ENTRIES 0 /* disabled */ 539 #define L2_DTLB_4K_ASSOC 4 540 #define L2_DTLB_4K_ENTRIES 512 541 542 #define L2_ITLB_2M_ASSOC 0 /* disabled */ 543 #define L2_ITLB_2M_ENTRIES 0 /* disabled */ 544 #define L2_ITLB_4K_ASSOC 4 545 #define L2_ITLB_4K_ENTRIES 512 546 547 /* CPUID Leaf 0x14 constants: */ 548 #define INTEL_PT_MAX_SUBLEAF 0x1 549 /* 550 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH 551 * MSR can be accessed; 552 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode; 553 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation 554 * of Intel PT MSRs across warm reset; 555 * bit[03]: Support MTC timing packet and suppression of COFI-based packets; 556 */ 557 #define INTEL_PT_MINIMAL_EBX 0xf 558 /* 559 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and 560 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be 561 * accessed; 562 * bit[01]: ToPA tables can hold any number of output entries, up to the 563 * maximum allowed by the MaskOrTableOffset field of 564 * IA32_RTIT_OUTPUT_MASK_PTRS; 565 * bit[02]: Support Single-Range Output scheme; 566 */ 567 #define INTEL_PT_MINIMAL_ECX 0x7 568 /* generated packets which contain IP payloads have LIP values */ 569 #define INTEL_PT_IP_LIP (1 << 31) 570 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */ 571 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3 572 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ 573 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ 574 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */ 575 576 void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, 577 uint32_t vendor2, uint32_t vendor3) 578 { 579 int i; 580 for (i = 0; i < 4; i++) { 581 dst[i] = vendor1 >> (8 * i); 582 dst[i + 4] = vendor2 >> (8 * i); 583 dst[i + 8] = vendor3 >> (8 * i); 584 } 585 dst[CPUID_VENDOR_SZ] = '\0'; 586 } 587 588 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) 589 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ 590 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) 591 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \ 592 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 593 CPUID_PSE36 | CPUID_FXSR) 594 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE) 595 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \ 596 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \ 597 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \ 598 CPUID_PAE | CPUID_SEP | CPUID_APIC) 599 600 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \ 601 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \ 602 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 603 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \ 604 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE) 605 /* partly implemented: 606 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */ 607 /* missing: 608 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */ 609 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \ 610 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \ 611 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \ 612 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \ 613 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \ 614 CPUID_EXT_RDRAND) 615 /* missing: 616 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX, 617 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA, 618 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA, 619 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX, 620 CPUID_EXT_F16C */ 621 622 #ifdef TARGET_X86_64 623 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM) 624 #else 625 #define TCG_EXT2_X86_64_FEATURES 0 626 #endif 627 628 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \ 629 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ 630 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \ 631 TCG_EXT2_X86_64_FEATURES) 632 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \ 633 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A) 634 #define TCG_EXT4_FEATURES 0 635 #define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \ 636 CPUID_SVM_SVME_ADDR_CHK) 637 #define TCG_KVM_FEATURES 0 638 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \ 639 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \ 640 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \ 641 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \ 642 CPUID_7_0_EBX_ERMS) 643 /* missing: 644 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2, 645 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM, 646 CPUID_7_0_EBX_RDSEED */ 647 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | \ 648 /* CPUID_7_0_ECX_OSPKE is dynamic */ \ 649 CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS) 650 #define TCG_7_0_EDX_FEATURES 0 651 #define TCG_7_1_EAX_FEATURES 0 652 #define TCG_APM_FEATURES 0 653 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT 654 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1) 655 /* missing: 656 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */ 657 #define TCG_14_0_ECX_FEATURES 0 658 #define TCG_SGX_12_0_EAX_FEATURES 0 659 #define TCG_SGX_12_0_EBX_FEATURES 0 660 #define TCG_SGX_12_1_EAX_FEATURES 0 661 662 FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 663 [FEAT_1_EDX] = { 664 .type = CPUID_FEATURE_WORD, 665 .feat_names = { 666 "fpu", "vme", "de", "pse", 667 "tsc", "msr", "pae", "mce", 668 "cx8", "apic", NULL, "sep", 669 "mtrr", "pge", "mca", "cmov", 670 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, 671 NULL, "ds" /* Intel dts */, "acpi", "mmx", 672 "fxsr", "sse", "sse2", "ss", 673 "ht" /* Intel htt */, "tm", "ia64", "pbe", 674 }, 675 .cpuid = {.eax = 1, .reg = R_EDX, }, 676 .tcg_features = TCG_FEATURES, 677 }, 678 [FEAT_1_ECX] = { 679 .type = CPUID_FEATURE_WORD, 680 .feat_names = { 681 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor", 682 "ds-cpl", "vmx", "smx", "est", 683 "tm2", "ssse3", "cid", NULL, 684 "fma", "cx16", "xtpr", "pdcm", 685 NULL, "pcid", "dca", "sse4.1", 686 "sse4.2", "x2apic", "movbe", "popcnt", 687 "tsc-deadline", "aes", "xsave", NULL /* osxsave */, 688 "avx", "f16c", "rdrand", "hypervisor", 689 }, 690 .cpuid = { .eax = 1, .reg = R_ECX, }, 691 .tcg_features = TCG_EXT_FEATURES, 692 }, 693 /* Feature names that are already defined on feature_name[] but 694 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their 695 * names on feat_names below. They are copied automatically 696 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD. 697 */ 698 [FEAT_8000_0001_EDX] = { 699 .type = CPUID_FEATURE_WORD, 700 .feat_names = { 701 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */, 702 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */, 703 NULL /* cx8 */, NULL /* apic */, NULL, "syscall", 704 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */, 705 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */, 706 "nx", NULL, "mmxext", NULL /* mmx */, 707 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp", 708 NULL, "lm", "3dnowext", "3dnow", 709 }, 710 .cpuid = { .eax = 0x80000001, .reg = R_EDX, }, 711 .tcg_features = TCG_EXT2_FEATURES, 712 }, 713 [FEAT_8000_0001_ECX] = { 714 .type = CPUID_FEATURE_WORD, 715 .feat_names = { 716 "lahf-lm", "cmp-legacy", "svm", "extapic", 717 "cr8legacy", "abm", "sse4a", "misalignsse", 718 "3dnowprefetch", "osvw", "ibs", "xop", 719 "skinit", "wdt", NULL, "lwp", 720 "fma4", "tce", NULL, "nodeid-msr", 721 NULL, "tbm", "topoext", "perfctr-core", 722 "perfctr-nb", NULL, NULL, NULL, 723 NULL, NULL, NULL, NULL, 724 }, 725 .cpuid = { .eax = 0x80000001, .reg = R_ECX, }, 726 .tcg_features = TCG_EXT3_FEATURES, 727 /* 728 * TOPOEXT is always allowed but can't be enabled blindly by 729 * "-cpu host", as it requires consistent cache topology info 730 * to be provided so it doesn't confuse guests. 731 */ 732 .no_autoenable_flags = CPUID_EXT3_TOPOEXT, 733 }, 734 [FEAT_C000_0001_EDX] = { 735 .type = CPUID_FEATURE_WORD, 736 .feat_names = { 737 NULL, NULL, "xstore", "xstore-en", 738 NULL, NULL, "xcrypt", "xcrypt-en", 739 "ace2", "ace2-en", "phe", "phe-en", 740 "pmm", "pmm-en", NULL, NULL, 741 NULL, NULL, NULL, NULL, 742 NULL, NULL, NULL, NULL, 743 NULL, NULL, NULL, NULL, 744 NULL, NULL, NULL, NULL, 745 }, 746 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, }, 747 .tcg_features = TCG_EXT4_FEATURES, 748 }, 749 [FEAT_KVM] = { 750 .type = CPUID_FEATURE_WORD, 751 .feat_names = { 752 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock", 753 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt", 754 NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi", 755 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id", 756 NULL, NULL, NULL, NULL, 757 NULL, NULL, NULL, NULL, 758 "kvmclock-stable-bit", NULL, NULL, NULL, 759 NULL, NULL, NULL, NULL, 760 }, 761 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, }, 762 .tcg_features = TCG_KVM_FEATURES, 763 }, 764 [FEAT_KVM_HINTS] = { 765 .type = CPUID_FEATURE_WORD, 766 .feat_names = { 767 "kvm-hint-dedicated", NULL, NULL, NULL, 768 NULL, NULL, NULL, NULL, 769 NULL, NULL, NULL, NULL, 770 NULL, NULL, NULL, NULL, 771 NULL, NULL, NULL, NULL, 772 NULL, NULL, NULL, NULL, 773 NULL, NULL, NULL, NULL, 774 NULL, NULL, NULL, NULL, 775 }, 776 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, }, 777 .tcg_features = TCG_KVM_FEATURES, 778 /* 779 * KVM hints aren't auto-enabled by -cpu host, they need to be 780 * explicitly enabled in the command-line. 781 */ 782 .no_autoenable_flags = ~0U, 783 }, 784 [FEAT_SVM] = { 785 .type = CPUID_FEATURE_WORD, 786 .feat_names = { 787 "npt", "lbrv", "svm-lock", "nrip-save", 788 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists", 789 NULL, NULL, "pause-filter", NULL, 790 "pfthreshold", "avic", NULL, "v-vmsave-vmload", 791 "vgif", NULL, NULL, NULL, 792 NULL, NULL, NULL, NULL, 793 NULL, NULL, NULL, NULL, 794 "svme-addr-chk", NULL, NULL, NULL, 795 }, 796 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, }, 797 .tcg_features = TCG_SVM_FEATURES, 798 }, 799 [FEAT_7_0_EBX] = { 800 .type = CPUID_FEATURE_WORD, 801 .feat_names = { 802 "fsgsbase", "tsc-adjust", "sgx", "bmi1", 803 "hle", "avx2", NULL, "smep", 804 "bmi2", "erms", "invpcid", "rtm", 805 NULL, NULL, "mpx", NULL, 806 "avx512f", "avx512dq", "rdseed", "adx", 807 "smap", "avx512ifma", "pcommit", "clflushopt", 808 "clwb", "intel-pt", "avx512pf", "avx512er", 809 "avx512cd", "sha-ni", "avx512bw", "avx512vl", 810 }, 811 .cpuid = { 812 .eax = 7, 813 .needs_ecx = true, .ecx = 0, 814 .reg = R_EBX, 815 }, 816 .tcg_features = TCG_7_0_EBX_FEATURES, 817 }, 818 [FEAT_7_0_ECX] = { 819 .type = CPUID_FEATURE_WORD, 820 .feat_names = { 821 NULL, "avx512vbmi", "umip", "pku", 822 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL, 823 "gfni", "vaes", "vpclmulqdq", "avx512vnni", 824 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, 825 "la57", NULL, NULL, NULL, 826 NULL, NULL, "rdpid", NULL, 827 "bus-lock-detect", "cldemote", NULL, "movdiri", 828 "movdir64b", NULL, "sgxlc", "pks", 829 }, 830 .cpuid = { 831 .eax = 7, 832 .needs_ecx = true, .ecx = 0, 833 .reg = R_ECX, 834 }, 835 .tcg_features = TCG_7_0_ECX_FEATURES, 836 }, 837 [FEAT_7_0_EDX] = { 838 .type = CPUID_FEATURE_WORD, 839 .feat_names = { 840 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", 841 "fsrm", NULL, NULL, NULL, 842 "avx512-vp2intersect", NULL, "md-clear", NULL, 843 NULL, NULL, "serialize", NULL, 844 "tsx-ldtrk", NULL, NULL /* pconfig */, NULL, 845 NULL, NULL, NULL, "avx512-fp16", 846 NULL, NULL, "spec-ctrl", "stibp", 847 NULL, "arch-capabilities", "core-capability", "ssbd", 848 }, 849 .cpuid = { 850 .eax = 7, 851 .needs_ecx = true, .ecx = 0, 852 .reg = R_EDX, 853 }, 854 .tcg_features = TCG_7_0_EDX_FEATURES, 855 }, 856 [FEAT_7_1_EAX] = { 857 .type = CPUID_FEATURE_WORD, 858 .feat_names = { 859 NULL, NULL, NULL, NULL, 860 "avx-vnni", "avx512-bf16", NULL, NULL, 861 NULL, NULL, NULL, NULL, 862 NULL, NULL, NULL, NULL, 863 NULL, NULL, NULL, NULL, 864 NULL, NULL, NULL, NULL, 865 NULL, NULL, NULL, NULL, 866 NULL, NULL, NULL, NULL, 867 }, 868 .cpuid = { 869 .eax = 7, 870 .needs_ecx = true, .ecx = 1, 871 .reg = R_EAX, 872 }, 873 .tcg_features = TCG_7_1_EAX_FEATURES, 874 }, 875 [FEAT_8000_0007_EDX] = { 876 .type = CPUID_FEATURE_WORD, 877 .feat_names = { 878 NULL, NULL, NULL, NULL, 879 NULL, NULL, NULL, NULL, 880 "invtsc", NULL, NULL, NULL, 881 NULL, NULL, NULL, NULL, 882 NULL, NULL, NULL, NULL, 883 NULL, NULL, NULL, NULL, 884 NULL, NULL, NULL, NULL, 885 NULL, NULL, NULL, NULL, 886 }, 887 .cpuid = { .eax = 0x80000007, .reg = R_EDX, }, 888 .tcg_features = TCG_APM_FEATURES, 889 .unmigratable_flags = CPUID_APM_INVTSC, 890 }, 891 [FEAT_8000_0008_EBX] = { 892 .type = CPUID_FEATURE_WORD, 893 .feat_names = { 894 "clzero", NULL, "xsaveerptr", NULL, 895 NULL, NULL, NULL, NULL, 896 NULL, "wbnoinvd", NULL, NULL, 897 "ibpb", NULL, "ibrs", "amd-stibp", 898 NULL, NULL, NULL, NULL, 899 NULL, NULL, NULL, NULL, 900 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL, 901 NULL, NULL, NULL, NULL, 902 }, 903 .cpuid = { .eax = 0x80000008, .reg = R_EBX, }, 904 .tcg_features = 0, 905 .unmigratable_flags = 0, 906 }, 907 [FEAT_XSAVE] = { 908 .type = CPUID_FEATURE_WORD, 909 .feat_names = { 910 "xsaveopt", "xsavec", "xgetbv1", "xsaves", 911 NULL, NULL, NULL, NULL, 912 NULL, NULL, NULL, NULL, 913 NULL, NULL, NULL, NULL, 914 NULL, NULL, NULL, NULL, 915 NULL, NULL, NULL, NULL, 916 NULL, NULL, NULL, NULL, 917 NULL, NULL, NULL, NULL, 918 }, 919 .cpuid = { 920 .eax = 0xd, 921 .needs_ecx = true, .ecx = 1, 922 .reg = R_EAX, 923 }, 924 .tcg_features = TCG_XSAVE_FEATURES, 925 }, 926 [FEAT_6_EAX] = { 927 .type = CPUID_FEATURE_WORD, 928 .feat_names = { 929 NULL, NULL, "arat", NULL, 930 NULL, NULL, NULL, NULL, 931 NULL, NULL, NULL, NULL, 932 NULL, NULL, NULL, NULL, 933 NULL, NULL, NULL, NULL, 934 NULL, NULL, NULL, NULL, 935 NULL, NULL, NULL, NULL, 936 NULL, NULL, NULL, NULL, 937 }, 938 .cpuid = { .eax = 6, .reg = R_EAX, }, 939 .tcg_features = TCG_6_EAX_FEATURES, 940 }, 941 [FEAT_XSAVE_COMP_LO] = { 942 .type = CPUID_FEATURE_WORD, 943 .cpuid = { 944 .eax = 0xD, 945 .needs_ecx = true, .ecx = 0, 946 .reg = R_EAX, 947 }, 948 .tcg_features = ~0U, 949 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK | 950 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 951 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK | 952 XSTATE_PKRU_MASK, 953 }, 954 [FEAT_XSAVE_COMP_HI] = { 955 .type = CPUID_FEATURE_WORD, 956 .cpuid = { 957 .eax = 0xD, 958 .needs_ecx = true, .ecx = 0, 959 .reg = R_EDX, 960 }, 961 .tcg_features = ~0U, 962 }, 963 /*Below are MSR exposed features*/ 964 [FEAT_ARCH_CAPABILITIES] = { 965 .type = MSR_FEATURE_WORD, 966 .feat_names = { 967 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry", 968 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl", 969 "taa-no", NULL, NULL, NULL, 970 NULL, NULL, NULL, NULL, 971 NULL, NULL, NULL, NULL, 972 NULL, NULL, NULL, NULL, 973 NULL, NULL, NULL, NULL, 974 NULL, NULL, NULL, NULL, 975 }, 976 .msr = { 977 .index = MSR_IA32_ARCH_CAPABILITIES, 978 }, 979 }, 980 [FEAT_CORE_CAPABILITY] = { 981 .type = MSR_FEATURE_WORD, 982 .feat_names = { 983 NULL, NULL, NULL, NULL, 984 NULL, "split-lock-detect", NULL, NULL, 985 NULL, NULL, NULL, NULL, 986 NULL, NULL, NULL, NULL, 987 NULL, NULL, NULL, NULL, 988 NULL, NULL, NULL, NULL, 989 NULL, NULL, NULL, NULL, 990 NULL, NULL, NULL, NULL, 991 }, 992 .msr = { 993 .index = MSR_IA32_CORE_CAPABILITY, 994 }, 995 }, 996 [FEAT_PERF_CAPABILITIES] = { 997 .type = MSR_FEATURE_WORD, 998 .feat_names = { 999 NULL, NULL, NULL, NULL, 1000 NULL, NULL, NULL, NULL, 1001 NULL, NULL, NULL, NULL, 1002 NULL, "full-width-write", NULL, NULL, 1003 NULL, NULL, NULL, NULL, 1004 NULL, NULL, NULL, NULL, 1005 NULL, NULL, NULL, NULL, 1006 NULL, NULL, NULL, NULL, 1007 }, 1008 .msr = { 1009 .index = MSR_IA32_PERF_CAPABILITIES, 1010 }, 1011 }, 1012 1013 [FEAT_VMX_PROCBASED_CTLS] = { 1014 .type = MSR_FEATURE_WORD, 1015 .feat_names = { 1016 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset", 1017 NULL, NULL, NULL, "vmx-hlt-exit", 1018 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit", 1019 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit", 1020 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit", 1021 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit", 1022 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf", 1023 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls", 1024 }, 1025 .msr = { 1026 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1027 } 1028 }, 1029 1030 [FEAT_VMX_SECONDARY_CTLS] = { 1031 .type = MSR_FEATURE_WORD, 1032 .feat_names = { 1033 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit", 1034 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest", 1035 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit", 1036 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit", 1037 "vmx-rdseed-exit", "vmx-pml", NULL, NULL, 1038 "vmx-xsaves", NULL, NULL, NULL, 1039 NULL, "vmx-tsc-scaling", NULL, NULL, 1040 NULL, NULL, NULL, NULL, 1041 }, 1042 .msr = { 1043 .index = MSR_IA32_VMX_PROCBASED_CTLS2, 1044 } 1045 }, 1046 1047 [FEAT_VMX_PINBASED_CTLS] = { 1048 .type = MSR_FEATURE_WORD, 1049 .feat_names = { 1050 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit", 1051 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr", 1052 NULL, NULL, NULL, NULL, 1053 NULL, NULL, NULL, NULL, 1054 NULL, NULL, NULL, NULL, 1055 NULL, NULL, NULL, NULL, 1056 NULL, NULL, NULL, NULL, 1057 NULL, NULL, NULL, NULL, 1058 }, 1059 .msr = { 1060 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1061 } 1062 }, 1063 1064 [FEAT_VMX_EXIT_CTLS] = { 1065 .type = MSR_FEATURE_WORD, 1066 /* 1067 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from 1068 * the LM CPUID bit. 1069 */ 1070 .feat_names = { 1071 NULL, NULL, "vmx-exit-nosave-debugctl", NULL, 1072 NULL, NULL, NULL, NULL, 1073 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL, 1074 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr", 1075 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat", 1076 "vmx-exit-save-efer", "vmx-exit-load-efer", 1077 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs", 1078 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL, 1079 NULL, "vmx-exit-load-pkrs", NULL, NULL, 1080 }, 1081 .msr = { 1082 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS, 1083 } 1084 }, 1085 1086 [FEAT_VMX_ENTRY_CTLS] = { 1087 .type = MSR_FEATURE_WORD, 1088 .feat_names = { 1089 NULL, NULL, "vmx-entry-noload-debugctl", NULL, 1090 NULL, NULL, NULL, NULL, 1091 NULL, "vmx-entry-ia32e-mode", NULL, NULL, 1092 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer", 1093 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL, 1094 NULL, NULL, "vmx-entry-load-pkrs", NULL, 1095 NULL, NULL, NULL, NULL, 1096 NULL, NULL, NULL, NULL, 1097 }, 1098 .msr = { 1099 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1100 } 1101 }, 1102 1103 [FEAT_VMX_MISC] = { 1104 .type = MSR_FEATURE_WORD, 1105 .feat_names = { 1106 NULL, NULL, NULL, NULL, 1107 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown", 1108 "vmx-activity-wait-sipi", NULL, NULL, NULL, 1109 NULL, NULL, NULL, NULL, 1110 NULL, NULL, NULL, NULL, 1111 NULL, NULL, NULL, NULL, 1112 NULL, NULL, NULL, NULL, 1113 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL, 1114 }, 1115 .msr = { 1116 .index = MSR_IA32_VMX_MISC, 1117 } 1118 }, 1119 1120 [FEAT_VMX_EPT_VPID_CAPS] = { 1121 .type = MSR_FEATURE_WORD, 1122 .feat_names = { 1123 "vmx-ept-execonly", NULL, NULL, NULL, 1124 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5", 1125 NULL, NULL, NULL, NULL, 1126 NULL, NULL, NULL, NULL, 1127 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL, 1128 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL, 1129 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL, 1130 NULL, NULL, NULL, NULL, 1131 "vmx-invvpid", NULL, NULL, NULL, 1132 NULL, NULL, NULL, NULL, 1133 "vmx-invvpid-single-addr", "vmx-invept-single-context", 1134 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals", 1135 NULL, NULL, NULL, NULL, 1136 NULL, NULL, NULL, NULL, 1137 NULL, NULL, NULL, NULL, 1138 NULL, NULL, NULL, NULL, 1139 NULL, NULL, NULL, NULL, 1140 }, 1141 .msr = { 1142 .index = MSR_IA32_VMX_EPT_VPID_CAP, 1143 } 1144 }, 1145 1146 [FEAT_VMX_BASIC] = { 1147 .type = MSR_FEATURE_WORD, 1148 .feat_names = { 1149 [54] = "vmx-ins-outs", 1150 [55] = "vmx-true-ctls", 1151 }, 1152 .msr = { 1153 .index = MSR_IA32_VMX_BASIC, 1154 }, 1155 /* Just to be safe - we don't support setting the MSEG version field. */ 1156 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR, 1157 }, 1158 1159 [FEAT_VMX_VMFUNC] = { 1160 .type = MSR_FEATURE_WORD, 1161 .feat_names = { 1162 [0] = "vmx-eptp-switching", 1163 }, 1164 .msr = { 1165 .index = MSR_IA32_VMX_VMFUNC, 1166 } 1167 }, 1168 1169 [FEAT_14_0_ECX] = { 1170 .type = CPUID_FEATURE_WORD, 1171 .feat_names = { 1172 NULL, NULL, NULL, NULL, 1173 NULL, NULL, NULL, NULL, 1174 NULL, NULL, NULL, NULL, 1175 NULL, NULL, NULL, NULL, 1176 NULL, NULL, NULL, NULL, 1177 NULL, NULL, NULL, NULL, 1178 NULL, NULL, NULL, NULL, 1179 NULL, NULL, NULL, "intel-pt-lip", 1180 }, 1181 .cpuid = { 1182 .eax = 0x14, 1183 .needs_ecx = true, .ecx = 0, 1184 .reg = R_ECX, 1185 }, 1186 .tcg_features = TCG_14_0_ECX_FEATURES, 1187 }, 1188 1189 [FEAT_SGX_12_0_EAX] = { 1190 .type = CPUID_FEATURE_WORD, 1191 .feat_names = { 1192 "sgx1", "sgx2", NULL, NULL, 1193 NULL, NULL, NULL, NULL, 1194 NULL, NULL, NULL, NULL, 1195 NULL, NULL, NULL, NULL, 1196 NULL, NULL, NULL, NULL, 1197 NULL, NULL, NULL, NULL, 1198 NULL, NULL, NULL, NULL, 1199 NULL, NULL, NULL, NULL, 1200 }, 1201 .cpuid = { 1202 .eax = 0x12, 1203 .needs_ecx = true, .ecx = 0, 1204 .reg = R_EAX, 1205 }, 1206 .tcg_features = TCG_SGX_12_0_EAX_FEATURES, 1207 }, 1208 1209 [FEAT_SGX_12_0_EBX] = { 1210 .type = CPUID_FEATURE_WORD, 1211 .feat_names = { 1212 "sgx-exinfo" , NULL, NULL, NULL, 1213 NULL, NULL, NULL, NULL, 1214 NULL, NULL, NULL, NULL, 1215 NULL, NULL, NULL, NULL, 1216 NULL, NULL, NULL, NULL, 1217 NULL, NULL, NULL, NULL, 1218 NULL, NULL, NULL, NULL, 1219 NULL, NULL, NULL, NULL, 1220 }, 1221 .cpuid = { 1222 .eax = 0x12, 1223 .needs_ecx = true, .ecx = 0, 1224 .reg = R_EBX, 1225 }, 1226 .tcg_features = TCG_SGX_12_0_EBX_FEATURES, 1227 }, 1228 1229 [FEAT_SGX_12_1_EAX] = { 1230 .type = CPUID_FEATURE_WORD, 1231 .feat_names = { 1232 NULL, "sgx-debug", "sgx-mode64", NULL, 1233 "sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss", 1234 NULL, NULL, NULL, NULL, 1235 NULL, NULL, NULL, NULL, 1236 NULL, NULL, NULL, NULL, 1237 NULL, NULL, NULL, NULL, 1238 NULL, NULL, NULL, NULL, 1239 NULL, NULL, NULL, NULL, 1240 }, 1241 .cpuid = { 1242 .eax = 0x12, 1243 .needs_ecx = true, .ecx = 1, 1244 .reg = R_EAX, 1245 }, 1246 .tcg_features = TCG_SGX_12_1_EAX_FEATURES, 1247 }, 1248 }; 1249 1250 typedef struct FeatureMask { 1251 FeatureWord index; 1252 uint64_t mask; 1253 } FeatureMask; 1254 1255 typedef struct FeatureDep { 1256 FeatureMask from, to; 1257 } FeatureDep; 1258 1259 static FeatureDep feature_dependencies[] = { 1260 { 1261 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES }, 1262 .to = { FEAT_ARCH_CAPABILITIES, ~0ull }, 1263 }, 1264 { 1265 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY }, 1266 .to = { FEAT_CORE_CAPABILITY, ~0ull }, 1267 }, 1268 { 1269 .from = { FEAT_1_ECX, CPUID_EXT_PDCM }, 1270 .to = { FEAT_PERF_CAPABILITIES, ~0ull }, 1271 }, 1272 { 1273 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1274 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull }, 1275 }, 1276 { 1277 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1278 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull }, 1279 }, 1280 { 1281 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1282 .to = { FEAT_VMX_EXIT_CTLS, ~0ull }, 1283 }, 1284 { 1285 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1286 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull }, 1287 }, 1288 { 1289 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1290 .to = { FEAT_VMX_MISC, ~0ull }, 1291 }, 1292 { 1293 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1294 .to = { FEAT_VMX_BASIC, ~0ull }, 1295 }, 1296 { 1297 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1298 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE }, 1299 }, 1300 { 1301 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS }, 1302 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull }, 1303 }, 1304 { 1305 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES }, 1306 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES }, 1307 }, 1308 { 1309 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND }, 1310 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING }, 1311 }, 1312 { 1313 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID }, 1314 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID }, 1315 }, 1316 { 1317 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED }, 1318 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING }, 1319 }, 1320 { 1321 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, 1322 .to = { FEAT_14_0_ECX, ~0ull }, 1323 }, 1324 { 1325 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP }, 1326 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP }, 1327 }, 1328 { 1329 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1330 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull }, 1331 }, 1332 { 1333 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1334 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST }, 1335 }, 1336 { 1337 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID }, 1338 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 }, 1339 }, 1340 { 1341 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC }, 1342 .to = { FEAT_VMX_VMFUNC, ~0ull }, 1343 }, 1344 { 1345 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM }, 1346 .to = { FEAT_SVM, ~0ull }, 1347 }, 1348 }; 1349 1350 typedef struct X86RegisterInfo32 { 1351 /* Name of register */ 1352 const char *name; 1353 /* QAPI enum value register */ 1354 X86CPURegister32 qapi_enum; 1355 } X86RegisterInfo32; 1356 1357 #define REGISTER(reg) \ 1358 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg } 1359 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = { 1360 REGISTER(EAX), 1361 REGISTER(ECX), 1362 REGISTER(EDX), 1363 REGISTER(EBX), 1364 REGISTER(ESP), 1365 REGISTER(EBP), 1366 REGISTER(ESI), 1367 REGISTER(EDI), 1368 }; 1369 #undef REGISTER 1370 1371 ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = { 1372 [XSTATE_FP_BIT] = { 1373 /* x87 FP state component is always enabled if XSAVE is supported */ 1374 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1375 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1376 }, 1377 [XSTATE_SSE_BIT] = { 1378 /* SSE state component is always enabled if XSAVE is supported */ 1379 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1380 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1381 }, 1382 [XSTATE_YMM_BIT] = 1383 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX, 1384 .size = sizeof(XSaveAVX) }, 1385 [XSTATE_BNDREGS_BIT] = 1386 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1387 .size = sizeof(XSaveBNDREG) }, 1388 [XSTATE_BNDCSR_BIT] = 1389 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1390 .size = sizeof(XSaveBNDCSR) }, 1391 [XSTATE_OPMASK_BIT] = 1392 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1393 .size = sizeof(XSaveOpmask) }, 1394 [XSTATE_ZMM_Hi256_BIT] = 1395 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1396 .size = sizeof(XSaveZMM_Hi256) }, 1397 [XSTATE_Hi16_ZMM_BIT] = 1398 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1399 .size = sizeof(XSaveHi16_ZMM) }, 1400 [XSTATE_PKRU_BIT] = 1401 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU, 1402 .size = sizeof(XSavePKRU) }, 1403 }; 1404 1405 static uint32_t xsave_area_size(uint64_t mask) 1406 { 1407 int i; 1408 uint64_t ret = 0; 1409 1410 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 1411 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 1412 if ((mask >> i) & 1) { 1413 ret = MAX(ret, esa->offset + esa->size); 1414 } 1415 } 1416 return ret; 1417 } 1418 1419 static inline bool accel_uses_host_cpuid(void) 1420 { 1421 return kvm_enabled() || hvf_enabled(); 1422 } 1423 1424 static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu) 1425 { 1426 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 | 1427 cpu->env.features[FEAT_XSAVE_COMP_LO]; 1428 } 1429 1430 /* Return name of 32-bit register, from a R_* constant */ 1431 static const char *get_register_name_32(unsigned int reg) 1432 { 1433 if (reg >= CPU_NB_REGS32) { 1434 return NULL; 1435 } 1436 return x86_reg_info_32[reg].name; 1437 } 1438 1439 /* 1440 * Returns the set of feature flags that are supported and migratable by 1441 * QEMU, for a given FeatureWord. 1442 */ 1443 static uint64_t x86_cpu_get_migratable_flags(FeatureWord w) 1444 { 1445 FeatureWordInfo *wi = &feature_word_info[w]; 1446 uint64_t r = 0; 1447 int i; 1448 1449 for (i = 0; i < 64; i++) { 1450 uint64_t f = 1ULL << i; 1451 1452 /* If the feature name is known, it is implicitly considered migratable, 1453 * unless it is explicitly set in unmigratable_flags */ 1454 if ((wi->migratable_flags & f) || 1455 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) { 1456 r |= f; 1457 } 1458 } 1459 return r; 1460 } 1461 1462 void host_cpuid(uint32_t function, uint32_t count, 1463 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) 1464 { 1465 uint32_t vec[4]; 1466 1467 #ifdef __x86_64__ 1468 asm volatile("cpuid" 1469 : "=a"(vec[0]), "=b"(vec[1]), 1470 "=c"(vec[2]), "=d"(vec[3]) 1471 : "0"(function), "c"(count) : "cc"); 1472 #elif defined(__i386__) 1473 asm volatile("pusha \n\t" 1474 "cpuid \n\t" 1475 "mov %%eax, 0(%2) \n\t" 1476 "mov %%ebx, 4(%2) \n\t" 1477 "mov %%ecx, 8(%2) \n\t" 1478 "mov %%edx, 12(%2) \n\t" 1479 "popa" 1480 : : "a"(function), "c"(count), "S"(vec) 1481 : "memory", "cc"); 1482 #else 1483 abort(); 1484 #endif 1485 1486 if (eax) 1487 *eax = vec[0]; 1488 if (ebx) 1489 *ebx = vec[1]; 1490 if (ecx) 1491 *ecx = vec[2]; 1492 if (edx) 1493 *edx = vec[3]; 1494 } 1495 1496 /* CPU class name definitions: */ 1497 1498 /* Return type name for a given CPU model name 1499 * Caller is responsible for freeing the returned string. 1500 */ 1501 static char *x86_cpu_type_name(const char *model_name) 1502 { 1503 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name); 1504 } 1505 1506 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model) 1507 { 1508 g_autofree char *typename = x86_cpu_type_name(cpu_model); 1509 return object_class_by_name(typename); 1510 } 1511 1512 static char *x86_cpu_class_get_model_name(X86CPUClass *cc) 1513 { 1514 const char *class_name = object_class_get_name(OBJECT_CLASS(cc)); 1515 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX)); 1516 return g_strndup(class_name, 1517 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX)); 1518 } 1519 1520 typedef struct X86CPUVersionDefinition { 1521 X86CPUVersion version; 1522 const char *alias; 1523 const char *note; 1524 PropValue *props; 1525 } X86CPUVersionDefinition; 1526 1527 /* Base definition for a CPU model */ 1528 typedef struct X86CPUDefinition { 1529 const char *name; 1530 uint32_t level; 1531 uint32_t xlevel; 1532 /* vendor is zero-terminated, 12 character ASCII string */ 1533 char vendor[CPUID_VENDOR_SZ + 1]; 1534 int family; 1535 int model; 1536 int stepping; 1537 FeatureWordArray features; 1538 const char *model_id; 1539 const CPUCaches *const cache_info; 1540 /* 1541 * Definitions for alternative versions of CPU model. 1542 * List is terminated by item with version == 0. 1543 * If NULL, version 1 will be registered automatically. 1544 */ 1545 const X86CPUVersionDefinition *versions; 1546 const char *deprecation_note; 1547 } X86CPUDefinition; 1548 1549 /* Reference to a specific CPU model version */ 1550 struct X86CPUModel { 1551 /* Base CPU definition */ 1552 const X86CPUDefinition *cpudef; 1553 /* CPU model version */ 1554 X86CPUVersion version; 1555 const char *note; 1556 /* 1557 * If true, this is an alias CPU model. 1558 * This matters only for "-cpu help" and query-cpu-definitions 1559 */ 1560 bool is_alias; 1561 }; 1562 1563 /* Get full model name for CPU version */ 1564 static char *x86_cpu_versioned_model_name(const X86CPUDefinition *cpudef, 1565 X86CPUVersion version) 1566 { 1567 assert(version > 0); 1568 return g_strdup_printf("%s-v%d", cpudef->name, (int)version); 1569 } 1570 1571 static const X86CPUVersionDefinition * 1572 x86_cpu_def_get_versions(const X86CPUDefinition *def) 1573 { 1574 /* When X86CPUDefinition::versions is NULL, we register only v1 */ 1575 static const X86CPUVersionDefinition default_version_list[] = { 1576 { 1 }, 1577 { /* end of list */ } 1578 }; 1579 1580 return def->versions ?: default_version_list; 1581 } 1582 1583 static const CPUCaches epyc_cache_info = { 1584 .l1d_cache = &(CPUCacheInfo) { 1585 .type = DATA_CACHE, 1586 .level = 1, 1587 .size = 32 * KiB, 1588 .line_size = 64, 1589 .associativity = 8, 1590 .partitions = 1, 1591 .sets = 64, 1592 .lines_per_tag = 1, 1593 .self_init = 1, 1594 .no_invd_sharing = true, 1595 }, 1596 .l1i_cache = &(CPUCacheInfo) { 1597 .type = INSTRUCTION_CACHE, 1598 .level = 1, 1599 .size = 64 * KiB, 1600 .line_size = 64, 1601 .associativity = 4, 1602 .partitions = 1, 1603 .sets = 256, 1604 .lines_per_tag = 1, 1605 .self_init = 1, 1606 .no_invd_sharing = true, 1607 }, 1608 .l2_cache = &(CPUCacheInfo) { 1609 .type = UNIFIED_CACHE, 1610 .level = 2, 1611 .size = 512 * KiB, 1612 .line_size = 64, 1613 .associativity = 8, 1614 .partitions = 1, 1615 .sets = 1024, 1616 .lines_per_tag = 1, 1617 }, 1618 .l3_cache = &(CPUCacheInfo) { 1619 .type = UNIFIED_CACHE, 1620 .level = 3, 1621 .size = 8 * MiB, 1622 .line_size = 64, 1623 .associativity = 16, 1624 .partitions = 1, 1625 .sets = 8192, 1626 .lines_per_tag = 1, 1627 .self_init = true, 1628 .inclusive = true, 1629 .complex_indexing = true, 1630 }, 1631 }; 1632 1633 static const CPUCaches epyc_rome_cache_info = { 1634 .l1d_cache = &(CPUCacheInfo) { 1635 .type = DATA_CACHE, 1636 .level = 1, 1637 .size = 32 * KiB, 1638 .line_size = 64, 1639 .associativity = 8, 1640 .partitions = 1, 1641 .sets = 64, 1642 .lines_per_tag = 1, 1643 .self_init = 1, 1644 .no_invd_sharing = true, 1645 }, 1646 .l1i_cache = &(CPUCacheInfo) { 1647 .type = INSTRUCTION_CACHE, 1648 .level = 1, 1649 .size = 32 * KiB, 1650 .line_size = 64, 1651 .associativity = 8, 1652 .partitions = 1, 1653 .sets = 64, 1654 .lines_per_tag = 1, 1655 .self_init = 1, 1656 .no_invd_sharing = true, 1657 }, 1658 .l2_cache = &(CPUCacheInfo) { 1659 .type = UNIFIED_CACHE, 1660 .level = 2, 1661 .size = 512 * KiB, 1662 .line_size = 64, 1663 .associativity = 8, 1664 .partitions = 1, 1665 .sets = 1024, 1666 .lines_per_tag = 1, 1667 }, 1668 .l3_cache = &(CPUCacheInfo) { 1669 .type = UNIFIED_CACHE, 1670 .level = 3, 1671 .size = 16 * MiB, 1672 .line_size = 64, 1673 .associativity = 16, 1674 .partitions = 1, 1675 .sets = 16384, 1676 .lines_per_tag = 1, 1677 .self_init = true, 1678 .inclusive = true, 1679 .complex_indexing = true, 1680 }, 1681 }; 1682 1683 static const CPUCaches epyc_milan_cache_info = { 1684 .l1d_cache = &(CPUCacheInfo) { 1685 .type = DATA_CACHE, 1686 .level = 1, 1687 .size = 32 * KiB, 1688 .line_size = 64, 1689 .associativity = 8, 1690 .partitions = 1, 1691 .sets = 64, 1692 .lines_per_tag = 1, 1693 .self_init = 1, 1694 .no_invd_sharing = true, 1695 }, 1696 .l1i_cache = &(CPUCacheInfo) { 1697 .type = INSTRUCTION_CACHE, 1698 .level = 1, 1699 .size = 32 * KiB, 1700 .line_size = 64, 1701 .associativity = 8, 1702 .partitions = 1, 1703 .sets = 64, 1704 .lines_per_tag = 1, 1705 .self_init = 1, 1706 .no_invd_sharing = true, 1707 }, 1708 .l2_cache = &(CPUCacheInfo) { 1709 .type = UNIFIED_CACHE, 1710 .level = 2, 1711 .size = 512 * KiB, 1712 .line_size = 64, 1713 .associativity = 8, 1714 .partitions = 1, 1715 .sets = 1024, 1716 .lines_per_tag = 1, 1717 }, 1718 .l3_cache = &(CPUCacheInfo) { 1719 .type = UNIFIED_CACHE, 1720 .level = 3, 1721 .size = 32 * MiB, 1722 .line_size = 64, 1723 .associativity = 16, 1724 .partitions = 1, 1725 .sets = 32768, 1726 .lines_per_tag = 1, 1727 .self_init = true, 1728 .inclusive = true, 1729 .complex_indexing = true, 1730 }, 1731 }; 1732 1733 /* The following VMX features are not supported by KVM and are left out in the 1734 * CPU definitions: 1735 * 1736 * Dual-monitor support (all processors) 1737 * Entry to SMM 1738 * Deactivate dual-monitor treatment 1739 * Number of CR3-target values 1740 * Shutdown activity state 1741 * Wait-for-SIPI activity state 1742 * PAUSE-loop exiting (Westmere and newer) 1743 * EPT-violation #VE (Broadwell and newer) 1744 * Inject event with insn length=0 (Skylake and newer) 1745 * Conceal non-root operation from PT 1746 * Conceal VM exits from PT 1747 * Conceal VM entries from PT 1748 * Enable ENCLS exiting 1749 * Mode-based execute control (XS/XU) 1750 s TSC scaling (Skylake Server and newer) 1751 * GPA translation for PT (IceLake and newer) 1752 * User wait and pause 1753 * ENCLV exiting 1754 * Load IA32_RTIT_CTL 1755 * Clear IA32_RTIT_CTL 1756 * Advanced VM-exit information for EPT violations 1757 * Sub-page write permissions 1758 * PT in VMX operation 1759 */ 1760 1761 static const X86CPUDefinition builtin_x86_defs[] = { 1762 { 1763 .name = "qemu64", 1764 .level = 0xd, 1765 .vendor = CPUID_VENDOR_AMD, 1766 .family = 15, 1767 .model = 107, 1768 .stepping = 1, 1769 .features[FEAT_1_EDX] = 1770 PPRO_FEATURES | 1771 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 1772 CPUID_PSE36, 1773 .features[FEAT_1_ECX] = 1774 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 1775 .features[FEAT_8000_0001_EDX] = 1776 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 1777 .features[FEAT_8000_0001_ECX] = 1778 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM, 1779 .xlevel = 0x8000000A, 1780 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 1781 }, 1782 { 1783 .name = "phenom", 1784 .level = 5, 1785 .vendor = CPUID_VENDOR_AMD, 1786 .family = 16, 1787 .model = 2, 1788 .stepping = 3, 1789 /* Missing: CPUID_HT */ 1790 .features[FEAT_1_EDX] = 1791 PPRO_FEATURES | 1792 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 1793 CPUID_PSE36 | CPUID_VME, 1794 .features[FEAT_1_ECX] = 1795 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | 1796 CPUID_EXT_POPCNT, 1797 .features[FEAT_8000_0001_EDX] = 1798 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | 1799 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | 1800 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, 1801 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 1802 CPUID_EXT3_CR8LEG, 1803 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 1804 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ 1805 .features[FEAT_8000_0001_ECX] = 1806 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | 1807 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, 1808 /* Missing: CPUID_SVM_LBRV */ 1809 .features[FEAT_SVM] = 1810 CPUID_SVM_NPT, 1811 .xlevel = 0x8000001A, 1812 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor" 1813 }, 1814 { 1815 .name = "core2duo", 1816 .level = 10, 1817 .vendor = CPUID_VENDOR_INTEL, 1818 .family = 6, 1819 .model = 15, 1820 .stepping = 11, 1821 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 1822 .features[FEAT_1_EDX] = 1823 PPRO_FEATURES | 1824 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 1825 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS, 1826 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST, 1827 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */ 1828 .features[FEAT_1_ECX] = 1829 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 1830 CPUID_EXT_CX16, 1831 .features[FEAT_8000_0001_EDX] = 1832 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 1833 .features[FEAT_8000_0001_ECX] = 1834 CPUID_EXT3_LAHF_LM, 1835 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 1836 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 1837 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 1838 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 1839 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 1840 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 1841 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 1842 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 1843 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 1844 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 1845 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 1846 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 1847 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 1848 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 1849 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 1850 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 1851 .features[FEAT_VMX_SECONDARY_CTLS] = 1852 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 1853 .xlevel = 0x80000008, 1854 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", 1855 }, 1856 { 1857 .name = "kvm64", 1858 .level = 0xd, 1859 .vendor = CPUID_VENDOR_INTEL, 1860 .family = 15, 1861 .model = 6, 1862 .stepping = 1, 1863 /* Missing: CPUID_HT */ 1864 .features[FEAT_1_EDX] = 1865 PPRO_FEATURES | CPUID_VME | 1866 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 1867 CPUID_PSE36, 1868 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ 1869 .features[FEAT_1_ECX] = 1870 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 1871 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ 1872 .features[FEAT_8000_0001_EDX] = 1873 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 1874 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 1875 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A, 1876 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 1877 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */ 1878 .features[FEAT_8000_0001_ECX] = 1879 0, 1880 /* VMX features from Cedar Mill/Prescott */ 1881 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 1882 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 1883 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 1884 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 1885 VMX_PIN_BASED_NMI_EXITING, 1886 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 1887 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 1888 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 1889 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 1890 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 1891 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 1892 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 1893 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING, 1894 .xlevel = 0x80000008, 1895 .model_id = "Common KVM processor" 1896 }, 1897 { 1898 .name = "qemu32", 1899 .level = 4, 1900 .vendor = CPUID_VENDOR_INTEL, 1901 .family = 6, 1902 .model = 6, 1903 .stepping = 3, 1904 .features[FEAT_1_EDX] = 1905 PPRO_FEATURES, 1906 .features[FEAT_1_ECX] = 1907 CPUID_EXT_SSE3, 1908 .xlevel = 0x80000004, 1909 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 1910 }, 1911 { 1912 .name = "kvm32", 1913 .level = 5, 1914 .vendor = CPUID_VENDOR_INTEL, 1915 .family = 15, 1916 .model = 6, 1917 .stepping = 1, 1918 .features[FEAT_1_EDX] = 1919 PPRO_FEATURES | CPUID_VME | 1920 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, 1921 .features[FEAT_1_ECX] = 1922 CPUID_EXT_SSE3, 1923 .features[FEAT_8000_0001_ECX] = 1924 0, 1925 /* VMX features from Yonah */ 1926 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 1927 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 1928 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 1929 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 1930 VMX_PIN_BASED_NMI_EXITING, 1931 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 1932 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 1933 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 1934 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 1935 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 1936 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 1937 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 1938 .xlevel = 0x80000008, 1939 .model_id = "Common 32-bit KVM processor" 1940 }, 1941 { 1942 .name = "coreduo", 1943 .level = 10, 1944 .vendor = CPUID_VENDOR_INTEL, 1945 .family = 6, 1946 .model = 14, 1947 .stepping = 8, 1948 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 1949 .features[FEAT_1_EDX] = 1950 PPRO_FEATURES | CPUID_VME | 1951 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI | 1952 CPUID_SS, 1953 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR, 1954 * CPUID_EXT_PDCM, CPUID_EXT_VMX */ 1955 .features[FEAT_1_ECX] = 1956 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, 1957 .features[FEAT_8000_0001_EDX] = 1958 CPUID_EXT2_NX, 1959 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 1960 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 1961 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 1962 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 1963 VMX_PIN_BASED_NMI_EXITING, 1964 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 1965 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 1966 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 1967 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 1968 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 1969 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 1970 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 1971 .xlevel = 0x80000008, 1972 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz", 1973 }, 1974 { 1975 .name = "486", 1976 .level = 1, 1977 .vendor = CPUID_VENDOR_INTEL, 1978 .family = 4, 1979 .model = 8, 1980 .stepping = 0, 1981 .features[FEAT_1_EDX] = 1982 I486_FEATURES, 1983 .xlevel = 0, 1984 .model_id = "", 1985 }, 1986 { 1987 .name = "pentium", 1988 .level = 1, 1989 .vendor = CPUID_VENDOR_INTEL, 1990 .family = 5, 1991 .model = 4, 1992 .stepping = 3, 1993 .features[FEAT_1_EDX] = 1994 PENTIUM_FEATURES, 1995 .xlevel = 0, 1996 .model_id = "", 1997 }, 1998 { 1999 .name = "pentium2", 2000 .level = 2, 2001 .vendor = CPUID_VENDOR_INTEL, 2002 .family = 6, 2003 .model = 5, 2004 .stepping = 2, 2005 .features[FEAT_1_EDX] = 2006 PENTIUM2_FEATURES, 2007 .xlevel = 0, 2008 .model_id = "", 2009 }, 2010 { 2011 .name = "pentium3", 2012 .level = 3, 2013 .vendor = CPUID_VENDOR_INTEL, 2014 .family = 6, 2015 .model = 7, 2016 .stepping = 3, 2017 .features[FEAT_1_EDX] = 2018 PENTIUM3_FEATURES, 2019 .xlevel = 0, 2020 .model_id = "", 2021 }, 2022 { 2023 .name = "athlon", 2024 .level = 2, 2025 .vendor = CPUID_VENDOR_AMD, 2026 .family = 6, 2027 .model = 2, 2028 .stepping = 3, 2029 .features[FEAT_1_EDX] = 2030 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | 2031 CPUID_MCA, 2032 .features[FEAT_8000_0001_EDX] = 2033 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, 2034 .xlevel = 0x80000008, 2035 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2036 }, 2037 { 2038 .name = "n270", 2039 .level = 10, 2040 .vendor = CPUID_VENDOR_INTEL, 2041 .family = 6, 2042 .model = 28, 2043 .stepping = 2, 2044 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2045 .features[FEAT_1_EDX] = 2046 PPRO_FEATURES | 2047 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | 2048 CPUID_ACPI | CPUID_SS, 2049 /* Some CPUs got no CPUID_SEP */ 2050 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2, 2051 * CPUID_EXT_XTPR */ 2052 .features[FEAT_1_ECX] = 2053 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2054 CPUID_EXT_MOVBE, 2055 .features[FEAT_8000_0001_EDX] = 2056 CPUID_EXT2_NX, 2057 .features[FEAT_8000_0001_ECX] = 2058 CPUID_EXT3_LAHF_LM, 2059 .xlevel = 0x80000008, 2060 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", 2061 }, 2062 { 2063 .name = "Conroe", 2064 .level = 10, 2065 .vendor = CPUID_VENDOR_INTEL, 2066 .family = 6, 2067 .model = 15, 2068 .stepping = 3, 2069 .features[FEAT_1_EDX] = 2070 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2071 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2072 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2073 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2074 CPUID_DE | CPUID_FP87, 2075 .features[FEAT_1_ECX] = 2076 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2077 .features[FEAT_8000_0001_EDX] = 2078 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2079 .features[FEAT_8000_0001_ECX] = 2080 CPUID_EXT3_LAHF_LM, 2081 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2082 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2083 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2084 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2085 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2086 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2087 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2088 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2089 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2090 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2091 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2092 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2093 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2094 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2095 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2096 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2097 .features[FEAT_VMX_SECONDARY_CTLS] = 2098 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2099 .xlevel = 0x80000008, 2100 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", 2101 }, 2102 { 2103 .name = "Penryn", 2104 .level = 10, 2105 .vendor = CPUID_VENDOR_INTEL, 2106 .family = 6, 2107 .model = 23, 2108 .stepping = 3, 2109 .features[FEAT_1_EDX] = 2110 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2111 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2112 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2113 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2114 CPUID_DE | CPUID_FP87, 2115 .features[FEAT_1_ECX] = 2116 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2117 CPUID_EXT_SSE3, 2118 .features[FEAT_8000_0001_EDX] = 2119 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2120 .features[FEAT_8000_0001_ECX] = 2121 CPUID_EXT3_LAHF_LM, 2122 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2123 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2124 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 2125 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT | 2126 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 2127 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2128 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2129 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2130 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2131 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2132 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2133 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2134 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2135 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2136 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2137 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2138 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2139 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2140 .features[FEAT_VMX_SECONDARY_CTLS] = 2141 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2142 VMX_SECONDARY_EXEC_WBINVD_EXITING, 2143 .xlevel = 0x80000008, 2144 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", 2145 }, 2146 { 2147 .name = "Nehalem", 2148 .level = 11, 2149 .vendor = CPUID_VENDOR_INTEL, 2150 .family = 6, 2151 .model = 26, 2152 .stepping = 3, 2153 .features[FEAT_1_EDX] = 2154 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2155 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2156 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2157 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2158 CPUID_DE | CPUID_FP87, 2159 .features[FEAT_1_ECX] = 2160 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2161 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2162 .features[FEAT_8000_0001_EDX] = 2163 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2164 .features[FEAT_8000_0001_ECX] = 2165 CPUID_EXT3_LAHF_LM, 2166 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2167 MSR_VMX_BASIC_TRUE_CTLS, 2168 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2169 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2170 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2171 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2172 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2173 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2174 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2175 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2176 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2177 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2178 .features[FEAT_VMX_EXIT_CTLS] = 2179 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2180 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2181 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2182 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2183 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2184 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2185 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2186 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2187 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2188 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2189 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2190 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2191 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2192 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2193 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2194 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2195 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2196 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2197 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2198 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2199 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2200 .features[FEAT_VMX_SECONDARY_CTLS] = 2201 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2202 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2203 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2204 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2205 VMX_SECONDARY_EXEC_ENABLE_VPID, 2206 .xlevel = 0x80000008, 2207 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)", 2208 .versions = (X86CPUVersionDefinition[]) { 2209 { .version = 1 }, 2210 { 2211 .version = 2, 2212 .alias = "Nehalem-IBRS", 2213 .props = (PropValue[]) { 2214 { "spec-ctrl", "on" }, 2215 { "model-id", 2216 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" }, 2217 { /* end of list */ } 2218 } 2219 }, 2220 { /* end of list */ } 2221 } 2222 }, 2223 { 2224 .name = "Westmere", 2225 .level = 11, 2226 .vendor = CPUID_VENDOR_INTEL, 2227 .family = 6, 2228 .model = 44, 2229 .stepping = 1, 2230 .features[FEAT_1_EDX] = 2231 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2232 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2233 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2234 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2235 CPUID_DE | CPUID_FP87, 2236 .features[FEAT_1_ECX] = 2237 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 2238 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2239 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 2240 .features[FEAT_8000_0001_EDX] = 2241 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2242 .features[FEAT_8000_0001_ECX] = 2243 CPUID_EXT3_LAHF_LM, 2244 .features[FEAT_6_EAX] = 2245 CPUID_6_EAX_ARAT, 2246 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2247 MSR_VMX_BASIC_TRUE_CTLS, 2248 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2249 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2250 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2251 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2252 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2253 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2254 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2255 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2256 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2257 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2258 .features[FEAT_VMX_EXIT_CTLS] = 2259 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2260 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2261 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2262 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2263 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2264 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2265 MSR_VMX_MISC_STORE_LMA, 2266 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2267 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2268 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2269 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2270 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2271 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2272 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2273 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2274 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2275 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2276 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2277 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2278 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2279 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2280 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2281 .features[FEAT_VMX_SECONDARY_CTLS] = 2282 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2283 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2284 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2285 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2286 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 2287 .xlevel = 0x80000008, 2288 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", 2289 .versions = (X86CPUVersionDefinition[]) { 2290 { .version = 1 }, 2291 { 2292 .version = 2, 2293 .alias = "Westmere-IBRS", 2294 .props = (PropValue[]) { 2295 { "spec-ctrl", "on" }, 2296 { "model-id", 2297 "Westmere E56xx/L56xx/X56xx (IBRS update)" }, 2298 { /* end of list */ } 2299 } 2300 }, 2301 { /* end of list */ } 2302 } 2303 }, 2304 { 2305 .name = "SandyBridge", 2306 .level = 0xd, 2307 .vendor = CPUID_VENDOR_INTEL, 2308 .family = 6, 2309 .model = 42, 2310 .stepping = 1, 2311 .features[FEAT_1_EDX] = 2312 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2313 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2314 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2315 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2316 CPUID_DE | CPUID_FP87, 2317 .features[FEAT_1_ECX] = 2318 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2319 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 2320 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2321 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 2322 CPUID_EXT_SSE3, 2323 .features[FEAT_8000_0001_EDX] = 2324 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2325 CPUID_EXT2_SYSCALL, 2326 .features[FEAT_8000_0001_ECX] = 2327 CPUID_EXT3_LAHF_LM, 2328 .features[FEAT_XSAVE] = 2329 CPUID_XSAVE_XSAVEOPT, 2330 .features[FEAT_6_EAX] = 2331 CPUID_6_EAX_ARAT, 2332 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2333 MSR_VMX_BASIC_TRUE_CTLS, 2334 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2335 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2336 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2337 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2338 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2339 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2340 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2341 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2342 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2343 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2344 .features[FEAT_VMX_EXIT_CTLS] = 2345 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2346 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2347 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2348 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2349 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2350 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2351 MSR_VMX_MISC_STORE_LMA, 2352 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2353 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2354 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2355 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2356 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2357 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2358 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2359 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2360 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2361 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2362 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2363 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2364 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2365 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2366 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2367 .features[FEAT_VMX_SECONDARY_CTLS] = 2368 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2369 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2370 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2371 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2372 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 2373 .xlevel = 0x80000008, 2374 .model_id = "Intel Xeon E312xx (Sandy Bridge)", 2375 .versions = (X86CPUVersionDefinition[]) { 2376 { .version = 1 }, 2377 { 2378 .version = 2, 2379 .alias = "SandyBridge-IBRS", 2380 .props = (PropValue[]) { 2381 { "spec-ctrl", "on" }, 2382 { "model-id", 2383 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" }, 2384 { /* end of list */ } 2385 } 2386 }, 2387 { /* end of list */ } 2388 } 2389 }, 2390 { 2391 .name = "IvyBridge", 2392 .level = 0xd, 2393 .vendor = CPUID_VENDOR_INTEL, 2394 .family = 6, 2395 .model = 58, 2396 .stepping = 9, 2397 .features[FEAT_1_EDX] = 2398 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2399 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2400 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2401 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2402 CPUID_DE | CPUID_FP87, 2403 .features[FEAT_1_ECX] = 2404 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2405 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 2406 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2407 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 2408 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2409 .features[FEAT_7_0_EBX] = 2410 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | 2411 CPUID_7_0_EBX_ERMS, 2412 .features[FEAT_8000_0001_EDX] = 2413 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2414 CPUID_EXT2_SYSCALL, 2415 .features[FEAT_8000_0001_ECX] = 2416 CPUID_EXT3_LAHF_LM, 2417 .features[FEAT_XSAVE] = 2418 CPUID_XSAVE_XSAVEOPT, 2419 .features[FEAT_6_EAX] = 2420 CPUID_6_EAX_ARAT, 2421 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2422 MSR_VMX_BASIC_TRUE_CTLS, 2423 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2424 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2425 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2426 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2427 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2428 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2429 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2430 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2431 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2432 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2433 .features[FEAT_VMX_EXIT_CTLS] = 2434 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2435 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2436 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2437 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2438 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2439 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2440 MSR_VMX_MISC_STORE_LMA, 2441 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2442 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2443 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 2444 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2445 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2446 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2447 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2448 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2449 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2450 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2451 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2452 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2453 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2454 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2455 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2456 .features[FEAT_VMX_SECONDARY_CTLS] = 2457 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2458 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2459 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2460 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2461 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2462 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 2463 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2464 VMX_SECONDARY_EXEC_RDRAND_EXITING, 2465 .xlevel = 0x80000008, 2466 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", 2467 .versions = (X86CPUVersionDefinition[]) { 2468 { .version = 1 }, 2469 { 2470 .version = 2, 2471 .alias = "IvyBridge-IBRS", 2472 .props = (PropValue[]) { 2473 { "spec-ctrl", "on" }, 2474 { "model-id", 2475 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" }, 2476 { /* end of list */ } 2477 } 2478 }, 2479 { /* end of list */ } 2480 } 2481 }, 2482 { 2483 .name = "Haswell", 2484 .level = 0xd, 2485 .vendor = CPUID_VENDOR_INTEL, 2486 .family = 6, 2487 .model = 60, 2488 .stepping = 4, 2489 .features[FEAT_1_EDX] = 2490 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2491 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2492 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2493 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2494 CPUID_DE | CPUID_FP87, 2495 .features[FEAT_1_ECX] = 2496 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2497 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2498 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2499 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2500 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2501 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2502 .features[FEAT_8000_0001_EDX] = 2503 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2504 CPUID_EXT2_SYSCALL, 2505 .features[FEAT_8000_0001_ECX] = 2506 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 2507 .features[FEAT_7_0_EBX] = 2508 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2509 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2510 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2511 CPUID_7_0_EBX_RTM, 2512 .features[FEAT_XSAVE] = 2513 CPUID_XSAVE_XSAVEOPT, 2514 .features[FEAT_6_EAX] = 2515 CPUID_6_EAX_ARAT, 2516 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2517 MSR_VMX_BASIC_TRUE_CTLS, 2518 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2519 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2520 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2521 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2522 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2523 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2524 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2525 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2526 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2527 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 2528 .features[FEAT_VMX_EXIT_CTLS] = 2529 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2530 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2531 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2532 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2533 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2534 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2535 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 2536 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2537 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2538 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 2539 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2540 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2541 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2542 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2543 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2544 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2545 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2546 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2547 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2548 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2549 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2550 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2551 .features[FEAT_VMX_SECONDARY_CTLS] = 2552 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2553 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2554 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2555 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2556 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2557 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 2558 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2559 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 2560 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 2561 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 2562 .xlevel = 0x80000008, 2563 .model_id = "Intel Core Processor (Haswell)", 2564 .versions = (X86CPUVersionDefinition[]) { 2565 { .version = 1 }, 2566 { 2567 .version = 2, 2568 .alias = "Haswell-noTSX", 2569 .props = (PropValue[]) { 2570 { "hle", "off" }, 2571 { "rtm", "off" }, 2572 { "stepping", "1" }, 2573 { "model-id", "Intel Core Processor (Haswell, no TSX)", }, 2574 { /* end of list */ } 2575 }, 2576 }, 2577 { 2578 .version = 3, 2579 .alias = "Haswell-IBRS", 2580 .props = (PropValue[]) { 2581 /* Restore TSX features removed by -v2 above */ 2582 { "hle", "on" }, 2583 { "rtm", "on" }, 2584 /* 2585 * Haswell and Haswell-IBRS had stepping=4 in 2586 * QEMU 4.0 and older 2587 */ 2588 { "stepping", "4" }, 2589 { "spec-ctrl", "on" }, 2590 { "model-id", 2591 "Intel Core Processor (Haswell, IBRS)" }, 2592 { /* end of list */ } 2593 } 2594 }, 2595 { 2596 .version = 4, 2597 .alias = "Haswell-noTSX-IBRS", 2598 .props = (PropValue[]) { 2599 { "hle", "off" }, 2600 { "rtm", "off" }, 2601 /* spec-ctrl was already enabled by -v3 above */ 2602 { "stepping", "1" }, 2603 { "model-id", 2604 "Intel Core Processor (Haswell, no TSX, IBRS)" }, 2605 { /* end of list */ } 2606 } 2607 }, 2608 { /* end of list */ } 2609 } 2610 }, 2611 { 2612 .name = "Broadwell", 2613 .level = 0xd, 2614 .vendor = CPUID_VENDOR_INTEL, 2615 .family = 6, 2616 .model = 61, 2617 .stepping = 2, 2618 .features[FEAT_1_EDX] = 2619 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2620 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2621 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2622 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2623 CPUID_DE | CPUID_FP87, 2624 .features[FEAT_1_ECX] = 2625 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2626 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2627 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2628 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2629 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2630 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2631 .features[FEAT_8000_0001_EDX] = 2632 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2633 CPUID_EXT2_SYSCALL, 2634 .features[FEAT_8000_0001_ECX] = 2635 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 2636 .features[FEAT_7_0_EBX] = 2637 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2638 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2639 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2640 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 2641 CPUID_7_0_EBX_SMAP, 2642 .features[FEAT_XSAVE] = 2643 CPUID_XSAVE_XSAVEOPT, 2644 .features[FEAT_6_EAX] = 2645 CPUID_6_EAX_ARAT, 2646 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2647 MSR_VMX_BASIC_TRUE_CTLS, 2648 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2649 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2650 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2651 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2652 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2653 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2654 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2655 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2656 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2657 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 2658 .features[FEAT_VMX_EXIT_CTLS] = 2659 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2660 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2661 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2662 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2663 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2664 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2665 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 2666 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2667 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2668 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 2669 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2670 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2671 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2672 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2673 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2674 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2675 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2676 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2677 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2678 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2679 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2680 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2681 .features[FEAT_VMX_SECONDARY_CTLS] = 2682 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2683 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2684 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2685 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2686 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2687 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 2688 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2689 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 2690 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 2691 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 2692 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 2693 .xlevel = 0x80000008, 2694 .model_id = "Intel Core Processor (Broadwell)", 2695 .versions = (X86CPUVersionDefinition[]) { 2696 { .version = 1 }, 2697 { 2698 .version = 2, 2699 .alias = "Broadwell-noTSX", 2700 .props = (PropValue[]) { 2701 { "hle", "off" }, 2702 { "rtm", "off" }, 2703 { "model-id", "Intel Core Processor (Broadwell, no TSX)", }, 2704 { /* end of list */ } 2705 }, 2706 }, 2707 { 2708 .version = 3, 2709 .alias = "Broadwell-IBRS", 2710 .props = (PropValue[]) { 2711 /* Restore TSX features removed by -v2 above */ 2712 { "hle", "on" }, 2713 { "rtm", "on" }, 2714 { "spec-ctrl", "on" }, 2715 { "model-id", 2716 "Intel Core Processor (Broadwell, IBRS)" }, 2717 { /* end of list */ } 2718 } 2719 }, 2720 { 2721 .version = 4, 2722 .alias = "Broadwell-noTSX-IBRS", 2723 .props = (PropValue[]) { 2724 { "hle", "off" }, 2725 { "rtm", "off" }, 2726 /* spec-ctrl was already enabled by -v3 above */ 2727 { "model-id", 2728 "Intel Core Processor (Broadwell, no TSX, IBRS)" }, 2729 { /* end of list */ } 2730 } 2731 }, 2732 { /* end of list */ } 2733 } 2734 }, 2735 { 2736 .name = "Skylake-Client", 2737 .level = 0xd, 2738 .vendor = CPUID_VENDOR_INTEL, 2739 .family = 6, 2740 .model = 94, 2741 .stepping = 3, 2742 .features[FEAT_1_EDX] = 2743 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2744 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2745 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2746 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2747 CPUID_DE | CPUID_FP87, 2748 .features[FEAT_1_ECX] = 2749 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2750 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2751 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2752 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2753 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2754 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2755 .features[FEAT_8000_0001_EDX] = 2756 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2757 CPUID_EXT2_SYSCALL, 2758 .features[FEAT_8000_0001_ECX] = 2759 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 2760 .features[FEAT_7_0_EBX] = 2761 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2762 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2763 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2764 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 2765 CPUID_7_0_EBX_SMAP, 2766 /* XSAVES is added in version 4 */ 2767 .features[FEAT_XSAVE] = 2768 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 2769 CPUID_XSAVE_XGETBV1, 2770 .features[FEAT_6_EAX] = 2771 CPUID_6_EAX_ARAT, 2772 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 2773 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2774 MSR_VMX_BASIC_TRUE_CTLS, 2775 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2776 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2777 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2778 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2779 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2780 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2781 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2782 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2783 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2784 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 2785 .features[FEAT_VMX_EXIT_CTLS] = 2786 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2787 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2788 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2789 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2790 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2791 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2792 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 2793 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2794 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2795 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2796 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2797 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2798 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2799 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2800 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2801 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2802 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2803 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2804 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2805 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2806 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2807 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2808 .features[FEAT_VMX_SECONDARY_CTLS] = 2809 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2810 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2811 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2812 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2813 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 2814 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 2815 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 2816 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 2817 .xlevel = 0x80000008, 2818 .model_id = "Intel Core Processor (Skylake)", 2819 .versions = (X86CPUVersionDefinition[]) { 2820 { .version = 1 }, 2821 { 2822 .version = 2, 2823 .alias = "Skylake-Client-IBRS", 2824 .props = (PropValue[]) { 2825 { "spec-ctrl", "on" }, 2826 { "model-id", 2827 "Intel Core Processor (Skylake, IBRS)" }, 2828 { /* end of list */ } 2829 } 2830 }, 2831 { 2832 .version = 3, 2833 .alias = "Skylake-Client-noTSX-IBRS", 2834 .props = (PropValue[]) { 2835 { "hle", "off" }, 2836 { "rtm", "off" }, 2837 { "model-id", 2838 "Intel Core Processor (Skylake, IBRS, no TSX)" }, 2839 { /* end of list */ } 2840 } 2841 }, 2842 { 2843 .version = 4, 2844 .note = "IBRS, XSAVES, no TSX", 2845 .props = (PropValue[]) { 2846 { "xsaves", "on" }, 2847 { "vmx-xsaves", "on" }, 2848 { /* end of list */ } 2849 } 2850 }, 2851 { /* end of list */ } 2852 } 2853 }, 2854 { 2855 .name = "Skylake-Server", 2856 .level = 0xd, 2857 .vendor = CPUID_VENDOR_INTEL, 2858 .family = 6, 2859 .model = 85, 2860 .stepping = 4, 2861 .features[FEAT_1_EDX] = 2862 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2863 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2864 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2865 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2866 CPUID_DE | CPUID_FP87, 2867 .features[FEAT_1_ECX] = 2868 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2869 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2870 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2871 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2872 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2873 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2874 .features[FEAT_8000_0001_EDX] = 2875 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 2876 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2877 .features[FEAT_8000_0001_ECX] = 2878 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 2879 .features[FEAT_7_0_EBX] = 2880 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2881 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2882 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2883 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 2884 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 2885 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 2886 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 2887 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 2888 .features[FEAT_7_0_ECX] = 2889 CPUID_7_0_ECX_PKU, 2890 /* XSAVES is added in version 5 */ 2891 .features[FEAT_XSAVE] = 2892 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 2893 CPUID_XSAVE_XGETBV1, 2894 .features[FEAT_6_EAX] = 2895 CPUID_6_EAX_ARAT, 2896 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 2897 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2898 MSR_VMX_BASIC_TRUE_CTLS, 2899 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2900 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2901 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2902 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2903 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2904 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2905 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2906 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2907 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2908 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 2909 .features[FEAT_VMX_EXIT_CTLS] = 2910 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2911 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2912 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2913 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2914 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2915 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2916 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 2917 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2918 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2919 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 2920 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2921 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2922 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2923 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2924 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2925 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2926 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2927 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2928 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2929 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2930 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2931 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2932 .features[FEAT_VMX_SECONDARY_CTLS] = 2933 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2934 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2935 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2936 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2937 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2938 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 2939 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2940 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 2941 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 2942 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 2943 .xlevel = 0x80000008, 2944 .model_id = "Intel Xeon Processor (Skylake)", 2945 .versions = (X86CPUVersionDefinition[]) { 2946 { .version = 1 }, 2947 { 2948 .version = 2, 2949 .alias = "Skylake-Server-IBRS", 2950 .props = (PropValue[]) { 2951 /* clflushopt was not added to Skylake-Server-IBRS */ 2952 /* TODO: add -v3 including clflushopt */ 2953 { "clflushopt", "off" }, 2954 { "spec-ctrl", "on" }, 2955 { "model-id", 2956 "Intel Xeon Processor (Skylake, IBRS)" }, 2957 { /* end of list */ } 2958 } 2959 }, 2960 { 2961 .version = 3, 2962 .alias = "Skylake-Server-noTSX-IBRS", 2963 .props = (PropValue[]) { 2964 { "hle", "off" }, 2965 { "rtm", "off" }, 2966 { "model-id", 2967 "Intel Xeon Processor (Skylake, IBRS, no TSX)" }, 2968 { /* end of list */ } 2969 } 2970 }, 2971 { 2972 .version = 4, 2973 .props = (PropValue[]) { 2974 { "vmx-eptp-switching", "on" }, 2975 { /* end of list */ } 2976 } 2977 }, 2978 { 2979 .version = 5, 2980 .note = "IBRS, XSAVES, EPT switching, no TSX", 2981 .props = (PropValue[]) { 2982 { "xsaves", "on" }, 2983 { "vmx-xsaves", "on" }, 2984 { /* end of list */ } 2985 } 2986 }, 2987 { /* end of list */ } 2988 } 2989 }, 2990 { 2991 .name = "Cascadelake-Server", 2992 .level = 0xd, 2993 .vendor = CPUID_VENDOR_INTEL, 2994 .family = 6, 2995 .model = 85, 2996 .stepping = 6, 2997 .features[FEAT_1_EDX] = 2998 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2999 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3000 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3001 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3002 CPUID_DE | CPUID_FP87, 3003 .features[FEAT_1_ECX] = 3004 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3005 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3006 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3007 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3008 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3009 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3010 .features[FEAT_8000_0001_EDX] = 3011 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3012 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3013 .features[FEAT_8000_0001_ECX] = 3014 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3015 .features[FEAT_7_0_EBX] = 3016 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3017 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3018 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3019 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3020 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3021 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3022 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3023 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3024 .features[FEAT_7_0_ECX] = 3025 CPUID_7_0_ECX_PKU | 3026 CPUID_7_0_ECX_AVX512VNNI, 3027 .features[FEAT_7_0_EDX] = 3028 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3029 /* XSAVES is added in version 5 */ 3030 .features[FEAT_XSAVE] = 3031 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3032 CPUID_XSAVE_XGETBV1, 3033 .features[FEAT_6_EAX] = 3034 CPUID_6_EAX_ARAT, 3035 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3036 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3037 MSR_VMX_BASIC_TRUE_CTLS, 3038 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3039 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3040 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3041 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3042 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3043 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3044 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3045 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3046 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3047 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3048 .features[FEAT_VMX_EXIT_CTLS] = 3049 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3050 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3051 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3052 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3053 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3054 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3055 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3056 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3057 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3058 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3059 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3060 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3061 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3062 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3063 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3064 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3065 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3066 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3067 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3068 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3069 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3070 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3071 .features[FEAT_VMX_SECONDARY_CTLS] = 3072 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3073 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3074 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3075 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3076 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3077 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3078 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3079 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3080 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3081 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3082 .xlevel = 0x80000008, 3083 .model_id = "Intel Xeon Processor (Cascadelake)", 3084 .versions = (X86CPUVersionDefinition[]) { 3085 { .version = 1 }, 3086 { .version = 2, 3087 .note = "ARCH_CAPABILITIES", 3088 .props = (PropValue[]) { 3089 { "arch-capabilities", "on" }, 3090 { "rdctl-no", "on" }, 3091 { "ibrs-all", "on" }, 3092 { "skip-l1dfl-vmentry", "on" }, 3093 { "mds-no", "on" }, 3094 { /* end of list */ } 3095 }, 3096 }, 3097 { .version = 3, 3098 .alias = "Cascadelake-Server-noTSX", 3099 .note = "ARCH_CAPABILITIES, no TSX", 3100 .props = (PropValue[]) { 3101 { "hle", "off" }, 3102 { "rtm", "off" }, 3103 { /* end of list */ } 3104 }, 3105 }, 3106 { .version = 4, 3107 .note = "ARCH_CAPABILITIES, no TSX", 3108 .props = (PropValue[]) { 3109 { "vmx-eptp-switching", "on" }, 3110 { /* end of list */ } 3111 }, 3112 }, 3113 { .version = 5, 3114 .note = "ARCH_CAPABILITIES, EPT switching, XSAVES, no TSX", 3115 .props = (PropValue[]) { 3116 { "xsaves", "on" }, 3117 { "vmx-xsaves", "on" }, 3118 { /* end of list */ } 3119 }, 3120 }, 3121 { /* end of list */ } 3122 } 3123 }, 3124 { 3125 .name = "Cooperlake", 3126 .level = 0xd, 3127 .vendor = CPUID_VENDOR_INTEL, 3128 .family = 6, 3129 .model = 85, 3130 .stepping = 10, 3131 .features[FEAT_1_EDX] = 3132 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3133 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3134 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3135 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3136 CPUID_DE | CPUID_FP87, 3137 .features[FEAT_1_ECX] = 3138 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3139 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3140 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3141 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3142 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3143 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3144 .features[FEAT_8000_0001_EDX] = 3145 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3146 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3147 .features[FEAT_8000_0001_ECX] = 3148 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3149 .features[FEAT_7_0_EBX] = 3150 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3151 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3152 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3153 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3154 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3155 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3156 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3157 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3158 .features[FEAT_7_0_ECX] = 3159 CPUID_7_0_ECX_PKU | 3160 CPUID_7_0_ECX_AVX512VNNI, 3161 .features[FEAT_7_0_EDX] = 3162 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP | 3163 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES, 3164 .features[FEAT_ARCH_CAPABILITIES] = 3165 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 3166 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 3167 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 3168 .features[FEAT_7_1_EAX] = 3169 CPUID_7_1_EAX_AVX512_BF16, 3170 /* XSAVES is added in version 2 */ 3171 .features[FEAT_XSAVE] = 3172 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3173 CPUID_XSAVE_XGETBV1, 3174 .features[FEAT_6_EAX] = 3175 CPUID_6_EAX_ARAT, 3176 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3177 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3178 MSR_VMX_BASIC_TRUE_CTLS, 3179 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3180 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3181 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3182 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3183 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3184 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3185 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3186 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3187 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3188 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3189 .features[FEAT_VMX_EXIT_CTLS] = 3190 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3191 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3192 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3193 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3194 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3195 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3196 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3197 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3198 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3199 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3200 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3201 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3202 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3203 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3204 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3205 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3206 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3207 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3208 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3209 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3210 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3211 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3212 .features[FEAT_VMX_SECONDARY_CTLS] = 3213 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3214 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3215 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3216 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3217 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3218 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3219 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3220 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3221 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3222 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3223 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3224 .xlevel = 0x80000008, 3225 .model_id = "Intel Xeon Processor (Cooperlake)", 3226 .versions = (X86CPUVersionDefinition[]) { 3227 { .version = 1 }, 3228 { .version = 2, 3229 .note = "XSAVES", 3230 .props = (PropValue[]) { 3231 { "xsaves", "on" }, 3232 { "vmx-xsaves", "on" }, 3233 { /* end of list */ } 3234 }, 3235 }, 3236 { /* end of list */ } 3237 } 3238 }, 3239 { 3240 .name = "Icelake-Client", 3241 .level = 0xd, 3242 .vendor = CPUID_VENDOR_INTEL, 3243 .family = 6, 3244 .model = 126, 3245 .stepping = 0, 3246 .features[FEAT_1_EDX] = 3247 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3248 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3249 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3250 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3251 CPUID_DE | CPUID_FP87, 3252 .features[FEAT_1_ECX] = 3253 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3254 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3255 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3256 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3257 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3258 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3259 .features[FEAT_8000_0001_EDX] = 3260 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3261 CPUID_EXT2_SYSCALL, 3262 .features[FEAT_8000_0001_ECX] = 3263 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3264 .features[FEAT_8000_0008_EBX] = 3265 CPUID_8000_0008_EBX_WBNOINVD, 3266 .features[FEAT_7_0_EBX] = 3267 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3268 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3269 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3270 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3271 CPUID_7_0_EBX_SMAP, 3272 .features[FEAT_7_0_ECX] = 3273 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 3274 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 3275 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 3276 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 3277 CPUID_7_0_ECX_AVX512_VPOPCNTDQ, 3278 .features[FEAT_7_0_EDX] = 3279 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3280 /* XSAVES is added in version 3 */ 3281 .features[FEAT_XSAVE] = 3282 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3283 CPUID_XSAVE_XGETBV1, 3284 .features[FEAT_6_EAX] = 3285 CPUID_6_EAX_ARAT, 3286 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3287 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3288 MSR_VMX_BASIC_TRUE_CTLS, 3289 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3290 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3291 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3292 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3293 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3294 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3295 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3296 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3297 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3298 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3299 .features[FEAT_VMX_EXIT_CTLS] = 3300 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3301 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3302 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3303 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3304 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3305 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3306 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3307 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3308 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3309 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3310 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3311 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3312 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3313 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3314 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3315 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3316 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3317 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3318 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3319 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3320 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3321 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3322 .features[FEAT_VMX_SECONDARY_CTLS] = 3323 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3324 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3325 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3326 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3327 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3328 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3329 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3330 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3331 .xlevel = 0x80000008, 3332 .model_id = "Intel Core Processor (Icelake)", 3333 .versions = (X86CPUVersionDefinition[]) { 3334 { 3335 .version = 1, 3336 .note = "deprecated" 3337 }, 3338 { 3339 .version = 2, 3340 .note = "no TSX, deprecated", 3341 .alias = "Icelake-Client-noTSX", 3342 .props = (PropValue[]) { 3343 { "hle", "off" }, 3344 { "rtm", "off" }, 3345 { /* end of list */ } 3346 }, 3347 }, 3348 { 3349 .version = 3, 3350 .note = "no TSX, XSAVES, deprecated", 3351 .props = (PropValue[]) { 3352 { "xsaves", "on" }, 3353 { "vmx-xsaves", "on" }, 3354 { /* end of list */ } 3355 }, 3356 }, 3357 { /* end of list */ } 3358 }, 3359 .deprecation_note = "use Icelake-Server instead" 3360 }, 3361 { 3362 .name = "Icelake-Server", 3363 .level = 0xd, 3364 .vendor = CPUID_VENDOR_INTEL, 3365 .family = 6, 3366 .model = 134, 3367 .stepping = 0, 3368 .features[FEAT_1_EDX] = 3369 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3370 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3371 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3372 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3373 CPUID_DE | CPUID_FP87, 3374 .features[FEAT_1_ECX] = 3375 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3376 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3377 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3378 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3379 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3380 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3381 .features[FEAT_8000_0001_EDX] = 3382 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3383 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3384 .features[FEAT_8000_0001_ECX] = 3385 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3386 .features[FEAT_8000_0008_EBX] = 3387 CPUID_8000_0008_EBX_WBNOINVD, 3388 .features[FEAT_7_0_EBX] = 3389 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3390 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3391 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3392 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3393 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3394 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3395 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3396 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3397 .features[FEAT_7_0_ECX] = 3398 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 3399 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 3400 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 3401 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 3402 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57, 3403 .features[FEAT_7_0_EDX] = 3404 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3405 /* XSAVES is added in version 5 */ 3406 .features[FEAT_XSAVE] = 3407 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3408 CPUID_XSAVE_XGETBV1, 3409 .features[FEAT_6_EAX] = 3410 CPUID_6_EAX_ARAT, 3411 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3412 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3413 MSR_VMX_BASIC_TRUE_CTLS, 3414 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3415 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3416 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3417 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3418 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3419 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3420 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3421 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3422 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3423 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3424 .features[FEAT_VMX_EXIT_CTLS] = 3425 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3426 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3427 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3428 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3429 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3430 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3431 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3432 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3433 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3434 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3435 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3436 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3437 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3438 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3439 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3440 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3441 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3442 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3443 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3444 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3445 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3446 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3447 .features[FEAT_VMX_SECONDARY_CTLS] = 3448 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3449 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3450 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3451 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3452 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3453 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3454 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3455 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3456 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 3457 .xlevel = 0x80000008, 3458 .model_id = "Intel Xeon Processor (Icelake)", 3459 .versions = (X86CPUVersionDefinition[]) { 3460 { .version = 1 }, 3461 { 3462 .version = 2, 3463 .note = "no TSX", 3464 .alias = "Icelake-Server-noTSX", 3465 .props = (PropValue[]) { 3466 { "hle", "off" }, 3467 { "rtm", "off" }, 3468 { /* end of list */ } 3469 }, 3470 }, 3471 { 3472 .version = 3, 3473 .props = (PropValue[]) { 3474 { "arch-capabilities", "on" }, 3475 { "rdctl-no", "on" }, 3476 { "ibrs-all", "on" }, 3477 { "skip-l1dfl-vmentry", "on" }, 3478 { "mds-no", "on" }, 3479 { "pschange-mc-no", "on" }, 3480 { "taa-no", "on" }, 3481 { /* end of list */ } 3482 }, 3483 }, 3484 { 3485 .version = 4, 3486 .props = (PropValue[]) { 3487 { "sha-ni", "on" }, 3488 { "avx512ifma", "on" }, 3489 { "rdpid", "on" }, 3490 { "fsrm", "on" }, 3491 { "vmx-rdseed-exit", "on" }, 3492 { "vmx-pml", "on" }, 3493 { "vmx-eptp-switching", "on" }, 3494 { "model", "106" }, 3495 { /* end of list */ } 3496 }, 3497 }, 3498 { 3499 .version = 5, 3500 .note = "XSAVES", 3501 .props = (PropValue[]) { 3502 { "xsaves", "on" }, 3503 { "vmx-xsaves", "on" }, 3504 { /* end of list */ } 3505 }, 3506 }, 3507 { /* end of list */ } 3508 } 3509 }, 3510 { 3511 .name = "Denverton", 3512 .level = 21, 3513 .vendor = CPUID_VENDOR_INTEL, 3514 .family = 6, 3515 .model = 95, 3516 .stepping = 1, 3517 .features[FEAT_1_EDX] = 3518 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 3519 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 3520 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 3521 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 3522 CPUID_SSE | CPUID_SSE2, 3523 .features[FEAT_1_ECX] = 3524 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 3525 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 | 3526 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 3527 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | 3528 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND, 3529 .features[FEAT_8000_0001_EDX] = 3530 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 3531 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 3532 .features[FEAT_8000_0001_ECX] = 3533 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3534 .features[FEAT_7_0_EBX] = 3535 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS | 3536 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP | 3537 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI, 3538 .features[FEAT_7_0_EDX] = 3539 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 3540 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3541 /* XSAVES is added in version 3 */ 3542 .features[FEAT_XSAVE] = 3543 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1, 3544 .features[FEAT_6_EAX] = 3545 CPUID_6_EAX_ARAT, 3546 .features[FEAT_ARCH_CAPABILITIES] = 3547 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY, 3548 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3549 MSR_VMX_BASIC_TRUE_CTLS, 3550 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3551 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3552 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3553 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3554 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3555 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3556 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3557 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3558 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3559 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3560 .features[FEAT_VMX_EXIT_CTLS] = 3561 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3562 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3563 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3564 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3565 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3566 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3567 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3568 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3569 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3570 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3571 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3572 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3573 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3574 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3575 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3576 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3577 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3578 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3579 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3580 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3581 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3582 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3583 .features[FEAT_VMX_SECONDARY_CTLS] = 3584 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3585 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3586 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3587 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3588 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3589 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3590 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3591 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3592 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3593 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3594 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3595 .xlevel = 0x80000008, 3596 .model_id = "Intel Atom Processor (Denverton)", 3597 .versions = (X86CPUVersionDefinition[]) { 3598 { .version = 1 }, 3599 { 3600 .version = 2, 3601 .note = "no MPX, no MONITOR", 3602 .props = (PropValue[]) { 3603 { "monitor", "off" }, 3604 { "mpx", "off" }, 3605 { /* end of list */ }, 3606 }, 3607 }, 3608 { 3609 .version = 3, 3610 .note = "XSAVES, no MPX, no MONITOR", 3611 .props = (PropValue[]) { 3612 { "xsaves", "on" }, 3613 { "vmx-xsaves", "on" }, 3614 { /* end of list */ }, 3615 }, 3616 }, 3617 { /* end of list */ }, 3618 }, 3619 }, 3620 { 3621 .name = "Snowridge", 3622 .level = 27, 3623 .vendor = CPUID_VENDOR_INTEL, 3624 .family = 6, 3625 .model = 134, 3626 .stepping = 1, 3627 .features[FEAT_1_EDX] = 3628 /* missing: CPUID_PN CPUID_IA64 */ 3629 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 3630 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | 3631 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | 3632 CPUID_CX8 | CPUID_APIC | CPUID_SEP | 3633 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 3634 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | 3635 CPUID_MMX | 3636 CPUID_FXSR | CPUID_SSE | CPUID_SSE2, 3637 .features[FEAT_1_ECX] = 3638 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 3639 CPUID_EXT_SSSE3 | 3640 CPUID_EXT_CX16 | 3641 CPUID_EXT_SSE41 | 3642 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 3643 CPUID_EXT_POPCNT | 3644 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE | 3645 CPUID_EXT_RDRAND, 3646 .features[FEAT_8000_0001_EDX] = 3647 CPUID_EXT2_SYSCALL | 3648 CPUID_EXT2_NX | 3649 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3650 CPUID_EXT2_LM, 3651 .features[FEAT_8000_0001_ECX] = 3652 CPUID_EXT3_LAHF_LM | 3653 CPUID_EXT3_3DNOWPREFETCH, 3654 .features[FEAT_7_0_EBX] = 3655 CPUID_7_0_EBX_FSGSBASE | 3656 CPUID_7_0_EBX_SMEP | 3657 CPUID_7_0_EBX_ERMS | 3658 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */ 3659 CPUID_7_0_EBX_RDSEED | 3660 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 3661 CPUID_7_0_EBX_CLWB | 3662 CPUID_7_0_EBX_SHA_NI, 3663 .features[FEAT_7_0_ECX] = 3664 CPUID_7_0_ECX_UMIP | 3665 /* missing bit 5 */ 3666 CPUID_7_0_ECX_GFNI | 3667 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE | 3668 CPUID_7_0_ECX_MOVDIR64B, 3669 .features[FEAT_7_0_EDX] = 3670 CPUID_7_0_EDX_SPEC_CTRL | 3671 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD | 3672 CPUID_7_0_EDX_CORE_CAPABILITY, 3673 .features[FEAT_CORE_CAPABILITY] = 3674 MSR_CORE_CAP_SPLIT_LOCK_DETECT, 3675 /* XSAVES is is added in version 3 */ 3676 .features[FEAT_XSAVE] = 3677 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3678 CPUID_XSAVE_XGETBV1, 3679 .features[FEAT_6_EAX] = 3680 CPUID_6_EAX_ARAT, 3681 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3682 MSR_VMX_BASIC_TRUE_CTLS, 3683 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3684 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3685 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3686 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3687 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3688 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3689 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3690 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3691 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3692 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3693 .features[FEAT_VMX_EXIT_CTLS] = 3694 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3695 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3696 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3697 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3698 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3699 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3700 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3701 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3702 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3703 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3704 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3705 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3706 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3707 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3708 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3709 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3710 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3711 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3712 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3713 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3714 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3715 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3716 .features[FEAT_VMX_SECONDARY_CTLS] = 3717 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3718 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3719 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3720 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3721 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3722 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3723 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3724 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3725 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3726 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3727 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3728 .xlevel = 0x80000008, 3729 .model_id = "Intel Atom Processor (SnowRidge)", 3730 .versions = (X86CPUVersionDefinition[]) { 3731 { .version = 1 }, 3732 { 3733 .version = 2, 3734 .props = (PropValue[]) { 3735 { "mpx", "off" }, 3736 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" }, 3737 { /* end of list */ }, 3738 }, 3739 }, 3740 { 3741 .version = 3, 3742 .note = "XSAVES, no MPX", 3743 .props = (PropValue[]) { 3744 { "xsaves", "on" }, 3745 { "vmx-xsaves", "on" }, 3746 { /* end of list */ }, 3747 }, 3748 }, 3749 { 3750 .version = 4, 3751 .note = "no split lock detect", 3752 .props = (PropValue[]) { 3753 { "split-lock-detect", "off" }, 3754 { /* end of list */ }, 3755 }, 3756 }, 3757 { /* end of list */ }, 3758 }, 3759 }, 3760 { 3761 .name = "KnightsMill", 3762 .level = 0xd, 3763 .vendor = CPUID_VENDOR_INTEL, 3764 .family = 6, 3765 .model = 133, 3766 .stepping = 0, 3767 .features[FEAT_1_EDX] = 3768 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | 3769 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 3770 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 3771 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 3772 CPUID_PSE | CPUID_DE | CPUID_FP87, 3773 .features[FEAT_1_ECX] = 3774 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3775 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3776 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3777 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3778 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3779 CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3780 .features[FEAT_8000_0001_EDX] = 3781 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3782 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3783 .features[FEAT_8000_0001_ECX] = 3784 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3785 .features[FEAT_7_0_EBX] = 3786 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 3787 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 3788 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F | 3789 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF | 3790 CPUID_7_0_EBX_AVX512ER, 3791 .features[FEAT_7_0_ECX] = 3792 CPUID_7_0_ECX_AVX512_VPOPCNTDQ, 3793 .features[FEAT_7_0_EDX] = 3794 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS, 3795 .features[FEAT_XSAVE] = 3796 CPUID_XSAVE_XSAVEOPT, 3797 .features[FEAT_6_EAX] = 3798 CPUID_6_EAX_ARAT, 3799 .xlevel = 0x80000008, 3800 .model_id = "Intel Xeon Phi Processor (Knights Mill)", 3801 }, 3802 { 3803 .name = "Opteron_G1", 3804 .level = 5, 3805 .vendor = CPUID_VENDOR_AMD, 3806 .family = 15, 3807 .model = 6, 3808 .stepping = 1, 3809 .features[FEAT_1_EDX] = 3810 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3811 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3812 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3813 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3814 CPUID_DE | CPUID_FP87, 3815 .features[FEAT_1_ECX] = 3816 CPUID_EXT_SSE3, 3817 .features[FEAT_8000_0001_EDX] = 3818 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3819 .xlevel = 0x80000008, 3820 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)", 3821 }, 3822 { 3823 .name = "Opteron_G2", 3824 .level = 5, 3825 .vendor = CPUID_VENDOR_AMD, 3826 .family = 15, 3827 .model = 6, 3828 .stepping = 1, 3829 .features[FEAT_1_EDX] = 3830 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3831 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3832 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3833 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3834 CPUID_DE | CPUID_FP87, 3835 .features[FEAT_1_ECX] = 3836 CPUID_EXT_CX16 | CPUID_EXT_SSE3, 3837 .features[FEAT_8000_0001_EDX] = 3838 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3839 .features[FEAT_8000_0001_ECX] = 3840 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 3841 .xlevel = 0x80000008, 3842 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)", 3843 }, 3844 { 3845 .name = "Opteron_G3", 3846 .level = 5, 3847 .vendor = CPUID_VENDOR_AMD, 3848 .family = 16, 3849 .model = 2, 3850 .stepping = 3, 3851 .features[FEAT_1_EDX] = 3852 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3853 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3854 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3855 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3856 CPUID_DE | CPUID_FP87, 3857 .features[FEAT_1_ECX] = 3858 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR | 3859 CPUID_EXT_SSE3, 3860 .features[FEAT_8000_0001_EDX] = 3861 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL | 3862 CPUID_EXT2_RDTSCP, 3863 .features[FEAT_8000_0001_ECX] = 3864 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | 3865 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 3866 .xlevel = 0x80000008, 3867 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)", 3868 }, 3869 { 3870 .name = "Opteron_G4", 3871 .level = 0xd, 3872 .vendor = CPUID_VENDOR_AMD, 3873 .family = 21, 3874 .model = 1, 3875 .stepping = 2, 3876 .features[FEAT_1_EDX] = 3877 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3878 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3879 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3880 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3881 CPUID_DE | CPUID_FP87, 3882 .features[FEAT_1_ECX] = 3883 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3884 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3885 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 3886 CPUID_EXT_SSE3, 3887 .features[FEAT_8000_0001_EDX] = 3888 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 3889 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 3890 .features[FEAT_8000_0001_ECX] = 3891 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 3892 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 3893 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 3894 CPUID_EXT3_LAHF_LM, 3895 .features[FEAT_SVM] = 3896 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 3897 /* no xsaveopt! */ 3898 .xlevel = 0x8000001A, 3899 .model_id = "AMD Opteron 62xx class CPU", 3900 }, 3901 { 3902 .name = "Opteron_G5", 3903 .level = 0xd, 3904 .vendor = CPUID_VENDOR_AMD, 3905 .family = 21, 3906 .model = 2, 3907 .stepping = 0, 3908 .features[FEAT_1_EDX] = 3909 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3910 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3911 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3912 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3913 CPUID_DE | CPUID_FP87, 3914 .features[FEAT_1_ECX] = 3915 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE | 3916 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 3917 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA | 3918 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 3919 .features[FEAT_8000_0001_EDX] = 3920 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 3921 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 3922 .features[FEAT_8000_0001_ECX] = 3923 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 3924 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 3925 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 3926 CPUID_EXT3_LAHF_LM, 3927 .features[FEAT_SVM] = 3928 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 3929 /* no xsaveopt! */ 3930 .xlevel = 0x8000001A, 3931 .model_id = "AMD Opteron 63xx class CPU", 3932 }, 3933 { 3934 .name = "EPYC", 3935 .level = 0xd, 3936 .vendor = CPUID_VENDOR_AMD, 3937 .family = 23, 3938 .model = 1, 3939 .stepping = 2, 3940 .features[FEAT_1_EDX] = 3941 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 3942 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 3943 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 3944 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 3945 CPUID_VME | CPUID_FP87, 3946 .features[FEAT_1_ECX] = 3947 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 3948 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 3949 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3950 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 3951 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 3952 .features[FEAT_8000_0001_EDX] = 3953 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 3954 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 3955 CPUID_EXT2_SYSCALL, 3956 .features[FEAT_8000_0001_ECX] = 3957 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 3958 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 3959 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 3960 CPUID_EXT3_TOPOEXT, 3961 .features[FEAT_7_0_EBX] = 3962 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 3963 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 3964 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 3965 CPUID_7_0_EBX_SHA_NI, 3966 .features[FEAT_XSAVE] = 3967 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3968 CPUID_XSAVE_XGETBV1, 3969 .features[FEAT_6_EAX] = 3970 CPUID_6_EAX_ARAT, 3971 .features[FEAT_SVM] = 3972 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 3973 .xlevel = 0x8000001E, 3974 .model_id = "AMD EPYC Processor", 3975 .cache_info = &epyc_cache_info, 3976 .versions = (X86CPUVersionDefinition[]) { 3977 { .version = 1 }, 3978 { 3979 .version = 2, 3980 .alias = "EPYC-IBPB", 3981 .props = (PropValue[]) { 3982 { "ibpb", "on" }, 3983 { "model-id", 3984 "AMD EPYC Processor (with IBPB)" }, 3985 { /* end of list */ } 3986 } 3987 }, 3988 { 3989 .version = 3, 3990 .props = (PropValue[]) { 3991 { "ibpb", "on" }, 3992 { "perfctr-core", "on" }, 3993 { "clzero", "on" }, 3994 { "xsaveerptr", "on" }, 3995 { "xsaves", "on" }, 3996 { "model-id", 3997 "AMD EPYC Processor" }, 3998 { /* end of list */ } 3999 } 4000 }, 4001 { /* end of list */ } 4002 } 4003 }, 4004 { 4005 .name = "Dhyana", 4006 .level = 0xd, 4007 .vendor = CPUID_VENDOR_HYGON, 4008 .family = 24, 4009 .model = 0, 4010 .stepping = 1, 4011 .features[FEAT_1_EDX] = 4012 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4013 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4014 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4015 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4016 CPUID_VME | CPUID_FP87, 4017 .features[FEAT_1_ECX] = 4018 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4019 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT | 4020 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4021 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4022 CPUID_EXT_MONITOR | CPUID_EXT_SSE3, 4023 .features[FEAT_8000_0001_EDX] = 4024 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4025 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4026 CPUID_EXT2_SYSCALL, 4027 .features[FEAT_8000_0001_ECX] = 4028 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4029 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4030 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4031 CPUID_EXT3_TOPOEXT, 4032 .features[FEAT_8000_0008_EBX] = 4033 CPUID_8000_0008_EBX_IBPB, 4034 .features[FEAT_7_0_EBX] = 4035 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4036 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4037 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT, 4038 /* XSAVES is added in version 2 */ 4039 .features[FEAT_XSAVE] = 4040 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4041 CPUID_XSAVE_XGETBV1, 4042 .features[FEAT_6_EAX] = 4043 CPUID_6_EAX_ARAT, 4044 .features[FEAT_SVM] = 4045 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4046 .xlevel = 0x8000001E, 4047 .model_id = "Hygon Dhyana Processor", 4048 .cache_info = &epyc_cache_info, 4049 .versions = (X86CPUVersionDefinition[]) { 4050 { .version = 1 }, 4051 { .version = 2, 4052 .note = "XSAVES", 4053 .props = (PropValue[]) { 4054 { "xsaves", "on" }, 4055 { /* end of list */ } 4056 }, 4057 }, 4058 { /* end of list */ } 4059 } 4060 }, 4061 { 4062 .name = "EPYC-Rome", 4063 .level = 0xd, 4064 .vendor = CPUID_VENDOR_AMD, 4065 .family = 23, 4066 .model = 49, 4067 .stepping = 0, 4068 .features[FEAT_1_EDX] = 4069 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4070 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4071 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4072 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4073 CPUID_VME | CPUID_FP87, 4074 .features[FEAT_1_ECX] = 4075 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4076 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4077 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4078 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4079 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4080 .features[FEAT_8000_0001_EDX] = 4081 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4082 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4083 CPUID_EXT2_SYSCALL, 4084 .features[FEAT_8000_0001_ECX] = 4085 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4086 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4087 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4088 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 4089 .features[FEAT_8000_0008_EBX] = 4090 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 4091 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 4092 CPUID_8000_0008_EBX_STIBP, 4093 .features[FEAT_7_0_EBX] = 4094 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4095 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4096 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4097 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB, 4098 .features[FEAT_7_0_ECX] = 4099 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID, 4100 .features[FEAT_XSAVE] = 4101 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4102 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4103 .features[FEAT_6_EAX] = 4104 CPUID_6_EAX_ARAT, 4105 .features[FEAT_SVM] = 4106 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4107 .xlevel = 0x8000001E, 4108 .model_id = "AMD EPYC-Rome Processor", 4109 .cache_info = &epyc_rome_cache_info, 4110 .versions = (X86CPUVersionDefinition[]) { 4111 { .version = 1 }, 4112 { 4113 .version = 2, 4114 .props = (PropValue[]) { 4115 { "ibrs", "on" }, 4116 { "amd-ssbd", "on" }, 4117 { /* end of list */ } 4118 } 4119 }, 4120 { /* end of list */ } 4121 } 4122 }, 4123 { 4124 .name = "EPYC-Milan", 4125 .level = 0xd, 4126 .vendor = CPUID_VENDOR_AMD, 4127 .family = 25, 4128 .model = 1, 4129 .stepping = 1, 4130 .features[FEAT_1_EDX] = 4131 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4132 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4133 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4134 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4135 CPUID_VME | CPUID_FP87, 4136 .features[FEAT_1_ECX] = 4137 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4138 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4139 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4140 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4141 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4142 CPUID_EXT_PCID, 4143 .features[FEAT_8000_0001_EDX] = 4144 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4145 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4146 CPUID_EXT2_SYSCALL, 4147 .features[FEAT_8000_0001_ECX] = 4148 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4149 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4150 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4151 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 4152 .features[FEAT_8000_0008_EBX] = 4153 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 4154 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 4155 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 4156 CPUID_8000_0008_EBX_AMD_SSBD, 4157 .features[FEAT_7_0_EBX] = 4158 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4159 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4160 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4161 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS | 4162 CPUID_7_0_EBX_INVPCID, 4163 .features[FEAT_7_0_ECX] = 4164 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU, 4165 .features[FEAT_7_0_EDX] = 4166 CPUID_7_0_EDX_FSRM, 4167 .features[FEAT_XSAVE] = 4168 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4169 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4170 .features[FEAT_6_EAX] = 4171 CPUID_6_EAX_ARAT, 4172 .features[FEAT_SVM] = 4173 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK, 4174 .xlevel = 0x8000001E, 4175 .model_id = "AMD EPYC-Milan Processor", 4176 .cache_info = &epyc_milan_cache_info, 4177 }, 4178 }; 4179 4180 /* 4181 * We resolve CPU model aliases using -v1 when using "-machine 4182 * none", but this is just for compatibility while libvirt isn't 4183 * adapted to resolve CPU model versions before creating VMs. 4184 * See "Runnability guarantee of CPU models" at 4185 * docs/about/deprecated.rst. 4186 */ 4187 X86CPUVersion default_cpu_version = 1; 4188 4189 void x86_cpu_set_default_version(X86CPUVersion version) 4190 { 4191 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */ 4192 assert(version != CPU_VERSION_AUTO); 4193 default_cpu_version = version; 4194 } 4195 4196 static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model) 4197 { 4198 int v = 0; 4199 const X86CPUVersionDefinition *vdef = 4200 x86_cpu_def_get_versions(model->cpudef); 4201 while (vdef->version) { 4202 v = vdef->version; 4203 vdef++; 4204 } 4205 return v; 4206 } 4207 4208 /* Return the actual version being used for a specific CPU model */ 4209 static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model) 4210 { 4211 X86CPUVersion v = model->version; 4212 if (v == CPU_VERSION_AUTO) { 4213 v = default_cpu_version; 4214 } 4215 if (v == CPU_VERSION_LATEST) { 4216 return x86_cpu_model_last_version(model); 4217 } 4218 return v; 4219 } 4220 4221 static Property max_x86_cpu_properties[] = { 4222 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true), 4223 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false), 4224 DEFINE_PROP_END_OF_LIST() 4225 }; 4226 4227 static void max_x86_cpu_class_init(ObjectClass *oc, void *data) 4228 { 4229 DeviceClass *dc = DEVICE_CLASS(oc); 4230 X86CPUClass *xcc = X86_CPU_CLASS(oc); 4231 4232 xcc->ordering = 9; 4233 4234 xcc->model_description = 4235 "Enables all features supported by the accelerator in the current host"; 4236 4237 device_class_set_props(dc, max_x86_cpu_properties); 4238 } 4239 4240 static void max_x86_cpu_initfn(Object *obj) 4241 { 4242 X86CPU *cpu = X86_CPU(obj); 4243 4244 /* We can't fill the features array here because we don't know yet if 4245 * "migratable" is true or false. 4246 */ 4247 cpu->max_features = true; 4248 object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort); 4249 4250 /* 4251 * these defaults are used for TCG and all other accelerators 4252 * besides KVM and HVF, which overwrite these values 4253 */ 4254 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD, 4255 &error_abort); 4256 #ifdef TARGET_X86_64 4257 object_property_set_int(OBJECT(cpu), "family", 15, &error_abort); 4258 object_property_set_int(OBJECT(cpu), "model", 107, &error_abort); 4259 object_property_set_int(OBJECT(cpu), "stepping", 1, &error_abort); 4260 #else 4261 object_property_set_int(OBJECT(cpu), "family", 6, &error_abort); 4262 object_property_set_int(OBJECT(cpu), "model", 6, &error_abort); 4263 object_property_set_int(OBJECT(cpu), "stepping", 3, &error_abort); 4264 #endif 4265 object_property_set_str(OBJECT(cpu), "model-id", 4266 "QEMU TCG CPU version " QEMU_HW_VERSION, 4267 &error_abort); 4268 } 4269 4270 static const TypeInfo max_x86_cpu_type_info = { 4271 .name = X86_CPU_TYPE_NAME("max"), 4272 .parent = TYPE_X86_CPU, 4273 .instance_init = max_x86_cpu_initfn, 4274 .class_init = max_x86_cpu_class_init, 4275 }; 4276 4277 static char *feature_word_description(FeatureWordInfo *f, uint32_t bit) 4278 { 4279 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD); 4280 4281 switch (f->type) { 4282 case CPUID_FEATURE_WORD: 4283 { 4284 const char *reg = get_register_name_32(f->cpuid.reg); 4285 assert(reg); 4286 return g_strdup_printf("CPUID.%02XH:%s", 4287 f->cpuid.eax, reg); 4288 } 4289 case MSR_FEATURE_WORD: 4290 return g_strdup_printf("MSR(%02XH)", 4291 f->msr.index); 4292 } 4293 4294 return NULL; 4295 } 4296 4297 static bool x86_cpu_have_filtered_features(X86CPU *cpu) 4298 { 4299 FeatureWord w; 4300 4301 for (w = 0; w < FEATURE_WORDS; w++) { 4302 if (cpu->filtered_features[w]) { 4303 return true; 4304 } 4305 } 4306 4307 return false; 4308 } 4309 4310 static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask, 4311 const char *verbose_prefix) 4312 { 4313 CPUX86State *env = &cpu->env; 4314 FeatureWordInfo *f = &feature_word_info[w]; 4315 int i; 4316 4317 if (!cpu->force_features) { 4318 env->features[w] &= ~mask; 4319 } 4320 cpu->filtered_features[w] |= mask; 4321 4322 if (!verbose_prefix) { 4323 return; 4324 } 4325 4326 for (i = 0; i < 64; ++i) { 4327 if ((1ULL << i) & mask) { 4328 g_autofree char *feat_word_str = feature_word_description(f, i); 4329 warn_report("%s: %s%s%s [bit %d]", 4330 verbose_prefix, 4331 feat_word_str, 4332 f->feat_names[i] ? "." : "", 4333 f->feat_names[i] ? f->feat_names[i] : "", i); 4334 } 4335 } 4336 } 4337 4338 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, 4339 const char *name, void *opaque, 4340 Error **errp) 4341 { 4342 X86CPU *cpu = X86_CPU(obj); 4343 CPUX86State *env = &cpu->env; 4344 int64_t value; 4345 4346 value = (env->cpuid_version >> 8) & 0xf; 4347 if (value == 0xf) { 4348 value += (env->cpuid_version >> 20) & 0xff; 4349 } 4350 visit_type_int(v, name, &value, errp); 4351 } 4352 4353 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, 4354 const char *name, void *opaque, 4355 Error **errp) 4356 { 4357 X86CPU *cpu = X86_CPU(obj); 4358 CPUX86State *env = &cpu->env; 4359 const int64_t min = 0; 4360 const int64_t max = 0xff + 0xf; 4361 int64_t value; 4362 4363 if (!visit_type_int(v, name, &value, errp)) { 4364 return; 4365 } 4366 if (value < min || value > max) { 4367 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 4368 name ? name : "null", value, min, max); 4369 return; 4370 } 4371 4372 env->cpuid_version &= ~0xff00f00; 4373 if (value > 0x0f) { 4374 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20); 4375 } else { 4376 env->cpuid_version |= value << 8; 4377 } 4378 } 4379 4380 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, 4381 const char *name, void *opaque, 4382 Error **errp) 4383 { 4384 X86CPU *cpu = X86_CPU(obj); 4385 CPUX86State *env = &cpu->env; 4386 int64_t value; 4387 4388 value = (env->cpuid_version >> 4) & 0xf; 4389 value |= ((env->cpuid_version >> 16) & 0xf) << 4; 4390 visit_type_int(v, name, &value, errp); 4391 } 4392 4393 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, 4394 const char *name, void *opaque, 4395 Error **errp) 4396 { 4397 X86CPU *cpu = X86_CPU(obj); 4398 CPUX86State *env = &cpu->env; 4399 const int64_t min = 0; 4400 const int64_t max = 0xff; 4401 int64_t value; 4402 4403 if (!visit_type_int(v, name, &value, errp)) { 4404 return; 4405 } 4406 if (value < min || value > max) { 4407 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 4408 name ? name : "null", value, min, max); 4409 return; 4410 } 4411 4412 env->cpuid_version &= ~0xf00f0; 4413 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16); 4414 } 4415 4416 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v, 4417 const char *name, void *opaque, 4418 Error **errp) 4419 { 4420 X86CPU *cpu = X86_CPU(obj); 4421 CPUX86State *env = &cpu->env; 4422 int64_t value; 4423 4424 value = env->cpuid_version & 0xf; 4425 visit_type_int(v, name, &value, errp); 4426 } 4427 4428 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v, 4429 const char *name, void *opaque, 4430 Error **errp) 4431 { 4432 X86CPU *cpu = X86_CPU(obj); 4433 CPUX86State *env = &cpu->env; 4434 const int64_t min = 0; 4435 const int64_t max = 0xf; 4436 int64_t value; 4437 4438 if (!visit_type_int(v, name, &value, errp)) { 4439 return; 4440 } 4441 if (value < min || value > max) { 4442 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 4443 name ? name : "null", value, min, max); 4444 return; 4445 } 4446 4447 env->cpuid_version &= ~0xf; 4448 env->cpuid_version |= value & 0xf; 4449 } 4450 4451 static char *x86_cpuid_get_vendor(Object *obj, Error **errp) 4452 { 4453 X86CPU *cpu = X86_CPU(obj); 4454 CPUX86State *env = &cpu->env; 4455 char *value; 4456 4457 value = g_malloc(CPUID_VENDOR_SZ + 1); 4458 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2, 4459 env->cpuid_vendor3); 4460 return value; 4461 } 4462 4463 static void x86_cpuid_set_vendor(Object *obj, const char *value, 4464 Error **errp) 4465 { 4466 X86CPU *cpu = X86_CPU(obj); 4467 CPUX86State *env = &cpu->env; 4468 int i; 4469 4470 if (strlen(value) != CPUID_VENDOR_SZ) { 4471 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value); 4472 return; 4473 } 4474 4475 env->cpuid_vendor1 = 0; 4476 env->cpuid_vendor2 = 0; 4477 env->cpuid_vendor3 = 0; 4478 for (i = 0; i < 4; i++) { 4479 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i); 4480 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i); 4481 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i); 4482 } 4483 } 4484 4485 static char *x86_cpuid_get_model_id(Object *obj, Error **errp) 4486 { 4487 X86CPU *cpu = X86_CPU(obj); 4488 CPUX86State *env = &cpu->env; 4489 char *value; 4490 int i; 4491 4492 value = g_malloc(48 + 1); 4493 for (i = 0; i < 48; i++) { 4494 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3)); 4495 } 4496 value[48] = '\0'; 4497 return value; 4498 } 4499 4500 static void x86_cpuid_set_model_id(Object *obj, const char *model_id, 4501 Error **errp) 4502 { 4503 X86CPU *cpu = X86_CPU(obj); 4504 CPUX86State *env = &cpu->env; 4505 int c, len, i; 4506 4507 if (model_id == NULL) { 4508 model_id = ""; 4509 } 4510 len = strlen(model_id); 4511 memset(env->cpuid_model, 0, 48); 4512 for (i = 0; i < 48; i++) { 4513 if (i >= len) { 4514 c = '\0'; 4515 } else { 4516 c = (uint8_t)model_id[i]; 4517 } 4518 env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); 4519 } 4520 } 4521 4522 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name, 4523 void *opaque, Error **errp) 4524 { 4525 X86CPU *cpu = X86_CPU(obj); 4526 int64_t value; 4527 4528 value = cpu->env.tsc_khz * 1000; 4529 visit_type_int(v, name, &value, errp); 4530 } 4531 4532 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name, 4533 void *opaque, Error **errp) 4534 { 4535 X86CPU *cpu = X86_CPU(obj); 4536 const int64_t min = 0; 4537 const int64_t max = INT64_MAX; 4538 int64_t value; 4539 4540 if (!visit_type_int(v, name, &value, errp)) { 4541 return; 4542 } 4543 if (value < min || value > max) { 4544 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 4545 name ? name : "null", value, min, max); 4546 return; 4547 } 4548 4549 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000; 4550 } 4551 4552 /* Generic getter for "feature-words" and "filtered-features" properties */ 4553 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, 4554 const char *name, void *opaque, 4555 Error **errp) 4556 { 4557 uint64_t *array = (uint64_t *)opaque; 4558 FeatureWord w; 4559 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { }; 4560 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { }; 4561 X86CPUFeatureWordInfoList *list = NULL; 4562 4563 for (w = 0; w < FEATURE_WORDS; w++) { 4564 FeatureWordInfo *wi = &feature_word_info[w]; 4565 /* 4566 * We didn't have MSR features when "feature-words" was 4567 * introduced. Therefore skipped other type entries. 4568 */ 4569 if (wi->type != CPUID_FEATURE_WORD) { 4570 continue; 4571 } 4572 X86CPUFeatureWordInfo *qwi = &word_infos[w]; 4573 qwi->cpuid_input_eax = wi->cpuid.eax; 4574 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx; 4575 qwi->cpuid_input_ecx = wi->cpuid.ecx; 4576 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum; 4577 qwi->features = array[w]; 4578 4579 /* List will be in reverse order, but order shouldn't matter */ 4580 list_entries[w].next = list; 4581 list_entries[w].value = &word_infos[w]; 4582 list = &list_entries[w]; 4583 } 4584 4585 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp); 4586 } 4587 4588 /* Convert all '_' in a feature string option name to '-', to make feature 4589 * name conform to QOM property naming rule, which uses '-' instead of '_'. 4590 */ 4591 static inline void feat2prop(char *s) 4592 { 4593 while ((s = strchr(s, '_'))) { 4594 *s = '-'; 4595 } 4596 } 4597 4598 /* Return the feature property name for a feature flag bit */ 4599 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr) 4600 { 4601 const char *name; 4602 /* XSAVE components are automatically enabled by other features, 4603 * so return the original feature name instead 4604 */ 4605 if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) { 4606 int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr; 4607 4608 if (comp < ARRAY_SIZE(x86_ext_save_areas) && 4609 x86_ext_save_areas[comp].bits) { 4610 w = x86_ext_save_areas[comp].feature; 4611 bitnr = ctz32(x86_ext_save_areas[comp].bits); 4612 } 4613 } 4614 4615 assert(bitnr < 64); 4616 assert(w < FEATURE_WORDS); 4617 name = feature_word_info[w].feat_names[bitnr]; 4618 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD)); 4619 return name; 4620 } 4621 4622 /* Compatibily hack to maintain legacy +-feat semantic, 4623 * where +-feat overwrites any feature set by 4624 * feat=on|feat even if the later is parsed after +-feat 4625 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled) 4626 */ 4627 static GList *plus_features, *minus_features; 4628 4629 static gint compare_string(gconstpointer a, gconstpointer b) 4630 { 4631 return g_strcmp0(a, b); 4632 } 4633 4634 /* Parse "+feature,-feature,feature=foo" CPU feature string 4635 */ 4636 static void x86_cpu_parse_featurestr(const char *typename, char *features, 4637 Error **errp) 4638 { 4639 char *featurestr; /* Single 'key=value" string being parsed */ 4640 static bool cpu_globals_initialized; 4641 bool ambiguous = false; 4642 4643 if (cpu_globals_initialized) { 4644 return; 4645 } 4646 cpu_globals_initialized = true; 4647 4648 if (!features) { 4649 return; 4650 } 4651 4652 for (featurestr = strtok(features, ","); 4653 featurestr; 4654 featurestr = strtok(NULL, ",")) { 4655 const char *name; 4656 const char *val = NULL; 4657 char *eq = NULL; 4658 char num[32]; 4659 GlobalProperty *prop; 4660 4661 /* Compatibility syntax: */ 4662 if (featurestr[0] == '+') { 4663 plus_features = g_list_append(plus_features, 4664 g_strdup(featurestr + 1)); 4665 continue; 4666 } else if (featurestr[0] == '-') { 4667 minus_features = g_list_append(minus_features, 4668 g_strdup(featurestr + 1)); 4669 continue; 4670 } 4671 4672 eq = strchr(featurestr, '='); 4673 if (eq) { 4674 *eq++ = 0; 4675 val = eq; 4676 } else { 4677 val = "on"; 4678 } 4679 4680 feat2prop(featurestr); 4681 name = featurestr; 4682 4683 if (g_list_find_custom(plus_features, name, compare_string)) { 4684 warn_report("Ambiguous CPU model string. " 4685 "Don't mix both \"+%s\" and \"%s=%s\"", 4686 name, name, val); 4687 ambiguous = true; 4688 } 4689 if (g_list_find_custom(minus_features, name, compare_string)) { 4690 warn_report("Ambiguous CPU model string. " 4691 "Don't mix both \"-%s\" and \"%s=%s\"", 4692 name, name, val); 4693 ambiguous = true; 4694 } 4695 4696 /* Special case: */ 4697 if (!strcmp(name, "tsc-freq")) { 4698 int ret; 4699 uint64_t tsc_freq; 4700 4701 ret = qemu_strtosz_metric(val, NULL, &tsc_freq); 4702 if (ret < 0 || tsc_freq > INT64_MAX) { 4703 error_setg(errp, "bad numerical value %s", val); 4704 return; 4705 } 4706 snprintf(num, sizeof(num), "%" PRId64, tsc_freq); 4707 val = num; 4708 name = "tsc-frequency"; 4709 } 4710 4711 prop = g_new0(typeof(*prop), 1); 4712 prop->driver = typename; 4713 prop->property = g_strdup(name); 4714 prop->value = g_strdup(val); 4715 qdev_prop_register_global(prop); 4716 } 4717 4718 if (ambiguous) { 4719 warn_report("Compatibility of ambiguous CPU model " 4720 "strings won't be kept on future QEMU versions"); 4721 } 4722 } 4723 4724 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose); 4725 4726 /* Build a list with the name of all features on a feature word array */ 4727 static void x86_cpu_list_feature_names(FeatureWordArray features, 4728 strList **list) 4729 { 4730 strList **tail = list; 4731 FeatureWord w; 4732 4733 for (w = 0; w < FEATURE_WORDS; w++) { 4734 uint64_t filtered = features[w]; 4735 int i; 4736 for (i = 0; i < 64; i++) { 4737 if (filtered & (1ULL << i)) { 4738 QAPI_LIST_APPEND(tail, g_strdup(x86_cpu_feature_name(w, i))); 4739 } 4740 } 4741 } 4742 } 4743 4744 static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v, 4745 const char *name, void *opaque, 4746 Error **errp) 4747 { 4748 X86CPU *xc = X86_CPU(obj); 4749 strList *result = NULL; 4750 4751 x86_cpu_list_feature_names(xc->filtered_features, &result); 4752 visit_type_strList(v, "unavailable-features", &result, errp); 4753 } 4754 4755 /* Check for missing features that may prevent the CPU class from 4756 * running using the current machine and accelerator. 4757 */ 4758 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc, 4759 strList **list) 4760 { 4761 strList **tail = list; 4762 X86CPU *xc; 4763 Error *err = NULL; 4764 4765 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 4766 QAPI_LIST_APPEND(tail, g_strdup("kvm")); 4767 return; 4768 } 4769 4770 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc))); 4771 4772 x86_cpu_expand_features(xc, &err); 4773 if (err) { 4774 /* Errors at x86_cpu_expand_features should never happen, 4775 * but in case it does, just report the model as not 4776 * runnable at all using the "type" property. 4777 */ 4778 QAPI_LIST_APPEND(tail, g_strdup("type")); 4779 error_free(err); 4780 } 4781 4782 x86_cpu_filter_features(xc, false); 4783 4784 x86_cpu_list_feature_names(xc->filtered_features, tail); 4785 4786 object_unref(OBJECT(xc)); 4787 } 4788 4789 /* Print all cpuid feature names in featureset 4790 */ 4791 static void listflags(GList *features) 4792 { 4793 size_t len = 0; 4794 GList *tmp; 4795 4796 for (tmp = features; tmp; tmp = tmp->next) { 4797 const char *name = tmp->data; 4798 if ((len + strlen(name) + 1) >= 75) { 4799 qemu_printf("\n"); 4800 len = 0; 4801 } 4802 qemu_printf("%s%s", len == 0 ? " " : " ", name); 4803 len += strlen(name) + 1; 4804 } 4805 qemu_printf("\n"); 4806 } 4807 4808 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */ 4809 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b) 4810 { 4811 ObjectClass *class_a = (ObjectClass *)a; 4812 ObjectClass *class_b = (ObjectClass *)b; 4813 X86CPUClass *cc_a = X86_CPU_CLASS(class_a); 4814 X86CPUClass *cc_b = X86_CPU_CLASS(class_b); 4815 int ret; 4816 4817 if (cc_a->ordering != cc_b->ordering) { 4818 ret = cc_a->ordering - cc_b->ordering; 4819 } else { 4820 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a); 4821 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b); 4822 ret = strcmp(name_a, name_b); 4823 } 4824 return ret; 4825 } 4826 4827 static GSList *get_sorted_cpu_model_list(void) 4828 { 4829 GSList *list = object_class_get_list(TYPE_X86_CPU, false); 4830 list = g_slist_sort(list, x86_cpu_list_compare); 4831 return list; 4832 } 4833 4834 static char *x86_cpu_class_get_model_id(X86CPUClass *xc) 4835 { 4836 Object *obj = object_new_with_class(OBJECT_CLASS(xc)); 4837 char *r = object_property_get_str(obj, "model-id", &error_abort); 4838 object_unref(obj); 4839 return r; 4840 } 4841 4842 static char *x86_cpu_class_get_alias_of(X86CPUClass *cc) 4843 { 4844 X86CPUVersion version; 4845 4846 if (!cc->model || !cc->model->is_alias) { 4847 return NULL; 4848 } 4849 version = x86_cpu_model_resolve_version(cc->model); 4850 if (version <= 0) { 4851 return NULL; 4852 } 4853 return x86_cpu_versioned_model_name(cc->model->cpudef, version); 4854 } 4855 4856 static void x86_cpu_list_entry(gpointer data, gpointer user_data) 4857 { 4858 ObjectClass *oc = data; 4859 X86CPUClass *cc = X86_CPU_CLASS(oc); 4860 g_autofree char *name = x86_cpu_class_get_model_name(cc); 4861 g_autofree char *desc = g_strdup(cc->model_description); 4862 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc); 4863 g_autofree char *model_id = x86_cpu_class_get_model_id(cc); 4864 4865 if (!desc && alias_of) { 4866 if (cc->model && cc->model->version == CPU_VERSION_AUTO) { 4867 desc = g_strdup("(alias configured by machine type)"); 4868 } else { 4869 desc = g_strdup_printf("(alias of %s)", alias_of); 4870 } 4871 } 4872 if (!desc && cc->model && cc->model->note) { 4873 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note); 4874 } 4875 if (!desc) { 4876 desc = g_strdup_printf("%s", model_id); 4877 } 4878 4879 qemu_printf("x86 %-20s %-58s\n", name, desc); 4880 } 4881 4882 /* list available CPU models and flags */ 4883 void x86_cpu_list(void) 4884 { 4885 int i, j; 4886 GSList *list; 4887 GList *names = NULL; 4888 4889 qemu_printf("Available CPUs:\n"); 4890 list = get_sorted_cpu_model_list(); 4891 g_slist_foreach(list, x86_cpu_list_entry, NULL); 4892 g_slist_free(list); 4893 4894 names = NULL; 4895 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) { 4896 FeatureWordInfo *fw = &feature_word_info[i]; 4897 for (j = 0; j < 64; j++) { 4898 if (fw->feat_names[j]) { 4899 names = g_list_append(names, (gpointer)fw->feat_names[j]); 4900 } 4901 } 4902 } 4903 4904 names = g_list_sort(names, (GCompareFunc)strcmp); 4905 4906 qemu_printf("\nRecognized CPUID flags:\n"); 4907 listflags(names); 4908 qemu_printf("\n"); 4909 g_list_free(names); 4910 } 4911 4912 static void x86_cpu_definition_entry(gpointer data, gpointer user_data) 4913 { 4914 ObjectClass *oc = data; 4915 X86CPUClass *cc = X86_CPU_CLASS(oc); 4916 CpuDefinitionInfoList **cpu_list = user_data; 4917 CpuDefinitionInfo *info; 4918 4919 info = g_malloc0(sizeof(*info)); 4920 info->name = x86_cpu_class_get_model_name(cc); 4921 x86_cpu_class_check_missing_features(cc, &info->unavailable_features); 4922 info->has_unavailable_features = true; 4923 info->q_typename = g_strdup(object_class_get_name(oc)); 4924 info->migration_safe = cc->migration_safe; 4925 info->has_migration_safe = true; 4926 info->q_static = cc->static_model; 4927 if (cc->model && cc->model->cpudef->deprecation_note) { 4928 info->deprecated = true; 4929 } else { 4930 info->deprecated = false; 4931 } 4932 /* 4933 * Old machine types won't report aliases, so that alias translation 4934 * doesn't break compatibility with previous QEMU versions. 4935 */ 4936 if (default_cpu_version != CPU_VERSION_LEGACY) { 4937 info->alias_of = x86_cpu_class_get_alias_of(cc); 4938 info->has_alias_of = !!info->alias_of; 4939 } 4940 4941 QAPI_LIST_PREPEND(*cpu_list, info); 4942 } 4943 4944 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 4945 { 4946 CpuDefinitionInfoList *cpu_list = NULL; 4947 GSList *list = get_sorted_cpu_model_list(); 4948 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list); 4949 g_slist_free(list); 4950 return cpu_list; 4951 } 4952 4953 static uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, 4954 bool migratable_only) 4955 { 4956 FeatureWordInfo *wi = &feature_word_info[w]; 4957 uint64_t r = 0; 4958 4959 if (kvm_enabled()) { 4960 switch (wi->type) { 4961 case CPUID_FEATURE_WORD: 4962 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax, 4963 wi->cpuid.ecx, 4964 wi->cpuid.reg); 4965 break; 4966 case MSR_FEATURE_WORD: 4967 r = kvm_arch_get_supported_msr_feature(kvm_state, 4968 wi->msr.index); 4969 break; 4970 } 4971 } else if (hvf_enabled()) { 4972 if (wi->type != CPUID_FEATURE_WORD) { 4973 return 0; 4974 } 4975 r = hvf_get_supported_cpuid(wi->cpuid.eax, 4976 wi->cpuid.ecx, 4977 wi->cpuid.reg); 4978 } else if (tcg_enabled()) { 4979 r = wi->tcg_features; 4980 } else { 4981 return ~0; 4982 } 4983 #ifndef TARGET_X86_64 4984 if (w == FEAT_8000_0001_EDX) { 4985 r &= ~CPUID_EXT2_LM; 4986 } 4987 #endif 4988 if (migratable_only) { 4989 r &= x86_cpu_get_migratable_flags(w); 4990 } 4991 return r; 4992 } 4993 4994 /* 4995 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 4996 */ 4997 void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) 4998 { 4999 PropValue *pv; 5000 for (pv = props; pv->prop; pv++) { 5001 if (!pv->value) { 5002 continue; 5003 } 5004 object_property_parse(OBJECT(cpu), pv->prop, pv->value, 5005 &error_abort); 5006 } 5007 } 5008 5009 /* 5010 * Apply properties for the CPU model version specified in model. 5011 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 5012 */ 5013 5014 static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model) 5015 { 5016 const X86CPUVersionDefinition *vdef; 5017 X86CPUVersion version = x86_cpu_model_resolve_version(model); 5018 5019 if (version == CPU_VERSION_LEGACY) { 5020 return; 5021 } 5022 5023 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 5024 PropValue *p; 5025 5026 for (p = vdef->props; p && p->prop; p++) { 5027 object_property_parse(OBJECT(cpu), p->prop, p->value, 5028 &error_abort); 5029 } 5030 5031 if (vdef->version == version) { 5032 break; 5033 } 5034 } 5035 5036 /* 5037 * If we reached the end of the list, version number was invalid 5038 */ 5039 assert(vdef->version == version); 5040 } 5041 5042 /* 5043 * Load data from X86CPUDefinition into a X86CPU object. 5044 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 5045 */ 5046 static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model) 5047 { 5048 const X86CPUDefinition *def = model->cpudef; 5049 CPUX86State *env = &cpu->env; 5050 FeatureWord w; 5051 5052 /*NOTE: any property set by this function should be returned by 5053 * x86_cpu_static_props(), so static expansion of 5054 * query-cpu-model-expansion is always complete. 5055 */ 5056 5057 /* CPU models only set _minimum_ values for level/xlevel: */ 5058 object_property_set_uint(OBJECT(cpu), "min-level", def->level, 5059 &error_abort); 5060 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel, 5061 &error_abort); 5062 5063 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort); 5064 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort); 5065 object_property_set_int(OBJECT(cpu), "stepping", def->stepping, 5066 &error_abort); 5067 object_property_set_str(OBJECT(cpu), "model-id", def->model_id, 5068 &error_abort); 5069 for (w = 0; w < FEATURE_WORDS; w++) { 5070 env->features[w] = def->features[w]; 5071 } 5072 5073 /* legacy-cache defaults to 'off' if CPU model provides cache info */ 5074 cpu->legacy_cache = !def->cache_info; 5075 5076 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR; 5077 5078 /* sysenter isn't supported in compatibility mode on AMD, 5079 * syscall isn't supported in compatibility mode on Intel. 5080 * Normally we advertise the actual CPU vendor, but you can 5081 * override this using the 'vendor' property if you want to use 5082 * KVM's sysenter/syscall emulation in compatibility mode and 5083 * when doing cross vendor migration 5084 */ 5085 5086 /* 5087 * vendor property is set here but then overloaded with the 5088 * host cpu vendor for KVM and HVF. 5089 */ 5090 object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort); 5091 5092 x86_cpu_apply_version_props(cpu, model); 5093 5094 /* 5095 * Properties in versioned CPU model are not user specified features. 5096 * We can simply clear env->user_features here since it will be filled later 5097 * in x86_cpu_expand_features() based on plus_features and minus_features. 5098 */ 5099 memset(&env->user_features, 0, sizeof(env->user_features)); 5100 } 5101 5102 static gchar *x86_gdb_arch_name(CPUState *cs) 5103 { 5104 #ifdef TARGET_X86_64 5105 return g_strdup("i386:x86-64"); 5106 #else 5107 return g_strdup("i386"); 5108 #endif 5109 } 5110 5111 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data) 5112 { 5113 X86CPUModel *model = data; 5114 X86CPUClass *xcc = X86_CPU_CLASS(oc); 5115 CPUClass *cc = CPU_CLASS(oc); 5116 5117 xcc->model = model; 5118 xcc->migration_safe = true; 5119 cc->deprecation_note = model->cpudef->deprecation_note; 5120 } 5121 5122 static void x86_register_cpu_model_type(const char *name, X86CPUModel *model) 5123 { 5124 g_autofree char *typename = x86_cpu_type_name(name); 5125 TypeInfo ti = { 5126 .name = typename, 5127 .parent = TYPE_X86_CPU, 5128 .class_init = x86_cpu_cpudef_class_init, 5129 .class_data = model, 5130 }; 5131 5132 type_register(&ti); 5133 } 5134 5135 5136 /* 5137 * register builtin_x86_defs; 5138 * "max", "base" and subclasses ("host") are not registered here. 5139 * See x86_cpu_register_types for all model registrations. 5140 */ 5141 static void x86_register_cpudef_types(const X86CPUDefinition *def) 5142 { 5143 X86CPUModel *m; 5144 const X86CPUVersionDefinition *vdef; 5145 5146 /* AMD aliases are handled at runtime based on CPUID vendor, so 5147 * they shouldn't be set on the CPU model table. 5148 */ 5149 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES)); 5150 /* catch mistakes instead of silently truncating model_id when too long */ 5151 assert(def->model_id && strlen(def->model_id) <= 48); 5152 5153 /* Unversioned model: */ 5154 m = g_new0(X86CPUModel, 1); 5155 m->cpudef = def; 5156 m->version = CPU_VERSION_AUTO; 5157 m->is_alias = true; 5158 x86_register_cpu_model_type(def->name, m); 5159 5160 /* Versioned models: */ 5161 5162 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) { 5163 X86CPUModel *m = g_new0(X86CPUModel, 1); 5164 g_autofree char *name = 5165 x86_cpu_versioned_model_name(def, vdef->version); 5166 m->cpudef = def; 5167 m->version = vdef->version; 5168 m->note = vdef->note; 5169 x86_register_cpu_model_type(name, m); 5170 5171 if (vdef->alias) { 5172 X86CPUModel *am = g_new0(X86CPUModel, 1); 5173 am->cpudef = def; 5174 am->version = vdef->version; 5175 am->is_alias = true; 5176 x86_register_cpu_model_type(vdef->alias, am); 5177 } 5178 } 5179 5180 } 5181 5182 uint32_t cpu_x86_virtual_addr_width(CPUX86State *env) 5183 { 5184 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) { 5185 return 57; /* 57 bits virtual */ 5186 } else { 5187 return 48; /* 48 bits virtual */ 5188 } 5189 } 5190 5191 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 5192 uint32_t *eax, uint32_t *ebx, 5193 uint32_t *ecx, uint32_t *edx) 5194 { 5195 X86CPU *cpu = env_archcpu(env); 5196 CPUState *cs = env_cpu(env); 5197 uint32_t die_offset; 5198 uint32_t limit; 5199 uint32_t signature[3]; 5200 X86CPUTopoInfo topo_info; 5201 5202 topo_info.dies_per_pkg = env->nr_dies; 5203 topo_info.cores_per_die = cs->nr_cores; 5204 topo_info.threads_per_core = cs->nr_threads; 5205 5206 /* Calculate & apply limits for different index ranges */ 5207 if (index >= 0xC0000000) { 5208 limit = env->cpuid_xlevel2; 5209 } else if (index >= 0x80000000) { 5210 limit = env->cpuid_xlevel; 5211 } else if (index >= 0x40000000) { 5212 limit = 0x40000001; 5213 } else { 5214 limit = env->cpuid_level; 5215 } 5216 5217 if (index > limit) { 5218 /* Intel documentation states that invalid EAX input will 5219 * return the same information as EAX=cpuid_level 5220 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID) 5221 */ 5222 index = env->cpuid_level; 5223 } 5224 5225 switch(index) { 5226 case 0: 5227 *eax = env->cpuid_level; 5228 *ebx = env->cpuid_vendor1; 5229 *edx = env->cpuid_vendor2; 5230 *ecx = env->cpuid_vendor3; 5231 break; 5232 case 1: 5233 *eax = env->cpuid_version; 5234 *ebx = (cpu->apic_id << 24) | 5235 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ 5236 *ecx = env->features[FEAT_1_ECX]; 5237 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) { 5238 *ecx |= CPUID_EXT_OSXSAVE; 5239 } 5240 *edx = env->features[FEAT_1_EDX]; 5241 if (cs->nr_cores * cs->nr_threads > 1) { 5242 *ebx |= (cs->nr_cores * cs->nr_threads) << 16; 5243 *edx |= CPUID_HT; 5244 } 5245 if (!cpu->enable_pmu) { 5246 *ecx &= ~CPUID_EXT_PDCM; 5247 } 5248 break; 5249 case 2: 5250 /* cache info: needed for Pentium Pro compatibility */ 5251 if (cpu->cache_info_passthrough) { 5252 host_cpuid(index, 0, eax, ebx, ecx, edx); 5253 break; 5254 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 5255 *eax = *ebx = *ecx = *edx = 0; 5256 break; 5257 } 5258 *eax = 1; /* Number of CPUID[EAX=2] calls required */ 5259 *ebx = 0; 5260 if (!cpu->enable_l3_cache) { 5261 *ecx = 0; 5262 } else { 5263 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache); 5264 } 5265 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) | 5266 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) | 5267 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache)); 5268 break; 5269 case 4: 5270 /* cache info: needed for Core compatibility */ 5271 if (cpu->cache_info_passthrough) { 5272 host_cpuid(index, count, eax, ebx, ecx, edx); 5273 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */ 5274 *eax &= ~0xFC000000; 5275 if ((*eax & 31) && cs->nr_cores > 1) { 5276 *eax |= (cs->nr_cores - 1) << 26; 5277 } 5278 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 5279 *eax = *ebx = *ecx = *edx = 0; 5280 } else { 5281 *eax = 0; 5282 switch (count) { 5283 case 0: /* L1 dcache info */ 5284 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, 5285 1, cs->nr_cores, 5286 eax, ebx, ecx, edx); 5287 break; 5288 case 1: /* L1 icache info */ 5289 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, 5290 1, cs->nr_cores, 5291 eax, ebx, ecx, edx); 5292 break; 5293 case 2: /* L2 cache info */ 5294 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, 5295 cs->nr_threads, cs->nr_cores, 5296 eax, ebx, ecx, edx); 5297 break; 5298 case 3: /* L3 cache info */ 5299 die_offset = apicid_die_offset(&topo_info); 5300 if (cpu->enable_l3_cache) { 5301 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, 5302 (1 << die_offset), cs->nr_cores, 5303 eax, ebx, ecx, edx); 5304 break; 5305 } 5306 /* fall through */ 5307 default: /* end of info */ 5308 *eax = *ebx = *ecx = *edx = 0; 5309 break; 5310 } 5311 } 5312 break; 5313 case 5: 5314 /* MONITOR/MWAIT Leaf */ 5315 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */ 5316 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */ 5317 *ecx = cpu->mwait.ecx; /* flags */ 5318 *edx = cpu->mwait.edx; /* mwait substates */ 5319 break; 5320 case 6: 5321 /* Thermal and Power Leaf */ 5322 *eax = env->features[FEAT_6_EAX]; 5323 *ebx = 0; 5324 *ecx = 0; 5325 *edx = 0; 5326 break; 5327 case 7: 5328 /* Structured Extended Feature Flags Enumeration Leaf */ 5329 if (count == 0) { 5330 /* Maximum ECX value for sub-leaves */ 5331 *eax = env->cpuid_level_func7; 5332 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */ 5333 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */ 5334 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) { 5335 *ecx |= CPUID_7_0_ECX_OSPKE; 5336 } 5337 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */ 5338 5339 /* 5340 * SGX cannot be emulated in software. If hardware does not 5341 * support enabling SGX and/or SGX flexible launch control, 5342 * then we need to update the VM's CPUID values accordingly. 5343 */ 5344 if ((*ebx & CPUID_7_0_EBX_SGX) && 5345 (!kvm_enabled() || 5346 !(kvm_arch_get_supported_cpuid(cs->kvm_state, 0x7, 0, R_EBX) & 5347 CPUID_7_0_EBX_SGX))) { 5348 *ebx &= ~CPUID_7_0_EBX_SGX; 5349 } 5350 5351 if ((*ecx & CPUID_7_0_ECX_SGX_LC) && 5352 (!(*ebx & CPUID_7_0_EBX_SGX) || !kvm_enabled() || 5353 !(kvm_arch_get_supported_cpuid(cs->kvm_state, 0x7, 0, R_ECX) & 5354 CPUID_7_0_ECX_SGX_LC))) { 5355 *ecx &= ~CPUID_7_0_ECX_SGX_LC; 5356 } 5357 } else if (count == 1) { 5358 *eax = env->features[FEAT_7_1_EAX]; 5359 *ebx = 0; 5360 *ecx = 0; 5361 *edx = 0; 5362 } else { 5363 *eax = 0; 5364 *ebx = 0; 5365 *ecx = 0; 5366 *edx = 0; 5367 } 5368 break; 5369 case 9: 5370 /* Direct Cache Access Information Leaf */ 5371 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */ 5372 *ebx = 0; 5373 *ecx = 0; 5374 *edx = 0; 5375 break; 5376 case 0xA: 5377 /* Architectural Performance Monitoring Leaf */ 5378 if (kvm_enabled() && cpu->enable_pmu) { 5379 KVMState *s = cs->kvm_state; 5380 5381 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX); 5382 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX); 5383 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX); 5384 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX); 5385 } else if (hvf_enabled() && cpu->enable_pmu) { 5386 *eax = hvf_get_supported_cpuid(0xA, count, R_EAX); 5387 *ebx = hvf_get_supported_cpuid(0xA, count, R_EBX); 5388 *ecx = hvf_get_supported_cpuid(0xA, count, R_ECX); 5389 *edx = hvf_get_supported_cpuid(0xA, count, R_EDX); 5390 } else { 5391 *eax = 0; 5392 *ebx = 0; 5393 *ecx = 0; 5394 *edx = 0; 5395 } 5396 break; 5397 case 0xB: 5398 /* Extended Topology Enumeration Leaf */ 5399 if (!cpu->enable_cpuid_0xb) { 5400 *eax = *ebx = *ecx = *edx = 0; 5401 break; 5402 } 5403 5404 *ecx = count & 0xff; 5405 *edx = cpu->apic_id; 5406 5407 switch (count) { 5408 case 0: 5409 *eax = apicid_core_offset(&topo_info); 5410 *ebx = cs->nr_threads; 5411 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT; 5412 break; 5413 case 1: 5414 *eax = apicid_pkg_offset(&topo_info); 5415 *ebx = cs->nr_cores * cs->nr_threads; 5416 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; 5417 break; 5418 default: 5419 *eax = 0; 5420 *ebx = 0; 5421 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID; 5422 } 5423 5424 assert(!(*eax & ~0x1f)); 5425 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 5426 break; 5427 case 0x1F: 5428 /* V2 Extended Topology Enumeration Leaf */ 5429 if (env->nr_dies < 2) { 5430 *eax = *ebx = *ecx = *edx = 0; 5431 break; 5432 } 5433 5434 *ecx = count & 0xff; 5435 *edx = cpu->apic_id; 5436 switch (count) { 5437 case 0: 5438 *eax = apicid_core_offset(&topo_info); 5439 *ebx = cs->nr_threads; 5440 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT; 5441 break; 5442 case 1: 5443 *eax = apicid_die_offset(&topo_info); 5444 *ebx = cs->nr_cores * cs->nr_threads; 5445 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; 5446 break; 5447 case 2: 5448 *eax = apicid_pkg_offset(&topo_info); 5449 *ebx = env->nr_dies * cs->nr_cores * cs->nr_threads; 5450 *ecx |= CPUID_TOPOLOGY_LEVEL_DIE; 5451 break; 5452 default: 5453 *eax = 0; 5454 *ebx = 0; 5455 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID; 5456 } 5457 assert(!(*eax & ~0x1f)); 5458 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 5459 break; 5460 case 0xD: { 5461 /* Processor Extended State */ 5462 *eax = 0; 5463 *ebx = 0; 5464 *ecx = 0; 5465 *edx = 0; 5466 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 5467 break; 5468 } 5469 5470 if (count == 0) { 5471 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu)); 5472 *eax = env->features[FEAT_XSAVE_COMP_LO]; 5473 *edx = env->features[FEAT_XSAVE_COMP_HI]; 5474 /* 5475 * The initial value of xcr0 and ebx == 0, On host without kvm 5476 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0 5477 * even through guest update xcr0, this will crash some legacy guest 5478 * (e.g., CentOS 6), So set ebx == ecx to workaroud it. 5479 */ 5480 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0); 5481 } else if (count == 1) { 5482 *eax = env->features[FEAT_XSAVE]; 5483 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) { 5484 if ((x86_cpu_xsave_components(cpu) >> count) & 1) { 5485 const ExtSaveArea *esa = &x86_ext_save_areas[count]; 5486 *eax = esa->size; 5487 *ebx = esa->offset; 5488 } 5489 } 5490 break; 5491 } 5492 case 0x12: 5493 #ifndef CONFIG_USER_ONLY 5494 if (!kvm_enabled() || 5495 !(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX)) { 5496 *eax = *ebx = *ecx = *edx = 0; 5497 break; 5498 } 5499 5500 /* 5501 * SGX sub-leafs CPUID.0x12.{0x2..N} enumerate EPC sections. Retrieve 5502 * the EPC properties, e.g. confidentiality and integrity, from the 5503 * host's first EPC section, i.e. assume there is one EPC section or 5504 * that all EPC sections have the same security properties. 5505 */ 5506 if (count > 1) { 5507 uint64_t epc_addr, epc_size; 5508 5509 if (sgx_epc_get_section(count - 2, &epc_addr, &epc_size)) { 5510 *eax = *ebx = *ecx = *edx = 0; 5511 break; 5512 } 5513 host_cpuid(index, 2, eax, ebx, ecx, edx); 5514 *eax = (uint32_t)(epc_addr & 0xfffff000) | 0x1; 5515 *ebx = (uint32_t)(epc_addr >> 32); 5516 *ecx = (uint32_t)(epc_size & 0xfffff000) | (*ecx & 0xf); 5517 *edx = (uint32_t)(epc_size >> 32); 5518 break; 5519 } 5520 5521 /* 5522 * SGX sub-leafs CPUID.0x12.{0x0,0x1} are heavily dependent on hardware 5523 * and KVM, i.e. QEMU cannot emulate features to override what KVM 5524 * supports. Features can be further restricted by userspace, but not 5525 * made more permissive. 5526 */ 5527 *eax = kvm_arch_get_supported_cpuid(cs->kvm_state, 0x12, count, R_EAX); 5528 *ebx = kvm_arch_get_supported_cpuid(cs->kvm_state, 0x12, count, R_EBX); 5529 *ecx = kvm_arch_get_supported_cpuid(cs->kvm_state, 0x12, count, R_ECX); 5530 *edx = kvm_arch_get_supported_cpuid(cs->kvm_state, 0x12, count, R_EDX); 5531 5532 if (count == 0) { 5533 *eax &= env->features[FEAT_SGX_12_0_EAX]; 5534 *ebx &= env->features[FEAT_SGX_12_0_EBX]; 5535 } else { 5536 *eax &= env->features[FEAT_SGX_12_1_EAX]; 5537 *ebx &= 0; /* ebx reserve */ 5538 *ecx &= env->features[FEAT_XSAVE_COMP_LO]; 5539 *edx &= env->features[FEAT_XSAVE_COMP_HI]; 5540 5541 /* FP and SSE are always allowed regardless of XSAVE/XCR0. */ 5542 *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK; 5543 5544 /* Access to PROVISIONKEY requires additional credentials. */ 5545 if ((*eax & (1U << 4)) && 5546 !kvm_enable_sgx_provisioning(cs->kvm_state)) { 5547 *eax &= ~(1U << 4); 5548 } 5549 } 5550 #endif 5551 break; 5552 case 0x14: { 5553 /* Intel Processor Trace Enumeration */ 5554 *eax = 0; 5555 *ebx = 0; 5556 *ecx = 0; 5557 *edx = 0; 5558 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) || 5559 !kvm_enabled()) { 5560 break; 5561 } 5562 5563 if (count == 0) { 5564 *eax = INTEL_PT_MAX_SUBLEAF; 5565 *ebx = INTEL_PT_MINIMAL_EBX; 5566 *ecx = INTEL_PT_MINIMAL_ECX; 5567 if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) { 5568 *ecx |= CPUID_14_0_ECX_LIP; 5569 } 5570 } else if (count == 1) { 5571 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM; 5572 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP; 5573 } 5574 break; 5575 } 5576 case 0x40000000: 5577 /* 5578 * CPUID code in kvm_arch_init_vcpu() ignores stuff 5579 * set here, but we restrict to TCG none the less. 5580 */ 5581 if (tcg_enabled() && cpu->expose_tcg) { 5582 memcpy(signature, "TCGTCGTCGTCG", 12); 5583 *eax = 0x40000001; 5584 *ebx = signature[0]; 5585 *ecx = signature[1]; 5586 *edx = signature[2]; 5587 } else { 5588 *eax = 0; 5589 *ebx = 0; 5590 *ecx = 0; 5591 *edx = 0; 5592 } 5593 break; 5594 case 0x40000001: 5595 *eax = 0; 5596 *ebx = 0; 5597 *ecx = 0; 5598 *edx = 0; 5599 break; 5600 case 0x80000000: 5601 *eax = env->cpuid_xlevel; 5602 *ebx = env->cpuid_vendor1; 5603 *edx = env->cpuid_vendor2; 5604 *ecx = env->cpuid_vendor3; 5605 break; 5606 case 0x80000001: 5607 *eax = env->cpuid_version; 5608 *ebx = 0; 5609 *ecx = env->features[FEAT_8000_0001_ECX]; 5610 *edx = env->features[FEAT_8000_0001_EDX]; 5611 5612 /* The Linux kernel checks for the CMPLegacy bit and 5613 * discards multiple thread information if it is set. 5614 * So don't set it here for Intel to make Linux guests happy. 5615 */ 5616 if (cs->nr_cores * cs->nr_threads > 1) { 5617 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 || 5618 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 || 5619 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) { 5620 *ecx |= 1 << 1; /* CmpLegacy bit */ 5621 } 5622 } 5623 break; 5624 case 0x80000002: 5625 case 0x80000003: 5626 case 0x80000004: 5627 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; 5628 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; 5629 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; 5630 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; 5631 break; 5632 case 0x80000005: 5633 /* cache info (L1 cache) */ 5634 if (cpu->cache_info_passthrough) { 5635 host_cpuid(index, 0, eax, ebx, ecx, edx); 5636 break; 5637 } 5638 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | 5639 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); 5640 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | 5641 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES); 5642 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache); 5643 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache); 5644 break; 5645 case 0x80000006: 5646 /* cache info (L2 cache) */ 5647 if (cpu->cache_info_passthrough) { 5648 host_cpuid(index, 0, eax, ebx, ecx, edx); 5649 break; 5650 } 5651 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | 5652 (L2_DTLB_2M_ENTRIES << 16) | 5653 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | 5654 (L2_ITLB_2M_ENTRIES); 5655 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | 5656 (L2_DTLB_4K_ENTRIES << 16) | 5657 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | 5658 (L2_ITLB_4K_ENTRIES); 5659 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache, 5660 cpu->enable_l3_cache ? 5661 env->cache_info_amd.l3_cache : NULL, 5662 ecx, edx); 5663 break; 5664 case 0x80000007: 5665 *eax = 0; 5666 *ebx = 0; 5667 *ecx = 0; 5668 *edx = env->features[FEAT_8000_0007_EDX]; 5669 break; 5670 case 0x80000008: 5671 /* virtual & phys address size in low 2 bytes. */ 5672 *eax = cpu->phys_bits; 5673 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 5674 /* 64 bit processor */ 5675 *eax |= (cpu_x86_virtual_addr_width(env) << 8); 5676 } 5677 *ebx = env->features[FEAT_8000_0008_EBX]; 5678 if (cs->nr_cores * cs->nr_threads > 1) { 5679 /* 5680 * Bits 15:12 is "The number of bits in the initial 5681 * Core::X86::Apic::ApicId[ApicId] value that indicate 5682 * thread ID within a package". 5683 * Bits 7:0 is "The number of threads in the package is NC+1" 5684 */ 5685 *ecx = (apicid_pkg_offset(&topo_info) << 12) | 5686 ((cs->nr_cores * cs->nr_threads) - 1); 5687 } else { 5688 *ecx = 0; 5689 } 5690 *edx = 0; 5691 break; 5692 case 0x8000000A: 5693 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 5694 *eax = 0x00000001; /* SVM Revision */ 5695 *ebx = 0x00000010; /* nr of ASIDs */ 5696 *ecx = 0; 5697 *edx = env->features[FEAT_SVM]; /* optional features */ 5698 } else { 5699 *eax = 0; 5700 *ebx = 0; 5701 *ecx = 0; 5702 *edx = 0; 5703 } 5704 break; 5705 case 0x8000001D: 5706 *eax = 0; 5707 if (cpu->cache_info_passthrough) { 5708 host_cpuid(index, count, eax, ebx, ecx, edx); 5709 break; 5710 } 5711 switch (count) { 5712 case 0: /* L1 dcache info */ 5713 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, 5714 &topo_info, eax, ebx, ecx, edx); 5715 break; 5716 case 1: /* L1 icache info */ 5717 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, 5718 &topo_info, eax, ebx, ecx, edx); 5719 break; 5720 case 2: /* L2 cache info */ 5721 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, 5722 &topo_info, eax, ebx, ecx, edx); 5723 break; 5724 case 3: /* L3 cache info */ 5725 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, 5726 &topo_info, eax, ebx, ecx, edx); 5727 break; 5728 default: /* end of info */ 5729 *eax = *ebx = *ecx = *edx = 0; 5730 break; 5731 } 5732 break; 5733 case 0x8000001E: 5734 if (cpu->core_id <= 255) { 5735 encode_topo_cpuid8000001e(cpu, &topo_info, eax, ebx, ecx, edx); 5736 } else { 5737 *eax = 0; 5738 *ebx = 0; 5739 *ecx = 0; 5740 *edx = 0; 5741 } 5742 break; 5743 case 0xC0000000: 5744 *eax = env->cpuid_xlevel2; 5745 *ebx = 0; 5746 *ecx = 0; 5747 *edx = 0; 5748 break; 5749 case 0xC0000001: 5750 /* Support for VIA CPU's CPUID instruction */ 5751 *eax = env->cpuid_version; 5752 *ebx = 0; 5753 *ecx = 0; 5754 *edx = env->features[FEAT_C000_0001_EDX]; 5755 break; 5756 case 0xC0000002: 5757 case 0xC0000003: 5758 case 0xC0000004: 5759 /* Reserved for the future, and now filled with zero */ 5760 *eax = 0; 5761 *ebx = 0; 5762 *ecx = 0; 5763 *edx = 0; 5764 break; 5765 case 0x8000001F: 5766 *eax = sev_enabled() ? 0x2 : 0; 5767 *eax |= sev_es_enabled() ? 0x8 : 0; 5768 *ebx = sev_get_cbit_position(); 5769 *ebx |= sev_get_reduced_phys_bits() << 6; 5770 *ecx = 0; 5771 *edx = 0; 5772 break; 5773 default: 5774 /* reserved values: zero */ 5775 *eax = 0; 5776 *ebx = 0; 5777 *ecx = 0; 5778 *edx = 0; 5779 break; 5780 } 5781 } 5782 5783 static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *env) 5784 { 5785 #ifndef CONFIG_USER_ONLY 5786 /* Those default values are defined in Skylake HW */ 5787 env->msr_ia32_sgxlepubkeyhash[0] = 0xa6053e051270b7acULL; 5788 env->msr_ia32_sgxlepubkeyhash[1] = 0x6cfbe8ba8b3b413dULL; 5789 env->msr_ia32_sgxlepubkeyhash[2] = 0xc4916d99f2b3735dULL; 5790 env->msr_ia32_sgxlepubkeyhash[3] = 0xd4f8c05909f9bb3bULL; 5791 #endif 5792 } 5793 5794 static void x86_cpu_reset(DeviceState *dev) 5795 { 5796 CPUState *s = CPU(dev); 5797 X86CPU *cpu = X86_CPU(s); 5798 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu); 5799 CPUX86State *env = &cpu->env; 5800 target_ulong cr4; 5801 uint64_t xcr0; 5802 int i; 5803 5804 xcc->parent_reset(dev); 5805 5806 memset(env, 0, offsetof(CPUX86State, end_reset_fields)); 5807 5808 env->old_exception = -1; 5809 5810 /* init to reset state */ 5811 env->int_ctl = 0; 5812 env->hflags2 |= HF2_GIF_MASK; 5813 env->hflags2 |= HF2_VGIF_MASK; 5814 env->hflags &= ~HF_GUEST_MASK; 5815 5816 cpu_x86_update_cr0(env, 0x60000010); 5817 env->a20_mask = ~0x0; 5818 env->smbase = 0x30000; 5819 env->msr_smi_count = 0; 5820 5821 env->idt.limit = 0xffff; 5822 env->gdt.limit = 0xffff; 5823 env->ldt.limit = 0xffff; 5824 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT); 5825 env->tr.limit = 0xffff; 5826 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); 5827 5828 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 5829 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | 5830 DESC_R_MASK | DESC_A_MASK); 5831 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, 5832 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 5833 DESC_A_MASK); 5834 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, 5835 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 5836 DESC_A_MASK); 5837 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, 5838 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 5839 DESC_A_MASK); 5840 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, 5841 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 5842 DESC_A_MASK); 5843 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, 5844 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 5845 DESC_A_MASK); 5846 5847 env->eip = 0xfff0; 5848 env->regs[R_EDX] = env->cpuid_version; 5849 5850 env->eflags = 0x2; 5851 5852 /* FPU init */ 5853 for (i = 0; i < 8; i++) { 5854 env->fptags[i] = 1; 5855 } 5856 cpu_set_fpuc(env, 0x37f); 5857 5858 env->mxcsr = 0x1f80; 5859 /* All units are in INIT state. */ 5860 env->xstate_bv = 0; 5861 5862 env->pat = 0x0007040600070406ULL; 5863 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; 5864 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) { 5865 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT; 5866 } 5867 5868 memset(env->dr, 0, sizeof(env->dr)); 5869 env->dr[6] = DR6_FIXED_1; 5870 env->dr[7] = DR7_FIXED_1; 5871 cpu_breakpoint_remove_all(s, BP_CPU); 5872 cpu_watchpoint_remove_all(s, BP_CPU); 5873 5874 cr4 = 0; 5875 xcr0 = XSTATE_FP_MASK; 5876 5877 #ifdef CONFIG_USER_ONLY 5878 /* Enable all the features for user-mode. */ 5879 if (env->features[FEAT_1_EDX] & CPUID_SSE) { 5880 xcr0 |= XSTATE_SSE_MASK; 5881 } 5882 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 5883 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 5884 if (env->features[esa->feature] & esa->bits) { 5885 xcr0 |= 1ull << i; 5886 } 5887 } 5888 5889 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) { 5890 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK; 5891 } 5892 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) { 5893 cr4 |= CR4_FSGSBASE_MASK; 5894 } 5895 #endif 5896 5897 env->xcr0 = xcr0; 5898 cpu_x86_update_cr4(env, cr4); 5899 5900 /* 5901 * SDM 11.11.5 requires: 5902 * - IA32_MTRR_DEF_TYPE MSR.E = 0 5903 * - IA32_MTRR_PHYSMASKn.V = 0 5904 * All other bits are undefined. For simplification, zero it all. 5905 */ 5906 env->mtrr_deftype = 0; 5907 memset(env->mtrr_var, 0, sizeof(env->mtrr_var)); 5908 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed)); 5909 5910 env->interrupt_injected = -1; 5911 env->exception_nr = -1; 5912 env->exception_pending = 0; 5913 env->exception_injected = 0; 5914 env->exception_has_payload = false; 5915 env->exception_payload = 0; 5916 env->nmi_injected = false; 5917 #if !defined(CONFIG_USER_ONLY) 5918 /* We hard-wire the BSP to the first CPU. */ 5919 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0); 5920 5921 s->halted = !cpu_is_bsp(cpu); 5922 5923 if (kvm_enabled()) { 5924 kvm_arch_reset_vcpu(cpu); 5925 } 5926 5927 x86_cpu_set_sgxlepubkeyhash(env); 5928 #endif 5929 } 5930 5931 static void mce_init(X86CPU *cpu) 5932 { 5933 CPUX86State *cenv = &cpu->env; 5934 unsigned int bank; 5935 5936 if (((cenv->cpuid_version >> 8) & 0xf) >= 6 5937 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == 5938 (CPUID_MCE | CPUID_MCA)) { 5939 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF | 5940 (cpu->enable_lmce ? MCG_LMCE_P : 0); 5941 cenv->mcg_ctl = ~(uint64_t)0; 5942 for (bank = 0; bank < MCE_BANKS_DEF; bank++) { 5943 cenv->mce_banks[bank * 4] = ~(uint64_t)0; 5944 } 5945 } 5946 } 5947 5948 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value) 5949 { 5950 if (*min < value) { 5951 *min = value; 5952 } 5953 } 5954 5955 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */ 5956 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w) 5957 { 5958 CPUX86State *env = &cpu->env; 5959 FeatureWordInfo *fi = &feature_word_info[w]; 5960 uint32_t eax = fi->cpuid.eax; 5961 uint32_t region = eax & 0xF0000000; 5962 5963 assert(feature_word_info[w].type == CPUID_FEATURE_WORD); 5964 if (!env->features[w]) { 5965 return; 5966 } 5967 5968 switch (region) { 5969 case 0x00000000: 5970 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax); 5971 break; 5972 case 0x80000000: 5973 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax); 5974 break; 5975 case 0xC0000000: 5976 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax); 5977 break; 5978 } 5979 5980 if (eax == 7) { 5981 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7, 5982 fi->cpuid.ecx); 5983 } 5984 } 5985 5986 /* Calculate XSAVE components based on the configured CPU feature flags */ 5987 static void x86_cpu_enable_xsave_components(X86CPU *cpu) 5988 { 5989 CPUX86State *env = &cpu->env; 5990 int i; 5991 uint64_t mask; 5992 5993 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 5994 env->features[FEAT_XSAVE_COMP_LO] = 0; 5995 env->features[FEAT_XSAVE_COMP_HI] = 0; 5996 return; 5997 } 5998 5999 mask = 0; 6000 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 6001 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 6002 if (env->features[esa->feature] & esa->bits) { 6003 mask |= (1ULL << i); 6004 } 6005 } 6006 6007 env->features[FEAT_XSAVE_COMP_LO] = mask; 6008 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32; 6009 } 6010 6011 /***** Steps involved on loading and filtering CPUID data 6012 * 6013 * When initializing and realizing a CPU object, the steps 6014 * involved in setting up CPUID data are: 6015 * 6016 * 1) Loading CPU model definition (X86CPUDefinition). This is 6017 * implemented by x86_cpu_load_model() and should be completely 6018 * transparent, as it is done automatically by instance_init. 6019 * No code should need to look at X86CPUDefinition structs 6020 * outside instance_init. 6021 * 6022 * 2) CPU expansion. This is done by realize before CPUID 6023 * filtering, and will make sure host/accelerator data is 6024 * loaded for CPU models that depend on host capabilities 6025 * (e.g. "host"). Done by x86_cpu_expand_features(). 6026 * 6027 * 3) CPUID filtering. This initializes extra data related to 6028 * CPUID, and checks if the host supports all capabilities 6029 * required by the CPU. Runnability of a CPU model is 6030 * determined at this step. Done by x86_cpu_filter_features(). 6031 * 6032 * Some operations don't require all steps to be performed. 6033 * More precisely: 6034 * 6035 * - CPU instance creation (instance_init) will run only CPU 6036 * model loading. CPU expansion can't run at instance_init-time 6037 * because host/accelerator data may be not available yet. 6038 * - CPU realization will perform both CPU model expansion and CPUID 6039 * filtering, and return an error in case one of them fails. 6040 * - query-cpu-definitions needs to run all 3 steps. It needs 6041 * to run CPUID filtering, as the 'unavailable-features' 6042 * field is set based on the filtering results. 6043 * - The query-cpu-model-expansion QMP command only needs to run 6044 * CPU model loading and CPU expansion. It should not filter 6045 * any CPUID data based on host capabilities. 6046 */ 6047 6048 /* Expand CPU configuration data, based on configured features 6049 * and host/accelerator capabilities when appropriate. 6050 */ 6051 void x86_cpu_expand_features(X86CPU *cpu, Error **errp) 6052 { 6053 CPUX86State *env = &cpu->env; 6054 FeatureWord w; 6055 int i; 6056 GList *l; 6057 6058 for (l = plus_features; l; l = l->next) { 6059 const char *prop = l->data; 6060 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) { 6061 return; 6062 } 6063 } 6064 6065 for (l = minus_features; l; l = l->next) { 6066 const char *prop = l->data; 6067 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) { 6068 return; 6069 } 6070 } 6071 6072 /*TODO: Now cpu->max_features doesn't overwrite features 6073 * set using QOM properties, and we can convert 6074 * plus_features & minus_features to global properties 6075 * inside x86_cpu_parse_featurestr() too. 6076 */ 6077 if (cpu->max_features) { 6078 for (w = 0; w < FEATURE_WORDS; w++) { 6079 /* Override only features that weren't set explicitly 6080 * by the user. 6081 */ 6082 env->features[w] |= 6083 x86_cpu_get_supported_feature_word(w, cpu->migratable) & 6084 ~env->user_features[w] & 6085 ~feature_word_info[w].no_autoenable_flags; 6086 } 6087 } 6088 6089 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) { 6090 FeatureDep *d = &feature_dependencies[i]; 6091 if (!(env->features[d->from.index] & d->from.mask)) { 6092 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask; 6093 6094 /* Not an error unless the dependent feature was added explicitly. */ 6095 mark_unavailable_features(cpu, d->to.index, 6096 unavailable_features & env->user_features[d->to.index], 6097 "This feature depends on other features that were not requested"); 6098 6099 env->features[d->to.index] &= ~unavailable_features; 6100 } 6101 } 6102 6103 if (!kvm_enabled() || !cpu->expose_kvm) { 6104 env->features[FEAT_KVM] = 0; 6105 } 6106 6107 x86_cpu_enable_xsave_components(cpu); 6108 6109 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */ 6110 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX); 6111 if (cpu->full_cpuid_auto_level) { 6112 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); 6113 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); 6114 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); 6115 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); 6116 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX); 6117 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); 6118 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); 6119 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); 6120 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX); 6121 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); 6122 x86_cpu_adjust_feat_level(cpu, FEAT_SVM); 6123 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); 6124 6125 /* Intel Processor Trace requires CPUID[0x14] */ 6126 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { 6127 if (cpu->intel_pt_auto_level) { 6128 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); 6129 } else if (cpu->env.cpuid_min_level < 0x14) { 6130 mark_unavailable_features(cpu, FEAT_7_0_EBX, 6131 CPUID_7_0_EBX_INTEL_PT, 6132 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\""); 6133 } 6134 } 6135 6136 /* 6137 * Intel CPU topology with multi-dies support requires CPUID[0x1F]. 6138 * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect 6139 * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless 6140 * cpu->vendor_cpuid_only has been unset for compatibility with older 6141 * machine types. 6142 */ 6143 if ((env->nr_dies > 1) && 6144 (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { 6145 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); 6146 } 6147 6148 /* SVM requires CPUID[0x8000000A] */ 6149 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 6150 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); 6151 } 6152 6153 /* SEV requires CPUID[0x8000001F] */ 6154 if (sev_enabled()) { 6155 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); 6156 } 6157 6158 /* SGX requires CPUID[0x12] for EPC enumeration */ 6159 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { 6160 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); 6161 } 6162 } 6163 6164 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */ 6165 if (env->cpuid_level_func7 == UINT32_MAX) { 6166 env->cpuid_level_func7 = env->cpuid_min_level_func7; 6167 } 6168 if (env->cpuid_level == UINT32_MAX) { 6169 env->cpuid_level = env->cpuid_min_level; 6170 } 6171 if (env->cpuid_xlevel == UINT32_MAX) { 6172 env->cpuid_xlevel = env->cpuid_min_xlevel; 6173 } 6174 if (env->cpuid_xlevel2 == UINT32_MAX) { 6175 env->cpuid_xlevel2 = env->cpuid_min_xlevel2; 6176 } 6177 6178 if (kvm_enabled()) { 6179 kvm_hyperv_expand_features(cpu, errp); 6180 } 6181 } 6182 6183 /* 6184 * Finishes initialization of CPUID data, filters CPU feature 6185 * words based on host availability of each feature. 6186 * 6187 * Returns: 0 if all flags are supported by the host, non-zero otherwise. 6188 */ 6189 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose) 6190 { 6191 CPUX86State *env = &cpu->env; 6192 FeatureWord w; 6193 const char *prefix = NULL; 6194 6195 if (verbose) { 6196 prefix = accel_uses_host_cpuid() 6197 ? "host doesn't support requested feature" 6198 : "TCG doesn't support requested feature"; 6199 } 6200 6201 for (w = 0; w < FEATURE_WORDS; w++) { 6202 uint64_t host_feat = 6203 x86_cpu_get_supported_feature_word(w, false); 6204 uint64_t requested_features = env->features[w]; 6205 uint64_t unavailable_features = requested_features & ~host_feat; 6206 mark_unavailable_features(cpu, w, unavailable_features, prefix); 6207 } 6208 6209 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && 6210 kvm_enabled()) { 6211 KVMState *s = CPU(cpu)->kvm_state; 6212 uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX); 6213 uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX); 6214 uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX); 6215 uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX); 6216 uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX); 6217 6218 if (!eax_0 || 6219 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) || 6220 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) || 6221 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) || 6222 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < 6223 INTEL_PT_ADDR_RANGES_NUM) || 6224 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) != 6225 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) || 6226 ((ecx_0 & CPUID_14_0_ECX_LIP) != 6227 (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) { 6228 /* 6229 * Processor Trace capabilities aren't configurable, so if the 6230 * host can't emulate the capabilities we report on 6231 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host. 6232 */ 6233 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix); 6234 } 6235 } 6236 } 6237 6238 static void x86_cpu_hyperv_realize(X86CPU *cpu) 6239 { 6240 size_t len; 6241 6242 /* Hyper-V vendor id */ 6243 if (!cpu->hyperv_vendor) { 6244 object_property_set_str(OBJECT(cpu), "hv-vendor-id", "Microsoft Hv", 6245 &error_abort); 6246 } 6247 len = strlen(cpu->hyperv_vendor); 6248 if (len > 12) { 6249 warn_report("hv-vendor-id truncated to 12 characters"); 6250 len = 12; 6251 } 6252 memset(cpu->hyperv_vendor_id, 0, 12); 6253 memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len); 6254 6255 /* 'Hv#1' interface identification*/ 6256 cpu->hyperv_interface_id[0] = 0x31237648; 6257 cpu->hyperv_interface_id[1] = 0; 6258 cpu->hyperv_interface_id[2] = 0; 6259 cpu->hyperv_interface_id[3] = 0; 6260 6261 /* Hypervisor implementation limits */ 6262 cpu->hyperv_limits[0] = 64; 6263 cpu->hyperv_limits[1] = 0; 6264 cpu->hyperv_limits[2] = 0; 6265 } 6266 6267 static void x86_cpu_realizefn(DeviceState *dev, Error **errp) 6268 { 6269 CPUState *cs = CPU(dev); 6270 X86CPU *cpu = X86_CPU(dev); 6271 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 6272 CPUX86State *env = &cpu->env; 6273 Error *local_err = NULL; 6274 static bool ht_warned; 6275 6276 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 6277 error_setg(errp, "apic-id property was not initialized properly"); 6278 return; 6279 } 6280 6281 /* 6282 * Process Hyper-V enlightenments. 6283 * Note: this currently has to happen before the expansion of CPU features. 6284 */ 6285 x86_cpu_hyperv_realize(cpu); 6286 6287 x86_cpu_expand_features(cpu, &local_err); 6288 if (local_err) { 6289 goto out; 6290 } 6291 6292 x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid); 6293 6294 if (cpu->enforce_cpuid && x86_cpu_have_filtered_features(cpu)) { 6295 error_setg(&local_err, 6296 accel_uses_host_cpuid() ? 6297 "Host doesn't support requested features" : 6298 "TCG doesn't support requested features"); 6299 goto out; 6300 } 6301 6302 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on 6303 * CPUID[1].EDX. 6304 */ 6305 if (IS_AMD_CPU(env)) { 6306 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES; 6307 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX] 6308 & CPUID_EXT2_AMD_ALIASES); 6309 } 6310 6311 x86_cpu_set_sgxlepubkeyhash(env); 6312 6313 /* 6314 * note: the call to the framework needs to happen after feature expansion, 6315 * but before the checks/modifications to ucode_rev, mwait, phys_bits. 6316 * These may be set by the accel-specific code, 6317 * and the results are subsequently checked / assumed in this function. 6318 */ 6319 cpu_exec_realizefn(cs, &local_err); 6320 if (local_err != NULL) { 6321 error_propagate(errp, local_err); 6322 return; 6323 } 6324 6325 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 6326 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 6327 error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name); 6328 goto out; 6329 } 6330 6331 if (cpu->ucode_rev == 0) { 6332 /* 6333 * The default is the same as KVM's. Note that this check 6334 * needs to happen after the evenual setting of ucode_rev in 6335 * accel-specific code in cpu_exec_realizefn. 6336 */ 6337 if (IS_AMD_CPU(env)) { 6338 cpu->ucode_rev = 0x01000065; 6339 } else { 6340 cpu->ucode_rev = 0x100000000ULL; 6341 } 6342 } 6343 6344 /* 6345 * mwait extended info: needed for Core compatibility 6346 * We always wake on interrupt even if host does not have the capability. 6347 * 6348 * requires the accel-specific code in cpu_exec_realizefn to 6349 * have already acquired the CPUID data into cpu->mwait. 6350 */ 6351 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; 6352 6353 /* For 64bit systems think about the number of physical bits to present. 6354 * ideally this should be the same as the host; anything other than matching 6355 * the host can cause incorrect guest behaviour. 6356 * QEMU used to pick the magic value of 40 bits that corresponds to 6357 * consumer AMD devices but nothing else. 6358 * 6359 * Note that this code assumes features expansion has already been done 6360 * (as it checks for CPUID_EXT2_LM), and also assumes that potential 6361 * phys_bits adjustments to match the host have been already done in 6362 * accel-specific code in cpu_exec_realizefn. 6363 */ 6364 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 6365 if (cpu->phys_bits && 6366 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || 6367 cpu->phys_bits < 32)) { 6368 error_setg(errp, "phys-bits should be between 32 and %u " 6369 " (but is %u)", 6370 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); 6371 return; 6372 } 6373 /* 6374 * 0 means it was not explicitly set by the user (or by machine 6375 * compat_props or by the host code in host-cpu.c). 6376 * In this case, the default is the value used by TCG (40). 6377 */ 6378 if (cpu->phys_bits == 0) { 6379 cpu->phys_bits = TCG_PHYS_ADDR_BITS; 6380 } 6381 } else { 6382 /* For 32 bit systems don't use the user set value, but keep 6383 * phys_bits consistent with what we tell the guest. 6384 */ 6385 if (cpu->phys_bits != 0) { 6386 error_setg(errp, "phys-bits is not user-configurable in 32 bit"); 6387 return; 6388 } 6389 6390 if (env->features[FEAT_1_EDX] & CPUID_PSE36) { 6391 cpu->phys_bits = 36; 6392 } else { 6393 cpu->phys_bits = 32; 6394 } 6395 } 6396 6397 /* Cache information initialization */ 6398 if (!cpu->legacy_cache) { 6399 if (!xcc->model || !xcc->model->cpudef->cache_info) { 6400 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 6401 error_setg(errp, 6402 "CPU model '%s' doesn't support legacy-cache=off", name); 6403 return; 6404 } 6405 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd = 6406 *xcc->model->cpudef->cache_info; 6407 } else { 6408 /* Build legacy cache information */ 6409 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache; 6410 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache; 6411 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2; 6412 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache; 6413 6414 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache; 6415 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache; 6416 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache; 6417 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache; 6418 6419 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd; 6420 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd; 6421 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd; 6422 env->cache_info_amd.l3_cache = &legacy_l3_cache; 6423 } 6424 6425 #ifndef CONFIG_USER_ONLY 6426 MachineState *ms = MACHINE(qdev_get_machine()); 6427 qemu_register_reset(x86_cpu_machine_reset_cb, cpu); 6428 6429 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { 6430 x86_cpu_apic_create(cpu, &local_err); 6431 if (local_err != NULL) { 6432 goto out; 6433 } 6434 } 6435 #endif 6436 6437 mce_init(cpu); 6438 6439 qemu_init_vcpu(cs); 6440 6441 /* 6442 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU 6443 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX 6444 * based on inputs (sockets,cores,threads), it is still better to give 6445 * users a warning. 6446 * 6447 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise 6448 * cs->nr_threads hasn't be populated yet and the checking is incorrect. 6449 */ 6450 if (IS_AMD_CPU(env) && 6451 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) && 6452 cs->nr_threads > 1 && !ht_warned) { 6453 warn_report("This family of AMD CPU doesn't support " 6454 "hyperthreading(%d)", 6455 cs->nr_threads); 6456 error_printf("Please configure -smp options properly" 6457 " or try enabling topoext feature.\n"); 6458 ht_warned = true; 6459 } 6460 6461 #ifndef CONFIG_USER_ONLY 6462 x86_cpu_apic_realize(cpu, &local_err); 6463 if (local_err != NULL) { 6464 goto out; 6465 } 6466 #endif /* !CONFIG_USER_ONLY */ 6467 cpu_reset(cs); 6468 6469 xcc->parent_realize(dev, &local_err); 6470 6471 out: 6472 if (local_err != NULL) { 6473 error_propagate(errp, local_err); 6474 return; 6475 } 6476 } 6477 6478 static void x86_cpu_unrealizefn(DeviceState *dev) 6479 { 6480 X86CPU *cpu = X86_CPU(dev); 6481 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 6482 6483 #ifndef CONFIG_USER_ONLY 6484 cpu_remove_sync(CPU(dev)); 6485 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev); 6486 #endif 6487 6488 if (cpu->apic_state) { 6489 object_unparent(OBJECT(cpu->apic_state)); 6490 cpu->apic_state = NULL; 6491 } 6492 6493 xcc->parent_unrealize(dev); 6494 } 6495 6496 typedef struct BitProperty { 6497 FeatureWord w; 6498 uint64_t mask; 6499 } BitProperty; 6500 6501 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name, 6502 void *opaque, Error **errp) 6503 { 6504 X86CPU *cpu = X86_CPU(obj); 6505 BitProperty *fp = opaque; 6506 uint64_t f = cpu->env.features[fp->w]; 6507 bool value = (f & fp->mask) == fp->mask; 6508 visit_type_bool(v, name, &value, errp); 6509 } 6510 6511 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name, 6512 void *opaque, Error **errp) 6513 { 6514 DeviceState *dev = DEVICE(obj); 6515 X86CPU *cpu = X86_CPU(obj); 6516 BitProperty *fp = opaque; 6517 bool value; 6518 6519 if (dev->realized) { 6520 qdev_prop_set_after_realize(dev, name, errp); 6521 return; 6522 } 6523 6524 if (!visit_type_bool(v, name, &value, errp)) { 6525 return; 6526 } 6527 6528 if (value) { 6529 cpu->env.features[fp->w] |= fp->mask; 6530 } else { 6531 cpu->env.features[fp->w] &= ~fp->mask; 6532 } 6533 cpu->env.user_features[fp->w] |= fp->mask; 6534 } 6535 6536 /* Register a boolean property to get/set a single bit in a uint32_t field. 6537 * 6538 * The same property name can be registered multiple times to make it affect 6539 * multiple bits in the same FeatureWord. In that case, the getter will return 6540 * true only if all bits are set. 6541 */ 6542 static void x86_cpu_register_bit_prop(X86CPUClass *xcc, 6543 const char *prop_name, 6544 FeatureWord w, 6545 int bitnr) 6546 { 6547 ObjectClass *oc = OBJECT_CLASS(xcc); 6548 BitProperty *fp; 6549 ObjectProperty *op; 6550 uint64_t mask = (1ULL << bitnr); 6551 6552 op = object_class_property_find(oc, prop_name); 6553 if (op) { 6554 fp = op->opaque; 6555 assert(fp->w == w); 6556 fp->mask |= mask; 6557 } else { 6558 fp = g_new0(BitProperty, 1); 6559 fp->w = w; 6560 fp->mask = mask; 6561 object_class_property_add(oc, prop_name, "bool", 6562 x86_cpu_get_bit_prop, 6563 x86_cpu_set_bit_prop, 6564 NULL, fp); 6565 } 6566 } 6567 6568 static void x86_cpu_register_feature_bit_props(X86CPUClass *xcc, 6569 FeatureWord w, 6570 int bitnr) 6571 { 6572 FeatureWordInfo *fi = &feature_word_info[w]; 6573 const char *name = fi->feat_names[bitnr]; 6574 6575 if (!name) { 6576 return; 6577 } 6578 6579 /* Property names should use "-" instead of "_". 6580 * Old names containing underscores are registered as aliases 6581 * using object_property_add_alias() 6582 */ 6583 assert(!strchr(name, '_')); 6584 /* aliases don't use "|" delimiters anymore, they are registered 6585 * manually using object_property_add_alias() */ 6586 assert(!strchr(name, '|')); 6587 x86_cpu_register_bit_prop(xcc, name, w, bitnr); 6588 } 6589 6590 static void x86_cpu_post_initfn(Object *obj) 6591 { 6592 accel_cpu_instance_init(CPU(obj)); 6593 } 6594 6595 static void x86_cpu_initfn(Object *obj) 6596 { 6597 X86CPU *cpu = X86_CPU(obj); 6598 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 6599 CPUX86State *env = &cpu->env; 6600 6601 env->nr_dies = 1; 6602 cpu_set_cpustate_pointers(cpu); 6603 6604 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", 6605 x86_cpu_get_feature_words, 6606 NULL, NULL, (void *)env->features); 6607 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo", 6608 x86_cpu_get_feature_words, 6609 NULL, NULL, (void *)cpu->filtered_features); 6610 6611 object_property_add_alias(obj, "sse3", obj, "pni"); 6612 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq"); 6613 object_property_add_alias(obj, "sse4-1", obj, "sse4.1"); 6614 object_property_add_alias(obj, "sse4-2", obj, "sse4.2"); 6615 object_property_add_alias(obj, "xd", obj, "nx"); 6616 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt"); 6617 object_property_add_alias(obj, "i64", obj, "lm"); 6618 6619 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl"); 6620 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust"); 6621 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt"); 6622 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm"); 6623 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy"); 6624 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr"); 6625 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core"); 6626 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb"); 6627 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay"); 6628 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu"); 6629 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf"); 6630 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int"); 6631 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time"); 6632 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi"); 6633 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt"); 6634 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control"); 6635 object_property_add_alias(obj, "svm_lock", obj, "svm-lock"); 6636 object_property_add_alias(obj, "nrip_save", obj, "nrip-save"); 6637 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale"); 6638 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean"); 6639 object_property_add_alias(obj, "pause_filter", obj, "pause-filter"); 6640 object_property_add_alias(obj, "sse4_1", obj, "sse4.1"); 6641 object_property_add_alias(obj, "sse4_2", obj, "sse4.2"); 6642 6643 object_property_add_alias(obj, "hv-apicv", obj, "hv-avic"); 6644 6645 if (xcc->model) { 6646 x86_cpu_load_model(cpu, xcc->model); 6647 } 6648 } 6649 6650 static int64_t x86_cpu_get_arch_id(CPUState *cs) 6651 { 6652 X86CPU *cpu = X86_CPU(cs); 6653 6654 return cpu->apic_id; 6655 } 6656 6657 #if !defined(CONFIG_USER_ONLY) 6658 static bool x86_cpu_get_paging_enabled(const CPUState *cs) 6659 { 6660 X86CPU *cpu = X86_CPU(cs); 6661 6662 return cpu->env.cr[0] & CR0_PG_MASK; 6663 } 6664 #endif /* !CONFIG_USER_ONLY */ 6665 6666 static void x86_cpu_set_pc(CPUState *cs, vaddr value) 6667 { 6668 X86CPU *cpu = X86_CPU(cs); 6669 6670 cpu->env.eip = value; 6671 } 6672 6673 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) 6674 { 6675 X86CPU *cpu = X86_CPU(cs); 6676 CPUX86State *env = &cpu->env; 6677 6678 #if !defined(CONFIG_USER_ONLY) 6679 if (interrupt_request & CPU_INTERRUPT_POLL) { 6680 return CPU_INTERRUPT_POLL; 6681 } 6682 #endif 6683 if (interrupt_request & CPU_INTERRUPT_SIPI) { 6684 return CPU_INTERRUPT_SIPI; 6685 } 6686 6687 if (env->hflags2 & HF2_GIF_MASK) { 6688 if ((interrupt_request & CPU_INTERRUPT_SMI) && 6689 !(env->hflags & HF_SMM_MASK)) { 6690 return CPU_INTERRUPT_SMI; 6691 } else if ((interrupt_request & CPU_INTERRUPT_NMI) && 6692 !(env->hflags2 & HF2_NMI_MASK)) { 6693 return CPU_INTERRUPT_NMI; 6694 } else if (interrupt_request & CPU_INTERRUPT_MCE) { 6695 return CPU_INTERRUPT_MCE; 6696 } else if ((interrupt_request & CPU_INTERRUPT_HARD) && 6697 (((env->hflags2 & HF2_VINTR_MASK) && 6698 (env->hflags2 & HF2_HIF_MASK)) || 6699 (!(env->hflags2 & HF2_VINTR_MASK) && 6700 (env->eflags & IF_MASK && 6701 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { 6702 return CPU_INTERRUPT_HARD; 6703 #if !defined(CONFIG_USER_ONLY) 6704 } else if (env->hflags2 & HF2_VGIF_MASK) { 6705 if((interrupt_request & CPU_INTERRUPT_VIRQ) && 6706 (env->eflags & IF_MASK) && 6707 !(env->hflags & HF_INHIBIT_IRQ_MASK)) { 6708 return CPU_INTERRUPT_VIRQ; 6709 } 6710 #endif 6711 } 6712 } 6713 6714 return 0; 6715 } 6716 6717 static bool x86_cpu_has_work(CPUState *cs) 6718 { 6719 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; 6720 } 6721 6722 static void x86_disas_set_info(CPUState *cs, disassemble_info *info) 6723 { 6724 X86CPU *cpu = X86_CPU(cs); 6725 CPUX86State *env = &cpu->env; 6726 6727 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64 6728 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386 6729 : bfd_mach_i386_i8086); 6730 info->print_insn = print_insn_i386; 6731 6732 info->cap_arch = CS_ARCH_X86; 6733 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64 6734 : env->hflags & HF_CS32_MASK ? CS_MODE_32 6735 : CS_MODE_16); 6736 info->cap_insn_unit = 1; 6737 info->cap_insn_split = 8; 6738 } 6739 6740 void x86_update_hflags(CPUX86State *env) 6741 { 6742 uint32_t hflags; 6743 #define HFLAG_COPY_MASK \ 6744 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ 6745 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ 6746 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ 6747 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) 6748 6749 hflags = env->hflags & HFLAG_COPY_MASK; 6750 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; 6751 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); 6752 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & 6753 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); 6754 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); 6755 6756 if (env->cr[4] & CR4_OSFXSR_MASK) { 6757 hflags |= HF_OSFXSR_MASK; 6758 } 6759 6760 if (env->efer & MSR_EFER_LMA) { 6761 hflags |= HF_LMA_MASK; 6762 } 6763 6764 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { 6765 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 6766 } else { 6767 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> 6768 (DESC_B_SHIFT - HF_CS32_SHIFT); 6769 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> 6770 (DESC_B_SHIFT - HF_SS32_SHIFT); 6771 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || 6772 !(hflags & HF_CS32_MASK)) { 6773 hflags |= HF_ADDSEG_MASK; 6774 } else { 6775 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | 6776 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; 6777 } 6778 } 6779 env->hflags = hflags; 6780 } 6781 6782 static Property x86_cpu_properties[] = { 6783 #ifdef CONFIG_USER_ONLY 6784 /* apic_id = 0 by default for *-user, see commit 9886e834 */ 6785 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0), 6786 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), 6787 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), 6788 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), 6789 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), 6790 #else 6791 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), 6792 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), 6793 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), 6794 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), 6795 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), 6796 #endif 6797 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), 6798 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), 6799 6800 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts, 6801 HYPERV_SPINLOCK_NEVER_NOTIFY), 6802 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features, 6803 HYPERV_FEAT_RELAXED, 0), 6804 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features, 6805 HYPERV_FEAT_VAPIC, 0), 6806 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features, 6807 HYPERV_FEAT_TIME, 0), 6808 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features, 6809 HYPERV_FEAT_CRASH, 0), 6810 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features, 6811 HYPERV_FEAT_RESET, 0), 6812 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features, 6813 HYPERV_FEAT_VPINDEX, 0), 6814 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features, 6815 HYPERV_FEAT_RUNTIME, 0), 6816 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features, 6817 HYPERV_FEAT_SYNIC, 0), 6818 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features, 6819 HYPERV_FEAT_STIMER, 0), 6820 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features, 6821 HYPERV_FEAT_FREQUENCIES, 0), 6822 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features, 6823 HYPERV_FEAT_REENLIGHTENMENT, 0), 6824 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features, 6825 HYPERV_FEAT_TLBFLUSH, 0), 6826 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features, 6827 HYPERV_FEAT_EVMCS, 0), 6828 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features, 6829 HYPERV_FEAT_IPI, 0), 6830 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features, 6831 HYPERV_FEAT_STIMER_DIRECT, 0), 6832 DEFINE_PROP_BIT64("hv-avic", X86CPU, hyperv_features, 6833 HYPERV_FEAT_AVIC, 0), 6834 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU, 6835 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF), 6836 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false), 6837 DEFINE_PROP_BOOL("hv-enforce-cpuid", X86CPU, hyperv_enforce_cpuid, false), 6838 6839 /* WS2008R2 identify by default */ 6840 DEFINE_PROP_UINT32("hv-version-id-build", X86CPU, hyperv_ver_id_build, 6841 0x3839), 6842 DEFINE_PROP_UINT16("hv-version-id-major", X86CPU, hyperv_ver_id_major, 6843 0x000A), 6844 DEFINE_PROP_UINT16("hv-version-id-minor", X86CPU, hyperv_ver_id_minor, 6845 0x0000), 6846 DEFINE_PROP_UINT32("hv-version-id-spack", X86CPU, hyperv_ver_id_sp, 0), 6847 DEFINE_PROP_UINT8("hv-version-id-sbranch", X86CPU, hyperv_ver_id_sb, 0), 6848 DEFINE_PROP_UINT32("hv-version-id-snumber", X86CPU, hyperv_ver_id_sn, 0), 6849 6850 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true), 6851 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), 6852 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false), 6853 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), 6854 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0), 6855 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), 6856 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0), 6857 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), 6858 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7, 6859 UINT32_MAX), 6860 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX), 6861 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX), 6862 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX), 6863 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0), 6864 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0), 6865 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), 6866 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), 6867 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), 6868 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), 6869 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), 6870 DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true), 6871 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), 6872 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), 6873 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration, 6874 false), 6875 DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU, kvm_pv_enforce_cpuid, 6876 false), 6877 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true), 6878 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true), 6879 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count, 6880 true), 6881 /* 6882 * lecacy_cache defaults to true unless the CPU model provides its 6883 * own cache information (see x86_cpu_load_def()). 6884 */ 6885 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true), 6886 6887 /* 6888 * From "Requirements for Implementing the Microsoft 6889 * Hypervisor Interface": 6890 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 6891 * 6892 * "Starting with Windows Server 2012 and Windows 8, if 6893 * CPUID.40000005.EAX contains a value of -1, Windows assumes that 6894 * the hypervisor imposes no specific limit to the number of VPs. 6895 * In this case, Windows Server 2012 guest VMs may use more than 6896 * 64 VPs, up to the maximum supported number of processors applicable 6897 * to the specific Windows version being used." 6898 */ 6899 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1), 6900 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only, 6901 false), 6902 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, 6903 true), 6904 DEFINE_PROP_END_OF_LIST() 6905 }; 6906 6907 #ifndef CONFIG_USER_ONLY 6908 #include "hw/core/sysemu-cpu-ops.h" 6909 6910 static const struct SysemuCPUOps i386_sysemu_ops = { 6911 .get_memory_mapping = x86_cpu_get_memory_mapping, 6912 .get_paging_enabled = x86_cpu_get_paging_enabled, 6913 .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug, 6914 .asidx_from_attrs = x86_asidx_from_attrs, 6915 .get_crash_info = x86_cpu_get_crash_info, 6916 .write_elf32_note = x86_cpu_write_elf32_note, 6917 .write_elf64_note = x86_cpu_write_elf64_note, 6918 .write_elf32_qemunote = x86_cpu_write_elf32_qemunote, 6919 .write_elf64_qemunote = x86_cpu_write_elf64_qemunote, 6920 .legacy_vmsd = &vmstate_x86_cpu, 6921 }; 6922 #endif 6923 6924 static void x86_cpu_common_class_init(ObjectClass *oc, void *data) 6925 { 6926 X86CPUClass *xcc = X86_CPU_CLASS(oc); 6927 CPUClass *cc = CPU_CLASS(oc); 6928 DeviceClass *dc = DEVICE_CLASS(oc); 6929 FeatureWord w; 6930 6931 device_class_set_parent_realize(dc, x86_cpu_realizefn, 6932 &xcc->parent_realize); 6933 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn, 6934 &xcc->parent_unrealize); 6935 device_class_set_props(dc, x86_cpu_properties); 6936 6937 device_class_set_parent_reset(dc, x86_cpu_reset, &xcc->parent_reset); 6938 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; 6939 6940 cc->class_by_name = x86_cpu_class_by_name; 6941 cc->parse_features = x86_cpu_parse_featurestr; 6942 cc->has_work = x86_cpu_has_work; 6943 cc->dump_state = x86_cpu_dump_state; 6944 cc->set_pc = x86_cpu_set_pc; 6945 cc->gdb_read_register = x86_cpu_gdb_read_register; 6946 cc->gdb_write_register = x86_cpu_gdb_write_register; 6947 cc->get_arch_id = x86_cpu_get_arch_id; 6948 6949 #ifndef CONFIG_USER_ONLY 6950 cc->sysemu_ops = &i386_sysemu_ops; 6951 #endif /* !CONFIG_USER_ONLY */ 6952 6953 cc->gdb_arch_name = x86_gdb_arch_name; 6954 #ifdef TARGET_X86_64 6955 cc->gdb_core_xml_file = "i386-64bit.xml"; 6956 cc->gdb_num_core_regs = 66; 6957 #else 6958 cc->gdb_core_xml_file = "i386-32bit.xml"; 6959 cc->gdb_num_core_regs = 50; 6960 #endif 6961 cc->disas_set_info = x86_disas_set_info; 6962 6963 dc->user_creatable = true; 6964 6965 object_class_property_add(oc, "family", "int", 6966 x86_cpuid_version_get_family, 6967 x86_cpuid_version_set_family, NULL, NULL); 6968 object_class_property_add(oc, "model", "int", 6969 x86_cpuid_version_get_model, 6970 x86_cpuid_version_set_model, NULL, NULL); 6971 object_class_property_add(oc, "stepping", "int", 6972 x86_cpuid_version_get_stepping, 6973 x86_cpuid_version_set_stepping, NULL, NULL); 6974 object_class_property_add_str(oc, "vendor", 6975 x86_cpuid_get_vendor, 6976 x86_cpuid_set_vendor); 6977 object_class_property_add_str(oc, "model-id", 6978 x86_cpuid_get_model_id, 6979 x86_cpuid_set_model_id); 6980 object_class_property_add(oc, "tsc-frequency", "int", 6981 x86_cpuid_get_tsc_freq, 6982 x86_cpuid_set_tsc_freq, NULL, NULL); 6983 /* 6984 * The "unavailable-features" property has the same semantics as 6985 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions" 6986 * QMP command: they list the features that would have prevented the 6987 * CPU from running if the "enforce" flag was set. 6988 */ 6989 object_class_property_add(oc, "unavailable-features", "strList", 6990 x86_cpu_get_unavailable_features, 6991 NULL, NULL, NULL); 6992 6993 #if !defined(CONFIG_USER_ONLY) 6994 object_class_property_add(oc, "crash-information", "GuestPanicInformation", 6995 x86_cpu_get_crash_info_qom, NULL, NULL, NULL); 6996 #endif 6997 6998 for (w = 0; w < FEATURE_WORDS; w++) { 6999 int bitnr; 7000 for (bitnr = 0; bitnr < 64; bitnr++) { 7001 x86_cpu_register_feature_bit_props(xcc, w, bitnr); 7002 } 7003 } 7004 } 7005 7006 static const TypeInfo x86_cpu_type_info = { 7007 .name = TYPE_X86_CPU, 7008 .parent = TYPE_CPU, 7009 .instance_size = sizeof(X86CPU), 7010 .instance_init = x86_cpu_initfn, 7011 .instance_post_init = x86_cpu_post_initfn, 7012 7013 .abstract = true, 7014 .class_size = sizeof(X86CPUClass), 7015 .class_init = x86_cpu_common_class_init, 7016 }; 7017 7018 /* "base" CPU model, used by query-cpu-model-expansion */ 7019 static void x86_cpu_base_class_init(ObjectClass *oc, void *data) 7020 { 7021 X86CPUClass *xcc = X86_CPU_CLASS(oc); 7022 7023 xcc->static_model = true; 7024 xcc->migration_safe = true; 7025 xcc->model_description = "base CPU model type with no features enabled"; 7026 xcc->ordering = 8; 7027 } 7028 7029 static const TypeInfo x86_base_cpu_type_info = { 7030 .name = X86_CPU_TYPE_NAME("base"), 7031 .parent = TYPE_X86_CPU, 7032 .class_init = x86_cpu_base_class_init, 7033 }; 7034 7035 static void x86_cpu_register_types(void) 7036 { 7037 int i; 7038 7039 type_register_static(&x86_cpu_type_info); 7040 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { 7041 x86_register_cpudef_types(&builtin_x86_defs[i]); 7042 } 7043 type_register_static(&max_x86_cpu_type_info); 7044 type_register_static(&x86_base_cpu_type_info); 7045 } 7046 7047 type_init(x86_cpu_register_types) 7048