1 /* 2 * QEMU KVM support 3 * 4 * Copyright (C) 2006-2008 Qumranet Technologies 5 * Copyright IBM, Corp. 2008 6 * 7 * Authors: 8 * Anthony Liguori <aliguori@us.ibm.com> 9 * 10 * This work is licensed under the terms of the GNU GPL, version 2 or later. 11 * See the COPYING file in the top-level directory. 12 * 13 */ 14 15 #include "qemu/osdep.h" 16 #include "qapi/qapi-events-run-state.h" 17 #include "qapi/error.h" 18 #include "qapi/visitor.h" 19 #include <sys/ioctl.h> 20 #include <sys/utsname.h> 21 #include <sys/syscall.h> 22 23 #include <linux/kvm.h> 24 #include "standard-headers/asm-x86/kvm_para.h" 25 #include "hw/xen/interface/arch-x86/cpuid.h" 26 27 #include "cpu.h" 28 #include "host-cpu.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/hw_accel.h" 31 #include "sysemu/kvm_int.h" 32 #include "sysemu/runstate.h" 33 #include "kvm_i386.h" 34 #include "sev.h" 35 #include "xen-emu.h" 36 #include "hyperv.h" 37 #include "hyperv-proto.h" 38 39 #include "exec/gdbstub.h" 40 #include "qemu/host-utils.h" 41 #include "qemu/main-loop.h" 42 #include "qemu/ratelimit.h" 43 #include "qemu/config-file.h" 44 #include "qemu/error-report.h" 45 #include "qemu/memalign.h" 46 #include "hw/i386/x86.h" 47 #include "hw/i386/kvm/xen_evtchn.h" 48 #include "hw/i386/pc.h" 49 #include "hw/i386/apic.h" 50 #include "hw/i386/apic_internal.h" 51 #include "hw/i386/apic-msidef.h" 52 #include "hw/i386/intel_iommu.h" 53 #include "hw/i386/x86-iommu.h" 54 #include "hw/i386/e820_memory_layout.h" 55 56 #include "hw/xen/xen.h" 57 58 #include "hw/pci/pci.h" 59 #include "hw/pci/msi.h" 60 #include "hw/pci/msix.h" 61 #include "migration/blocker.h" 62 #include "exec/memattrs.h" 63 #include "trace.h" 64 65 #include CONFIG_DEVICES 66 67 //#define DEBUG_KVM 68 69 #ifdef DEBUG_KVM 70 #define DPRINTF(fmt, ...) \ 71 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) 72 #else 73 #define DPRINTF(fmt, ...) \ 74 do { } while (0) 75 #endif 76 77 /* From arch/x86/kvm/lapic.h */ 78 #define KVM_APIC_BUS_CYCLE_NS 1 79 #define KVM_APIC_BUS_FREQUENCY (1000000000ULL / KVM_APIC_BUS_CYCLE_NS) 80 81 #define MSR_KVM_WALL_CLOCK 0x11 82 #define MSR_KVM_SYSTEM_TIME 0x12 83 84 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus 85 * 255 kvm_msr_entry structs */ 86 #define MSR_BUF_SIZE 4096 87 88 static void kvm_init_msrs(X86CPU *cpu); 89 90 const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 91 KVM_CAP_INFO(SET_TSS_ADDR), 92 KVM_CAP_INFO(EXT_CPUID), 93 KVM_CAP_INFO(MP_STATE), 94 KVM_CAP_INFO(SIGNAL_MSI), 95 KVM_CAP_INFO(IRQ_ROUTING), 96 KVM_CAP_INFO(DEBUGREGS), 97 KVM_CAP_INFO(XSAVE), 98 KVM_CAP_INFO(VCPU_EVENTS), 99 KVM_CAP_INFO(X86_ROBUST_SINGLESTEP), 100 KVM_CAP_INFO(MCE), 101 KVM_CAP_INFO(ADJUST_CLOCK), 102 KVM_CAP_INFO(SET_IDENTITY_MAP_ADDR), 103 KVM_CAP_LAST_INFO 104 }; 105 106 static bool has_msr_star; 107 static bool has_msr_hsave_pa; 108 static bool has_msr_tsc_aux; 109 static bool has_msr_tsc_adjust; 110 static bool has_msr_tsc_deadline; 111 static bool has_msr_feature_control; 112 static bool has_msr_misc_enable; 113 static bool has_msr_smbase; 114 static bool has_msr_bndcfgs; 115 static int lm_capable_kernel; 116 static bool has_msr_hv_hypercall; 117 static bool has_msr_hv_crash; 118 static bool has_msr_hv_reset; 119 static bool has_msr_hv_vpindex; 120 static bool hv_vpindex_settable; 121 static bool has_msr_hv_runtime; 122 static bool has_msr_hv_synic; 123 static bool has_msr_hv_stimer; 124 static bool has_msr_hv_frequencies; 125 static bool has_msr_hv_reenlightenment; 126 static bool has_msr_hv_syndbg_options; 127 static bool has_msr_xss; 128 static bool has_msr_umwait; 129 static bool has_msr_spec_ctrl; 130 static bool has_tsc_scale_msr; 131 static bool has_msr_tsx_ctrl; 132 static bool has_msr_virt_ssbd; 133 static bool has_msr_smi_count; 134 static bool has_msr_arch_capabs; 135 static bool has_msr_core_capabs; 136 static bool has_msr_vmx_vmfunc; 137 static bool has_msr_ucode_rev; 138 static bool has_msr_vmx_procbased_ctls2; 139 static bool has_msr_perf_capabs; 140 static bool has_msr_pkrs; 141 142 static uint32_t has_architectural_pmu_version; 143 static uint32_t num_architectural_pmu_gp_counters; 144 static uint32_t num_architectural_pmu_fixed_counters; 145 146 static int has_xsave2; 147 static int has_xcrs; 148 static int has_sregs2; 149 static int has_exception_payload; 150 static int has_triple_fault_event; 151 152 static bool has_msr_mcg_ext_ctl; 153 154 static struct kvm_cpuid2 *cpuid_cache; 155 static struct kvm_cpuid2 *hv_cpuid_cache; 156 static struct kvm_msr_list *kvm_feature_msrs; 157 158 static KVMMSRHandlers msr_handlers[KVM_MSR_FILTER_MAX_RANGES]; 159 160 #define BUS_LOCK_SLICE_TIME 1000000000ULL /* ns */ 161 static RateLimit bus_lock_ratelimit_ctrl; 162 static int kvm_get_one_msr(X86CPU *cpu, int index, uint64_t *value); 163 164 bool kvm_has_smm(void) 165 { 166 return kvm_vm_check_extension(kvm_state, KVM_CAP_X86_SMM); 167 } 168 169 bool kvm_has_adjust_clock_stable(void) 170 { 171 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK); 172 173 return (ret & KVM_CLOCK_TSC_STABLE); 174 } 175 176 bool kvm_has_exception_payload(void) 177 { 178 return has_exception_payload; 179 } 180 181 static bool kvm_x2apic_api_set_flags(uint64_t flags) 182 { 183 KVMState *s = KVM_STATE(current_accel()); 184 185 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags); 186 } 187 188 #define MEMORIZE(fn, _result) \ 189 ({ \ 190 static bool _memorized; \ 191 \ 192 if (_memorized) { \ 193 return _result; \ 194 } \ 195 _memorized = true; \ 196 _result = fn; \ 197 }) 198 199 static bool has_x2apic_api; 200 201 bool kvm_has_x2apic_api(void) 202 { 203 return has_x2apic_api; 204 } 205 206 bool kvm_enable_x2apic(void) 207 { 208 return MEMORIZE( 209 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS | 210 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK), 211 has_x2apic_api); 212 } 213 214 bool kvm_hv_vpindex_settable(void) 215 { 216 return hv_vpindex_settable; 217 } 218 219 static int kvm_get_tsc(CPUState *cs) 220 { 221 X86CPU *cpu = X86_CPU(cs); 222 CPUX86State *env = &cpu->env; 223 uint64_t value; 224 int ret; 225 226 if (env->tsc_valid) { 227 return 0; 228 } 229 230 env->tsc_valid = !runstate_is_running(); 231 232 ret = kvm_get_one_msr(cpu, MSR_IA32_TSC, &value); 233 if (ret < 0) { 234 return ret; 235 } 236 237 env->tsc = value; 238 return 0; 239 } 240 241 static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg) 242 { 243 kvm_get_tsc(cpu); 244 } 245 246 void kvm_synchronize_all_tsc(void) 247 { 248 CPUState *cpu; 249 250 if (kvm_enabled()) { 251 CPU_FOREACH(cpu) { 252 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL); 253 } 254 } 255 } 256 257 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max) 258 { 259 struct kvm_cpuid2 *cpuid; 260 int r, size; 261 262 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries); 263 cpuid = g_malloc0(size); 264 cpuid->nent = max; 265 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid); 266 if (r == 0 && cpuid->nent >= max) { 267 r = -E2BIG; 268 } 269 if (r < 0) { 270 if (r == -E2BIG) { 271 g_free(cpuid); 272 return NULL; 273 } else { 274 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n", 275 strerror(-r)); 276 exit(1); 277 } 278 } 279 return cpuid; 280 } 281 282 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough 283 * for all entries. 284 */ 285 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s) 286 { 287 struct kvm_cpuid2 *cpuid; 288 int max = 1; 289 290 if (cpuid_cache != NULL) { 291 return cpuid_cache; 292 } 293 while ((cpuid = try_get_cpuid(s, max)) == NULL) { 294 max *= 2; 295 } 296 cpuid_cache = cpuid; 297 return cpuid; 298 } 299 300 static bool host_tsx_broken(void) 301 { 302 int family, model, stepping;\ 303 char vendor[CPUID_VENDOR_SZ + 1]; 304 305 host_cpu_vendor_fms(vendor, &family, &model, &stepping); 306 307 /* Check if we are running on a Haswell host known to have broken TSX */ 308 return !strcmp(vendor, CPUID_VENDOR_INTEL) && 309 (family == 6) && 310 ((model == 63 && stepping < 4) || 311 model == 60 || model == 69 || model == 70); 312 } 313 314 /* Returns the value for a specific register on the cpuid entry 315 */ 316 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg) 317 { 318 uint32_t ret = 0; 319 switch (reg) { 320 case R_EAX: 321 ret = entry->eax; 322 break; 323 case R_EBX: 324 ret = entry->ebx; 325 break; 326 case R_ECX: 327 ret = entry->ecx; 328 break; 329 case R_EDX: 330 ret = entry->edx; 331 break; 332 } 333 return ret; 334 } 335 336 /* Find matching entry for function/index on kvm_cpuid2 struct 337 */ 338 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid, 339 uint32_t function, 340 uint32_t index) 341 { 342 int i; 343 for (i = 0; i < cpuid->nent; ++i) { 344 if (cpuid->entries[i].function == function && 345 cpuid->entries[i].index == index) { 346 return &cpuid->entries[i]; 347 } 348 } 349 /* not found: */ 350 return NULL; 351 } 352 353 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function, 354 uint32_t index, int reg) 355 { 356 struct kvm_cpuid2 *cpuid; 357 uint32_t ret = 0; 358 uint32_t cpuid_1_edx, unused; 359 uint64_t bitmask; 360 361 cpuid = get_supported_cpuid(s); 362 363 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index); 364 if (entry) { 365 ret = cpuid_entry_get_reg(entry, reg); 366 } 367 368 /* Fixups for the data returned by KVM, below */ 369 370 if (function == 1 && reg == R_EDX) { 371 /* KVM before 2.6.30 misreports the following features */ 372 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA; 373 /* KVM never reports CPUID_HT but QEMU can support when vcpus > 1 */ 374 ret |= CPUID_HT; 375 } else if (function == 1 && reg == R_ECX) { 376 /* We can set the hypervisor flag, even if KVM does not return it on 377 * GET_SUPPORTED_CPUID 378 */ 379 ret |= CPUID_EXT_HYPERVISOR; 380 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it 381 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER, 382 * and the irqchip is in the kernel. 383 */ 384 if (kvm_irqchip_in_kernel() && 385 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) { 386 ret |= CPUID_EXT_TSC_DEADLINE_TIMER; 387 } 388 389 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled 390 * without the in-kernel irqchip 391 */ 392 if (!kvm_irqchip_in_kernel()) { 393 ret &= ~CPUID_EXT_X2APIC; 394 } 395 396 if (enable_cpu_pm) { 397 int disable_exits = kvm_check_extension(s, 398 KVM_CAP_X86_DISABLE_EXITS); 399 400 if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) { 401 ret |= CPUID_EXT_MONITOR; 402 } 403 } 404 } else if (function == 6 && reg == R_EAX) { 405 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */ 406 } else if (function == 7 && index == 0 && reg == R_EBX) { 407 /* Not new instructions, just an optimization. */ 408 uint32_t ebx; 409 host_cpuid(7, 0, &unused, &ebx, &unused, &unused); 410 ret |= ebx & CPUID_7_0_EBX_ERMS; 411 412 if (host_tsx_broken()) { 413 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE); 414 } 415 } else if (function == 7 && index == 0 && reg == R_EDX) { 416 /* Not new instructions, just an optimization. */ 417 uint32_t edx; 418 host_cpuid(7, 0, &unused, &unused, &unused, &edx); 419 ret |= edx & CPUID_7_0_EDX_FSRM; 420 421 /* 422 * Linux v4.17-v4.20 incorrectly return ARCH_CAPABILITIES on SVM hosts. 423 * We can detect the bug by checking if MSR_IA32_ARCH_CAPABILITIES is 424 * returned by KVM_GET_MSR_INDEX_LIST. 425 */ 426 if (!has_msr_arch_capabs) { 427 ret &= ~CPUID_7_0_EDX_ARCH_CAPABILITIES; 428 } 429 } else if (function == 7 && index == 1 && reg == R_EAX) { 430 /* Not new instructions, just an optimization. */ 431 uint32_t eax; 432 host_cpuid(7, 1, &eax, &unused, &unused, &unused); 433 ret |= eax & (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC); 434 } else if (function == 7 && index == 2 && reg == R_EDX) { 435 uint32_t edx; 436 host_cpuid(7, 2, &unused, &unused, &unused, &edx); 437 ret |= edx & CPUID_7_2_EDX_MCDT_NO; 438 } else if (function == 0xd && index == 0 && 439 (reg == R_EAX || reg == R_EDX)) { 440 /* 441 * The value returned by KVM_GET_SUPPORTED_CPUID does not include 442 * features that still have to be enabled with the arch_prctl 443 * system call. QEMU needs the full value, which is retrieved 444 * with KVM_GET_DEVICE_ATTR. 445 */ 446 struct kvm_device_attr attr = { 447 .group = 0, 448 .attr = KVM_X86_XCOMP_GUEST_SUPP, 449 .addr = (unsigned long) &bitmask 450 }; 451 452 bool sys_attr = kvm_check_extension(s, KVM_CAP_SYS_ATTRIBUTES); 453 if (!sys_attr) { 454 return ret; 455 } 456 457 int rc = kvm_ioctl(s, KVM_GET_DEVICE_ATTR, &attr); 458 if (rc < 0) { 459 if (rc != -ENXIO) { 460 warn_report("KVM_GET_DEVICE_ATTR(0, KVM_X86_XCOMP_GUEST_SUPP) " 461 "error: %d", rc); 462 } 463 return ret; 464 } 465 ret = (reg == R_EAX) ? bitmask : bitmask >> 32; 466 } else if (function == 0x80000001 && reg == R_ECX) { 467 /* 468 * It's safe to enable TOPOEXT even if it's not returned by 469 * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows 470 * us to keep CPU models including TOPOEXT runnable on older kernels. 471 */ 472 ret |= CPUID_EXT3_TOPOEXT; 473 } else if (function == 0x80000001 && reg == R_EDX) { 474 /* On Intel, kvm returns cpuid according to the Intel spec, 475 * so add missing bits according to the AMD spec: 476 */ 477 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX); 478 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES; 479 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) { 480 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't 481 * be enabled without the in-kernel irqchip 482 */ 483 if (!kvm_irqchip_in_kernel()) { 484 ret &= ~(1U << KVM_FEATURE_PV_UNHALT); 485 } 486 if (kvm_irqchip_is_split()) { 487 ret |= 1U << KVM_FEATURE_MSI_EXT_DEST_ID; 488 } 489 } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) { 490 ret |= 1U << KVM_HINTS_REALTIME; 491 } 492 493 return ret; 494 } 495 496 uint64_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index) 497 { 498 struct { 499 struct kvm_msrs info; 500 struct kvm_msr_entry entries[1]; 501 } msr_data = {}; 502 uint64_t value; 503 uint32_t ret, can_be_one, must_be_one; 504 505 if (kvm_feature_msrs == NULL) { /* Host doesn't support feature MSRs */ 506 return 0; 507 } 508 509 /* Check if requested MSR is supported feature MSR */ 510 int i; 511 for (i = 0; i < kvm_feature_msrs->nmsrs; i++) 512 if (kvm_feature_msrs->indices[i] == index) { 513 break; 514 } 515 if (i == kvm_feature_msrs->nmsrs) { 516 return 0; /* if the feature MSR is not supported, simply return 0 */ 517 } 518 519 msr_data.info.nmsrs = 1; 520 msr_data.entries[0].index = index; 521 522 ret = kvm_ioctl(s, KVM_GET_MSRS, &msr_data); 523 if (ret != 1) { 524 error_report("KVM get MSR (index=0x%x) feature failed, %s", 525 index, strerror(-ret)); 526 exit(1); 527 } 528 529 value = msr_data.entries[0].data; 530 switch (index) { 531 case MSR_IA32_VMX_PROCBASED_CTLS2: 532 if (!has_msr_vmx_procbased_ctls2) { 533 /* KVM forgot to add these bits for some time, do this ourselves. */ 534 if (kvm_arch_get_supported_cpuid(s, 0xD, 1, R_ECX) & 535 CPUID_XSAVE_XSAVES) { 536 value |= (uint64_t)VMX_SECONDARY_EXEC_XSAVES << 32; 537 } 538 if (kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX) & 539 CPUID_EXT_RDRAND) { 540 value |= (uint64_t)VMX_SECONDARY_EXEC_RDRAND_EXITING << 32; 541 } 542 if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) & 543 CPUID_7_0_EBX_INVPCID) { 544 value |= (uint64_t)VMX_SECONDARY_EXEC_ENABLE_INVPCID << 32; 545 } 546 if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) & 547 CPUID_7_0_EBX_RDSEED) { 548 value |= (uint64_t)VMX_SECONDARY_EXEC_RDSEED_EXITING << 32; 549 } 550 if (kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX) & 551 CPUID_EXT2_RDTSCP) { 552 value |= (uint64_t)VMX_SECONDARY_EXEC_RDTSCP << 32; 553 } 554 } 555 /* fall through */ 556 case MSR_IA32_VMX_TRUE_PINBASED_CTLS: 557 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: 558 case MSR_IA32_VMX_TRUE_ENTRY_CTLS: 559 case MSR_IA32_VMX_TRUE_EXIT_CTLS: 560 /* 561 * Return true for bits that can be one, but do not have to be one. 562 * The SDM tells us which bits could have a "must be one" setting, 563 * so we can do the opposite transformation in make_vmx_msr_value. 564 */ 565 must_be_one = (uint32_t)value; 566 can_be_one = (uint32_t)(value >> 32); 567 return can_be_one & ~must_be_one; 568 569 default: 570 return value; 571 } 572 } 573 574 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap, 575 int *max_banks) 576 { 577 *max_banks = kvm_check_extension(s, KVM_CAP_MCE); 578 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap); 579 } 580 581 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code) 582 { 583 CPUState *cs = CPU(cpu); 584 CPUX86State *env = &cpu->env; 585 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | 586 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S; 587 uint64_t mcg_status = MCG_STATUS_MCIP; 588 int flags = 0; 589 590 if (code == BUS_MCEERR_AR) { 591 status |= MCI_STATUS_AR | 0x134; 592 mcg_status |= MCG_STATUS_RIPV | MCG_STATUS_EIPV; 593 } else { 594 status |= 0xc0; 595 mcg_status |= MCG_STATUS_RIPV; 596 } 597 598 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0; 599 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the 600 * guest kernel back into env->mcg_ext_ctl. 601 */ 602 cpu_synchronize_state(cs); 603 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) { 604 mcg_status |= MCG_STATUS_LMCE; 605 flags = 0; 606 } 607 608 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr, 609 (MCM_ADDR_PHYS << 6) | 0xc, flags); 610 } 611 612 static void emit_hypervisor_memory_failure(MemoryFailureAction action, bool ar) 613 { 614 MemoryFailureFlags mff = {.action_required = ar, .recursive = false}; 615 616 qapi_event_send_memory_failure(MEMORY_FAILURE_RECIPIENT_HYPERVISOR, action, 617 &mff); 618 } 619 620 static void hardware_memory_error(void *host_addr) 621 { 622 emit_hypervisor_memory_failure(MEMORY_FAILURE_ACTION_FATAL, true); 623 error_report("QEMU got Hardware memory error at addr %p", host_addr); 624 exit(1); 625 } 626 627 void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr) 628 { 629 X86CPU *cpu = X86_CPU(c); 630 CPUX86State *env = &cpu->env; 631 ram_addr_t ram_addr; 632 hwaddr paddr; 633 634 /* If we get an action required MCE, it has been injected by KVM 635 * while the VM was running. An action optional MCE instead should 636 * be coming from the main thread, which qemu_init_sigbus identifies 637 * as the "early kill" thread. 638 */ 639 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO); 640 641 if ((env->mcg_cap & MCG_SER_P) && addr) { 642 ram_addr = qemu_ram_addr_from_host(addr); 643 if (ram_addr != RAM_ADDR_INVALID && 644 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) { 645 kvm_hwpoison_page_add(ram_addr); 646 kvm_mce_inject(cpu, paddr, code); 647 648 /* 649 * Use different logging severity based on error type. 650 * If there is additional MCE reporting on the hypervisor, QEMU VA 651 * could be another source to identify the PA and MCE details. 652 */ 653 if (code == BUS_MCEERR_AR) { 654 error_report("Guest MCE Memory Error at QEMU addr %p and " 655 "GUEST addr 0x%" HWADDR_PRIx " of type %s injected", 656 addr, paddr, "BUS_MCEERR_AR"); 657 } else { 658 warn_report("Guest MCE Memory Error at QEMU addr %p and " 659 "GUEST addr 0x%" HWADDR_PRIx " of type %s injected", 660 addr, paddr, "BUS_MCEERR_AO"); 661 } 662 663 return; 664 } 665 666 if (code == BUS_MCEERR_AO) { 667 warn_report("Hardware memory error at addr %p of type %s " 668 "for memory used by QEMU itself instead of guest system!", 669 addr, "BUS_MCEERR_AO"); 670 } 671 } 672 673 if (code == BUS_MCEERR_AR) { 674 hardware_memory_error(addr); 675 } 676 677 /* Hope we are lucky for AO MCE, just notify a event */ 678 emit_hypervisor_memory_failure(MEMORY_FAILURE_ACTION_IGNORE, false); 679 } 680 681 static void kvm_queue_exception(CPUX86State *env, 682 int32_t exception_nr, 683 uint8_t exception_has_payload, 684 uint64_t exception_payload) 685 { 686 assert(env->exception_nr == -1); 687 assert(!env->exception_pending); 688 assert(!env->exception_injected); 689 assert(!env->exception_has_payload); 690 691 env->exception_nr = exception_nr; 692 693 if (has_exception_payload) { 694 env->exception_pending = 1; 695 696 env->exception_has_payload = exception_has_payload; 697 env->exception_payload = exception_payload; 698 } else { 699 env->exception_injected = 1; 700 701 if (exception_nr == EXCP01_DB) { 702 assert(exception_has_payload); 703 env->dr[6] = exception_payload; 704 } else if (exception_nr == EXCP0E_PAGE) { 705 assert(exception_has_payload); 706 env->cr[2] = exception_payload; 707 } else { 708 assert(!exception_has_payload); 709 } 710 } 711 } 712 713 static void cpu_update_state(void *opaque, bool running, RunState state) 714 { 715 CPUX86State *env = opaque; 716 717 if (running) { 718 env->tsc_valid = false; 719 } 720 } 721 722 unsigned long kvm_arch_vcpu_id(CPUState *cs) 723 { 724 X86CPU *cpu = X86_CPU(cs); 725 return cpu->apic_id; 726 } 727 728 #ifndef KVM_CPUID_SIGNATURE_NEXT 729 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100 730 #endif 731 732 static bool hyperv_enabled(X86CPU *cpu) 733 { 734 return kvm_check_extension(kvm_state, KVM_CAP_HYPERV) > 0 && 735 ((cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_NOTIFY) || 736 cpu->hyperv_features || cpu->hyperv_passthrough); 737 } 738 739 /* 740 * Check whether target_freq is within conservative 741 * ntp correctable bounds (250ppm) of freq 742 */ 743 static inline bool freq_within_bounds(int freq, int target_freq) 744 { 745 int max_freq = freq + (freq * 250 / 1000000); 746 int min_freq = freq - (freq * 250 / 1000000); 747 748 if (target_freq >= min_freq && target_freq <= max_freq) { 749 return true; 750 } 751 752 return false; 753 } 754 755 static int kvm_arch_set_tsc_khz(CPUState *cs) 756 { 757 X86CPU *cpu = X86_CPU(cs); 758 CPUX86State *env = &cpu->env; 759 int r, cur_freq; 760 bool set_ioctl = false; 761 762 if (!env->tsc_khz) { 763 return 0; 764 } 765 766 cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ? 767 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) : -ENOTSUP; 768 769 /* 770 * If TSC scaling is supported, attempt to set TSC frequency. 771 */ 772 if (kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL)) { 773 set_ioctl = true; 774 } 775 776 /* 777 * If desired TSC frequency is within bounds of NTP correction, 778 * attempt to set TSC frequency. 779 */ 780 if (cur_freq != -ENOTSUP && freq_within_bounds(cur_freq, env->tsc_khz)) { 781 set_ioctl = true; 782 } 783 784 r = set_ioctl ? 785 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) : 786 -ENOTSUP; 787 788 if (r < 0) { 789 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current 790 * TSC frequency doesn't match the one we want. 791 */ 792 cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ? 793 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) : 794 -ENOTSUP; 795 if (cur_freq <= 0 || cur_freq != env->tsc_khz) { 796 warn_report("TSC frequency mismatch between " 797 "VM (%" PRId64 " kHz) and host (%d kHz), " 798 "and TSC scaling unavailable", 799 env->tsc_khz, cur_freq); 800 return r; 801 } 802 } 803 804 return 0; 805 } 806 807 static bool tsc_is_stable_and_known(CPUX86State *env) 808 { 809 if (!env->tsc_khz) { 810 return false; 811 } 812 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) 813 || env->user_tsc_khz; 814 } 815 816 #define DEFAULT_EVMCS_VERSION ((1 << 8) | 1) 817 818 static struct { 819 const char *desc; 820 struct { 821 uint32_t func; 822 int reg; 823 uint32_t bits; 824 } flags[2]; 825 uint64_t dependencies; 826 } kvm_hyperv_properties[] = { 827 [HYPERV_FEAT_RELAXED] = { 828 .desc = "relaxed timing (hv-relaxed)", 829 .flags = { 830 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX, 831 .bits = HV_RELAXED_TIMING_RECOMMENDED} 832 } 833 }, 834 [HYPERV_FEAT_VAPIC] = { 835 .desc = "virtual APIC (hv-vapic)", 836 .flags = { 837 {.func = HV_CPUID_FEATURES, .reg = R_EAX, 838 .bits = HV_APIC_ACCESS_AVAILABLE} 839 } 840 }, 841 [HYPERV_FEAT_TIME] = { 842 .desc = "clocksources (hv-time)", 843 .flags = { 844 {.func = HV_CPUID_FEATURES, .reg = R_EAX, 845 .bits = HV_TIME_REF_COUNT_AVAILABLE | HV_REFERENCE_TSC_AVAILABLE} 846 } 847 }, 848 [HYPERV_FEAT_CRASH] = { 849 .desc = "crash MSRs (hv-crash)", 850 .flags = { 851 {.func = HV_CPUID_FEATURES, .reg = R_EDX, 852 .bits = HV_GUEST_CRASH_MSR_AVAILABLE} 853 } 854 }, 855 [HYPERV_FEAT_RESET] = { 856 .desc = "reset MSR (hv-reset)", 857 .flags = { 858 {.func = HV_CPUID_FEATURES, .reg = R_EAX, 859 .bits = HV_RESET_AVAILABLE} 860 } 861 }, 862 [HYPERV_FEAT_VPINDEX] = { 863 .desc = "VP_INDEX MSR (hv-vpindex)", 864 .flags = { 865 {.func = HV_CPUID_FEATURES, .reg = R_EAX, 866 .bits = HV_VP_INDEX_AVAILABLE} 867 } 868 }, 869 [HYPERV_FEAT_RUNTIME] = { 870 .desc = "VP_RUNTIME MSR (hv-runtime)", 871 .flags = { 872 {.func = HV_CPUID_FEATURES, .reg = R_EAX, 873 .bits = HV_VP_RUNTIME_AVAILABLE} 874 } 875 }, 876 [HYPERV_FEAT_SYNIC] = { 877 .desc = "synthetic interrupt controller (hv-synic)", 878 .flags = { 879 {.func = HV_CPUID_FEATURES, .reg = R_EAX, 880 .bits = HV_SYNIC_AVAILABLE} 881 } 882 }, 883 [HYPERV_FEAT_STIMER] = { 884 .desc = "synthetic timers (hv-stimer)", 885 .flags = { 886 {.func = HV_CPUID_FEATURES, .reg = R_EAX, 887 .bits = HV_SYNTIMERS_AVAILABLE} 888 }, 889 .dependencies = BIT(HYPERV_FEAT_SYNIC) | BIT(HYPERV_FEAT_TIME) 890 }, 891 [HYPERV_FEAT_FREQUENCIES] = { 892 .desc = "frequency MSRs (hv-frequencies)", 893 .flags = { 894 {.func = HV_CPUID_FEATURES, .reg = R_EAX, 895 .bits = HV_ACCESS_FREQUENCY_MSRS}, 896 {.func = HV_CPUID_FEATURES, .reg = R_EDX, 897 .bits = HV_FREQUENCY_MSRS_AVAILABLE} 898 } 899 }, 900 [HYPERV_FEAT_REENLIGHTENMENT] = { 901 .desc = "reenlightenment MSRs (hv-reenlightenment)", 902 .flags = { 903 {.func = HV_CPUID_FEATURES, .reg = R_EAX, 904 .bits = HV_ACCESS_REENLIGHTENMENTS_CONTROL} 905 } 906 }, 907 [HYPERV_FEAT_TLBFLUSH] = { 908 .desc = "paravirtualized TLB flush (hv-tlbflush)", 909 .flags = { 910 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX, 911 .bits = HV_REMOTE_TLB_FLUSH_RECOMMENDED | 912 HV_EX_PROCESSOR_MASKS_RECOMMENDED} 913 }, 914 .dependencies = BIT(HYPERV_FEAT_VPINDEX) 915 }, 916 [HYPERV_FEAT_EVMCS] = { 917 .desc = "enlightened VMCS (hv-evmcs)", 918 .flags = { 919 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX, 920 .bits = HV_ENLIGHTENED_VMCS_RECOMMENDED} 921 }, 922 .dependencies = BIT(HYPERV_FEAT_VAPIC) 923 }, 924 [HYPERV_FEAT_IPI] = { 925 .desc = "paravirtualized IPI (hv-ipi)", 926 .flags = { 927 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX, 928 .bits = HV_CLUSTER_IPI_RECOMMENDED | 929 HV_EX_PROCESSOR_MASKS_RECOMMENDED} 930 }, 931 .dependencies = BIT(HYPERV_FEAT_VPINDEX) 932 }, 933 [HYPERV_FEAT_STIMER_DIRECT] = { 934 .desc = "direct mode synthetic timers (hv-stimer-direct)", 935 .flags = { 936 {.func = HV_CPUID_FEATURES, .reg = R_EDX, 937 .bits = HV_STIMER_DIRECT_MODE_AVAILABLE} 938 }, 939 .dependencies = BIT(HYPERV_FEAT_STIMER) 940 }, 941 [HYPERV_FEAT_AVIC] = { 942 .desc = "AVIC/APICv support (hv-avic/hv-apicv)", 943 .flags = { 944 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX, 945 .bits = HV_DEPRECATING_AEOI_RECOMMENDED} 946 } 947 }, 948 #ifdef CONFIG_SYNDBG 949 [HYPERV_FEAT_SYNDBG] = { 950 .desc = "Enable synthetic kernel debugger channel (hv-syndbg)", 951 .flags = { 952 {.func = HV_CPUID_FEATURES, .reg = R_EDX, 953 .bits = HV_FEATURE_DEBUG_MSRS_AVAILABLE} 954 }, 955 .dependencies = BIT(HYPERV_FEAT_SYNIC) | BIT(HYPERV_FEAT_RELAXED) 956 }, 957 #endif 958 [HYPERV_FEAT_MSR_BITMAP] = { 959 .desc = "enlightened MSR-Bitmap (hv-emsr-bitmap)", 960 .flags = { 961 {.func = HV_CPUID_NESTED_FEATURES, .reg = R_EAX, 962 .bits = HV_NESTED_MSR_BITMAP} 963 } 964 }, 965 [HYPERV_FEAT_XMM_INPUT] = { 966 .desc = "XMM fast hypercall input (hv-xmm-input)", 967 .flags = { 968 {.func = HV_CPUID_FEATURES, .reg = R_EDX, 969 .bits = HV_HYPERCALL_XMM_INPUT_AVAILABLE} 970 } 971 }, 972 [HYPERV_FEAT_TLBFLUSH_EXT] = { 973 .desc = "Extended gva ranges for TLB flush hypercalls (hv-tlbflush-ext)", 974 .flags = { 975 {.func = HV_CPUID_FEATURES, .reg = R_EDX, 976 .bits = HV_EXT_GVA_RANGES_FLUSH_AVAILABLE} 977 }, 978 .dependencies = BIT(HYPERV_FEAT_TLBFLUSH) 979 }, 980 [HYPERV_FEAT_TLBFLUSH_DIRECT] = { 981 .desc = "direct TLB flush (hv-tlbflush-direct)", 982 .flags = { 983 {.func = HV_CPUID_NESTED_FEATURES, .reg = R_EAX, 984 .bits = HV_NESTED_DIRECT_FLUSH} 985 }, 986 .dependencies = BIT(HYPERV_FEAT_VAPIC) 987 }, 988 }; 989 990 static struct kvm_cpuid2 *try_get_hv_cpuid(CPUState *cs, int max, 991 bool do_sys_ioctl) 992 { 993 struct kvm_cpuid2 *cpuid; 994 int r, size; 995 996 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries); 997 cpuid = g_malloc0(size); 998 cpuid->nent = max; 999 1000 if (do_sys_ioctl) { 1001 r = kvm_ioctl(kvm_state, KVM_GET_SUPPORTED_HV_CPUID, cpuid); 1002 } else { 1003 r = kvm_vcpu_ioctl(cs, KVM_GET_SUPPORTED_HV_CPUID, cpuid); 1004 } 1005 if (r == 0 && cpuid->nent >= max) { 1006 r = -E2BIG; 1007 } 1008 if (r < 0) { 1009 if (r == -E2BIG) { 1010 g_free(cpuid); 1011 return NULL; 1012 } else { 1013 fprintf(stderr, "KVM_GET_SUPPORTED_HV_CPUID failed: %s\n", 1014 strerror(-r)); 1015 exit(1); 1016 } 1017 } 1018 return cpuid; 1019 } 1020 1021 /* 1022 * Run KVM_GET_SUPPORTED_HV_CPUID ioctl(), allocating a buffer large enough 1023 * for all entries. 1024 */ 1025 static struct kvm_cpuid2 *get_supported_hv_cpuid(CPUState *cs) 1026 { 1027 struct kvm_cpuid2 *cpuid; 1028 /* 0x40000000..0x40000005, 0x4000000A, 0x40000080..0x40000082 leaves */ 1029 int max = 11; 1030 int i; 1031 bool do_sys_ioctl; 1032 1033 do_sys_ioctl = 1034 kvm_check_extension(kvm_state, KVM_CAP_SYS_HYPERV_CPUID) > 0; 1035 1036 /* 1037 * Non-empty KVM context is needed when KVM_CAP_SYS_HYPERV_CPUID is 1038 * unsupported, kvm_hyperv_expand_features() checks for that. 1039 */ 1040 assert(do_sys_ioctl || cs->kvm_state); 1041 1042 /* 1043 * When the buffer is too small, KVM_GET_SUPPORTED_HV_CPUID fails with 1044 * -E2BIG, however, it doesn't report back the right size. Keep increasing 1045 * it and re-trying until we succeed. 1046 */ 1047 while ((cpuid = try_get_hv_cpuid(cs, max, do_sys_ioctl)) == NULL) { 1048 max++; 1049 } 1050 1051 /* 1052 * KVM_GET_SUPPORTED_HV_CPUID does not set EVMCS CPUID bit before 1053 * KVM_CAP_HYPERV_ENLIGHTENED_VMCS is enabled but we want to get the 1054 * information early, just check for the capability and set the bit 1055 * manually. 1056 */ 1057 if (!do_sys_ioctl && kvm_check_extension(cs->kvm_state, 1058 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) { 1059 for (i = 0; i < cpuid->nent; i++) { 1060 if (cpuid->entries[i].function == HV_CPUID_ENLIGHTMENT_INFO) { 1061 cpuid->entries[i].eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED; 1062 } 1063 } 1064 } 1065 1066 return cpuid; 1067 } 1068 1069 /* 1070 * When KVM_GET_SUPPORTED_HV_CPUID is not supported we fill CPUID feature 1071 * leaves from KVM_CAP_HYPERV* and present MSRs data. 1072 */ 1073 static struct kvm_cpuid2 *get_supported_hv_cpuid_legacy(CPUState *cs) 1074 { 1075 X86CPU *cpu = X86_CPU(cs); 1076 struct kvm_cpuid2 *cpuid; 1077 struct kvm_cpuid_entry2 *entry_feat, *entry_recomm; 1078 1079 /* HV_CPUID_FEATURES, HV_CPUID_ENLIGHTMENT_INFO */ 1080 cpuid = g_malloc0(sizeof(*cpuid) + 2 * sizeof(*cpuid->entries)); 1081 cpuid->nent = 2; 1082 1083 /* HV_CPUID_VENDOR_AND_MAX_FUNCTIONS */ 1084 entry_feat = &cpuid->entries[0]; 1085 entry_feat->function = HV_CPUID_FEATURES; 1086 1087 entry_recomm = &cpuid->entries[1]; 1088 entry_recomm->function = HV_CPUID_ENLIGHTMENT_INFO; 1089 entry_recomm->ebx = cpu->hyperv_spinlock_attempts; 1090 1091 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0) { 1092 entry_feat->eax |= HV_HYPERCALL_AVAILABLE; 1093 entry_feat->eax |= HV_APIC_ACCESS_AVAILABLE; 1094 entry_feat->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE; 1095 entry_recomm->eax |= HV_RELAXED_TIMING_RECOMMENDED; 1096 entry_recomm->eax |= HV_APIC_ACCESS_RECOMMENDED; 1097 } 1098 1099 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) { 1100 entry_feat->eax |= HV_TIME_REF_COUNT_AVAILABLE; 1101 entry_feat->eax |= HV_REFERENCE_TSC_AVAILABLE; 1102 } 1103 1104 if (has_msr_hv_frequencies) { 1105 entry_feat->eax |= HV_ACCESS_FREQUENCY_MSRS; 1106 entry_feat->edx |= HV_FREQUENCY_MSRS_AVAILABLE; 1107 } 1108 1109 if (has_msr_hv_crash) { 1110 entry_feat->edx |= HV_GUEST_CRASH_MSR_AVAILABLE; 1111 } 1112 1113 if (has_msr_hv_reenlightenment) { 1114 entry_feat->eax |= HV_ACCESS_REENLIGHTENMENTS_CONTROL; 1115 } 1116 1117 if (has_msr_hv_reset) { 1118 entry_feat->eax |= HV_RESET_AVAILABLE; 1119 } 1120 1121 if (has_msr_hv_vpindex) { 1122 entry_feat->eax |= HV_VP_INDEX_AVAILABLE; 1123 } 1124 1125 if (has_msr_hv_runtime) { 1126 entry_feat->eax |= HV_VP_RUNTIME_AVAILABLE; 1127 } 1128 1129 if (has_msr_hv_synic) { 1130 unsigned int cap = cpu->hyperv_synic_kvm_only ? 1131 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2; 1132 1133 if (kvm_check_extension(cs->kvm_state, cap) > 0) { 1134 entry_feat->eax |= HV_SYNIC_AVAILABLE; 1135 } 1136 } 1137 1138 if (has_msr_hv_stimer) { 1139 entry_feat->eax |= HV_SYNTIMERS_AVAILABLE; 1140 } 1141 1142 if (has_msr_hv_syndbg_options) { 1143 entry_feat->edx |= HV_GUEST_DEBUGGING_AVAILABLE; 1144 entry_feat->edx |= HV_FEATURE_DEBUG_MSRS_AVAILABLE; 1145 entry_feat->ebx |= HV_PARTITION_DEBUGGING_ALLOWED; 1146 } 1147 1148 if (kvm_check_extension(cs->kvm_state, 1149 KVM_CAP_HYPERV_TLBFLUSH) > 0) { 1150 entry_recomm->eax |= HV_REMOTE_TLB_FLUSH_RECOMMENDED; 1151 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED; 1152 } 1153 1154 if (kvm_check_extension(cs->kvm_state, 1155 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) { 1156 entry_recomm->eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED; 1157 } 1158 1159 if (kvm_check_extension(cs->kvm_state, 1160 KVM_CAP_HYPERV_SEND_IPI) > 0) { 1161 entry_recomm->eax |= HV_CLUSTER_IPI_RECOMMENDED; 1162 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED; 1163 } 1164 1165 return cpuid; 1166 } 1167 1168 static uint32_t hv_cpuid_get_host(CPUState *cs, uint32_t func, int reg) 1169 { 1170 struct kvm_cpuid_entry2 *entry; 1171 struct kvm_cpuid2 *cpuid; 1172 1173 if (hv_cpuid_cache) { 1174 cpuid = hv_cpuid_cache; 1175 } else { 1176 if (kvm_check_extension(kvm_state, KVM_CAP_HYPERV_CPUID) > 0) { 1177 cpuid = get_supported_hv_cpuid(cs); 1178 } else { 1179 /* 1180 * 'cs->kvm_state' may be NULL when Hyper-V features are expanded 1181 * before KVM context is created but this is only done when 1182 * KVM_CAP_SYS_HYPERV_CPUID is supported and it implies 1183 * KVM_CAP_HYPERV_CPUID. 1184 */ 1185 assert(cs->kvm_state); 1186 1187 cpuid = get_supported_hv_cpuid_legacy(cs); 1188 } 1189 hv_cpuid_cache = cpuid; 1190 } 1191 1192 if (!cpuid) { 1193 return 0; 1194 } 1195 1196 entry = cpuid_find_entry(cpuid, func, 0); 1197 if (!entry) { 1198 return 0; 1199 } 1200 1201 return cpuid_entry_get_reg(entry, reg); 1202 } 1203 1204 static bool hyperv_feature_supported(CPUState *cs, int feature) 1205 { 1206 uint32_t func, bits; 1207 int i, reg; 1208 1209 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties[feature].flags); i++) { 1210 1211 func = kvm_hyperv_properties[feature].flags[i].func; 1212 reg = kvm_hyperv_properties[feature].flags[i].reg; 1213 bits = kvm_hyperv_properties[feature].flags[i].bits; 1214 1215 if (!func) { 1216 continue; 1217 } 1218 1219 if ((hv_cpuid_get_host(cs, func, reg) & bits) != bits) { 1220 return false; 1221 } 1222 } 1223 1224 return true; 1225 } 1226 1227 /* Checks that all feature dependencies are enabled */ 1228 static bool hv_feature_check_deps(X86CPU *cpu, int feature, Error **errp) 1229 { 1230 uint64_t deps; 1231 int dep_feat; 1232 1233 deps = kvm_hyperv_properties[feature].dependencies; 1234 while (deps) { 1235 dep_feat = ctz64(deps); 1236 if (!(hyperv_feat_enabled(cpu, dep_feat))) { 1237 error_setg(errp, "Hyper-V %s requires Hyper-V %s", 1238 kvm_hyperv_properties[feature].desc, 1239 kvm_hyperv_properties[dep_feat].desc); 1240 return false; 1241 } 1242 deps &= ~(1ull << dep_feat); 1243 } 1244 1245 return true; 1246 } 1247 1248 static uint32_t hv_build_cpuid_leaf(CPUState *cs, uint32_t func, int reg) 1249 { 1250 X86CPU *cpu = X86_CPU(cs); 1251 uint32_t r = 0; 1252 int i, j; 1253 1254 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties); i++) { 1255 if (!hyperv_feat_enabled(cpu, i)) { 1256 continue; 1257 } 1258 1259 for (j = 0; j < ARRAY_SIZE(kvm_hyperv_properties[i].flags); j++) { 1260 if (kvm_hyperv_properties[i].flags[j].func != func) { 1261 continue; 1262 } 1263 if (kvm_hyperv_properties[i].flags[j].reg != reg) { 1264 continue; 1265 } 1266 1267 r |= kvm_hyperv_properties[i].flags[j].bits; 1268 } 1269 } 1270 1271 /* HV_CPUID_NESTED_FEATURES.EAX also encodes the supported eVMCS range */ 1272 if (func == HV_CPUID_NESTED_FEATURES && reg == R_EAX) { 1273 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) { 1274 r |= DEFAULT_EVMCS_VERSION; 1275 } 1276 } 1277 1278 return r; 1279 } 1280 1281 /* 1282 * Expand Hyper-V CPU features. In partucular, check that all the requested 1283 * features are supported by the host and the sanity of the configuration 1284 * (that all the required dependencies are included). Also, this takes care 1285 * of 'hv_passthrough' mode and fills the environment with all supported 1286 * Hyper-V features. 1287 */ 1288 bool kvm_hyperv_expand_features(X86CPU *cpu, Error **errp) 1289 { 1290 CPUState *cs = CPU(cpu); 1291 Error *local_err = NULL; 1292 int feat; 1293 1294 if (!hyperv_enabled(cpu)) 1295 return true; 1296 1297 /* 1298 * When kvm_hyperv_expand_features is called at CPU feature expansion 1299 * time per-CPU kvm_state is not available yet so we can only proceed 1300 * when KVM_CAP_SYS_HYPERV_CPUID is supported. 1301 */ 1302 if (!cs->kvm_state && 1303 !kvm_check_extension(kvm_state, KVM_CAP_SYS_HYPERV_CPUID)) 1304 return true; 1305 1306 if (cpu->hyperv_passthrough) { 1307 cpu->hyperv_vendor_id[0] = 1308 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_EBX); 1309 cpu->hyperv_vendor_id[1] = 1310 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_ECX); 1311 cpu->hyperv_vendor_id[2] = 1312 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_EDX); 1313 cpu->hyperv_vendor = g_realloc(cpu->hyperv_vendor, 1314 sizeof(cpu->hyperv_vendor_id) + 1); 1315 memcpy(cpu->hyperv_vendor, cpu->hyperv_vendor_id, 1316 sizeof(cpu->hyperv_vendor_id)); 1317 cpu->hyperv_vendor[sizeof(cpu->hyperv_vendor_id)] = 0; 1318 1319 cpu->hyperv_interface_id[0] = 1320 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EAX); 1321 cpu->hyperv_interface_id[1] = 1322 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EBX); 1323 cpu->hyperv_interface_id[2] = 1324 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_ECX); 1325 cpu->hyperv_interface_id[3] = 1326 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EDX); 1327 1328 cpu->hyperv_ver_id_build = 1329 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EAX); 1330 cpu->hyperv_ver_id_major = 1331 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EBX) >> 16; 1332 cpu->hyperv_ver_id_minor = 1333 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EBX) & 0xffff; 1334 cpu->hyperv_ver_id_sp = 1335 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_ECX); 1336 cpu->hyperv_ver_id_sb = 1337 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EDX) >> 24; 1338 cpu->hyperv_ver_id_sn = 1339 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EDX) & 0xffffff; 1340 1341 cpu->hv_max_vps = hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, 1342 R_EAX); 1343 cpu->hyperv_limits[0] = 1344 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_EBX); 1345 cpu->hyperv_limits[1] = 1346 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_ECX); 1347 cpu->hyperv_limits[2] = 1348 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_EDX); 1349 1350 cpu->hyperv_spinlock_attempts = 1351 hv_cpuid_get_host(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EBX); 1352 1353 /* 1354 * Mark feature as enabled in 'cpu->hyperv_features' as 1355 * hv_build_cpuid_leaf() uses this info to build guest CPUIDs. 1356 */ 1357 for (feat = 0; feat < ARRAY_SIZE(kvm_hyperv_properties); feat++) { 1358 if (hyperv_feature_supported(cs, feat)) { 1359 cpu->hyperv_features |= BIT(feat); 1360 } 1361 } 1362 } else { 1363 /* Check features availability and dependencies */ 1364 for (feat = 0; feat < ARRAY_SIZE(kvm_hyperv_properties); feat++) { 1365 /* If the feature was not requested skip it. */ 1366 if (!hyperv_feat_enabled(cpu, feat)) { 1367 continue; 1368 } 1369 1370 /* Check if the feature is supported by KVM */ 1371 if (!hyperv_feature_supported(cs, feat)) { 1372 error_setg(errp, "Hyper-V %s is not supported by kernel", 1373 kvm_hyperv_properties[feat].desc); 1374 return false; 1375 } 1376 1377 /* Check dependencies */ 1378 if (!hv_feature_check_deps(cpu, feat, &local_err)) { 1379 error_propagate(errp, local_err); 1380 return false; 1381 } 1382 } 1383 } 1384 1385 /* Additional dependencies not covered by kvm_hyperv_properties[] */ 1386 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) && 1387 !cpu->hyperv_synic_kvm_only && 1388 !hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)) { 1389 error_setg(errp, "Hyper-V %s requires Hyper-V %s", 1390 kvm_hyperv_properties[HYPERV_FEAT_SYNIC].desc, 1391 kvm_hyperv_properties[HYPERV_FEAT_VPINDEX].desc); 1392 return false; 1393 } 1394 1395 return true; 1396 } 1397 1398 /* 1399 * Fill in Hyper-V CPUIDs. Returns the number of entries filled in cpuid_ent. 1400 */ 1401 static int hyperv_fill_cpuids(CPUState *cs, 1402 struct kvm_cpuid_entry2 *cpuid_ent) 1403 { 1404 X86CPU *cpu = X86_CPU(cs); 1405 struct kvm_cpuid_entry2 *c; 1406 uint32_t signature[3]; 1407 uint32_t cpuid_i = 0, max_cpuid_leaf = 0; 1408 uint32_t nested_eax = 1409 hv_build_cpuid_leaf(cs, HV_CPUID_NESTED_FEATURES, R_EAX); 1410 1411 max_cpuid_leaf = nested_eax ? HV_CPUID_NESTED_FEATURES : 1412 HV_CPUID_IMPLEMENT_LIMITS; 1413 1414 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNDBG)) { 1415 max_cpuid_leaf = 1416 MAX(max_cpuid_leaf, HV_CPUID_SYNDBG_PLATFORM_CAPABILITIES); 1417 } 1418 1419 c = &cpuid_ent[cpuid_i++]; 1420 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS; 1421 c->eax = max_cpuid_leaf; 1422 c->ebx = cpu->hyperv_vendor_id[0]; 1423 c->ecx = cpu->hyperv_vendor_id[1]; 1424 c->edx = cpu->hyperv_vendor_id[2]; 1425 1426 c = &cpuid_ent[cpuid_i++]; 1427 c->function = HV_CPUID_INTERFACE; 1428 c->eax = cpu->hyperv_interface_id[0]; 1429 c->ebx = cpu->hyperv_interface_id[1]; 1430 c->ecx = cpu->hyperv_interface_id[2]; 1431 c->edx = cpu->hyperv_interface_id[3]; 1432 1433 c = &cpuid_ent[cpuid_i++]; 1434 c->function = HV_CPUID_VERSION; 1435 c->eax = cpu->hyperv_ver_id_build; 1436 c->ebx = (uint32_t)cpu->hyperv_ver_id_major << 16 | 1437 cpu->hyperv_ver_id_minor; 1438 c->ecx = cpu->hyperv_ver_id_sp; 1439 c->edx = (uint32_t)cpu->hyperv_ver_id_sb << 24 | 1440 (cpu->hyperv_ver_id_sn & 0xffffff); 1441 1442 c = &cpuid_ent[cpuid_i++]; 1443 c->function = HV_CPUID_FEATURES; 1444 c->eax = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EAX); 1445 c->ebx = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EBX); 1446 c->edx = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EDX); 1447 1448 /* Unconditionally required with any Hyper-V enlightenment */ 1449 c->eax |= HV_HYPERCALL_AVAILABLE; 1450 1451 /* SynIC and Vmbus devices require messages/signals hypercalls */ 1452 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) && 1453 !cpu->hyperv_synic_kvm_only) { 1454 c->ebx |= HV_POST_MESSAGES | HV_SIGNAL_EVENTS; 1455 } 1456 1457 1458 /* Not exposed by KVM but needed to make CPU hotplug in Windows work */ 1459 c->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE; 1460 1461 c = &cpuid_ent[cpuid_i++]; 1462 c->function = HV_CPUID_ENLIGHTMENT_INFO; 1463 c->eax = hv_build_cpuid_leaf(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EAX); 1464 c->ebx = cpu->hyperv_spinlock_attempts; 1465 1466 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC) && 1467 !hyperv_feat_enabled(cpu, HYPERV_FEAT_AVIC)) { 1468 c->eax |= HV_APIC_ACCESS_RECOMMENDED; 1469 } 1470 1471 if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_ON) { 1472 c->eax |= HV_NO_NONARCH_CORESHARING; 1473 } else if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO) { 1474 c->eax |= hv_cpuid_get_host(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EAX) & 1475 HV_NO_NONARCH_CORESHARING; 1476 } 1477 1478 c = &cpuid_ent[cpuid_i++]; 1479 c->function = HV_CPUID_IMPLEMENT_LIMITS; 1480 c->eax = cpu->hv_max_vps; 1481 c->ebx = cpu->hyperv_limits[0]; 1482 c->ecx = cpu->hyperv_limits[1]; 1483 c->edx = cpu->hyperv_limits[2]; 1484 1485 if (nested_eax) { 1486 uint32_t function; 1487 1488 /* Create zeroed 0x40000006..0x40000009 leaves */ 1489 for (function = HV_CPUID_IMPLEMENT_LIMITS + 1; 1490 function < HV_CPUID_NESTED_FEATURES; function++) { 1491 c = &cpuid_ent[cpuid_i++]; 1492 c->function = function; 1493 } 1494 1495 c = &cpuid_ent[cpuid_i++]; 1496 c->function = HV_CPUID_NESTED_FEATURES; 1497 c->eax = nested_eax; 1498 } 1499 1500 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNDBG)) { 1501 c = &cpuid_ent[cpuid_i++]; 1502 c->function = HV_CPUID_SYNDBG_VENDOR_AND_MAX_FUNCTIONS; 1503 c->eax = hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ? 1504 HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS; 1505 memcpy(signature, "Microsoft VS", 12); 1506 c->eax = 0; 1507 c->ebx = signature[0]; 1508 c->ecx = signature[1]; 1509 c->edx = signature[2]; 1510 1511 c = &cpuid_ent[cpuid_i++]; 1512 c->function = HV_CPUID_SYNDBG_INTERFACE; 1513 memcpy(signature, "VS#1\0\0\0\0\0\0\0\0", 12); 1514 c->eax = signature[0]; 1515 c->ebx = 0; 1516 c->ecx = 0; 1517 c->edx = 0; 1518 1519 c = &cpuid_ent[cpuid_i++]; 1520 c->function = HV_CPUID_SYNDBG_PLATFORM_CAPABILITIES; 1521 c->eax = HV_SYNDBG_CAP_ALLOW_KERNEL_DEBUGGING; 1522 c->ebx = 0; 1523 c->ecx = 0; 1524 c->edx = 0; 1525 } 1526 1527 return cpuid_i; 1528 } 1529 1530 static Error *hv_passthrough_mig_blocker; 1531 static Error *hv_no_nonarch_cs_mig_blocker; 1532 1533 /* Checks that the exposed eVMCS version range is supported by KVM */ 1534 static bool evmcs_version_supported(uint16_t evmcs_version, 1535 uint16_t supported_evmcs_version) 1536 { 1537 uint8_t min_version = evmcs_version & 0xff; 1538 uint8_t max_version = evmcs_version >> 8; 1539 uint8_t min_supported_version = supported_evmcs_version & 0xff; 1540 uint8_t max_supported_version = supported_evmcs_version >> 8; 1541 1542 return (min_version >= min_supported_version) && 1543 (max_version <= max_supported_version); 1544 } 1545 1546 static int hyperv_init_vcpu(X86CPU *cpu) 1547 { 1548 CPUState *cs = CPU(cpu); 1549 Error *local_err = NULL; 1550 int ret; 1551 1552 if (cpu->hyperv_passthrough && hv_passthrough_mig_blocker == NULL) { 1553 error_setg(&hv_passthrough_mig_blocker, 1554 "'hv-passthrough' CPU flag prevents migration, use explicit" 1555 " set of hv-* flags instead"); 1556 ret = migrate_add_blocker(&hv_passthrough_mig_blocker, &local_err); 1557 if (ret < 0) { 1558 error_report_err(local_err); 1559 return ret; 1560 } 1561 } 1562 1563 if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO && 1564 hv_no_nonarch_cs_mig_blocker == NULL) { 1565 error_setg(&hv_no_nonarch_cs_mig_blocker, 1566 "'hv-no-nonarch-coresharing=auto' CPU flag prevents migration" 1567 " use explicit 'hv-no-nonarch-coresharing=on' instead (but" 1568 " make sure SMT is disabled and/or that vCPUs are properly" 1569 " pinned)"); 1570 ret = migrate_add_blocker(&hv_no_nonarch_cs_mig_blocker, &local_err); 1571 if (ret < 0) { 1572 error_report_err(local_err); 1573 return ret; 1574 } 1575 } 1576 1577 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && !hv_vpindex_settable) { 1578 /* 1579 * the kernel doesn't support setting vp_index; assert that its value 1580 * is in sync 1581 */ 1582 uint64_t value; 1583 1584 ret = kvm_get_one_msr(cpu, HV_X64_MSR_VP_INDEX, &value); 1585 if (ret < 0) { 1586 return ret; 1587 } 1588 1589 if (value != hyperv_vp_index(CPU(cpu))) { 1590 error_report("kernel's vp_index != QEMU's vp_index"); 1591 return -ENXIO; 1592 } 1593 } 1594 1595 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) { 1596 uint32_t synic_cap = cpu->hyperv_synic_kvm_only ? 1597 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2; 1598 ret = kvm_vcpu_enable_cap(cs, synic_cap, 0); 1599 if (ret < 0) { 1600 error_report("failed to turn on HyperV SynIC in KVM: %s", 1601 strerror(-ret)); 1602 return ret; 1603 } 1604 1605 if (!cpu->hyperv_synic_kvm_only) { 1606 ret = hyperv_x86_synic_add(cpu); 1607 if (ret < 0) { 1608 error_report("failed to create HyperV SynIC: %s", 1609 strerror(-ret)); 1610 return ret; 1611 } 1612 } 1613 } 1614 1615 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) { 1616 uint16_t evmcs_version = DEFAULT_EVMCS_VERSION; 1617 uint16_t supported_evmcs_version; 1618 1619 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 0, 1620 (uintptr_t)&supported_evmcs_version); 1621 1622 /* 1623 * KVM is required to support EVMCS ver.1. as that's what 'hv-evmcs' 1624 * option sets. Note: we hardcode the maximum supported eVMCS version 1625 * to '1' as well so 'hv-evmcs' feature is migratable even when (and if) 1626 * ver.2 is implemented. A new option (e.g. 'hv-evmcs=2') will then have 1627 * to be added. 1628 */ 1629 if (ret < 0) { 1630 error_report("Hyper-V %s is not supported by kernel", 1631 kvm_hyperv_properties[HYPERV_FEAT_EVMCS].desc); 1632 return ret; 1633 } 1634 1635 if (!evmcs_version_supported(evmcs_version, supported_evmcs_version)) { 1636 error_report("eVMCS version range [%d..%d] is not supported by " 1637 "kernel (supported: [%d..%d])", evmcs_version & 0xff, 1638 evmcs_version >> 8, supported_evmcs_version & 0xff, 1639 supported_evmcs_version >> 8); 1640 return -ENOTSUP; 1641 } 1642 } 1643 1644 if (cpu->hyperv_enforce_cpuid) { 1645 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENFORCE_CPUID, 0, 1); 1646 if (ret < 0) { 1647 error_report("failed to enable KVM_CAP_HYPERV_ENFORCE_CPUID: %s", 1648 strerror(-ret)); 1649 return ret; 1650 } 1651 } 1652 1653 /* Skip SynIC and VP_INDEX since they are hard deps already */ 1654 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_STIMER) && 1655 hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC) && 1656 hyperv_feat_enabled(cpu, HYPERV_FEAT_RUNTIME)) { 1657 hyperv_x86_set_vmbus_recommended_features_enabled(); 1658 } 1659 1660 return 0; 1661 } 1662 1663 static Error *invtsc_mig_blocker; 1664 1665 #define KVM_MAX_CPUID_ENTRIES 100 1666 1667 static void kvm_init_xsave(CPUX86State *env) 1668 { 1669 if (has_xsave2) { 1670 env->xsave_buf_len = QEMU_ALIGN_UP(has_xsave2, 4096); 1671 } else { 1672 env->xsave_buf_len = sizeof(struct kvm_xsave); 1673 } 1674 1675 env->xsave_buf = qemu_memalign(4096, env->xsave_buf_len); 1676 memset(env->xsave_buf, 0, env->xsave_buf_len); 1677 /* 1678 * The allocated storage must be large enough for all of the 1679 * possible XSAVE state components. 1680 */ 1681 assert(kvm_arch_get_supported_cpuid(kvm_state, 0xd, 0, R_ECX) <= 1682 env->xsave_buf_len); 1683 } 1684 1685 static void kvm_init_nested_state(CPUX86State *env) 1686 { 1687 struct kvm_vmx_nested_state_hdr *vmx_hdr; 1688 uint32_t size; 1689 1690 if (!env->nested_state) { 1691 return; 1692 } 1693 1694 size = env->nested_state->size; 1695 1696 memset(env->nested_state, 0, size); 1697 env->nested_state->size = size; 1698 1699 if (cpu_has_vmx(env)) { 1700 env->nested_state->format = KVM_STATE_NESTED_FORMAT_VMX; 1701 vmx_hdr = &env->nested_state->hdr.vmx; 1702 vmx_hdr->vmxon_pa = -1ull; 1703 vmx_hdr->vmcs12_pa = -1ull; 1704 } else if (cpu_has_svm(env)) { 1705 env->nested_state->format = KVM_STATE_NESTED_FORMAT_SVM; 1706 } 1707 } 1708 1709 static uint32_t kvm_x86_build_cpuid(CPUX86State *env, 1710 struct kvm_cpuid_entry2 *entries, 1711 uint32_t cpuid_i) 1712 { 1713 uint32_t limit, i, j; 1714 uint32_t unused; 1715 struct kvm_cpuid_entry2 *c; 1716 1717 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused); 1718 1719 for (i = 0; i <= limit; i++) { 1720 j = 0; 1721 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { 1722 goto full; 1723 } 1724 c = &entries[cpuid_i++]; 1725 switch (i) { 1726 case 2: { 1727 /* Keep reading function 2 till all the input is received */ 1728 int times; 1729 1730 c->function = i; 1731 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC | 1732 KVM_CPUID_FLAG_STATE_READ_NEXT; 1733 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); 1734 times = c->eax & 0xff; 1735 1736 for (j = 1; j < times; ++j) { 1737 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { 1738 goto full; 1739 } 1740 c = &entries[cpuid_i++]; 1741 c->function = i; 1742 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC; 1743 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); 1744 } 1745 break; 1746 } 1747 case 0x1f: 1748 if (env->nr_dies < 2) { 1749 cpuid_i--; 1750 break; 1751 } 1752 /* fallthrough */ 1753 case 4: 1754 case 0xb: 1755 case 0xd: 1756 for (j = 0; ; j++) { 1757 if (i == 0xd && j == 64) { 1758 break; 1759 } 1760 1761 c->function = i; 1762 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 1763 c->index = j; 1764 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx); 1765 1766 if (i == 4 && c->eax == 0) { 1767 break; 1768 } 1769 if (i == 0xb && !(c->ecx & 0xff00)) { 1770 break; 1771 } 1772 if (i == 0x1f && !(c->ecx & 0xff00)) { 1773 break; 1774 } 1775 if (i == 0xd && c->eax == 0) { 1776 continue; 1777 } 1778 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { 1779 goto full; 1780 } 1781 c = &entries[cpuid_i++]; 1782 } 1783 break; 1784 case 0x12: 1785 for (j = 0; ; j++) { 1786 c->function = i; 1787 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 1788 c->index = j; 1789 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx); 1790 1791 if (j > 1 && (c->eax & 0xf) != 1) { 1792 break; 1793 } 1794 1795 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { 1796 goto full; 1797 } 1798 c = &entries[cpuid_i++]; 1799 } 1800 break; 1801 case 0x7: 1802 case 0x14: 1803 case 0x1d: 1804 case 0x1e: { 1805 uint32_t times; 1806 1807 c->function = i; 1808 c->index = 0; 1809 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 1810 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); 1811 times = c->eax; 1812 1813 for (j = 1; j <= times; ++j) { 1814 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { 1815 goto full; 1816 } 1817 c = &entries[cpuid_i++]; 1818 c->function = i; 1819 c->index = j; 1820 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 1821 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx); 1822 } 1823 break; 1824 } 1825 default: 1826 c->function = i; 1827 c->flags = 0; 1828 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); 1829 if (!c->eax && !c->ebx && !c->ecx && !c->edx) { 1830 /* 1831 * KVM already returns all zeroes if a CPUID entry is missing, 1832 * so we can omit it and avoid hitting KVM's 80-entry limit. 1833 */ 1834 cpuid_i--; 1835 } 1836 break; 1837 } 1838 } 1839 1840 if (limit >= 0x0a) { 1841 uint32_t eax, edx; 1842 1843 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx); 1844 1845 has_architectural_pmu_version = eax & 0xff; 1846 if (has_architectural_pmu_version > 0) { 1847 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8; 1848 1849 /* Shouldn't be more than 32, since that's the number of bits 1850 * available in EBX to tell us _which_ counters are available. 1851 * Play it safe. 1852 */ 1853 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) { 1854 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS; 1855 } 1856 1857 if (has_architectural_pmu_version > 1) { 1858 num_architectural_pmu_fixed_counters = edx & 0x1f; 1859 1860 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) { 1861 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS; 1862 } 1863 } 1864 } 1865 } 1866 1867 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused); 1868 1869 for (i = 0x80000000; i <= limit; i++) { 1870 j = 0; 1871 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { 1872 goto full; 1873 } 1874 c = &entries[cpuid_i++]; 1875 1876 switch (i) { 1877 case 0x8000001d: 1878 /* Query for all AMD cache information leaves */ 1879 for (j = 0; ; j++) { 1880 c->function = i; 1881 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 1882 c->index = j; 1883 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx); 1884 1885 if (c->eax == 0) { 1886 break; 1887 } 1888 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { 1889 goto full; 1890 } 1891 c = &entries[cpuid_i++]; 1892 } 1893 break; 1894 default: 1895 c->function = i; 1896 c->flags = 0; 1897 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); 1898 if (!c->eax && !c->ebx && !c->ecx && !c->edx) { 1899 /* 1900 * KVM already returns all zeroes if a CPUID entry is missing, 1901 * so we can omit it and avoid hitting KVM's 80-entry limit. 1902 */ 1903 cpuid_i--; 1904 } 1905 break; 1906 } 1907 } 1908 1909 /* Call Centaur's CPUID instructions they are supported. */ 1910 if (env->cpuid_xlevel2 > 0) { 1911 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused); 1912 1913 for (i = 0xC0000000; i <= limit; i++) { 1914 j = 0; 1915 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { 1916 goto full; 1917 } 1918 c = &entries[cpuid_i++]; 1919 1920 c->function = i; 1921 c->flags = 0; 1922 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); 1923 } 1924 } 1925 1926 return cpuid_i; 1927 1928 full: 1929 fprintf(stderr, "cpuid_data is full, no space for " 1930 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j); 1931 abort(); 1932 } 1933 1934 int kvm_arch_init_vcpu(CPUState *cs) 1935 { 1936 struct { 1937 struct kvm_cpuid2 cpuid; 1938 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES]; 1939 } cpuid_data; 1940 /* 1941 * The kernel defines these structs with padding fields so there 1942 * should be no extra padding in our cpuid_data struct. 1943 */ 1944 QEMU_BUILD_BUG_ON(sizeof(cpuid_data) != 1945 sizeof(struct kvm_cpuid2) + 1946 sizeof(struct kvm_cpuid_entry2) * KVM_MAX_CPUID_ENTRIES); 1947 1948 X86CPU *cpu = X86_CPU(cs); 1949 CPUX86State *env = &cpu->env; 1950 uint32_t cpuid_i; 1951 struct kvm_cpuid_entry2 *c; 1952 uint32_t signature[3]; 1953 int kvm_base = KVM_CPUID_SIGNATURE; 1954 int max_nested_state_len; 1955 int r; 1956 Error *local_err = NULL; 1957 1958 memset(&cpuid_data, 0, sizeof(cpuid_data)); 1959 1960 cpuid_i = 0; 1961 1962 has_xsave2 = kvm_check_extension(cs->kvm_state, KVM_CAP_XSAVE2); 1963 1964 r = kvm_arch_set_tsc_khz(cs); 1965 if (r < 0) { 1966 return r; 1967 } 1968 1969 /* vcpu's TSC frequency is either specified by user, or following 1970 * the value used by KVM if the former is not present. In the 1971 * latter case, we query it from KVM and record in env->tsc_khz, 1972 * so that vcpu's TSC frequency can be migrated later via this field. 1973 */ 1974 if (!env->tsc_khz) { 1975 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ? 1976 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) : 1977 -ENOTSUP; 1978 if (r > 0) { 1979 env->tsc_khz = r; 1980 } 1981 } 1982 1983 env->apic_bus_freq = KVM_APIC_BUS_FREQUENCY; 1984 1985 /* 1986 * kvm_hyperv_expand_features() is called here for the second time in case 1987 * KVM_CAP_SYS_HYPERV_CPUID is not supported. While we can't possibly handle 1988 * 'query-cpu-model-expansion' in this case as we don't have a KVM vCPU to 1989 * check which Hyper-V enlightenments are supported and which are not, we 1990 * can still proceed and check/expand Hyper-V enlightenments here so legacy 1991 * behavior is preserved. 1992 */ 1993 if (!kvm_hyperv_expand_features(cpu, &local_err)) { 1994 error_report_err(local_err); 1995 return -ENOSYS; 1996 } 1997 1998 if (hyperv_enabled(cpu)) { 1999 r = hyperv_init_vcpu(cpu); 2000 if (r) { 2001 return r; 2002 } 2003 2004 cpuid_i = hyperv_fill_cpuids(cs, cpuid_data.entries); 2005 kvm_base = KVM_CPUID_SIGNATURE_NEXT; 2006 has_msr_hv_hypercall = true; 2007 } 2008 2009 if (cs->kvm_state->xen_version) { 2010 #ifdef CONFIG_XEN_EMU 2011 struct kvm_cpuid_entry2 *xen_max_leaf; 2012 2013 memcpy(signature, "XenVMMXenVMM", 12); 2014 2015 xen_max_leaf = c = &cpuid_data.entries[cpuid_i++]; 2016 c->function = kvm_base + XEN_CPUID_SIGNATURE; 2017 c->eax = kvm_base + XEN_CPUID_TIME; 2018 c->ebx = signature[0]; 2019 c->ecx = signature[1]; 2020 c->edx = signature[2]; 2021 2022 c = &cpuid_data.entries[cpuid_i++]; 2023 c->function = kvm_base + XEN_CPUID_VENDOR; 2024 c->eax = cs->kvm_state->xen_version; 2025 c->ebx = 0; 2026 c->ecx = 0; 2027 c->edx = 0; 2028 2029 c = &cpuid_data.entries[cpuid_i++]; 2030 c->function = kvm_base + XEN_CPUID_HVM_MSR; 2031 /* Number of hypercall-transfer pages */ 2032 c->eax = 1; 2033 /* Hypercall MSR base address */ 2034 if (hyperv_enabled(cpu)) { 2035 c->ebx = XEN_HYPERCALL_MSR_HYPERV; 2036 kvm_xen_init(cs->kvm_state, c->ebx); 2037 } else { 2038 c->ebx = XEN_HYPERCALL_MSR; 2039 } 2040 c->ecx = 0; 2041 c->edx = 0; 2042 2043 c = &cpuid_data.entries[cpuid_i++]; 2044 c->function = kvm_base + XEN_CPUID_TIME; 2045 c->eax = ((!!tsc_is_stable_and_known(env) << 1) | 2046 (!!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP) << 2)); 2047 /* default=0 (emulate if necessary) */ 2048 c->ebx = 0; 2049 /* guest tsc frequency */ 2050 c->ecx = env->user_tsc_khz; 2051 /* guest tsc incarnation (migration count) */ 2052 c->edx = 0; 2053 2054 c = &cpuid_data.entries[cpuid_i++]; 2055 c->function = kvm_base + XEN_CPUID_HVM; 2056 xen_max_leaf->eax = kvm_base + XEN_CPUID_HVM; 2057 if (cs->kvm_state->xen_version >= XEN_VERSION(4, 5)) { 2058 c->function = kvm_base + XEN_CPUID_HVM; 2059 2060 if (cpu->xen_vapic) { 2061 c->eax |= XEN_HVM_CPUID_APIC_ACCESS_VIRT; 2062 c->eax |= XEN_HVM_CPUID_X2APIC_VIRT; 2063 } 2064 2065 c->eax |= XEN_HVM_CPUID_IOMMU_MAPPINGS; 2066 2067 if (cs->kvm_state->xen_version >= XEN_VERSION(4, 6)) { 2068 c->eax |= XEN_HVM_CPUID_VCPU_ID_PRESENT; 2069 c->ebx = cs->cpu_index; 2070 } 2071 2072 if (cs->kvm_state->xen_version >= XEN_VERSION(4, 17)) { 2073 c->eax |= XEN_HVM_CPUID_UPCALL_VECTOR; 2074 } 2075 } 2076 2077 r = kvm_xen_init_vcpu(cs); 2078 if (r) { 2079 return r; 2080 } 2081 2082 kvm_base += 0x100; 2083 #else /* CONFIG_XEN_EMU */ 2084 /* This should never happen as kvm_arch_init() would have died first. */ 2085 fprintf(stderr, "Cannot enable Xen CPUID without Xen support\n"); 2086 abort(); 2087 #endif 2088 } else if (cpu->expose_kvm) { 2089 memcpy(signature, "KVMKVMKVM\0\0\0", 12); 2090 c = &cpuid_data.entries[cpuid_i++]; 2091 c->function = KVM_CPUID_SIGNATURE | kvm_base; 2092 c->eax = KVM_CPUID_FEATURES | kvm_base; 2093 c->ebx = signature[0]; 2094 c->ecx = signature[1]; 2095 c->edx = signature[2]; 2096 2097 c = &cpuid_data.entries[cpuid_i++]; 2098 c->function = KVM_CPUID_FEATURES | kvm_base; 2099 c->eax = env->features[FEAT_KVM]; 2100 c->edx = env->features[FEAT_KVM_HINTS]; 2101 } 2102 2103 if (cpu->kvm_pv_enforce_cpuid) { 2104 r = kvm_vcpu_enable_cap(cs, KVM_CAP_ENFORCE_PV_FEATURE_CPUID, 0, 1); 2105 if (r < 0) { 2106 fprintf(stderr, 2107 "failed to enable KVM_CAP_ENFORCE_PV_FEATURE_CPUID: %s", 2108 strerror(-r)); 2109 abort(); 2110 } 2111 } 2112 2113 cpuid_i = kvm_x86_build_cpuid(env, cpuid_data.entries, cpuid_i); 2114 cpuid_data.cpuid.nent = cpuid_i; 2115 2116 if (((env->cpuid_version >> 8)&0xF) >= 6 2117 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == 2118 (CPUID_MCE | CPUID_MCA)) { 2119 uint64_t mcg_cap, unsupported_caps; 2120 int banks; 2121 int ret; 2122 2123 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks); 2124 if (ret < 0) { 2125 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret)); 2126 return ret; 2127 } 2128 2129 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) { 2130 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)", 2131 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks); 2132 return -ENOTSUP; 2133 } 2134 2135 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK); 2136 if (unsupported_caps) { 2137 if (unsupported_caps & MCG_LMCE_P) { 2138 error_report("kvm: LMCE not supported"); 2139 return -ENOTSUP; 2140 } 2141 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64, 2142 unsupported_caps); 2143 } 2144 2145 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK; 2146 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap); 2147 if (ret < 0) { 2148 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret)); 2149 return ret; 2150 } 2151 } 2152 2153 cpu->vmsentry = qemu_add_vm_change_state_handler(cpu_update_state, env); 2154 2155 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0); 2156 if (c) { 2157 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) || 2158 !!(c->ecx & CPUID_EXT_SMX); 2159 } 2160 2161 c = cpuid_find_entry(&cpuid_data.cpuid, 7, 0); 2162 if (c && (c->ebx & CPUID_7_0_EBX_SGX)) { 2163 has_msr_feature_control = true; 2164 } 2165 2166 if (env->mcg_cap & MCG_LMCE_P) { 2167 has_msr_mcg_ext_ctl = has_msr_feature_control = true; 2168 } 2169 2170 if (!env->user_tsc_khz) { 2171 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) && 2172 invtsc_mig_blocker == NULL) { 2173 error_setg(&invtsc_mig_blocker, 2174 "State blocked by non-migratable CPU device" 2175 " (invtsc flag)"); 2176 r = migrate_add_blocker(&invtsc_mig_blocker, &local_err); 2177 if (r < 0) { 2178 error_report_err(local_err); 2179 return r; 2180 } 2181 } 2182 } 2183 2184 if (cpu->vmware_cpuid_freq 2185 /* Guests depend on 0x40000000 to detect this feature, so only expose 2186 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */ 2187 && cpu->expose_kvm 2188 && kvm_base == KVM_CPUID_SIGNATURE 2189 /* TSC clock must be stable and known for this feature. */ 2190 && tsc_is_stable_and_known(env)) { 2191 2192 c = &cpuid_data.entries[cpuid_i++]; 2193 c->function = KVM_CPUID_SIGNATURE | 0x10; 2194 c->eax = env->tsc_khz; 2195 c->ebx = env->apic_bus_freq / 1000; /* Hz to KHz */ 2196 c->ecx = c->edx = 0; 2197 2198 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0); 2199 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10); 2200 } 2201 2202 cpuid_data.cpuid.nent = cpuid_i; 2203 2204 cpuid_data.cpuid.padding = 0; 2205 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data); 2206 if (r) { 2207 goto fail; 2208 } 2209 kvm_init_xsave(env); 2210 2211 max_nested_state_len = kvm_max_nested_state_length(); 2212 if (max_nested_state_len > 0) { 2213 assert(max_nested_state_len >= offsetof(struct kvm_nested_state, data)); 2214 2215 if (cpu_has_vmx(env) || cpu_has_svm(env)) { 2216 env->nested_state = g_malloc0(max_nested_state_len); 2217 env->nested_state->size = max_nested_state_len; 2218 2219 kvm_init_nested_state(env); 2220 } 2221 } 2222 2223 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE); 2224 2225 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) { 2226 has_msr_tsc_aux = false; 2227 } 2228 2229 kvm_init_msrs(cpu); 2230 2231 return 0; 2232 2233 fail: 2234 migrate_del_blocker(&invtsc_mig_blocker); 2235 2236 return r; 2237 } 2238 2239 int kvm_arch_destroy_vcpu(CPUState *cs) 2240 { 2241 X86CPU *cpu = X86_CPU(cs); 2242 CPUX86State *env = &cpu->env; 2243 2244 g_free(env->xsave_buf); 2245 2246 g_free(cpu->kvm_msr_buf); 2247 cpu->kvm_msr_buf = NULL; 2248 2249 g_free(env->nested_state); 2250 env->nested_state = NULL; 2251 2252 qemu_del_vm_change_state_handler(cpu->vmsentry); 2253 2254 return 0; 2255 } 2256 2257 void kvm_arch_reset_vcpu(X86CPU *cpu) 2258 { 2259 CPUX86State *env = &cpu->env; 2260 2261 env->xcr0 = 1; 2262 if (kvm_irqchip_in_kernel()) { 2263 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE : 2264 KVM_MP_STATE_UNINITIALIZED; 2265 } else { 2266 env->mp_state = KVM_MP_STATE_RUNNABLE; 2267 } 2268 2269 /* enabled by default */ 2270 env->poll_control_msr = 1; 2271 2272 kvm_init_nested_state(env); 2273 2274 sev_es_set_reset_vector(CPU(cpu)); 2275 } 2276 2277 void kvm_arch_after_reset_vcpu(X86CPU *cpu) 2278 { 2279 CPUX86State *env = &cpu->env; 2280 int i; 2281 2282 /* 2283 * Reset SynIC after all other devices have been reset to let them remove 2284 * their SINT routes first. 2285 */ 2286 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) { 2287 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) { 2288 env->msr_hv_synic_sint[i] = HV_SINT_MASKED; 2289 } 2290 2291 hyperv_x86_synic_reset(cpu); 2292 } 2293 } 2294 2295 void kvm_arch_do_init_vcpu(X86CPU *cpu) 2296 { 2297 CPUX86State *env = &cpu->env; 2298 2299 /* APs get directly into wait-for-SIPI state. */ 2300 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) { 2301 env->mp_state = KVM_MP_STATE_INIT_RECEIVED; 2302 } 2303 } 2304 2305 static int kvm_get_supported_feature_msrs(KVMState *s) 2306 { 2307 int ret = 0; 2308 2309 if (kvm_feature_msrs != NULL) { 2310 return 0; 2311 } 2312 2313 if (!kvm_check_extension(s, KVM_CAP_GET_MSR_FEATURES)) { 2314 return 0; 2315 } 2316 2317 struct kvm_msr_list msr_list; 2318 2319 msr_list.nmsrs = 0; 2320 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, &msr_list); 2321 if (ret < 0 && ret != -E2BIG) { 2322 error_report("Fetch KVM feature MSR list failed: %s", 2323 strerror(-ret)); 2324 return ret; 2325 } 2326 2327 assert(msr_list.nmsrs > 0); 2328 kvm_feature_msrs = g_malloc0(sizeof(msr_list) + 2329 msr_list.nmsrs * sizeof(msr_list.indices[0])); 2330 2331 kvm_feature_msrs->nmsrs = msr_list.nmsrs; 2332 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, kvm_feature_msrs); 2333 2334 if (ret < 0) { 2335 error_report("Fetch KVM feature MSR list failed: %s", 2336 strerror(-ret)); 2337 g_free(kvm_feature_msrs); 2338 kvm_feature_msrs = NULL; 2339 return ret; 2340 } 2341 2342 return 0; 2343 } 2344 2345 static int kvm_get_supported_msrs(KVMState *s) 2346 { 2347 int ret = 0; 2348 struct kvm_msr_list msr_list, *kvm_msr_list; 2349 2350 /* 2351 * Obtain MSR list from KVM. These are the MSRs that we must 2352 * save/restore. 2353 */ 2354 msr_list.nmsrs = 0; 2355 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list); 2356 if (ret < 0 && ret != -E2BIG) { 2357 return ret; 2358 } 2359 /* 2360 * Old kernel modules had a bug and could write beyond the provided 2361 * memory. Allocate at least a safe amount of 1K. 2362 */ 2363 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) + 2364 msr_list.nmsrs * 2365 sizeof(msr_list.indices[0]))); 2366 2367 kvm_msr_list->nmsrs = msr_list.nmsrs; 2368 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list); 2369 if (ret >= 0) { 2370 int i; 2371 2372 for (i = 0; i < kvm_msr_list->nmsrs; i++) { 2373 switch (kvm_msr_list->indices[i]) { 2374 case MSR_STAR: 2375 has_msr_star = true; 2376 break; 2377 case MSR_VM_HSAVE_PA: 2378 has_msr_hsave_pa = true; 2379 break; 2380 case MSR_TSC_AUX: 2381 has_msr_tsc_aux = true; 2382 break; 2383 case MSR_TSC_ADJUST: 2384 has_msr_tsc_adjust = true; 2385 break; 2386 case MSR_IA32_TSCDEADLINE: 2387 has_msr_tsc_deadline = true; 2388 break; 2389 case MSR_IA32_SMBASE: 2390 has_msr_smbase = true; 2391 break; 2392 case MSR_SMI_COUNT: 2393 has_msr_smi_count = true; 2394 break; 2395 case MSR_IA32_MISC_ENABLE: 2396 has_msr_misc_enable = true; 2397 break; 2398 case MSR_IA32_BNDCFGS: 2399 has_msr_bndcfgs = true; 2400 break; 2401 case MSR_IA32_XSS: 2402 has_msr_xss = true; 2403 break; 2404 case MSR_IA32_UMWAIT_CONTROL: 2405 has_msr_umwait = true; 2406 break; 2407 case HV_X64_MSR_CRASH_CTL: 2408 has_msr_hv_crash = true; 2409 break; 2410 case HV_X64_MSR_RESET: 2411 has_msr_hv_reset = true; 2412 break; 2413 case HV_X64_MSR_VP_INDEX: 2414 has_msr_hv_vpindex = true; 2415 break; 2416 case HV_X64_MSR_VP_RUNTIME: 2417 has_msr_hv_runtime = true; 2418 break; 2419 case HV_X64_MSR_SCONTROL: 2420 has_msr_hv_synic = true; 2421 break; 2422 case HV_X64_MSR_STIMER0_CONFIG: 2423 has_msr_hv_stimer = true; 2424 break; 2425 case HV_X64_MSR_TSC_FREQUENCY: 2426 has_msr_hv_frequencies = true; 2427 break; 2428 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 2429 has_msr_hv_reenlightenment = true; 2430 break; 2431 case HV_X64_MSR_SYNDBG_OPTIONS: 2432 has_msr_hv_syndbg_options = true; 2433 break; 2434 case MSR_IA32_SPEC_CTRL: 2435 has_msr_spec_ctrl = true; 2436 break; 2437 case MSR_AMD64_TSC_RATIO: 2438 has_tsc_scale_msr = true; 2439 break; 2440 case MSR_IA32_TSX_CTRL: 2441 has_msr_tsx_ctrl = true; 2442 break; 2443 case MSR_VIRT_SSBD: 2444 has_msr_virt_ssbd = true; 2445 break; 2446 case MSR_IA32_ARCH_CAPABILITIES: 2447 has_msr_arch_capabs = true; 2448 break; 2449 case MSR_IA32_CORE_CAPABILITY: 2450 has_msr_core_capabs = true; 2451 break; 2452 case MSR_IA32_PERF_CAPABILITIES: 2453 has_msr_perf_capabs = true; 2454 break; 2455 case MSR_IA32_VMX_VMFUNC: 2456 has_msr_vmx_vmfunc = true; 2457 break; 2458 case MSR_IA32_UCODE_REV: 2459 has_msr_ucode_rev = true; 2460 break; 2461 case MSR_IA32_VMX_PROCBASED_CTLS2: 2462 has_msr_vmx_procbased_ctls2 = true; 2463 break; 2464 case MSR_IA32_PKRS: 2465 has_msr_pkrs = true; 2466 break; 2467 } 2468 } 2469 } 2470 2471 g_free(kvm_msr_list); 2472 2473 return ret; 2474 } 2475 2476 static bool kvm_rdmsr_core_thread_count(X86CPU *cpu, uint32_t msr, 2477 uint64_t *val) 2478 { 2479 CPUState *cs = CPU(cpu); 2480 2481 *val = cs->nr_threads * cs->nr_cores; /* thread count, bits 15..0 */ 2482 *val |= ((uint32_t)cs->nr_cores << 16); /* core count, bits 31..16 */ 2483 2484 return true; 2485 } 2486 2487 static Notifier smram_machine_done; 2488 static KVMMemoryListener smram_listener; 2489 static AddressSpace smram_address_space; 2490 static MemoryRegion smram_as_root; 2491 static MemoryRegion smram_as_mem; 2492 2493 static void register_smram_listener(Notifier *n, void *unused) 2494 { 2495 MemoryRegion *smram = 2496 (MemoryRegion *) object_resolve_path("/machine/smram", NULL); 2497 2498 /* Outer container... */ 2499 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull); 2500 memory_region_set_enabled(&smram_as_root, true); 2501 2502 /* ... with two regions inside: normal system memory with low 2503 * priority, and... 2504 */ 2505 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram", 2506 get_system_memory(), 0, ~0ull); 2507 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0); 2508 memory_region_set_enabled(&smram_as_mem, true); 2509 2510 if (smram) { 2511 /* ... SMRAM with higher priority */ 2512 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10); 2513 memory_region_set_enabled(smram, true); 2514 } 2515 2516 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM"); 2517 kvm_memory_listener_register(kvm_state, &smram_listener, 2518 &smram_address_space, 1, "kvm-smram"); 2519 } 2520 2521 int kvm_arch_get_default_type(MachineState *ms) 2522 { 2523 return 0; 2524 } 2525 2526 int kvm_arch_init(MachineState *ms, KVMState *s) 2527 { 2528 uint64_t identity_base = 0xfffbc000; 2529 uint64_t shadow_mem; 2530 int ret; 2531 struct utsname utsname; 2532 Error *local_err = NULL; 2533 2534 /* 2535 * Initialize SEV context, if required 2536 * 2537 * If no memory encryption is requested (ms->cgs == NULL) this is 2538 * a no-op. 2539 * 2540 * It's also a no-op if a non-SEV confidential guest support 2541 * mechanism is selected. SEV is the only mechanism available to 2542 * select on x86 at present, so this doesn't arise, but if new 2543 * mechanisms are supported in future (e.g. TDX), they'll need 2544 * their own initialization either here or elsewhere. 2545 */ 2546 if (ms->cgs) { 2547 ret = confidential_guest_kvm_init(ms->cgs, &local_err); 2548 if (ret < 0) { 2549 error_report_err(local_err); 2550 return ret; 2551 } 2552 } 2553 2554 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS); 2555 has_sregs2 = kvm_check_extension(s, KVM_CAP_SREGS2) > 0; 2556 2557 hv_vpindex_settable = kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX); 2558 2559 has_exception_payload = kvm_check_extension(s, KVM_CAP_EXCEPTION_PAYLOAD); 2560 if (has_exception_payload) { 2561 ret = kvm_vm_enable_cap(s, KVM_CAP_EXCEPTION_PAYLOAD, 0, true); 2562 if (ret < 0) { 2563 error_report("kvm: Failed to enable exception payload cap: %s", 2564 strerror(-ret)); 2565 return ret; 2566 } 2567 } 2568 2569 has_triple_fault_event = kvm_check_extension(s, KVM_CAP_X86_TRIPLE_FAULT_EVENT); 2570 if (has_triple_fault_event) { 2571 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_TRIPLE_FAULT_EVENT, 0, true); 2572 if (ret < 0) { 2573 error_report("kvm: Failed to enable triple fault event cap: %s", 2574 strerror(-ret)); 2575 return ret; 2576 } 2577 } 2578 2579 if (s->xen_version) { 2580 #ifdef CONFIG_XEN_EMU 2581 if (!object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE)) { 2582 error_report("kvm: Xen support only available in PC machine"); 2583 return -ENOTSUP; 2584 } 2585 /* hyperv_enabled() doesn't work yet. */ 2586 uint32_t msr = XEN_HYPERCALL_MSR; 2587 ret = kvm_xen_init(s, msr); 2588 if (ret < 0) { 2589 return ret; 2590 } 2591 #else 2592 error_report("kvm: Xen support not enabled in qemu"); 2593 return -ENOTSUP; 2594 #endif 2595 } 2596 2597 ret = kvm_get_supported_msrs(s); 2598 if (ret < 0) { 2599 return ret; 2600 } 2601 2602 kvm_get_supported_feature_msrs(s); 2603 2604 uname(&utsname); 2605 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0; 2606 2607 /* 2608 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly. 2609 * In order to use vm86 mode, an EPT identity map and a TSS are needed. 2610 * Since these must be part of guest physical memory, we need to allocate 2611 * them, both by setting their start addresses in the kernel and by 2612 * creating a corresponding e820 entry. We need 4 pages before the BIOS, 2613 * so this value allows up to 16M BIOSes. 2614 */ 2615 identity_base = 0xfeffc000; 2616 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base); 2617 if (ret < 0) { 2618 return ret; 2619 } 2620 2621 /* Set TSS base one page after EPT identity map. */ 2622 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000); 2623 if (ret < 0) { 2624 return ret; 2625 } 2626 2627 /* Tell fw_cfg to notify the BIOS to reserve the range. */ 2628 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED); 2629 if (ret < 0) { 2630 fprintf(stderr, "e820_add_entry() table is full\n"); 2631 return ret; 2632 } 2633 2634 shadow_mem = object_property_get_int(OBJECT(s), "kvm-shadow-mem", &error_abort); 2635 if (shadow_mem != -1) { 2636 shadow_mem /= 4096; 2637 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem); 2638 if (ret < 0) { 2639 return ret; 2640 } 2641 } 2642 2643 if (kvm_check_extension(s, KVM_CAP_X86_SMM) && 2644 object_dynamic_cast(OBJECT(ms), TYPE_X86_MACHINE) && 2645 x86_machine_is_smm_enabled(X86_MACHINE(ms))) { 2646 smram_machine_done.notify = register_smram_listener; 2647 qemu_add_machine_init_done_notifier(&smram_machine_done); 2648 } 2649 2650 if (enable_cpu_pm) { 2651 int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS); 2652 /* Work around for kernel header with a typo. TODO: fix header and drop. */ 2653 #if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT) 2654 #define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL 2655 #endif 2656 if (disable_exits) { 2657 disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT | 2658 KVM_X86_DISABLE_EXITS_HLT | 2659 KVM_X86_DISABLE_EXITS_PAUSE | 2660 KVM_X86_DISABLE_EXITS_CSTATE); 2661 } 2662 2663 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0, 2664 disable_exits); 2665 if (ret < 0) { 2666 error_report("kvm: guest stopping CPU not supported: %s", 2667 strerror(-ret)); 2668 } 2669 } 2670 2671 if (object_dynamic_cast(OBJECT(ms), TYPE_X86_MACHINE)) { 2672 X86MachineState *x86ms = X86_MACHINE(ms); 2673 2674 if (x86ms->bus_lock_ratelimit > 0) { 2675 ret = kvm_check_extension(s, KVM_CAP_X86_BUS_LOCK_EXIT); 2676 if (!(ret & KVM_BUS_LOCK_DETECTION_EXIT)) { 2677 error_report("kvm: bus lock detection unsupported"); 2678 return -ENOTSUP; 2679 } 2680 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_BUS_LOCK_EXIT, 0, 2681 KVM_BUS_LOCK_DETECTION_EXIT); 2682 if (ret < 0) { 2683 error_report("kvm: Failed to enable bus lock detection cap: %s", 2684 strerror(-ret)); 2685 return ret; 2686 } 2687 ratelimit_init(&bus_lock_ratelimit_ctrl); 2688 ratelimit_set_speed(&bus_lock_ratelimit_ctrl, 2689 x86ms->bus_lock_ratelimit, BUS_LOCK_SLICE_TIME); 2690 } 2691 } 2692 2693 if (s->notify_vmexit != NOTIFY_VMEXIT_OPTION_DISABLE && 2694 kvm_check_extension(s, KVM_CAP_X86_NOTIFY_VMEXIT)) { 2695 uint64_t notify_window_flags = 2696 ((uint64_t)s->notify_window << 32) | 2697 KVM_X86_NOTIFY_VMEXIT_ENABLED | 2698 KVM_X86_NOTIFY_VMEXIT_USER; 2699 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_NOTIFY_VMEXIT, 0, 2700 notify_window_flags); 2701 if (ret < 0) { 2702 error_report("kvm: Failed to enable notify vmexit cap: %s", 2703 strerror(-ret)); 2704 return ret; 2705 } 2706 } 2707 if (kvm_vm_check_extension(s, KVM_CAP_X86_USER_SPACE_MSR)) { 2708 bool r; 2709 2710 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_USER_SPACE_MSR, 0, 2711 KVM_MSR_EXIT_REASON_FILTER); 2712 if (ret) { 2713 error_report("Could not enable user space MSRs: %s", 2714 strerror(-ret)); 2715 exit(1); 2716 } 2717 2718 r = kvm_filter_msr(s, MSR_CORE_THREAD_COUNT, 2719 kvm_rdmsr_core_thread_count, NULL); 2720 if (!r) { 2721 error_report("Could not install MSR_CORE_THREAD_COUNT handler: %s", 2722 strerror(-ret)); 2723 exit(1); 2724 } 2725 } 2726 2727 return 0; 2728 } 2729 2730 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs) 2731 { 2732 lhs->selector = rhs->selector; 2733 lhs->base = rhs->base; 2734 lhs->limit = rhs->limit; 2735 lhs->type = 3; 2736 lhs->present = 1; 2737 lhs->dpl = 3; 2738 lhs->db = 0; 2739 lhs->s = 1; 2740 lhs->l = 0; 2741 lhs->g = 0; 2742 lhs->avl = 0; 2743 lhs->unusable = 0; 2744 } 2745 2746 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs) 2747 { 2748 unsigned flags = rhs->flags; 2749 lhs->selector = rhs->selector; 2750 lhs->base = rhs->base; 2751 lhs->limit = rhs->limit; 2752 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15; 2753 lhs->present = (flags & DESC_P_MASK) != 0; 2754 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3; 2755 lhs->db = (flags >> DESC_B_SHIFT) & 1; 2756 lhs->s = (flags & DESC_S_MASK) != 0; 2757 lhs->l = (flags >> DESC_L_SHIFT) & 1; 2758 lhs->g = (flags & DESC_G_MASK) != 0; 2759 lhs->avl = (flags & DESC_AVL_MASK) != 0; 2760 lhs->unusable = !lhs->present; 2761 lhs->padding = 0; 2762 } 2763 2764 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs) 2765 { 2766 lhs->selector = rhs->selector; 2767 lhs->base = rhs->base; 2768 lhs->limit = rhs->limit; 2769 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) | 2770 ((rhs->present && !rhs->unusable) * DESC_P_MASK) | 2771 (rhs->dpl << DESC_DPL_SHIFT) | 2772 (rhs->db << DESC_B_SHIFT) | 2773 (rhs->s * DESC_S_MASK) | 2774 (rhs->l << DESC_L_SHIFT) | 2775 (rhs->g * DESC_G_MASK) | 2776 (rhs->avl * DESC_AVL_MASK); 2777 } 2778 2779 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set) 2780 { 2781 if (set) { 2782 *kvm_reg = *qemu_reg; 2783 } else { 2784 *qemu_reg = *kvm_reg; 2785 } 2786 } 2787 2788 static int kvm_getput_regs(X86CPU *cpu, int set) 2789 { 2790 CPUX86State *env = &cpu->env; 2791 struct kvm_regs regs; 2792 int ret = 0; 2793 2794 if (!set) { 2795 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, ®s); 2796 if (ret < 0) { 2797 return ret; 2798 } 2799 } 2800 2801 kvm_getput_reg(®s.rax, &env->regs[R_EAX], set); 2802 kvm_getput_reg(®s.rbx, &env->regs[R_EBX], set); 2803 kvm_getput_reg(®s.rcx, &env->regs[R_ECX], set); 2804 kvm_getput_reg(®s.rdx, &env->regs[R_EDX], set); 2805 kvm_getput_reg(®s.rsi, &env->regs[R_ESI], set); 2806 kvm_getput_reg(®s.rdi, &env->regs[R_EDI], set); 2807 kvm_getput_reg(®s.rsp, &env->regs[R_ESP], set); 2808 kvm_getput_reg(®s.rbp, &env->regs[R_EBP], set); 2809 #ifdef TARGET_X86_64 2810 kvm_getput_reg(®s.r8, &env->regs[8], set); 2811 kvm_getput_reg(®s.r9, &env->regs[9], set); 2812 kvm_getput_reg(®s.r10, &env->regs[10], set); 2813 kvm_getput_reg(®s.r11, &env->regs[11], set); 2814 kvm_getput_reg(®s.r12, &env->regs[12], set); 2815 kvm_getput_reg(®s.r13, &env->regs[13], set); 2816 kvm_getput_reg(®s.r14, &env->regs[14], set); 2817 kvm_getput_reg(®s.r15, &env->regs[15], set); 2818 #endif 2819 2820 kvm_getput_reg(®s.rflags, &env->eflags, set); 2821 kvm_getput_reg(®s.rip, &env->eip, set); 2822 2823 if (set) { 2824 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, ®s); 2825 } 2826 2827 return ret; 2828 } 2829 2830 static int kvm_put_xsave(X86CPU *cpu) 2831 { 2832 CPUX86State *env = &cpu->env; 2833 void *xsave = env->xsave_buf; 2834 2835 x86_cpu_xsave_all_areas(cpu, xsave, env->xsave_buf_len); 2836 2837 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave); 2838 } 2839 2840 static int kvm_put_xcrs(X86CPU *cpu) 2841 { 2842 CPUX86State *env = &cpu->env; 2843 struct kvm_xcrs xcrs = {}; 2844 2845 if (!has_xcrs) { 2846 return 0; 2847 } 2848 2849 xcrs.nr_xcrs = 1; 2850 xcrs.flags = 0; 2851 xcrs.xcrs[0].xcr = 0; 2852 xcrs.xcrs[0].value = env->xcr0; 2853 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs); 2854 } 2855 2856 static int kvm_put_sregs(X86CPU *cpu) 2857 { 2858 CPUX86State *env = &cpu->env; 2859 struct kvm_sregs sregs; 2860 2861 /* 2862 * The interrupt_bitmap is ignored because KVM_SET_SREGS is 2863 * always followed by KVM_SET_VCPU_EVENTS. 2864 */ 2865 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap)); 2866 2867 if ((env->eflags & VM_MASK)) { 2868 set_v8086_seg(&sregs.cs, &env->segs[R_CS]); 2869 set_v8086_seg(&sregs.ds, &env->segs[R_DS]); 2870 set_v8086_seg(&sregs.es, &env->segs[R_ES]); 2871 set_v8086_seg(&sregs.fs, &env->segs[R_FS]); 2872 set_v8086_seg(&sregs.gs, &env->segs[R_GS]); 2873 set_v8086_seg(&sregs.ss, &env->segs[R_SS]); 2874 } else { 2875 set_seg(&sregs.cs, &env->segs[R_CS]); 2876 set_seg(&sregs.ds, &env->segs[R_DS]); 2877 set_seg(&sregs.es, &env->segs[R_ES]); 2878 set_seg(&sregs.fs, &env->segs[R_FS]); 2879 set_seg(&sregs.gs, &env->segs[R_GS]); 2880 set_seg(&sregs.ss, &env->segs[R_SS]); 2881 } 2882 2883 set_seg(&sregs.tr, &env->tr); 2884 set_seg(&sregs.ldt, &env->ldt); 2885 2886 sregs.idt.limit = env->idt.limit; 2887 sregs.idt.base = env->idt.base; 2888 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding); 2889 sregs.gdt.limit = env->gdt.limit; 2890 sregs.gdt.base = env->gdt.base; 2891 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding); 2892 2893 sregs.cr0 = env->cr[0]; 2894 sregs.cr2 = env->cr[2]; 2895 sregs.cr3 = env->cr[3]; 2896 sregs.cr4 = env->cr[4]; 2897 2898 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state); 2899 sregs.apic_base = cpu_get_apic_base(cpu->apic_state); 2900 2901 sregs.efer = env->efer; 2902 2903 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs); 2904 } 2905 2906 static int kvm_put_sregs2(X86CPU *cpu) 2907 { 2908 CPUX86State *env = &cpu->env; 2909 struct kvm_sregs2 sregs; 2910 int i; 2911 2912 sregs.flags = 0; 2913 2914 if ((env->eflags & VM_MASK)) { 2915 set_v8086_seg(&sregs.cs, &env->segs[R_CS]); 2916 set_v8086_seg(&sregs.ds, &env->segs[R_DS]); 2917 set_v8086_seg(&sregs.es, &env->segs[R_ES]); 2918 set_v8086_seg(&sregs.fs, &env->segs[R_FS]); 2919 set_v8086_seg(&sregs.gs, &env->segs[R_GS]); 2920 set_v8086_seg(&sregs.ss, &env->segs[R_SS]); 2921 } else { 2922 set_seg(&sregs.cs, &env->segs[R_CS]); 2923 set_seg(&sregs.ds, &env->segs[R_DS]); 2924 set_seg(&sregs.es, &env->segs[R_ES]); 2925 set_seg(&sregs.fs, &env->segs[R_FS]); 2926 set_seg(&sregs.gs, &env->segs[R_GS]); 2927 set_seg(&sregs.ss, &env->segs[R_SS]); 2928 } 2929 2930 set_seg(&sregs.tr, &env->tr); 2931 set_seg(&sregs.ldt, &env->ldt); 2932 2933 sregs.idt.limit = env->idt.limit; 2934 sregs.idt.base = env->idt.base; 2935 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding); 2936 sregs.gdt.limit = env->gdt.limit; 2937 sregs.gdt.base = env->gdt.base; 2938 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding); 2939 2940 sregs.cr0 = env->cr[0]; 2941 sregs.cr2 = env->cr[2]; 2942 sregs.cr3 = env->cr[3]; 2943 sregs.cr4 = env->cr[4]; 2944 2945 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state); 2946 sregs.apic_base = cpu_get_apic_base(cpu->apic_state); 2947 2948 sregs.efer = env->efer; 2949 2950 if (env->pdptrs_valid) { 2951 for (i = 0; i < 4; i++) { 2952 sregs.pdptrs[i] = env->pdptrs[i]; 2953 } 2954 sregs.flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID; 2955 } 2956 2957 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS2, &sregs); 2958 } 2959 2960 2961 static void kvm_msr_buf_reset(X86CPU *cpu) 2962 { 2963 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE); 2964 } 2965 2966 static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value) 2967 { 2968 struct kvm_msrs *msrs = cpu->kvm_msr_buf; 2969 void *limit = ((void *)msrs) + MSR_BUF_SIZE; 2970 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs]; 2971 2972 assert((void *)(entry + 1) <= limit); 2973 2974 entry->index = index; 2975 entry->reserved = 0; 2976 entry->data = value; 2977 msrs->nmsrs++; 2978 } 2979 2980 static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value) 2981 { 2982 kvm_msr_buf_reset(cpu); 2983 kvm_msr_entry_add(cpu, index, value); 2984 2985 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf); 2986 } 2987 2988 static int kvm_get_one_msr(X86CPU *cpu, int index, uint64_t *value) 2989 { 2990 int ret; 2991 struct { 2992 struct kvm_msrs info; 2993 struct kvm_msr_entry entries[1]; 2994 } msr_data = { 2995 .info.nmsrs = 1, 2996 .entries[0].index = index, 2997 }; 2998 2999 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data); 3000 if (ret < 0) { 3001 return ret; 3002 } 3003 assert(ret == 1); 3004 *value = msr_data.entries[0].data; 3005 return ret; 3006 } 3007 void kvm_put_apicbase(X86CPU *cpu, uint64_t value) 3008 { 3009 int ret; 3010 3011 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value); 3012 assert(ret == 1); 3013 } 3014 3015 static int kvm_put_tscdeadline_msr(X86CPU *cpu) 3016 { 3017 CPUX86State *env = &cpu->env; 3018 int ret; 3019 3020 if (!has_msr_tsc_deadline) { 3021 return 0; 3022 } 3023 3024 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline); 3025 if (ret < 0) { 3026 return ret; 3027 } 3028 3029 assert(ret == 1); 3030 return 0; 3031 } 3032 3033 /* 3034 * Provide a separate write service for the feature control MSR in order to 3035 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done 3036 * before writing any other state because forcibly leaving nested mode 3037 * invalidates the VCPU state. 3038 */ 3039 static int kvm_put_msr_feature_control(X86CPU *cpu) 3040 { 3041 int ret; 3042 3043 if (!has_msr_feature_control) { 3044 return 0; 3045 } 3046 3047 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL, 3048 cpu->env.msr_ia32_feature_control); 3049 if (ret < 0) { 3050 return ret; 3051 } 3052 3053 assert(ret == 1); 3054 return 0; 3055 } 3056 3057 static uint64_t make_vmx_msr_value(uint32_t index, uint32_t features) 3058 { 3059 uint32_t default1, can_be_one, can_be_zero; 3060 uint32_t must_be_one; 3061 3062 switch (index) { 3063 case MSR_IA32_VMX_TRUE_PINBASED_CTLS: 3064 default1 = 0x00000016; 3065 break; 3066 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: 3067 default1 = 0x0401e172; 3068 break; 3069 case MSR_IA32_VMX_TRUE_ENTRY_CTLS: 3070 default1 = 0x000011ff; 3071 break; 3072 case MSR_IA32_VMX_TRUE_EXIT_CTLS: 3073 default1 = 0x00036dff; 3074 break; 3075 case MSR_IA32_VMX_PROCBASED_CTLS2: 3076 default1 = 0; 3077 break; 3078 default: 3079 abort(); 3080 } 3081 3082 /* If a feature bit is set, the control can be either set or clear. 3083 * Otherwise the value is limited to either 0 or 1 by default1. 3084 */ 3085 can_be_one = features | default1; 3086 can_be_zero = features | ~default1; 3087 must_be_one = ~can_be_zero; 3088 3089 /* 3090 * Bit 0:31 -> 0 if the control bit can be zero (i.e. 1 if it must be one). 3091 * Bit 32:63 -> 1 if the control bit can be one. 3092 */ 3093 return must_be_one | (((uint64_t)can_be_one) << 32); 3094 } 3095 3096 static void kvm_msr_entry_add_vmx(X86CPU *cpu, FeatureWordArray f) 3097 { 3098 uint64_t kvm_vmx_basic = 3099 kvm_arch_get_supported_msr_feature(kvm_state, 3100 MSR_IA32_VMX_BASIC); 3101 3102 if (!kvm_vmx_basic) { 3103 /* If the kernel doesn't support VMX feature (kvm_intel.nested=0), 3104 * then kvm_vmx_basic will be 0 and KVM_SET_MSR will fail. 3105 */ 3106 return; 3107 } 3108 3109 uint64_t kvm_vmx_misc = 3110 kvm_arch_get_supported_msr_feature(kvm_state, 3111 MSR_IA32_VMX_MISC); 3112 uint64_t kvm_vmx_ept_vpid = 3113 kvm_arch_get_supported_msr_feature(kvm_state, 3114 MSR_IA32_VMX_EPT_VPID_CAP); 3115 3116 /* 3117 * If the guest is 64-bit, a value of 1 is allowed for the host address 3118 * space size vmexit control. 3119 */ 3120 uint64_t fixed_vmx_exit = f[FEAT_8000_0001_EDX] & CPUID_EXT2_LM 3121 ? (uint64_t)VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE << 32 : 0; 3122 3123 /* 3124 * Bits 0-30, 32-44 and 50-53 come from the host. KVM should 3125 * not change them for backwards compatibility. 3126 */ 3127 uint64_t fixed_vmx_basic = kvm_vmx_basic & 3128 (MSR_VMX_BASIC_VMCS_REVISION_MASK | 3129 MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK | 3130 MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK); 3131 3132 /* 3133 * Same for bits 0-4 and 25-27. Bits 16-24 (CR3 target count) can 3134 * change in the future but are always zero for now, clear them to be 3135 * future proof. Bits 32-63 in theory could change, though KVM does 3136 * not support dual-monitor treatment and probably never will; mask 3137 * them out as well. 3138 */ 3139 uint64_t fixed_vmx_misc = kvm_vmx_misc & 3140 (MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK | 3141 MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK); 3142 3143 /* 3144 * EPT memory types should not change either, so we do not bother 3145 * adding features for them. 3146 */ 3147 uint64_t fixed_vmx_ept_mask = 3148 (f[FEAT_VMX_SECONDARY_CTLS] & VMX_SECONDARY_EXEC_ENABLE_EPT ? 3149 MSR_VMX_EPT_UC | MSR_VMX_EPT_WB : 0); 3150 uint64_t fixed_vmx_ept_vpid = kvm_vmx_ept_vpid & fixed_vmx_ept_mask; 3151 3152 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 3153 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 3154 f[FEAT_VMX_PROCBASED_CTLS])); 3155 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PINBASED_CTLS, 3156 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PINBASED_CTLS, 3157 f[FEAT_VMX_PINBASED_CTLS])); 3158 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_EXIT_CTLS, 3159 make_vmx_msr_value(MSR_IA32_VMX_TRUE_EXIT_CTLS, 3160 f[FEAT_VMX_EXIT_CTLS]) | fixed_vmx_exit); 3161 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_ENTRY_CTLS, 3162 make_vmx_msr_value(MSR_IA32_VMX_TRUE_ENTRY_CTLS, 3163 f[FEAT_VMX_ENTRY_CTLS])); 3164 kvm_msr_entry_add(cpu, MSR_IA32_VMX_PROCBASED_CTLS2, 3165 make_vmx_msr_value(MSR_IA32_VMX_PROCBASED_CTLS2, 3166 f[FEAT_VMX_SECONDARY_CTLS])); 3167 kvm_msr_entry_add(cpu, MSR_IA32_VMX_EPT_VPID_CAP, 3168 f[FEAT_VMX_EPT_VPID_CAPS] | fixed_vmx_ept_vpid); 3169 kvm_msr_entry_add(cpu, MSR_IA32_VMX_BASIC, 3170 f[FEAT_VMX_BASIC] | fixed_vmx_basic); 3171 kvm_msr_entry_add(cpu, MSR_IA32_VMX_MISC, 3172 f[FEAT_VMX_MISC] | fixed_vmx_misc); 3173 if (has_msr_vmx_vmfunc) { 3174 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMFUNC, f[FEAT_VMX_VMFUNC]); 3175 } 3176 3177 /* 3178 * Just to be safe, write these with constant values. The CRn_FIXED1 3179 * MSRs are generated by KVM based on the vCPU's CPUID. 3180 */ 3181 kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR0_FIXED0, 3182 CR0_PE_MASK | CR0_PG_MASK | CR0_NE_MASK); 3183 kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR4_FIXED0, 3184 CR4_VMXE_MASK); 3185 3186 if (f[FEAT_VMX_SECONDARY_CTLS] & VMX_SECONDARY_EXEC_TSC_SCALING) { 3187 /* TSC multiplier (0x2032). */ 3188 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x32); 3189 } else { 3190 /* Preemption timer (0x482E). */ 3191 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x2E); 3192 } 3193 } 3194 3195 static void kvm_msr_entry_add_perf(X86CPU *cpu, FeatureWordArray f) 3196 { 3197 uint64_t kvm_perf_cap = 3198 kvm_arch_get_supported_msr_feature(kvm_state, 3199 MSR_IA32_PERF_CAPABILITIES); 3200 3201 if (kvm_perf_cap) { 3202 kvm_msr_entry_add(cpu, MSR_IA32_PERF_CAPABILITIES, 3203 kvm_perf_cap & f[FEAT_PERF_CAPABILITIES]); 3204 } 3205 } 3206 3207 static int kvm_buf_set_msrs(X86CPU *cpu) 3208 { 3209 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf); 3210 if (ret < 0) { 3211 return ret; 3212 } 3213 3214 if (ret < cpu->kvm_msr_buf->nmsrs) { 3215 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret]; 3216 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64, 3217 (uint32_t)e->index, (uint64_t)e->data); 3218 } 3219 3220 assert(ret == cpu->kvm_msr_buf->nmsrs); 3221 return 0; 3222 } 3223 3224 static void kvm_init_msrs(X86CPU *cpu) 3225 { 3226 CPUX86State *env = &cpu->env; 3227 3228 kvm_msr_buf_reset(cpu); 3229 if (has_msr_arch_capabs) { 3230 kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES, 3231 env->features[FEAT_ARCH_CAPABILITIES]); 3232 } 3233 3234 if (has_msr_core_capabs) { 3235 kvm_msr_entry_add(cpu, MSR_IA32_CORE_CAPABILITY, 3236 env->features[FEAT_CORE_CAPABILITY]); 3237 } 3238 3239 if (has_msr_perf_capabs && cpu->enable_pmu) { 3240 kvm_msr_entry_add_perf(cpu, env->features); 3241 } 3242 3243 if (has_msr_ucode_rev) { 3244 kvm_msr_entry_add(cpu, MSR_IA32_UCODE_REV, cpu->ucode_rev); 3245 } 3246 3247 /* 3248 * Older kernels do not include VMX MSRs in KVM_GET_MSR_INDEX_LIST, but 3249 * all kernels with MSR features should have them. 3250 */ 3251 if (kvm_feature_msrs && cpu_has_vmx(env)) { 3252 kvm_msr_entry_add_vmx(cpu, env->features); 3253 } 3254 3255 assert(kvm_buf_set_msrs(cpu) == 0); 3256 } 3257 3258 static int kvm_put_msrs(X86CPU *cpu, int level) 3259 { 3260 CPUX86State *env = &cpu->env; 3261 int i; 3262 3263 kvm_msr_buf_reset(cpu); 3264 3265 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs); 3266 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp); 3267 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip); 3268 kvm_msr_entry_add(cpu, MSR_PAT, env->pat); 3269 if (has_msr_star) { 3270 kvm_msr_entry_add(cpu, MSR_STAR, env->star); 3271 } 3272 if (has_msr_hsave_pa) { 3273 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave); 3274 } 3275 if (has_msr_tsc_aux) { 3276 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux); 3277 } 3278 if (has_msr_tsc_adjust) { 3279 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust); 3280 } 3281 if (has_msr_misc_enable) { 3282 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 3283 env->msr_ia32_misc_enable); 3284 } 3285 if (has_msr_smbase) { 3286 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase); 3287 } 3288 if (has_msr_smi_count) { 3289 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count); 3290 } 3291 if (has_msr_pkrs) { 3292 kvm_msr_entry_add(cpu, MSR_IA32_PKRS, env->pkrs); 3293 } 3294 if (has_msr_bndcfgs) { 3295 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs); 3296 } 3297 if (has_msr_xss) { 3298 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss); 3299 } 3300 if (has_msr_umwait) { 3301 kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, env->umwait); 3302 } 3303 if (has_msr_spec_ctrl) { 3304 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl); 3305 } 3306 if (has_tsc_scale_msr) { 3307 kvm_msr_entry_add(cpu, MSR_AMD64_TSC_RATIO, env->amd_tsc_scale_msr); 3308 } 3309 3310 if (has_msr_tsx_ctrl) { 3311 kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, env->tsx_ctrl); 3312 } 3313 if (has_msr_virt_ssbd) { 3314 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd); 3315 } 3316 3317 #ifdef TARGET_X86_64 3318 if (lm_capable_kernel) { 3319 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar); 3320 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase); 3321 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask); 3322 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar); 3323 } 3324 #endif 3325 3326 /* 3327 * The following MSRs have side effects on the guest or are too heavy 3328 * for normal writeback. Limit them to reset or full state updates. 3329 */ 3330 if (level >= KVM_PUT_RESET_STATE) { 3331 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc); 3332 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr); 3333 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr); 3334 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF_INT)) { 3335 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_INT, env->async_pf_int_msr); 3336 } 3337 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) { 3338 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr); 3339 } 3340 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) { 3341 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr); 3342 } 3343 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) { 3344 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr); 3345 } 3346 3347 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_POLL_CONTROL)) { 3348 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, env->poll_control_msr); 3349 } 3350 3351 if (has_architectural_pmu_version > 0) { 3352 if (has_architectural_pmu_version > 1) { 3353 /* Stop the counter. */ 3354 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0); 3355 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0); 3356 } 3357 3358 /* Set the counter values. */ 3359 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) { 3360 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 3361 env->msr_fixed_counters[i]); 3362 } 3363 for (i = 0; i < num_architectural_pmu_gp_counters; i++) { 3364 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 3365 env->msr_gp_counters[i]); 3366 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 3367 env->msr_gp_evtsel[i]); 3368 } 3369 if (has_architectural_pmu_version > 1) { 3370 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 3371 env->msr_global_status); 3372 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 3373 env->msr_global_ovf_ctrl); 3374 3375 /* Now start the PMU. */ 3376 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 3377 env->msr_fixed_ctr_ctrl); 3378 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 3379 env->msr_global_ctrl); 3380 } 3381 } 3382 /* 3383 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add, 3384 * only sync them to KVM on the first cpu 3385 */ 3386 if (current_cpu == first_cpu) { 3387 if (has_msr_hv_hypercall) { 3388 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 3389 env->msr_hv_guest_os_id); 3390 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 3391 env->msr_hv_hypercall); 3392 } 3393 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) { 3394 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 3395 env->msr_hv_tsc); 3396 } 3397 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) { 3398 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 3399 env->msr_hv_reenlightenment_control); 3400 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 3401 env->msr_hv_tsc_emulation_control); 3402 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 3403 env->msr_hv_tsc_emulation_status); 3404 } 3405 #ifdef CONFIG_SYNDBG 3406 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNDBG) && 3407 has_msr_hv_syndbg_options) { 3408 kvm_msr_entry_add(cpu, HV_X64_MSR_SYNDBG_OPTIONS, 3409 hyperv_syndbg_query_options()); 3410 } 3411 #endif 3412 } 3413 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) { 3414 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 3415 env->msr_hv_vapic); 3416 } 3417 if (has_msr_hv_crash) { 3418 int j; 3419 3420 for (j = 0; j < HV_CRASH_PARAMS; j++) 3421 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 3422 env->msr_hv_crash_params[j]); 3423 3424 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY); 3425 } 3426 if (has_msr_hv_runtime) { 3427 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime); 3428 } 3429 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) 3430 && hv_vpindex_settable) { 3431 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_INDEX, 3432 hyperv_vp_index(CPU(cpu))); 3433 } 3434 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) { 3435 int j; 3436 3437 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION); 3438 3439 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 3440 env->msr_hv_synic_control); 3441 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 3442 env->msr_hv_synic_evt_page); 3443 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 3444 env->msr_hv_synic_msg_page); 3445 3446 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) { 3447 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j, 3448 env->msr_hv_synic_sint[j]); 3449 } 3450 } 3451 if (has_msr_hv_stimer) { 3452 int j; 3453 3454 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) { 3455 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2, 3456 env->msr_hv_stimer_config[j]); 3457 } 3458 3459 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) { 3460 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2, 3461 env->msr_hv_stimer_count[j]); 3462 } 3463 } 3464 if (env->features[FEAT_1_EDX] & CPUID_MTRR) { 3465 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits); 3466 3467 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype); 3468 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]); 3469 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]); 3470 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]); 3471 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]); 3472 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]); 3473 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]); 3474 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]); 3475 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]); 3476 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]); 3477 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]); 3478 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]); 3479 for (i = 0; i < MSR_MTRRcap_VCNT; i++) { 3480 /* The CPU GPs if we write to a bit above the physical limit of 3481 * the host CPU (and KVM emulates that) 3482 */ 3483 uint64_t mask = env->mtrr_var[i].mask; 3484 mask &= phys_mask; 3485 3486 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 3487 env->mtrr_var[i].base); 3488 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask); 3489 } 3490 } 3491 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) { 3492 int addr_num = kvm_arch_get_supported_cpuid(kvm_state, 3493 0x14, 1, R_EAX) & 0x7; 3494 3495 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 3496 env->msr_rtit_ctrl); 3497 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 3498 env->msr_rtit_status); 3499 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 3500 env->msr_rtit_output_base); 3501 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 3502 env->msr_rtit_output_mask); 3503 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 3504 env->msr_rtit_cr3_match); 3505 for (i = 0; i < addr_num; i++) { 3506 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 3507 env->msr_rtit_addrs[i]); 3508 } 3509 } 3510 3511 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_SGX_LC) { 3512 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH0, 3513 env->msr_ia32_sgxlepubkeyhash[0]); 3514 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH1, 3515 env->msr_ia32_sgxlepubkeyhash[1]); 3516 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH2, 3517 env->msr_ia32_sgxlepubkeyhash[2]); 3518 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH3, 3519 env->msr_ia32_sgxlepubkeyhash[3]); 3520 } 3521 3522 if (env->features[FEAT_XSAVE] & CPUID_D_1_EAX_XFD) { 3523 kvm_msr_entry_add(cpu, MSR_IA32_XFD, 3524 env->msr_xfd); 3525 kvm_msr_entry_add(cpu, MSR_IA32_XFD_ERR, 3526 env->msr_xfd_err); 3527 } 3528 3529 if (kvm_enabled() && cpu->enable_pmu && 3530 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 3531 uint64_t depth; 3532 int ret; 3533 3534 /* 3535 * Only migrate Arch LBR states when the host Arch LBR depth 3536 * equals that of source guest's, this is to avoid mismatch 3537 * of guest/host config for the msr hence avoid unexpected 3538 * misbehavior. 3539 */ 3540 ret = kvm_get_one_msr(cpu, MSR_ARCH_LBR_DEPTH, &depth); 3541 3542 if (ret == 1 && !!depth && depth == env->msr_lbr_depth) { 3543 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_CTL, env->msr_lbr_ctl); 3544 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_DEPTH, env->msr_lbr_depth); 3545 3546 for (i = 0; i < ARCH_LBR_NR_ENTRIES; i++) { 3547 if (!env->lbr_records[i].from) { 3548 continue; 3549 } 3550 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_FROM_0 + i, 3551 env->lbr_records[i].from); 3552 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_TO_0 + i, 3553 env->lbr_records[i].to); 3554 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_INFO_0 + i, 3555 env->lbr_records[i].info); 3556 } 3557 } 3558 } 3559 3560 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see 3561 * kvm_put_msr_feature_control. */ 3562 } 3563 3564 if (env->mcg_cap) { 3565 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status); 3566 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl); 3567 if (has_msr_mcg_ext_ctl) { 3568 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl); 3569 } 3570 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) { 3571 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]); 3572 } 3573 } 3574 3575 return kvm_buf_set_msrs(cpu); 3576 } 3577 3578 3579 static int kvm_get_xsave(X86CPU *cpu) 3580 { 3581 CPUX86State *env = &cpu->env; 3582 void *xsave = env->xsave_buf; 3583 int type, ret; 3584 3585 type = has_xsave2 ? KVM_GET_XSAVE2 : KVM_GET_XSAVE; 3586 ret = kvm_vcpu_ioctl(CPU(cpu), type, xsave); 3587 if (ret < 0) { 3588 return ret; 3589 } 3590 x86_cpu_xrstor_all_areas(cpu, xsave, env->xsave_buf_len); 3591 3592 return 0; 3593 } 3594 3595 static int kvm_get_xcrs(X86CPU *cpu) 3596 { 3597 CPUX86State *env = &cpu->env; 3598 int i, ret; 3599 struct kvm_xcrs xcrs; 3600 3601 if (!has_xcrs) { 3602 return 0; 3603 } 3604 3605 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs); 3606 if (ret < 0) { 3607 return ret; 3608 } 3609 3610 for (i = 0; i < xcrs.nr_xcrs; i++) { 3611 /* Only support xcr0 now */ 3612 if (xcrs.xcrs[i].xcr == 0) { 3613 env->xcr0 = xcrs.xcrs[i].value; 3614 break; 3615 } 3616 } 3617 return 0; 3618 } 3619 3620 static int kvm_get_sregs(X86CPU *cpu) 3621 { 3622 CPUX86State *env = &cpu->env; 3623 struct kvm_sregs sregs; 3624 int ret; 3625 3626 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs); 3627 if (ret < 0) { 3628 return ret; 3629 } 3630 3631 /* 3632 * The interrupt_bitmap is ignored because KVM_GET_SREGS is 3633 * always preceded by KVM_GET_VCPU_EVENTS. 3634 */ 3635 3636 get_seg(&env->segs[R_CS], &sregs.cs); 3637 get_seg(&env->segs[R_DS], &sregs.ds); 3638 get_seg(&env->segs[R_ES], &sregs.es); 3639 get_seg(&env->segs[R_FS], &sregs.fs); 3640 get_seg(&env->segs[R_GS], &sregs.gs); 3641 get_seg(&env->segs[R_SS], &sregs.ss); 3642 3643 get_seg(&env->tr, &sregs.tr); 3644 get_seg(&env->ldt, &sregs.ldt); 3645 3646 env->idt.limit = sregs.idt.limit; 3647 env->idt.base = sregs.idt.base; 3648 env->gdt.limit = sregs.gdt.limit; 3649 env->gdt.base = sregs.gdt.base; 3650 3651 env->cr[0] = sregs.cr0; 3652 env->cr[2] = sregs.cr2; 3653 env->cr[3] = sregs.cr3; 3654 env->cr[4] = sregs.cr4; 3655 3656 env->efer = sregs.efer; 3657 if (sev_es_enabled() && env->efer & MSR_EFER_LME && 3658 env->cr[0] & CR0_PG_MASK) { 3659 env->efer |= MSR_EFER_LMA; 3660 } 3661 3662 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */ 3663 x86_update_hflags(env); 3664 3665 return 0; 3666 } 3667 3668 static int kvm_get_sregs2(X86CPU *cpu) 3669 { 3670 CPUX86State *env = &cpu->env; 3671 struct kvm_sregs2 sregs; 3672 int i, ret; 3673 3674 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS2, &sregs); 3675 if (ret < 0) { 3676 return ret; 3677 } 3678 3679 get_seg(&env->segs[R_CS], &sregs.cs); 3680 get_seg(&env->segs[R_DS], &sregs.ds); 3681 get_seg(&env->segs[R_ES], &sregs.es); 3682 get_seg(&env->segs[R_FS], &sregs.fs); 3683 get_seg(&env->segs[R_GS], &sregs.gs); 3684 get_seg(&env->segs[R_SS], &sregs.ss); 3685 3686 get_seg(&env->tr, &sregs.tr); 3687 get_seg(&env->ldt, &sregs.ldt); 3688 3689 env->idt.limit = sregs.idt.limit; 3690 env->idt.base = sregs.idt.base; 3691 env->gdt.limit = sregs.gdt.limit; 3692 env->gdt.base = sregs.gdt.base; 3693 3694 env->cr[0] = sregs.cr0; 3695 env->cr[2] = sregs.cr2; 3696 env->cr[3] = sregs.cr3; 3697 env->cr[4] = sregs.cr4; 3698 3699 env->efer = sregs.efer; 3700 if (sev_es_enabled() && env->efer & MSR_EFER_LME && 3701 env->cr[0] & CR0_PG_MASK) { 3702 env->efer |= MSR_EFER_LMA; 3703 } 3704 3705 env->pdptrs_valid = sregs.flags & KVM_SREGS2_FLAGS_PDPTRS_VALID; 3706 3707 if (env->pdptrs_valid) { 3708 for (i = 0; i < 4; i++) { 3709 env->pdptrs[i] = sregs.pdptrs[i]; 3710 } 3711 } 3712 3713 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */ 3714 x86_update_hflags(env); 3715 3716 return 0; 3717 } 3718 3719 static int kvm_get_msrs(X86CPU *cpu) 3720 { 3721 CPUX86State *env = &cpu->env; 3722 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries; 3723 int ret, i; 3724 uint64_t mtrr_top_bits; 3725 3726 kvm_msr_buf_reset(cpu); 3727 3728 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0); 3729 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0); 3730 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0); 3731 kvm_msr_entry_add(cpu, MSR_PAT, 0); 3732 if (has_msr_star) { 3733 kvm_msr_entry_add(cpu, MSR_STAR, 0); 3734 } 3735 if (has_msr_hsave_pa) { 3736 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0); 3737 } 3738 if (has_msr_tsc_aux) { 3739 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0); 3740 } 3741 if (has_msr_tsc_adjust) { 3742 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0); 3743 } 3744 if (has_msr_tsc_deadline) { 3745 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0); 3746 } 3747 if (has_msr_misc_enable) { 3748 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0); 3749 } 3750 if (has_msr_smbase) { 3751 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0); 3752 } 3753 if (has_msr_smi_count) { 3754 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0); 3755 } 3756 if (has_msr_feature_control) { 3757 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0); 3758 } 3759 if (has_msr_pkrs) { 3760 kvm_msr_entry_add(cpu, MSR_IA32_PKRS, 0); 3761 } 3762 if (has_msr_bndcfgs) { 3763 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0); 3764 } 3765 if (has_msr_xss) { 3766 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0); 3767 } 3768 if (has_msr_umwait) { 3769 kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, 0); 3770 } 3771 if (has_msr_spec_ctrl) { 3772 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0); 3773 } 3774 if (has_tsc_scale_msr) { 3775 kvm_msr_entry_add(cpu, MSR_AMD64_TSC_RATIO, 0); 3776 } 3777 3778 if (has_msr_tsx_ctrl) { 3779 kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, 0); 3780 } 3781 if (has_msr_virt_ssbd) { 3782 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0); 3783 } 3784 if (!env->tsc_valid) { 3785 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0); 3786 env->tsc_valid = !runstate_is_running(); 3787 } 3788 3789 #ifdef TARGET_X86_64 3790 if (lm_capable_kernel) { 3791 kvm_msr_entry_add(cpu, MSR_CSTAR, 0); 3792 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0); 3793 kvm_msr_entry_add(cpu, MSR_FMASK, 0); 3794 kvm_msr_entry_add(cpu, MSR_LSTAR, 0); 3795 } 3796 #endif 3797 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0); 3798 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0); 3799 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF_INT)) { 3800 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_INT, 0); 3801 } 3802 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) { 3803 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0); 3804 } 3805 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) { 3806 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0); 3807 } 3808 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) { 3809 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0); 3810 } 3811 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_POLL_CONTROL)) { 3812 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, 1); 3813 } 3814 if (has_architectural_pmu_version > 0) { 3815 if (has_architectural_pmu_version > 1) { 3816 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0); 3817 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0); 3818 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0); 3819 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0); 3820 } 3821 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) { 3822 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0); 3823 } 3824 for (i = 0; i < num_architectural_pmu_gp_counters; i++) { 3825 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0); 3826 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0); 3827 } 3828 } 3829 3830 if (env->mcg_cap) { 3831 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0); 3832 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0); 3833 if (has_msr_mcg_ext_ctl) { 3834 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0); 3835 } 3836 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) { 3837 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0); 3838 } 3839 } 3840 3841 if (has_msr_hv_hypercall) { 3842 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0); 3843 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0); 3844 } 3845 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) { 3846 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0); 3847 } 3848 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) { 3849 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0); 3850 } 3851 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) { 3852 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0); 3853 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0); 3854 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0); 3855 } 3856 if (has_msr_hv_syndbg_options) { 3857 kvm_msr_entry_add(cpu, HV_X64_MSR_SYNDBG_OPTIONS, 0); 3858 } 3859 if (has_msr_hv_crash) { 3860 int j; 3861 3862 for (j = 0; j < HV_CRASH_PARAMS; j++) { 3863 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0); 3864 } 3865 } 3866 if (has_msr_hv_runtime) { 3867 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0); 3868 } 3869 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) { 3870 uint32_t msr; 3871 3872 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0); 3873 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0); 3874 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0); 3875 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) { 3876 kvm_msr_entry_add(cpu, msr, 0); 3877 } 3878 } 3879 if (has_msr_hv_stimer) { 3880 uint32_t msr; 3881 3882 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT; 3883 msr++) { 3884 kvm_msr_entry_add(cpu, msr, 0); 3885 } 3886 } 3887 if (env->features[FEAT_1_EDX] & CPUID_MTRR) { 3888 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0); 3889 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0); 3890 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0); 3891 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0); 3892 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0); 3893 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0); 3894 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0); 3895 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0); 3896 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0); 3897 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0); 3898 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0); 3899 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0); 3900 for (i = 0; i < MSR_MTRRcap_VCNT; i++) { 3901 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0); 3902 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0); 3903 } 3904 } 3905 3906 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) { 3907 int addr_num = 3908 kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7; 3909 3910 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0); 3911 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0); 3912 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0); 3913 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0); 3914 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0); 3915 for (i = 0; i < addr_num; i++) { 3916 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0); 3917 } 3918 } 3919 3920 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_SGX_LC) { 3921 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH0, 0); 3922 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH1, 0); 3923 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH2, 0); 3924 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH3, 0); 3925 } 3926 3927 if (env->features[FEAT_XSAVE] & CPUID_D_1_EAX_XFD) { 3928 kvm_msr_entry_add(cpu, MSR_IA32_XFD, 0); 3929 kvm_msr_entry_add(cpu, MSR_IA32_XFD_ERR, 0); 3930 } 3931 3932 if (kvm_enabled() && cpu->enable_pmu && 3933 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 3934 uint64_t depth; 3935 3936 ret = kvm_get_one_msr(cpu, MSR_ARCH_LBR_DEPTH, &depth); 3937 if (ret == 1 && depth == ARCH_LBR_NR_ENTRIES) { 3938 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_CTL, 0); 3939 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_DEPTH, 0); 3940 3941 for (i = 0; i < ARCH_LBR_NR_ENTRIES; i++) { 3942 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_FROM_0 + i, 0); 3943 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_TO_0 + i, 0); 3944 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_INFO_0 + i, 0); 3945 } 3946 } 3947 } 3948 3949 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf); 3950 if (ret < 0) { 3951 return ret; 3952 } 3953 3954 if (ret < cpu->kvm_msr_buf->nmsrs) { 3955 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret]; 3956 error_report("error: failed to get MSR 0x%" PRIx32, 3957 (uint32_t)e->index); 3958 } 3959 3960 assert(ret == cpu->kvm_msr_buf->nmsrs); 3961 /* 3962 * MTRR masks: Each mask consists of 5 parts 3963 * a 10..0: must be zero 3964 * b 11 : valid bit 3965 * c n-1.12: actual mask bits 3966 * d 51..n: reserved must be zero 3967 * e 63.52: reserved must be zero 3968 * 3969 * 'n' is the number of physical bits supported by the CPU and is 3970 * apparently always <= 52. We know our 'n' but don't know what 3971 * the destinations 'n' is; it might be smaller, in which case 3972 * it masks (c) on loading. It might be larger, in which case 3973 * we fill 'd' so that d..c is consistent irrespetive of the 'n' 3974 * we're migrating to. 3975 */ 3976 3977 if (cpu->fill_mtrr_mask) { 3978 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52); 3979 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS); 3980 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits); 3981 } else { 3982 mtrr_top_bits = 0; 3983 } 3984 3985 for (i = 0; i < ret; i++) { 3986 uint32_t index = msrs[i].index; 3987 switch (index) { 3988 case MSR_IA32_SYSENTER_CS: 3989 env->sysenter_cs = msrs[i].data; 3990 break; 3991 case MSR_IA32_SYSENTER_ESP: 3992 env->sysenter_esp = msrs[i].data; 3993 break; 3994 case MSR_IA32_SYSENTER_EIP: 3995 env->sysenter_eip = msrs[i].data; 3996 break; 3997 case MSR_PAT: 3998 env->pat = msrs[i].data; 3999 break; 4000 case MSR_STAR: 4001 env->star = msrs[i].data; 4002 break; 4003 #ifdef TARGET_X86_64 4004 case MSR_CSTAR: 4005 env->cstar = msrs[i].data; 4006 break; 4007 case MSR_KERNELGSBASE: 4008 env->kernelgsbase = msrs[i].data; 4009 break; 4010 case MSR_FMASK: 4011 env->fmask = msrs[i].data; 4012 break; 4013 case MSR_LSTAR: 4014 env->lstar = msrs[i].data; 4015 break; 4016 #endif 4017 case MSR_IA32_TSC: 4018 env->tsc = msrs[i].data; 4019 break; 4020 case MSR_TSC_AUX: 4021 env->tsc_aux = msrs[i].data; 4022 break; 4023 case MSR_TSC_ADJUST: 4024 env->tsc_adjust = msrs[i].data; 4025 break; 4026 case MSR_IA32_TSCDEADLINE: 4027 env->tsc_deadline = msrs[i].data; 4028 break; 4029 case MSR_VM_HSAVE_PA: 4030 env->vm_hsave = msrs[i].data; 4031 break; 4032 case MSR_KVM_SYSTEM_TIME: 4033 env->system_time_msr = msrs[i].data; 4034 break; 4035 case MSR_KVM_WALL_CLOCK: 4036 env->wall_clock_msr = msrs[i].data; 4037 break; 4038 case MSR_MCG_STATUS: 4039 env->mcg_status = msrs[i].data; 4040 break; 4041 case MSR_MCG_CTL: 4042 env->mcg_ctl = msrs[i].data; 4043 break; 4044 case MSR_MCG_EXT_CTL: 4045 env->mcg_ext_ctl = msrs[i].data; 4046 break; 4047 case MSR_IA32_MISC_ENABLE: 4048 env->msr_ia32_misc_enable = msrs[i].data; 4049 break; 4050 case MSR_IA32_SMBASE: 4051 env->smbase = msrs[i].data; 4052 break; 4053 case MSR_SMI_COUNT: 4054 env->msr_smi_count = msrs[i].data; 4055 break; 4056 case MSR_IA32_FEATURE_CONTROL: 4057 env->msr_ia32_feature_control = msrs[i].data; 4058 break; 4059 case MSR_IA32_BNDCFGS: 4060 env->msr_bndcfgs = msrs[i].data; 4061 break; 4062 case MSR_IA32_XSS: 4063 env->xss = msrs[i].data; 4064 break; 4065 case MSR_IA32_UMWAIT_CONTROL: 4066 env->umwait = msrs[i].data; 4067 break; 4068 case MSR_IA32_PKRS: 4069 env->pkrs = msrs[i].data; 4070 break; 4071 default: 4072 if (msrs[i].index >= MSR_MC0_CTL && 4073 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) { 4074 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data; 4075 } 4076 break; 4077 case MSR_KVM_ASYNC_PF_EN: 4078 env->async_pf_en_msr = msrs[i].data; 4079 break; 4080 case MSR_KVM_ASYNC_PF_INT: 4081 env->async_pf_int_msr = msrs[i].data; 4082 break; 4083 case MSR_KVM_PV_EOI_EN: 4084 env->pv_eoi_en_msr = msrs[i].data; 4085 break; 4086 case MSR_KVM_STEAL_TIME: 4087 env->steal_time_msr = msrs[i].data; 4088 break; 4089 case MSR_KVM_POLL_CONTROL: { 4090 env->poll_control_msr = msrs[i].data; 4091 break; 4092 } 4093 case MSR_CORE_PERF_FIXED_CTR_CTRL: 4094 env->msr_fixed_ctr_ctrl = msrs[i].data; 4095 break; 4096 case MSR_CORE_PERF_GLOBAL_CTRL: 4097 env->msr_global_ctrl = msrs[i].data; 4098 break; 4099 case MSR_CORE_PERF_GLOBAL_STATUS: 4100 env->msr_global_status = msrs[i].data; 4101 break; 4102 case MSR_CORE_PERF_GLOBAL_OVF_CTRL: 4103 env->msr_global_ovf_ctrl = msrs[i].data; 4104 break; 4105 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1: 4106 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data; 4107 break; 4108 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1: 4109 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data; 4110 break; 4111 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1: 4112 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data; 4113 break; 4114 case HV_X64_MSR_HYPERCALL: 4115 env->msr_hv_hypercall = msrs[i].data; 4116 break; 4117 case HV_X64_MSR_GUEST_OS_ID: 4118 env->msr_hv_guest_os_id = msrs[i].data; 4119 break; 4120 case HV_X64_MSR_APIC_ASSIST_PAGE: 4121 env->msr_hv_vapic = msrs[i].data; 4122 break; 4123 case HV_X64_MSR_REFERENCE_TSC: 4124 env->msr_hv_tsc = msrs[i].data; 4125 break; 4126 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 4127 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data; 4128 break; 4129 case HV_X64_MSR_VP_RUNTIME: 4130 env->msr_hv_runtime = msrs[i].data; 4131 break; 4132 case HV_X64_MSR_SCONTROL: 4133 env->msr_hv_synic_control = msrs[i].data; 4134 break; 4135 case HV_X64_MSR_SIEFP: 4136 env->msr_hv_synic_evt_page = msrs[i].data; 4137 break; 4138 case HV_X64_MSR_SIMP: 4139 env->msr_hv_synic_msg_page = msrs[i].data; 4140 break; 4141 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15: 4142 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data; 4143 break; 4144 case HV_X64_MSR_STIMER0_CONFIG: 4145 case HV_X64_MSR_STIMER1_CONFIG: 4146 case HV_X64_MSR_STIMER2_CONFIG: 4147 case HV_X64_MSR_STIMER3_CONFIG: 4148 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] = 4149 msrs[i].data; 4150 break; 4151 case HV_X64_MSR_STIMER0_COUNT: 4152 case HV_X64_MSR_STIMER1_COUNT: 4153 case HV_X64_MSR_STIMER2_COUNT: 4154 case HV_X64_MSR_STIMER3_COUNT: 4155 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] = 4156 msrs[i].data; 4157 break; 4158 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 4159 env->msr_hv_reenlightenment_control = msrs[i].data; 4160 break; 4161 case HV_X64_MSR_TSC_EMULATION_CONTROL: 4162 env->msr_hv_tsc_emulation_control = msrs[i].data; 4163 break; 4164 case HV_X64_MSR_TSC_EMULATION_STATUS: 4165 env->msr_hv_tsc_emulation_status = msrs[i].data; 4166 break; 4167 case HV_X64_MSR_SYNDBG_OPTIONS: 4168 env->msr_hv_syndbg_options = msrs[i].data; 4169 break; 4170 case MSR_MTRRdefType: 4171 env->mtrr_deftype = msrs[i].data; 4172 break; 4173 case MSR_MTRRfix64K_00000: 4174 env->mtrr_fixed[0] = msrs[i].data; 4175 break; 4176 case MSR_MTRRfix16K_80000: 4177 env->mtrr_fixed[1] = msrs[i].data; 4178 break; 4179 case MSR_MTRRfix16K_A0000: 4180 env->mtrr_fixed[2] = msrs[i].data; 4181 break; 4182 case MSR_MTRRfix4K_C0000: 4183 env->mtrr_fixed[3] = msrs[i].data; 4184 break; 4185 case MSR_MTRRfix4K_C8000: 4186 env->mtrr_fixed[4] = msrs[i].data; 4187 break; 4188 case MSR_MTRRfix4K_D0000: 4189 env->mtrr_fixed[5] = msrs[i].data; 4190 break; 4191 case MSR_MTRRfix4K_D8000: 4192 env->mtrr_fixed[6] = msrs[i].data; 4193 break; 4194 case MSR_MTRRfix4K_E0000: 4195 env->mtrr_fixed[7] = msrs[i].data; 4196 break; 4197 case MSR_MTRRfix4K_E8000: 4198 env->mtrr_fixed[8] = msrs[i].data; 4199 break; 4200 case MSR_MTRRfix4K_F0000: 4201 env->mtrr_fixed[9] = msrs[i].data; 4202 break; 4203 case MSR_MTRRfix4K_F8000: 4204 env->mtrr_fixed[10] = msrs[i].data; 4205 break; 4206 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1): 4207 if (index & 1) { 4208 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data | 4209 mtrr_top_bits; 4210 } else { 4211 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data; 4212 } 4213 break; 4214 case MSR_IA32_SPEC_CTRL: 4215 env->spec_ctrl = msrs[i].data; 4216 break; 4217 case MSR_AMD64_TSC_RATIO: 4218 env->amd_tsc_scale_msr = msrs[i].data; 4219 break; 4220 case MSR_IA32_TSX_CTRL: 4221 env->tsx_ctrl = msrs[i].data; 4222 break; 4223 case MSR_VIRT_SSBD: 4224 env->virt_ssbd = msrs[i].data; 4225 break; 4226 case MSR_IA32_RTIT_CTL: 4227 env->msr_rtit_ctrl = msrs[i].data; 4228 break; 4229 case MSR_IA32_RTIT_STATUS: 4230 env->msr_rtit_status = msrs[i].data; 4231 break; 4232 case MSR_IA32_RTIT_OUTPUT_BASE: 4233 env->msr_rtit_output_base = msrs[i].data; 4234 break; 4235 case MSR_IA32_RTIT_OUTPUT_MASK: 4236 env->msr_rtit_output_mask = msrs[i].data; 4237 break; 4238 case MSR_IA32_RTIT_CR3_MATCH: 4239 env->msr_rtit_cr3_match = msrs[i].data; 4240 break; 4241 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 4242 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data; 4243 break; 4244 case MSR_IA32_SGXLEPUBKEYHASH0 ... MSR_IA32_SGXLEPUBKEYHASH3: 4245 env->msr_ia32_sgxlepubkeyhash[index - MSR_IA32_SGXLEPUBKEYHASH0] = 4246 msrs[i].data; 4247 break; 4248 case MSR_IA32_XFD: 4249 env->msr_xfd = msrs[i].data; 4250 break; 4251 case MSR_IA32_XFD_ERR: 4252 env->msr_xfd_err = msrs[i].data; 4253 break; 4254 case MSR_ARCH_LBR_CTL: 4255 env->msr_lbr_ctl = msrs[i].data; 4256 break; 4257 case MSR_ARCH_LBR_DEPTH: 4258 env->msr_lbr_depth = msrs[i].data; 4259 break; 4260 case MSR_ARCH_LBR_FROM_0 ... MSR_ARCH_LBR_FROM_0 + 31: 4261 env->lbr_records[index - MSR_ARCH_LBR_FROM_0].from = msrs[i].data; 4262 break; 4263 case MSR_ARCH_LBR_TO_0 ... MSR_ARCH_LBR_TO_0 + 31: 4264 env->lbr_records[index - MSR_ARCH_LBR_TO_0].to = msrs[i].data; 4265 break; 4266 case MSR_ARCH_LBR_INFO_0 ... MSR_ARCH_LBR_INFO_0 + 31: 4267 env->lbr_records[index - MSR_ARCH_LBR_INFO_0].info = msrs[i].data; 4268 break; 4269 } 4270 } 4271 4272 return 0; 4273 } 4274 4275 static int kvm_put_mp_state(X86CPU *cpu) 4276 { 4277 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state }; 4278 4279 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state); 4280 } 4281 4282 static int kvm_get_mp_state(X86CPU *cpu) 4283 { 4284 CPUState *cs = CPU(cpu); 4285 CPUX86State *env = &cpu->env; 4286 struct kvm_mp_state mp_state; 4287 int ret; 4288 4289 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state); 4290 if (ret < 0) { 4291 return ret; 4292 } 4293 env->mp_state = mp_state.mp_state; 4294 if (kvm_irqchip_in_kernel()) { 4295 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED); 4296 } 4297 return 0; 4298 } 4299 4300 static int kvm_get_apic(X86CPU *cpu) 4301 { 4302 DeviceState *apic = cpu->apic_state; 4303 struct kvm_lapic_state kapic; 4304 int ret; 4305 4306 if (apic && kvm_irqchip_in_kernel()) { 4307 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic); 4308 if (ret < 0) { 4309 return ret; 4310 } 4311 4312 kvm_get_apic_state(apic, &kapic); 4313 } 4314 return 0; 4315 } 4316 4317 static int kvm_put_vcpu_events(X86CPU *cpu, int level) 4318 { 4319 CPUState *cs = CPU(cpu); 4320 CPUX86State *env = &cpu->env; 4321 struct kvm_vcpu_events events = {}; 4322 4323 events.flags = 0; 4324 4325 if (has_exception_payload) { 4326 events.flags |= KVM_VCPUEVENT_VALID_PAYLOAD; 4327 events.exception.pending = env->exception_pending; 4328 events.exception_has_payload = env->exception_has_payload; 4329 events.exception_payload = env->exception_payload; 4330 } 4331 events.exception.nr = env->exception_nr; 4332 events.exception.injected = env->exception_injected; 4333 events.exception.has_error_code = env->has_error_code; 4334 events.exception.error_code = env->error_code; 4335 4336 events.interrupt.injected = (env->interrupt_injected >= 0); 4337 events.interrupt.nr = env->interrupt_injected; 4338 events.interrupt.soft = env->soft_interrupt; 4339 4340 events.nmi.injected = env->nmi_injected; 4341 events.nmi.pending = env->nmi_pending; 4342 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK); 4343 4344 events.sipi_vector = env->sipi_vector; 4345 4346 if (has_msr_smbase) { 4347 events.smi.smm = !!(env->hflags & HF_SMM_MASK); 4348 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK); 4349 if (kvm_irqchip_in_kernel()) { 4350 /* As soon as these are moved to the kernel, remove them 4351 * from cs->interrupt_request. 4352 */ 4353 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI; 4354 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT; 4355 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI); 4356 } else { 4357 /* Keep these in cs->interrupt_request. */ 4358 events.smi.pending = 0; 4359 events.smi.latched_init = 0; 4360 } 4361 /* Stop SMI delivery on old machine types to avoid a reboot 4362 * on an inward migration of an old VM. 4363 */ 4364 if (!cpu->kvm_no_smi_migration) { 4365 events.flags |= KVM_VCPUEVENT_VALID_SMM; 4366 } 4367 } 4368 4369 if (level >= KVM_PUT_RESET_STATE) { 4370 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING; 4371 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { 4372 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR; 4373 } 4374 } 4375 4376 if (has_triple_fault_event) { 4377 events.flags |= KVM_VCPUEVENT_VALID_TRIPLE_FAULT; 4378 events.triple_fault.pending = env->triple_fault_pending; 4379 } 4380 4381 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events); 4382 } 4383 4384 static int kvm_get_vcpu_events(X86CPU *cpu) 4385 { 4386 CPUX86State *env = &cpu->env; 4387 struct kvm_vcpu_events events; 4388 int ret; 4389 4390 memset(&events, 0, sizeof(events)); 4391 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events); 4392 if (ret < 0) { 4393 return ret; 4394 } 4395 4396 if (events.flags & KVM_VCPUEVENT_VALID_PAYLOAD) { 4397 env->exception_pending = events.exception.pending; 4398 env->exception_has_payload = events.exception_has_payload; 4399 env->exception_payload = events.exception_payload; 4400 } else { 4401 env->exception_pending = 0; 4402 env->exception_has_payload = false; 4403 } 4404 env->exception_injected = events.exception.injected; 4405 env->exception_nr = 4406 (env->exception_pending || env->exception_injected) ? 4407 events.exception.nr : -1; 4408 env->has_error_code = events.exception.has_error_code; 4409 env->error_code = events.exception.error_code; 4410 4411 env->interrupt_injected = 4412 events.interrupt.injected ? events.interrupt.nr : -1; 4413 env->soft_interrupt = events.interrupt.soft; 4414 4415 env->nmi_injected = events.nmi.injected; 4416 env->nmi_pending = events.nmi.pending; 4417 if (events.nmi.masked) { 4418 env->hflags2 |= HF2_NMI_MASK; 4419 } else { 4420 env->hflags2 &= ~HF2_NMI_MASK; 4421 } 4422 4423 if (events.flags & KVM_VCPUEVENT_VALID_SMM) { 4424 if (events.smi.smm) { 4425 env->hflags |= HF_SMM_MASK; 4426 } else { 4427 env->hflags &= ~HF_SMM_MASK; 4428 } 4429 if (events.smi.pending) { 4430 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 4431 } else { 4432 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 4433 } 4434 if (events.smi.smm_inside_nmi) { 4435 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK; 4436 } else { 4437 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK; 4438 } 4439 if (events.smi.latched_init) { 4440 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT); 4441 } else { 4442 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT); 4443 } 4444 } 4445 4446 if (events.flags & KVM_VCPUEVENT_VALID_TRIPLE_FAULT) { 4447 env->triple_fault_pending = events.triple_fault.pending; 4448 } 4449 4450 env->sipi_vector = events.sipi_vector; 4451 4452 return 0; 4453 } 4454 4455 static int kvm_put_debugregs(X86CPU *cpu) 4456 { 4457 CPUX86State *env = &cpu->env; 4458 struct kvm_debugregs dbgregs; 4459 int i; 4460 4461 memset(&dbgregs, 0, sizeof(dbgregs)); 4462 for (i = 0; i < 4; i++) { 4463 dbgregs.db[i] = env->dr[i]; 4464 } 4465 dbgregs.dr6 = env->dr[6]; 4466 dbgregs.dr7 = env->dr[7]; 4467 dbgregs.flags = 0; 4468 4469 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs); 4470 } 4471 4472 static int kvm_get_debugregs(X86CPU *cpu) 4473 { 4474 CPUX86State *env = &cpu->env; 4475 struct kvm_debugregs dbgregs; 4476 int i, ret; 4477 4478 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs); 4479 if (ret < 0) { 4480 return ret; 4481 } 4482 for (i = 0; i < 4; i++) { 4483 env->dr[i] = dbgregs.db[i]; 4484 } 4485 env->dr[4] = env->dr[6] = dbgregs.dr6; 4486 env->dr[5] = env->dr[7] = dbgregs.dr7; 4487 4488 return 0; 4489 } 4490 4491 static int kvm_put_nested_state(X86CPU *cpu) 4492 { 4493 CPUX86State *env = &cpu->env; 4494 int max_nested_state_len = kvm_max_nested_state_length(); 4495 4496 if (!env->nested_state) { 4497 return 0; 4498 } 4499 4500 /* 4501 * Copy flags that are affected by reset from env->hflags and env->hflags2. 4502 */ 4503 if (env->hflags & HF_GUEST_MASK) { 4504 env->nested_state->flags |= KVM_STATE_NESTED_GUEST_MODE; 4505 } else { 4506 env->nested_state->flags &= ~KVM_STATE_NESTED_GUEST_MODE; 4507 } 4508 4509 /* Don't set KVM_STATE_NESTED_GIF_SET on VMX as it is illegal */ 4510 if (cpu_has_svm(env) && (env->hflags2 & HF2_GIF_MASK)) { 4511 env->nested_state->flags |= KVM_STATE_NESTED_GIF_SET; 4512 } else { 4513 env->nested_state->flags &= ~KVM_STATE_NESTED_GIF_SET; 4514 } 4515 4516 assert(env->nested_state->size <= max_nested_state_len); 4517 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_NESTED_STATE, env->nested_state); 4518 } 4519 4520 static int kvm_get_nested_state(X86CPU *cpu) 4521 { 4522 CPUX86State *env = &cpu->env; 4523 int max_nested_state_len = kvm_max_nested_state_length(); 4524 int ret; 4525 4526 if (!env->nested_state) { 4527 return 0; 4528 } 4529 4530 /* 4531 * It is possible that migration restored a smaller size into 4532 * nested_state->hdr.size than what our kernel support. 4533 * We preserve migration origin nested_state->hdr.size for 4534 * call to KVM_SET_NESTED_STATE but wish that our next call 4535 * to KVM_GET_NESTED_STATE will use max size our kernel support. 4536 */ 4537 env->nested_state->size = max_nested_state_len; 4538 4539 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_NESTED_STATE, env->nested_state); 4540 if (ret < 0) { 4541 return ret; 4542 } 4543 4544 /* 4545 * Copy flags that are affected by reset to env->hflags and env->hflags2. 4546 */ 4547 if (env->nested_state->flags & KVM_STATE_NESTED_GUEST_MODE) { 4548 env->hflags |= HF_GUEST_MASK; 4549 } else { 4550 env->hflags &= ~HF_GUEST_MASK; 4551 } 4552 4553 /* Keep HF2_GIF_MASK set on !SVM as x86_cpu_pending_interrupt() needs it */ 4554 if (cpu_has_svm(env)) { 4555 if (env->nested_state->flags & KVM_STATE_NESTED_GIF_SET) { 4556 env->hflags2 |= HF2_GIF_MASK; 4557 } else { 4558 env->hflags2 &= ~HF2_GIF_MASK; 4559 } 4560 } 4561 4562 return ret; 4563 } 4564 4565 int kvm_arch_put_registers(CPUState *cpu, int level) 4566 { 4567 X86CPU *x86_cpu = X86_CPU(cpu); 4568 int ret; 4569 4570 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu)); 4571 4572 /* 4573 * Put MSR_IA32_FEATURE_CONTROL first, this ensures the VM gets out of VMX 4574 * root operation upon vCPU reset. kvm_put_msr_feature_control() should also 4575 * precede kvm_put_nested_state() when 'real' nested state is set. 4576 */ 4577 if (level >= KVM_PUT_RESET_STATE) { 4578 ret = kvm_put_msr_feature_control(x86_cpu); 4579 if (ret < 0) { 4580 return ret; 4581 } 4582 } 4583 4584 /* must be before kvm_put_nested_state so that EFER.SVME is set */ 4585 ret = has_sregs2 ? kvm_put_sregs2(x86_cpu) : kvm_put_sregs(x86_cpu); 4586 if (ret < 0) { 4587 return ret; 4588 } 4589 4590 if (level >= KVM_PUT_RESET_STATE) { 4591 ret = kvm_put_nested_state(x86_cpu); 4592 if (ret < 0) { 4593 return ret; 4594 } 4595 } 4596 4597 if (level == KVM_PUT_FULL_STATE) { 4598 /* We don't check for kvm_arch_set_tsc_khz() errors here, 4599 * because TSC frequency mismatch shouldn't abort migration, 4600 * unless the user explicitly asked for a more strict TSC 4601 * setting (e.g. using an explicit "tsc-freq" option). 4602 */ 4603 kvm_arch_set_tsc_khz(cpu); 4604 } 4605 4606 #ifdef CONFIG_XEN_EMU 4607 if (xen_mode == XEN_EMULATE && level == KVM_PUT_FULL_STATE) { 4608 ret = kvm_put_xen_state(cpu); 4609 if (ret < 0) { 4610 return ret; 4611 } 4612 } 4613 #endif 4614 4615 ret = kvm_getput_regs(x86_cpu, 1); 4616 if (ret < 0) { 4617 return ret; 4618 } 4619 ret = kvm_put_xsave(x86_cpu); 4620 if (ret < 0) { 4621 return ret; 4622 } 4623 ret = kvm_put_xcrs(x86_cpu); 4624 if (ret < 0) { 4625 return ret; 4626 } 4627 ret = kvm_put_msrs(x86_cpu, level); 4628 if (ret < 0) { 4629 return ret; 4630 } 4631 ret = kvm_put_vcpu_events(x86_cpu, level); 4632 if (ret < 0) { 4633 return ret; 4634 } 4635 if (level >= KVM_PUT_RESET_STATE) { 4636 ret = kvm_put_mp_state(x86_cpu); 4637 if (ret < 0) { 4638 return ret; 4639 } 4640 } 4641 4642 ret = kvm_put_tscdeadline_msr(x86_cpu); 4643 if (ret < 0) { 4644 return ret; 4645 } 4646 ret = kvm_put_debugregs(x86_cpu); 4647 if (ret < 0) { 4648 return ret; 4649 } 4650 return 0; 4651 } 4652 4653 int kvm_arch_get_registers(CPUState *cs) 4654 { 4655 X86CPU *cpu = X86_CPU(cs); 4656 int ret; 4657 4658 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs)); 4659 4660 ret = kvm_get_vcpu_events(cpu); 4661 if (ret < 0) { 4662 goto out; 4663 } 4664 /* 4665 * KVM_GET_MPSTATE can modify CS and RIP, call it before 4666 * KVM_GET_REGS and KVM_GET_SREGS. 4667 */ 4668 ret = kvm_get_mp_state(cpu); 4669 if (ret < 0) { 4670 goto out; 4671 } 4672 ret = kvm_getput_regs(cpu, 0); 4673 if (ret < 0) { 4674 goto out; 4675 } 4676 ret = kvm_get_xsave(cpu); 4677 if (ret < 0) { 4678 goto out; 4679 } 4680 ret = kvm_get_xcrs(cpu); 4681 if (ret < 0) { 4682 goto out; 4683 } 4684 ret = has_sregs2 ? kvm_get_sregs2(cpu) : kvm_get_sregs(cpu); 4685 if (ret < 0) { 4686 goto out; 4687 } 4688 ret = kvm_get_msrs(cpu); 4689 if (ret < 0) { 4690 goto out; 4691 } 4692 ret = kvm_get_apic(cpu); 4693 if (ret < 0) { 4694 goto out; 4695 } 4696 ret = kvm_get_debugregs(cpu); 4697 if (ret < 0) { 4698 goto out; 4699 } 4700 ret = kvm_get_nested_state(cpu); 4701 if (ret < 0) { 4702 goto out; 4703 } 4704 #ifdef CONFIG_XEN_EMU 4705 if (xen_mode == XEN_EMULATE) { 4706 ret = kvm_get_xen_state(cs); 4707 if (ret < 0) { 4708 goto out; 4709 } 4710 } 4711 #endif 4712 ret = 0; 4713 out: 4714 cpu_sync_bndcs_hflags(&cpu->env); 4715 return ret; 4716 } 4717 4718 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run) 4719 { 4720 X86CPU *x86_cpu = X86_CPU(cpu); 4721 CPUX86State *env = &x86_cpu->env; 4722 int ret; 4723 4724 /* Inject NMI */ 4725 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) { 4726 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) { 4727 bql_lock(); 4728 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI; 4729 bql_unlock(); 4730 DPRINTF("injected NMI\n"); 4731 ret = kvm_vcpu_ioctl(cpu, KVM_NMI); 4732 if (ret < 0) { 4733 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n", 4734 strerror(-ret)); 4735 } 4736 } 4737 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) { 4738 bql_lock(); 4739 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI; 4740 bql_unlock(); 4741 DPRINTF("injected SMI\n"); 4742 ret = kvm_vcpu_ioctl(cpu, KVM_SMI); 4743 if (ret < 0) { 4744 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n", 4745 strerror(-ret)); 4746 } 4747 } 4748 } 4749 4750 if (!kvm_pic_in_kernel()) { 4751 bql_lock(); 4752 } 4753 4754 /* Force the VCPU out of its inner loop to process any INIT requests 4755 * or (for userspace APIC, but it is cheap to combine the checks here) 4756 * pending TPR access reports. 4757 */ 4758 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) { 4759 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) && 4760 !(env->hflags & HF_SMM_MASK)) { 4761 cpu->exit_request = 1; 4762 } 4763 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) { 4764 cpu->exit_request = 1; 4765 } 4766 } 4767 4768 if (!kvm_pic_in_kernel()) { 4769 /* Try to inject an interrupt if the guest can accept it */ 4770 if (run->ready_for_interrupt_injection && 4771 (cpu->interrupt_request & CPU_INTERRUPT_HARD) && 4772 (env->eflags & IF_MASK)) { 4773 int irq; 4774 4775 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD; 4776 irq = cpu_get_pic_interrupt(env); 4777 if (irq >= 0) { 4778 struct kvm_interrupt intr; 4779 4780 intr.irq = irq; 4781 DPRINTF("injected interrupt %d\n", irq); 4782 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr); 4783 if (ret < 0) { 4784 fprintf(stderr, 4785 "KVM: injection failed, interrupt lost (%s)\n", 4786 strerror(-ret)); 4787 } 4788 } 4789 } 4790 4791 /* If we have an interrupt but the guest is not ready to receive an 4792 * interrupt, request an interrupt window exit. This will 4793 * cause a return to userspace as soon as the guest is ready to 4794 * receive interrupts. */ 4795 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) { 4796 run->request_interrupt_window = 1; 4797 } else { 4798 run->request_interrupt_window = 0; 4799 } 4800 4801 DPRINTF("setting tpr\n"); 4802 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state); 4803 4804 bql_unlock(); 4805 } 4806 } 4807 4808 static void kvm_rate_limit_on_bus_lock(void) 4809 { 4810 uint64_t delay_ns = ratelimit_calculate_delay(&bus_lock_ratelimit_ctrl, 1); 4811 4812 if (delay_ns) { 4813 g_usleep(delay_ns / SCALE_US); 4814 } 4815 } 4816 4817 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run) 4818 { 4819 X86CPU *x86_cpu = X86_CPU(cpu); 4820 CPUX86State *env = &x86_cpu->env; 4821 4822 if (run->flags & KVM_RUN_X86_SMM) { 4823 env->hflags |= HF_SMM_MASK; 4824 } else { 4825 env->hflags &= ~HF_SMM_MASK; 4826 } 4827 if (run->if_flag) { 4828 env->eflags |= IF_MASK; 4829 } else { 4830 env->eflags &= ~IF_MASK; 4831 } 4832 if (run->flags & KVM_RUN_X86_BUS_LOCK) { 4833 kvm_rate_limit_on_bus_lock(); 4834 } 4835 4836 #ifdef CONFIG_XEN_EMU 4837 /* 4838 * If the callback is asserted as a GSI (or PCI INTx) then check if 4839 * vcpu_info->evtchn_upcall_pending has been cleared, and deassert 4840 * the callback IRQ if so. Ideally we could hook into the PIC/IOAPIC 4841 * EOI and only resample then, exactly how the VFIO eventfd pairs 4842 * are designed to work for level triggered interrupts. 4843 */ 4844 if (x86_cpu->env.xen_callback_asserted) { 4845 kvm_xen_maybe_deassert_callback(cpu); 4846 } 4847 #endif 4848 4849 /* We need to protect the apic state against concurrent accesses from 4850 * different threads in case the userspace irqchip is used. */ 4851 if (!kvm_irqchip_in_kernel()) { 4852 bql_lock(); 4853 } 4854 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8); 4855 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base); 4856 if (!kvm_irqchip_in_kernel()) { 4857 bql_unlock(); 4858 } 4859 return cpu_get_mem_attrs(env); 4860 } 4861 4862 int kvm_arch_process_async_events(CPUState *cs) 4863 { 4864 X86CPU *cpu = X86_CPU(cs); 4865 CPUX86State *env = &cpu->env; 4866 4867 if (cs->interrupt_request & CPU_INTERRUPT_MCE) { 4868 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */ 4869 assert(env->mcg_cap); 4870 4871 cs->interrupt_request &= ~CPU_INTERRUPT_MCE; 4872 4873 kvm_cpu_synchronize_state(cs); 4874 4875 if (env->exception_nr == EXCP08_DBLE) { 4876 /* this means triple fault */ 4877 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 4878 cs->exit_request = 1; 4879 return 0; 4880 } 4881 kvm_queue_exception(env, EXCP12_MCHK, 0, 0); 4882 env->has_error_code = 0; 4883 4884 cs->halted = 0; 4885 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) { 4886 env->mp_state = KVM_MP_STATE_RUNNABLE; 4887 } 4888 } 4889 4890 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) && 4891 !(env->hflags & HF_SMM_MASK)) { 4892 kvm_cpu_synchronize_state(cs); 4893 do_cpu_init(cpu); 4894 } 4895 4896 if (kvm_irqchip_in_kernel()) { 4897 return 0; 4898 } 4899 4900 if (cs->interrupt_request & CPU_INTERRUPT_POLL) { 4901 cs->interrupt_request &= ~CPU_INTERRUPT_POLL; 4902 apic_poll_irq(cpu->apic_state); 4903 } 4904 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) && 4905 (env->eflags & IF_MASK)) || 4906 (cs->interrupt_request & CPU_INTERRUPT_NMI)) { 4907 cs->halted = 0; 4908 } 4909 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) { 4910 kvm_cpu_synchronize_state(cs); 4911 do_cpu_sipi(cpu); 4912 } 4913 if (cs->interrupt_request & CPU_INTERRUPT_TPR) { 4914 cs->interrupt_request &= ~CPU_INTERRUPT_TPR; 4915 kvm_cpu_synchronize_state(cs); 4916 apic_handle_tpr_access_report(cpu->apic_state, env->eip, 4917 env->tpr_access_type); 4918 } 4919 4920 return cs->halted; 4921 } 4922 4923 static int kvm_handle_halt(X86CPU *cpu) 4924 { 4925 CPUState *cs = CPU(cpu); 4926 CPUX86State *env = &cpu->env; 4927 4928 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) && 4929 (env->eflags & IF_MASK)) && 4930 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) { 4931 cs->halted = 1; 4932 return EXCP_HLT; 4933 } 4934 4935 return 0; 4936 } 4937 4938 static int kvm_handle_tpr_access(X86CPU *cpu) 4939 { 4940 CPUState *cs = CPU(cpu); 4941 struct kvm_run *run = cs->kvm_run; 4942 4943 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip, 4944 run->tpr_access.is_write ? TPR_ACCESS_WRITE 4945 : TPR_ACCESS_READ); 4946 return 1; 4947 } 4948 4949 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 4950 { 4951 static const uint8_t int3 = 0xcc; 4952 4953 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) || 4954 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) { 4955 return -EINVAL; 4956 } 4957 return 0; 4958 } 4959 4960 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 4961 { 4962 uint8_t int3; 4963 4964 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0)) { 4965 return -EINVAL; 4966 } 4967 if (int3 != 0xcc) { 4968 return 0; 4969 } 4970 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) { 4971 return -EINVAL; 4972 } 4973 return 0; 4974 } 4975 4976 static struct { 4977 target_ulong addr; 4978 int len; 4979 int type; 4980 } hw_breakpoint[4]; 4981 4982 static int nb_hw_breakpoint; 4983 4984 static int find_hw_breakpoint(target_ulong addr, int len, int type) 4985 { 4986 int n; 4987 4988 for (n = 0; n < nb_hw_breakpoint; n++) { 4989 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type && 4990 (hw_breakpoint[n].len == len || len == -1)) { 4991 return n; 4992 } 4993 } 4994 return -1; 4995 } 4996 4997 int kvm_arch_insert_hw_breakpoint(vaddr addr, vaddr len, int type) 4998 { 4999 switch (type) { 5000 case GDB_BREAKPOINT_HW: 5001 len = 1; 5002 break; 5003 case GDB_WATCHPOINT_WRITE: 5004 case GDB_WATCHPOINT_ACCESS: 5005 switch (len) { 5006 case 1: 5007 break; 5008 case 2: 5009 case 4: 5010 case 8: 5011 if (addr & (len - 1)) { 5012 return -EINVAL; 5013 } 5014 break; 5015 default: 5016 return -EINVAL; 5017 } 5018 break; 5019 default: 5020 return -ENOSYS; 5021 } 5022 5023 if (nb_hw_breakpoint == 4) { 5024 return -ENOBUFS; 5025 } 5026 if (find_hw_breakpoint(addr, len, type) >= 0) { 5027 return -EEXIST; 5028 } 5029 hw_breakpoint[nb_hw_breakpoint].addr = addr; 5030 hw_breakpoint[nb_hw_breakpoint].len = len; 5031 hw_breakpoint[nb_hw_breakpoint].type = type; 5032 nb_hw_breakpoint++; 5033 5034 return 0; 5035 } 5036 5037 int kvm_arch_remove_hw_breakpoint(vaddr addr, vaddr len, int type) 5038 { 5039 int n; 5040 5041 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type); 5042 if (n < 0) { 5043 return -ENOENT; 5044 } 5045 nb_hw_breakpoint--; 5046 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint]; 5047 5048 return 0; 5049 } 5050 5051 void kvm_arch_remove_all_hw_breakpoints(void) 5052 { 5053 nb_hw_breakpoint = 0; 5054 } 5055 5056 static CPUWatchpoint hw_watchpoint; 5057 5058 static int kvm_handle_debug(X86CPU *cpu, 5059 struct kvm_debug_exit_arch *arch_info) 5060 { 5061 CPUState *cs = CPU(cpu); 5062 CPUX86State *env = &cpu->env; 5063 int ret = 0; 5064 int n; 5065 5066 if (arch_info->exception == EXCP01_DB) { 5067 if (arch_info->dr6 & DR6_BS) { 5068 if (cs->singlestep_enabled) { 5069 ret = EXCP_DEBUG; 5070 } 5071 } else { 5072 for (n = 0; n < 4; n++) { 5073 if (arch_info->dr6 & (1 << n)) { 5074 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) { 5075 case 0x0: 5076 ret = EXCP_DEBUG; 5077 break; 5078 case 0x1: 5079 ret = EXCP_DEBUG; 5080 cs->watchpoint_hit = &hw_watchpoint; 5081 hw_watchpoint.vaddr = hw_breakpoint[n].addr; 5082 hw_watchpoint.flags = BP_MEM_WRITE; 5083 break; 5084 case 0x3: 5085 ret = EXCP_DEBUG; 5086 cs->watchpoint_hit = &hw_watchpoint; 5087 hw_watchpoint.vaddr = hw_breakpoint[n].addr; 5088 hw_watchpoint.flags = BP_MEM_ACCESS; 5089 break; 5090 } 5091 } 5092 } 5093 } 5094 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) { 5095 ret = EXCP_DEBUG; 5096 } 5097 if (ret == 0) { 5098 cpu_synchronize_state(cs); 5099 assert(env->exception_nr == -1); 5100 5101 /* pass to guest */ 5102 kvm_queue_exception(env, arch_info->exception, 5103 arch_info->exception == EXCP01_DB, 5104 arch_info->dr6); 5105 env->has_error_code = 0; 5106 } 5107 5108 return ret; 5109 } 5110 5111 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg) 5112 { 5113 const uint8_t type_code[] = { 5114 [GDB_BREAKPOINT_HW] = 0x0, 5115 [GDB_WATCHPOINT_WRITE] = 0x1, 5116 [GDB_WATCHPOINT_ACCESS] = 0x3 5117 }; 5118 const uint8_t len_code[] = { 5119 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2 5120 }; 5121 int n; 5122 5123 if (kvm_sw_breakpoints_active(cpu)) { 5124 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP; 5125 } 5126 if (nb_hw_breakpoint > 0) { 5127 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP; 5128 dbg->arch.debugreg[7] = 0x0600; 5129 for (n = 0; n < nb_hw_breakpoint; n++) { 5130 dbg->arch.debugreg[n] = hw_breakpoint[n].addr; 5131 dbg->arch.debugreg[7] |= (2 << (n * 2)) | 5132 (type_code[hw_breakpoint[n].type] << (16 + n*4)) | 5133 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4)); 5134 } 5135 } 5136 } 5137 5138 static bool kvm_install_msr_filters(KVMState *s) 5139 { 5140 uint64_t zero = 0; 5141 struct kvm_msr_filter filter = { 5142 .flags = KVM_MSR_FILTER_DEFAULT_ALLOW, 5143 }; 5144 int r, i, j = 0; 5145 5146 for (i = 0; i < KVM_MSR_FILTER_MAX_RANGES; i++) { 5147 KVMMSRHandlers *handler = &msr_handlers[i]; 5148 if (handler->msr) { 5149 struct kvm_msr_filter_range *range = &filter.ranges[j++]; 5150 5151 *range = (struct kvm_msr_filter_range) { 5152 .flags = 0, 5153 .nmsrs = 1, 5154 .base = handler->msr, 5155 .bitmap = (__u8 *)&zero, 5156 }; 5157 5158 if (handler->rdmsr) { 5159 range->flags |= KVM_MSR_FILTER_READ; 5160 } 5161 5162 if (handler->wrmsr) { 5163 range->flags |= KVM_MSR_FILTER_WRITE; 5164 } 5165 } 5166 } 5167 5168 r = kvm_vm_ioctl(s, KVM_X86_SET_MSR_FILTER, &filter); 5169 if (r) { 5170 return false; 5171 } 5172 5173 return true; 5174 } 5175 5176 bool kvm_filter_msr(KVMState *s, uint32_t msr, QEMURDMSRHandler *rdmsr, 5177 QEMUWRMSRHandler *wrmsr) 5178 { 5179 int i; 5180 5181 for (i = 0; i < ARRAY_SIZE(msr_handlers); i++) { 5182 if (!msr_handlers[i].msr) { 5183 msr_handlers[i] = (KVMMSRHandlers) { 5184 .msr = msr, 5185 .rdmsr = rdmsr, 5186 .wrmsr = wrmsr, 5187 }; 5188 5189 if (!kvm_install_msr_filters(s)) { 5190 msr_handlers[i] = (KVMMSRHandlers) { }; 5191 return false; 5192 } 5193 5194 return true; 5195 } 5196 } 5197 5198 return false; 5199 } 5200 5201 static int kvm_handle_rdmsr(X86CPU *cpu, struct kvm_run *run) 5202 { 5203 int i; 5204 bool r; 5205 5206 for (i = 0; i < ARRAY_SIZE(msr_handlers); i++) { 5207 KVMMSRHandlers *handler = &msr_handlers[i]; 5208 if (run->msr.index == handler->msr) { 5209 if (handler->rdmsr) { 5210 r = handler->rdmsr(cpu, handler->msr, 5211 (uint64_t *)&run->msr.data); 5212 run->msr.error = r ? 0 : 1; 5213 return 0; 5214 } 5215 } 5216 } 5217 5218 assert(false); 5219 } 5220 5221 static int kvm_handle_wrmsr(X86CPU *cpu, struct kvm_run *run) 5222 { 5223 int i; 5224 bool r; 5225 5226 for (i = 0; i < ARRAY_SIZE(msr_handlers); i++) { 5227 KVMMSRHandlers *handler = &msr_handlers[i]; 5228 if (run->msr.index == handler->msr) { 5229 if (handler->wrmsr) { 5230 r = handler->wrmsr(cpu, handler->msr, run->msr.data); 5231 run->msr.error = r ? 0 : 1; 5232 return 0; 5233 } 5234 } 5235 } 5236 5237 assert(false); 5238 } 5239 5240 static bool has_sgx_provisioning; 5241 5242 static bool __kvm_enable_sgx_provisioning(KVMState *s) 5243 { 5244 int fd, ret; 5245 5246 if (!kvm_vm_check_extension(s, KVM_CAP_SGX_ATTRIBUTE)) { 5247 return false; 5248 } 5249 5250 fd = qemu_open_old("/dev/sgx_provision", O_RDONLY); 5251 if (fd < 0) { 5252 return false; 5253 } 5254 5255 ret = kvm_vm_enable_cap(s, KVM_CAP_SGX_ATTRIBUTE, 0, fd); 5256 if (ret) { 5257 error_report("Could not enable SGX PROVISIONKEY: %s", strerror(-ret)); 5258 exit(1); 5259 } 5260 close(fd); 5261 return true; 5262 } 5263 5264 bool kvm_enable_sgx_provisioning(KVMState *s) 5265 { 5266 return MEMORIZE(__kvm_enable_sgx_provisioning(s), has_sgx_provisioning); 5267 } 5268 5269 static bool host_supports_vmx(void) 5270 { 5271 uint32_t ecx, unused; 5272 5273 host_cpuid(1, 0, &unused, &unused, &ecx, &unused); 5274 return ecx & CPUID_EXT_VMX; 5275 } 5276 5277 #define VMX_INVALID_GUEST_STATE 0x80000021 5278 5279 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 5280 { 5281 X86CPU *cpu = X86_CPU(cs); 5282 uint64_t code; 5283 int ret; 5284 bool ctx_invalid; 5285 char str[256]; 5286 KVMState *state; 5287 5288 switch (run->exit_reason) { 5289 case KVM_EXIT_HLT: 5290 DPRINTF("handle_hlt\n"); 5291 bql_lock(); 5292 ret = kvm_handle_halt(cpu); 5293 bql_unlock(); 5294 break; 5295 case KVM_EXIT_SET_TPR: 5296 ret = 0; 5297 break; 5298 case KVM_EXIT_TPR_ACCESS: 5299 bql_lock(); 5300 ret = kvm_handle_tpr_access(cpu); 5301 bql_unlock(); 5302 break; 5303 case KVM_EXIT_FAIL_ENTRY: 5304 code = run->fail_entry.hardware_entry_failure_reason; 5305 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n", 5306 code); 5307 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) { 5308 fprintf(stderr, 5309 "\nIf you're running a guest on an Intel machine without " 5310 "unrestricted mode\n" 5311 "support, the failure can be most likely due to the guest " 5312 "entering an invalid\n" 5313 "state for Intel VT. For example, the guest maybe running " 5314 "in big real mode\n" 5315 "which is not supported on less recent Intel processors." 5316 "\n\n"); 5317 } 5318 ret = -1; 5319 break; 5320 case KVM_EXIT_EXCEPTION: 5321 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n", 5322 run->ex.exception, run->ex.error_code); 5323 ret = -1; 5324 break; 5325 case KVM_EXIT_DEBUG: 5326 DPRINTF("kvm_exit_debug\n"); 5327 bql_lock(); 5328 ret = kvm_handle_debug(cpu, &run->debug.arch); 5329 bql_unlock(); 5330 break; 5331 case KVM_EXIT_HYPERV: 5332 ret = kvm_hv_handle_exit(cpu, &run->hyperv); 5333 break; 5334 case KVM_EXIT_IOAPIC_EOI: 5335 ioapic_eoi_broadcast(run->eoi.vector); 5336 ret = 0; 5337 break; 5338 case KVM_EXIT_X86_BUS_LOCK: 5339 /* already handled in kvm_arch_post_run */ 5340 ret = 0; 5341 break; 5342 case KVM_EXIT_NOTIFY: 5343 ctx_invalid = !!(run->notify.flags & KVM_NOTIFY_CONTEXT_INVALID); 5344 state = KVM_STATE(current_accel()); 5345 sprintf(str, "Encounter a notify exit with %svalid context in" 5346 " guest. There can be possible misbehaves in guest." 5347 " Please have a look.", ctx_invalid ? "in" : ""); 5348 if (ctx_invalid || 5349 state->notify_vmexit == NOTIFY_VMEXIT_OPTION_INTERNAL_ERROR) { 5350 warn_report("KVM internal error: %s", str); 5351 ret = -1; 5352 } else { 5353 warn_report_once("KVM: %s", str); 5354 ret = 0; 5355 } 5356 break; 5357 case KVM_EXIT_X86_RDMSR: 5358 /* We only enable MSR filtering, any other exit is bogus */ 5359 assert(run->msr.reason == KVM_MSR_EXIT_REASON_FILTER); 5360 ret = kvm_handle_rdmsr(cpu, run); 5361 break; 5362 case KVM_EXIT_X86_WRMSR: 5363 /* We only enable MSR filtering, any other exit is bogus */ 5364 assert(run->msr.reason == KVM_MSR_EXIT_REASON_FILTER); 5365 ret = kvm_handle_wrmsr(cpu, run); 5366 break; 5367 #ifdef CONFIG_XEN_EMU 5368 case KVM_EXIT_XEN: 5369 ret = kvm_xen_handle_exit(cpu, &run->xen); 5370 break; 5371 #endif 5372 default: 5373 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason); 5374 ret = -1; 5375 break; 5376 } 5377 5378 return ret; 5379 } 5380 5381 bool kvm_arch_stop_on_emulation_error(CPUState *cs) 5382 { 5383 X86CPU *cpu = X86_CPU(cs); 5384 CPUX86State *env = &cpu->env; 5385 5386 kvm_cpu_synchronize_state(cs); 5387 return !(env->cr[0] & CR0_PE_MASK) || 5388 ((env->segs[R_CS].selector & 3) != 3); 5389 } 5390 5391 void kvm_arch_init_irq_routing(KVMState *s) 5392 { 5393 /* We know at this point that we're using the in-kernel 5394 * irqchip, so we can use irqfds, and on x86 we know 5395 * we can use msi via irqfd and GSI routing. 5396 */ 5397 kvm_msi_via_irqfd_allowed = true; 5398 kvm_gsi_routing_allowed = true; 5399 5400 if (kvm_irqchip_is_split()) { 5401 KVMRouteChange c = kvm_irqchip_begin_route_changes(s); 5402 int i; 5403 5404 /* If the ioapic is in QEMU and the lapics are in KVM, reserve 5405 MSI routes for signaling interrupts to the local apics. */ 5406 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 5407 if (kvm_irqchip_add_msi_route(&c, 0, NULL) < 0) { 5408 error_report("Could not enable split IRQ mode."); 5409 exit(1); 5410 } 5411 } 5412 kvm_irqchip_commit_route_changes(&c); 5413 } 5414 } 5415 5416 int kvm_arch_irqchip_create(KVMState *s) 5417 { 5418 int ret; 5419 if (kvm_kernel_irqchip_split()) { 5420 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24); 5421 if (ret) { 5422 error_report("Could not enable split irqchip mode: %s", 5423 strerror(-ret)); 5424 exit(1); 5425 } else { 5426 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n"); 5427 kvm_split_irqchip = true; 5428 return 1; 5429 } 5430 } else { 5431 return 0; 5432 } 5433 } 5434 5435 uint64_t kvm_swizzle_msi_ext_dest_id(uint64_t address) 5436 { 5437 CPUX86State *env; 5438 uint64_t ext_id; 5439 5440 if (!first_cpu) { 5441 return address; 5442 } 5443 env = &X86_CPU(first_cpu)->env; 5444 if (!(env->features[FEAT_KVM] & (1 << KVM_FEATURE_MSI_EXT_DEST_ID))) { 5445 return address; 5446 } 5447 5448 /* 5449 * If the remappable format bit is set, or the upper bits are 5450 * already set in address_hi, or the low extended bits aren't 5451 * there anyway, do nothing. 5452 */ 5453 ext_id = address & (0xff << MSI_ADDR_DEST_IDX_SHIFT); 5454 if (!ext_id || (ext_id & (1 << MSI_ADDR_DEST_IDX_SHIFT)) || (address >> 32)) { 5455 return address; 5456 } 5457 5458 address &= ~ext_id; 5459 address |= ext_id << 35; 5460 return address; 5461 } 5462 5463 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 5464 uint64_t address, uint32_t data, PCIDevice *dev) 5465 { 5466 X86IOMMUState *iommu = x86_iommu_get_default(); 5467 5468 if (iommu) { 5469 X86IOMMUClass *class = X86_IOMMU_DEVICE_GET_CLASS(iommu); 5470 5471 if (class->int_remap) { 5472 int ret; 5473 MSIMessage src, dst; 5474 5475 src.address = route->u.msi.address_hi; 5476 src.address <<= VTD_MSI_ADDR_HI_SHIFT; 5477 src.address |= route->u.msi.address_lo; 5478 src.data = route->u.msi.data; 5479 5480 ret = class->int_remap(iommu, &src, &dst, dev ? \ 5481 pci_requester_id(dev) : \ 5482 X86_IOMMU_SID_INVALID); 5483 if (ret) { 5484 trace_kvm_x86_fixup_msi_error(route->gsi); 5485 return 1; 5486 } 5487 5488 /* 5489 * Handled untranslated compatibility format interrupt with 5490 * extended destination ID in the low bits 11-5. */ 5491 dst.address = kvm_swizzle_msi_ext_dest_id(dst.address); 5492 5493 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT; 5494 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK; 5495 route->u.msi.data = dst.data; 5496 return 0; 5497 } 5498 } 5499 5500 #ifdef CONFIG_XEN_EMU 5501 if (xen_mode == XEN_EMULATE) { 5502 int handled = xen_evtchn_translate_pirq_msi(route, address, data); 5503 5504 /* 5505 * If it was a PIRQ and successfully routed (handled == 0) or it was 5506 * an error (handled < 0), return. If it wasn't a PIRQ, keep going. 5507 */ 5508 if (handled <= 0) { 5509 return handled; 5510 } 5511 } 5512 #endif 5513 5514 address = kvm_swizzle_msi_ext_dest_id(address); 5515 route->u.msi.address_hi = address >> VTD_MSI_ADDR_HI_SHIFT; 5516 route->u.msi.address_lo = address & VTD_MSI_ADDR_LO_MASK; 5517 return 0; 5518 } 5519 5520 typedef struct MSIRouteEntry MSIRouteEntry; 5521 5522 struct MSIRouteEntry { 5523 PCIDevice *dev; /* Device pointer */ 5524 int vector; /* MSI/MSIX vector index */ 5525 int virq; /* Virtual IRQ index */ 5526 QLIST_ENTRY(MSIRouteEntry) list; 5527 }; 5528 5529 /* List of used GSI routes */ 5530 static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \ 5531 QLIST_HEAD_INITIALIZER(msi_route_list); 5532 5533 void kvm_update_msi_routes_all(void *private, bool global, 5534 uint32_t index, uint32_t mask) 5535 { 5536 int cnt = 0, vector; 5537 MSIRouteEntry *entry; 5538 MSIMessage msg; 5539 PCIDevice *dev; 5540 5541 /* TODO: explicit route update */ 5542 QLIST_FOREACH(entry, &msi_route_list, list) { 5543 cnt++; 5544 vector = entry->vector; 5545 dev = entry->dev; 5546 if (msix_enabled(dev) && !msix_is_masked(dev, vector)) { 5547 msg = msix_get_message(dev, vector); 5548 } else if (msi_enabled(dev) && !msi_is_masked(dev, vector)) { 5549 msg = msi_get_message(dev, vector); 5550 } else { 5551 /* 5552 * Either MSI/MSIX is disabled for the device, or the 5553 * specific message was masked out. Skip this one. 5554 */ 5555 continue; 5556 } 5557 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev); 5558 } 5559 kvm_irqchip_commit_routes(kvm_state); 5560 trace_kvm_x86_update_msi_routes(cnt); 5561 } 5562 5563 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 5564 int vector, PCIDevice *dev) 5565 { 5566 static bool notify_list_inited = false; 5567 MSIRouteEntry *entry; 5568 5569 if (!dev) { 5570 /* These are (possibly) IOAPIC routes only used for split 5571 * kernel irqchip mode, while what we are housekeeping are 5572 * PCI devices only. */ 5573 return 0; 5574 } 5575 5576 entry = g_new0(MSIRouteEntry, 1); 5577 entry->dev = dev; 5578 entry->vector = vector; 5579 entry->virq = route->gsi; 5580 QLIST_INSERT_HEAD(&msi_route_list, entry, list); 5581 5582 trace_kvm_x86_add_msi_route(route->gsi); 5583 5584 if (!notify_list_inited) { 5585 /* For the first time we do add route, add ourselves into 5586 * IOMMU's IEC notify list if needed. */ 5587 X86IOMMUState *iommu = x86_iommu_get_default(); 5588 if (iommu) { 5589 x86_iommu_iec_register_notifier(iommu, 5590 kvm_update_msi_routes_all, 5591 NULL); 5592 } 5593 notify_list_inited = true; 5594 } 5595 return 0; 5596 } 5597 5598 int kvm_arch_release_virq_post(int virq) 5599 { 5600 MSIRouteEntry *entry, *next; 5601 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) { 5602 if (entry->virq == virq) { 5603 trace_kvm_x86_remove_msi_route(virq); 5604 QLIST_REMOVE(entry, list); 5605 g_free(entry); 5606 break; 5607 } 5608 } 5609 return 0; 5610 } 5611 5612 int kvm_arch_msi_data_to_gsi(uint32_t data) 5613 { 5614 abort(); 5615 } 5616 5617 bool kvm_has_waitpkg(void) 5618 { 5619 return has_msr_umwait; 5620 } 5621 5622 #define ARCH_REQ_XCOMP_GUEST_PERM 0x1025 5623 5624 void kvm_request_xsave_components(X86CPU *cpu, uint64_t mask) 5625 { 5626 KVMState *s = kvm_state; 5627 uint64_t supported; 5628 5629 mask &= XSTATE_DYNAMIC_MASK; 5630 if (!mask) { 5631 return; 5632 } 5633 /* 5634 * Just ignore bits that are not in CPUID[EAX=0xD,ECX=0]. 5635 * ARCH_REQ_XCOMP_GUEST_PERM would fail, and QEMU has warned 5636 * about them already because they are not supported features. 5637 */ 5638 supported = kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX); 5639 supported |= (uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32; 5640 mask &= supported; 5641 5642 while (mask) { 5643 int bit = ctz64(mask); 5644 int rc = syscall(SYS_arch_prctl, ARCH_REQ_XCOMP_GUEST_PERM, bit); 5645 if (rc) { 5646 /* 5647 * Older kernel version (<5.17) do not support 5648 * ARCH_REQ_XCOMP_GUEST_PERM, but also do not return 5649 * any dynamic feature from kvm_arch_get_supported_cpuid. 5650 */ 5651 warn_report("prctl(ARCH_REQ_XCOMP_GUEST_PERM) failure " 5652 "for feature bit %d", bit); 5653 } 5654 mask &= ~BIT_ULL(bit); 5655 } 5656 } 5657 5658 static int kvm_arch_get_notify_vmexit(Object *obj, Error **errp) 5659 { 5660 KVMState *s = KVM_STATE(obj); 5661 return s->notify_vmexit; 5662 } 5663 5664 static void kvm_arch_set_notify_vmexit(Object *obj, int value, Error **errp) 5665 { 5666 KVMState *s = KVM_STATE(obj); 5667 5668 if (s->fd != -1) { 5669 error_setg(errp, "Cannot set properties after the accelerator has been initialized"); 5670 return; 5671 } 5672 5673 s->notify_vmexit = value; 5674 } 5675 5676 static void kvm_arch_get_notify_window(Object *obj, Visitor *v, 5677 const char *name, void *opaque, 5678 Error **errp) 5679 { 5680 KVMState *s = KVM_STATE(obj); 5681 uint32_t value = s->notify_window; 5682 5683 visit_type_uint32(v, name, &value, errp); 5684 } 5685 5686 static void kvm_arch_set_notify_window(Object *obj, Visitor *v, 5687 const char *name, void *opaque, 5688 Error **errp) 5689 { 5690 KVMState *s = KVM_STATE(obj); 5691 uint32_t value; 5692 5693 if (s->fd != -1) { 5694 error_setg(errp, "Cannot set properties after the accelerator has been initialized"); 5695 return; 5696 } 5697 5698 if (!visit_type_uint32(v, name, &value, errp)) { 5699 return; 5700 } 5701 5702 s->notify_window = value; 5703 } 5704 5705 static void kvm_arch_get_xen_version(Object *obj, Visitor *v, 5706 const char *name, void *opaque, 5707 Error **errp) 5708 { 5709 KVMState *s = KVM_STATE(obj); 5710 uint32_t value = s->xen_version; 5711 5712 visit_type_uint32(v, name, &value, errp); 5713 } 5714 5715 static void kvm_arch_set_xen_version(Object *obj, Visitor *v, 5716 const char *name, void *opaque, 5717 Error **errp) 5718 { 5719 KVMState *s = KVM_STATE(obj); 5720 Error *error = NULL; 5721 uint32_t value; 5722 5723 visit_type_uint32(v, name, &value, &error); 5724 if (error) { 5725 error_propagate(errp, error); 5726 return; 5727 } 5728 5729 s->xen_version = value; 5730 if (value && xen_mode == XEN_DISABLED) { 5731 xen_mode = XEN_EMULATE; 5732 } 5733 } 5734 5735 static void kvm_arch_get_xen_gnttab_max_frames(Object *obj, Visitor *v, 5736 const char *name, void *opaque, 5737 Error **errp) 5738 { 5739 KVMState *s = KVM_STATE(obj); 5740 uint16_t value = s->xen_gnttab_max_frames; 5741 5742 visit_type_uint16(v, name, &value, errp); 5743 } 5744 5745 static void kvm_arch_set_xen_gnttab_max_frames(Object *obj, Visitor *v, 5746 const char *name, void *opaque, 5747 Error **errp) 5748 { 5749 KVMState *s = KVM_STATE(obj); 5750 Error *error = NULL; 5751 uint16_t value; 5752 5753 visit_type_uint16(v, name, &value, &error); 5754 if (error) { 5755 error_propagate(errp, error); 5756 return; 5757 } 5758 5759 s->xen_gnttab_max_frames = value; 5760 } 5761 5762 static void kvm_arch_get_xen_evtchn_max_pirq(Object *obj, Visitor *v, 5763 const char *name, void *opaque, 5764 Error **errp) 5765 { 5766 KVMState *s = KVM_STATE(obj); 5767 uint16_t value = s->xen_evtchn_max_pirq; 5768 5769 visit_type_uint16(v, name, &value, errp); 5770 } 5771 5772 static void kvm_arch_set_xen_evtchn_max_pirq(Object *obj, Visitor *v, 5773 const char *name, void *opaque, 5774 Error **errp) 5775 { 5776 KVMState *s = KVM_STATE(obj); 5777 Error *error = NULL; 5778 uint16_t value; 5779 5780 visit_type_uint16(v, name, &value, &error); 5781 if (error) { 5782 error_propagate(errp, error); 5783 return; 5784 } 5785 5786 s->xen_evtchn_max_pirq = value; 5787 } 5788 5789 void kvm_arch_accel_class_init(ObjectClass *oc) 5790 { 5791 object_class_property_add_enum(oc, "notify-vmexit", "NotifyVMexitOption", 5792 &NotifyVmexitOption_lookup, 5793 kvm_arch_get_notify_vmexit, 5794 kvm_arch_set_notify_vmexit); 5795 object_class_property_set_description(oc, "notify-vmexit", 5796 "Enable notify VM exit"); 5797 5798 object_class_property_add(oc, "notify-window", "uint32", 5799 kvm_arch_get_notify_window, 5800 kvm_arch_set_notify_window, 5801 NULL, NULL); 5802 object_class_property_set_description(oc, "notify-window", 5803 "Clock cycles without an event window " 5804 "after which a notification VM exit occurs"); 5805 5806 object_class_property_add(oc, "xen-version", "uint32", 5807 kvm_arch_get_xen_version, 5808 kvm_arch_set_xen_version, 5809 NULL, NULL); 5810 object_class_property_set_description(oc, "xen-version", 5811 "Xen version to be emulated " 5812 "(in XENVER_version form " 5813 "e.g. 0x4000a for 4.10)"); 5814 5815 object_class_property_add(oc, "xen-gnttab-max-frames", "uint16", 5816 kvm_arch_get_xen_gnttab_max_frames, 5817 kvm_arch_set_xen_gnttab_max_frames, 5818 NULL, NULL); 5819 object_class_property_set_description(oc, "xen-gnttab-max-frames", 5820 "Maximum number of grant table frames"); 5821 5822 object_class_property_add(oc, "xen-evtchn-max-pirq", "uint16", 5823 kvm_arch_get_xen_evtchn_max_pirq, 5824 kvm_arch_set_xen_evtchn_max_pirq, 5825 NULL, NULL); 5826 object_class_property_set_description(oc, "xen-evtchn-max-pirq", 5827 "Maximum number of Xen PIRQs"); 5828 } 5829 5830 void kvm_set_max_apic_id(uint32_t max_apic_id) 5831 { 5832 kvm_vm_enable_cap(kvm_state, KVM_CAP_MAX_VCPU_ID, 0, max_apic_id); 5833 } 5834