1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU LoongArch CPU 4 * 5 * Copyright (c) 2021 Loongson Technology Corporation Limited 6 */ 7 8 #include "qemu/osdep.h" 9 #include "qemu/log.h" 10 #include "qemu/qemu-print.h" 11 #include "qapi/error.h" 12 #include "qemu/module.h" 13 #include "sysemu/qtest.h" 14 #include "exec/exec-all.h" 15 #include "qapi/qapi-commands-machine-target.h" 16 #include "cpu.h" 17 #include "internals.h" 18 #include "fpu/softfloat-helpers.h" 19 #include "cpu-csr.h" 20 #include "sysemu/reset.h" 21 22 const char * const regnames[32] = { 23 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 24 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 25 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 26 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 27 }; 28 29 const char * const fregnames[32] = { 30 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 31 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 32 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 33 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 34 }; 35 36 static const char * const excp_names[] = { 37 [EXCCODE_INT] = "Interrupt", 38 [EXCCODE_PIL] = "Page invalid exception for load", 39 [EXCCODE_PIS] = "Page invalid exception for store", 40 [EXCCODE_PIF] = "Page invalid exception for fetch", 41 [EXCCODE_PME] = "Page modified exception", 42 [EXCCODE_PNR] = "Page Not Readable exception", 43 [EXCCODE_PNX] = "Page Not Executable exception", 44 [EXCCODE_PPI] = "Page Privilege error", 45 [EXCCODE_ADEF] = "Address error for instruction fetch", 46 [EXCCODE_ADEM] = "Address error for Memory access", 47 [EXCCODE_SYS] = "Syscall", 48 [EXCCODE_BRK] = "Break", 49 [EXCCODE_INE] = "Instruction Non-Existent", 50 [EXCCODE_IPE] = "Instruction privilege error", 51 [EXCCODE_FPD] = "Floating Point Disabled", 52 [EXCCODE_FPE] = "Floating Point Exception", 53 [EXCCODE_DBP] = "Debug breakpoint", 54 [EXCCODE_BCE] = "Bound Check Exception", 55 }; 56 57 const char *loongarch_exception_name(int32_t exception) 58 { 59 assert(excp_names[exception]); 60 return excp_names[exception]; 61 } 62 63 void G_NORETURN do_raise_exception(CPULoongArchState *env, 64 uint32_t exception, 65 uintptr_t pc) 66 { 67 CPUState *cs = env_cpu(env); 68 69 qemu_log_mask(CPU_LOG_INT, "%s: %d (%s)\n", 70 __func__, 71 exception, 72 loongarch_exception_name(exception)); 73 cs->exception_index = exception; 74 75 cpu_loop_exit_restore(cs, pc); 76 } 77 78 static void loongarch_cpu_set_pc(CPUState *cs, vaddr value) 79 { 80 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 81 CPULoongArchState *env = &cpu->env; 82 83 env->pc = value; 84 } 85 86 static vaddr loongarch_cpu_get_pc(CPUState *cs) 87 { 88 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 89 CPULoongArchState *env = &cpu->env; 90 91 return env->pc; 92 } 93 94 #ifndef CONFIG_USER_ONLY 95 #include "hw/loongarch/virt.h" 96 97 void loongarch_cpu_set_irq(void *opaque, int irq, int level) 98 { 99 LoongArchCPU *cpu = opaque; 100 CPULoongArchState *env = &cpu->env; 101 CPUState *cs = CPU(cpu); 102 103 if (irq < 0 || irq >= N_IRQS) { 104 return; 105 } 106 107 env->CSR_ESTAT = deposit64(env->CSR_ESTAT, irq, 1, level != 0); 108 109 if (FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS)) { 110 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 111 } else { 112 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 113 } 114 } 115 116 static inline bool cpu_loongarch_hw_interrupts_enabled(CPULoongArchState *env) 117 { 118 bool ret = 0; 119 120 ret = (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE) && 121 !(FIELD_EX64(env->CSR_DBG, CSR_DBG, DST))); 122 123 return ret; 124 } 125 126 /* Check if there is pending and not masked out interrupt */ 127 static inline bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env) 128 { 129 uint32_t pending; 130 uint32_t status; 131 132 pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS); 133 status = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE); 134 135 return (pending & status) != 0; 136 } 137 138 static void loongarch_cpu_do_interrupt(CPUState *cs) 139 { 140 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 141 CPULoongArchState *env = &cpu->env; 142 bool update_badinstr = 1; 143 int cause = -1; 144 const char *name; 145 bool tlbfill = FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR); 146 uint32_t vec_size = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, VS); 147 148 if (cs->exception_index != EXCCODE_INT) { 149 if (cs->exception_index < 0 || 150 cs->exception_index >= ARRAY_SIZE(excp_names)) { 151 name = "unknown"; 152 } else { 153 name = excp_names[cs->exception_index]; 154 } 155 156 qemu_log_mask(CPU_LOG_INT, 157 "%s enter: pc " TARGET_FMT_lx " ERA " TARGET_FMT_lx 158 " TLBRERA " TARGET_FMT_lx " %s exception\n", __func__, 159 env->pc, env->CSR_ERA, env->CSR_TLBRERA, name); 160 } 161 162 switch (cs->exception_index) { 163 case EXCCODE_DBP: 164 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DCL, 1); 165 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, ECODE, 0xC); 166 goto set_DERA; 167 set_DERA: 168 env->CSR_DERA = env->pc; 169 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DST, 1); 170 env->pc = env->CSR_EENTRY + 0x480; 171 break; 172 case EXCCODE_INT: 173 if (FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) { 174 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DEI, 1); 175 goto set_DERA; 176 } 177 QEMU_FALLTHROUGH; 178 case EXCCODE_PIF: 179 case EXCCODE_ADEF: 180 cause = cs->exception_index; 181 update_badinstr = 0; 182 break; 183 case EXCCODE_SYS: 184 case EXCCODE_BRK: 185 case EXCCODE_INE: 186 case EXCCODE_IPE: 187 case EXCCODE_FPD: 188 case EXCCODE_FPE: 189 case EXCCODE_BCE: 190 env->CSR_BADV = env->pc; 191 QEMU_FALLTHROUGH; 192 case EXCCODE_ADEM: 193 case EXCCODE_PIL: 194 case EXCCODE_PIS: 195 case EXCCODE_PME: 196 case EXCCODE_PNR: 197 case EXCCODE_PNX: 198 case EXCCODE_PPI: 199 cause = cs->exception_index; 200 break; 201 default: 202 qemu_log("Error: exception(%d) has not been supported\n", 203 cs->exception_index); 204 abort(); 205 } 206 207 if (update_badinstr) { 208 env->CSR_BADI = cpu_ldl_code(env, env->pc); 209 } 210 211 /* Save PLV and IE */ 212 if (tlbfill) { 213 env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PPLV, 214 FIELD_EX64(env->CSR_CRMD, 215 CSR_CRMD, PLV)); 216 env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PIE, 217 FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE)); 218 /* set the DA mode */ 219 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1); 220 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0); 221 env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, 222 PC, (env->pc >> 2)); 223 } else { 224 env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE, 225 EXCODE_MCODE(cause)); 226 env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ESUBCODE, 227 EXCODE_SUBCODE(cause)); 228 env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PPLV, 229 FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV)); 230 env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PIE, 231 FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE)); 232 env->CSR_ERA = env->pc; 233 } 234 235 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0); 236 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0); 237 238 if (vec_size) { 239 vec_size = (1 << vec_size) * 4; 240 } 241 242 if (cs->exception_index == EXCCODE_INT) { 243 /* Interrupt */ 244 uint32_t vector = 0; 245 uint32_t pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS); 246 pending &= FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE); 247 248 /* Find the highest-priority interrupt. */ 249 vector = 31 - clz32(pending); 250 env->pc = env->CSR_EENTRY + (EXCCODE_EXTERNAL_INT + vector) * vec_size; 251 qemu_log_mask(CPU_LOG_INT, 252 "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx 253 " cause %d\n" " A " TARGET_FMT_lx " D " 254 TARGET_FMT_lx " vector = %d ExC " TARGET_FMT_lx "ExS" 255 TARGET_FMT_lx "\n", 256 __func__, env->pc, env->CSR_ERA, 257 cause, env->CSR_BADV, env->CSR_DERA, vector, 258 env->CSR_ECFG, env->CSR_ESTAT); 259 } else { 260 if (tlbfill) { 261 env->pc = env->CSR_TLBRENTRY; 262 } else { 263 env->pc = env->CSR_EENTRY; 264 env->pc += EXCODE_MCODE(cause) * vec_size; 265 } 266 qemu_log_mask(CPU_LOG_INT, 267 "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx 268 " cause %d%s\n, ESTAT " TARGET_FMT_lx 269 " EXCFG " TARGET_FMT_lx " BADVA " TARGET_FMT_lx 270 "BADI " TARGET_FMT_lx " SYS_NUM " TARGET_FMT_lu 271 " cpu %d asid " TARGET_FMT_lx "\n", __func__, env->pc, 272 tlbfill ? env->CSR_TLBRERA : env->CSR_ERA, 273 cause, tlbfill ? "(refill)" : "", env->CSR_ESTAT, 274 env->CSR_ECFG, 275 tlbfill ? env->CSR_TLBRBADV : env->CSR_BADV, 276 env->CSR_BADI, env->gpr[11], cs->cpu_index, 277 env->CSR_ASID); 278 } 279 cs->exception_index = -1; 280 } 281 282 static void loongarch_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 283 vaddr addr, unsigned size, 284 MMUAccessType access_type, 285 int mmu_idx, MemTxAttrs attrs, 286 MemTxResult response, 287 uintptr_t retaddr) 288 { 289 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 290 CPULoongArchState *env = &cpu->env; 291 292 if (access_type == MMU_INST_FETCH) { 293 do_raise_exception(env, EXCCODE_ADEF, retaddr); 294 } else { 295 do_raise_exception(env, EXCCODE_ADEM, retaddr); 296 } 297 } 298 299 static bool loongarch_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 300 { 301 if (interrupt_request & CPU_INTERRUPT_HARD) { 302 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 303 CPULoongArchState *env = &cpu->env; 304 305 if (cpu_loongarch_hw_interrupts_enabled(env) && 306 cpu_loongarch_hw_interrupts_pending(env)) { 307 /* Raise it */ 308 cs->exception_index = EXCCODE_INT; 309 loongarch_cpu_do_interrupt(cs); 310 return true; 311 } 312 } 313 return false; 314 } 315 #endif 316 317 #ifdef CONFIG_TCG 318 static void loongarch_cpu_synchronize_from_tb(CPUState *cs, 319 const TranslationBlock *tb) 320 { 321 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 322 CPULoongArchState *env = &cpu->env; 323 324 env->pc = tb_pc(tb); 325 } 326 327 static void loongarch_restore_state_to_opc(CPUState *cs, 328 const TranslationBlock *tb, 329 const uint64_t *data) 330 { 331 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 332 CPULoongArchState *env = &cpu->env; 333 334 env->pc = data[0]; 335 } 336 #endif /* CONFIG_TCG */ 337 338 static bool loongarch_cpu_has_work(CPUState *cs) 339 { 340 #ifdef CONFIG_USER_ONLY 341 return true; 342 #else 343 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 344 CPULoongArchState *env = &cpu->env; 345 bool has_work = false; 346 347 if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && 348 cpu_loongarch_hw_interrupts_pending(env)) { 349 has_work = true; 350 } 351 352 return has_work; 353 #endif 354 } 355 356 static void loongarch_la464_initfn(Object *obj) 357 { 358 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 359 CPULoongArchState *env = &cpu->env; 360 int i; 361 362 for (i = 0; i < 21; i++) { 363 env->cpucfg[i] = 0x0; 364 } 365 366 cpu->dtb_compatible = "loongarch,Loongson-3A5000"; 367 env->cpucfg[0] = 0x14c010; /* PRID */ 368 369 uint32_t data = 0; 370 data = FIELD_DP32(data, CPUCFG1, ARCH, 2); 371 data = FIELD_DP32(data, CPUCFG1, PGMMU, 1); 372 data = FIELD_DP32(data, CPUCFG1, IOCSR, 1); 373 data = FIELD_DP32(data, CPUCFG1, PALEN, 0x2f); 374 data = FIELD_DP32(data, CPUCFG1, VALEN, 0x2f); 375 data = FIELD_DP32(data, CPUCFG1, UAL, 1); 376 data = FIELD_DP32(data, CPUCFG1, RI, 1); 377 data = FIELD_DP32(data, CPUCFG1, EP, 1); 378 data = FIELD_DP32(data, CPUCFG1, RPLV, 1); 379 data = FIELD_DP32(data, CPUCFG1, HP, 1); 380 data = FIELD_DP32(data, CPUCFG1, IOCSR_BRD, 1); 381 env->cpucfg[1] = data; 382 383 data = 0; 384 data = FIELD_DP32(data, CPUCFG2, FP, 1); 385 data = FIELD_DP32(data, CPUCFG2, FP_SP, 1); 386 data = FIELD_DP32(data, CPUCFG2, FP_DP, 1); 387 data = FIELD_DP32(data, CPUCFG2, FP_VER, 1); 388 data = FIELD_DP32(data, CPUCFG2, LLFTP, 1); 389 data = FIELD_DP32(data, CPUCFG2, LLFTP_VER, 1); 390 data = FIELD_DP32(data, CPUCFG2, LAM, 1); 391 env->cpucfg[2] = data; 392 393 env->cpucfg[4] = 100 * 1000 * 1000; /* Crystal frequency */ 394 395 data = 0; 396 data = FIELD_DP32(data, CPUCFG5, CC_MUL, 1); 397 data = FIELD_DP32(data, CPUCFG5, CC_DIV, 1); 398 env->cpucfg[5] = data; 399 400 data = 0; 401 data = FIELD_DP32(data, CPUCFG16, L1_IUPRE, 1); 402 data = FIELD_DP32(data, CPUCFG16, L1_DPRE, 1); 403 data = FIELD_DP32(data, CPUCFG16, L2_IUPRE, 1); 404 data = FIELD_DP32(data, CPUCFG16, L2_IUUNIFY, 1); 405 data = FIELD_DP32(data, CPUCFG16, L2_IUPRIV, 1); 406 data = FIELD_DP32(data, CPUCFG16, L3_IUPRE, 1); 407 data = FIELD_DP32(data, CPUCFG16, L3_IUUNIFY, 1); 408 data = FIELD_DP32(data, CPUCFG16, L3_IUINCL, 1); 409 env->cpucfg[16] = data; 410 411 data = 0; 412 data = FIELD_DP32(data, CPUCFG17, L1IU_WAYS, 3); 413 data = FIELD_DP32(data, CPUCFG17, L1IU_SETS, 8); 414 data = FIELD_DP32(data, CPUCFG17, L1IU_SIZE, 6); 415 env->cpucfg[17] = data; 416 417 data = 0; 418 data = FIELD_DP32(data, CPUCFG18, L1D_WAYS, 3); 419 data = FIELD_DP32(data, CPUCFG18, L1D_SETS, 8); 420 data = FIELD_DP32(data, CPUCFG18, L1D_SIZE, 6); 421 env->cpucfg[18] = data; 422 423 data = 0; 424 data = FIELD_DP32(data, CPUCFG19, L2IU_WAYS, 15); 425 data = FIELD_DP32(data, CPUCFG19, L2IU_SETS, 8); 426 data = FIELD_DP32(data, CPUCFG19, L2IU_SIZE, 6); 427 env->cpucfg[19] = data; 428 429 data = 0; 430 data = FIELD_DP32(data, CPUCFG20, L3IU_WAYS, 15); 431 data = FIELD_DP32(data, CPUCFG20, L3IU_SETS, 14); 432 data = FIELD_DP32(data, CPUCFG20, L3IU_SIZE, 6); 433 env->cpucfg[20] = data; 434 435 env->CSR_ASID = FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa); 436 } 437 438 static void loongarch_cpu_list_entry(gpointer data, gpointer user_data) 439 { 440 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 441 442 qemu_printf("%s\n", typename); 443 } 444 445 void loongarch_cpu_list(void) 446 { 447 GSList *list; 448 list = object_class_get_list_sorted(TYPE_LOONGARCH_CPU, false); 449 g_slist_foreach(list, loongarch_cpu_list_entry, NULL); 450 g_slist_free(list); 451 } 452 453 static void loongarch_cpu_reset(DeviceState *dev) 454 { 455 CPUState *cs = CPU(dev); 456 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 457 LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(cpu); 458 CPULoongArchState *env = &cpu->env; 459 460 lacc->parent_reset(dev); 461 462 env->fcsr0_mask = FCSR0_M1 | FCSR0_M2 | FCSR0_M3; 463 env->fcsr0 = 0x0; 464 465 int n; 466 /* Set csr registers value after reset */ 467 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0); 468 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0); 469 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1); 470 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0); 471 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATF, 1); 472 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATM, 1); 473 474 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, FPE, 0); 475 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, SXE, 0); 476 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, ASXE, 0); 477 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, BTE, 0); 478 479 env->CSR_MISC = 0; 480 481 env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, VS, 0); 482 env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, LIE, 0); 483 484 env->CSR_ESTAT = env->CSR_ESTAT & (~MAKE_64BIT_MASK(0, 2)); 485 env->CSR_RVACFG = FIELD_DP64(env->CSR_RVACFG, CSR_RVACFG, RBITS, 0); 486 env->CSR_TCFG = FIELD_DP64(env->CSR_TCFG, CSR_TCFG, EN, 0); 487 env->CSR_LLBCTL = FIELD_DP64(env->CSR_LLBCTL, CSR_LLBCTL, KLO, 0); 488 env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 0); 489 env->CSR_MERRCTL = FIELD_DP64(env->CSR_MERRCTL, CSR_MERRCTL, ISMERR, 0); 490 491 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, TLB_TYPE, 2); 492 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, MTLB_ENTRY, 63); 493 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_WAYS, 7); 494 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_SETS, 8); 495 496 for (n = 0; n < 4; n++) { 497 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV0, 0); 498 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV1, 0); 499 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV2, 0); 500 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV3, 0); 501 } 502 503 #ifndef CONFIG_USER_ONLY 504 env->pc = 0x1c000000; 505 memset(env->tlb, 0, sizeof(env->tlb)); 506 #endif 507 508 restore_fp_status(env); 509 cs->exception_index = -1; 510 } 511 512 static void loongarch_cpu_disas_set_info(CPUState *s, disassemble_info *info) 513 { 514 info->print_insn = print_insn_loongarch; 515 } 516 517 static void loongarch_cpu_realizefn(DeviceState *dev, Error **errp) 518 { 519 CPUState *cs = CPU(dev); 520 LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(dev); 521 Error *local_err = NULL; 522 523 cpu_exec_realizefn(cs, &local_err); 524 if (local_err != NULL) { 525 error_propagate(errp, local_err); 526 return; 527 } 528 529 loongarch_cpu_register_gdb_regs_for_features(cs); 530 531 cpu_reset(cs); 532 qemu_init_vcpu(cs); 533 534 lacc->parent_realize(dev, errp); 535 } 536 537 #ifndef CONFIG_USER_ONLY 538 static void loongarch_qemu_write(void *opaque, hwaddr addr, 539 uint64_t val, unsigned size) 540 { 541 } 542 543 static uint64_t loongarch_qemu_read(void *opaque, hwaddr addr, unsigned size) 544 { 545 switch (addr) { 546 case FEATURE_REG: 547 return 1ULL << IOCSRF_MSI | 1ULL << IOCSRF_EXTIOI | 548 1ULL << IOCSRF_CSRIPI; 549 case VENDOR_REG: 550 return 0x6e6f73676e6f6f4cULL; /* "Loongson" */ 551 case CPUNAME_REG: 552 return 0x303030354133ULL; /* "3A5000" */ 553 case MISC_FUNC_REG: 554 return 1ULL << IOCSRM_EXTIOI_EN; 555 } 556 return 0ULL; 557 } 558 559 static const MemoryRegionOps loongarch_qemu_ops = { 560 .read = loongarch_qemu_read, 561 .write = loongarch_qemu_write, 562 .endianness = DEVICE_LITTLE_ENDIAN, 563 .valid = { 564 .min_access_size = 4, 565 .max_access_size = 8, 566 }, 567 .impl = { 568 .min_access_size = 8, 569 .max_access_size = 8, 570 }, 571 }; 572 #endif 573 574 static void loongarch_cpu_init(Object *obj) 575 { 576 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 577 578 cpu_set_cpustate_pointers(cpu); 579 580 #ifndef CONFIG_USER_ONLY 581 CPULoongArchState *env = &cpu->env; 582 qdev_init_gpio_in(DEVICE(cpu), loongarch_cpu_set_irq, N_IRQS); 583 timer_init_ns(&cpu->timer, QEMU_CLOCK_VIRTUAL, 584 &loongarch_constant_timer_cb, cpu); 585 memory_region_init_io(&env->system_iocsr, OBJECT(cpu), NULL, 586 env, "iocsr", UINT64_MAX); 587 address_space_init(&env->address_space_iocsr, &env->system_iocsr, "IOCSR"); 588 memory_region_init_io(&env->iocsr_mem, OBJECT(cpu), &loongarch_qemu_ops, 589 NULL, "iocsr_misc", 0x428); 590 memory_region_add_subregion(&env->system_iocsr, 0, &env->iocsr_mem); 591 #endif 592 } 593 594 static ObjectClass *loongarch_cpu_class_by_name(const char *cpu_model) 595 { 596 ObjectClass *oc; 597 598 oc = object_class_by_name(cpu_model); 599 if (!oc) { 600 g_autofree char *typename 601 = g_strdup_printf(LOONGARCH_CPU_TYPE_NAME("%s"), cpu_model); 602 oc = object_class_by_name(typename); 603 if (!oc) { 604 return NULL; 605 } 606 } 607 608 if (object_class_dynamic_cast(oc, TYPE_LOONGARCH_CPU) 609 && !object_class_is_abstract(oc)) { 610 return oc; 611 } 612 return NULL; 613 } 614 615 void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags) 616 { 617 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 618 CPULoongArchState *env = &cpu->env; 619 int i; 620 621 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 622 qemu_fprintf(f, " FCSR0 0x%08x fp_status 0x%02x\n", env->fcsr0, 623 get_float_exception_flags(&env->fp_status)); 624 625 /* gpr */ 626 for (i = 0; i < 32; i++) { 627 if ((i & 3) == 0) { 628 qemu_fprintf(f, " GPR%02d:", i); 629 } 630 qemu_fprintf(f, " %s %016" PRIx64, regnames[i], env->gpr[i]); 631 if ((i & 3) == 3) { 632 qemu_fprintf(f, "\n"); 633 } 634 } 635 636 qemu_fprintf(f, "CRMD=%016" PRIx64 "\n", env->CSR_CRMD); 637 qemu_fprintf(f, "PRMD=%016" PRIx64 "\n", env->CSR_PRMD); 638 qemu_fprintf(f, "EUEN=%016" PRIx64 "\n", env->CSR_EUEN); 639 qemu_fprintf(f, "ESTAT=%016" PRIx64 "\n", env->CSR_ESTAT); 640 qemu_fprintf(f, "ERA=%016" PRIx64 "\n", env->CSR_ERA); 641 qemu_fprintf(f, "BADV=%016" PRIx64 "\n", env->CSR_BADV); 642 qemu_fprintf(f, "BADI=%016" PRIx64 "\n", env->CSR_BADI); 643 qemu_fprintf(f, "EENTRY=%016" PRIx64 "\n", env->CSR_EENTRY); 644 qemu_fprintf(f, "PRCFG1=%016" PRIx64 ", PRCFG2=%016" PRIx64 "," 645 " PRCFG3=%016" PRIx64 "\n", 646 env->CSR_PRCFG1, env->CSR_PRCFG3, env->CSR_PRCFG3); 647 qemu_fprintf(f, "TLBRENTRY=%016" PRIx64 "\n", env->CSR_TLBRENTRY); 648 qemu_fprintf(f, "TLBRBADV=%016" PRIx64 "\n", env->CSR_TLBRBADV); 649 qemu_fprintf(f, "TLBRERA=%016" PRIx64 "\n", env->CSR_TLBRERA); 650 651 /* fpr */ 652 if (flags & CPU_DUMP_FPU) { 653 for (i = 0; i < 32; i++) { 654 qemu_fprintf(f, " %s %016" PRIx64, fregnames[i], env->fpr[i]); 655 if ((i & 3) == 3) { 656 qemu_fprintf(f, "\n"); 657 } 658 } 659 } 660 } 661 662 #ifdef CONFIG_TCG 663 #include "hw/core/tcg-cpu-ops.h" 664 665 static struct TCGCPUOps loongarch_tcg_ops = { 666 .initialize = loongarch_translate_init, 667 .synchronize_from_tb = loongarch_cpu_synchronize_from_tb, 668 .restore_state_to_opc = loongarch_restore_state_to_opc, 669 670 #ifndef CONFIG_USER_ONLY 671 .tlb_fill = loongarch_cpu_tlb_fill, 672 .cpu_exec_interrupt = loongarch_cpu_exec_interrupt, 673 .do_interrupt = loongarch_cpu_do_interrupt, 674 .do_transaction_failed = loongarch_cpu_do_transaction_failed, 675 #endif 676 }; 677 #endif /* CONFIG_TCG */ 678 679 #ifndef CONFIG_USER_ONLY 680 #include "hw/core/sysemu-cpu-ops.h" 681 682 static const struct SysemuCPUOps loongarch_sysemu_ops = { 683 .get_phys_page_debug = loongarch_cpu_get_phys_page_debug, 684 }; 685 #endif 686 687 static gchar *loongarch_gdb_arch_name(CPUState *cs) 688 { 689 return g_strdup("loongarch64"); 690 } 691 692 static void loongarch_cpu_class_init(ObjectClass *c, void *data) 693 { 694 LoongArchCPUClass *lacc = LOONGARCH_CPU_CLASS(c); 695 CPUClass *cc = CPU_CLASS(c); 696 DeviceClass *dc = DEVICE_CLASS(c); 697 698 device_class_set_parent_realize(dc, loongarch_cpu_realizefn, 699 &lacc->parent_realize); 700 device_class_set_parent_reset(dc, loongarch_cpu_reset, &lacc->parent_reset); 701 702 cc->class_by_name = loongarch_cpu_class_by_name; 703 cc->has_work = loongarch_cpu_has_work; 704 cc->dump_state = loongarch_cpu_dump_state; 705 cc->set_pc = loongarch_cpu_set_pc; 706 cc->get_pc = loongarch_cpu_get_pc; 707 #ifndef CONFIG_USER_ONLY 708 dc->vmsd = &vmstate_loongarch_cpu; 709 cc->sysemu_ops = &loongarch_sysemu_ops; 710 #endif 711 cc->disas_set_info = loongarch_cpu_disas_set_info; 712 cc->gdb_read_register = loongarch_cpu_gdb_read_register; 713 cc->gdb_write_register = loongarch_cpu_gdb_write_register; 714 cc->disas_set_info = loongarch_cpu_disas_set_info; 715 cc->gdb_num_core_regs = 35; 716 cc->gdb_core_xml_file = "loongarch-base64.xml"; 717 cc->gdb_stop_before_watchpoint = true; 718 cc->gdb_arch_name = loongarch_gdb_arch_name; 719 720 #ifdef CONFIG_TCG 721 cc->tcg_ops = &loongarch_tcg_ops; 722 #endif 723 } 724 725 #define DEFINE_LOONGARCH_CPU_TYPE(model, initfn) \ 726 { \ 727 .parent = TYPE_LOONGARCH_CPU, \ 728 .instance_init = initfn, \ 729 .name = LOONGARCH_CPU_TYPE_NAME(model), \ 730 } 731 732 static const TypeInfo loongarch_cpu_type_infos[] = { 733 { 734 .name = TYPE_LOONGARCH_CPU, 735 .parent = TYPE_CPU, 736 .instance_size = sizeof(LoongArchCPU), 737 .instance_init = loongarch_cpu_init, 738 739 .abstract = true, 740 .class_size = sizeof(LoongArchCPUClass), 741 .class_init = loongarch_cpu_class_init, 742 }, 743 DEFINE_LOONGARCH_CPU_TYPE("la464", loongarch_la464_initfn), 744 }; 745 746 DEFINE_TYPES(loongarch_cpu_type_infos) 747 748 static void loongarch_cpu_add_definition(gpointer data, gpointer user_data) 749 { 750 ObjectClass *oc = data; 751 CpuDefinitionInfoList **cpu_list = user_data; 752 CpuDefinitionInfo *info = g_new0(CpuDefinitionInfo, 1); 753 const char *typename = object_class_get_name(oc); 754 755 info->name = g_strndup(typename, 756 strlen(typename) - strlen("-" TYPE_LOONGARCH_CPU)); 757 info->q_typename = g_strdup(typename); 758 759 QAPI_LIST_PREPEND(*cpu_list, info); 760 } 761 762 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 763 { 764 CpuDefinitionInfoList *cpu_list = NULL; 765 GSList *list; 766 767 list = object_class_get_list(TYPE_LOONGARCH_CPU, false); 768 g_slist_foreach(list, loongarch_cpu_add_definition, &cpu_list); 769 g_slist_free(list); 770 771 return cpu_list; 772 } 773