1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU LoongArch CPU 4 * 5 * Copyright (c) 2021 Loongson Technology Corporation Limited 6 */ 7 8 #include "qemu/osdep.h" 9 #include "qemu/log.h" 10 #include "qemu/qemu-print.h" 11 #include "qapi/error.h" 12 #include "qemu/module.h" 13 #include "sysemu/qtest.h" 14 #include "exec/exec-all.h" 15 #include "qapi/qapi-commands-machine-target.h" 16 #include "cpu.h" 17 #include "internals.h" 18 #include "fpu/softfloat-helpers.h" 19 #include "cpu-csr.h" 20 #include "sysemu/reset.h" 21 22 const char * const regnames[32] = { 23 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 24 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 25 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 26 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 27 }; 28 29 const char * const fregnames[32] = { 30 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 31 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 32 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 33 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 34 }; 35 36 static const char * const excp_names[] = { 37 [EXCCODE_INT] = "Interrupt", 38 [EXCCODE_PIL] = "Page invalid exception for load", 39 [EXCCODE_PIS] = "Page invalid exception for store", 40 [EXCCODE_PIF] = "Page invalid exception for fetch", 41 [EXCCODE_PME] = "Page modified exception", 42 [EXCCODE_PNR] = "Page Not Readable exception", 43 [EXCCODE_PNX] = "Page Not Executable exception", 44 [EXCCODE_PPI] = "Page Privilege error", 45 [EXCCODE_ADEF] = "Address error for instruction fetch", 46 [EXCCODE_ADEM] = "Address error for Memory access", 47 [EXCCODE_SYS] = "Syscall", 48 [EXCCODE_BRK] = "Break", 49 [EXCCODE_INE] = "Instruction Non-Existent", 50 [EXCCODE_IPE] = "Instruction privilege error", 51 [EXCCODE_FPD] = "Floating Point Disabled", 52 [EXCCODE_FPE] = "Floating Point Exception", 53 [EXCCODE_DBP] = "Debug breakpoint", 54 [EXCCODE_BCE] = "Bound Check Exception", 55 }; 56 57 const char *loongarch_exception_name(int32_t exception) 58 { 59 assert(excp_names[exception]); 60 return excp_names[exception]; 61 } 62 63 void G_NORETURN do_raise_exception(CPULoongArchState *env, 64 uint32_t exception, 65 uintptr_t pc) 66 { 67 CPUState *cs = env_cpu(env); 68 69 qemu_log_mask(CPU_LOG_INT, "%s: %d (%s)\n", 70 __func__, 71 exception, 72 loongarch_exception_name(exception)); 73 cs->exception_index = exception; 74 75 cpu_loop_exit_restore(cs, pc); 76 } 77 78 static void loongarch_cpu_set_pc(CPUState *cs, vaddr value) 79 { 80 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 81 CPULoongArchState *env = &cpu->env; 82 83 env->pc = value; 84 } 85 86 static vaddr loongarch_cpu_get_pc(CPUState *cs) 87 { 88 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 89 CPULoongArchState *env = &cpu->env; 90 91 return env->pc; 92 } 93 94 #ifndef CONFIG_USER_ONLY 95 #include "hw/loongarch/virt.h" 96 97 void loongarch_cpu_set_irq(void *opaque, int irq, int level) 98 { 99 LoongArchCPU *cpu = opaque; 100 CPULoongArchState *env = &cpu->env; 101 CPUState *cs = CPU(cpu); 102 103 if (irq < 0 || irq >= N_IRQS) { 104 return; 105 } 106 107 env->CSR_ESTAT = deposit64(env->CSR_ESTAT, irq, 1, level != 0); 108 109 if (FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS)) { 110 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 111 } else { 112 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 113 } 114 } 115 116 static inline bool cpu_loongarch_hw_interrupts_enabled(CPULoongArchState *env) 117 { 118 bool ret = 0; 119 120 ret = (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE) && 121 !(FIELD_EX64(env->CSR_DBG, CSR_DBG, DST))); 122 123 return ret; 124 } 125 126 /* Check if there is pending and not masked out interrupt */ 127 static inline bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env) 128 { 129 uint32_t pending; 130 uint32_t status; 131 bool r; 132 133 pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS); 134 status = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE); 135 136 r = (pending & status) != 0; 137 return r; 138 } 139 140 static void loongarch_cpu_do_interrupt(CPUState *cs) 141 { 142 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 143 CPULoongArchState *env = &cpu->env; 144 bool update_badinstr = 1; 145 int cause = -1; 146 const char *name; 147 bool tlbfill = FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR); 148 uint32_t vec_size = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, VS); 149 150 if (cs->exception_index != EXCCODE_INT) { 151 if (cs->exception_index < 0 || 152 cs->exception_index >= ARRAY_SIZE(excp_names)) { 153 name = "unknown"; 154 } else { 155 name = excp_names[cs->exception_index]; 156 } 157 158 qemu_log_mask(CPU_LOG_INT, 159 "%s enter: pc " TARGET_FMT_lx " ERA " TARGET_FMT_lx 160 " TLBRERA " TARGET_FMT_lx " %s exception\n", __func__, 161 env->pc, env->CSR_ERA, env->CSR_TLBRERA, name); 162 } 163 164 switch (cs->exception_index) { 165 case EXCCODE_DBP: 166 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DCL, 1); 167 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, ECODE, 0xC); 168 goto set_DERA; 169 set_DERA: 170 env->CSR_DERA = env->pc; 171 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DST, 1); 172 env->pc = env->CSR_EENTRY + 0x480; 173 break; 174 case EXCCODE_INT: 175 if (FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) { 176 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DEI, 1); 177 goto set_DERA; 178 } 179 QEMU_FALLTHROUGH; 180 case EXCCODE_PIF: 181 case EXCCODE_ADEF: 182 cause = cs->exception_index; 183 update_badinstr = 0; 184 break; 185 case EXCCODE_SYS: 186 case EXCCODE_BRK: 187 case EXCCODE_INE: 188 case EXCCODE_IPE: 189 case EXCCODE_FPD: 190 case EXCCODE_FPE: 191 case EXCCODE_BCE: 192 env->CSR_BADV = env->pc; 193 QEMU_FALLTHROUGH; 194 case EXCCODE_ADEM: 195 case EXCCODE_PIL: 196 case EXCCODE_PIS: 197 case EXCCODE_PME: 198 case EXCCODE_PNR: 199 case EXCCODE_PNX: 200 case EXCCODE_PPI: 201 cause = cs->exception_index; 202 break; 203 default: 204 qemu_log("Error: exception(%d) has not been supported\n", 205 cs->exception_index); 206 abort(); 207 } 208 209 if (update_badinstr) { 210 env->CSR_BADI = cpu_ldl_code(env, env->pc); 211 } 212 213 /* Save PLV and IE */ 214 if (tlbfill) { 215 env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PPLV, 216 FIELD_EX64(env->CSR_CRMD, 217 CSR_CRMD, PLV)); 218 env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PIE, 219 FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE)); 220 /* set the DA mode */ 221 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1); 222 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0); 223 env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, 224 PC, (env->pc >> 2)); 225 } else { 226 env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE, 227 EXCODE_MCODE(cause)); 228 env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ESUBCODE, 229 EXCODE_SUBCODE(cause)); 230 env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PPLV, 231 FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV)); 232 env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PIE, 233 FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE)); 234 env->CSR_ERA = env->pc; 235 } 236 237 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0); 238 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0); 239 240 if (vec_size) { 241 vec_size = (1 << vec_size) * 4; 242 } 243 244 if (cs->exception_index == EXCCODE_INT) { 245 /* Interrupt */ 246 uint32_t vector = 0; 247 uint32_t pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS); 248 pending &= FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE); 249 250 /* Find the highest-priority interrupt. */ 251 vector = 31 - clz32(pending); 252 env->pc = env->CSR_EENTRY + (EXCCODE_EXTERNAL_INT + vector) * vec_size; 253 qemu_log_mask(CPU_LOG_INT, 254 "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx 255 " cause %d\n" " A " TARGET_FMT_lx " D " 256 TARGET_FMT_lx " vector = %d ExC " TARGET_FMT_lx "ExS" 257 TARGET_FMT_lx "\n", 258 __func__, env->pc, env->CSR_ERA, 259 cause, env->CSR_BADV, env->CSR_DERA, vector, 260 env->CSR_ECFG, env->CSR_ESTAT); 261 } else { 262 if (tlbfill) { 263 env->pc = env->CSR_TLBRENTRY; 264 } else { 265 env->pc = env->CSR_EENTRY; 266 env->pc += EXCODE_MCODE(cause) * vec_size; 267 } 268 qemu_log_mask(CPU_LOG_INT, 269 "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx 270 " cause %d%s\n, ESTAT " TARGET_FMT_lx 271 " EXCFG " TARGET_FMT_lx " BADVA " TARGET_FMT_lx 272 "BADI " TARGET_FMT_lx " SYS_NUM " TARGET_FMT_lu 273 " cpu %d asid " TARGET_FMT_lx "\n", __func__, env->pc, 274 tlbfill ? env->CSR_TLBRERA : env->CSR_ERA, 275 cause, tlbfill ? "(refill)" : "", env->CSR_ESTAT, 276 env->CSR_ECFG, 277 tlbfill ? env->CSR_TLBRBADV : env->CSR_BADV, 278 env->CSR_BADI, env->gpr[11], cs->cpu_index, 279 env->CSR_ASID); 280 } 281 cs->exception_index = -1; 282 } 283 284 static void loongarch_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 285 vaddr addr, unsigned size, 286 MMUAccessType access_type, 287 int mmu_idx, MemTxAttrs attrs, 288 MemTxResult response, 289 uintptr_t retaddr) 290 { 291 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 292 CPULoongArchState *env = &cpu->env; 293 294 if (access_type == MMU_INST_FETCH) { 295 do_raise_exception(env, EXCCODE_ADEF, retaddr); 296 } else { 297 do_raise_exception(env, EXCCODE_ADEM, retaddr); 298 } 299 } 300 301 static bool loongarch_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 302 { 303 if (interrupt_request & CPU_INTERRUPT_HARD) { 304 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 305 CPULoongArchState *env = &cpu->env; 306 307 if (cpu_loongarch_hw_interrupts_enabled(env) && 308 cpu_loongarch_hw_interrupts_pending(env)) { 309 /* Raise it */ 310 cs->exception_index = EXCCODE_INT; 311 loongarch_cpu_do_interrupt(cs); 312 return true; 313 } 314 } 315 return false; 316 } 317 #endif 318 319 #ifdef CONFIG_TCG 320 static void loongarch_cpu_synchronize_from_tb(CPUState *cs, 321 const TranslationBlock *tb) 322 { 323 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 324 CPULoongArchState *env = &cpu->env; 325 326 env->pc = tb_pc(tb); 327 } 328 329 static void loongarch_restore_state_to_opc(CPUState *cs, 330 const TranslationBlock *tb, 331 const uint64_t *data) 332 { 333 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 334 CPULoongArchState *env = &cpu->env; 335 336 env->pc = data[0]; 337 } 338 #endif /* CONFIG_TCG */ 339 340 static bool loongarch_cpu_has_work(CPUState *cs) 341 { 342 #ifdef CONFIG_USER_ONLY 343 return true; 344 #else 345 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 346 CPULoongArchState *env = &cpu->env; 347 bool has_work = false; 348 349 if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && 350 cpu_loongarch_hw_interrupts_pending(env)) { 351 has_work = true; 352 } 353 354 return has_work; 355 #endif 356 } 357 358 static void loongarch_la464_initfn(Object *obj) 359 { 360 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 361 CPULoongArchState *env = &cpu->env; 362 int i; 363 364 for (i = 0; i < 21; i++) { 365 env->cpucfg[i] = 0x0; 366 } 367 368 cpu->dtb_compatible = "loongarch,Loongson-3A5000"; 369 env->cpucfg[0] = 0x14c010; /* PRID */ 370 371 uint32_t data = 0; 372 data = FIELD_DP32(data, CPUCFG1, ARCH, 2); 373 data = FIELD_DP32(data, CPUCFG1, PGMMU, 1); 374 data = FIELD_DP32(data, CPUCFG1, IOCSR, 1); 375 data = FIELD_DP32(data, CPUCFG1, PALEN, 0x2f); 376 data = FIELD_DP32(data, CPUCFG1, VALEN, 0x2f); 377 data = FIELD_DP32(data, CPUCFG1, UAL, 1); 378 data = FIELD_DP32(data, CPUCFG1, RI, 1); 379 data = FIELD_DP32(data, CPUCFG1, EP, 1); 380 data = FIELD_DP32(data, CPUCFG1, RPLV, 1); 381 data = FIELD_DP32(data, CPUCFG1, HP, 1); 382 data = FIELD_DP32(data, CPUCFG1, IOCSR_BRD, 1); 383 env->cpucfg[1] = data; 384 385 data = 0; 386 data = FIELD_DP32(data, CPUCFG2, FP, 1); 387 data = FIELD_DP32(data, CPUCFG2, FP_SP, 1); 388 data = FIELD_DP32(data, CPUCFG2, FP_DP, 1); 389 data = FIELD_DP32(data, CPUCFG2, FP_VER, 1); 390 data = FIELD_DP32(data, CPUCFG2, LLFTP, 1); 391 data = FIELD_DP32(data, CPUCFG2, LLFTP_VER, 1); 392 data = FIELD_DP32(data, CPUCFG2, LAM, 1); 393 env->cpucfg[2] = data; 394 395 env->cpucfg[4] = 100 * 1000 * 1000; /* Crystal frequency */ 396 397 data = 0; 398 data = FIELD_DP32(data, CPUCFG5, CC_MUL, 1); 399 data = FIELD_DP32(data, CPUCFG5, CC_DIV, 1); 400 env->cpucfg[5] = data; 401 402 data = 0; 403 data = FIELD_DP32(data, CPUCFG16, L1_IUPRE, 1); 404 data = FIELD_DP32(data, CPUCFG16, L1_DPRE, 1); 405 data = FIELD_DP32(data, CPUCFG16, L2_IUPRE, 1); 406 data = FIELD_DP32(data, CPUCFG16, L2_IUUNIFY, 1); 407 data = FIELD_DP32(data, CPUCFG16, L2_IUPRIV, 1); 408 data = FIELD_DP32(data, CPUCFG16, L3_IUPRE, 1); 409 data = FIELD_DP32(data, CPUCFG16, L3_IUUNIFY, 1); 410 data = FIELD_DP32(data, CPUCFG16, L3_IUINCL, 1); 411 env->cpucfg[16] = data; 412 413 data = 0; 414 data = FIELD_DP32(data, CPUCFG17, L1IU_WAYS, 3); 415 data = FIELD_DP32(data, CPUCFG17, L1IU_SETS, 8); 416 data = FIELD_DP32(data, CPUCFG17, L1IU_SIZE, 6); 417 env->cpucfg[17] = data; 418 419 data = 0; 420 data = FIELD_DP32(data, CPUCFG18, L1D_WAYS, 3); 421 data = FIELD_DP32(data, CPUCFG18, L1D_SETS, 8); 422 data = FIELD_DP32(data, CPUCFG18, L1D_SIZE, 6); 423 env->cpucfg[18] = data; 424 425 data = 0; 426 data = FIELD_DP32(data, CPUCFG19, L2IU_WAYS, 15); 427 data = FIELD_DP32(data, CPUCFG19, L2IU_SETS, 8); 428 data = FIELD_DP32(data, CPUCFG19, L2IU_SIZE, 6); 429 env->cpucfg[19] = data; 430 431 data = 0; 432 data = FIELD_DP32(data, CPUCFG20, L3IU_WAYS, 15); 433 data = FIELD_DP32(data, CPUCFG20, L3IU_SETS, 14); 434 data = FIELD_DP32(data, CPUCFG20, L3IU_SIZE, 6); 435 env->cpucfg[20] = data; 436 437 env->CSR_ASID = FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa); 438 } 439 440 static void loongarch_cpu_list_entry(gpointer data, gpointer user_data) 441 { 442 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 443 444 qemu_printf("%s\n", typename); 445 } 446 447 void loongarch_cpu_list(void) 448 { 449 GSList *list; 450 list = object_class_get_list_sorted(TYPE_LOONGARCH_CPU, false); 451 g_slist_foreach(list, loongarch_cpu_list_entry, NULL); 452 g_slist_free(list); 453 } 454 455 static void loongarch_cpu_reset(DeviceState *dev) 456 { 457 CPUState *cs = CPU(dev); 458 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 459 LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(cpu); 460 CPULoongArchState *env = &cpu->env; 461 462 lacc->parent_reset(dev); 463 464 env->fcsr0_mask = FCSR0_M1 | FCSR0_M2 | FCSR0_M3; 465 env->fcsr0 = 0x0; 466 467 int n; 468 /* Set csr registers value after reset */ 469 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0); 470 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0); 471 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1); 472 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0); 473 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATF, 1); 474 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATM, 1); 475 476 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, FPE, 0); 477 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, SXE, 0); 478 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, ASXE, 0); 479 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, BTE, 0); 480 481 env->CSR_MISC = 0; 482 483 env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, VS, 0); 484 env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, LIE, 0); 485 486 env->CSR_ESTAT = env->CSR_ESTAT & (~MAKE_64BIT_MASK(0, 2)); 487 env->CSR_RVACFG = FIELD_DP64(env->CSR_RVACFG, CSR_RVACFG, RBITS, 0); 488 env->CSR_TCFG = FIELD_DP64(env->CSR_TCFG, CSR_TCFG, EN, 0); 489 env->CSR_LLBCTL = FIELD_DP64(env->CSR_LLBCTL, CSR_LLBCTL, KLO, 0); 490 env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 0); 491 env->CSR_MERRCTL = FIELD_DP64(env->CSR_MERRCTL, CSR_MERRCTL, ISMERR, 0); 492 493 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, TLB_TYPE, 2); 494 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, MTLB_ENTRY, 63); 495 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_WAYS, 7); 496 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_SETS, 8); 497 498 for (n = 0; n < 4; n++) { 499 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV0, 0); 500 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV1, 0); 501 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV2, 0); 502 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV3, 0); 503 } 504 505 #ifndef CONFIG_USER_ONLY 506 env->pc = 0x1c000000; 507 memset(env->tlb, 0, sizeof(env->tlb)); 508 #endif 509 510 restore_fp_status(env); 511 cs->exception_index = -1; 512 } 513 514 static void loongarch_cpu_disas_set_info(CPUState *s, disassemble_info *info) 515 { 516 info->print_insn = print_insn_loongarch; 517 } 518 519 static void loongarch_cpu_realizefn(DeviceState *dev, Error **errp) 520 { 521 CPUState *cs = CPU(dev); 522 LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(dev); 523 Error *local_err = NULL; 524 525 cpu_exec_realizefn(cs, &local_err); 526 if (local_err != NULL) { 527 error_propagate(errp, local_err); 528 return; 529 } 530 531 loongarch_cpu_register_gdb_regs_for_features(cs); 532 533 cpu_reset(cs); 534 qemu_init_vcpu(cs); 535 536 lacc->parent_realize(dev, errp); 537 } 538 539 #ifndef CONFIG_USER_ONLY 540 static void loongarch_qemu_write(void *opaque, hwaddr addr, 541 uint64_t val, unsigned size) 542 { 543 } 544 545 static uint64_t loongarch_qemu_read(void *opaque, hwaddr addr, unsigned size) 546 { 547 switch (addr) { 548 case FEATURE_REG: 549 return 1ULL << IOCSRF_MSI | 1ULL << IOCSRF_EXTIOI | 550 1ULL << IOCSRF_CSRIPI; 551 case VENDOR_REG: 552 return 0x6e6f73676e6f6f4cULL; /* "Loongson" */ 553 case CPUNAME_REG: 554 return 0x303030354133ULL; /* "3A5000" */ 555 case MISC_FUNC_REG: 556 return 1ULL << IOCSRM_EXTIOI_EN; 557 } 558 return 0ULL; 559 } 560 561 static const MemoryRegionOps loongarch_qemu_ops = { 562 .read = loongarch_qemu_read, 563 .write = loongarch_qemu_write, 564 .endianness = DEVICE_LITTLE_ENDIAN, 565 .valid = { 566 .min_access_size = 4, 567 .max_access_size = 8, 568 }, 569 .impl = { 570 .min_access_size = 8, 571 .max_access_size = 8, 572 }, 573 }; 574 #endif 575 576 static void loongarch_cpu_init(Object *obj) 577 { 578 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 579 580 cpu_set_cpustate_pointers(cpu); 581 582 #ifndef CONFIG_USER_ONLY 583 CPULoongArchState *env = &cpu->env; 584 qdev_init_gpio_in(DEVICE(cpu), loongarch_cpu_set_irq, N_IRQS); 585 timer_init_ns(&cpu->timer, QEMU_CLOCK_VIRTUAL, 586 &loongarch_constant_timer_cb, cpu); 587 memory_region_init_io(&env->system_iocsr, OBJECT(cpu), NULL, 588 env, "iocsr", UINT64_MAX); 589 address_space_init(&env->address_space_iocsr, &env->system_iocsr, "IOCSR"); 590 memory_region_init_io(&env->iocsr_mem, OBJECT(cpu), &loongarch_qemu_ops, 591 NULL, "iocsr_misc", 0x428); 592 memory_region_add_subregion(&env->system_iocsr, 0, &env->iocsr_mem); 593 #endif 594 } 595 596 static ObjectClass *loongarch_cpu_class_by_name(const char *cpu_model) 597 { 598 ObjectClass *oc; 599 600 oc = object_class_by_name(cpu_model); 601 if (!oc) { 602 g_autofree char *typename 603 = g_strdup_printf(LOONGARCH_CPU_TYPE_NAME("%s"), cpu_model); 604 oc = object_class_by_name(typename); 605 if (!oc) { 606 return NULL; 607 } 608 } 609 610 if (object_class_dynamic_cast(oc, TYPE_LOONGARCH_CPU) 611 && !object_class_is_abstract(oc)) { 612 return oc; 613 } 614 return NULL; 615 } 616 617 void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags) 618 { 619 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 620 CPULoongArchState *env = &cpu->env; 621 int i; 622 623 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 624 qemu_fprintf(f, " FCSR0 0x%08x fp_status 0x%02x\n", env->fcsr0, 625 get_float_exception_flags(&env->fp_status)); 626 627 /* gpr */ 628 for (i = 0; i < 32; i++) { 629 if ((i & 3) == 0) { 630 qemu_fprintf(f, " GPR%02d:", i); 631 } 632 qemu_fprintf(f, " %s %016" PRIx64, regnames[i], env->gpr[i]); 633 if ((i & 3) == 3) { 634 qemu_fprintf(f, "\n"); 635 } 636 } 637 638 qemu_fprintf(f, "CRMD=%016" PRIx64 "\n", env->CSR_CRMD); 639 qemu_fprintf(f, "PRMD=%016" PRIx64 "\n", env->CSR_PRMD); 640 qemu_fprintf(f, "EUEN=%016" PRIx64 "\n", env->CSR_EUEN); 641 qemu_fprintf(f, "ESTAT=%016" PRIx64 "\n", env->CSR_ESTAT); 642 qemu_fprintf(f, "ERA=%016" PRIx64 "\n", env->CSR_ERA); 643 qemu_fprintf(f, "BADV=%016" PRIx64 "\n", env->CSR_BADV); 644 qemu_fprintf(f, "BADI=%016" PRIx64 "\n", env->CSR_BADI); 645 qemu_fprintf(f, "EENTRY=%016" PRIx64 "\n", env->CSR_EENTRY); 646 qemu_fprintf(f, "PRCFG1=%016" PRIx64 ", PRCFG2=%016" PRIx64 "," 647 " PRCFG3=%016" PRIx64 "\n", 648 env->CSR_PRCFG1, env->CSR_PRCFG3, env->CSR_PRCFG3); 649 qemu_fprintf(f, "TLBRENTRY=%016" PRIx64 "\n", env->CSR_TLBRENTRY); 650 qemu_fprintf(f, "TLBRBADV=%016" PRIx64 "\n", env->CSR_TLBRBADV); 651 qemu_fprintf(f, "TLBRERA=%016" PRIx64 "\n", env->CSR_TLBRERA); 652 653 /* fpr */ 654 if (flags & CPU_DUMP_FPU) { 655 for (i = 0; i < 32; i++) { 656 qemu_fprintf(f, " %s %016" PRIx64, fregnames[i], env->fpr[i]); 657 if ((i & 3) == 3) { 658 qemu_fprintf(f, "\n"); 659 } 660 } 661 } 662 } 663 664 #ifdef CONFIG_TCG 665 #include "hw/core/tcg-cpu-ops.h" 666 667 static struct TCGCPUOps loongarch_tcg_ops = { 668 .initialize = loongarch_translate_init, 669 .synchronize_from_tb = loongarch_cpu_synchronize_from_tb, 670 .restore_state_to_opc = loongarch_restore_state_to_opc, 671 672 #ifndef CONFIG_USER_ONLY 673 .tlb_fill = loongarch_cpu_tlb_fill, 674 .cpu_exec_interrupt = loongarch_cpu_exec_interrupt, 675 .do_interrupt = loongarch_cpu_do_interrupt, 676 .do_transaction_failed = loongarch_cpu_do_transaction_failed, 677 #endif 678 }; 679 #endif /* CONFIG_TCG */ 680 681 #ifndef CONFIG_USER_ONLY 682 #include "hw/core/sysemu-cpu-ops.h" 683 684 static const struct SysemuCPUOps loongarch_sysemu_ops = { 685 .get_phys_page_debug = loongarch_cpu_get_phys_page_debug, 686 }; 687 #endif 688 689 static gchar *loongarch_gdb_arch_name(CPUState *cs) 690 { 691 return g_strdup("loongarch64"); 692 } 693 694 static void loongarch_cpu_class_init(ObjectClass *c, void *data) 695 { 696 LoongArchCPUClass *lacc = LOONGARCH_CPU_CLASS(c); 697 CPUClass *cc = CPU_CLASS(c); 698 DeviceClass *dc = DEVICE_CLASS(c); 699 700 device_class_set_parent_realize(dc, loongarch_cpu_realizefn, 701 &lacc->parent_realize); 702 device_class_set_parent_reset(dc, loongarch_cpu_reset, &lacc->parent_reset); 703 704 cc->class_by_name = loongarch_cpu_class_by_name; 705 cc->has_work = loongarch_cpu_has_work; 706 cc->dump_state = loongarch_cpu_dump_state; 707 cc->set_pc = loongarch_cpu_set_pc; 708 cc->get_pc = loongarch_cpu_get_pc; 709 #ifndef CONFIG_USER_ONLY 710 dc->vmsd = &vmstate_loongarch_cpu; 711 cc->sysemu_ops = &loongarch_sysemu_ops; 712 #endif 713 cc->disas_set_info = loongarch_cpu_disas_set_info; 714 cc->gdb_read_register = loongarch_cpu_gdb_read_register; 715 cc->gdb_write_register = loongarch_cpu_gdb_write_register; 716 cc->disas_set_info = loongarch_cpu_disas_set_info; 717 cc->gdb_num_core_regs = 35; 718 cc->gdb_core_xml_file = "loongarch-base64.xml"; 719 cc->gdb_stop_before_watchpoint = true; 720 cc->gdb_arch_name = loongarch_gdb_arch_name; 721 722 #ifdef CONFIG_TCG 723 cc->tcg_ops = &loongarch_tcg_ops; 724 #endif 725 } 726 727 #define DEFINE_LOONGARCH_CPU_TYPE(model, initfn) \ 728 { \ 729 .parent = TYPE_LOONGARCH_CPU, \ 730 .instance_init = initfn, \ 731 .name = LOONGARCH_CPU_TYPE_NAME(model), \ 732 } 733 734 static const TypeInfo loongarch_cpu_type_infos[] = { 735 { 736 .name = TYPE_LOONGARCH_CPU, 737 .parent = TYPE_CPU, 738 .instance_size = sizeof(LoongArchCPU), 739 .instance_init = loongarch_cpu_init, 740 741 .abstract = true, 742 .class_size = sizeof(LoongArchCPUClass), 743 .class_init = loongarch_cpu_class_init, 744 }, 745 DEFINE_LOONGARCH_CPU_TYPE("la464", loongarch_la464_initfn), 746 }; 747 748 DEFINE_TYPES(loongarch_cpu_type_infos) 749 750 static void loongarch_cpu_add_definition(gpointer data, gpointer user_data) 751 { 752 ObjectClass *oc = data; 753 CpuDefinitionInfoList **cpu_list = user_data; 754 CpuDefinitionInfo *info = g_new0(CpuDefinitionInfo, 1); 755 const char *typename = object_class_get_name(oc); 756 757 info->name = g_strndup(typename, 758 strlen(typename) - strlen("-" TYPE_LOONGARCH_CPU)); 759 info->q_typename = g_strdup(typename); 760 761 QAPI_LIST_PREPEND(*cpu_list, info); 762 } 763 764 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 765 { 766 CpuDefinitionInfoList *cpu_list = NULL; 767 GSList *list; 768 769 list = object_class_get_list(TYPE_LOONGARCH_CPU, false); 770 g_slist_foreach(list, loongarch_cpu_add_definition, &cpu_list); 771 g_slist_free(list); 772 773 return cpu_list; 774 } 775