1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU LoongArch CPU 4 * 5 * Copyright (c) 2021 Loongson Technology Corporation Limited 6 */ 7 8 #include "qemu/osdep.h" 9 #include "qemu/log.h" 10 #include "qemu/qemu-print.h" 11 #include "qapi/error.h" 12 #include "qemu/module.h" 13 #include "sysemu/qtest.h" 14 #include "exec/cpu_ldst.h" 15 #include "exec/exec-all.h" 16 #include "cpu.h" 17 #include "internals.h" 18 #include "fpu/softfloat-helpers.h" 19 #include "cpu-csr.h" 20 #ifndef CONFIG_USER_ONLY 21 #include "sysemu/reset.h" 22 #endif 23 #include "tcg/tcg.h" 24 #include "vec.h" 25 26 const char * const regnames[32] = { 27 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 28 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 29 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 30 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 31 }; 32 33 const char * const fregnames[32] = { 34 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 35 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 36 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 37 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 38 }; 39 40 static const char * const excp_names[] = { 41 [EXCCODE_INT] = "Interrupt", 42 [EXCCODE_PIL] = "Page invalid exception for load", 43 [EXCCODE_PIS] = "Page invalid exception for store", 44 [EXCCODE_PIF] = "Page invalid exception for fetch", 45 [EXCCODE_PME] = "Page modified exception", 46 [EXCCODE_PNR] = "Page Not Readable exception", 47 [EXCCODE_PNX] = "Page Not Executable exception", 48 [EXCCODE_PPI] = "Page Privilege error", 49 [EXCCODE_ADEF] = "Address error for instruction fetch", 50 [EXCCODE_ADEM] = "Address error for Memory access", 51 [EXCCODE_SYS] = "Syscall", 52 [EXCCODE_BRK] = "Break", 53 [EXCCODE_INE] = "Instruction Non-Existent", 54 [EXCCODE_IPE] = "Instruction privilege error", 55 [EXCCODE_FPD] = "Floating Point Disabled", 56 [EXCCODE_FPE] = "Floating Point Exception", 57 [EXCCODE_DBP] = "Debug breakpoint", 58 [EXCCODE_BCE] = "Bound Check Exception", 59 [EXCCODE_SXD] = "128 bit vector instructions Disable exception", 60 [EXCCODE_ASXD] = "256 bit vector instructions Disable exception", 61 }; 62 63 const char *loongarch_exception_name(int32_t exception) 64 { 65 assert(excp_names[exception]); 66 return excp_names[exception]; 67 } 68 69 void G_NORETURN do_raise_exception(CPULoongArchState *env, 70 uint32_t exception, 71 uintptr_t pc) 72 { 73 CPUState *cs = env_cpu(env); 74 75 qemu_log_mask(CPU_LOG_INT, "%s: %d (%s)\n", 76 __func__, 77 exception, 78 loongarch_exception_name(exception)); 79 cs->exception_index = exception; 80 81 cpu_loop_exit_restore(cs, pc); 82 } 83 84 static void loongarch_cpu_set_pc(CPUState *cs, vaddr value) 85 { 86 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 87 CPULoongArchState *env = &cpu->env; 88 89 set_pc(env, value); 90 } 91 92 static vaddr loongarch_cpu_get_pc(CPUState *cs) 93 { 94 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 95 CPULoongArchState *env = &cpu->env; 96 97 return env->pc; 98 } 99 100 #ifndef CONFIG_USER_ONLY 101 #include "hw/loongarch/virt.h" 102 103 void loongarch_cpu_set_irq(void *opaque, int irq, int level) 104 { 105 LoongArchCPU *cpu = opaque; 106 CPULoongArchState *env = &cpu->env; 107 CPUState *cs = CPU(cpu); 108 109 if (irq < 0 || irq >= N_IRQS) { 110 return; 111 } 112 113 env->CSR_ESTAT = deposit64(env->CSR_ESTAT, irq, 1, level != 0); 114 115 if (FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS)) { 116 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 117 } else { 118 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 119 } 120 } 121 122 static inline bool cpu_loongarch_hw_interrupts_enabled(CPULoongArchState *env) 123 { 124 bool ret = 0; 125 126 ret = (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE) && 127 !(FIELD_EX64(env->CSR_DBG, CSR_DBG, DST))); 128 129 return ret; 130 } 131 132 /* Check if there is pending and not masked out interrupt */ 133 static inline bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env) 134 { 135 uint32_t pending; 136 uint32_t status; 137 138 pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS); 139 status = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE); 140 141 return (pending & status) != 0; 142 } 143 144 static void loongarch_cpu_do_interrupt(CPUState *cs) 145 { 146 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 147 CPULoongArchState *env = &cpu->env; 148 bool update_badinstr = 1; 149 int cause = -1; 150 const char *name; 151 bool tlbfill = FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR); 152 uint32_t vec_size = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, VS); 153 154 if (cs->exception_index != EXCCODE_INT) { 155 if (cs->exception_index < 0 || 156 cs->exception_index >= ARRAY_SIZE(excp_names)) { 157 name = "unknown"; 158 } else { 159 name = excp_names[cs->exception_index]; 160 } 161 162 qemu_log_mask(CPU_LOG_INT, 163 "%s enter: pc " TARGET_FMT_lx " ERA " TARGET_FMT_lx 164 " TLBRERA " TARGET_FMT_lx " %s exception\n", __func__, 165 env->pc, env->CSR_ERA, env->CSR_TLBRERA, name); 166 } 167 168 switch (cs->exception_index) { 169 case EXCCODE_DBP: 170 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DCL, 1); 171 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, ECODE, 0xC); 172 goto set_DERA; 173 set_DERA: 174 env->CSR_DERA = env->pc; 175 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DST, 1); 176 set_pc(env, env->CSR_EENTRY + 0x480); 177 break; 178 case EXCCODE_INT: 179 if (FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) { 180 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DEI, 1); 181 goto set_DERA; 182 } 183 QEMU_FALLTHROUGH; 184 case EXCCODE_PIF: 185 case EXCCODE_ADEF: 186 cause = cs->exception_index; 187 update_badinstr = 0; 188 break; 189 case EXCCODE_SYS: 190 case EXCCODE_BRK: 191 case EXCCODE_INE: 192 case EXCCODE_IPE: 193 case EXCCODE_FPD: 194 case EXCCODE_FPE: 195 case EXCCODE_SXD: 196 case EXCCODE_ASXD: 197 env->CSR_BADV = env->pc; 198 QEMU_FALLTHROUGH; 199 case EXCCODE_BCE: 200 case EXCCODE_ADEM: 201 case EXCCODE_PIL: 202 case EXCCODE_PIS: 203 case EXCCODE_PME: 204 case EXCCODE_PNR: 205 case EXCCODE_PNX: 206 case EXCCODE_PPI: 207 cause = cs->exception_index; 208 break; 209 default: 210 qemu_log("Error: exception(%d) has not been supported\n", 211 cs->exception_index); 212 abort(); 213 } 214 215 if (update_badinstr) { 216 env->CSR_BADI = cpu_ldl_code(env, env->pc); 217 } 218 219 /* Save PLV and IE */ 220 if (tlbfill) { 221 env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PPLV, 222 FIELD_EX64(env->CSR_CRMD, 223 CSR_CRMD, PLV)); 224 env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PIE, 225 FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE)); 226 /* set the DA mode */ 227 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1); 228 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0); 229 env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, 230 PC, (env->pc >> 2)); 231 } else { 232 env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE, 233 EXCODE_MCODE(cause)); 234 env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ESUBCODE, 235 EXCODE_SUBCODE(cause)); 236 env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PPLV, 237 FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV)); 238 env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PIE, 239 FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE)); 240 env->CSR_ERA = env->pc; 241 } 242 243 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0); 244 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0); 245 246 if (vec_size) { 247 vec_size = (1 << vec_size) * 4; 248 } 249 250 if (cs->exception_index == EXCCODE_INT) { 251 /* Interrupt */ 252 uint32_t vector = 0; 253 uint32_t pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS); 254 pending &= FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE); 255 256 /* Find the highest-priority interrupt. */ 257 vector = 31 - clz32(pending); 258 set_pc(env, env->CSR_EENTRY + \ 259 (EXCCODE_EXTERNAL_INT + vector) * vec_size); 260 qemu_log_mask(CPU_LOG_INT, 261 "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx 262 " cause %d\n" " A " TARGET_FMT_lx " D " 263 TARGET_FMT_lx " vector = %d ExC " TARGET_FMT_lx "ExS" 264 TARGET_FMT_lx "\n", 265 __func__, env->pc, env->CSR_ERA, 266 cause, env->CSR_BADV, env->CSR_DERA, vector, 267 env->CSR_ECFG, env->CSR_ESTAT); 268 } else { 269 if (tlbfill) { 270 set_pc(env, env->CSR_TLBRENTRY); 271 } else { 272 set_pc(env, env->CSR_EENTRY + EXCODE_MCODE(cause) * vec_size); 273 } 274 qemu_log_mask(CPU_LOG_INT, 275 "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx 276 " cause %d%s\n, ESTAT " TARGET_FMT_lx 277 " EXCFG " TARGET_FMT_lx " BADVA " TARGET_FMT_lx 278 "BADI " TARGET_FMT_lx " SYS_NUM " TARGET_FMT_lu 279 " cpu %d asid " TARGET_FMT_lx "\n", __func__, env->pc, 280 tlbfill ? env->CSR_TLBRERA : env->CSR_ERA, 281 cause, tlbfill ? "(refill)" : "", env->CSR_ESTAT, 282 env->CSR_ECFG, 283 tlbfill ? env->CSR_TLBRBADV : env->CSR_BADV, 284 env->CSR_BADI, env->gpr[11], cs->cpu_index, 285 env->CSR_ASID); 286 } 287 cs->exception_index = -1; 288 } 289 290 static void loongarch_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 291 vaddr addr, unsigned size, 292 MMUAccessType access_type, 293 int mmu_idx, MemTxAttrs attrs, 294 MemTxResult response, 295 uintptr_t retaddr) 296 { 297 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 298 CPULoongArchState *env = &cpu->env; 299 300 if (access_type == MMU_INST_FETCH) { 301 do_raise_exception(env, EXCCODE_ADEF, retaddr); 302 } else { 303 do_raise_exception(env, EXCCODE_ADEM, retaddr); 304 } 305 } 306 307 static bool loongarch_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 308 { 309 if (interrupt_request & CPU_INTERRUPT_HARD) { 310 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 311 CPULoongArchState *env = &cpu->env; 312 313 if (cpu_loongarch_hw_interrupts_enabled(env) && 314 cpu_loongarch_hw_interrupts_pending(env)) { 315 /* Raise it */ 316 cs->exception_index = EXCCODE_INT; 317 loongarch_cpu_do_interrupt(cs); 318 return true; 319 } 320 } 321 return false; 322 } 323 #endif 324 325 #ifdef CONFIG_TCG 326 static void loongarch_cpu_synchronize_from_tb(CPUState *cs, 327 const TranslationBlock *tb) 328 { 329 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 330 CPULoongArchState *env = &cpu->env; 331 332 tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); 333 set_pc(env, tb->pc); 334 } 335 336 static void loongarch_restore_state_to_opc(CPUState *cs, 337 const TranslationBlock *tb, 338 const uint64_t *data) 339 { 340 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 341 CPULoongArchState *env = &cpu->env; 342 343 set_pc(env, data[0]); 344 } 345 #endif /* CONFIG_TCG */ 346 347 static bool loongarch_cpu_has_work(CPUState *cs) 348 { 349 #ifdef CONFIG_USER_ONLY 350 return true; 351 #else 352 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 353 CPULoongArchState *env = &cpu->env; 354 bool has_work = false; 355 356 if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && 357 cpu_loongarch_hw_interrupts_pending(env)) { 358 has_work = true; 359 } 360 361 return has_work; 362 #endif 363 } 364 365 static void loongarch_la464_initfn(Object *obj) 366 { 367 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 368 CPULoongArchState *env = &cpu->env; 369 int i; 370 371 for (i = 0; i < 21; i++) { 372 env->cpucfg[i] = 0x0; 373 } 374 375 cpu->dtb_compatible = "loongarch,Loongson-3A5000"; 376 env->cpucfg[0] = 0x14c010; /* PRID */ 377 378 uint32_t data = 0; 379 data = FIELD_DP32(data, CPUCFG1, ARCH, 2); 380 data = FIELD_DP32(data, CPUCFG1, PGMMU, 1); 381 data = FIELD_DP32(data, CPUCFG1, IOCSR, 1); 382 data = FIELD_DP32(data, CPUCFG1, PALEN, 0x2f); 383 data = FIELD_DP32(data, CPUCFG1, VALEN, 0x2f); 384 data = FIELD_DP32(data, CPUCFG1, UAL, 1); 385 data = FIELD_DP32(data, CPUCFG1, RI, 1); 386 data = FIELD_DP32(data, CPUCFG1, EP, 1); 387 data = FIELD_DP32(data, CPUCFG1, RPLV, 1); 388 data = FIELD_DP32(data, CPUCFG1, HP, 1); 389 data = FIELD_DP32(data, CPUCFG1, IOCSR_BRD, 1); 390 env->cpucfg[1] = data; 391 392 data = 0; 393 data = FIELD_DP32(data, CPUCFG2, FP, 1); 394 data = FIELD_DP32(data, CPUCFG2, FP_SP, 1); 395 data = FIELD_DP32(data, CPUCFG2, FP_DP, 1); 396 data = FIELD_DP32(data, CPUCFG2, FP_VER, 1); 397 data = FIELD_DP32(data, CPUCFG2, LSX, 1), 398 data = FIELD_DP32(data, CPUCFG2, LASX, 1), 399 data = FIELD_DP32(data, CPUCFG2, LLFTP, 1); 400 data = FIELD_DP32(data, CPUCFG2, LLFTP_VER, 1); 401 data = FIELD_DP32(data, CPUCFG2, LSPW, 1); 402 data = FIELD_DP32(data, CPUCFG2, LAM, 1); 403 env->cpucfg[2] = data; 404 405 env->cpucfg[4] = 100 * 1000 * 1000; /* Crystal frequency */ 406 407 data = 0; 408 data = FIELD_DP32(data, CPUCFG5, CC_MUL, 1); 409 data = FIELD_DP32(data, CPUCFG5, CC_DIV, 1); 410 env->cpucfg[5] = data; 411 412 data = 0; 413 data = FIELD_DP32(data, CPUCFG16, L1_IUPRE, 1); 414 data = FIELD_DP32(data, CPUCFG16, L1_DPRE, 1); 415 data = FIELD_DP32(data, CPUCFG16, L2_IUPRE, 1); 416 data = FIELD_DP32(data, CPUCFG16, L2_IUUNIFY, 1); 417 data = FIELD_DP32(data, CPUCFG16, L2_IUPRIV, 1); 418 data = FIELD_DP32(data, CPUCFG16, L3_IUPRE, 1); 419 data = FIELD_DP32(data, CPUCFG16, L3_IUUNIFY, 1); 420 data = FIELD_DP32(data, CPUCFG16, L3_IUINCL, 1); 421 env->cpucfg[16] = data; 422 423 data = 0; 424 data = FIELD_DP32(data, CPUCFG17, L1IU_WAYS, 3); 425 data = FIELD_DP32(data, CPUCFG17, L1IU_SETS, 8); 426 data = FIELD_DP32(data, CPUCFG17, L1IU_SIZE, 6); 427 env->cpucfg[17] = data; 428 429 data = 0; 430 data = FIELD_DP32(data, CPUCFG18, L1D_WAYS, 3); 431 data = FIELD_DP32(data, CPUCFG18, L1D_SETS, 8); 432 data = FIELD_DP32(data, CPUCFG18, L1D_SIZE, 6); 433 env->cpucfg[18] = data; 434 435 data = 0; 436 data = FIELD_DP32(data, CPUCFG19, L2IU_WAYS, 15); 437 data = FIELD_DP32(data, CPUCFG19, L2IU_SETS, 8); 438 data = FIELD_DP32(data, CPUCFG19, L2IU_SIZE, 6); 439 env->cpucfg[19] = data; 440 441 data = 0; 442 data = FIELD_DP32(data, CPUCFG20, L3IU_WAYS, 15); 443 data = FIELD_DP32(data, CPUCFG20, L3IU_SETS, 14); 444 data = FIELD_DP32(data, CPUCFG20, L3IU_SIZE, 6); 445 env->cpucfg[20] = data; 446 447 env->CSR_ASID = FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa); 448 loongarch_cpu_post_init(obj); 449 } 450 451 static void loongarch_la132_initfn(Object *obj) 452 { 453 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 454 CPULoongArchState *env = &cpu->env; 455 456 int i; 457 458 for (i = 0; i < 21; i++) { 459 env->cpucfg[i] = 0x0; 460 } 461 462 cpu->dtb_compatible = "loongarch,Loongson-1C103"; 463 env->cpucfg[0] = 0x148042; /* PRID */ 464 465 uint32_t data = 0; 466 data = FIELD_DP32(data, CPUCFG1, ARCH, 1); /* LA32 */ 467 data = FIELD_DP32(data, CPUCFG1, PGMMU, 1); 468 data = FIELD_DP32(data, CPUCFG1, IOCSR, 1); 469 data = FIELD_DP32(data, CPUCFG1, PALEN, 0x1f); /* 32 bits */ 470 data = FIELD_DP32(data, CPUCFG1, VALEN, 0x1f); /* 32 bits */ 471 data = FIELD_DP32(data, CPUCFG1, UAL, 1); 472 data = FIELD_DP32(data, CPUCFG1, RI, 0); 473 data = FIELD_DP32(data, CPUCFG1, EP, 0); 474 data = FIELD_DP32(data, CPUCFG1, RPLV, 0); 475 data = FIELD_DP32(data, CPUCFG1, HP, 1); 476 data = FIELD_DP32(data, CPUCFG1, IOCSR_BRD, 1); 477 env->cpucfg[1] = data; 478 } 479 480 static void loongarch_max_initfn(Object *obj) 481 { 482 /* '-cpu max' for TCG: we use cpu la464. */ 483 loongarch_la464_initfn(obj); 484 } 485 486 static void loongarch_cpu_reset_hold(Object *obj) 487 { 488 CPUState *cs = CPU(obj); 489 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 490 LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(cpu); 491 CPULoongArchState *env = &cpu->env; 492 493 if (lacc->parent_phases.hold) { 494 lacc->parent_phases.hold(obj); 495 } 496 497 env->fcsr0_mask = FCSR0_M1 | FCSR0_M2 | FCSR0_M3; 498 env->fcsr0 = 0x0; 499 500 int n; 501 /* Set csr registers value after reset */ 502 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0); 503 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0); 504 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1); 505 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0); 506 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATF, 1); 507 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATM, 1); 508 509 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, FPE, 0); 510 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, SXE, 0); 511 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, ASXE, 0); 512 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, BTE, 0); 513 514 env->CSR_MISC = 0; 515 516 env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, VS, 0); 517 env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, LIE, 0); 518 519 env->CSR_ESTAT = env->CSR_ESTAT & (~MAKE_64BIT_MASK(0, 2)); 520 env->CSR_RVACFG = FIELD_DP64(env->CSR_RVACFG, CSR_RVACFG, RBITS, 0); 521 env->CSR_TCFG = FIELD_DP64(env->CSR_TCFG, CSR_TCFG, EN, 0); 522 env->CSR_LLBCTL = FIELD_DP64(env->CSR_LLBCTL, CSR_LLBCTL, KLO, 0); 523 env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 0); 524 env->CSR_MERRCTL = FIELD_DP64(env->CSR_MERRCTL, CSR_MERRCTL, ISMERR, 0); 525 526 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, TLB_TYPE, 2); 527 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, MTLB_ENTRY, 63); 528 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_WAYS, 7); 529 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_SETS, 8); 530 531 for (n = 0; n < 4; n++) { 532 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV0, 0); 533 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV1, 0); 534 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV2, 0); 535 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV3, 0); 536 } 537 538 #ifndef CONFIG_USER_ONLY 539 env->pc = 0x1c000000; 540 memset(env->tlb, 0, sizeof(env->tlb)); 541 #endif 542 543 restore_fp_status(env); 544 cs->exception_index = -1; 545 } 546 547 static void loongarch_cpu_disas_set_info(CPUState *s, disassemble_info *info) 548 { 549 info->print_insn = print_insn_loongarch; 550 } 551 552 static void loongarch_cpu_realizefn(DeviceState *dev, Error **errp) 553 { 554 CPUState *cs = CPU(dev); 555 LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(dev); 556 Error *local_err = NULL; 557 558 cpu_exec_realizefn(cs, &local_err); 559 if (local_err != NULL) { 560 error_propagate(errp, local_err); 561 return; 562 } 563 564 loongarch_cpu_register_gdb_regs_for_features(cs); 565 566 cpu_reset(cs); 567 qemu_init_vcpu(cs); 568 569 lacc->parent_realize(dev, errp); 570 } 571 572 #ifndef CONFIG_USER_ONLY 573 static void loongarch_qemu_write(void *opaque, hwaddr addr, 574 uint64_t val, unsigned size) 575 { 576 qemu_log_mask(LOG_UNIMP, "[%s]: Unimplemented reg 0x%" HWADDR_PRIx "\n", 577 __func__, addr); 578 } 579 580 static uint64_t loongarch_qemu_read(void *opaque, hwaddr addr, unsigned size) 581 { 582 switch (addr) { 583 case VERSION_REG: 584 return 0x11ULL; 585 case FEATURE_REG: 586 return 1ULL << IOCSRF_MSI | 1ULL << IOCSRF_EXTIOI | 587 1ULL << IOCSRF_CSRIPI; 588 case VENDOR_REG: 589 return 0x6e6f73676e6f6f4cULL; /* "Loongson" */ 590 case CPUNAME_REG: 591 return 0x303030354133ULL; /* "3A5000" */ 592 case MISC_FUNC_REG: 593 return 1ULL << IOCSRM_EXTIOI_EN; 594 } 595 return 0ULL; 596 } 597 598 static const MemoryRegionOps loongarch_qemu_ops = { 599 .read = loongarch_qemu_read, 600 .write = loongarch_qemu_write, 601 .endianness = DEVICE_LITTLE_ENDIAN, 602 .valid = { 603 .min_access_size = 4, 604 .max_access_size = 8, 605 }, 606 .impl = { 607 .min_access_size = 8, 608 .max_access_size = 8, 609 }, 610 }; 611 #endif 612 613 static bool loongarch_get_lsx(Object *obj, Error **errp) 614 { 615 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 616 bool ret; 617 618 if (FIELD_EX32(cpu->env.cpucfg[2], CPUCFG2, LSX)) { 619 ret = true; 620 } else { 621 ret = false; 622 } 623 return ret; 624 } 625 626 static void loongarch_set_lsx(Object *obj, bool value, Error **errp) 627 { 628 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 629 630 if (value) { 631 cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LSX, 1); 632 } else { 633 cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LSX, 0); 634 cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LASX, 0); 635 } 636 } 637 638 static bool loongarch_get_lasx(Object *obj, Error **errp) 639 { 640 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 641 bool ret; 642 643 if (FIELD_EX32(cpu->env.cpucfg[2], CPUCFG2, LASX)) { 644 ret = true; 645 } else { 646 ret = false; 647 } 648 return ret; 649 } 650 651 static void loongarch_set_lasx(Object *obj, bool value, Error **errp) 652 { 653 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 654 655 if (value) { 656 if (!FIELD_EX32(cpu->env.cpucfg[2], CPUCFG2, LSX)) { 657 cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LSX, 1); 658 } 659 cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LASX, 1); 660 } else { 661 cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LASX, 0); 662 } 663 } 664 665 void loongarch_cpu_post_init(Object *obj) 666 { 667 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 668 669 if (FIELD_EX32(cpu->env.cpucfg[2], CPUCFG2, LSX)) { 670 object_property_add_bool(obj, "lsx", loongarch_get_lsx, 671 loongarch_set_lsx); 672 } 673 if (FIELD_EX32(cpu->env.cpucfg[2], CPUCFG2, LASX)) { 674 object_property_add_bool(obj, "lasx", loongarch_get_lasx, 675 loongarch_set_lasx); 676 } 677 } 678 679 static void loongarch_cpu_init(Object *obj) 680 { 681 #ifndef CONFIG_USER_ONLY 682 LoongArchCPU *cpu = LOONGARCH_CPU(obj); 683 CPULoongArchState *env = &cpu->env; 684 685 qdev_init_gpio_in(DEVICE(cpu), loongarch_cpu_set_irq, N_IRQS); 686 timer_init_ns(&cpu->timer, QEMU_CLOCK_VIRTUAL, 687 &loongarch_constant_timer_cb, cpu); 688 memory_region_init_io(&env->system_iocsr, OBJECT(cpu), NULL, 689 env, "iocsr", UINT64_MAX); 690 address_space_init(&env->address_space_iocsr, &env->system_iocsr, "IOCSR"); 691 memory_region_init_io(&env->iocsr_mem, OBJECT(cpu), &loongarch_qemu_ops, 692 NULL, "iocsr_misc", 0x428); 693 memory_region_add_subregion(&env->system_iocsr, 0, &env->iocsr_mem); 694 #endif 695 } 696 697 static ObjectClass *loongarch_cpu_class_by_name(const char *cpu_model) 698 { 699 ObjectClass *oc; 700 701 oc = object_class_by_name(cpu_model); 702 if (!oc) { 703 g_autofree char *typename 704 = g_strdup_printf(LOONGARCH_CPU_TYPE_NAME("%s"), cpu_model); 705 oc = object_class_by_name(typename); 706 } 707 708 return oc; 709 } 710 711 void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags) 712 { 713 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 714 CPULoongArchState *env = &cpu->env; 715 int i; 716 717 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 718 qemu_fprintf(f, " FCSR0 0x%08x fp_status 0x%02x\n", env->fcsr0, 719 get_float_exception_flags(&env->fp_status)); 720 721 /* gpr */ 722 for (i = 0; i < 32; i++) { 723 if ((i & 3) == 0) { 724 qemu_fprintf(f, " GPR%02d:", i); 725 } 726 qemu_fprintf(f, " %s %016" PRIx64, regnames[i], env->gpr[i]); 727 if ((i & 3) == 3) { 728 qemu_fprintf(f, "\n"); 729 } 730 } 731 732 qemu_fprintf(f, "CRMD=%016" PRIx64 "\n", env->CSR_CRMD); 733 qemu_fprintf(f, "PRMD=%016" PRIx64 "\n", env->CSR_PRMD); 734 qemu_fprintf(f, "EUEN=%016" PRIx64 "\n", env->CSR_EUEN); 735 qemu_fprintf(f, "ESTAT=%016" PRIx64 "\n", env->CSR_ESTAT); 736 qemu_fprintf(f, "ERA=%016" PRIx64 "\n", env->CSR_ERA); 737 qemu_fprintf(f, "BADV=%016" PRIx64 "\n", env->CSR_BADV); 738 qemu_fprintf(f, "BADI=%016" PRIx64 "\n", env->CSR_BADI); 739 qemu_fprintf(f, "EENTRY=%016" PRIx64 "\n", env->CSR_EENTRY); 740 qemu_fprintf(f, "PRCFG1=%016" PRIx64 ", PRCFG2=%016" PRIx64 "," 741 " PRCFG3=%016" PRIx64 "\n", 742 env->CSR_PRCFG1, env->CSR_PRCFG3, env->CSR_PRCFG3); 743 qemu_fprintf(f, "TLBRENTRY=%016" PRIx64 "\n", env->CSR_TLBRENTRY); 744 qemu_fprintf(f, "TLBRBADV=%016" PRIx64 "\n", env->CSR_TLBRBADV); 745 qemu_fprintf(f, "TLBRERA=%016" PRIx64 "\n", env->CSR_TLBRERA); 746 qemu_fprintf(f, "TCFG=%016" PRIx64 "\n", env->CSR_TCFG); 747 qemu_fprintf(f, "TVAL=%016" PRIx64 "\n", env->CSR_TVAL); 748 749 /* fpr */ 750 if (flags & CPU_DUMP_FPU) { 751 for (i = 0; i < 32; i++) { 752 qemu_fprintf(f, " %s %016" PRIx64, fregnames[i], env->fpr[i].vreg.D(0)); 753 if ((i & 3) == 3) { 754 qemu_fprintf(f, "\n"); 755 } 756 } 757 } 758 } 759 760 #ifdef CONFIG_TCG 761 #include "hw/core/tcg-cpu-ops.h" 762 763 static struct TCGCPUOps loongarch_tcg_ops = { 764 .initialize = loongarch_translate_init, 765 .synchronize_from_tb = loongarch_cpu_synchronize_from_tb, 766 .restore_state_to_opc = loongarch_restore_state_to_opc, 767 768 #ifndef CONFIG_USER_ONLY 769 .tlb_fill = loongarch_cpu_tlb_fill, 770 .cpu_exec_interrupt = loongarch_cpu_exec_interrupt, 771 .do_interrupt = loongarch_cpu_do_interrupt, 772 .do_transaction_failed = loongarch_cpu_do_transaction_failed, 773 #endif 774 }; 775 #endif /* CONFIG_TCG */ 776 777 #ifndef CONFIG_USER_ONLY 778 #include "hw/core/sysemu-cpu-ops.h" 779 780 static const struct SysemuCPUOps loongarch_sysemu_ops = { 781 .get_phys_page_debug = loongarch_cpu_get_phys_page_debug, 782 }; 783 784 static int64_t loongarch_cpu_get_arch_id(CPUState *cs) 785 { 786 LoongArchCPU *cpu = LOONGARCH_CPU(cs); 787 788 return cpu->phy_id; 789 } 790 #endif 791 792 static void loongarch_cpu_class_init(ObjectClass *c, void *data) 793 { 794 LoongArchCPUClass *lacc = LOONGARCH_CPU_CLASS(c); 795 CPUClass *cc = CPU_CLASS(c); 796 DeviceClass *dc = DEVICE_CLASS(c); 797 ResettableClass *rc = RESETTABLE_CLASS(c); 798 799 device_class_set_parent_realize(dc, loongarch_cpu_realizefn, 800 &lacc->parent_realize); 801 resettable_class_set_parent_phases(rc, NULL, loongarch_cpu_reset_hold, NULL, 802 &lacc->parent_phases); 803 804 cc->class_by_name = loongarch_cpu_class_by_name; 805 cc->has_work = loongarch_cpu_has_work; 806 cc->dump_state = loongarch_cpu_dump_state; 807 cc->set_pc = loongarch_cpu_set_pc; 808 cc->get_pc = loongarch_cpu_get_pc; 809 #ifndef CONFIG_USER_ONLY 810 cc->get_arch_id = loongarch_cpu_get_arch_id; 811 dc->vmsd = &vmstate_loongarch_cpu; 812 cc->sysemu_ops = &loongarch_sysemu_ops; 813 #endif 814 cc->disas_set_info = loongarch_cpu_disas_set_info; 815 cc->gdb_read_register = loongarch_cpu_gdb_read_register; 816 cc->gdb_write_register = loongarch_cpu_gdb_write_register; 817 cc->gdb_stop_before_watchpoint = true; 818 819 #ifdef CONFIG_TCG 820 cc->tcg_ops = &loongarch_tcg_ops; 821 #endif 822 } 823 824 static const gchar *loongarch32_gdb_arch_name(CPUState *cs) 825 { 826 return "loongarch32"; 827 } 828 829 static void loongarch32_cpu_class_init(ObjectClass *c, void *data) 830 { 831 CPUClass *cc = CPU_CLASS(c); 832 833 cc->gdb_num_core_regs = 35; 834 cc->gdb_core_xml_file = "loongarch-base32.xml"; 835 cc->gdb_arch_name = loongarch32_gdb_arch_name; 836 } 837 838 static const gchar *loongarch64_gdb_arch_name(CPUState *cs) 839 { 840 return "loongarch64"; 841 } 842 843 static void loongarch64_cpu_class_init(ObjectClass *c, void *data) 844 { 845 CPUClass *cc = CPU_CLASS(c); 846 847 cc->gdb_num_core_regs = 35; 848 cc->gdb_core_xml_file = "loongarch-base64.xml"; 849 cc->gdb_arch_name = loongarch64_gdb_arch_name; 850 } 851 852 #define DEFINE_LOONGARCH_CPU_TYPE(size, model, initfn) \ 853 { \ 854 .parent = TYPE_LOONGARCH##size##_CPU, \ 855 .instance_init = initfn, \ 856 .name = LOONGARCH_CPU_TYPE_NAME(model), \ 857 } 858 859 static const TypeInfo loongarch_cpu_type_infos[] = { 860 { 861 .name = TYPE_LOONGARCH_CPU, 862 .parent = TYPE_CPU, 863 .instance_size = sizeof(LoongArchCPU), 864 .instance_align = __alignof(LoongArchCPU), 865 .instance_init = loongarch_cpu_init, 866 867 .abstract = true, 868 .class_size = sizeof(LoongArchCPUClass), 869 .class_init = loongarch_cpu_class_init, 870 }, 871 { 872 .name = TYPE_LOONGARCH32_CPU, 873 .parent = TYPE_LOONGARCH_CPU, 874 875 .abstract = true, 876 .class_init = loongarch32_cpu_class_init, 877 }, 878 { 879 .name = TYPE_LOONGARCH64_CPU, 880 .parent = TYPE_LOONGARCH_CPU, 881 882 .abstract = true, 883 .class_init = loongarch64_cpu_class_init, 884 }, 885 DEFINE_LOONGARCH_CPU_TYPE(64, "la464", loongarch_la464_initfn), 886 DEFINE_LOONGARCH_CPU_TYPE(32, "la132", loongarch_la132_initfn), 887 DEFINE_LOONGARCH_CPU_TYPE(64, "max", loongarch_max_initfn), 888 }; 889 890 DEFINE_TYPES(loongarch_cpu_type_infos) 891