1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU LoongArch CPU 4 * 5 * Copyright (c) 2021 Loongson Technology Corporation Limited 6 */ 7 8 #ifndef LOONGARCH_CPU_H 9 #define LOONGARCH_CPU_H 10 11 #include "qemu/int128.h" 12 #include "exec/cpu-defs.h" 13 #include "fpu/softfloat-types.h" 14 #include "hw/registerfields.h" 15 #include "qemu/timer.h" 16 #ifndef CONFIG_USER_ONLY 17 #include "exec/memory.h" 18 #endif 19 #include "cpu-csr.h" 20 21 #define IOCSRF_TEMP 0 22 #define IOCSRF_NODECNT 1 23 #define IOCSRF_MSI 2 24 #define IOCSRF_EXTIOI 3 25 #define IOCSRF_CSRIPI 4 26 #define IOCSRF_FREQCSR 5 27 #define IOCSRF_FREQSCALE 6 28 #define IOCSRF_DVFSV1 7 29 #define IOCSRF_GMOD 9 30 #define IOCSRF_VM 11 31 32 #define VERSION_REG 0x0 33 #define FEATURE_REG 0x8 34 #define VENDOR_REG 0x10 35 #define CPUNAME_REG 0x20 36 #define MISC_FUNC_REG 0x420 37 #define IOCSRM_EXTIOI_EN 48 38 39 #define IOCSR_MEM_SIZE 0x428 40 41 #define TCG_GUEST_DEFAULT_MO (0) 42 43 #define FCSR0_M1 0x1f /* FCSR1 mask, Enables */ 44 #define FCSR0_M2 0x1f1f0000 /* FCSR2 mask, Cause and Flags */ 45 #define FCSR0_M3 0x300 /* FCSR3 mask, Round Mode */ 46 #define FCSR0_RM 8 /* Round Mode bit num on fcsr0 */ 47 48 FIELD(FCSR0, ENABLES, 0, 5) 49 FIELD(FCSR0, RM, 8, 2) 50 FIELD(FCSR0, FLAGS, 16, 5) 51 FIELD(FCSR0, CAUSE, 24, 5) 52 53 #define GET_FP_CAUSE(REG) FIELD_EX32(REG, FCSR0, CAUSE) 54 #define SET_FP_CAUSE(REG, V) \ 55 do { \ 56 (REG) = FIELD_DP32(REG, FCSR0, CAUSE, V); \ 57 } while (0) 58 59 #define GET_FP_ENABLES(REG) FIELD_EX32(REG, FCSR0, ENABLES) 60 #define SET_FP_ENABLES(REG, V) \ 61 do { \ 62 (REG) = FIELD_DP32(REG, FCSR0, ENABLES, V); \ 63 } while (0) 64 65 #define GET_FP_FLAGS(REG) FIELD_EX32(REG, FCSR0, FLAGS) 66 #define SET_FP_FLAGS(REG, V) \ 67 do { \ 68 (REG) = FIELD_DP32(REG, FCSR0, FLAGS, V); \ 69 } while (0) 70 71 #define UPDATE_FP_FLAGS(REG, V) \ 72 do { \ 73 (REG) |= FIELD_DP32(0, FCSR0, FLAGS, V); \ 74 } while (0) 75 76 #define FP_INEXACT 1 77 #define FP_UNDERFLOW 2 78 #define FP_OVERFLOW 4 79 #define FP_DIV0 8 80 #define FP_INVALID 16 81 82 #define EXCODE(code, subcode) ( ((subcode) << 6) | (code) ) 83 #define EXCODE_MCODE(code) ( (code) & 0x3f ) 84 #define EXCODE_SUBCODE(code) ( (code) >> 6 ) 85 86 #define EXCCODE_EXTERNAL_INT 64 /* plus external interrupt number */ 87 #define EXCCODE_INT EXCODE(0, 0) 88 #define EXCCODE_PIL EXCODE(1, 0) 89 #define EXCCODE_PIS EXCODE(2, 0) 90 #define EXCCODE_PIF EXCODE(3, 0) 91 #define EXCCODE_PME EXCODE(4, 0) 92 #define EXCCODE_PNR EXCODE(5, 0) 93 #define EXCCODE_PNX EXCODE(6, 0) 94 #define EXCCODE_PPI EXCODE(7, 0) 95 #define EXCCODE_ADEF EXCODE(8, 0) /* Different exception subcode */ 96 #define EXCCODE_ADEM EXCODE(8, 1) 97 #define EXCCODE_ALE EXCODE(9, 0) 98 #define EXCCODE_BCE EXCODE(10, 0) 99 #define EXCCODE_SYS EXCODE(11, 0) 100 #define EXCCODE_BRK EXCODE(12, 0) 101 #define EXCCODE_INE EXCODE(13, 0) 102 #define EXCCODE_IPE EXCODE(14, 0) 103 #define EXCCODE_FPD EXCODE(15, 0) 104 #define EXCCODE_SXD EXCODE(16, 0) 105 #define EXCCODE_ASXD EXCODE(17, 0) 106 #define EXCCODE_FPE EXCODE(18, 0) /* Different exception subcode */ 107 #define EXCCODE_VFPE EXCODE(18, 1) 108 #define EXCCODE_WPEF EXCODE(19, 0) /* Different exception subcode */ 109 #define EXCCODE_WPEM EXCODE(19, 1) 110 #define EXCCODE_BTD EXCODE(20, 0) 111 #define EXCCODE_BTE EXCODE(21, 0) 112 #define EXCCODE_DBP EXCODE(26, 0) /* Reserved subcode used for debug */ 113 114 /* cpucfg[0] bits */ 115 FIELD(CPUCFG0, PRID, 0, 32) 116 117 /* cpucfg[1] bits */ 118 FIELD(CPUCFG1, ARCH, 0, 2) 119 FIELD(CPUCFG1, PGMMU, 2, 1) 120 FIELD(CPUCFG1, IOCSR, 3, 1) 121 FIELD(CPUCFG1, PALEN, 4, 8) 122 FIELD(CPUCFG1, VALEN, 12, 8) 123 FIELD(CPUCFG1, UAL, 20, 1) 124 FIELD(CPUCFG1, RI, 21, 1) 125 FIELD(CPUCFG1, EP, 22, 1) 126 FIELD(CPUCFG1, RPLV, 23, 1) 127 FIELD(CPUCFG1, HP, 24, 1) 128 FIELD(CPUCFG1, IOCSR_BRD, 25, 1) 129 FIELD(CPUCFG1, MSG_INT, 26, 1) 130 131 /* cpucfg[2] bits */ 132 FIELD(CPUCFG2, FP, 0, 1) 133 FIELD(CPUCFG2, FP_SP, 1, 1) 134 FIELD(CPUCFG2, FP_DP, 2, 1) 135 FIELD(CPUCFG2, FP_VER, 3, 3) 136 FIELD(CPUCFG2, LSX, 6, 1) 137 FIELD(CPUCFG2, LASX, 7, 1) 138 FIELD(CPUCFG2, COMPLEX, 8, 1) 139 FIELD(CPUCFG2, CRYPTO, 9, 1) 140 FIELD(CPUCFG2, LVZ, 10, 1) 141 FIELD(CPUCFG2, LVZ_VER, 11, 3) 142 FIELD(CPUCFG2, LLFTP, 14, 1) 143 FIELD(CPUCFG2, LLFTP_VER, 15, 3) 144 FIELD(CPUCFG2, LBT_X86, 18, 1) 145 FIELD(CPUCFG2, LBT_ARM, 19, 1) 146 FIELD(CPUCFG2, LBT_MIPS, 20, 1) 147 FIELD(CPUCFG2, LSPW, 21, 1) 148 FIELD(CPUCFG2, LAM, 22, 1) 149 150 /* cpucfg[3] bits */ 151 FIELD(CPUCFG3, CCDMA, 0, 1) 152 FIELD(CPUCFG3, SFB, 1, 1) 153 FIELD(CPUCFG3, UCACC, 2, 1) 154 FIELD(CPUCFG3, LLEXC, 3, 1) 155 FIELD(CPUCFG3, SCDLY, 4, 1) 156 FIELD(CPUCFG3, LLDBAR, 5, 1) 157 FIELD(CPUCFG3, ITLBHMC, 6, 1) 158 FIELD(CPUCFG3, ICHMC, 7, 1) 159 FIELD(CPUCFG3, SPW_LVL, 8, 3) 160 FIELD(CPUCFG3, SPW_HP_HF, 11, 1) 161 FIELD(CPUCFG3, RVA, 12, 1) 162 FIELD(CPUCFG3, RVAMAX, 13, 4) 163 164 /* cpucfg[4] bits */ 165 FIELD(CPUCFG4, CC_FREQ, 0, 32) 166 167 /* cpucfg[5] bits */ 168 FIELD(CPUCFG5, CC_MUL, 0, 16) 169 FIELD(CPUCFG5, CC_DIV, 16, 16) 170 171 /* cpucfg[6] bits */ 172 FIELD(CPUCFG6, PMP, 0, 1) 173 FIELD(CPUCFG6, PMVER, 1, 3) 174 FIELD(CPUCFG6, PMNUM, 4, 4) 175 FIELD(CPUCFG6, PMBITS, 8, 6) 176 FIELD(CPUCFG6, UPM, 14, 1) 177 178 /* cpucfg[16] bits */ 179 FIELD(CPUCFG16, L1_IUPRE, 0, 1) 180 FIELD(CPUCFG16, L1_IUUNIFY, 1, 1) 181 FIELD(CPUCFG16, L1_DPRE, 2, 1) 182 FIELD(CPUCFG16, L2_IUPRE, 3, 1) 183 FIELD(CPUCFG16, L2_IUUNIFY, 4, 1) 184 FIELD(CPUCFG16, L2_IUPRIV, 5, 1) 185 FIELD(CPUCFG16, L2_IUINCL, 6, 1) 186 FIELD(CPUCFG16, L2_DPRE, 7, 1) 187 FIELD(CPUCFG16, L2_DPRIV, 8, 1) 188 FIELD(CPUCFG16, L2_DINCL, 9, 1) 189 FIELD(CPUCFG16, L3_IUPRE, 10, 1) 190 FIELD(CPUCFG16, L3_IUUNIFY, 11, 1) 191 FIELD(CPUCFG16, L3_IUPRIV, 12, 1) 192 FIELD(CPUCFG16, L3_IUINCL, 13, 1) 193 FIELD(CPUCFG16, L3_DPRE, 14, 1) 194 FIELD(CPUCFG16, L3_DPRIV, 15, 1) 195 FIELD(CPUCFG16, L3_DINCL, 16, 1) 196 197 /* cpucfg[17] bits */ 198 FIELD(CPUCFG17, L1IU_WAYS, 0, 16) 199 FIELD(CPUCFG17, L1IU_SETS, 16, 8) 200 FIELD(CPUCFG17, L1IU_SIZE, 24, 7) 201 202 /* cpucfg[18] bits */ 203 FIELD(CPUCFG18, L1D_WAYS, 0, 16) 204 FIELD(CPUCFG18, L1D_SETS, 16, 8) 205 FIELD(CPUCFG18, L1D_SIZE, 24, 7) 206 207 /* cpucfg[19] bits */ 208 FIELD(CPUCFG19, L2IU_WAYS, 0, 16) 209 FIELD(CPUCFG19, L2IU_SETS, 16, 8) 210 FIELD(CPUCFG19, L2IU_SIZE, 24, 7) 211 212 /* cpucfg[20] bits */ 213 FIELD(CPUCFG20, L3IU_WAYS, 0, 16) 214 FIELD(CPUCFG20, L3IU_SETS, 16, 8) 215 FIELD(CPUCFG20, L3IU_SIZE, 24, 7) 216 217 /*CSR_CRMD */ 218 FIELD(CSR_CRMD, PLV, 0, 2) 219 FIELD(CSR_CRMD, IE, 2, 1) 220 FIELD(CSR_CRMD, DA, 3, 1) 221 FIELD(CSR_CRMD, PG, 4, 1) 222 FIELD(CSR_CRMD, DATF, 5, 2) 223 FIELD(CSR_CRMD, DATM, 7, 2) 224 FIELD(CSR_CRMD, WE, 9, 1) 225 226 extern const char * const regnames[32]; 227 extern const char * const fregnames[32]; 228 229 #define N_IRQS 13 230 #define IRQ_TIMER 11 231 #define IRQ_IPI 12 232 233 #define LOONGARCH_STLB 2048 /* 2048 STLB */ 234 #define LOONGARCH_MTLB 64 /* 64 MTLB */ 235 #define LOONGARCH_TLB_MAX (LOONGARCH_STLB + LOONGARCH_MTLB) 236 237 /* 238 * define the ASID PS E VPPN field of TLB 239 */ 240 FIELD(TLB_MISC, E, 0, 1) 241 FIELD(TLB_MISC, ASID, 1, 10) 242 FIELD(TLB_MISC, VPPN, 13, 35) 243 FIELD(TLB_MISC, PS, 48, 6) 244 245 #define LSX_LEN (128) 246 typedef union VReg { 247 int8_t B[LSX_LEN / 8]; 248 int16_t H[LSX_LEN / 16]; 249 int32_t W[LSX_LEN / 32]; 250 int64_t D[LSX_LEN / 64]; 251 uint8_t UB[LSX_LEN / 8]; 252 uint16_t UH[LSX_LEN / 16]; 253 uint32_t UW[LSX_LEN / 32]; 254 uint64_t UD[LSX_LEN / 64]; 255 Int128 Q[LSX_LEN / 128]; 256 }VReg; 257 258 typedef union fpr_t fpr_t; 259 union fpr_t { 260 VReg vreg; 261 }; 262 263 struct LoongArchTLB { 264 uint64_t tlb_misc; 265 /* Fields corresponding to CSR_TLBELO0/1 */ 266 uint64_t tlb_entry0; 267 uint64_t tlb_entry1; 268 }; 269 typedef struct LoongArchTLB LoongArchTLB; 270 271 typedef struct CPUArchState { 272 uint64_t gpr[32]; 273 uint64_t pc; 274 275 fpr_t fpr[32]; 276 float_status fp_status; 277 bool cf[8]; 278 279 uint32_t fcsr0; 280 uint32_t fcsr0_mask; 281 282 uint32_t cpucfg[21]; 283 284 uint64_t lladdr; /* LL virtual address compared against SC */ 285 uint64_t llval; 286 287 /* LoongArch CSRs */ 288 uint64_t CSR_CRMD; 289 uint64_t CSR_PRMD; 290 uint64_t CSR_EUEN; 291 uint64_t CSR_MISC; 292 uint64_t CSR_ECFG; 293 uint64_t CSR_ESTAT; 294 uint64_t CSR_ERA; 295 uint64_t CSR_BADV; 296 uint64_t CSR_BADI; 297 uint64_t CSR_EENTRY; 298 uint64_t CSR_TLBIDX; 299 uint64_t CSR_TLBEHI; 300 uint64_t CSR_TLBELO0; 301 uint64_t CSR_TLBELO1; 302 uint64_t CSR_ASID; 303 uint64_t CSR_PGDL; 304 uint64_t CSR_PGDH; 305 uint64_t CSR_PGD; 306 uint64_t CSR_PWCL; 307 uint64_t CSR_PWCH; 308 uint64_t CSR_STLBPS; 309 uint64_t CSR_RVACFG; 310 uint64_t CSR_PRCFG1; 311 uint64_t CSR_PRCFG2; 312 uint64_t CSR_PRCFG3; 313 uint64_t CSR_SAVE[16]; 314 uint64_t CSR_TID; 315 uint64_t CSR_TCFG; 316 uint64_t CSR_TVAL; 317 uint64_t CSR_CNTC; 318 uint64_t CSR_TICLR; 319 uint64_t CSR_LLBCTL; 320 uint64_t CSR_IMPCTL1; 321 uint64_t CSR_IMPCTL2; 322 uint64_t CSR_TLBRENTRY; 323 uint64_t CSR_TLBRBADV; 324 uint64_t CSR_TLBRERA; 325 uint64_t CSR_TLBRSAVE; 326 uint64_t CSR_TLBRELO0; 327 uint64_t CSR_TLBRELO1; 328 uint64_t CSR_TLBREHI; 329 uint64_t CSR_TLBRPRMD; 330 uint64_t CSR_MERRCTL; 331 uint64_t CSR_MERRINFO1; 332 uint64_t CSR_MERRINFO2; 333 uint64_t CSR_MERRENTRY; 334 uint64_t CSR_MERRERA; 335 uint64_t CSR_MERRSAVE; 336 uint64_t CSR_CTAG; 337 uint64_t CSR_DMW[4]; 338 uint64_t CSR_DBG; 339 uint64_t CSR_DERA; 340 uint64_t CSR_DSAVE; 341 342 #ifndef CONFIG_USER_ONLY 343 LoongArchTLB tlb[LOONGARCH_TLB_MAX]; 344 345 AddressSpace address_space_iocsr; 346 MemoryRegion system_iocsr; 347 MemoryRegion iocsr_mem; 348 bool load_elf; 349 uint64_t elf_address; 350 #endif 351 } CPULoongArchState; 352 353 /** 354 * LoongArchCPU: 355 * @env: #CPULoongArchState 356 * 357 * A LoongArch CPU. 358 */ 359 struct ArchCPU { 360 /*< private >*/ 361 CPUState parent_obj; 362 /*< public >*/ 363 364 CPUNegativeOffsetState neg; 365 CPULoongArchState env; 366 QEMUTimer timer; 367 368 /* 'compatible' string for this CPU for Linux device trees */ 369 const char *dtb_compatible; 370 }; 371 372 #define TYPE_LOONGARCH_CPU "loongarch-cpu" 373 374 OBJECT_DECLARE_CPU_TYPE(LoongArchCPU, LoongArchCPUClass, 375 LOONGARCH_CPU) 376 377 /** 378 * LoongArchCPUClass: 379 * @parent_realize: The parent class' realize handler. 380 * @parent_phases: The parent class' reset phase handlers. 381 * 382 * A LoongArch CPU model. 383 */ 384 struct LoongArchCPUClass { 385 /*< private >*/ 386 CPUClass parent_class; 387 /*< public >*/ 388 389 DeviceRealize parent_realize; 390 ResettablePhases parent_phases; 391 }; 392 393 /* 394 * LoongArch CPUs has 4 privilege levels. 395 * 0 for kernel mode, 3 for user mode. 396 * Define an extra index for DA(direct addressing) mode. 397 */ 398 #define MMU_PLV_KERNEL 0 399 #define MMU_PLV_USER 3 400 #define MMU_IDX_KERNEL MMU_PLV_KERNEL 401 #define MMU_IDX_USER MMU_PLV_USER 402 #define MMU_IDX_DA 4 403 404 static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch) 405 { 406 #ifdef CONFIG_USER_ONLY 407 return MMU_IDX_USER; 408 #else 409 if (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG)) { 410 return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV); 411 } 412 return MMU_IDX_DA; 413 #endif 414 } 415 416 /* 417 * LoongArch CPUs hardware flags. 418 */ 419 #define HW_FLAGS_PLV_MASK R_CSR_CRMD_PLV_MASK /* 0x03 */ 420 #define HW_FLAGS_CRMD_PG R_CSR_CRMD_PG_MASK /* 0x10 */ 421 #define HW_FLAGS_EUEN_FPE 0x04 422 423 static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, 424 target_ulong *pc, 425 target_ulong *cs_base, 426 uint32_t *flags) 427 { 428 *pc = env->pc; 429 *cs_base = 0; 430 *flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK); 431 *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FPE; 432 } 433 434 void loongarch_cpu_list(void); 435 436 #define cpu_list loongarch_cpu_list 437 438 #include "exec/cpu-all.h" 439 440 #define LOONGARCH_CPU_TYPE_SUFFIX "-" TYPE_LOONGARCH_CPU 441 #define LOONGARCH_CPU_TYPE_NAME(model) model LOONGARCH_CPU_TYPE_SUFFIX 442 #define CPU_RESOLVING_TYPE TYPE_LOONGARCH_CPU 443 444 #endif /* LOONGARCH_CPU_H */ 445