1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Copyright (c) 2021 Loongson Technology Corporation Limited
4 */
5
6#ifndef CONFIG_USER_ONLY
7#define CHECK_FPE do { \
8    if ((ctx->base.tb->flags & HW_FLAGS_EUEN_FPE) == 0) { \
9        generate_exception(ctx, EXCCODE_FPD); \
10        return true; \
11    } \
12} while (0)
13#else
14#define CHECK_FPE
15#endif
16
17static bool gen_fff(DisasContext *ctx, arg_fff *a,
18                    void (*func)(TCGv, TCGv_env, TCGv, TCGv))
19{
20    TCGv dest = get_fpr(ctx, a->fd);
21    TCGv src1 = get_fpr(ctx, a->fj);
22    TCGv src2 = get_fpr(ctx, a->fk);
23
24    CHECK_FPE;
25
26    func(dest, tcg_env, src1, src2);
27    set_fpr(a->fd, dest);
28
29    return true;
30}
31
32static bool gen_ff(DisasContext *ctx, arg_ff *a,
33                   void (*func)(TCGv, TCGv_env, TCGv))
34{
35    TCGv dest = get_fpr(ctx, a->fd);
36    TCGv src = get_fpr(ctx, a->fj);
37
38    CHECK_FPE;
39
40    func(dest, tcg_env, src);
41    set_fpr(a->fd, dest);
42
43    return true;
44}
45
46static bool gen_muladd(DisasContext *ctx, arg_ffff *a,
47                       void (*func)(TCGv, TCGv_env, TCGv, TCGv, TCGv, TCGv_i32),
48                       int flag)
49{
50    TCGv_i32 tflag = tcg_constant_i32(flag);
51    TCGv dest = get_fpr(ctx, a->fd);
52    TCGv src1 = get_fpr(ctx, a->fj);
53    TCGv src2 = get_fpr(ctx, a->fk);
54    TCGv src3 = get_fpr(ctx, a->fa);
55
56    CHECK_FPE;
57
58    func(dest, tcg_env, src1, src2, src3, tflag);
59    set_fpr(a->fd, dest);
60
61    return true;
62}
63
64static bool trans_fcopysign_s(DisasContext *ctx, arg_fcopysign_s *a)
65{
66    TCGv dest = get_fpr(ctx, a->fd);
67    TCGv src1 = get_fpr(ctx, a->fk);
68    TCGv src2 = get_fpr(ctx, a->fj);
69
70    if (!avail_FP_SP(ctx)) {
71        return false;
72    }
73
74    CHECK_FPE;
75
76    tcg_gen_deposit_i64(dest, src1, src2, 0, 31);
77    set_fpr(a->fd, dest);
78
79    return true;
80}
81
82static bool trans_fcopysign_d(DisasContext *ctx, arg_fcopysign_d *a)
83{
84    TCGv dest = get_fpr(ctx, a->fd);
85    TCGv src1 = get_fpr(ctx, a->fk);
86    TCGv src2 = get_fpr(ctx, a->fj);
87
88    if (!avail_FP_DP(ctx)) {
89        return false;
90    }
91
92    CHECK_FPE;
93
94    tcg_gen_deposit_i64(dest, src1, src2, 0, 63);
95    set_fpr(a->fd, dest);
96
97    return true;
98}
99
100static bool trans_fabs_s(DisasContext *ctx, arg_fabs_s *a)
101{
102    TCGv dest = get_fpr(ctx, a->fd);
103    TCGv src = get_fpr(ctx, a->fj);
104
105    if (!avail_FP_SP(ctx)) {
106        return false;
107    }
108
109    CHECK_FPE;
110
111    tcg_gen_andi_i64(dest, src, MAKE_64BIT_MASK(0, 31));
112    gen_nanbox_s(dest, dest);
113    set_fpr(a->fd, dest);
114
115    return true;
116}
117
118static bool trans_fabs_d(DisasContext *ctx, arg_fabs_d *a)
119{
120    TCGv dest = get_fpr(ctx, a->fd);
121    TCGv src = get_fpr(ctx, a->fj);
122
123    if (!avail_FP_DP(ctx)) {
124        return false;
125    }
126
127    CHECK_FPE;
128
129    tcg_gen_andi_i64(dest, src, MAKE_64BIT_MASK(0, 63));
130    set_fpr(a->fd, dest);
131
132    return true;
133}
134
135static bool trans_fneg_s(DisasContext *ctx, arg_fneg_s *a)
136{
137    TCGv dest = get_fpr(ctx, a->fd);
138    TCGv src = get_fpr(ctx, a->fj);
139
140    if (!avail_FP_SP(ctx)) {
141        return false;
142    }
143
144    CHECK_FPE;
145
146    tcg_gen_xori_i64(dest, src, 0x80000000);
147    gen_nanbox_s(dest, dest);
148    set_fpr(a->fd, dest);
149
150    return true;
151}
152
153static bool trans_fneg_d(DisasContext *ctx, arg_fneg_d *a)
154{
155    TCGv dest = get_fpr(ctx, a->fd);
156    TCGv src = get_fpr(ctx, a->fj);
157
158    if (!avail_FP_DP(ctx)) {
159        return false;
160    }
161
162    CHECK_FPE;
163
164    tcg_gen_xori_i64(dest, src, 0x8000000000000000LL);
165    set_fpr(a->fd, dest);
166
167    return true;
168}
169
170TRANS(fadd_s, FP_SP, gen_fff, gen_helper_fadd_s)
171TRANS(fadd_d, FP_DP, gen_fff, gen_helper_fadd_d)
172TRANS(fsub_s, FP_SP, gen_fff, gen_helper_fsub_s)
173TRANS(fsub_d, FP_DP, gen_fff, gen_helper_fsub_d)
174TRANS(fmul_s, FP_SP, gen_fff, gen_helper_fmul_s)
175TRANS(fmul_d, FP_DP, gen_fff, gen_helper_fmul_d)
176TRANS(fdiv_s, FP_SP, gen_fff, gen_helper_fdiv_s)
177TRANS(fdiv_d, FP_DP, gen_fff, gen_helper_fdiv_d)
178TRANS(fmax_s, FP_SP, gen_fff, gen_helper_fmax_s)
179TRANS(fmax_d, FP_DP, gen_fff, gen_helper_fmax_d)
180TRANS(fmin_s, FP_SP, gen_fff, gen_helper_fmin_s)
181TRANS(fmin_d, FP_DP, gen_fff, gen_helper_fmin_d)
182TRANS(fmaxa_s, FP_SP, gen_fff, gen_helper_fmaxa_s)
183TRANS(fmaxa_d, FP_DP, gen_fff, gen_helper_fmaxa_d)
184TRANS(fmina_s, FP_SP, gen_fff, gen_helper_fmina_s)
185TRANS(fmina_d, FP_DP, gen_fff, gen_helper_fmina_d)
186TRANS(fscaleb_s, FP_SP, gen_fff, gen_helper_fscaleb_s)
187TRANS(fscaleb_d, FP_DP, gen_fff, gen_helper_fscaleb_d)
188TRANS(fsqrt_s, FP_SP, gen_ff, gen_helper_fsqrt_s)
189TRANS(fsqrt_d, FP_DP, gen_ff, gen_helper_fsqrt_d)
190TRANS(frecip_s, FP_SP, gen_ff, gen_helper_frecip_s)
191TRANS(frecip_d, FP_DP, gen_ff, gen_helper_frecip_d)
192TRANS(frsqrt_s, FP_SP, gen_ff, gen_helper_frsqrt_s)
193TRANS(frsqrt_d, FP_DP, gen_ff, gen_helper_frsqrt_d)
194TRANS(flogb_s, FP_SP, gen_ff, gen_helper_flogb_s)
195TRANS(flogb_d, FP_DP, gen_ff, gen_helper_flogb_d)
196TRANS(fclass_s, FP_SP, gen_ff, gen_helper_fclass_s)
197TRANS(fclass_d, FP_DP, gen_ff, gen_helper_fclass_d)
198TRANS(fmadd_s, FP_SP, gen_muladd, gen_helper_fmuladd_s, 0)
199TRANS(fmadd_d, FP_DP, gen_muladd, gen_helper_fmuladd_d, 0)
200TRANS(fmsub_s, FP_SP, gen_muladd, gen_helper_fmuladd_s, float_muladd_negate_c)
201TRANS(fmsub_d, FP_DP, gen_muladd, gen_helper_fmuladd_d, float_muladd_negate_c)
202TRANS(fnmadd_s, FP_SP, gen_muladd, gen_helper_fmuladd_s, float_muladd_negate_result)
203TRANS(fnmadd_d, FP_DP, gen_muladd, gen_helper_fmuladd_d, float_muladd_negate_result)
204TRANS(fnmsub_s, FP_SP, gen_muladd, gen_helper_fmuladd_s,
205      float_muladd_negate_c | float_muladd_negate_result)
206TRANS(fnmsub_d, FP_DP, gen_muladd, gen_helper_fmuladd_d,
207      float_muladd_negate_c | float_muladd_negate_result)
208