xref: /qemu/target/loongarch/tcg/translate.c (revision 7c0dfcf9) 
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * LoongArch emulation for QEMU - main translation routines.
4  *
5  * Copyright (c) 2021 Loongson Technology Corporation Limited
6  */
7 
8 #include "qemu/osdep.h"
9 #include "cpu.h"
10 #include "tcg/tcg-op.h"
11 #include "tcg/tcg-op-gvec.h"
12 #include "exec/translation-block.h"
13 #include "exec/translator.h"
14 #include "exec/helper-proto.h"
15 #include "exec/helper-gen.h"
16 #include "exec/log.h"
17 #include "qemu/qemu-print.h"
18 #include "fpu/softfloat.h"
19 #include "translate.h"
20 #include "internals.h"
21 #include "vec.h"
22 
23 /* Global register indices */
24 TCGv cpu_gpr[32], cpu_pc;
25 static TCGv cpu_lladdr, cpu_llval;
26 
27 #define HELPER_H "helper.h"
28 #include "exec/helper-info.c.inc"
29 #undef  HELPER_H
30 
31 #define DISAS_STOP        DISAS_TARGET_0
32 #define DISAS_EXIT        DISAS_TARGET_1
33 #define DISAS_EXIT_UPDATE DISAS_TARGET_2
34 
35 static inline int vec_full_offset(int regno)
36 {
37     return  offsetof(CPULoongArchState, fpr[regno]);
38 }
39 
40 static inline int vec_reg_offset(int regno, int index, MemOp mop)
41 {
42     const uint8_t size = 1 << mop;
43     int offs = index * size;
44 
45     if (HOST_BIG_ENDIAN && size < 8 ) {
46         offs ^= (8 - size);
47     }
48 
49     return offs + vec_full_offset(regno);
50 }
51 
52 static inline void get_vreg64(TCGv_i64 dest, int regno, int index)
53 {
54     tcg_gen_ld_i64(dest, tcg_env,
55                    offsetof(CPULoongArchState, fpr[regno].vreg.D(index)));
56 }
57 
58 static inline void set_vreg64(TCGv_i64 src, int regno, int index)
59 {
60     tcg_gen_st_i64(src, tcg_env,
61                    offsetof(CPULoongArchState, fpr[regno].vreg.D(index)));
62 }
63 
64 static inline int plus_1(DisasContext *ctx, int x)
65 {
66     return x + 1;
67 }
68 
69 static inline int shl_1(DisasContext *ctx, int x)
70 {
71     return x << 1;
72 }
73 
74 static inline int shl_2(DisasContext *ctx, int x)
75 {
76     return x << 2;
77 }
78 
79 static inline int shl_3(DisasContext *ctx, int x)
80 {
81     return x << 3;
82 }
83 
84 /*
85  * LoongArch the upper 32 bits are undefined ("can be any value").
86  * QEMU chooses to nanbox, because it is most likely to show guest bugs early.
87  */
88 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in)
89 {
90     tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32));
91 }
92 
93 void generate_exception(DisasContext *ctx, int excp)
94 {
95     tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
96     gen_helper_raise_exception(tcg_env, tcg_constant_i32(excp));
97     ctx->base.is_jmp = DISAS_NORETURN;
98 }
99 
100 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
101 {
102     if (ctx->va32) {
103         dest = (uint32_t) dest;
104     }
105 
106     if (translator_use_goto_tb(&ctx->base, dest)) {
107         tcg_gen_goto_tb(n);
108         tcg_gen_movi_tl(cpu_pc, dest);
109         tcg_gen_exit_tb(ctx->base.tb, n);
110     } else {
111         tcg_gen_movi_tl(cpu_pc, dest);
112         tcg_gen_lookup_and_goto_ptr();
113     }
114 }
115 
116 static void loongarch_tr_init_disas_context(DisasContextBase *dcbase,
117                                             CPUState *cs)
118 {
119     int64_t bound;
120     CPULoongArchState *env = cpu_env(cs);
121     DisasContext *ctx = container_of(dcbase, DisasContext, base);
122 
123     ctx->page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
124     ctx->plv = ctx->base.tb->flags & HW_FLAGS_PLV_MASK;
125     if (ctx->base.tb->flags & HW_FLAGS_CRMD_PG) {
126         ctx->mem_idx = ctx->plv;
127     } else {
128         ctx->mem_idx = MMU_DA_IDX;
129     }
130 
131     /* Bound the number of insns to execute to those left on the page.  */
132     bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
133     ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
134 
135     if (FIELD_EX64(env->cpucfg[2], CPUCFG2, LSX)) {
136         ctx->vl = LSX_LEN;
137     }
138 
139     if (FIELD_EX64(env->cpucfg[2], CPUCFG2, LASX)) {
140         ctx->vl = LASX_LEN;
141     }
142 
143     ctx->la64 = is_la64(env);
144     ctx->va32 = (ctx->base.tb->flags & HW_FLAGS_VA32) != 0;
145 
146     ctx->zero = tcg_constant_tl(0);
147 
148     ctx->cpucfg1 = env->cpucfg[1];
149     ctx->cpucfg2 = env->cpucfg[2];
150 }
151 
152 static void loongarch_tr_tb_start(DisasContextBase *dcbase, CPUState *cs)
153 {
154 }
155 
156 static void loongarch_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
157 {
158     DisasContext *ctx = container_of(dcbase, DisasContext, base);
159 
160     tcg_gen_insn_start(ctx->base.pc_next);
161 }
162 
163 /*
164  * Wrappers for getting reg values.
165  *
166  * The $zero register does not have cpu_gpr[0] allocated -- we supply the
167  * constant zero as a source, and an uninitialized sink as destination.
168  *
169  * Further, we may provide an extension for word operations.
170  */
171 static TCGv gpr_src(DisasContext *ctx, int reg_num, DisasExtend src_ext)
172 {
173     TCGv t;
174 
175     if (reg_num == 0) {
176         return ctx->zero;
177     }
178 
179     switch (src_ext) {
180     case EXT_NONE:
181         return cpu_gpr[reg_num];
182     case EXT_SIGN:
183         t = tcg_temp_new();
184         tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]);
185         return t;
186     case EXT_ZERO:
187         t = tcg_temp_new();
188         tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]);
189         return t;
190     }
191     g_assert_not_reached();
192 }
193 
194 static TCGv gpr_dst(DisasContext *ctx, int reg_num, DisasExtend dst_ext)
195 {
196     if (reg_num == 0 || dst_ext) {
197         return tcg_temp_new();
198     }
199     return cpu_gpr[reg_num];
200 }
201 
202 static void gen_set_gpr(int reg_num, TCGv t, DisasExtend dst_ext)
203 {
204     if (reg_num != 0) {
205         switch (dst_ext) {
206         case EXT_NONE:
207             tcg_gen_mov_tl(cpu_gpr[reg_num], t);
208             break;
209         case EXT_SIGN:
210             tcg_gen_ext32s_tl(cpu_gpr[reg_num], t);
211             break;
212         case EXT_ZERO:
213             tcg_gen_ext32u_tl(cpu_gpr[reg_num], t);
214             break;
215         default:
216             g_assert_not_reached();
217         }
218     }
219 }
220 
221 static TCGv get_fpr(DisasContext *ctx, int reg_num)
222 {
223     TCGv t = tcg_temp_new();
224     tcg_gen_ld_i64(t, tcg_env,
225                    offsetof(CPULoongArchState, fpr[reg_num].vreg.D(0)));
226     return  t;
227 }
228 
229 static void set_fpr(int reg_num, TCGv val)
230 {
231     tcg_gen_st_i64(val, tcg_env,
232                    offsetof(CPULoongArchState, fpr[reg_num].vreg.D(0)));
233 }
234 
235 static TCGv make_address_x(DisasContext *ctx, TCGv base, TCGv addend)
236 {
237     TCGv temp = NULL;
238 
239     if (addend || ctx->va32) {
240         temp = tcg_temp_new();
241     }
242     if (addend) {
243         tcg_gen_add_tl(temp, base, addend);
244         base = temp;
245     }
246     if (ctx->va32) {
247         tcg_gen_ext32u_tl(temp, base);
248         base = temp;
249     }
250     return base;
251 }
252 
253 static TCGv make_address_i(DisasContext *ctx, TCGv base, target_long ofs)
254 {
255     TCGv addend = ofs ? tcg_constant_tl(ofs) : NULL;
256     return make_address_x(ctx, base, addend);
257 }
258 
259 static uint64_t make_address_pc(DisasContext *ctx, uint64_t addr)
260 {
261     if (ctx->va32) {
262         addr = (int32_t)addr;
263     }
264     return addr;
265 }
266 
267 #include "decode-insns.c.inc"
268 #include "insn_trans/trans_arith.c.inc"
269 #include "insn_trans/trans_shift.c.inc"
270 #include "insn_trans/trans_bit.c.inc"
271 #include "insn_trans/trans_memory.c.inc"
272 #include "insn_trans/trans_atomic.c.inc"
273 #include "insn_trans/trans_extra.c.inc"
274 #include "insn_trans/trans_farith.c.inc"
275 #include "insn_trans/trans_fcmp.c.inc"
276 #include "insn_trans/trans_fcnv.c.inc"
277 #include "insn_trans/trans_fmov.c.inc"
278 #include "insn_trans/trans_fmemory.c.inc"
279 #include "insn_trans/trans_branch.c.inc"
280 #include "insn_trans/trans_privileged.c.inc"
281 #include "insn_trans/trans_vec.c.inc"
282 
283 static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
284 {
285     CPULoongArchState *env = cpu_env(cs);
286     DisasContext *ctx = container_of(dcbase, DisasContext, base);
287 
288     ctx->opcode = translator_ldl(env, &ctx->base, ctx->base.pc_next);
289 
290     if (!decode(ctx, ctx->opcode)) {
291         qemu_log_mask(LOG_UNIMP, "Error: unknown opcode. "
292                       TARGET_FMT_lx ": 0x%x\n",
293                       ctx->base.pc_next, ctx->opcode);
294         generate_exception(ctx, EXCCODE_INE);
295     }
296 
297     ctx->base.pc_next += 4;
298 
299     if (ctx->va32) {
300         ctx->base.pc_next = (uint32_t)ctx->base.pc_next;
301     }
302 }
303 
304 static void loongarch_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
305 {
306     DisasContext *ctx = container_of(dcbase, DisasContext, base);
307 
308     switch (ctx->base.is_jmp) {
309     case DISAS_STOP:
310         tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
311         tcg_gen_lookup_and_goto_ptr();
312         break;
313     case DISAS_TOO_MANY:
314         gen_goto_tb(ctx, 0, ctx->base.pc_next);
315         break;
316     case DISAS_NORETURN:
317         break;
318     case DISAS_EXIT_UPDATE:
319         tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
320         QEMU_FALLTHROUGH;
321     case DISAS_EXIT:
322         tcg_gen_exit_tb(NULL, 0);
323         break;
324     default:
325         g_assert_not_reached();
326     }
327 }
328 
329 static void loongarch_tr_disas_log(const DisasContextBase *dcbase,
330                                    CPUState *cpu, FILE *logfile)
331 {
332     qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
333     target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size);
334 }
335 
336 static const TranslatorOps loongarch_tr_ops = {
337     .init_disas_context = loongarch_tr_init_disas_context,
338     .tb_start           = loongarch_tr_tb_start,
339     .insn_start         = loongarch_tr_insn_start,
340     .translate_insn     = loongarch_tr_translate_insn,
341     .tb_stop            = loongarch_tr_tb_stop,
342     .disas_log          = loongarch_tr_disas_log,
343 };
344 
345 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
346                            vaddr pc, void *host_pc)
347 {
348     DisasContext ctx;
349 
350     translator_loop(cs, tb, max_insns, pc, host_pc,
351                     &loongarch_tr_ops, &ctx.base);
352 }
353 
354 void loongarch_translate_init(void)
355 {
356     int i;
357 
358     cpu_gpr[0] = NULL;
359     for (i = 1; i < 32; i++) {
360         cpu_gpr[i] = tcg_global_mem_new(tcg_env,
361                                         offsetof(CPULoongArchState, gpr[i]),
362                                         regnames[i]);
363     }
364 
365     cpu_pc = tcg_global_mem_new(tcg_env, offsetof(CPULoongArchState, pc), "pc");
366     cpu_lladdr = tcg_global_mem_new(tcg_env,
367                     offsetof(CPULoongArchState, lladdr), "lladdr");
368     cpu_llval = tcg_global_mem_new(tcg_env,
369                     offsetof(CPULoongArchState, llval), "llval");
370 }
371